1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 44cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 54cbb8e50SLuciano Coelho * Copyright(c) 2016 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/etherdevice.h> 326eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 33e705c121SKalle Valo #include <linux/slab.h> 34e705c121SKalle Valo #include <linux/sched.h> 356eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 366eb5e529SEmmanuel Grumbach #include <net/tso.h> 37e705c121SKalle Valo 38e705c121SKalle Valo #include "iwl-debug.h" 39e705c121SKalle Valo #include "iwl-csr.h" 40e705c121SKalle Valo #include "iwl-prph.h" 41e705c121SKalle Valo #include "iwl-io.h" 42e705c121SKalle Valo #include "iwl-scd.h" 43e705c121SKalle Valo #include "iwl-op-mode.h" 44e705c121SKalle Valo #include "internal.h" 45e705c121SKalle Valo /* FIXME: need to abstract out TX command (once we know what it looks like) */ 46e705c121SKalle Valo #include "dvm/commands.h" 47e705c121SKalle Valo 48e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 49e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 50e705c121SKalle Valo 51e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 52e705c121SKalle Valo * DMA services 53e705c121SKalle Valo * 54e705c121SKalle Valo * Theory of operation 55e705c121SKalle Valo * 56e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 57e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 58e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 59e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 60e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 61e705c121SKalle Valo * queue states. 62e705c121SKalle Valo * 63e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 64e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 65e705c121SKalle Valo * 66e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 67e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 68e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 69e705c121SKalle Valo * Tx queue resumed. 70e705c121SKalle Valo * 71e705c121SKalle Valo ***************************************************/ 72e705c121SKalle Valo static int iwl_queue_space(const struct iwl_queue *q) 73e705c121SKalle Valo { 74e705c121SKalle Valo unsigned int max; 75e705c121SKalle Valo unsigned int used; 76e705c121SKalle Valo 77e705c121SKalle Valo /* 78e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 79e705c121SKalle Valo * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 80e705c121SKalle Valo * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 81e705c121SKalle Valo * to reserve any queue entries for this purpose. 82e705c121SKalle Valo */ 83e705c121SKalle Valo if (q->n_window < TFD_QUEUE_SIZE_MAX) 84e705c121SKalle Valo max = q->n_window; 85e705c121SKalle Valo else 86e705c121SKalle Valo max = TFD_QUEUE_SIZE_MAX - 1; 87e705c121SKalle Valo 88e705c121SKalle Valo /* 89e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 90e705c121SKalle Valo * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 91e705c121SKalle Valo */ 92e705c121SKalle Valo used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 93e705c121SKalle Valo 94e705c121SKalle Valo if (WARN_ON(used > max)) 95e705c121SKalle Valo return 0; 96e705c121SKalle Valo 97e705c121SKalle Valo return max - used; 98e705c121SKalle Valo } 99e705c121SKalle Valo 100e705c121SKalle Valo /* 101e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 102e705c121SKalle Valo */ 103e705c121SKalle Valo static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) 104e705c121SKalle Valo { 105e705c121SKalle Valo q->n_window = slots_num; 106e705c121SKalle Valo q->id = id; 107e705c121SKalle Valo 108e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 109e705c121SKalle Valo * get_cmd_index is broken. */ 110e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 111e705c121SKalle Valo return -EINVAL; 112e705c121SKalle Valo 113e705c121SKalle Valo q->low_mark = q->n_window / 4; 114e705c121SKalle Valo if (q->low_mark < 4) 115e705c121SKalle Valo q->low_mark = 4; 116e705c121SKalle Valo 117e705c121SKalle Valo q->high_mark = q->n_window / 8; 118e705c121SKalle Valo if (q->high_mark < 2) 119e705c121SKalle Valo q->high_mark = 2; 120e705c121SKalle Valo 121e705c121SKalle Valo q->write_ptr = 0; 122e705c121SKalle Valo q->read_ptr = 0; 123e705c121SKalle Valo 124e705c121SKalle Valo return 0; 125e705c121SKalle Valo } 126e705c121SKalle Valo 127e705c121SKalle Valo static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 128e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 129e705c121SKalle Valo { 130e705c121SKalle Valo if (WARN_ON(ptr->addr)) 131e705c121SKalle Valo return -EINVAL; 132e705c121SKalle Valo 133e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 134e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 135e705c121SKalle Valo if (!ptr->addr) 136e705c121SKalle Valo return -ENOMEM; 137e705c121SKalle Valo ptr->size = size; 138e705c121SKalle Valo return 0; 139e705c121SKalle Valo } 140e705c121SKalle Valo 141e705c121SKalle Valo static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, 142e705c121SKalle Valo struct iwl_dma_ptr *ptr) 143e705c121SKalle Valo { 144e705c121SKalle Valo if (unlikely(!ptr->addr)) 145e705c121SKalle Valo return; 146e705c121SKalle Valo 147e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 148e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 149e705c121SKalle Valo } 150e705c121SKalle Valo 151e705c121SKalle Valo static void iwl_pcie_txq_stuck_timer(unsigned long data) 152e705c121SKalle Valo { 153e705c121SKalle Valo struct iwl_txq *txq = (void *)data; 154e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 155e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 156e705c121SKalle Valo u32 scd_sram_addr = trans_pcie->scd_base_addr + 157e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 158e705c121SKalle Valo u8 buf[16]; 159e705c121SKalle Valo int i; 160e705c121SKalle Valo 161e705c121SKalle Valo spin_lock(&txq->lock); 162e705c121SKalle Valo /* check if triggered erroneously */ 163e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) { 164e705c121SKalle Valo spin_unlock(&txq->lock); 165e705c121SKalle Valo return; 166e705c121SKalle Valo } 167e705c121SKalle Valo spin_unlock(&txq->lock); 168e705c121SKalle Valo 169e705c121SKalle Valo IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, 170e705c121SKalle Valo jiffies_to_msecs(txq->wd_timeout)); 171e705c121SKalle Valo IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 172e705c121SKalle Valo txq->q.read_ptr, txq->q.write_ptr); 173e705c121SKalle Valo 174e705c121SKalle Valo iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 175e705c121SKalle Valo 176e705c121SKalle Valo iwl_print_hex_error(trans, buf, sizeof(buf)); 177e705c121SKalle Valo 178e705c121SKalle Valo for (i = 0; i < FH_TCSR_CHNL_NUM; i++) 179e705c121SKalle Valo IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, 180e705c121SKalle Valo iwl_read_direct32(trans, FH_TX_TRB_REG(i))); 181e705c121SKalle Valo 182e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 183e705c121SKalle Valo u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); 184e705c121SKalle Valo u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 185e705c121SKalle Valo bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 186e705c121SKalle Valo u32 tbl_dw = 187e705c121SKalle Valo iwl_trans_read_mem32(trans, 188e705c121SKalle Valo trans_pcie->scd_base_addr + 189e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(i)); 190e705c121SKalle Valo 191e705c121SKalle Valo if (i & 0x1) 192e705c121SKalle Valo tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 193e705c121SKalle Valo else 194e705c121SKalle Valo tbl_dw = tbl_dw & 0x0000FFFF; 195e705c121SKalle Valo 196e705c121SKalle Valo IWL_ERR(trans, 197e705c121SKalle Valo "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 198e705c121SKalle Valo i, active ? "" : "in", fifo, tbl_dw, 199e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) & 200e705c121SKalle Valo (TFD_QUEUE_SIZE_MAX - 1), 201e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); 202e705c121SKalle Valo } 203e705c121SKalle Valo 204e705c121SKalle Valo iwl_force_nmi(trans); 205e705c121SKalle Valo } 206e705c121SKalle Valo 207e705c121SKalle Valo /* 208e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 209e705c121SKalle Valo */ 210e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 211e705c121SKalle Valo struct iwl_txq *txq, u16 byte_cnt) 212e705c121SKalle Valo { 213e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 214e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 215e705c121SKalle Valo int write_ptr = txq->q.write_ptr; 216e705c121SKalle Valo int txq_id = txq->q.id; 217e705c121SKalle Valo u8 sec_ctl = 0; 218e705c121SKalle Valo u8 sta_id = 0; 219e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 220e705c121SKalle Valo __le16 bc_ent; 221e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 222e705c121SKalle Valo (void *) txq->entries[txq->q.write_ptr].cmd->payload; 223e705c121SKalle Valo 224e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 225e705c121SKalle Valo 226e705c121SKalle Valo sta_id = tx_cmd->sta_id; 227e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 228e705c121SKalle Valo 229e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 230e705c121SKalle Valo case TX_CMD_SEC_CCM: 231e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 232e705c121SKalle Valo break; 233e705c121SKalle Valo case TX_CMD_SEC_TKIP: 234e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 235e705c121SKalle Valo break; 236e705c121SKalle Valo case TX_CMD_SEC_WEP: 237e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 238e705c121SKalle Valo break; 239e705c121SKalle Valo } 240e705c121SKalle Valo 241e705c121SKalle Valo if (trans_pcie->bc_table_dword) 242e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 243e705c121SKalle Valo 244e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 245e705c121SKalle Valo return; 246e705c121SKalle Valo 247e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 248e705c121SKalle Valo 249e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 250e705c121SKalle Valo 251e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 252e705c121SKalle Valo scd_bc_tbl[txq_id]. 253e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 254e705c121SKalle Valo } 255e705c121SKalle Valo 256e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 257e705c121SKalle Valo struct iwl_txq *txq) 258e705c121SKalle Valo { 259e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 260e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 261e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 262e705c121SKalle Valo int txq_id = txq->q.id; 263e705c121SKalle Valo int read_ptr = txq->q.read_ptr; 264e705c121SKalle Valo u8 sta_id = 0; 265e705c121SKalle Valo __le16 bc_ent; 266e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 267e705c121SKalle Valo (void *)txq->entries[txq->q.read_ptr].cmd->payload; 268e705c121SKalle Valo 269e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 270e705c121SKalle Valo 271e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 272e705c121SKalle Valo sta_id = tx_cmd->sta_id; 273e705c121SKalle Valo 274e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 275e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 276e705c121SKalle Valo 277e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 278e705c121SKalle Valo scd_bc_tbl[txq_id]. 279e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 280e705c121SKalle Valo } 281e705c121SKalle Valo 282e705c121SKalle Valo /* 283e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 284e705c121SKalle Valo */ 285e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 286e705c121SKalle Valo struct iwl_txq *txq) 287e705c121SKalle Valo { 288e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 289e705c121SKalle Valo u32 reg = 0; 290e705c121SKalle Valo int txq_id = txq->q.id; 291e705c121SKalle Valo 292e705c121SKalle Valo lockdep_assert_held(&txq->lock); 293e705c121SKalle Valo 294e705c121SKalle Valo /* 295e705c121SKalle Valo * explicitly wake up the NIC if: 296e705c121SKalle Valo * 1. shadow registers aren't enabled 297e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 298e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 299e705c121SKalle Valo */ 300e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 301e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 302e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 303e705c121SKalle Valo /* 304e705c121SKalle Valo * wake up nic if it's powered down ... 305e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 306e705c121SKalle Valo * time we'll skip this part. 307e705c121SKalle Valo */ 308e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 309e705c121SKalle Valo 310e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 311e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 312e705c121SKalle Valo txq_id, reg); 313e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 314e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 315e705c121SKalle Valo txq->need_update = true; 316e705c121SKalle Valo return; 317e705c121SKalle Valo } 318e705c121SKalle Valo } 319e705c121SKalle Valo 320e705c121SKalle Valo /* 321e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 322e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 323e705c121SKalle Valo */ 324e705c121SKalle Valo IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); 3250cd58eaaSEmmanuel Grumbach if (!txq->block) 3260cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 3270cd58eaaSEmmanuel Grumbach txq->q.write_ptr | (txq_id << 8)); 328e705c121SKalle Valo } 329e705c121SKalle Valo 330e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 331e705c121SKalle Valo { 332e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 333e705c121SKalle Valo int i; 334e705c121SKalle Valo 335e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 336e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[i]; 337e705c121SKalle Valo 338e705c121SKalle Valo spin_lock_bh(&txq->lock); 339e705c121SKalle Valo if (trans_pcie->txq[i].need_update) { 340e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 341e705c121SKalle Valo trans_pcie->txq[i].need_update = false; 342e705c121SKalle Valo } 343e705c121SKalle Valo spin_unlock_bh(&txq->lock); 344e705c121SKalle Valo } 345e705c121SKalle Valo } 346e705c121SKalle Valo 347e705c121SKalle Valo static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) 348e705c121SKalle Valo { 349e705c121SKalle Valo struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 350e705c121SKalle Valo 351e705c121SKalle Valo dma_addr_t addr = get_unaligned_le32(&tb->lo); 352e705c121SKalle Valo if (sizeof(dma_addr_t) > sizeof(u32)) 353e705c121SKalle Valo addr |= 354e705c121SKalle Valo ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; 355e705c121SKalle Valo 356e705c121SKalle Valo return addr; 357e705c121SKalle Valo } 358e705c121SKalle Valo 359e705c121SKalle Valo static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, 360e705c121SKalle Valo dma_addr_t addr, u16 len) 361e705c121SKalle Valo { 362e705c121SKalle Valo struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 363e705c121SKalle Valo u16 hi_n_len = len << 4; 364e705c121SKalle Valo 365e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 366e705c121SKalle Valo if (sizeof(dma_addr_t) > sizeof(u32)) 367e705c121SKalle Valo hi_n_len |= ((addr >> 16) >> 16) & 0xF; 368e705c121SKalle Valo 369e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 370e705c121SKalle Valo 371e705c121SKalle Valo tfd->num_tbs = idx + 1; 372e705c121SKalle Valo } 373e705c121SKalle Valo 374e705c121SKalle Valo static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) 375e705c121SKalle Valo { 376e705c121SKalle Valo return tfd->num_tbs & 0x1f; 377e705c121SKalle Valo } 378e705c121SKalle Valo 379e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 380e705c121SKalle Valo struct iwl_cmd_meta *meta, 381e705c121SKalle Valo struct iwl_tfd *tfd) 382e705c121SKalle Valo { 383e705c121SKalle Valo int i; 384e705c121SKalle Valo int num_tbs; 385e705c121SKalle Valo 386e705c121SKalle Valo /* Sanity check on number of chunks */ 387e705c121SKalle Valo num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 388e705c121SKalle Valo 389e705c121SKalle Valo if (num_tbs >= IWL_NUM_OF_TBS) { 390e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 391e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 392e705c121SKalle Valo return; 393e705c121SKalle Valo } 394e705c121SKalle Valo 395e705c121SKalle Valo /* first TB is never freed - it's the scratchbuf data */ 396e705c121SKalle Valo 397e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 398e705c121SKalle Valo if (meta->flags & BIT(i + CMD_TB_BITMAP_POS)) 399e705c121SKalle Valo dma_unmap_page(trans->dev, 400e705c121SKalle Valo iwl_pcie_tfd_tb_get_addr(tfd, i), 401e705c121SKalle Valo iwl_pcie_tfd_tb_get_len(tfd, i), 402e705c121SKalle Valo DMA_TO_DEVICE); 403e705c121SKalle Valo else 404e705c121SKalle Valo dma_unmap_single(trans->dev, 405e705c121SKalle Valo iwl_pcie_tfd_tb_get_addr(tfd, i), 406e705c121SKalle Valo iwl_pcie_tfd_tb_get_len(tfd, i), 407e705c121SKalle Valo DMA_TO_DEVICE); 408e705c121SKalle Valo } 409e705c121SKalle Valo tfd->num_tbs = 0; 410e705c121SKalle Valo } 411e705c121SKalle Valo 412e705c121SKalle Valo /* 413e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 414e705c121SKalle Valo * @trans - transport private data 415e705c121SKalle Valo * @txq - tx queue 416e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 417e705c121SKalle Valo * 418e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 419e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 420e705c121SKalle Valo */ 421e705c121SKalle Valo static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 422e705c121SKalle Valo { 423e705c121SKalle Valo struct iwl_tfd *tfd_tmp = txq->tfds; 424e705c121SKalle Valo 425e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 426e705c121SKalle Valo * idx is bounded by n_window 427e705c121SKalle Valo */ 428e705c121SKalle Valo int rd_ptr = txq->q.read_ptr; 429e705c121SKalle Valo int idx = get_cmd_index(&txq->q, rd_ptr); 430e705c121SKalle Valo 431e705c121SKalle Valo lockdep_assert_held(&txq->lock); 432e705c121SKalle Valo 433e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 434e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 435e705c121SKalle Valo */ 436e705c121SKalle Valo iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); 437e705c121SKalle Valo 438e705c121SKalle Valo /* free SKB */ 439e705c121SKalle Valo if (txq->entries) { 440e705c121SKalle Valo struct sk_buff *skb; 441e705c121SKalle Valo 442e705c121SKalle Valo skb = txq->entries[idx].skb; 443e705c121SKalle Valo 444e705c121SKalle Valo /* Can be called from irqs-disabled context 445e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 446e705c121SKalle Valo * freed and that the queue is not empty - free the skb 447e705c121SKalle Valo */ 448e705c121SKalle Valo if (skb) { 449e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 450e705c121SKalle Valo txq->entries[idx].skb = NULL; 451e705c121SKalle Valo } 452e705c121SKalle Valo } 453e705c121SKalle Valo } 454e705c121SKalle Valo 455e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 456e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 457e705c121SKalle Valo { 458e705c121SKalle Valo struct iwl_queue *q; 459e705c121SKalle Valo struct iwl_tfd *tfd, *tfd_tmp; 460e705c121SKalle Valo u32 num_tbs; 461e705c121SKalle Valo 462e705c121SKalle Valo q = &txq->q; 463e705c121SKalle Valo tfd_tmp = txq->tfds; 464e705c121SKalle Valo tfd = &tfd_tmp[q->write_ptr]; 465e705c121SKalle Valo 466e705c121SKalle Valo if (reset) 467e705c121SKalle Valo memset(tfd, 0, sizeof(*tfd)); 468e705c121SKalle Valo 469e705c121SKalle Valo num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); 470e705c121SKalle Valo 471e705c121SKalle Valo /* Each TFD can point to a maximum 20 Tx buffers */ 472e705c121SKalle Valo if (num_tbs >= IWL_NUM_OF_TBS) { 473e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 474e705c121SKalle Valo IWL_NUM_OF_TBS); 475e705c121SKalle Valo return -EINVAL; 476e705c121SKalle Valo } 477e705c121SKalle Valo 478e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 479e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 480e705c121SKalle Valo return -EINVAL; 481e705c121SKalle Valo 482e705c121SKalle Valo iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); 483e705c121SKalle Valo 484e705c121SKalle Valo return num_tbs; 485e705c121SKalle Valo } 486e705c121SKalle Valo 487e705c121SKalle Valo static int iwl_pcie_txq_alloc(struct iwl_trans *trans, 488e705c121SKalle Valo struct iwl_txq *txq, int slots_num, 489e705c121SKalle Valo u32 txq_id) 490e705c121SKalle Valo { 491e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 492e705c121SKalle Valo size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; 493e705c121SKalle Valo size_t scratchbuf_sz; 494e705c121SKalle Valo int i; 495e705c121SKalle Valo 496e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 497e705c121SKalle Valo return -EINVAL; 498e705c121SKalle Valo 499e705c121SKalle Valo setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 500e705c121SKalle Valo (unsigned long)txq); 501e705c121SKalle Valo txq->trans_pcie = trans_pcie; 502e705c121SKalle Valo 503e705c121SKalle Valo txq->q.n_window = slots_num; 504e705c121SKalle Valo 505e705c121SKalle Valo txq->entries = kcalloc(slots_num, 506e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 507e705c121SKalle Valo GFP_KERNEL); 508e705c121SKalle Valo 509e705c121SKalle Valo if (!txq->entries) 510e705c121SKalle Valo goto error; 511e705c121SKalle Valo 512e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 513e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 514e705c121SKalle Valo txq->entries[i].cmd = 515e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 516e705c121SKalle Valo GFP_KERNEL); 517e705c121SKalle Valo if (!txq->entries[i].cmd) 518e705c121SKalle Valo goto error; 519e705c121SKalle Valo } 520e705c121SKalle Valo 521e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 522e705c121SKalle Valo * shared with device */ 523e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 524e705c121SKalle Valo &txq->q.dma_addr, GFP_KERNEL); 525e705c121SKalle Valo if (!txq->tfds) 526e705c121SKalle Valo goto error; 527e705c121SKalle Valo 528e705c121SKalle Valo BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); 529e705c121SKalle Valo BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != 530e705c121SKalle Valo sizeof(struct iwl_cmd_header) + 531e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch)); 532e705c121SKalle Valo 533e705c121SKalle Valo scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; 534e705c121SKalle Valo 535e705c121SKalle Valo txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, 536e705c121SKalle Valo &txq->scratchbufs_dma, 537e705c121SKalle Valo GFP_KERNEL); 538e705c121SKalle Valo if (!txq->scratchbufs) 539e705c121SKalle Valo goto err_free_tfds; 540e705c121SKalle Valo 541e705c121SKalle Valo txq->q.id = txq_id; 542e705c121SKalle Valo 543e705c121SKalle Valo return 0; 544e705c121SKalle Valo err_free_tfds: 545e705c121SKalle Valo dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); 546e705c121SKalle Valo error: 547e705c121SKalle Valo if (txq->entries && txq_id == trans_pcie->cmd_queue) 548e705c121SKalle Valo for (i = 0; i < slots_num; i++) 549e705c121SKalle Valo kfree(txq->entries[i].cmd); 550e705c121SKalle Valo kfree(txq->entries); 551e705c121SKalle Valo txq->entries = NULL; 552e705c121SKalle Valo 553e705c121SKalle Valo return -ENOMEM; 554e705c121SKalle Valo 555e705c121SKalle Valo } 556e705c121SKalle Valo 557e705c121SKalle Valo static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 558e705c121SKalle Valo int slots_num, u32 txq_id) 559e705c121SKalle Valo { 560e705c121SKalle Valo int ret; 561e705c121SKalle Valo 562e705c121SKalle Valo txq->need_update = false; 563e705c121SKalle Valo 564e705c121SKalle Valo /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 565e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 566e705c121SKalle Valo BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 567e705c121SKalle Valo 568e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 569e705c121SKalle Valo ret = iwl_queue_init(&txq->q, slots_num, txq_id); 570e705c121SKalle Valo if (ret) 571e705c121SKalle Valo return ret; 572e705c121SKalle Valo 573e705c121SKalle Valo spin_lock_init(&txq->lock); 5743955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 575e705c121SKalle Valo 576e705c121SKalle Valo /* 577e705c121SKalle Valo * Tell nic where to find circular buffer of Tx Frame Descriptors for 578e705c121SKalle Valo * given Tx queue, and enable the DMA channel used for that queue. 579e705c121SKalle Valo * Circular buffer (TFD queue in DRAM) physical base address */ 580e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), 581e705c121SKalle Valo txq->q.dma_addr >> 8); 582e705c121SKalle Valo 583e705c121SKalle Valo return 0; 584e705c121SKalle Valo } 585e705c121SKalle Valo 5866eb5e529SEmmanuel Grumbach static void iwl_pcie_free_tso_page(struct sk_buff *skb) 5876eb5e529SEmmanuel Grumbach { 5886eb5e529SEmmanuel Grumbach struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5896eb5e529SEmmanuel Grumbach 5906eb5e529SEmmanuel Grumbach if (info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]) { 5916eb5e529SEmmanuel Grumbach struct page *page = 5926eb5e529SEmmanuel Grumbach info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA]; 5936eb5e529SEmmanuel Grumbach 5946eb5e529SEmmanuel Grumbach __free_page(page); 5956eb5e529SEmmanuel Grumbach info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = NULL; 5966eb5e529SEmmanuel Grumbach } 5976eb5e529SEmmanuel Grumbach } 5986eb5e529SEmmanuel Grumbach 599e705c121SKalle Valo /* 600e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 601e705c121SKalle Valo */ 602e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 603e705c121SKalle Valo { 604e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 605e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 606e705c121SKalle Valo struct iwl_queue *q = &txq->q; 607e705c121SKalle Valo 608e705c121SKalle Valo spin_lock_bh(&txq->lock); 609e705c121SKalle Valo while (q->write_ptr != q->read_ptr) { 610e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 611e705c121SKalle Valo txq_id, q->read_ptr); 6126eb5e529SEmmanuel Grumbach 6136eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 6146eb5e529SEmmanuel Grumbach struct sk_buff *skb = txq->entries[q->read_ptr].skb; 6156eb5e529SEmmanuel Grumbach 6166eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6176eb5e529SEmmanuel Grumbach continue; 6186eb5e529SEmmanuel Grumbach 6196eb5e529SEmmanuel Grumbach iwl_pcie_free_tso_page(skb); 6206eb5e529SEmmanuel Grumbach } 621e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 622e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); 623e705c121SKalle Valo } 624e705c121SKalle Valo txq->active = false; 6253955525dSEmmanuel Grumbach 6263955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 6273955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 6283955525dSEmmanuel Grumbach 6293955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 6303955525dSEmmanuel Grumbach } 6313955525dSEmmanuel Grumbach 632e705c121SKalle Valo spin_unlock_bh(&txq->lock); 633e705c121SKalle Valo 634e705c121SKalle Valo /* just in case - this queue may have been stopped */ 635e705c121SKalle Valo iwl_wake_queue(trans, txq); 636e705c121SKalle Valo } 637e705c121SKalle Valo 638e705c121SKalle Valo /* 639e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 640e705c121SKalle Valo * @txq: Transmit queue to deallocate. 641e705c121SKalle Valo * 642e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 643e705c121SKalle Valo * Free all buffers. 644e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 645e705c121SKalle Valo */ 646e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 647e705c121SKalle Valo { 648e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 649e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 650e705c121SKalle Valo struct device *dev = trans->dev; 651e705c121SKalle Valo int i; 652e705c121SKalle Valo 653e705c121SKalle Valo if (WARN_ON(!txq)) 654e705c121SKalle Valo return; 655e705c121SKalle Valo 656e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 657e705c121SKalle Valo 658e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 659e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 660e705c121SKalle Valo for (i = 0; i < txq->q.n_window; i++) { 661e705c121SKalle Valo kzfree(txq->entries[i].cmd); 662e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 663e705c121SKalle Valo } 664e705c121SKalle Valo 665e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 666e705c121SKalle Valo if (txq->tfds) { 667e705c121SKalle Valo dma_free_coherent(dev, 668e705c121SKalle Valo sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX, 669e705c121SKalle Valo txq->tfds, txq->q.dma_addr); 670e705c121SKalle Valo txq->q.dma_addr = 0; 671e705c121SKalle Valo txq->tfds = NULL; 672e705c121SKalle Valo 673e705c121SKalle Valo dma_free_coherent(dev, 674e705c121SKalle Valo sizeof(*txq->scratchbufs) * txq->q.n_window, 675e705c121SKalle Valo txq->scratchbufs, txq->scratchbufs_dma); 676e705c121SKalle Valo } 677e705c121SKalle Valo 678e705c121SKalle Valo kfree(txq->entries); 679e705c121SKalle Valo txq->entries = NULL; 680e705c121SKalle Valo 681e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 682e705c121SKalle Valo 683e705c121SKalle Valo /* 0-fill queue descriptor structure */ 684e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 685e705c121SKalle Valo } 686e705c121SKalle Valo 687e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 688e705c121SKalle Valo { 689e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 690e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 691e705c121SKalle Valo int chan; 692e705c121SKalle Valo u32 reg_val; 693e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 694e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 695e705c121SKalle Valo 696e705c121SKalle Valo /* make sure all queue are not stopped/used */ 697e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 698e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 699e705c121SKalle Valo 700e705c121SKalle Valo trans_pcie->scd_base_addr = 701e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 702e705c121SKalle Valo 703e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 704e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 705e705c121SKalle Valo 706e705c121SKalle Valo /* reset context data, TX status and translation data */ 707e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 708e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 709e705c121SKalle Valo NULL, clear_dwords); 710e705c121SKalle Valo 711e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 712e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 713e705c121SKalle Valo 714e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 715e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 716e705c121SKalle Valo */ 717e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 718e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 719e705c121SKalle Valo 720e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 721e705c121SKalle Valo trans_pcie->cmd_fifo, 722e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 723e705c121SKalle Valo 724e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 725e705c121SKalle Valo iwl_scd_activate_fifos(trans); 726e705c121SKalle Valo 727e705c121SKalle Valo /* Enable DMA channel */ 728e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 729e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 730e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 731e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 732e705c121SKalle Valo 733e705c121SKalle Valo /* Update FH chicken bits */ 734e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 735e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 736e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 737e705c121SKalle Valo 738e705c121SKalle Valo /* Enable L1-Active */ 739e705c121SKalle Valo if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 740e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 741e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 742e705c121SKalle Valo } 743e705c121SKalle Valo 744e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 745e705c121SKalle Valo { 746e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 747e705c121SKalle Valo int txq_id; 748e705c121SKalle Valo 749e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 750e705c121SKalle Valo txq_id++) { 751e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 752e705c121SKalle Valo 753e705c121SKalle Valo iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), 754e705c121SKalle Valo txq->q.dma_addr >> 8); 755e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 756e705c121SKalle Valo txq->q.read_ptr = 0; 757e705c121SKalle Valo txq->q.write_ptr = 0; 758e705c121SKalle Valo } 759e705c121SKalle Valo 760e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 761e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 762e705c121SKalle Valo trans_pcie->kw.dma >> 4); 763e705c121SKalle Valo 764e705c121SKalle Valo /* 765e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 766e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 767e705c121SKalle Valo * contain garbage. 768e705c121SKalle Valo */ 769e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 770e705c121SKalle Valo } 771e705c121SKalle Valo 772e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 773e705c121SKalle Valo { 774e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 775e705c121SKalle Valo unsigned long flags; 776e705c121SKalle Valo int ch, ret; 777e705c121SKalle Valo u32 mask = 0; 778e705c121SKalle Valo 779e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 780e705c121SKalle Valo 78123ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 782e705c121SKalle Valo goto out; 783e705c121SKalle Valo 784e705c121SKalle Valo /* Stop each Tx DMA channel */ 785e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 786e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 787e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 788e705c121SKalle Valo } 789e705c121SKalle Valo 790e705c121SKalle Valo /* Wait for DMA channels to be idle */ 791e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 792e705c121SKalle Valo if (ret < 0) 793e705c121SKalle Valo IWL_ERR(trans, 794e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 795e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 796e705c121SKalle Valo 797e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 798e705c121SKalle Valo 799e705c121SKalle Valo out: 800e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 801e705c121SKalle Valo } 802e705c121SKalle Valo 803e705c121SKalle Valo /* 804e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 805e705c121SKalle Valo */ 806e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 807e705c121SKalle Valo { 808e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 809e705c121SKalle Valo int txq_id; 810e705c121SKalle Valo 811e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 812e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 813e705c121SKalle Valo 814e705c121SKalle Valo /* Turn off all Tx DMA channels */ 815e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 816e705c121SKalle Valo 817e705c121SKalle Valo /* 818e705c121SKalle Valo * This function can be called before the op_mode disabled the 819e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 820e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 821e705c121SKalle Valo */ 822e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 823e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 824e705c121SKalle Valo 825e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 826e705c121SKalle Valo if (!trans_pcie->txq) 827e705c121SKalle Valo return 0; 828e705c121SKalle Valo 829e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 830e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 831e705c121SKalle Valo txq_id++) 832e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 833e705c121SKalle Valo 834e705c121SKalle Valo return 0; 835e705c121SKalle Valo } 836e705c121SKalle Valo 837e705c121SKalle Valo /* 838e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 839e705c121SKalle Valo * 840e705c121SKalle Valo * Destroy all TX DMA queues and structures 841e705c121SKalle Valo */ 842e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 843e705c121SKalle Valo { 844e705c121SKalle Valo int txq_id; 845e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 846e705c121SKalle Valo 847e705c121SKalle Valo /* Tx queues */ 848e705c121SKalle Valo if (trans_pcie->txq) { 849e705c121SKalle Valo for (txq_id = 0; 850e705c121SKalle Valo txq_id < trans->cfg->base_params->num_of_queues; txq_id++) 851e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 852e705c121SKalle Valo } 853e705c121SKalle Valo 854e705c121SKalle Valo kfree(trans_pcie->txq); 855e705c121SKalle Valo trans_pcie->txq = NULL; 856e705c121SKalle Valo 857e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 858e705c121SKalle Valo 859e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 860e705c121SKalle Valo } 861e705c121SKalle Valo 862e705c121SKalle Valo /* 863e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 864e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 865e705c121SKalle Valo */ 866e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 867e705c121SKalle Valo { 868e705c121SKalle Valo int ret; 869e705c121SKalle Valo int txq_id, slots_num; 870e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 871e705c121SKalle Valo 872e705c121SKalle Valo u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 873e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 874e705c121SKalle Valo 875e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 876e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 877e705c121SKalle Valo if (WARN_ON(trans_pcie->txq)) { 878e705c121SKalle Valo ret = -EINVAL; 879e705c121SKalle Valo goto error; 880e705c121SKalle Valo } 881e705c121SKalle Valo 882e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 883e705c121SKalle Valo scd_bc_tbls_size); 884e705c121SKalle Valo if (ret) { 885e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 886e705c121SKalle Valo goto error; 887e705c121SKalle Valo } 888e705c121SKalle Valo 889e705c121SKalle Valo /* Alloc keep-warm buffer */ 890e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 891e705c121SKalle Valo if (ret) { 892e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 893e705c121SKalle Valo goto error; 894e705c121SKalle Valo } 895e705c121SKalle Valo 896e705c121SKalle Valo trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, 897e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 898e705c121SKalle Valo if (!trans_pcie->txq) { 899e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 900e705c121SKalle Valo ret = -ENOMEM; 901e705c121SKalle Valo goto error; 902e705c121SKalle Valo } 903e705c121SKalle Valo 904e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 905e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 906e705c121SKalle Valo txq_id++) { 907e705c121SKalle Valo slots_num = (txq_id == trans_pcie->cmd_queue) ? 908e705c121SKalle Valo TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 909e705c121SKalle Valo ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], 910e705c121SKalle Valo slots_num, txq_id); 911e705c121SKalle Valo if (ret) { 912e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 913e705c121SKalle Valo goto error; 914e705c121SKalle Valo } 915e705c121SKalle Valo } 916e705c121SKalle Valo 917e705c121SKalle Valo return 0; 918e705c121SKalle Valo 919e705c121SKalle Valo error: 920e705c121SKalle Valo iwl_pcie_tx_free(trans); 921e705c121SKalle Valo 922e705c121SKalle Valo return ret; 923e705c121SKalle Valo } 924e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 925e705c121SKalle Valo { 926e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 927e705c121SKalle Valo int ret; 928e705c121SKalle Valo int txq_id, slots_num; 929e705c121SKalle Valo bool alloc = false; 930e705c121SKalle Valo 931e705c121SKalle Valo if (!trans_pcie->txq) { 932e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 933e705c121SKalle Valo if (ret) 934e705c121SKalle Valo goto error; 935e705c121SKalle Valo alloc = true; 936e705c121SKalle Valo } 937e705c121SKalle Valo 938e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 939e705c121SKalle Valo 940e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 941e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 942e705c121SKalle Valo 943e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 944e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 945e705c121SKalle Valo trans_pcie->kw.dma >> 4); 946e705c121SKalle Valo 947e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 948e705c121SKalle Valo 949e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 950e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 951e705c121SKalle Valo txq_id++) { 952e705c121SKalle Valo slots_num = (txq_id == trans_pcie->cmd_queue) ? 953e705c121SKalle Valo TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 954e705c121SKalle Valo ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], 955e705c121SKalle Valo slots_num, txq_id); 956e705c121SKalle Valo if (ret) { 957e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 958e705c121SKalle Valo goto error; 959e705c121SKalle Valo } 960e705c121SKalle Valo } 961e705c121SKalle Valo 962e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 963e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 964e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 965e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 966e705c121SKalle Valo 967e705c121SKalle Valo return 0; 968e705c121SKalle Valo error: 969e705c121SKalle Valo /*Upon error, free only if we allocated something */ 970e705c121SKalle Valo if (alloc) 971e705c121SKalle Valo iwl_pcie_tx_free(trans); 972e705c121SKalle Valo return ret; 973e705c121SKalle Valo } 974e705c121SKalle Valo 975e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 976e705c121SKalle Valo { 977e705c121SKalle Valo lockdep_assert_held(&txq->lock); 978e705c121SKalle Valo 979e705c121SKalle Valo if (!txq->wd_timeout) 980e705c121SKalle Valo return; 981e705c121SKalle Valo 982e705c121SKalle Valo /* 983e705c121SKalle Valo * station is asleep and we send data - that must 984e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 985e705c121SKalle Valo */ 986e705c121SKalle Valo if (txq->frozen) 987e705c121SKalle Valo return; 988e705c121SKalle Valo 989e705c121SKalle Valo /* 990e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 991e705c121SKalle Valo * since we're making progress on this queue 992e705c121SKalle Valo */ 993e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) 994e705c121SKalle Valo del_timer(&txq->stuck_timer); 995e705c121SKalle Valo else 996e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 997e705c121SKalle Valo } 998e705c121SKalle Valo 999e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1000e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1001e705c121SKalle Valo struct sk_buff_head *skbs) 1002e705c121SKalle Valo { 1003e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1004e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1005e705c121SKalle Valo int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 1006e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1007e705c121SKalle Valo int last_to_free; 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1010e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1011e705c121SKalle Valo return; 1012e705c121SKalle Valo 1013e705c121SKalle Valo spin_lock_bh(&txq->lock); 1014e705c121SKalle Valo 1015e705c121SKalle Valo if (!txq->active) { 1016e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1017e705c121SKalle Valo txq_id, ssn); 1018e705c121SKalle Valo goto out; 1019e705c121SKalle Valo } 1020e705c121SKalle Valo 1021e705c121SKalle Valo if (txq->q.read_ptr == tfd_num) 1022e705c121SKalle Valo goto out; 1023e705c121SKalle Valo 1024e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1025e705c121SKalle Valo txq_id, txq->q.read_ptr, tfd_num, ssn); 1026e705c121SKalle Valo 1027e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1028e705c121SKalle Valo * the last we will free. This one must be used */ 1029e705c121SKalle Valo last_to_free = iwl_queue_dec_wrap(tfd_num); 1030e705c121SKalle Valo 1031e705c121SKalle Valo if (!iwl_queue_used(q, last_to_free)) { 1032e705c121SKalle Valo IWL_ERR(trans, 1033e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1034e705c121SKalle Valo __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 1035e705c121SKalle Valo q->write_ptr, q->read_ptr); 1036e705c121SKalle Valo goto out; 1037e705c121SKalle Valo } 1038e705c121SKalle Valo 1039e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1040e705c121SKalle Valo goto out; 1041e705c121SKalle Valo 1042e705c121SKalle Valo for (; 1043e705c121SKalle Valo q->read_ptr != tfd_num; 1044e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 10456eb5e529SEmmanuel Grumbach struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb; 1046e705c121SKalle Valo 10476eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1048e705c121SKalle Valo continue; 1049e705c121SKalle Valo 10506eb5e529SEmmanuel Grumbach iwl_pcie_free_tso_page(skb); 10516eb5e529SEmmanuel Grumbach 10526eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1053e705c121SKalle Valo 1054e705c121SKalle Valo txq->entries[txq->q.read_ptr].skb = NULL; 1055e705c121SKalle Valo 1056e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1057e705c121SKalle Valo 1058e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1059e705c121SKalle Valo } 1060e705c121SKalle Valo 1061e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1062e705c121SKalle Valo 10633955525dSEmmanuel Grumbach if (iwl_queue_space(&txq->q) > txq->q.low_mark && 10643955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1065685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 10663955525dSEmmanuel Grumbach 1067685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1068685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 10693955525dSEmmanuel Grumbach 10703955525dSEmmanuel Grumbach /* 10713955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 10723955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 10733955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 10743955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 10753955525dSEmmanuel Grumbach * later. 10763955525dSEmmanuel Grumbach */ 10773955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 10783955525dSEmmanuel Grumbach 1079685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1080685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 10813955525dSEmmanuel Grumbach struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 10823955525dSEmmanuel Grumbach u8 dev_cmd_idx = IWL_TRANS_FIRST_DRIVER_DATA + 1; 10833955525dSEmmanuel Grumbach struct iwl_device_cmd *dev_cmd = 10843955525dSEmmanuel Grumbach info->driver_data[dev_cmd_idx]; 10853955525dSEmmanuel Grumbach 10863955525dSEmmanuel Grumbach /* 10873955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 10883955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 10893955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 10903955525dSEmmanuel Grumbach */ 10913955525dSEmmanuel Grumbach iwl_trans_pcie_tx(trans, skb, dev_cmd, txq_id); 10923955525dSEmmanuel Grumbach } 10933955525dSEmmanuel Grumbach spin_lock_bh(&txq->lock); 10943955525dSEmmanuel Grumbach 1095e705c121SKalle Valo if (iwl_queue_space(&txq->q) > txq->q.low_mark) 1096e705c121SKalle Valo iwl_wake_queue(trans, txq); 10973955525dSEmmanuel Grumbach } 1098e705c121SKalle Valo 1099e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 1100e705c121SKalle Valo IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); 1101e705c121SKalle Valo iwl_trans_pcie_unref(trans); 1102e705c121SKalle Valo } 1103e705c121SKalle Valo 1104e705c121SKalle Valo out: 1105e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1106e705c121SKalle Valo } 1107e705c121SKalle Valo 1108e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1109e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1110e705c121SKalle Valo { 1111e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1112e705c121SKalle Valo int ret; 1113e705c121SKalle Valo 1114e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1115e705c121SKalle Valo 1116e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1117e705c121SKalle Valo !trans_pcie->ref_cmd_in_flight) { 1118e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = true; 1119e705c121SKalle Valo IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1120e705c121SKalle Valo iwl_trans_pcie_ref(trans); 1121e705c121SKalle Valo } 1122e705c121SKalle Valo 1123e705c121SKalle Valo /* 1124e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1125e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1126e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1127e705c121SKalle Valo * apmg_wake_up_wa set. 1128e705c121SKalle Valo */ 1129e705c121SKalle Valo if (trans->cfg->base_params->apmg_wake_up_wa && 1130e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1131e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1132e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1133e705c121SKalle Valo 1134e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1135e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1136e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1137e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1138e705c121SKalle Valo 15000); 1139e705c121SKalle Valo if (ret < 0) { 1140e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1141e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1142e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1143e705c121SKalle Valo return -EIO; 1144e705c121SKalle Valo } 1145e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1146e705c121SKalle Valo } 1147e705c121SKalle Valo 1148e705c121SKalle Valo return 0; 1149e705c121SKalle Valo } 1150e705c121SKalle Valo 1151e705c121SKalle Valo static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 1152e705c121SKalle Valo { 1153e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1154e705c121SKalle Valo 1155e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1156e705c121SKalle Valo 1157e705c121SKalle Valo if (trans_pcie->ref_cmd_in_flight) { 1158e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = false; 1159e705c121SKalle Valo IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 1160e705c121SKalle Valo iwl_trans_pcie_unref(trans); 1161e705c121SKalle Valo } 1162e705c121SKalle Valo 1163e705c121SKalle Valo if (trans->cfg->base_params->apmg_wake_up_wa) { 1164e705c121SKalle Valo if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 1165e705c121SKalle Valo return 0; 1166e705c121SKalle Valo 1167e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = false; 1168e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1169e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1170e705c121SKalle Valo } 1171e705c121SKalle Valo return 0; 1172e705c121SKalle Valo } 1173e705c121SKalle Valo 1174e705c121SKalle Valo /* 1175e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1176e705c121SKalle Valo * 1177e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1178e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1179e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1180e705c121SKalle Valo */ 1181e705c121SKalle Valo static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1182e705c121SKalle Valo { 1183e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1184e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1185e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1186e705c121SKalle Valo unsigned long flags; 1187e705c121SKalle Valo int nfreed = 0; 1188e705c121SKalle Valo 1189e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1190e705c121SKalle Valo 1191e705c121SKalle Valo if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { 1192e705c121SKalle Valo IWL_ERR(trans, 1193e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1194e705c121SKalle Valo __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1195e705c121SKalle Valo q->write_ptr, q->read_ptr); 1196e705c121SKalle Valo return; 1197e705c121SKalle Valo } 1198e705c121SKalle Valo 1199e705c121SKalle Valo for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; 1200e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 1201e705c121SKalle Valo 1202e705c121SKalle Valo if (nfreed++ > 0) { 1203e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1204e705c121SKalle Valo idx, q->write_ptr, q->read_ptr); 1205e705c121SKalle Valo iwl_force_nmi(trans); 1206e705c121SKalle Valo } 1207e705c121SKalle Valo } 1208e705c121SKalle Valo 1209e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 1210e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1211e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1212e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1213e705c121SKalle Valo } 1214e705c121SKalle Valo 1215e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1216e705c121SKalle Valo } 1217e705c121SKalle Valo 1218e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1219e705c121SKalle Valo u16 txq_id) 1220e705c121SKalle Valo { 1221e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1222e705c121SKalle Valo u32 tbl_dw_addr; 1223e705c121SKalle Valo u32 tbl_dw; 1224e705c121SKalle Valo u16 scd_q2ratid; 1225e705c121SKalle Valo 1226e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1227e705c121SKalle Valo 1228e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1229e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1230e705c121SKalle Valo 1231e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1232e705c121SKalle Valo 1233e705c121SKalle Valo if (txq_id & 0x1) 1234e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1235e705c121SKalle Valo else 1236e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1237e705c121SKalle Valo 1238e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1239e705c121SKalle Valo 1240e705c121SKalle Valo return 0; 1241e705c121SKalle Valo } 1242e705c121SKalle Valo 1243e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1244e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1245e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1246e705c121SKalle Valo 1247e705c121SKalle Valo void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1248e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1249e705c121SKalle Valo unsigned int wdg_timeout) 1250e705c121SKalle Valo { 1251e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1252e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1253e705c121SKalle Valo int fifo = -1; 1254e705c121SKalle Valo 1255e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1256e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1257e705c121SKalle Valo 1258e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1259e705c121SKalle Valo 1260e705c121SKalle Valo if (cfg) { 1261e705c121SKalle Valo fifo = cfg->fifo; 1262e705c121SKalle Valo 1263e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1264e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1265e705c121SKalle Valo trans_pcie->scd_set_active) 1266e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1267e705c121SKalle Valo 1268e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1269e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1270e705c121SKalle Valo 1271e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1272e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1273e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1274e705c121SKalle Valo 1275e705c121SKalle Valo if (cfg->aggregate) { 1276e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1277e705c121SKalle Valo 1278e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1279e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1280e705c121SKalle Valo 1281e705c121SKalle Valo /* enable aggregations for the queue */ 1282e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1283e705c121SKalle Valo txq->ampdu = true; 1284e705c121SKalle Valo } else { 1285e705c121SKalle Valo /* 1286e705c121SKalle Valo * disable aggregations for the queue, this will also 1287e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1288e705c121SKalle Valo * since it is now a non-AGG queue. 1289e705c121SKalle Valo */ 1290e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1291e705c121SKalle Valo 1292e705c121SKalle Valo ssn = txq->q.read_ptr; 1293e705c121SKalle Valo } 1294e705c121SKalle Valo } 1295e705c121SKalle Valo 1296e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1297e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1298e705c121SKalle Valo txq->q.read_ptr = (ssn & 0xff); 1299e705c121SKalle Valo txq->q.write_ptr = (ssn & 0xff); 1300e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1301e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1302e705c121SKalle Valo 1303e705c121SKalle Valo if (cfg) { 1304e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1305e705c121SKalle Valo 1306e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1307e705c121SKalle Valo 1308e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1309e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1310e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1311e705c121SKalle Valo iwl_trans_write_mem32(trans, 1312e705c121SKalle Valo trans_pcie->scd_base_addr + 1313e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1314e705c121SKalle Valo ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1315e705c121SKalle Valo SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1316e705c121SKalle Valo ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1317e705c121SKalle Valo SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1318e705c121SKalle Valo 1319e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1320e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1321e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1322e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1323e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1324e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1325e705c121SKalle Valo 1326e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1327e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1328e705c121SKalle Valo trans_pcie->scd_set_active) 1329e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1330e705c121SKalle Valo 1331e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1332e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1333e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1334e705c121SKalle Valo } else { 1335e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1336e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1337e705c121SKalle Valo txq_id, ssn & 0xff); 1338e705c121SKalle Valo } 1339e705c121SKalle Valo 1340e705c121SKalle Valo txq->active = true; 1341e705c121SKalle Valo } 1342e705c121SKalle Valo 1343e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1344e705c121SKalle Valo bool configure_scd) 1345e705c121SKalle Valo { 1346e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1347e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1348e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1349e705c121SKalle Valo static const u32 zero_val[4] = {}; 1350e705c121SKalle Valo 1351e705c121SKalle Valo trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; 1352e705c121SKalle Valo trans_pcie->txq[txq_id].frozen = false; 1353e705c121SKalle Valo 1354e705c121SKalle Valo /* 1355e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1356e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1357e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1358e705c121SKalle Valo * stop_device. 1359e705c121SKalle Valo */ 1360e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1361e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1362e705c121SKalle Valo "queue %d not used", txq_id); 1363e705c121SKalle Valo return; 1364e705c121SKalle Valo } 1365e705c121SKalle Valo 1366e705c121SKalle Valo if (configure_scd) { 1367e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1368e705c121SKalle Valo 1369e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1370e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1371e705c121SKalle Valo } 1372e705c121SKalle Valo 1373e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1374e705c121SKalle Valo trans_pcie->txq[txq_id].ampdu = false; 1375e705c121SKalle Valo 1376e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1377e705c121SKalle Valo } 1378e705c121SKalle Valo 1379e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1380e705c121SKalle Valo 1381e705c121SKalle Valo /* 1382e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1383e705c121SKalle Valo * @priv: device private data point 1384e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1385e705c121SKalle Valo * 1386e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1387e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1388e705c121SKalle Valo * command queue. 1389e705c121SKalle Valo */ 1390e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1391e705c121SKalle Valo struct iwl_host_cmd *cmd) 1392e705c121SKalle Valo { 1393e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1394e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1395e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1396e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1397e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1398e705c121SKalle Valo unsigned long flags; 1399e705c121SKalle Valo void *dup_buf = NULL; 1400e705c121SKalle Valo dma_addr_t phys_addr; 1401e705c121SKalle Valo int idx; 1402e705c121SKalle Valo u16 copy_size, cmd_size, scratch_size; 1403e705c121SKalle Valo bool had_nocopy = false; 1404e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1405e705c121SKalle Valo int i, ret; 1406e705c121SKalle Valo u32 cmd_pos; 1407e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1408e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1409e705c121SKalle Valo 1410e705c121SKalle Valo if (WARN(!trans_pcie->wide_cmd_header && 1411e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1412e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1413e705c121SKalle Valo return -EINVAL; 1414e705c121SKalle Valo 1415e705c121SKalle Valo if (group_id != 0) { 1416e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1417e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1418e705c121SKalle Valo } else { 1419e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1420e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1421e705c121SKalle Valo } 1422e705c121SKalle Valo 1423e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1424e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1425e705c121SKalle Valo 1426e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1427e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1428e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1429e705c121SKalle Valo 1430e705c121SKalle Valo if (!cmd->len[i]) 1431e705c121SKalle Valo continue; 1432e705c121SKalle Valo 1433e705c121SKalle Valo /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ 1434e705c121SKalle Valo if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { 1435e705c121SKalle Valo int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; 1436e705c121SKalle Valo 1437e705c121SKalle Valo if (copy > cmdlen[i]) 1438e705c121SKalle Valo copy = cmdlen[i]; 1439e705c121SKalle Valo cmdlen[i] -= copy; 1440e705c121SKalle Valo cmddata[i] += copy; 1441e705c121SKalle Valo copy_size += copy; 1442e705c121SKalle Valo } 1443e705c121SKalle Valo 1444e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1445e705c121SKalle Valo had_nocopy = true; 1446e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1447e705c121SKalle Valo idx = -EINVAL; 1448e705c121SKalle Valo goto free_dup_buf; 1449e705c121SKalle Valo } 1450e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1451e705c121SKalle Valo /* 1452e705c121SKalle Valo * This is also a chunk that isn't copied 1453e705c121SKalle Valo * to the static buffer so set had_nocopy. 1454e705c121SKalle Valo */ 1455e705c121SKalle Valo had_nocopy = true; 1456e705c121SKalle Valo 1457e705c121SKalle Valo /* only allowed once */ 1458e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1459e705c121SKalle Valo idx = -EINVAL; 1460e705c121SKalle Valo goto free_dup_buf; 1461e705c121SKalle Valo } 1462e705c121SKalle Valo 1463e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1464e705c121SKalle Valo GFP_ATOMIC); 1465e705c121SKalle Valo if (!dup_buf) 1466e705c121SKalle Valo return -ENOMEM; 1467e705c121SKalle Valo } else { 1468e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1469e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1470e705c121SKalle Valo idx = -EINVAL; 1471e705c121SKalle Valo goto free_dup_buf; 1472e705c121SKalle Valo } 1473e705c121SKalle Valo copy_size += cmdlen[i]; 1474e705c121SKalle Valo } 1475e705c121SKalle Valo cmd_size += cmd->len[i]; 1476e705c121SKalle Valo } 1477e705c121SKalle Valo 1478e705c121SKalle Valo /* 1479e705c121SKalle Valo * If any of the command structures end up being larger than 1480e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1481e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1482e705c121SKalle Valo * increase the size of the buffers. 1483e705c121SKalle Valo */ 1484e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1485e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 148639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 148739bdb17eSSharon Dvir cmd->id, copy_size)) { 1488e705c121SKalle Valo idx = -EINVAL; 1489e705c121SKalle Valo goto free_dup_buf; 1490e705c121SKalle Valo } 1491e705c121SKalle Valo 1492e705c121SKalle Valo spin_lock_bh(&txq->lock); 1493e705c121SKalle Valo 1494e705c121SKalle Valo if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1495e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1496e705c121SKalle Valo 1497e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1498e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1499e705c121SKalle Valo idx = -ENOSPC; 1500e705c121SKalle Valo goto free_dup_buf; 1501e705c121SKalle Valo } 1502e705c121SKalle Valo 1503e705c121SKalle Valo idx = get_cmd_index(q, q->write_ptr); 1504e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1505e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1506e705c121SKalle Valo 1507e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1508e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1509e705c121SKalle Valo out_meta->source = cmd; 1510e705c121SKalle Valo 1511e705c121SKalle Valo /* set up the header */ 1512e705c121SKalle Valo if (group_id != 0) { 1513e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1514e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1515e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1516e705c121SKalle Valo out_cmd->hdr_wide.length = 1517e705c121SKalle Valo cpu_to_le16(cmd_size - 1518e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1519e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1520e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1521e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1522e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr)); 1523e705c121SKalle Valo 1524e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1525e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1526e705c121SKalle Valo } else { 1527e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1528e705c121SKalle Valo out_cmd->hdr.sequence = 1529e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1530e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr)); 1531e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1532e705c121SKalle Valo 1533e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1534e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1535e705c121SKalle Valo } 1536e705c121SKalle Valo 1537e705c121SKalle Valo /* and copy the data that needs to be copied */ 1538e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1539e705c121SKalle Valo int copy; 1540e705c121SKalle Valo 1541e705c121SKalle Valo if (!cmd->len[i]) 1542e705c121SKalle Valo continue; 1543e705c121SKalle Valo 1544e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1545e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1546e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1547e705c121SKalle Valo copy = cmd->len[i]; 1548e705c121SKalle Valo 1549e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1550e705c121SKalle Valo cmd_pos += copy; 1551e705c121SKalle Valo copy_size += copy; 1552e705c121SKalle Valo continue; 1553e705c121SKalle Valo } 1554e705c121SKalle Valo 1555e705c121SKalle Valo /* 1556e705c121SKalle Valo * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied 1557e705c121SKalle Valo * in total (for the scratchbuf handling), but copy up to what 1558e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1559e705c121SKalle Valo */ 1560e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1561e705c121SKalle Valo 1562e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1563e705c121SKalle Valo cmd_pos += copy; 1564e705c121SKalle Valo 1565e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 1566e705c121SKalle Valo if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { 1567e705c121SKalle Valo copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; 1568e705c121SKalle Valo 1569e705c121SKalle Valo if (copy > cmd->len[i]) 1570e705c121SKalle Valo copy = cmd->len[i]; 1571e705c121SKalle Valo copy_size += copy; 1572e705c121SKalle Valo } 1573e705c121SKalle Valo } 1574e705c121SKalle Valo 1575e705c121SKalle Valo IWL_DEBUG_HC(trans, 1576e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 157739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1578e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1579e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1580e705c121SKalle Valo cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); 1581e705c121SKalle Valo 1582e705c121SKalle Valo /* start the TFD with the scratchbuf */ 1583e705c121SKalle Valo scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); 1584e705c121SKalle Valo memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); 1585e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 1586e705c121SKalle Valo iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), 1587e705c121SKalle Valo scratch_size, true); 1588e705c121SKalle Valo 1589e705c121SKalle Valo /* map first command fragment, if any remains */ 1590e705c121SKalle Valo if (copy_size > scratch_size) { 1591e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 1592e705c121SKalle Valo ((u8 *)&out_cmd->hdr) + scratch_size, 1593e705c121SKalle Valo copy_size - scratch_size, 1594e705c121SKalle Valo DMA_TO_DEVICE); 1595e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1596e705c121SKalle Valo iwl_pcie_tfd_unmap(trans, out_meta, 1597e705c121SKalle Valo &txq->tfds[q->write_ptr]); 1598e705c121SKalle Valo idx = -ENOMEM; 1599e705c121SKalle Valo goto out; 1600e705c121SKalle Valo } 1601e705c121SKalle Valo 1602e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 1603e705c121SKalle Valo copy_size - scratch_size, false); 1604e705c121SKalle Valo } 1605e705c121SKalle Valo 1606e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1607e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1608e705c121SKalle Valo const void *data = cmddata[i]; 1609e705c121SKalle Valo 1610e705c121SKalle Valo if (!cmdlen[i]) 1611e705c121SKalle Valo continue; 1612e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1613e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1614e705c121SKalle Valo continue; 1615e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1616e705c121SKalle Valo data = dup_buf; 1617e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1618e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1619e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1620e705c121SKalle Valo iwl_pcie_tfd_unmap(trans, out_meta, 1621e705c121SKalle Valo &txq->tfds[q->write_ptr]); 1622e705c121SKalle Valo idx = -ENOMEM; 1623e705c121SKalle Valo goto out; 1624e705c121SKalle Valo } 1625e705c121SKalle Valo 1626e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1627e705c121SKalle Valo } 1628e705c121SKalle Valo 1629e705c121SKalle Valo BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS > 1630e705c121SKalle Valo sizeof(out_meta->flags) * BITS_PER_BYTE); 1631e705c121SKalle Valo out_meta->flags = cmd->flags; 1632e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1633e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1634e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1635e705c121SKalle Valo 1636e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1637e705c121SKalle Valo 1638e705c121SKalle Valo /* start timer if queue currently empty */ 1639e705c121SKalle Valo if (q->read_ptr == q->write_ptr && txq->wd_timeout) 1640e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1641e705c121SKalle Valo 1642e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1643e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1644e705c121SKalle Valo if (ret < 0) { 1645e705c121SKalle Valo idx = ret; 1646e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1647e705c121SKalle Valo goto out; 1648e705c121SKalle Valo } 1649e705c121SKalle Valo 1650e705c121SKalle Valo /* Increment and update queue's write index */ 1651e705c121SKalle Valo q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 1652e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1653e705c121SKalle Valo 1654e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1655e705c121SKalle Valo 1656e705c121SKalle Valo out: 1657e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1658e705c121SKalle Valo free_dup_buf: 1659e705c121SKalle Valo if (idx < 0) 1660e705c121SKalle Valo kfree(dup_buf); 1661e705c121SKalle Valo return idx; 1662e705c121SKalle Valo } 1663e705c121SKalle Valo 1664e705c121SKalle Valo /* 1665e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1666e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1667e705c121SKalle Valo */ 1668e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1669e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1670e705c121SKalle Valo { 1671e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1672e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 167339bdb17eSSharon Dvir u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id); 167439bdb17eSSharon Dvir u32 cmd_id; 1675e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1676e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1677e705c121SKalle Valo int cmd_index; 1678e705c121SKalle Valo struct iwl_device_cmd *cmd; 1679e705c121SKalle Valo struct iwl_cmd_meta *meta; 1680e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1681e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1682e705c121SKalle Valo 1683e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1684e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1685e705c121SKalle Valo * in the queue management code. */ 1686e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1687e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1688e705c121SKalle Valo txq_id, trans_pcie->cmd_queue, sequence, 1689e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, 1690e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { 1691e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1692e705c121SKalle Valo return; 1693e705c121SKalle Valo } 1694e705c121SKalle Valo 1695e705c121SKalle Valo spin_lock_bh(&txq->lock); 1696e705c121SKalle Valo 1697e705c121SKalle Valo cmd_index = get_cmd_index(&txq->q, index); 1698e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1699e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 170039bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1701e705c121SKalle Valo 1702e705c121SKalle Valo iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); 1703e705c121SKalle Valo 1704e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1705e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1706e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1707e705c121SKalle Valo 1708e705c121SKalle Valo meta->source->resp_pkt = pkt; 1709e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1710e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1711e705c121SKalle Valo } 1712e705c121SKalle Valo 1713dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1714dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1715dcbb4746SEmmanuel Grumbach 1716e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1717e705c121SKalle Valo 1718e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1719e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1720e705c121SKalle Valo IWL_WARN(trans, 1721e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 172239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1723e705c121SKalle Valo } 1724e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1725e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 172639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1727e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1728e705c121SKalle Valo } 1729e705c121SKalle Valo 17304cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 17314cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 17324cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 17334cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 17344cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 17354cbb8e50SLuciano Coelho } 17364cbb8e50SLuciano Coelho 17374cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 17384cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 17394cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 17404cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 17414cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 17424cbb8e50SLuciano Coelho } 17434cbb8e50SLuciano Coelho 1744e705c121SKalle Valo meta->flags = 0; 1745e705c121SKalle Valo 1746e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1747e705c121SKalle Valo } 1748e705c121SKalle Valo 1749e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1750e705c121SKalle Valo 1751e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1752e705c121SKalle Valo struct iwl_host_cmd *cmd) 1753e705c121SKalle Valo { 1754e705c121SKalle Valo int ret; 1755e705c121SKalle Valo 1756e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1757e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1758e705c121SKalle Valo return -EINVAL; 1759e705c121SKalle Valo 1760e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1761e705c121SKalle Valo if (ret < 0) { 1762e705c121SKalle Valo IWL_ERR(trans, 1763e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 176439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1765e705c121SKalle Valo return ret; 1766e705c121SKalle Valo } 1767e705c121SKalle Valo return 0; 1768e705c121SKalle Valo } 1769e705c121SKalle Valo 1770e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1771e705c121SKalle Valo struct iwl_host_cmd *cmd) 1772e705c121SKalle Valo { 1773e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1774e705c121SKalle Valo int cmd_idx; 1775e705c121SKalle Valo int ret; 1776e705c121SKalle Valo 1777e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 177839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1779e705c121SKalle Valo 1780e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1781e705c121SKalle Valo &trans->status), 1782e705c121SKalle Valo "Command %s: a command is already active!\n", 178339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1784e705c121SKalle Valo return -EIO; 1785e705c121SKalle Valo 1786e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 178739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1788e705c121SKalle Valo 1789e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1790e705c121SKalle Valo if (cmd_idx < 0) { 1791e705c121SKalle Valo ret = cmd_idx; 1792e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1793e705c121SKalle Valo IWL_ERR(trans, 1794e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 179539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1796e705c121SKalle Valo return ret; 1797e705c121SKalle Valo } 1798e705c121SKalle Valo 1799e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1800e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1801e705c121SKalle Valo &trans->status), 1802e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1803e705c121SKalle Valo if (!ret) { 1804e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1805e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1806e705c121SKalle Valo 1807e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 180839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1809e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1810e705c121SKalle Valo 1811e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1812e705c121SKalle Valo q->read_ptr, q->write_ptr); 1813e705c121SKalle Valo 1814e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1815e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 181639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1817e705c121SKalle Valo ret = -ETIMEDOUT; 1818e705c121SKalle Valo 1819e705c121SKalle Valo iwl_force_nmi(trans); 1820e705c121SKalle Valo iwl_trans_fw_error(trans); 1821e705c121SKalle Valo 1822e705c121SKalle Valo goto cancel; 1823e705c121SKalle Valo } 1824e705c121SKalle Valo 1825e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1826e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 182739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1828e705c121SKalle Valo dump_stack(); 1829e705c121SKalle Valo ret = -EIO; 1830e705c121SKalle Valo goto cancel; 1831e705c121SKalle Valo } 1832e705c121SKalle Valo 1833e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1834e705c121SKalle Valo test_bit(STATUS_RFKILL, &trans->status)) { 1835e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1836e705c121SKalle Valo ret = -ERFKILL; 1837e705c121SKalle Valo goto cancel; 1838e705c121SKalle Valo } 1839e705c121SKalle Valo 1840e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1841e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 184239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1843e705c121SKalle Valo ret = -EIO; 1844e705c121SKalle Valo goto cancel; 1845e705c121SKalle Valo } 1846e705c121SKalle Valo 1847e705c121SKalle Valo return 0; 1848e705c121SKalle Valo 1849e705c121SKalle Valo cancel: 1850e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1851e705c121SKalle Valo /* 1852e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1853e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1854e705c121SKalle Valo * in later, it will possibly set an invalid 1855e705c121SKalle Valo * address (cmd->meta.source). 1856e705c121SKalle Valo */ 1857e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue]. 1858e705c121SKalle Valo entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1859e705c121SKalle Valo } 1860e705c121SKalle Valo 1861e705c121SKalle Valo if (cmd->resp_pkt) { 1862e705c121SKalle Valo iwl_free_resp(cmd); 1863e705c121SKalle Valo cmd->resp_pkt = NULL; 1864e705c121SKalle Valo } 1865e705c121SKalle Valo 1866e705c121SKalle Valo return ret; 1867e705c121SKalle Valo } 1868e705c121SKalle Valo 1869e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1870e705c121SKalle Valo { 1871e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1872e705c121SKalle Valo test_bit(STATUS_RFKILL, &trans->status)) { 1873e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1874e705c121SKalle Valo cmd->id); 1875e705c121SKalle Valo return -ERFKILL; 1876e705c121SKalle Valo } 1877e705c121SKalle Valo 1878e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 1879e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 1880e705c121SKalle Valo 1881e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 1882e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 1883e705c121SKalle Valo } 1884e705c121SKalle Valo 18853a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 18863a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 18873a0b2a42SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 18883a0b2a42SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 18893a0b2a42SEmmanuel Grumbach { 18903a0b2a42SEmmanuel Grumbach struct iwl_queue *q = &txq->q; 18913a0b2a42SEmmanuel Grumbach u16 tb2_len; 18923a0b2a42SEmmanuel Grumbach int i; 18933a0b2a42SEmmanuel Grumbach 18943a0b2a42SEmmanuel Grumbach /* 18953a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 18963a0b2a42SEmmanuel Grumbach * of skb's head, if any 18973a0b2a42SEmmanuel Grumbach */ 18983a0b2a42SEmmanuel Grumbach tb2_len = skb_headlen(skb) - hdr_len; 18993a0b2a42SEmmanuel Grumbach 19003a0b2a42SEmmanuel Grumbach if (tb2_len > 0) { 19013a0b2a42SEmmanuel Grumbach dma_addr_t tb2_phys = dma_map_single(trans->dev, 19023a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 19033a0b2a42SEmmanuel Grumbach tb2_len, DMA_TO_DEVICE); 19043a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 19053a0b2a42SEmmanuel Grumbach iwl_pcie_tfd_unmap(trans, out_meta, 19063a0b2a42SEmmanuel Grumbach &txq->tfds[q->write_ptr]); 19073a0b2a42SEmmanuel Grumbach return -EINVAL; 19083a0b2a42SEmmanuel Grumbach } 19093a0b2a42SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 19103a0b2a42SEmmanuel Grumbach } 19113a0b2a42SEmmanuel Grumbach 19123a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 19133a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 19143a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 19153a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 19163a0b2a42SEmmanuel Grumbach int tb_idx; 19173a0b2a42SEmmanuel Grumbach 19183a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 19193a0b2a42SEmmanuel Grumbach continue; 19203a0b2a42SEmmanuel Grumbach 19213a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 19223a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 19233a0b2a42SEmmanuel Grumbach 19243a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 19253a0b2a42SEmmanuel Grumbach iwl_pcie_tfd_unmap(trans, out_meta, 19263a0b2a42SEmmanuel Grumbach &txq->tfds[q->write_ptr]); 19273a0b2a42SEmmanuel Grumbach return -EINVAL; 19283a0b2a42SEmmanuel Grumbach } 19293a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 19303a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 19313a0b2a42SEmmanuel Grumbach 19323a0b2a42SEmmanuel Grumbach out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS); 19333a0b2a42SEmmanuel Grumbach } 19343a0b2a42SEmmanuel Grumbach 19353a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 19363a0b2a42SEmmanuel Grumbach &txq->tfds[txq->q.write_ptr], 19373a0b2a42SEmmanuel Grumbach sizeof(struct iwl_tfd), 19383a0b2a42SEmmanuel Grumbach &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, 19393a0b2a42SEmmanuel Grumbach skb->data + hdr_len, tb2_len); 19403a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx_data(trans->dev, skb, 19413a0b2a42SEmmanuel Grumbach hdr_len, skb->len - hdr_len); 19423a0b2a42SEmmanuel Grumbach return 0; 19433a0b2a42SEmmanuel Grumbach } 19443a0b2a42SEmmanuel Grumbach 19456eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 19466eb5e529SEmmanuel Grumbach static struct iwl_tso_hdr_page * 19476eb5e529SEmmanuel Grumbach get_page_hdr(struct iwl_trans *trans, size_t len) 19486eb5e529SEmmanuel Grumbach { 19496eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19506eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 19516eb5e529SEmmanuel Grumbach 19526eb5e529SEmmanuel Grumbach if (!p->page) 19536eb5e529SEmmanuel Grumbach goto alloc; 19546eb5e529SEmmanuel Grumbach 19556eb5e529SEmmanuel Grumbach /* enough room on this page */ 19566eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 19576eb5e529SEmmanuel Grumbach return p; 19586eb5e529SEmmanuel Grumbach 19596eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 19606eb5e529SEmmanuel Grumbach __free_page(p->page); 19616eb5e529SEmmanuel Grumbach 19626eb5e529SEmmanuel Grumbach alloc: 19636eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 19646eb5e529SEmmanuel Grumbach if (!p->page) 19656eb5e529SEmmanuel Grumbach return NULL; 19666eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 19676eb5e529SEmmanuel Grumbach return p; 19686eb5e529SEmmanuel Grumbach } 19696eb5e529SEmmanuel Grumbach 19706eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 19716eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 19726eb5e529SEmmanuel Grumbach { 19736eb5e529SEmmanuel Grumbach if (ipv6) { 19746eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 19756eb5e529SEmmanuel Grumbach 19766eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 19776eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 19786eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 19796eb5e529SEmmanuel Grumbach } else { 19806eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 19816eb5e529SEmmanuel Grumbach 19826eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 19836eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 19846eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 19856eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 19866eb5e529SEmmanuel Grumbach } 19876eb5e529SEmmanuel Grumbach } 19886eb5e529SEmmanuel Grumbach 19896eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 19906eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 19916eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 19926eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 19936eb5e529SEmmanuel Grumbach { 19946eb5e529SEmmanuel Grumbach struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 19956eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 19966eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 19976eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 19986eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 19996eb5e529SEmmanuel Grumbach struct iwl_queue *q = &txq->q; 20006eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 20016eb5e529SEmmanuel Grumbach u8 *start_hdr; 20026eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 20036eb5e529SEmmanuel Grumbach int ret; 20046eb5e529SEmmanuel Grumbach struct tso_t tso; 20056eb5e529SEmmanuel Grumbach 20066eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 20076eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 20086eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 20096eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 20106eb5e529SEmmanuel Grumbach 20116eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 20126eb5e529SEmmanuel Grumbach &txq->tfds[txq->q.write_ptr], 20136eb5e529SEmmanuel Grumbach sizeof(struct iwl_tfd), 20146eb5e529SEmmanuel Grumbach &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, 20156eb5e529SEmmanuel Grumbach NULL, 0); 20166eb5e529SEmmanuel Grumbach 20176eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 20186eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 20196eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 20206eb5e529SEmmanuel Grumbach amsdu_pad = 0; 20216eb5e529SEmmanuel Grumbach 20226eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 20236eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 20246eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 20256eb5e529SEmmanuel Grumbach 20266eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 20276eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 20286eb5e529SEmmanuel Grumbach if (!hdr_page) 20296eb5e529SEmmanuel Grumbach return -ENOMEM; 20306eb5e529SEmmanuel Grumbach 20316eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 20326eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 20336eb5e529SEmmanuel Grumbach info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA] = hdr_page->page; 20346eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 20356eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 20366eb5e529SEmmanuel Grumbach 20376eb5e529SEmmanuel Grumbach /* 20386eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 20396eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 20406eb5e529SEmmanuel Grumbach */ 20416eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 20426eb5e529SEmmanuel Grumbach 20436eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 20446eb5e529SEmmanuel Grumbach 20456eb5e529SEmmanuel Grumbach while (total_len) { 20466eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 20476eb5e529SEmmanuel Grumbach unsigned int data_left = 20486eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 20496eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 20506eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 20516eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 20526eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 20536eb5e529SEmmanuel Grumbach u8 *iph; 20546eb5e529SEmmanuel Grumbach 20556eb5e529SEmmanuel Grumbach total_len -= data_left; 20566eb5e529SEmmanuel Grumbach 20576eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 20586eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 20596eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 20606eb5e529SEmmanuel Grumbach data_left)) & 0x3; 20616eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 20626eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 20636eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 20646eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 20656eb5e529SEmmanuel Grumbach 20666eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 20676eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 20686eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 20696eb5e529SEmmanuel Grumbach 20706eb5e529SEmmanuel Grumbach /* 20716eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 20726eb5e529SEmmanuel Grumbach * as MAC header. 20736eb5e529SEmmanuel Grumbach */ 20746eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 20756eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 20766eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 20776eb5e529SEmmanuel Grumbach 20786eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 20796eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 20806eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 20816eb5e529SEmmanuel Grumbach GFP_ATOMIC); 20826eb5e529SEmmanuel Grumbach if (!csum_skb) { 20836eb5e529SEmmanuel Grumbach ret = -ENOMEM; 20846eb5e529SEmmanuel Grumbach goto out_unmap; 20856eb5e529SEmmanuel Grumbach } 20866eb5e529SEmmanuel Grumbach 20876eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 20886eb5e529SEmmanuel Grumbach skb->protocol == 20896eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 20906eb5e529SEmmanuel Grumbach data_left); 20916eb5e529SEmmanuel Grumbach 20926eb5e529SEmmanuel Grumbach memcpy(skb_put(csum_skb, tcp_hdrlen(skb)), 20936eb5e529SEmmanuel Grumbach tcph, tcp_hdrlen(skb)); 20946eb5e529SEmmanuel Grumbach skb_set_transport_header(csum_skb, 0); 20956eb5e529SEmmanuel Grumbach csum_skb->csum_start = 20966eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 20976eb5e529SEmmanuel Grumbach csum_skb->head; 20986eb5e529SEmmanuel Grumbach } 20996eb5e529SEmmanuel Grumbach 21006eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 21016eb5e529SEmmanuel Grumbach 21026eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 21036eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 21046eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 21056eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 21066eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 21076eb5e529SEmmanuel Grumbach ret = -EINVAL; 21086eb5e529SEmmanuel Grumbach goto out_unmap; 21096eb5e529SEmmanuel Grumbach } 21106eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 21116eb5e529SEmmanuel Grumbach hdr_tb_len, false); 21126eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 21136eb5e529SEmmanuel Grumbach hdr_tb_len); 21146eb5e529SEmmanuel Grumbach 21156eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 21166eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 21176eb5e529SEmmanuel Grumbach 21186eb5e529SEmmanuel Grumbach /* put the payload */ 21196eb5e529SEmmanuel Grumbach while (data_left) { 21206eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 21216eb5e529SEmmanuel Grumbach data_left); 21226eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 21236eb5e529SEmmanuel Grumbach 21246eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 21256eb5e529SEmmanuel Grumbach memcpy(skb_put(csum_skb, size), tso.data, size); 21266eb5e529SEmmanuel Grumbach 21276eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 21286eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 21296eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 21306eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 21316eb5e529SEmmanuel Grumbach ret = -EINVAL; 21326eb5e529SEmmanuel Grumbach goto out_unmap; 21336eb5e529SEmmanuel Grumbach } 21346eb5e529SEmmanuel Grumbach 21356eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 21366eb5e529SEmmanuel Grumbach size, false); 21376eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 21386eb5e529SEmmanuel Grumbach size); 21396eb5e529SEmmanuel Grumbach 21406eb5e529SEmmanuel Grumbach data_left -= size; 21416eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 21426eb5e529SEmmanuel Grumbach } 21436eb5e529SEmmanuel Grumbach 21446eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 21456eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 21466eb5e529SEmmanuel Grumbach __wsum csum; 21476eb5e529SEmmanuel Grumbach 21486eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 21496eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 21506eb5e529SEmmanuel Grumbach csum_skb->len - 21516eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 21526eb5e529SEmmanuel Grumbach 0); 21536eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 21546eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 21556eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 21566eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 21576eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 21586eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 21596eb5e529SEmmanuel Grumbach } 21606eb5e529SEmmanuel Grumbach } 21616eb5e529SEmmanuel Grumbach 21626eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 21636eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 21646eb5e529SEmmanuel Grumbach 21656eb5e529SEmmanuel Grumbach return 0; 21666eb5e529SEmmanuel Grumbach 21676eb5e529SEmmanuel Grumbach out_unmap: 21686eb5e529SEmmanuel Grumbach iwl_pcie_tfd_unmap(trans, out_meta, &txq->tfds[q->write_ptr]); 21696eb5e529SEmmanuel Grumbach return ret; 21706eb5e529SEmmanuel Grumbach } 21716eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 21726eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 21736eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 21746eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 21756eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 21766eb5e529SEmmanuel Grumbach { 21776eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 21786eb5e529SEmmanuel Grumbach WARN_ON(1); 21796eb5e529SEmmanuel Grumbach 21806eb5e529SEmmanuel Grumbach return -1; 21816eb5e529SEmmanuel Grumbach } 21826eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 21836eb5e529SEmmanuel Grumbach 2184e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2185e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2186e705c121SKalle Valo { 2187e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2188e705c121SKalle Valo struct ieee80211_hdr *hdr; 2189e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2190e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2191e705c121SKalle Valo struct iwl_txq *txq; 2192e705c121SKalle Valo struct iwl_queue *q; 2193e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2194e705c121SKalle Valo void *tb1_addr; 21953a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2196e705c121SKalle Valo bool wait_write_ptr; 2197e705c121SKalle Valo __le16 fc; 2198e705c121SKalle Valo u8 hdr_len; 2199e705c121SKalle Valo u16 wifi_seq; 2200e705c121SKalle Valo 2201e705c121SKalle Valo txq = &trans_pcie->txq[txq_id]; 2202e705c121SKalle Valo q = &txq->q; 2203e705c121SKalle Valo 2204e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2205e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2206e705c121SKalle Valo return -EINVAL; 2207e705c121SKalle Valo 220841837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 220941837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 221041837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 221141837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 221241837ca9SEmmanuel Grumbach __wsum csum; 221341837ca9SEmmanuel Grumbach 221441837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 221541837ca9SEmmanuel Grumbach return -1; 221641837ca9SEmmanuel Grumbach 221741837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 221841837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 22193955525dSEmmanuel Grumbach 22203955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 222141837ca9SEmmanuel Grumbach } 222241837ca9SEmmanuel Grumbach 2223e705c121SKalle Valo if (skb_is_nonlinear(skb) && 2224e705c121SKalle Valo skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS && 2225e705c121SKalle Valo __skb_linearize(skb)) 2226e705c121SKalle Valo return -ENOMEM; 2227e705c121SKalle Valo 2228e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2229e705c121SKalle Valo * so there's no need to check if it's readable there 2230e705c121SKalle Valo */ 2231e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2232e705c121SKalle Valo fc = hdr->frame_control; 2233e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2234e705c121SKalle Valo 2235e705c121SKalle Valo spin_lock(&txq->lock); 2236e705c121SKalle Valo 22373955525dSEmmanuel Grumbach if (iwl_queue_space(q) < q->high_mark) { 22383955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 22393955525dSEmmanuel Grumbach 22403955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 22413955525dSEmmanuel Grumbach if (unlikely(iwl_queue_space(q) < 3)) { 22423955525dSEmmanuel Grumbach struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 22433955525dSEmmanuel Grumbach 22443955525dSEmmanuel Grumbach info->driver_data[IWL_TRANS_FIRST_DRIVER_DATA + 1] = 22453955525dSEmmanuel Grumbach dev_cmd; 22463955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 22473955525dSEmmanuel Grumbach 22483955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 22493955525dSEmmanuel Grumbach return 0; 22503955525dSEmmanuel Grumbach } 22513955525dSEmmanuel Grumbach } 22523955525dSEmmanuel Grumbach 2253e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2254e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2255e705c121SKalle Valo * the BA. 2256e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2257e705c121SKalle Valo */ 2258e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2259e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2260e705c121SKalle Valo (wifi_seq & 0xff) != q->write_ptr, 2261e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2262e705c121SKalle Valo txq_id, wifi_seq, q->write_ptr); 2263e705c121SKalle Valo 2264e705c121SKalle Valo /* Set up driver data for this TFD */ 2265e705c121SKalle Valo txq->entries[q->write_ptr].skb = skb; 2266e705c121SKalle Valo txq->entries[q->write_ptr].cmd = dev_cmd; 2267e705c121SKalle Valo 2268e705c121SKalle Valo dev_cmd->hdr.sequence = 2269e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2270e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr))); 2271e705c121SKalle Valo 2272e705c121SKalle Valo tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); 2273e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2274e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2275e705c121SKalle Valo 2276e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2277e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2278e705c121SKalle Valo 2279e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2280e705c121SKalle Valo out_meta = &txq->entries[q->write_ptr].meta; 2281e705c121SKalle Valo out_meta->flags = 0; 2282e705c121SKalle Valo 2283e705c121SKalle Valo /* 2284e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2285e705c121SKalle Valo * and the 802.11 header - dword aligned size 2286e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2287e705c121SKalle Valo * setup of the first TB) 2288e705c121SKalle Valo */ 2289e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 2290e705c121SKalle Valo hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; 2291e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2292e705c121SKalle Valo 2293e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2294e705c121SKalle Valo if (tb1_len != len) 2295e705c121SKalle Valo tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 2296e705c121SKalle Valo 2297e705c121SKalle Valo /* The first TB points to the scratchbuf data - min_copy bytes */ 2298e705c121SKalle Valo memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, 2299e705c121SKalle Valo IWL_HCMD_SCRATCHBUF_SIZE); 2300e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 2301e705c121SKalle Valo IWL_HCMD_SCRATCHBUF_SIZE, true); 2302e705c121SKalle Valo 2303e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 2304e705c121SKalle Valo BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); 2305e705c121SKalle Valo 2306e705c121SKalle Valo /* map the data for TB1 */ 2307e705c121SKalle Valo tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; 2308e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2309e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2310e705c121SKalle Valo goto out_err; 2311e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2312e705c121SKalle Valo 23136eb5e529SEmmanuel Grumbach if (ieee80211_is_data_qos(fc) && 23146eb5e529SEmmanuel Grumbach (*ieee80211_get_qos_ctl(hdr) & IEEE80211_QOS_CTL_A_MSDU_PRESENT)) { 23156eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 23166eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 23176eb5e529SEmmanuel Grumbach tb1_len))) 2318e705c121SKalle Valo goto out_err; 23196eb5e529SEmmanuel Grumbach } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 23206eb5e529SEmmanuel Grumbach out_meta, dev_cmd, tb1_len))) { 23216eb5e529SEmmanuel Grumbach goto out_err; 23226eb5e529SEmmanuel Grumbach } 2323e705c121SKalle Valo 2324e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 2325e705c121SKalle Valo iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); 2326e705c121SKalle Valo 2327e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2328e705c121SKalle Valo 2329e705c121SKalle Valo /* start timer if queue currently empty */ 2330e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 2331e705c121SKalle Valo if (txq->wd_timeout) { 2332e705c121SKalle Valo /* 2333e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2334e705c121SKalle Valo * set the timer in remainder so that the timer will 2335e705c121SKalle Valo * be armed with the right value when the station will 2336e705c121SKalle Valo * wake up. 2337e705c121SKalle Valo */ 2338e705c121SKalle Valo if (!txq->frozen) 2339e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2340e705c121SKalle Valo jiffies + txq->wd_timeout); 2341e705c121SKalle Valo else 2342e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2343e705c121SKalle Valo } 2344e705c121SKalle Valo IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); 2345e705c121SKalle Valo iwl_trans_pcie_ref(trans); 2346e705c121SKalle Valo } 2347e705c121SKalle Valo 2348e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 2349e705c121SKalle Valo q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 2350e705c121SKalle Valo if (!wait_write_ptr) 2351e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2352e705c121SKalle Valo 2353e705c121SKalle Valo /* 2354e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2355e705c121SKalle Valo * and we will get a TX status notification eventually. 2356e705c121SKalle Valo */ 2357e705c121SKalle Valo spin_unlock(&txq->lock); 2358e705c121SKalle Valo return 0; 2359e705c121SKalle Valo out_err: 2360e705c121SKalle Valo spin_unlock(&txq->lock); 2361e705c121SKalle Valo return -1; 2362e705c121SKalle Valo } 2363