1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 44cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 54cbb8e50SLuciano Coelho * Copyright(c) 2016 Intel Deutschland GmbH 6e705c121SKalle Valo * 7e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 8e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 9e705c121SKalle Valo * 10e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 11e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 12e705c121SKalle Valo * published by the Free Software Foundation. 13e705c121SKalle Valo * 14e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 15e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17e705c121SKalle Valo * more details. 18e705c121SKalle Valo * 19e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 20e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 21e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 22e705c121SKalle Valo * 23e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 24e705c121SKalle Valo * file called LICENSE. 25e705c121SKalle Valo * 26e705c121SKalle Valo * Contact Information: 27cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 28e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 29e705c121SKalle Valo * 30e705c121SKalle Valo *****************************************************************************/ 31e705c121SKalle Valo #include <linux/etherdevice.h> 326eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 33e705c121SKalle Valo #include <linux/slab.h> 34e705c121SKalle Valo #include <linux/sched.h> 3571b1230cSLuca Coelho #include <linux/pm_runtime.h> 366eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 376eb5e529SEmmanuel Grumbach #include <net/tso.h> 38e705c121SKalle Valo 39e705c121SKalle Valo #include "iwl-debug.h" 40e705c121SKalle Valo #include "iwl-csr.h" 41e705c121SKalle Valo #include "iwl-prph.h" 42e705c121SKalle Valo #include "iwl-io.h" 43e705c121SKalle Valo #include "iwl-scd.h" 44e705c121SKalle Valo #include "iwl-op-mode.h" 45e705c121SKalle Valo #include "internal.h" 46e705c121SKalle Valo /* FIXME: need to abstract out TX command (once we know what it looks like) */ 47e705c121SKalle Valo #include "dvm/commands.h" 48e705c121SKalle Valo 49e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 50e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 51e705c121SKalle Valo 52e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 53e705c121SKalle Valo * DMA services 54e705c121SKalle Valo * 55e705c121SKalle Valo * Theory of operation 56e705c121SKalle Valo * 57e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 58e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 59e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 60e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 61e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 62e705c121SKalle Valo * queue states. 63e705c121SKalle Valo * 64e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 65e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 66e705c121SKalle Valo * 67e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 68e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 69e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 70e705c121SKalle Valo * Tx queue resumed. 71e705c121SKalle Valo * 72e705c121SKalle Valo ***************************************************/ 73e22744afSSara Sharon 74e705c121SKalle Valo static int iwl_queue_space(const struct iwl_queue *q) 75e705c121SKalle Valo { 76e705c121SKalle Valo unsigned int max; 77e705c121SKalle Valo unsigned int used; 78e705c121SKalle Valo 79e705c121SKalle Valo /* 80e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 81e705c121SKalle Valo * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue. 82e705c121SKalle Valo * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need 83e705c121SKalle Valo * to reserve any queue entries for this purpose. 84e705c121SKalle Valo */ 85e705c121SKalle Valo if (q->n_window < TFD_QUEUE_SIZE_MAX) 86e705c121SKalle Valo max = q->n_window; 87e705c121SKalle Valo else 88e705c121SKalle Valo max = TFD_QUEUE_SIZE_MAX - 1; 89e705c121SKalle Valo 90e705c121SKalle Valo /* 91e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to 92e705c121SKalle Valo * modulo by TFD_QUEUE_SIZE_MAX and is well defined. 93e705c121SKalle Valo */ 94e705c121SKalle Valo used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1); 95e705c121SKalle Valo 96e705c121SKalle Valo if (WARN_ON(used > max)) 97e705c121SKalle Valo return 0; 98e705c121SKalle Valo 99e705c121SKalle Valo return max - used; 100e705c121SKalle Valo } 101e705c121SKalle Valo 102e705c121SKalle Valo /* 103e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 104e705c121SKalle Valo */ 105e705c121SKalle Valo static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id) 106e705c121SKalle Valo { 107e705c121SKalle Valo q->n_window = slots_num; 108e705c121SKalle Valo q->id = id; 109e705c121SKalle Valo 110e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 111e705c121SKalle Valo * get_cmd_index is broken. */ 112e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 113e705c121SKalle Valo return -EINVAL; 114e705c121SKalle Valo 115e705c121SKalle Valo q->low_mark = q->n_window / 4; 116e705c121SKalle Valo if (q->low_mark < 4) 117e705c121SKalle Valo q->low_mark = 4; 118e705c121SKalle Valo 119e705c121SKalle Valo q->high_mark = q->n_window / 8; 120e705c121SKalle Valo if (q->high_mark < 2) 121e705c121SKalle Valo q->high_mark = 2; 122e705c121SKalle Valo 123e705c121SKalle Valo q->write_ptr = 0; 124e705c121SKalle Valo q->read_ptr = 0; 125e705c121SKalle Valo 126e705c121SKalle Valo return 0; 127e705c121SKalle Valo } 128e705c121SKalle Valo 129e705c121SKalle Valo static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 130e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 131e705c121SKalle Valo { 132e705c121SKalle Valo if (WARN_ON(ptr->addr)) 133e705c121SKalle Valo return -EINVAL; 134e705c121SKalle Valo 135e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 136e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 137e705c121SKalle Valo if (!ptr->addr) 138e705c121SKalle Valo return -ENOMEM; 139e705c121SKalle Valo ptr->size = size; 140e705c121SKalle Valo return 0; 141e705c121SKalle Valo } 142e705c121SKalle Valo 143e705c121SKalle Valo static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, 144e705c121SKalle Valo struct iwl_dma_ptr *ptr) 145e705c121SKalle Valo { 146e705c121SKalle Valo if (unlikely(!ptr->addr)) 147e705c121SKalle Valo return; 148e705c121SKalle Valo 149e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 150e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 151e705c121SKalle Valo } 152e705c121SKalle Valo 153e705c121SKalle Valo static void iwl_pcie_txq_stuck_timer(unsigned long data) 154e705c121SKalle Valo { 155e705c121SKalle Valo struct iwl_txq *txq = (void *)data; 156e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 157e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 158e705c121SKalle Valo 159e705c121SKalle Valo spin_lock(&txq->lock); 160e705c121SKalle Valo /* check if triggered erroneously */ 161e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) { 162e705c121SKalle Valo spin_unlock(&txq->lock); 163e705c121SKalle Valo return; 164e705c121SKalle Valo } 165e705c121SKalle Valo spin_unlock(&txq->lock); 166e705c121SKalle Valo 167e705c121SKalle Valo IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, 168e705c121SKalle Valo jiffies_to_msecs(txq->wd_timeout)); 169e705c121SKalle Valo 17038398efbSSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 171e705c121SKalle Valo 172e705c121SKalle Valo iwl_force_nmi(trans); 173e705c121SKalle Valo } 174e705c121SKalle Valo 175e705c121SKalle Valo /* 176e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 177e705c121SKalle Valo */ 178e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 1794fe10bc6SSara Sharon struct iwl_txq *txq, u16 byte_cnt, 1804fe10bc6SSara Sharon int num_tbs) 181e705c121SKalle Valo { 182e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 183e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 184e705c121SKalle Valo int write_ptr = txq->q.write_ptr; 185e705c121SKalle Valo int txq_id = txq->q.id; 186e705c121SKalle Valo u8 sec_ctl = 0; 187e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 188e705c121SKalle Valo __le16 bc_ent; 189e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 190e705c121SKalle Valo (void *) txq->entries[txq->q.write_ptr].cmd->payload; 191e705c121SKalle Valo 192e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 193e705c121SKalle Valo 194e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 195e705c121SKalle Valo 196e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 197e705c121SKalle Valo case TX_CMD_SEC_CCM: 198e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 199e705c121SKalle Valo break; 200e705c121SKalle Valo case TX_CMD_SEC_TKIP: 201e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 202e705c121SKalle Valo break; 203e705c121SKalle Valo case TX_CMD_SEC_WEP: 204e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 205e705c121SKalle Valo break; 206e705c121SKalle Valo } 207e705c121SKalle Valo if (trans_pcie->bc_table_dword) 208e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 209e705c121SKalle Valo 210e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 211e705c121SKalle Valo return; 212e705c121SKalle Valo 2134fe10bc6SSara Sharon if (trans->cfg->use_tfh) { 2144fe10bc6SSara Sharon u8 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) + 2154fe10bc6SSara Sharon num_tbs * sizeof(struct iwl_tfh_tb); 2164fe10bc6SSara Sharon /* 2174fe10bc6SSara Sharon * filled_tfd_size contains the number of filled bytes in the 2184fe10bc6SSara Sharon * TFD. 2194fe10bc6SSara Sharon * Dividing it by 64 will give the number of chunks to fetch 2204fe10bc6SSara Sharon * to SRAM- 0 for one chunk, 1 for 2 and so on. 2214fe10bc6SSara Sharon * If, for example, TFD contains only 3 TBs then 32 bytes 2224fe10bc6SSara Sharon * of the TFD are used, and only one chunk of 64 bytes should 2234fe10bc6SSara Sharon * be fetched 2244fe10bc6SSara Sharon */ 2254fe10bc6SSara Sharon u8 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1; 2264fe10bc6SSara Sharon 2274fe10bc6SSara Sharon bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12)); 2284fe10bc6SSara Sharon } else { 2294fe10bc6SSara Sharon u8 sta_id = tx_cmd->sta_id; 2304fe10bc6SSara Sharon 231e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 2324fe10bc6SSara Sharon } 233e705c121SKalle Valo 234e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 235e705c121SKalle Valo 236e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 237e705c121SKalle Valo scd_bc_tbl[txq_id]. 238e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 239e705c121SKalle Valo } 240e705c121SKalle Valo 241e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 242e705c121SKalle Valo struct iwl_txq *txq) 243e705c121SKalle Valo { 244e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 245e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 246e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 247e705c121SKalle Valo int txq_id = txq->q.id; 248e705c121SKalle Valo int read_ptr = txq->q.read_ptr; 249e705c121SKalle Valo u8 sta_id = 0; 250e705c121SKalle Valo __le16 bc_ent; 251e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 252e705c121SKalle Valo (void *)txq->entries[txq->q.read_ptr].cmd->payload; 253e705c121SKalle Valo 254e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 255e705c121SKalle Valo 256e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 257e705c121SKalle Valo sta_id = tx_cmd->sta_id; 258e705c121SKalle Valo 259e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 2604fe10bc6SSara Sharon 261e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 262e705c121SKalle Valo 263e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 264e705c121SKalle Valo scd_bc_tbl[txq_id]. 265e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 266e705c121SKalle Valo } 267e705c121SKalle Valo 268e705c121SKalle Valo /* 269e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 270e705c121SKalle Valo */ 271e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 272e705c121SKalle Valo struct iwl_txq *txq) 273e705c121SKalle Valo { 274e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 275e705c121SKalle Valo u32 reg = 0; 276e705c121SKalle Valo int txq_id = txq->q.id; 277e705c121SKalle Valo 278e705c121SKalle Valo lockdep_assert_held(&txq->lock); 279e705c121SKalle Valo 280e705c121SKalle Valo /* 281e705c121SKalle Valo * explicitly wake up the NIC if: 282e705c121SKalle Valo * 1. shadow registers aren't enabled 283e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 284e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 285e705c121SKalle Valo */ 286e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 287e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 288e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 289e705c121SKalle Valo /* 290e705c121SKalle Valo * wake up nic if it's powered down ... 291e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 292e705c121SKalle Valo * time we'll skip this part. 293e705c121SKalle Valo */ 294e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 295e705c121SKalle Valo 296e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 297e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 298e705c121SKalle Valo txq_id, reg); 299e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 300e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 301e705c121SKalle Valo txq->need_update = true; 302e705c121SKalle Valo return; 303e705c121SKalle Valo } 304e705c121SKalle Valo } 305e705c121SKalle Valo 306e705c121SKalle Valo /* 307e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 308e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 309e705c121SKalle Valo */ 310e705c121SKalle Valo IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr); 3110cd58eaaSEmmanuel Grumbach if (!txq->block) 3120cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 3130cd58eaaSEmmanuel Grumbach txq->q.write_ptr | (txq_id << 8)); 314e705c121SKalle Valo } 315e705c121SKalle Valo 316e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 317e705c121SKalle Valo { 318e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 319e705c121SKalle Valo int i; 320e705c121SKalle Valo 321e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 322e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[i]; 323e705c121SKalle Valo 324e705c121SKalle Valo spin_lock_bh(&txq->lock); 325e705c121SKalle Valo if (trans_pcie->txq[i].need_update) { 326e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 327e705c121SKalle Valo trans_pcie->txq[i].need_update = false; 328e705c121SKalle Valo } 329e705c121SKalle Valo spin_unlock_bh(&txq->lock); 330e705c121SKalle Valo } 331e705c121SKalle Valo } 332e705c121SKalle Valo 3336983ba69SSara Sharon static inline void *iwl_pcie_get_tfd(struct iwl_trans_pcie *trans_pcie, 3346983ba69SSara Sharon struct iwl_txq *txq, int idx) 335e705c121SKalle Valo { 3366983ba69SSara Sharon return txq->tfds + trans_pcie->tfd_size * idx; 3376983ba69SSara Sharon } 338e705c121SKalle Valo 3396983ba69SSara Sharon static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 3406983ba69SSara Sharon void *tfd, u8 idx) 3416983ba69SSara Sharon { 3426983ba69SSara Sharon struct iwl_tfd *tfd_fh; 3436983ba69SSara Sharon struct iwl_tfd_tb *tb; 3446983ba69SSara Sharon dma_addr_t addr; 3456983ba69SSara Sharon 3466983ba69SSara Sharon if (trans->cfg->use_tfh) { 3476983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 3486983ba69SSara Sharon struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx]; 3496983ba69SSara Sharon 3506983ba69SSara Sharon return (dma_addr_t)(le64_to_cpu(tb->addr)); 3516983ba69SSara Sharon } 3526983ba69SSara Sharon 3536983ba69SSara Sharon tfd_fh = (void *)tfd; 3546983ba69SSara Sharon tb = &tfd_fh->tbs[idx]; 3556983ba69SSara Sharon addr = get_unaligned_le32(&tb->lo); 3566983ba69SSara Sharon 357e705c121SKalle Valo if (sizeof(dma_addr_t) > sizeof(u32)) 358e705c121SKalle Valo addr |= 359e705c121SKalle Valo ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; 360e705c121SKalle Valo 361e705c121SKalle Valo return addr; 362e705c121SKalle Valo } 363e705c121SKalle Valo 3646983ba69SSara Sharon static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 3656983ba69SSara Sharon u8 idx, dma_addr_t addr, u16 len) 366e705c121SKalle Valo { 3676983ba69SSara Sharon if (trans->cfg->use_tfh) { 3686983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 3696983ba69SSara Sharon struct iwl_tfh_tb *tb = &tfd_fh->tbs[idx]; 3706983ba69SSara Sharon 3716983ba69SSara Sharon put_unaligned_le64(addr, &tb->addr); 3726983ba69SSara Sharon tb->tb_len = cpu_to_le16(len); 3736983ba69SSara Sharon 3746983ba69SSara Sharon tfd_fh->num_tbs = cpu_to_le16(idx + 1); 3756983ba69SSara Sharon } else { 3766983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 3776983ba69SSara Sharon struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 3786983ba69SSara Sharon 379e705c121SKalle Valo u16 hi_n_len = len << 4; 380e705c121SKalle Valo 381e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 382e705c121SKalle Valo if (sizeof(dma_addr_t) > sizeof(u32)) 383e705c121SKalle Valo hi_n_len |= ((addr >> 16) >> 16) & 0xF; 384e705c121SKalle Valo 385e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 386e705c121SKalle Valo 3876983ba69SSara Sharon tfd_fh->num_tbs = idx + 1; 3886983ba69SSara Sharon } 389e705c121SKalle Valo } 390e705c121SKalle Valo 3916983ba69SSara Sharon static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *tfd) 392e705c121SKalle Valo { 3936983ba69SSara Sharon struct iwl_tfd *tfd_fh; 3946983ba69SSara Sharon 3956983ba69SSara Sharon if (trans->cfg->use_tfh) { 3966983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 3976983ba69SSara Sharon 3986983ba69SSara Sharon return le16_to_cpu(tfd_fh->num_tbs) & 0x1f; 3996983ba69SSara Sharon } 4006983ba69SSara Sharon 4016983ba69SSara Sharon tfd_fh = (void *)tfd; 4026983ba69SSara Sharon return tfd_fh->num_tbs & 0x1f; 403e705c121SKalle Valo } 404e705c121SKalle Valo 405e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 406e705c121SKalle Valo struct iwl_cmd_meta *meta, 4076983ba69SSara Sharon struct iwl_txq *txq, int index) 408e705c121SKalle Valo { 4093cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4103cd1980bSSara Sharon int i, num_tbs; 4116983ba69SSara Sharon void *tfd = iwl_pcie_get_tfd(trans_pcie, txq, index); 412e705c121SKalle Valo 413e705c121SKalle Valo /* Sanity check on number of chunks */ 4146983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 415e705c121SKalle Valo 4163cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 417e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 418e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 419e705c121SKalle Valo return; 420e705c121SKalle Valo } 421e705c121SKalle Valo 4228de437c7SSara Sharon /* first TB is never freed - it's the bidirectional DMA data */ 423e705c121SKalle Valo 424e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 4253cd1980bSSara Sharon if (meta->tbs & BIT(i)) 426e705c121SKalle Valo dma_unmap_page(trans->dev, 4276983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 4286983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, i), 429e705c121SKalle Valo DMA_TO_DEVICE); 430e705c121SKalle Valo else 431e705c121SKalle Valo dma_unmap_single(trans->dev, 4326983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, 4336983ba69SSara Sharon i), 4346983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, 4356983ba69SSara Sharon i), 436e705c121SKalle Valo DMA_TO_DEVICE); 437e705c121SKalle Valo } 4386983ba69SSara Sharon 4396983ba69SSara Sharon if (trans->cfg->use_tfh) { 4406983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4416983ba69SSara Sharon 4426983ba69SSara Sharon tfd_fh->num_tbs = 0; 4436983ba69SSara Sharon } else { 4446983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 4456983ba69SSara Sharon 4466983ba69SSara Sharon tfd_fh->num_tbs = 0; 4476983ba69SSara Sharon } 4486983ba69SSara Sharon 449e705c121SKalle Valo } 450e705c121SKalle Valo 451e705c121SKalle Valo /* 452e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 453e705c121SKalle Valo * @trans - transport private data 454e705c121SKalle Valo * @txq - tx queue 455e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 456e705c121SKalle Valo * 457e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 458e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 459e705c121SKalle Valo */ 460e705c121SKalle Valo static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 461e705c121SKalle Valo { 462e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 463e705c121SKalle Valo * idx is bounded by n_window 464e705c121SKalle Valo */ 465e705c121SKalle Valo int rd_ptr = txq->q.read_ptr; 466e705c121SKalle Valo int idx = get_cmd_index(&txq->q, rd_ptr); 467e705c121SKalle Valo 468e705c121SKalle Valo lockdep_assert_held(&txq->lock); 469e705c121SKalle Valo 470e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 471e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 472e705c121SKalle Valo */ 4736983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 474e705c121SKalle Valo 475e705c121SKalle Valo /* free SKB */ 476e705c121SKalle Valo if (txq->entries) { 477e705c121SKalle Valo struct sk_buff *skb; 478e705c121SKalle Valo 479e705c121SKalle Valo skb = txq->entries[idx].skb; 480e705c121SKalle Valo 481e705c121SKalle Valo /* Can be called from irqs-disabled context 482e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 483e705c121SKalle Valo * freed and that the queue is not empty - free the skb 484e705c121SKalle Valo */ 485e705c121SKalle Valo if (skb) { 486e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 487e705c121SKalle Valo txq->entries[idx].skb = NULL; 488e705c121SKalle Valo } 489e705c121SKalle Valo } 490e705c121SKalle Valo } 491e705c121SKalle Valo 492e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 493e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 494e705c121SKalle Valo { 4953cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 496e705c121SKalle Valo struct iwl_queue *q; 4976983ba69SSara Sharon void *tfd; 498e705c121SKalle Valo u32 num_tbs; 499e705c121SKalle Valo 500e705c121SKalle Valo q = &txq->q; 5016983ba69SSara Sharon tfd = txq->tfds + trans_pcie->tfd_size * q->write_ptr; 502e705c121SKalle Valo 503e705c121SKalle Valo if (reset) 5046983ba69SSara Sharon memset(tfd, 0, trans_pcie->tfd_size); 505e705c121SKalle Valo 5066983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 507e705c121SKalle Valo 5086983ba69SSara Sharon /* Each TFD can point to a maximum max_tbs Tx buffers */ 5093cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 510e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 5113cd1980bSSara Sharon trans_pcie->max_tbs); 512e705c121SKalle Valo return -EINVAL; 513e705c121SKalle Valo } 514e705c121SKalle Valo 515e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 516e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 517e705c121SKalle Valo return -EINVAL; 518e705c121SKalle Valo 5196983ba69SSara Sharon iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 520e705c121SKalle Valo 521e705c121SKalle Valo return num_tbs; 522e705c121SKalle Valo } 523e705c121SKalle Valo 524e705c121SKalle Valo static int iwl_pcie_txq_alloc(struct iwl_trans *trans, 525e705c121SKalle Valo struct iwl_txq *txq, int slots_num, 526e705c121SKalle Valo u32 txq_id) 527e705c121SKalle Valo { 528e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5296983ba69SSara Sharon size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX; 5308de437c7SSara Sharon size_t tb0_buf_sz; 531e705c121SKalle Valo int i; 532e705c121SKalle Valo 533e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 534e705c121SKalle Valo return -EINVAL; 535e705c121SKalle Valo 536e705c121SKalle Valo setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 537e705c121SKalle Valo (unsigned long)txq); 538e705c121SKalle Valo txq->trans_pcie = trans_pcie; 539e705c121SKalle Valo 540e705c121SKalle Valo txq->q.n_window = slots_num; 541e705c121SKalle Valo 542e705c121SKalle Valo txq->entries = kcalloc(slots_num, 543e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 544e705c121SKalle Valo GFP_KERNEL); 545e705c121SKalle Valo 546e705c121SKalle Valo if (!txq->entries) 547e705c121SKalle Valo goto error; 548e705c121SKalle Valo 549e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 550e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 551e705c121SKalle Valo txq->entries[i].cmd = 552e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 553e705c121SKalle Valo GFP_KERNEL); 554e705c121SKalle Valo if (!txq->entries[i].cmd) 555e705c121SKalle Valo goto error; 556e705c121SKalle Valo } 557e705c121SKalle Valo 558e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 559e705c121SKalle Valo * shared with device */ 560e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 561e705c121SKalle Valo &txq->q.dma_addr, GFP_KERNEL); 562e705c121SKalle Valo if (!txq->tfds) 563e705c121SKalle Valo goto error; 564e705c121SKalle Valo 5658de437c7SSara Sharon BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 566e705c121SKalle Valo 5678de437c7SSara Sharon tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 568e705c121SKalle Valo 5698de437c7SSara Sharon txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 5708de437c7SSara Sharon &txq->first_tb_dma, 571e705c121SKalle Valo GFP_KERNEL); 5728de437c7SSara Sharon if (!txq->first_tb_bufs) 573e705c121SKalle Valo goto err_free_tfds; 574e705c121SKalle Valo 575e705c121SKalle Valo txq->q.id = txq_id; 576e705c121SKalle Valo 577e705c121SKalle Valo return 0; 578e705c121SKalle Valo err_free_tfds: 579e705c121SKalle Valo dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); 580e705c121SKalle Valo error: 581e705c121SKalle Valo if (txq->entries && txq_id == trans_pcie->cmd_queue) 582e705c121SKalle Valo for (i = 0; i < slots_num; i++) 583e705c121SKalle Valo kfree(txq->entries[i].cmd); 584e705c121SKalle Valo kfree(txq->entries); 585e705c121SKalle Valo txq->entries = NULL; 586e705c121SKalle Valo 587e705c121SKalle Valo return -ENOMEM; 588e705c121SKalle Valo 589e705c121SKalle Valo } 590e705c121SKalle Valo 591e705c121SKalle Valo static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 592e705c121SKalle Valo int slots_num, u32 txq_id) 593e705c121SKalle Valo { 594e705c121SKalle Valo int ret; 595e705c121SKalle Valo 596e705c121SKalle Valo txq->need_update = false; 597e705c121SKalle Valo 598e705c121SKalle Valo /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise 599e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 600e705c121SKalle Valo BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); 601e705c121SKalle Valo 602e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 603e705c121SKalle Valo ret = iwl_queue_init(&txq->q, slots_num, txq_id); 604e705c121SKalle Valo if (ret) 605e705c121SKalle Valo return ret; 606e705c121SKalle Valo 607e705c121SKalle Valo spin_lock_init(&txq->lock); 6083955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 609e705c121SKalle Valo 610e705c121SKalle Valo /* 611e705c121SKalle Valo * Tell nic where to find circular buffer of Tx Frame Descriptors for 612e705c121SKalle Valo * given Tx queue, and enable the DMA channel used for that queue. 613e705c121SKalle Valo * Circular buffer (TFD queue in DRAM) physical base address */ 614e22744afSSara Sharon if (trans->cfg->use_tfh) 615e22744afSSara Sharon iwl_write_direct64(trans, 616e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 617e22744afSSara Sharon txq->q.dma_addr); 618e22744afSSara Sharon else 619e22744afSSara Sharon iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 620e705c121SKalle Valo txq->q.dma_addr >> 8); 621e705c121SKalle Valo 622e705c121SKalle Valo return 0; 623e705c121SKalle Valo } 624e705c121SKalle Valo 62521cb3222SJohannes Berg static void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 62621cb3222SJohannes Berg struct sk_buff *skb) 6276eb5e529SEmmanuel Grumbach { 62821cb3222SJohannes Berg struct page **page_ptr; 6296eb5e529SEmmanuel Grumbach 63021cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 6316eb5e529SEmmanuel Grumbach 63221cb3222SJohannes Berg if (*page_ptr) { 63321cb3222SJohannes Berg __free_page(*page_ptr); 63421cb3222SJohannes Berg *page_ptr = NULL; 6356eb5e529SEmmanuel Grumbach } 6366eb5e529SEmmanuel Grumbach } 6376eb5e529SEmmanuel Grumbach 63801d11cd1SSara Sharon static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 63901d11cd1SSara Sharon { 64001d11cd1SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 64101d11cd1SSara Sharon 64201d11cd1SSara Sharon lockdep_assert_held(&trans_pcie->reg_lock); 64301d11cd1SSara Sharon 64401d11cd1SSara Sharon if (trans_pcie->ref_cmd_in_flight) { 64501d11cd1SSara Sharon trans_pcie->ref_cmd_in_flight = false; 64601d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 647c24c7f58SLuca Coelho iwl_trans_unref(trans); 64801d11cd1SSara Sharon } 64901d11cd1SSara Sharon 65001d11cd1SSara Sharon if (!trans->cfg->base_params->apmg_wake_up_wa) 65101d11cd1SSara Sharon return; 65201d11cd1SSara Sharon if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 65301d11cd1SSara Sharon return; 65401d11cd1SSara Sharon 65501d11cd1SSara Sharon trans_pcie->cmd_hold_nic_awake = false; 65601d11cd1SSara Sharon __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 65701d11cd1SSara Sharon CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 65801d11cd1SSara Sharon } 65901d11cd1SSara Sharon 660e705c121SKalle Valo /* 661e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 662e705c121SKalle Valo */ 663e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 664e705c121SKalle Valo { 665e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 666e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 667e705c121SKalle Valo struct iwl_queue *q = &txq->q; 668e705c121SKalle Valo 669e705c121SKalle Valo spin_lock_bh(&txq->lock); 670e705c121SKalle Valo while (q->write_ptr != q->read_ptr) { 671e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 672e705c121SKalle Valo txq_id, q->read_ptr); 6736eb5e529SEmmanuel Grumbach 6746eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 6756eb5e529SEmmanuel Grumbach struct sk_buff *skb = txq->entries[q->read_ptr].skb; 6766eb5e529SEmmanuel Grumbach 6776eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6786eb5e529SEmmanuel Grumbach continue; 6796eb5e529SEmmanuel Grumbach 68021cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 6816eb5e529SEmmanuel Grumbach } 682e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 683e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr); 68401d11cd1SSara Sharon 68501d11cd1SSara Sharon if (q->read_ptr == q->write_ptr) { 68601d11cd1SSara Sharon unsigned long flags; 68701d11cd1SSara Sharon 68801d11cd1SSara Sharon spin_lock_irqsave(&trans_pcie->reg_lock, flags); 68901d11cd1SSara Sharon if (txq_id != trans_pcie->cmd_queue) { 69001d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 69101d11cd1SSara Sharon q->id); 692c24c7f58SLuca Coelho iwl_trans_unref(trans); 69301d11cd1SSara Sharon } else { 69401d11cd1SSara Sharon iwl_pcie_clear_cmd_in_flight(trans); 69501d11cd1SSara Sharon } 69601d11cd1SSara Sharon spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 69701d11cd1SSara Sharon } 698e705c121SKalle Valo } 699e705c121SKalle Valo txq->active = false; 7003955525dSEmmanuel Grumbach 7013955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 7023955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 7033955525dSEmmanuel Grumbach 7043955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 7053955525dSEmmanuel Grumbach } 7063955525dSEmmanuel Grumbach 707e705c121SKalle Valo spin_unlock_bh(&txq->lock); 708e705c121SKalle Valo 709e705c121SKalle Valo /* just in case - this queue may have been stopped */ 710e705c121SKalle Valo iwl_wake_queue(trans, txq); 711e705c121SKalle Valo } 712e705c121SKalle Valo 713e705c121SKalle Valo /* 714e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 715e705c121SKalle Valo * @txq: Transmit queue to deallocate. 716e705c121SKalle Valo * 717e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 718e705c121SKalle Valo * Free all buffers. 719e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 720e705c121SKalle Valo */ 721e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 722e705c121SKalle Valo { 723e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 725e705c121SKalle Valo struct device *dev = trans->dev; 726e705c121SKalle Valo int i; 727e705c121SKalle Valo 728e705c121SKalle Valo if (WARN_ON(!txq)) 729e705c121SKalle Valo return; 730e705c121SKalle Valo 731e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 732e705c121SKalle Valo 733e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 734e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 735e705c121SKalle Valo for (i = 0; i < txq->q.n_window; i++) { 736e705c121SKalle Valo kzfree(txq->entries[i].cmd); 737e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 738e705c121SKalle Valo } 739e705c121SKalle Valo 740e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 741e705c121SKalle Valo if (txq->tfds) { 742e705c121SKalle Valo dma_free_coherent(dev, 7436983ba69SSara Sharon trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX, 744e705c121SKalle Valo txq->tfds, txq->q.dma_addr); 745e705c121SKalle Valo txq->q.dma_addr = 0; 746e705c121SKalle Valo txq->tfds = NULL; 747e705c121SKalle Valo 748e705c121SKalle Valo dma_free_coherent(dev, 7498de437c7SSara Sharon sizeof(*txq->first_tb_bufs) * txq->q.n_window, 7508de437c7SSara Sharon txq->first_tb_bufs, txq->first_tb_dma); 751e705c121SKalle Valo } 752e705c121SKalle Valo 753e705c121SKalle Valo kfree(txq->entries); 754e705c121SKalle Valo txq->entries = NULL; 755e705c121SKalle Valo 756e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 757e705c121SKalle Valo 758e705c121SKalle Valo /* 0-fill queue descriptor structure */ 759e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 760e705c121SKalle Valo } 761e705c121SKalle Valo 762e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 763e705c121SKalle Valo { 764e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 765e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 766e705c121SKalle Valo int chan; 767e705c121SKalle Valo u32 reg_val; 768e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 769e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 770e705c121SKalle Valo 771e705c121SKalle Valo /* make sure all queue are not stopped/used */ 772e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 773e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 774e705c121SKalle Valo 775ae79785fSSara Sharon if (trans->cfg->use_tfh) 776ae79785fSSara Sharon return; 777ae79785fSSara Sharon 778e705c121SKalle Valo trans_pcie->scd_base_addr = 779e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 780e705c121SKalle Valo 781e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 782e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 783e705c121SKalle Valo 784e705c121SKalle Valo /* reset context data, TX status and translation data */ 785e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 786e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 787e705c121SKalle Valo NULL, clear_dwords); 788e705c121SKalle Valo 789e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 790e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 791e705c121SKalle Valo 792e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 793e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 794e705c121SKalle Valo */ 795e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 796e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 797e705c121SKalle Valo 798e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 799e705c121SKalle Valo trans_pcie->cmd_fifo, 800e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 801e705c121SKalle Valo 802e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 803e705c121SKalle Valo iwl_scd_activate_fifos(trans); 804e705c121SKalle Valo 805e705c121SKalle Valo /* Enable DMA channel */ 806e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 807e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 808e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 809e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 810e705c121SKalle Valo 811e705c121SKalle Valo /* Update FH chicken bits */ 812e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 813e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 814e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 815e705c121SKalle Valo 816e705c121SKalle Valo /* Enable L1-Active */ 817e705c121SKalle Valo if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 818e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 819e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 820e705c121SKalle Valo } 821e705c121SKalle Valo 822e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 823e705c121SKalle Valo { 824e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 825e705c121SKalle Valo int txq_id; 826e705c121SKalle Valo 827e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 828e705c121SKalle Valo txq_id++) { 829e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 830e22744afSSara Sharon if (trans->cfg->use_tfh) 831e22744afSSara Sharon iwl_write_direct64(trans, 832e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 833e22744afSSara Sharon txq->q.dma_addr); 834e22744afSSara Sharon else 835e22744afSSara Sharon iwl_write_direct32(trans, 836e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 837e705c121SKalle Valo txq->q.dma_addr >> 8); 838e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 839e705c121SKalle Valo txq->q.read_ptr = 0; 840e705c121SKalle Valo txq->q.write_ptr = 0; 841e705c121SKalle Valo } 842e705c121SKalle Valo 843e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 844e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 845e705c121SKalle Valo trans_pcie->kw.dma >> 4); 846e705c121SKalle Valo 847e705c121SKalle Valo /* 848e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 849e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 850e705c121SKalle Valo * contain garbage. 851e705c121SKalle Valo */ 852e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 853e705c121SKalle Valo } 854e705c121SKalle Valo 855e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 856e705c121SKalle Valo { 857e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 858e705c121SKalle Valo unsigned long flags; 859e705c121SKalle Valo int ch, ret; 860e705c121SKalle Valo u32 mask = 0; 861e705c121SKalle Valo 862e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 863e705c121SKalle Valo 86423ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 865e705c121SKalle Valo goto out; 866e705c121SKalle Valo 867e705c121SKalle Valo /* Stop each Tx DMA channel */ 868e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 869e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 870e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 871e705c121SKalle Valo } 872e705c121SKalle Valo 873e705c121SKalle Valo /* Wait for DMA channels to be idle */ 874e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 875e705c121SKalle Valo if (ret < 0) 876e705c121SKalle Valo IWL_ERR(trans, 877e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 878e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 879e705c121SKalle Valo 880e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 881e705c121SKalle Valo 882e705c121SKalle Valo out: 883e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 884e705c121SKalle Valo } 885e705c121SKalle Valo 886e705c121SKalle Valo /* 887e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 888e705c121SKalle Valo */ 889e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 890e705c121SKalle Valo { 891e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 892e705c121SKalle Valo int txq_id; 893e705c121SKalle Valo 894e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 895e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 896e705c121SKalle Valo 897e705c121SKalle Valo /* Turn off all Tx DMA channels */ 898e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 899e705c121SKalle Valo 900e705c121SKalle Valo /* 901e705c121SKalle Valo * This function can be called before the op_mode disabled the 902e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 903e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 904e705c121SKalle Valo */ 905e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 906e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 907e705c121SKalle Valo 908e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 909e705c121SKalle Valo if (!trans_pcie->txq) 910e705c121SKalle Valo return 0; 911e705c121SKalle Valo 912e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 913e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 914e705c121SKalle Valo txq_id++) 915e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 916e705c121SKalle Valo 917e705c121SKalle Valo return 0; 918e705c121SKalle Valo } 919e705c121SKalle Valo 920e705c121SKalle Valo /* 921e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 922e705c121SKalle Valo * 923e705c121SKalle Valo * Destroy all TX DMA queues and structures 924e705c121SKalle Valo */ 925e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 926e705c121SKalle Valo { 927e705c121SKalle Valo int txq_id; 928e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 929e705c121SKalle Valo 930e705c121SKalle Valo /* Tx queues */ 931e705c121SKalle Valo if (trans_pcie->txq) { 932e705c121SKalle Valo for (txq_id = 0; 933e705c121SKalle Valo txq_id < trans->cfg->base_params->num_of_queues; txq_id++) 934e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 935e705c121SKalle Valo } 936e705c121SKalle Valo 937e705c121SKalle Valo kfree(trans_pcie->txq); 938e705c121SKalle Valo trans_pcie->txq = NULL; 939e705c121SKalle Valo 940e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 941e705c121SKalle Valo 942e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 943e705c121SKalle Valo } 944e705c121SKalle Valo 945e705c121SKalle Valo /* 946e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 947e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 948e705c121SKalle Valo */ 949e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 950e705c121SKalle Valo { 951e705c121SKalle Valo int ret; 952e705c121SKalle Valo int txq_id, slots_num; 953e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 954e705c121SKalle Valo 955e705c121SKalle Valo u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * 956e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 957e705c121SKalle Valo 958e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 959e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 960e705c121SKalle Valo if (WARN_ON(trans_pcie->txq)) { 961e705c121SKalle Valo ret = -EINVAL; 962e705c121SKalle Valo goto error; 963e705c121SKalle Valo } 964e705c121SKalle Valo 965e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 966e705c121SKalle Valo scd_bc_tbls_size); 967e705c121SKalle Valo if (ret) { 968e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 969e705c121SKalle Valo goto error; 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo /* Alloc keep-warm buffer */ 973e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 974e705c121SKalle Valo if (ret) { 975e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 976e705c121SKalle Valo goto error; 977e705c121SKalle Valo } 978e705c121SKalle Valo 979e705c121SKalle Valo trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, 980e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 981e705c121SKalle Valo if (!trans_pcie->txq) { 982e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 983e705c121SKalle Valo ret = -ENOMEM; 984e705c121SKalle Valo goto error; 985e705c121SKalle Valo } 986e705c121SKalle Valo 987e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 988e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 989e705c121SKalle Valo txq_id++) { 990e705c121SKalle Valo slots_num = (txq_id == trans_pcie->cmd_queue) ? 991e705c121SKalle Valo TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 992e705c121SKalle Valo ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], 993e705c121SKalle Valo slots_num, txq_id); 994e705c121SKalle Valo if (ret) { 995e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 996e705c121SKalle Valo goto error; 997e705c121SKalle Valo } 998e705c121SKalle Valo } 999e705c121SKalle Valo 1000e705c121SKalle Valo return 0; 1001e705c121SKalle Valo 1002e705c121SKalle Valo error: 1003e705c121SKalle Valo iwl_pcie_tx_free(trans); 1004e705c121SKalle Valo 1005e705c121SKalle Valo return ret; 1006e705c121SKalle Valo } 1007e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 1008e705c121SKalle Valo { 1009e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1010e705c121SKalle Valo int ret; 1011e705c121SKalle Valo int txq_id, slots_num; 1012e705c121SKalle Valo bool alloc = false; 1013e705c121SKalle Valo 1014e705c121SKalle Valo if (!trans_pcie->txq) { 1015e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 1016e705c121SKalle Valo if (ret) 1017e705c121SKalle Valo goto error; 1018e705c121SKalle Valo alloc = true; 1019e705c121SKalle Valo } 1020e705c121SKalle Valo 1021e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1022e705c121SKalle Valo 1023e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 1024e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 1025e705c121SKalle Valo 1026e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 1027e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1028e705c121SKalle Valo trans_pcie->kw.dma >> 4); 1029e705c121SKalle Valo 1030e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1031e705c121SKalle Valo 1032e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1033e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1034e705c121SKalle Valo txq_id++) { 1035e705c121SKalle Valo slots_num = (txq_id == trans_pcie->cmd_queue) ? 1036e705c121SKalle Valo TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1037e705c121SKalle Valo ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], 1038e705c121SKalle Valo slots_num, txq_id); 1039e705c121SKalle Valo if (ret) { 1040e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1041e705c121SKalle Valo goto error; 1042e705c121SKalle Valo } 1043e705c121SKalle Valo } 1044e705c121SKalle Valo 1045ae79785fSSara Sharon if (trans->cfg->use_tfh) { 1046e22744afSSara Sharon iwl_write_direct32(trans, TFH_TRANSFER_MODE, 1047e22744afSSara Sharon TFH_TRANSFER_MAX_PENDING_REQ | 1048e22744afSSara Sharon TFH_CHUNK_SIZE_128 | 1049e22744afSSara Sharon TFH_CHUNK_SPLIT_MODE); 1050ae79785fSSara Sharon return 0; 1051ae79785fSSara Sharon } 1052e22744afSSara Sharon 1053e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1054e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 1055e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 1056e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 1057e705c121SKalle Valo 1058e705c121SKalle Valo return 0; 1059e705c121SKalle Valo error: 1060e705c121SKalle Valo /*Upon error, free only if we allocated something */ 1061e705c121SKalle Valo if (alloc) 1062e705c121SKalle Valo iwl_pcie_tx_free(trans); 1063e705c121SKalle Valo return ret; 1064e705c121SKalle Valo } 1065e705c121SKalle Valo 1066e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1067e705c121SKalle Valo { 1068e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1069e705c121SKalle Valo 1070e705c121SKalle Valo if (!txq->wd_timeout) 1071e705c121SKalle Valo return; 1072e705c121SKalle Valo 1073e705c121SKalle Valo /* 1074e705c121SKalle Valo * station is asleep and we send data - that must 1075e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 1076e705c121SKalle Valo */ 1077e705c121SKalle Valo if (txq->frozen) 1078e705c121SKalle Valo return; 1079e705c121SKalle Valo 1080e705c121SKalle Valo /* 1081e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 1082e705c121SKalle Valo * since we're making progress on this queue 1083e705c121SKalle Valo */ 1084e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) 1085e705c121SKalle Valo del_timer(&txq->stuck_timer); 1086e705c121SKalle Valo else 1087e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1088e705c121SKalle Valo } 1089e705c121SKalle Valo 1090e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1091e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1092e705c121SKalle Valo struct sk_buff_head *skbs) 1093e705c121SKalle Valo { 1094e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1095e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1096e705c121SKalle Valo int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1); 1097e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1098e705c121SKalle Valo int last_to_free; 1099e705c121SKalle Valo 1100e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1101e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1102e705c121SKalle Valo return; 1103e705c121SKalle Valo 1104e705c121SKalle Valo spin_lock_bh(&txq->lock); 1105e705c121SKalle Valo 1106e705c121SKalle Valo if (!txq->active) { 1107e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1108e705c121SKalle Valo txq_id, ssn); 1109e705c121SKalle Valo goto out; 1110e705c121SKalle Valo } 1111e705c121SKalle Valo 1112e705c121SKalle Valo if (txq->q.read_ptr == tfd_num) 1113e705c121SKalle Valo goto out; 1114e705c121SKalle Valo 1115e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1116e705c121SKalle Valo txq_id, txq->q.read_ptr, tfd_num, ssn); 1117e705c121SKalle Valo 1118e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1119e705c121SKalle Valo * the last we will free. This one must be used */ 1120e705c121SKalle Valo last_to_free = iwl_queue_dec_wrap(tfd_num); 1121e705c121SKalle Valo 1122e705c121SKalle Valo if (!iwl_queue_used(q, last_to_free)) { 1123e705c121SKalle Valo IWL_ERR(trans, 1124e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 1125e705c121SKalle Valo __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX, 1126e705c121SKalle Valo q->write_ptr, q->read_ptr); 1127e705c121SKalle Valo goto out; 1128e705c121SKalle Valo } 1129e705c121SKalle Valo 1130e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1131e705c121SKalle Valo goto out; 1132e705c121SKalle Valo 1133e705c121SKalle Valo for (; 1134e705c121SKalle Valo q->read_ptr != tfd_num; 1135e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 11366eb5e529SEmmanuel Grumbach struct sk_buff *skb = txq->entries[txq->q.read_ptr].skb; 1137e705c121SKalle Valo 11386eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1139e705c121SKalle Valo continue; 1140e705c121SKalle Valo 114121cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 11426eb5e529SEmmanuel Grumbach 11436eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1144e705c121SKalle Valo 1145e705c121SKalle Valo txq->entries[txq->q.read_ptr].skb = NULL; 1146e705c121SKalle Valo 11474fe10bc6SSara Sharon if (!trans->cfg->use_tfh) 1148e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1149e705c121SKalle Valo 1150e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1151e705c121SKalle Valo } 1152e705c121SKalle Valo 1153e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1154e705c121SKalle Valo 11553955525dSEmmanuel Grumbach if (iwl_queue_space(&txq->q) > txq->q.low_mark && 11563955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1157685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 11583955525dSEmmanuel Grumbach 1159685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1160685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 11613955525dSEmmanuel Grumbach 11623955525dSEmmanuel Grumbach /* 11633955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 11643955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 11653955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 11663955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 11673955525dSEmmanuel Grumbach * later. 11683955525dSEmmanuel Grumbach */ 11693955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 11703955525dSEmmanuel Grumbach 1171685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1172685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 117321cb3222SJohannes Berg struct iwl_device_cmd *dev_cmd_ptr; 117421cb3222SJohannes Berg 117521cb3222SJohannes Berg dev_cmd_ptr = *(void **)((u8 *)skb->cb + 117621cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 11773955525dSEmmanuel Grumbach 11783955525dSEmmanuel Grumbach /* 11793955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 11803955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 11813955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 11823955525dSEmmanuel Grumbach */ 118321cb3222SJohannes Berg iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id); 11843955525dSEmmanuel Grumbach } 11853955525dSEmmanuel Grumbach spin_lock_bh(&txq->lock); 11863955525dSEmmanuel Grumbach 1187e705c121SKalle Valo if (iwl_queue_space(&txq->q) > txq->q.low_mark) 1188e705c121SKalle Valo iwl_wake_queue(trans, txq); 11893955525dSEmmanuel Grumbach } 1190e705c121SKalle Valo 1191e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 1192e705c121SKalle Valo IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id); 1193c24c7f58SLuca Coelho iwl_trans_unref(trans); 1194e705c121SKalle Valo } 1195e705c121SKalle Valo 1196e705c121SKalle Valo out: 1197e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1198e705c121SKalle Valo } 1199e705c121SKalle Valo 1200e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1201e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1202e705c121SKalle Valo { 1203e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1204e705c121SKalle Valo int ret; 1205e705c121SKalle Valo 1206e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1207e705c121SKalle Valo 1208e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1209e705c121SKalle Valo !trans_pcie->ref_cmd_in_flight) { 1210e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = true; 1211e705c121SKalle Valo IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1212c24c7f58SLuca Coelho iwl_trans_ref(trans); 1213e705c121SKalle Valo } 1214e705c121SKalle Valo 1215e705c121SKalle Valo /* 1216e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1217e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1218e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1219e705c121SKalle Valo * apmg_wake_up_wa set. 1220e705c121SKalle Valo */ 1221e705c121SKalle Valo if (trans->cfg->base_params->apmg_wake_up_wa && 1222e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1223e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1224e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1225e705c121SKalle Valo 1226e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1227e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1228e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1229e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1230e705c121SKalle Valo 15000); 1231e705c121SKalle Valo if (ret < 0) { 1232e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1233e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1234e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1235e705c121SKalle Valo return -EIO; 1236e705c121SKalle Valo } 1237e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1238e705c121SKalle Valo } 1239e705c121SKalle Valo 1240e705c121SKalle Valo return 0; 1241e705c121SKalle Valo } 1242e705c121SKalle Valo 1243e705c121SKalle Valo /* 1244e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1245e705c121SKalle Valo * 1246e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1247e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1248e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1249e705c121SKalle Valo */ 1250e705c121SKalle Valo static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1251e705c121SKalle Valo { 1252e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1253e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1254e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1255e705c121SKalle Valo unsigned long flags; 1256e705c121SKalle Valo int nfreed = 0; 1257e705c121SKalle Valo 1258e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1259e705c121SKalle Valo 1260e705c121SKalle Valo if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) { 1261e705c121SKalle Valo IWL_ERR(trans, 1262e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 1263e705c121SKalle Valo __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX, 1264e705c121SKalle Valo q->write_ptr, q->read_ptr); 1265e705c121SKalle Valo return; 1266e705c121SKalle Valo } 1267e705c121SKalle Valo 1268e705c121SKalle Valo for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx; 1269e705c121SKalle Valo q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) { 1270e705c121SKalle Valo 1271e705c121SKalle Valo if (nfreed++ > 0) { 1272e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1273e705c121SKalle Valo idx, q->write_ptr, q->read_ptr); 1274e705c121SKalle Valo iwl_force_nmi(trans); 1275e705c121SKalle Valo } 1276e705c121SKalle Valo } 1277e705c121SKalle Valo 1278e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 1279e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1280e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1281e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1282e705c121SKalle Valo } 1283e705c121SKalle Valo 1284e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1285e705c121SKalle Valo } 1286e705c121SKalle Valo 1287e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1288e705c121SKalle Valo u16 txq_id) 1289e705c121SKalle Valo { 1290e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1291e705c121SKalle Valo u32 tbl_dw_addr; 1292e705c121SKalle Valo u32 tbl_dw; 1293e705c121SKalle Valo u16 scd_q2ratid; 1294e705c121SKalle Valo 1295e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1296e705c121SKalle Valo 1297e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1298e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1299e705c121SKalle Valo 1300e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1301e705c121SKalle Valo 1302e705c121SKalle Valo if (txq_id & 0x1) 1303e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1304e705c121SKalle Valo else 1305e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1306e705c121SKalle Valo 1307e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1308e705c121SKalle Valo 1309e705c121SKalle Valo return 0; 1310e705c121SKalle Valo } 1311e705c121SKalle Valo 1312e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1313e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1314e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1315e705c121SKalle Valo 1316e705c121SKalle Valo void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1317e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1318e705c121SKalle Valo unsigned int wdg_timeout) 1319e705c121SKalle Valo { 1320e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1321e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 1322e705c121SKalle Valo int fifo = -1; 1323e705c121SKalle Valo 1324e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1325e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1326e705c121SKalle Valo 1327ae79785fSSara Sharon if (cfg && trans->cfg->use_tfh) 1328ae79785fSSara Sharon WARN_ONCE(1, "Expected no calls to SCD configuration"); 1329ae79785fSSara Sharon 1330e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1331e705c121SKalle Valo 1332e705c121SKalle Valo if (cfg) { 1333e705c121SKalle Valo fifo = cfg->fifo; 1334e705c121SKalle Valo 1335e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1336e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1337e705c121SKalle Valo trans_pcie->scd_set_active) 1338e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1339e705c121SKalle Valo 1340e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1341e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1342e705c121SKalle Valo 1343e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1344e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1345e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1346e705c121SKalle Valo 1347e705c121SKalle Valo if (cfg->aggregate) { 1348e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1349e705c121SKalle Valo 1350e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1351e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1352e705c121SKalle Valo 1353e705c121SKalle Valo /* enable aggregations for the queue */ 1354e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1355e705c121SKalle Valo txq->ampdu = true; 1356e705c121SKalle Valo } else { 1357e705c121SKalle Valo /* 1358e705c121SKalle Valo * disable aggregations for the queue, this will also 1359e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1360e705c121SKalle Valo * since it is now a non-AGG queue. 1361e705c121SKalle Valo */ 1362e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1363e705c121SKalle Valo 1364e705c121SKalle Valo ssn = txq->q.read_ptr; 1365e705c121SKalle Valo } 1366e705c121SKalle Valo } 1367e705c121SKalle Valo 1368e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1369e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1370e705c121SKalle Valo txq->q.read_ptr = (ssn & 0xff); 1371e705c121SKalle Valo txq->q.write_ptr = (ssn & 0xff); 1372e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1373e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1374e705c121SKalle Valo 1375e705c121SKalle Valo if (cfg) { 1376e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1377e705c121SKalle Valo 1378e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1379e705c121SKalle Valo 1380e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1381e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1382e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1383e705c121SKalle Valo iwl_trans_write_mem32(trans, 1384e705c121SKalle Valo trans_pcie->scd_base_addr + 1385e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1386e705c121SKalle Valo ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & 1387e705c121SKalle Valo SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | 1388e705c121SKalle Valo ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 1389e705c121SKalle Valo SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); 1390e705c121SKalle Valo 1391e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1392e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1393e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1394e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1395e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1396e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1397e705c121SKalle Valo 1398e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1399e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1400e705c121SKalle Valo trans_pcie->scd_set_active) 1401e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1402e705c121SKalle Valo 1403e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1404e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1405e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1406e705c121SKalle Valo } else { 1407e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1408e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1409e705c121SKalle Valo txq_id, ssn & 0xff); 1410e705c121SKalle Valo } 1411e705c121SKalle Valo 1412e705c121SKalle Valo txq->active = true; 1413e705c121SKalle Valo } 1414e705c121SKalle Valo 141542db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 141642db09c1SLiad Kaufman bool shared_mode) 141742db09c1SLiad Kaufman { 141842db09c1SLiad Kaufman struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 141942db09c1SLiad Kaufman struct iwl_txq *txq = &trans_pcie->txq[txq_id]; 142042db09c1SLiad Kaufman 142142db09c1SLiad Kaufman txq->ampdu = !shared_mode; 142242db09c1SLiad Kaufman } 142342db09c1SLiad Kaufman 14248aacf4b7SSara Sharon dma_addr_t iwl_trans_pcie_get_txq_byte_table(struct iwl_trans *trans, int txq) 14258aacf4b7SSara Sharon { 14268aacf4b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14278aacf4b7SSara Sharon 14288aacf4b7SSara Sharon return trans_pcie->scd_bc_tbls.dma + 14298aacf4b7SSara Sharon txq * sizeof(struct iwlagn_scd_bc_tbl); 14308aacf4b7SSara Sharon } 14318aacf4b7SSara Sharon 1432e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1433e705c121SKalle Valo bool configure_scd) 1434e705c121SKalle Valo { 1435e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1436e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1437e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1438e705c121SKalle Valo static const u32 zero_val[4] = {}; 1439e705c121SKalle Valo 1440e705c121SKalle Valo trans_pcie->txq[txq_id].frozen_expiry_remainder = 0; 1441e705c121SKalle Valo trans_pcie->txq[txq_id].frozen = false; 1442e705c121SKalle Valo 1443e705c121SKalle Valo /* 1444e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1445e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1446e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1447e705c121SKalle Valo * stop_device. 1448e705c121SKalle Valo */ 1449e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1450e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1451e705c121SKalle Valo "queue %d not used", txq_id); 1452e705c121SKalle Valo return; 1453e705c121SKalle Valo } 1454e705c121SKalle Valo 1455ae79785fSSara Sharon if (configure_scd && trans->cfg->use_tfh) 1456ae79785fSSara Sharon WARN_ONCE(1, "Expected no calls to SCD configuration"); 1457ae79785fSSara Sharon 1458e705c121SKalle Valo if (configure_scd) { 1459e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1460e705c121SKalle Valo 1461e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1462e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1463e705c121SKalle Valo } 1464e705c121SKalle Valo 1465e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1466e705c121SKalle Valo trans_pcie->txq[txq_id].ampdu = false; 1467e705c121SKalle Valo 1468e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1469e705c121SKalle Valo } 1470e705c121SKalle Valo 1471e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1472e705c121SKalle Valo 1473e705c121SKalle Valo /* 1474e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1475e705c121SKalle Valo * @priv: device private data point 1476e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1477e705c121SKalle Valo * 1478e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1479e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1480e705c121SKalle Valo * command queue. 1481e705c121SKalle Valo */ 1482e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1483e705c121SKalle Valo struct iwl_host_cmd *cmd) 1484e705c121SKalle Valo { 1485e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1486e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1487e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1488e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1489e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1490e705c121SKalle Valo unsigned long flags; 1491e705c121SKalle Valo void *dup_buf = NULL; 1492e705c121SKalle Valo dma_addr_t phys_addr; 1493e705c121SKalle Valo int idx; 14948de437c7SSara Sharon u16 copy_size, cmd_size, tb0_size; 1495e705c121SKalle Valo bool had_nocopy = false; 1496e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1497e705c121SKalle Valo int i, ret; 1498e705c121SKalle Valo u32 cmd_pos; 1499e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1500e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1501e705c121SKalle Valo 1502e705c121SKalle Valo if (WARN(!trans_pcie->wide_cmd_header && 1503e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1504e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1505e705c121SKalle Valo return -EINVAL; 1506e705c121SKalle Valo 1507e705c121SKalle Valo if (group_id != 0) { 1508e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1509e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1510e705c121SKalle Valo } else { 1511e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1512e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1513e705c121SKalle Valo } 1514e705c121SKalle Valo 1515e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1516e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1517e705c121SKalle Valo 1518e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1519e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1520e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1521e705c121SKalle Valo 1522e705c121SKalle Valo if (!cmd->len[i]) 1523e705c121SKalle Valo continue; 1524e705c121SKalle Valo 15258de437c7SSara Sharon /* need at least IWL_FIRST_TB_SIZE copied */ 15268de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 15278de437c7SSara Sharon int copy = IWL_FIRST_TB_SIZE - copy_size; 1528e705c121SKalle Valo 1529e705c121SKalle Valo if (copy > cmdlen[i]) 1530e705c121SKalle Valo copy = cmdlen[i]; 1531e705c121SKalle Valo cmdlen[i] -= copy; 1532e705c121SKalle Valo cmddata[i] += copy; 1533e705c121SKalle Valo copy_size += copy; 1534e705c121SKalle Valo } 1535e705c121SKalle Valo 1536e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1537e705c121SKalle Valo had_nocopy = true; 1538e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1539e705c121SKalle Valo idx = -EINVAL; 1540e705c121SKalle Valo goto free_dup_buf; 1541e705c121SKalle Valo } 1542e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1543e705c121SKalle Valo /* 1544e705c121SKalle Valo * This is also a chunk that isn't copied 1545e705c121SKalle Valo * to the static buffer so set had_nocopy. 1546e705c121SKalle Valo */ 1547e705c121SKalle Valo had_nocopy = true; 1548e705c121SKalle Valo 1549e705c121SKalle Valo /* only allowed once */ 1550e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1551e705c121SKalle Valo idx = -EINVAL; 1552e705c121SKalle Valo goto free_dup_buf; 1553e705c121SKalle Valo } 1554e705c121SKalle Valo 1555e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1556e705c121SKalle Valo GFP_ATOMIC); 1557e705c121SKalle Valo if (!dup_buf) 1558e705c121SKalle Valo return -ENOMEM; 1559e705c121SKalle Valo } else { 1560e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1561e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1562e705c121SKalle Valo idx = -EINVAL; 1563e705c121SKalle Valo goto free_dup_buf; 1564e705c121SKalle Valo } 1565e705c121SKalle Valo copy_size += cmdlen[i]; 1566e705c121SKalle Valo } 1567e705c121SKalle Valo cmd_size += cmd->len[i]; 1568e705c121SKalle Valo } 1569e705c121SKalle Valo 1570e705c121SKalle Valo /* 1571e705c121SKalle Valo * If any of the command structures end up being larger than 1572e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1573e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1574e705c121SKalle Valo * increase the size of the buffers. 1575e705c121SKalle Valo */ 1576e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1577e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 157839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 157939bdb17eSSharon Dvir cmd->id, copy_size)) { 1580e705c121SKalle Valo idx = -EINVAL; 1581e705c121SKalle Valo goto free_dup_buf; 1582e705c121SKalle Valo } 1583e705c121SKalle Valo 1584e705c121SKalle Valo spin_lock_bh(&txq->lock); 1585e705c121SKalle Valo 1586e705c121SKalle Valo if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1587e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1588e705c121SKalle Valo 1589e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1590e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1591e705c121SKalle Valo idx = -ENOSPC; 1592e705c121SKalle Valo goto free_dup_buf; 1593e705c121SKalle Valo } 1594e705c121SKalle Valo 1595e705c121SKalle Valo idx = get_cmd_index(q, q->write_ptr); 1596e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1597e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1598e705c121SKalle Valo 1599e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1600e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1601e705c121SKalle Valo out_meta->source = cmd; 1602e705c121SKalle Valo 1603e705c121SKalle Valo /* set up the header */ 1604e705c121SKalle Valo if (group_id != 0) { 1605e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1606e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1607e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1608e705c121SKalle Valo out_cmd->hdr_wide.length = 1609e705c121SKalle Valo cpu_to_le16(cmd_size - 1610e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1611e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1612e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1613e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1614e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr)); 1615e705c121SKalle Valo 1616e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1617e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1618e705c121SKalle Valo } else { 1619e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1620e705c121SKalle Valo out_cmd->hdr.sequence = 1621e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1622e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr)); 1623e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1624e705c121SKalle Valo 1625e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1626e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1627e705c121SKalle Valo } 1628e705c121SKalle Valo 1629e705c121SKalle Valo /* and copy the data that needs to be copied */ 1630e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1631e705c121SKalle Valo int copy; 1632e705c121SKalle Valo 1633e705c121SKalle Valo if (!cmd->len[i]) 1634e705c121SKalle Valo continue; 1635e705c121SKalle Valo 1636e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1637e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1638e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1639e705c121SKalle Valo copy = cmd->len[i]; 1640e705c121SKalle Valo 1641e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1642e705c121SKalle Valo cmd_pos += copy; 1643e705c121SKalle Valo copy_size += copy; 1644e705c121SKalle Valo continue; 1645e705c121SKalle Valo } 1646e705c121SKalle Valo 1647e705c121SKalle Valo /* 16488de437c7SSara Sharon * Otherwise we need at least IWL_FIRST_TB_SIZE copied 16498de437c7SSara Sharon * in total (for bi-directional DMA), but copy up to what 1650e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1651e705c121SKalle Valo */ 1652e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1653e705c121SKalle Valo 1654e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1655e705c121SKalle Valo cmd_pos += copy; 1656e705c121SKalle Valo 1657e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 16588de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 16598de437c7SSara Sharon copy = IWL_FIRST_TB_SIZE - copy_size; 1660e705c121SKalle Valo 1661e705c121SKalle Valo if (copy > cmd->len[i]) 1662e705c121SKalle Valo copy = cmd->len[i]; 1663e705c121SKalle Valo copy_size += copy; 1664e705c121SKalle Valo } 1665e705c121SKalle Valo } 1666e705c121SKalle Valo 1667e705c121SKalle Valo IWL_DEBUG_HC(trans, 1668e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 166939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1670e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1671e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1672e705c121SKalle Valo cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); 1673e705c121SKalle Valo 16748de437c7SSara Sharon /* start the TFD with the minimum copy bytes */ 16758de437c7SSara Sharon tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 16768de437c7SSara Sharon memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1677e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 16788de437c7SSara Sharon iwl_pcie_get_first_tb_dma(txq, idx), 16798de437c7SSara Sharon tb0_size, true); 1680e705c121SKalle Valo 1681e705c121SKalle Valo /* map first command fragment, if any remains */ 16828de437c7SSara Sharon if (copy_size > tb0_size) { 1683e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 16848de437c7SSara Sharon ((u8 *)&out_cmd->hdr) + tb0_size, 16858de437c7SSara Sharon copy_size - tb0_size, 1686e705c121SKalle Valo DMA_TO_DEVICE); 1687e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 16886983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, q->write_ptr); 1689e705c121SKalle Valo idx = -ENOMEM; 1690e705c121SKalle Valo goto out; 1691e705c121SKalle Valo } 1692e705c121SKalle Valo 1693e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 16948de437c7SSara Sharon copy_size - tb0_size, false); 1695e705c121SKalle Valo } 1696e705c121SKalle Valo 1697e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1698e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1699e705c121SKalle Valo const void *data = cmddata[i]; 1700e705c121SKalle Valo 1701e705c121SKalle Valo if (!cmdlen[i]) 1702e705c121SKalle Valo continue; 1703e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1704e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1705e705c121SKalle Valo continue; 1706e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1707e705c121SKalle Valo data = dup_buf; 1708e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1709e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1710e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 17116983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, q->write_ptr); 1712e705c121SKalle Valo idx = -ENOMEM; 1713e705c121SKalle Valo goto out; 1714e705c121SKalle Valo } 1715e705c121SKalle Valo 1716e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1717e705c121SKalle Valo } 1718e705c121SKalle Valo 17193cd1980bSSara Sharon BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1720e705c121SKalle Valo out_meta->flags = cmd->flags; 1721e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1722e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1723e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1724e705c121SKalle Valo 1725e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1726e705c121SKalle Valo 1727e705c121SKalle Valo /* start timer if queue currently empty */ 1728e705c121SKalle Valo if (q->read_ptr == q->write_ptr && txq->wd_timeout) 1729e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1730e705c121SKalle Valo 1731e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1732e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1733e705c121SKalle Valo if (ret < 0) { 1734e705c121SKalle Valo idx = ret; 1735e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1736e705c121SKalle Valo goto out; 1737e705c121SKalle Valo } 1738e705c121SKalle Valo 1739e705c121SKalle Valo /* Increment and update queue's write index */ 1740e705c121SKalle Valo q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 1741e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1742e705c121SKalle Valo 1743e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1744e705c121SKalle Valo 1745e705c121SKalle Valo out: 1746e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1747e705c121SKalle Valo free_dup_buf: 1748e705c121SKalle Valo if (idx < 0) 1749e705c121SKalle Valo kfree(dup_buf); 1750e705c121SKalle Valo return idx; 1751e705c121SKalle Valo } 1752e705c121SKalle Valo 1753e705c121SKalle Valo /* 1754e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1755e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1756e705c121SKalle Valo */ 1757e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1758e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1759e705c121SKalle Valo { 1760e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1761e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 176239bdb17eSSharon Dvir u8 group_id = iwl_cmd_groupid(pkt->hdr.group_id); 176339bdb17eSSharon Dvir u32 cmd_id; 1764e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1765e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1766e705c121SKalle Valo int cmd_index; 1767e705c121SKalle Valo struct iwl_device_cmd *cmd; 1768e705c121SKalle Valo struct iwl_cmd_meta *meta; 1769e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1770e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1771e705c121SKalle Valo 1772e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1773e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1774e705c121SKalle Valo * in the queue management code. */ 1775e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1776e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1777e705c121SKalle Valo txq_id, trans_pcie->cmd_queue, sequence, 1778e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, 1779e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { 1780e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1781e705c121SKalle Valo return; 1782e705c121SKalle Valo } 1783e705c121SKalle Valo 1784e705c121SKalle Valo spin_lock_bh(&txq->lock); 1785e705c121SKalle Valo 1786e705c121SKalle Valo cmd_index = get_cmd_index(&txq->q, index); 1787e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1788e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 178939bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1790e705c121SKalle Valo 17916983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, meta, txq, index); 1792e705c121SKalle Valo 1793e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1794e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1795e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1796e705c121SKalle Valo 1797e705c121SKalle Valo meta->source->resp_pkt = pkt; 1798e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1799e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1800e705c121SKalle Valo } 1801e705c121SKalle Valo 1802dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1803dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1804dcbb4746SEmmanuel Grumbach 1805e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1806e705c121SKalle Valo 1807e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1808e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1809e705c121SKalle Valo IWL_WARN(trans, 1810e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 181139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1812e705c121SKalle Valo } 1813e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1814e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 181539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1816e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1817e705c121SKalle Valo } 1818e705c121SKalle Valo 18194cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 18204cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 18214cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18224cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 18234cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18244cbb8e50SLuciano Coelho } 18254cbb8e50SLuciano Coelho 18264cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 18274cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 18284cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18294cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 18304cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18314cbb8e50SLuciano Coelho } 18324cbb8e50SLuciano Coelho 1833e705c121SKalle Valo meta->flags = 0; 1834e705c121SKalle Valo 1835e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1836e705c121SKalle Valo } 1837e705c121SKalle Valo 1838e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1839e705c121SKalle Valo 1840e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1841e705c121SKalle Valo struct iwl_host_cmd *cmd) 1842e705c121SKalle Valo { 1843e705c121SKalle Valo int ret; 1844e705c121SKalle Valo 1845e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1846e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1847e705c121SKalle Valo return -EINVAL; 1848e705c121SKalle Valo 1849e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1850e705c121SKalle Valo if (ret < 0) { 1851e705c121SKalle Valo IWL_ERR(trans, 1852e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 185339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1854e705c121SKalle Valo return ret; 1855e705c121SKalle Valo } 1856e705c121SKalle Valo return 0; 1857e705c121SKalle Valo } 1858e705c121SKalle Valo 1859e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1860e705c121SKalle Valo struct iwl_host_cmd *cmd) 1861e705c121SKalle Valo { 1862e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1863e705c121SKalle Valo int cmd_idx; 1864e705c121SKalle Valo int ret; 1865e705c121SKalle Valo 1866e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 186739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1868e705c121SKalle Valo 1869e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1870e705c121SKalle Valo &trans->status), 1871e705c121SKalle Valo "Command %s: a command is already active!\n", 187239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1873e705c121SKalle Valo return -EIO; 1874e705c121SKalle Valo 1875e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 187639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1877e705c121SKalle Valo 187871b1230cSLuca Coelho if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 187971b1230cSLuca Coelho ret = wait_event_timeout(trans_pcie->d0i3_waitq, 188071b1230cSLuca Coelho pm_runtime_active(&trans_pcie->pci_dev->dev), 188171b1230cSLuca Coelho msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 188271b1230cSLuca Coelho if (!ret) { 188371b1230cSLuca Coelho IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 188471b1230cSLuca Coelho return -ETIMEDOUT; 188571b1230cSLuca Coelho } 188671b1230cSLuca Coelho } 188771b1230cSLuca Coelho 1888e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1889e705c121SKalle Valo if (cmd_idx < 0) { 1890e705c121SKalle Valo ret = cmd_idx; 1891e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1892e705c121SKalle Valo IWL_ERR(trans, 1893e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 189439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1895e705c121SKalle Valo return ret; 1896e705c121SKalle Valo } 1897e705c121SKalle Valo 1898e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1899e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1900e705c121SKalle Valo &trans->status), 1901e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1902e705c121SKalle Valo if (!ret) { 1903e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; 1904e705c121SKalle Valo struct iwl_queue *q = &txq->q; 1905e705c121SKalle Valo 1906e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 190739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1908e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1909e705c121SKalle Valo 1910e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1911e705c121SKalle Valo q->read_ptr, q->write_ptr); 1912e705c121SKalle Valo 1913e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1914e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 191539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1916e705c121SKalle Valo ret = -ETIMEDOUT; 1917e705c121SKalle Valo 1918e705c121SKalle Valo iwl_force_nmi(trans); 1919e705c121SKalle Valo iwl_trans_fw_error(trans); 1920e705c121SKalle Valo 1921e705c121SKalle Valo goto cancel; 1922e705c121SKalle Valo } 1923e705c121SKalle Valo 1924e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 1925e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 192639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1927e705c121SKalle Valo dump_stack(); 1928e705c121SKalle Valo ret = -EIO; 1929e705c121SKalle Valo goto cancel; 1930e705c121SKalle Valo } 1931e705c121SKalle Valo 1932e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1933e705c121SKalle Valo test_bit(STATUS_RFKILL, &trans->status)) { 1934e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1935e705c121SKalle Valo ret = -ERFKILL; 1936e705c121SKalle Valo goto cancel; 1937e705c121SKalle Valo } 1938e705c121SKalle Valo 1939e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1940e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 194139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1942e705c121SKalle Valo ret = -EIO; 1943e705c121SKalle Valo goto cancel; 1944e705c121SKalle Valo } 1945e705c121SKalle Valo 1946e705c121SKalle Valo return 0; 1947e705c121SKalle Valo 1948e705c121SKalle Valo cancel: 1949e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1950e705c121SKalle Valo /* 1951e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1952e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1953e705c121SKalle Valo * in later, it will possibly set an invalid 1954e705c121SKalle Valo * address (cmd->meta.source). 1955e705c121SKalle Valo */ 1956e705c121SKalle Valo trans_pcie->txq[trans_pcie->cmd_queue]. 1957e705c121SKalle Valo entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1958e705c121SKalle Valo } 1959e705c121SKalle Valo 1960e705c121SKalle Valo if (cmd->resp_pkt) { 1961e705c121SKalle Valo iwl_free_resp(cmd); 1962e705c121SKalle Valo cmd->resp_pkt = NULL; 1963e705c121SKalle Valo } 1964e705c121SKalle Valo 1965e705c121SKalle Valo return ret; 1966e705c121SKalle Valo } 1967e705c121SKalle Valo 1968e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1969e705c121SKalle Valo { 1970e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1971e705c121SKalle Valo test_bit(STATUS_RFKILL, &trans->status)) { 1972e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1973e705c121SKalle Valo cmd->id); 1974e705c121SKalle Valo return -ERFKILL; 1975e705c121SKalle Valo } 1976e705c121SKalle Valo 1977e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 1978e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 1979e705c121SKalle Valo 1980e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 1981e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 1982e705c121SKalle Valo } 1983e705c121SKalle Valo 19843a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 19853a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 19863a0b2a42SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 19873a0b2a42SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 19883a0b2a42SEmmanuel Grumbach { 19896983ba69SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19903a0b2a42SEmmanuel Grumbach struct iwl_queue *q = &txq->q; 19913a0b2a42SEmmanuel Grumbach u16 tb2_len; 19923a0b2a42SEmmanuel Grumbach int i; 19933a0b2a42SEmmanuel Grumbach 19943a0b2a42SEmmanuel Grumbach /* 19953a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 19963a0b2a42SEmmanuel Grumbach * of skb's head, if any 19973a0b2a42SEmmanuel Grumbach */ 19983a0b2a42SEmmanuel Grumbach tb2_len = skb_headlen(skb) - hdr_len; 19993a0b2a42SEmmanuel Grumbach 20003a0b2a42SEmmanuel Grumbach if (tb2_len > 0) { 20013a0b2a42SEmmanuel Grumbach dma_addr_t tb2_phys = dma_map_single(trans->dev, 20023a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 20033a0b2a42SEmmanuel Grumbach tb2_len, DMA_TO_DEVICE); 20043a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 20056983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, q->write_ptr); 20063a0b2a42SEmmanuel Grumbach return -EINVAL; 20073a0b2a42SEmmanuel Grumbach } 20083a0b2a42SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 20093a0b2a42SEmmanuel Grumbach } 20103a0b2a42SEmmanuel Grumbach 20113a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 20123a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 20133a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 20143a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 20153a0b2a42SEmmanuel Grumbach int tb_idx; 20163a0b2a42SEmmanuel Grumbach 20173a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 20183a0b2a42SEmmanuel Grumbach continue; 20193a0b2a42SEmmanuel Grumbach 20203a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 20213a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 20223a0b2a42SEmmanuel Grumbach 20233a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 20246983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, q->write_ptr); 20253a0b2a42SEmmanuel Grumbach return -EINVAL; 20263a0b2a42SEmmanuel Grumbach } 20273a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 20283a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 20293a0b2a42SEmmanuel Grumbach 20303cd1980bSSara Sharon out_meta->tbs |= BIT(tb_idx); 20313a0b2a42SEmmanuel Grumbach } 20323a0b2a42SEmmanuel Grumbach 20333a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 20346983ba69SSara Sharon iwl_pcie_get_tfd(trans_pcie, txq, q->write_ptr), 20356983ba69SSara Sharon trans_pcie->tfd_size, 20368de437c7SSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 20373a0b2a42SEmmanuel Grumbach skb->data + hdr_len, tb2_len); 20383a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx_data(trans->dev, skb, 20393a0b2a42SEmmanuel Grumbach hdr_len, skb->len - hdr_len); 20403a0b2a42SEmmanuel Grumbach return 0; 20413a0b2a42SEmmanuel Grumbach } 20423a0b2a42SEmmanuel Grumbach 20436eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 20446eb5e529SEmmanuel Grumbach static struct iwl_tso_hdr_page * 20456eb5e529SEmmanuel Grumbach get_page_hdr(struct iwl_trans *trans, size_t len) 20466eb5e529SEmmanuel Grumbach { 20476eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20486eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 20496eb5e529SEmmanuel Grumbach 20506eb5e529SEmmanuel Grumbach if (!p->page) 20516eb5e529SEmmanuel Grumbach goto alloc; 20526eb5e529SEmmanuel Grumbach 20536eb5e529SEmmanuel Grumbach /* enough room on this page */ 20546eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 20556eb5e529SEmmanuel Grumbach return p; 20566eb5e529SEmmanuel Grumbach 20576eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 20586eb5e529SEmmanuel Grumbach __free_page(p->page); 20596eb5e529SEmmanuel Grumbach 20606eb5e529SEmmanuel Grumbach alloc: 20616eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 20626eb5e529SEmmanuel Grumbach if (!p->page) 20636eb5e529SEmmanuel Grumbach return NULL; 20646eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 20656eb5e529SEmmanuel Grumbach return p; 20666eb5e529SEmmanuel Grumbach } 20676eb5e529SEmmanuel Grumbach 20686eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 20696eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 20706eb5e529SEmmanuel Grumbach { 20716eb5e529SEmmanuel Grumbach if (ipv6) { 20726eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 20736eb5e529SEmmanuel Grumbach 20746eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 20756eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20766eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20776eb5e529SEmmanuel Grumbach } else { 20786eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 20796eb5e529SEmmanuel Grumbach 20806eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 20816eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 20826eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20836eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20846eb5e529SEmmanuel Grumbach } 20856eb5e529SEmmanuel Grumbach } 20866eb5e529SEmmanuel Grumbach 20876eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 20886eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 20896eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 20906eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 20916eb5e529SEmmanuel Grumbach { 20926eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 20936eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 20946eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 20956eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 20966eb5e529SEmmanuel Grumbach struct iwl_queue *q = &txq->q; 20976eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 20986eb5e529SEmmanuel Grumbach u8 *start_hdr; 20996eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 210021cb3222SJohannes Berg struct page **page_ptr; 21016eb5e529SEmmanuel Grumbach int ret; 21026eb5e529SEmmanuel Grumbach struct tso_t tso; 21036eb5e529SEmmanuel Grumbach 21046eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 21056eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 21066eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 21076eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 21086eb5e529SEmmanuel Grumbach 21096eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 21106983ba69SSara Sharon iwl_pcie_get_tfd(trans_pcie, txq, q->write_ptr), 21116983ba69SSara Sharon trans_pcie->tfd_size, 21128de437c7SSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 21136eb5e529SEmmanuel Grumbach NULL, 0); 21146eb5e529SEmmanuel Grumbach 21156eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 21166eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 21176eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 21186eb5e529SEmmanuel Grumbach amsdu_pad = 0; 21196eb5e529SEmmanuel Grumbach 21206eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 21216eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 21226eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 21236eb5e529SEmmanuel Grumbach 21246eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 21256eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 21266eb5e529SEmmanuel Grumbach if (!hdr_page) 21276eb5e529SEmmanuel Grumbach return -ENOMEM; 21286eb5e529SEmmanuel Grumbach 21296eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 21306eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 213121cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 213221cb3222SJohannes Berg *page_ptr = hdr_page->page; 21336eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 21346eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 21356eb5e529SEmmanuel Grumbach 21366eb5e529SEmmanuel Grumbach /* 21376eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 21386eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 21396eb5e529SEmmanuel Grumbach */ 21406eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 21416eb5e529SEmmanuel Grumbach 21426eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 21436eb5e529SEmmanuel Grumbach 21446eb5e529SEmmanuel Grumbach while (total_len) { 21456eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 21466eb5e529SEmmanuel Grumbach unsigned int data_left = 21476eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 21486eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 21496eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 21506eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 21516eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 21526eb5e529SEmmanuel Grumbach u8 *iph; 21536eb5e529SEmmanuel Grumbach 21546eb5e529SEmmanuel Grumbach total_len -= data_left; 21556eb5e529SEmmanuel Grumbach 21566eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 21576eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 21586eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 21596eb5e529SEmmanuel Grumbach data_left)) & 0x3; 21606eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 21616eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21626eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 21636eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21646eb5e529SEmmanuel Grumbach 21656eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 21666eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 21676eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 21686eb5e529SEmmanuel Grumbach 21696eb5e529SEmmanuel Grumbach /* 21706eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 21716eb5e529SEmmanuel Grumbach * as MAC header. 21726eb5e529SEmmanuel Grumbach */ 21736eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 21746eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 21756eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 21766eb5e529SEmmanuel Grumbach 21776eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 21786eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 21796eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 21806eb5e529SEmmanuel Grumbach GFP_ATOMIC); 21816eb5e529SEmmanuel Grumbach if (!csum_skb) { 21826eb5e529SEmmanuel Grumbach ret = -ENOMEM; 21836eb5e529SEmmanuel Grumbach goto out_unmap; 21846eb5e529SEmmanuel Grumbach } 21856eb5e529SEmmanuel Grumbach 21866eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 21876eb5e529SEmmanuel Grumbach skb->protocol == 21886eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 21896eb5e529SEmmanuel Grumbach data_left); 21906eb5e529SEmmanuel Grumbach 21916eb5e529SEmmanuel Grumbach memcpy(skb_put(csum_skb, tcp_hdrlen(skb)), 21926eb5e529SEmmanuel Grumbach tcph, tcp_hdrlen(skb)); 21936eb5e529SEmmanuel Grumbach skb_set_transport_header(csum_skb, 0); 21946eb5e529SEmmanuel Grumbach csum_skb->csum_start = 21956eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 21966eb5e529SEmmanuel Grumbach csum_skb->head; 21976eb5e529SEmmanuel Grumbach } 21986eb5e529SEmmanuel Grumbach 21996eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 22006eb5e529SEmmanuel Grumbach 22016eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 22026eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 22036eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22046eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 22056eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22066eb5e529SEmmanuel Grumbach ret = -EINVAL; 22076eb5e529SEmmanuel Grumbach goto out_unmap; 22086eb5e529SEmmanuel Grumbach } 22096eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 22106eb5e529SEmmanuel Grumbach hdr_tb_len, false); 22116eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 22126eb5e529SEmmanuel Grumbach hdr_tb_len); 22136eb5e529SEmmanuel Grumbach 22146eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 22156eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 22166eb5e529SEmmanuel Grumbach 22176eb5e529SEmmanuel Grumbach /* put the payload */ 22186eb5e529SEmmanuel Grumbach while (data_left) { 22196eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 22206eb5e529SEmmanuel Grumbach data_left); 22216eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 22226eb5e529SEmmanuel Grumbach 22236eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 22246eb5e529SEmmanuel Grumbach memcpy(skb_put(csum_skb, size), tso.data, size); 22256eb5e529SEmmanuel Grumbach 22266eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 22276eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 22286eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 22296eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22306eb5e529SEmmanuel Grumbach ret = -EINVAL; 22316eb5e529SEmmanuel Grumbach goto out_unmap; 22326eb5e529SEmmanuel Grumbach } 22336eb5e529SEmmanuel Grumbach 22346eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 22356eb5e529SEmmanuel Grumbach size, false); 22366eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 22376eb5e529SEmmanuel Grumbach size); 22386eb5e529SEmmanuel Grumbach 22396eb5e529SEmmanuel Grumbach data_left -= size; 22406eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 22416eb5e529SEmmanuel Grumbach } 22426eb5e529SEmmanuel Grumbach 22436eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 22446eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22456eb5e529SEmmanuel Grumbach __wsum csum; 22466eb5e529SEmmanuel Grumbach 22476eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 22486eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22496eb5e529SEmmanuel Grumbach csum_skb->len - 22506eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22516eb5e529SEmmanuel Grumbach 0); 22526eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22536eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 22546eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22556eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 22566eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 22576eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22586eb5e529SEmmanuel Grumbach } 22596eb5e529SEmmanuel Grumbach } 22606eb5e529SEmmanuel Grumbach 22616eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 22626eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 22636eb5e529SEmmanuel Grumbach 22646eb5e529SEmmanuel Grumbach return 0; 22656eb5e529SEmmanuel Grumbach 22666eb5e529SEmmanuel Grumbach out_unmap: 22676983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, q->write_ptr); 22686eb5e529SEmmanuel Grumbach return ret; 22696eb5e529SEmmanuel Grumbach } 22706eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 22716eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 22726eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 22736eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 22746eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 22756eb5e529SEmmanuel Grumbach { 22766eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 22776eb5e529SEmmanuel Grumbach WARN_ON(1); 22786eb5e529SEmmanuel Grumbach 22796eb5e529SEmmanuel Grumbach return -1; 22806eb5e529SEmmanuel Grumbach } 22816eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 22826eb5e529SEmmanuel Grumbach 2283e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2284e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2285e705c121SKalle Valo { 2286e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2287e705c121SKalle Valo struct ieee80211_hdr *hdr; 2288e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2289e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2290e705c121SKalle Valo struct iwl_txq *txq; 2291e705c121SKalle Valo struct iwl_queue *q; 2292e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2293e705c121SKalle Valo void *tb1_addr; 22944fe10bc6SSara Sharon void *tfd; 22953a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2296e705c121SKalle Valo bool wait_write_ptr; 2297e705c121SKalle Valo __le16 fc; 2298e705c121SKalle Valo u8 hdr_len; 2299e705c121SKalle Valo u16 wifi_seq; 2300c772a3d3SSara Sharon bool amsdu; 2301e705c121SKalle Valo 2302e705c121SKalle Valo txq = &trans_pcie->txq[txq_id]; 2303e705c121SKalle Valo q = &txq->q; 2304e705c121SKalle Valo 2305e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2306e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2307e705c121SKalle Valo return -EINVAL; 2308e705c121SKalle Valo 230941837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 231041837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 231141837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 231241837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 231341837ca9SEmmanuel Grumbach __wsum csum; 231441837ca9SEmmanuel Grumbach 231541837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 231641837ca9SEmmanuel Grumbach return -1; 231741837ca9SEmmanuel Grumbach 231841837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 231941837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 23203955525dSEmmanuel Grumbach 23213955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 232241837ca9SEmmanuel Grumbach } 232341837ca9SEmmanuel Grumbach 2324e705c121SKalle Valo if (skb_is_nonlinear(skb) && 23253cd1980bSSara Sharon skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2326e705c121SKalle Valo __skb_linearize(skb)) 2327e705c121SKalle Valo return -ENOMEM; 2328e705c121SKalle Valo 2329e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2330e705c121SKalle Valo * so there's no need to check if it's readable there 2331e705c121SKalle Valo */ 2332e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2333e705c121SKalle Valo fc = hdr->frame_control; 2334e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2335e705c121SKalle Valo 2336e705c121SKalle Valo spin_lock(&txq->lock); 2337e705c121SKalle Valo 23383955525dSEmmanuel Grumbach if (iwl_queue_space(q) < q->high_mark) { 23393955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 23403955525dSEmmanuel Grumbach 23413955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 23423955525dSEmmanuel Grumbach if (unlikely(iwl_queue_space(q) < 3)) { 234321cb3222SJohannes Berg struct iwl_device_cmd **dev_cmd_ptr; 23443955525dSEmmanuel Grumbach 234521cb3222SJohannes Berg dev_cmd_ptr = (void *)((u8 *)skb->cb + 234621cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 234721cb3222SJohannes Berg 234821cb3222SJohannes Berg *dev_cmd_ptr = dev_cmd; 23493955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 23503955525dSEmmanuel Grumbach 23513955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 23523955525dSEmmanuel Grumbach return 0; 23533955525dSEmmanuel Grumbach } 23543955525dSEmmanuel Grumbach } 23553955525dSEmmanuel Grumbach 2356e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2357e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2358e705c121SKalle Valo * the BA. 2359e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2360e705c121SKalle Valo */ 2361e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2362e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2363e705c121SKalle Valo (wifi_seq & 0xff) != q->write_ptr, 2364e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2365e705c121SKalle Valo txq_id, wifi_seq, q->write_ptr); 2366e705c121SKalle Valo 2367e705c121SKalle Valo /* Set up driver data for this TFD */ 2368e705c121SKalle Valo txq->entries[q->write_ptr].skb = skb; 2369e705c121SKalle Valo txq->entries[q->write_ptr].cmd = dev_cmd; 2370e705c121SKalle Valo 2371e705c121SKalle Valo dev_cmd->hdr.sequence = 2372e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2373e705c121SKalle Valo INDEX_TO_SEQ(q->write_ptr))); 2374e705c121SKalle Valo 23758de437c7SSara Sharon tb0_phys = iwl_pcie_get_first_tb_dma(txq, q->write_ptr); 2376e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2377e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2378e705c121SKalle Valo 2379e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2380e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2381e705c121SKalle Valo 2382e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2383e705c121SKalle Valo out_meta = &txq->entries[q->write_ptr].meta; 2384e705c121SKalle Valo out_meta->flags = 0; 2385e705c121SKalle Valo 2386e705c121SKalle Valo /* 2387e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2388e705c121SKalle Valo * and the 802.11 header - dword aligned size 2389e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2390e705c121SKalle Valo * setup of the first TB) 2391e705c121SKalle Valo */ 2392e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 23938de437c7SSara Sharon hdr_len - IWL_FIRST_TB_SIZE; 2394c772a3d3SSara Sharon /* do not align A-MSDU to dword as the subframe header aligns it */ 2395c772a3d3SSara Sharon amsdu = ieee80211_is_data_qos(fc) && 2396c772a3d3SSara Sharon (*ieee80211_get_qos_ctl(hdr) & 2397c772a3d3SSara Sharon IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2398c772a3d3SSara Sharon if (trans_pcie->sw_csum_tx || !amsdu) { 2399e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2400e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2401e705c121SKalle Valo if (tb1_len != len) 2402e705c121SKalle Valo tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 2403c772a3d3SSara Sharon } else { 2404c772a3d3SSara Sharon tb1_len = len; 2405c772a3d3SSara Sharon } 2406e705c121SKalle Valo 24078de437c7SSara Sharon /* The first TB points to bi-directional DMA data */ 24088de437c7SSara Sharon memcpy(&txq->first_tb_bufs[q->write_ptr], &dev_cmd->hdr, 24098de437c7SSara Sharon IWL_FIRST_TB_SIZE); 2410e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 24118de437c7SSara Sharon IWL_FIRST_TB_SIZE, true); 2412e705c121SKalle Valo 2413e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 24148de437c7SSara Sharon BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2415e705c121SKalle Valo 2416e705c121SKalle Valo /* map the data for TB1 */ 24178de437c7SSara Sharon tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2418e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2419e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2420e705c121SKalle Valo goto out_err; 2421e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2422e705c121SKalle Valo 2423c772a3d3SSara Sharon if (amsdu) { 24246eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 24256eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 24266eb5e529SEmmanuel Grumbach tb1_len))) 2427e705c121SKalle Valo goto out_err; 24286eb5e529SEmmanuel Grumbach } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 24296eb5e529SEmmanuel Grumbach out_meta, dev_cmd, tb1_len))) { 24306eb5e529SEmmanuel Grumbach goto out_err; 24316eb5e529SEmmanuel Grumbach } 2432e705c121SKalle Valo 24334fe10bc6SSara Sharon tfd = iwl_pcie_get_tfd(trans_pcie, txq, q->write_ptr); 2434e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 24354fe10bc6SSara Sharon iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 24364fe10bc6SSara Sharon iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2437e705c121SKalle Valo 2438e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2439e705c121SKalle Valo 2440e705c121SKalle Valo /* start timer if queue currently empty */ 2441e705c121SKalle Valo if (q->read_ptr == q->write_ptr) { 2442e705c121SKalle Valo if (txq->wd_timeout) { 2443e705c121SKalle Valo /* 2444e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2445e705c121SKalle Valo * set the timer in remainder so that the timer will 2446e705c121SKalle Valo * be armed with the right value when the station will 2447e705c121SKalle Valo * wake up. 2448e705c121SKalle Valo */ 2449e705c121SKalle Valo if (!txq->frozen) 2450e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2451e705c121SKalle Valo jiffies + txq->wd_timeout); 2452e705c121SKalle Valo else 2453e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2454e705c121SKalle Valo } 2455e705c121SKalle Valo IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id); 2456c24c7f58SLuca Coelho iwl_trans_ref(trans); 2457e705c121SKalle Valo } 2458e705c121SKalle Valo 2459e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 2460e705c121SKalle Valo q->write_ptr = iwl_queue_inc_wrap(q->write_ptr); 2461e705c121SKalle Valo if (!wait_write_ptr) 2462e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2463e705c121SKalle Valo 2464e705c121SKalle Valo /* 2465e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2466e705c121SKalle Valo * and we will get a TX status notification eventually. 2467e705c121SKalle Valo */ 2468e705c121SKalle Valo spin_unlock(&txq->lock); 2469e705c121SKalle Valo return 0; 2470e705c121SKalle Valo out_err: 2471e705c121SKalle Valo spin_unlock(&txq->lock); 2472e705c121SKalle Valo return -1; 2473e705c121SKalle Valo } 2474