1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 44cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 21e705c121SKalle Valo * file called LICENSE. 22e705c121SKalle Valo * 23e705c121SKalle Valo * Contact Information: 24cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 25e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26e705c121SKalle Valo * 27e705c121SKalle Valo *****************************************************************************/ 28e705c121SKalle Valo #include <linux/etherdevice.h> 296eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 30e705c121SKalle Valo #include <linux/slab.h> 31e705c121SKalle Valo #include <linux/sched.h> 3271b1230cSLuca Coelho #include <linux/pm_runtime.h> 336eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 346eb5e529SEmmanuel Grumbach #include <net/tso.h> 35e705c121SKalle Valo 36e705c121SKalle Valo #include "iwl-debug.h" 37e705c121SKalle Valo #include "iwl-csr.h" 38e705c121SKalle Valo #include "iwl-prph.h" 39e705c121SKalle Valo #include "iwl-io.h" 40e705c121SKalle Valo #include "iwl-scd.h" 41e705c121SKalle Valo #include "iwl-op-mode.h" 42e705c121SKalle Valo #include "internal.h" 43d172a5efSJohannes Berg #include "fw/api/tx.h" 44e705c121SKalle Valo 45e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 46e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 47e705c121SKalle Valo 48e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 49e705c121SKalle Valo * DMA services 50e705c121SKalle Valo * 51e705c121SKalle Valo * Theory of operation 52e705c121SKalle Valo * 53e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 54e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 55e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 56e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 57e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 58e705c121SKalle Valo * queue states. 59e705c121SKalle Valo * 60e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 61e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 62e705c121SKalle Valo * 63e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 64e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 65e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 66e705c121SKalle Valo * Tx queue resumed. 67e705c121SKalle Valo * 68e705c121SKalle Valo ***************************************************/ 69e22744afSSara Sharon 707b3e42eaSGolan Ben Ami int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q) 71e705c121SKalle Valo { 72e705c121SKalle Valo unsigned int max; 73e705c121SKalle Valo unsigned int used; 74e705c121SKalle Valo 75e705c121SKalle Valo /* 76e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 777b3e42eaSGolan Ben Ami * should always be less than max_tfd_queue_size elements in the queue. 787b3e42eaSGolan Ben Ami * If q->n_window is smaller than max_tfd_queue_size, there is no need 79e705c121SKalle Valo * to reserve any queue entries for this purpose. 80e705c121SKalle Valo */ 817b3e42eaSGolan Ben Ami if (q->n_window < trans->cfg->base_params->max_tfd_queue_size) 82e705c121SKalle Valo max = q->n_window; 83e705c121SKalle Valo else 847b3e42eaSGolan Ben Ami max = trans->cfg->base_params->max_tfd_queue_size - 1; 85e705c121SKalle Valo 86e705c121SKalle Valo /* 877b3e42eaSGolan Ben Ami * max_tfd_queue_size is a power of 2, so the following is equivalent to 887b3e42eaSGolan Ben Ami * modulo by max_tfd_queue_size and is well defined. 89e705c121SKalle Valo */ 907b3e42eaSGolan Ben Ami used = (q->write_ptr - q->read_ptr) & 917b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1); 92e705c121SKalle Valo 93e705c121SKalle Valo if (WARN_ON(used > max)) 94e705c121SKalle Valo return 0; 95e705c121SKalle Valo 96e705c121SKalle Valo return max - used; 97e705c121SKalle Valo } 98e705c121SKalle Valo 99e705c121SKalle Valo /* 100e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 101e705c121SKalle Valo */ 102b8e8d7ceSSara Sharon static int iwl_queue_init(struct iwl_txq *q, int slots_num) 103e705c121SKalle Valo { 104e705c121SKalle Valo q->n_window = slots_num; 105e705c121SKalle Valo 106e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 1074ecab561SEmmanuel Grumbach * iwl_pcie_get_cmd_index is broken. */ 108e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 109e705c121SKalle Valo return -EINVAL; 110e705c121SKalle Valo 111e705c121SKalle Valo q->low_mark = q->n_window / 4; 112e705c121SKalle Valo if (q->low_mark < 4) 113e705c121SKalle Valo q->low_mark = 4; 114e705c121SKalle Valo 115e705c121SKalle Valo q->high_mark = q->n_window / 8; 116e705c121SKalle Valo if (q->high_mark < 2) 117e705c121SKalle Valo q->high_mark = 2; 118e705c121SKalle Valo 119e705c121SKalle Valo q->write_ptr = 0; 120e705c121SKalle Valo q->read_ptr = 0; 121e705c121SKalle Valo 122e705c121SKalle Valo return 0; 123e705c121SKalle Valo } 124e705c121SKalle Valo 12513a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 126e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 127e705c121SKalle Valo { 128e705c121SKalle Valo if (WARN_ON(ptr->addr)) 129e705c121SKalle Valo return -EINVAL; 130e705c121SKalle Valo 131e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 132e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 133e705c121SKalle Valo if (!ptr->addr) 134e705c121SKalle Valo return -ENOMEM; 135e705c121SKalle Valo ptr->size = size; 136e705c121SKalle Valo return 0; 137e705c121SKalle Valo } 138e705c121SKalle Valo 13913a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 140e705c121SKalle Valo { 141e705c121SKalle Valo if (unlikely(!ptr->addr)) 142e705c121SKalle Valo return; 143e705c121SKalle Valo 144e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 145e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 146e705c121SKalle Valo } 147e705c121SKalle Valo 148e99e88a9SKees Cook static void iwl_pcie_txq_stuck_timer(struct timer_list *t) 149e705c121SKalle Valo { 150e99e88a9SKees Cook struct iwl_txq *txq = from_timer(txq, t, stuck_timer); 151e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 152e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 153e705c121SKalle Valo 154e705c121SKalle Valo spin_lock(&txq->lock); 155e705c121SKalle Valo /* check if triggered erroneously */ 156bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 157e705c121SKalle Valo spin_unlock(&txq->lock); 158e705c121SKalle Valo return; 159e705c121SKalle Valo } 160e705c121SKalle Valo spin_unlock(&txq->lock); 161e705c121SKalle Valo 16238398efbSSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 163e705c121SKalle Valo 164e705c121SKalle Valo iwl_force_nmi(trans); 165e705c121SKalle Valo } 166e705c121SKalle Valo 167e705c121SKalle Valo /* 168e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 169e705c121SKalle Valo */ 170e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 1714fe10bc6SSara Sharon struct iwl_txq *txq, u16 byte_cnt, 1724fe10bc6SSara Sharon int num_tbs) 173e705c121SKalle Valo { 174e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 175e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 176bb98ecd4SSara Sharon int write_ptr = txq->write_ptr; 177bb98ecd4SSara Sharon int txq_id = txq->id; 178e705c121SKalle Valo u8 sec_ctl = 0; 179e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 180e705c121SKalle Valo __le16 bc_ent; 181e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 182bb98ecd4SSara Sharon (void *)txq->entries[txq->write_ptr].cmd->payload; 183ab6c6445SSara Sharon u8 sta_id = tx_cmd->sta_id; 184e705c121SKalle Valo 185e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 186e705c121SKalle Valo 187e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 188e705c121SKalle Valo 189e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 190e705c121SKalle Valo case TX_CMD_SEC_CCM: 191e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 192e705c121SKalle Valo break; 193e705c121SKalle Valo case TX_CMD_SEC_TKIP: 194e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 195e705c121SKalle Valo break; 196e705c121SKalle Valo case TX_CMD_SEC_WEP: 197e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 198e705c121SKalle Valo break; 199e705c121SKalle Valo } 200e705c121SKalle Valo if (trans_pcie->bc_table_dword) 201e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 202e705c121SKalle Valo 203e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 204e705c121SKalle Valo return; 205e705c121SKalle Valo 206e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 207e705c121SKalle Valo 208e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 209e705c121SKalle Valo 210e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 211e705c121SKalle Valo scd_bc_tbl[txq_id]. 212e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 213e705c121SKalle Valo } 214e705c121SKalle Valo 215e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 216e705c121SKalle Valo struct iwl_txq *txq) 217e705c121SKalle Valo { 218e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 219e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 220e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 221bb98ecd4SSara Sharon int txq_id = txq->id; 222bb98ecd4SSara Sharon int read_ptr = txq->read_ptr; 223e705c121SKalle Valo u8 sta_id = 0; 224e705c121SKalle Valo __le16 bc_ent; 225e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 226bb98ecd4SSara Sharon (void *)txq->entries[read_ptr].cmd->payload; 227e705c121SKalle Valo 228e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 229e705c121SKalle Valo 230e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 231e705c121SKalle Valo sta_id = tx_cmd->sta_id; 232e705c121SKalle Valo 233e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 2344fe10bc6SSara Sharon 235e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 236e705c121SKalle Valo 237e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 238e705c121SKalle Valo scd_bc_tbl[txq_id]. 239e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 240e705c121SKalle Valo } 241e705c121SKalle Valo 242e705c121SKalle Valo /* 243e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 244e705c121SKalle Valo */ 245e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 246e705c121SKalle Valo struct iwl_txq *txq) 247e705c121SKalle Valo { 248e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 249e705c121SKalle Valo u32 reg = 0; 250bb98ecd4SSara Sharon int txq_id = txq->id; 251e705c121SKalle Valo 252e705c121SKalle Valo lockdep_assert_held(&txq->lock); 253e705c121SKalle Valo 254e705c121SKalle Valo /* 255e705c121SKalle Valo * explicitly wake up the NIC if: 256e705c121SKalle Valo * 1. shadow registers aren't enabled 257e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 258e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 259e705c121SKalle Valo */ 260e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 261e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 262e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 263e705c121SKalle Valo /* 264e705c121SKalle Valo * wake up nic if it's powered down ... 265e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 266e705c121SKalle Valo * time we'll skip this part. 267e705c121SKalle Valo */ 268e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 269e705c121SKalle Valo 270e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 271e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 272e705c121SKalle Valo txq_id, reg); 273e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 274a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 275e705c121SKalle Valo txq->need_update = true; 276e705c121SKalle Valo return; 277e705c121SKalle Valo } 278e705c121SKalle Valo } 279e705c121SKalle Valo 280e705c121SKalle Valo /* 281e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 282e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 283e705c121SKalle Valo */ 284bb98ecd4SSara Sharon IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 2850cd58eaaSEmmanuel Grumbach if (!txq->block) 2860cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 287bb98ecd4SSara Sharon txq->write_ptr | (txq_id << 8)); 288e705c121SKalle Valo } 289e705c121SKalle Valo 290e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 291e705c121SKalle Valo { 292e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 293e705c121SKalle Valo int i; 294e705c121SKalle Valo 295e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 296b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 297e705c121SKalle Valo 298f6eac740SMordechai Goodstein if (!test_bit(i, trans_pcie->queue_used)) 299f6eac740SMordechai Goodstein continue; 300f6eac740SMordechai Goodstein 301e705c121SKalle Valo spin_lock_bh(&txq->lock); 302b2a3b1c1SSara Sharon if (txq->need_update) { 303e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 304b2a3b1c1SSara Sharon txq->need_update = false; 305e705c121SKalle Valo } 306e705c121SKalle Valo spin_unlock_bh(&txq->lock); 307e705c121SKalle Valo } 308e705c121SKalle Valo } 309e705c121SKalle Valo 3106983ba69SSara Sharon static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 311cc2f41f8SJohannes Berg void *_tfd, u8 idx) 3126983ba69SSara Sharon { 3136983ba69SSara Sharon 3146983ba69SSara Sharon if (trans->cfg->use_tfh) { 315cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 316cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 3176983ba69SSara Sharon 3186983ba69SSara Sharon return (dma_addr_t)(le64_to_cpu(tb->addr)); 319cc2f41f8SJohannes Berg } else { 320cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 321cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 322cc2f41f8SJohannes Berg dma_addr_t addr = get_unaligned_le32(&tb->lo); 323cc2f41f8SJohannes Berg dma_addr_t hi_len; 3246983ba69SSara Sharon 325cc2f41f8SJohannes Berg if (sizeof(dma_addr_t) <= sizeof(u32)) 326e705c121SKalle Valo return addr; 327cc2f41f8SJohannes Berg 328cc2f41f8SJohannes Berg hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 329cc2f41f8SJohannes Berg 330cc2f41f8SJohannes Berg /* 331cc2f41f8SJohannes Berg * shift by 16 twice to avoid warnings on 32-bit 332cc2f41f8SJohannes Berg * (where this code never runs anyway due to the 333cc2f41f8SJohannes Berg * if statement above) 334cc2f41f8SJohannes Berg */ 335cc2f41f8SJohannes Berg return addr | ((hi_len << 16) << 16); 336cc2f41f8SJohannes Berg } 337e705c121SKalle Valo } 338e705c121SKalle Valo 3396983ba69SSara Sharon static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 3406983ba69SSara Sharon u8 idx, dma_addr_t addr, u16 len) 341e705c121SKalle Valo { 3426983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 3436983ba69SSara Sharon struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 3446983ba69SSara Sharon 345e705c121SKalle Valo u16 hi_n_len = len << 4; 346e705c121SKalle Valo 347e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 3487abf6fdeSJohannes Berg hi_n_len |= iwl_get_dma_hi_addr(addr); 349e705c121SKalle Valo 350e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 351e705c121SKalle Valo 3526983ba69SSara Sharon tfd_fh->num_tbs = idx + 1; 3536983ba69SSara Sharon } 354e705c121SKalle Valo 355cc2f41f8SJohannes Berg static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 356e705c121SKalle Valo { 3576983ba69SSara Sharon if (trans->cfg->use_tfh) { 358cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 3596983ba69SSara Sharon 360cc2f41f8SJohannes Berg return le16_to_cpu(tfd->num_tbs) & 0x1f; 361cc2f41f8SJohannes Berg } else { 362cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 363cc2f41f8SJohannes Berg 364cc2f41f8SJohannes Berg return tfd->num_tbs & 0x1f; 3656983ba69SSara Sharon } 366e705c121SKalle Valo } 367e705c121SKalle Valo 368e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 369e705c121SKalle Valo struct iwl_cmd_meta *meta, 3706983ba69SSara Sharon struct iwl_txq *txq, int index) 371e705c121SKalle Valo { 3723cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3733cd1980bSSara Sharon int i, num_tbs; 374943309d4SEmmanuel Grumbach void *tfd = iwl_pcie_get_tfd(trans, txq, index); 375e705c121SKalle Valo 376e705c121SKalle Valo /* Sanity check on number of chunks */ 3776983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 378e705c121SKalle Valo 3794437ba7eSEmmanuel Grumbach if (num_tbs > trans_pcie->max_tbs) { 380e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 381e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 382e705c121SKalle Valo return; 383e705c121SKalle Valo } 384e705c121SKalle Valo 3858de437c7SSara Sharon /* first TB is never freed - it's the bidirectional DMA data */ 386e705c121SKalle Valo 387e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 3883cd1980bSSara Sharon if (meta->tbs & BIT(i)) 389e705c121SKalle Valo dma_unmap_page(trans->dev, 3906983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 3916983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, i), 392e705c121SKalle Valo DMA_TO_DEVICE); 393e705c121SKalle Valo else 394e705c121SKalle Valo dma_unmap_single(trans->dev, 3956983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, 3966983ba69SSara Sharon i), 3976983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, 3986983ba69SSara Sharon i), 399e705c121SKalle Valo DMA_TO_DEVICE); 400e705c121SKalle Valo } 4016983ba69SSara Sharon 4026983ba69SSara Sharon if (trans->cfg->use_tfh) { 4036983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4046983ba69SSara Sharon 4056983ba69SSara Sharon tfd_fh->num_tbs = 0; 4066983ba69SSara Sharon } else { 4076983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 4086983ba69SSara Sharon 4096983ba69SSara Sharon tfd_fh->num_tbs = 0; 4106983ba69SSara Sharon } 4116983ba69SSara Sharon 412e705c121SKalle Valo } 413e705c121SKalle Valo 414e705c121SKalle Valo /* 415e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 416e705c121SKalle Valo * @trans - transport private data 417e705c121SKalle Valo * @txq - tx queue 418e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 419e705c121SKalle Valo * 420e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 421e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 422e705c121SKalle Valo */ 4236b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 424e705c121SKalle Valo { 425e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 426e705c121SKalle Valo * idx is bounded by n_window 427e705c121SKalle Valo */ 428bb98ecd4SSara Sharon int rd_ptr = txq->read_ptr; 4294ecab561SEmmanuel Grumbach int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 430e705c121SKalle Valo 431e705c121SKalle Valo lockdep_assert_held(&txq->lock); 432e705c121SKalle Valo 433e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 434e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 435e705c121SKalle Valo */ 4366983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 437e705c121SKalle Valo 438e705c121SKalle Valo /* free SKB */ 439e705c121SKalle Valo if (txq->entries) { 440e705c121SKalle Valo struct sk_buff *skb; 441e705c121SKalle Valo 442e705c121SKalle Valo skb = txq->entries[idx].skb; 443e705c121SKalle Valo 444e705c121SKalle Valo /* Can be called from irqs-disabled context 445e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 446e705c121SKalle Valo * freed and that the queue is not empty - free the skb 447e705c121SKalle Valo */ 448e705c121SKalle Valo if (skb) { 449e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 450e705c121SKalle Valo txq->entries[idx].skb = NULL; 451e705c121SKalle Valo } 452e705c121SKalle Valo } 453e705c121SKalle Valo } 454e705c121SKalle Valo 455e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 456e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 457e705c121SKalle Valo { 4583cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4596983ba69SSara Sharon void *tfd; 460e705c121SKalle Valo u32 num_tbs; 461e705c121SKalle Valo 462bb98ecd4SSara Sharon tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 463e705c121SKalle Valo 464e705c121SKalle Valo if (reset) 4656983ba69SSara Sharon memset(tfd, 0, trans_pcie->tfd_size); 466e705c121SKalle Valo 4676983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 468e705c121SKalle Valo 4696983ba69SSara Sharon /* Each TFD can point to a maximum max_tbs Tx buffers */ 4703cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 471e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 4723cd1980bSSara Sharon trans_pcie->max_tbs); 473e705c121SKalle Valo return -EINVAL; 474e705c121SKalle Valo } 475e705c121SKalle Valo 476e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 477e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 478e705c121SKalle Valo return -EINVAL; 479e705c121SKalle Valo 4806983ba69SSara Sharon iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 481e705c121SKalle Valo 482e705c121SKalle Valo return num_tbs; 483e705c121SKalle Valo } 484e705c121SKalle Valo 48513a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 486b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 487e705c121SKalle Valo { 488e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4897b3e42eaSGolan Ben Ami size_t tfd_sz = trans_pcie->tfd_size * 4907b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size; 4918de437c7SSara Sharon size_t tb0_buf_sz; 492e705c121SKalle Valo int i; 493e705c121SKalle Valo 494e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 495e705c121SKalle Valo return -EINVAL; 496e705c121SKalle Valo 497e0498146SSara Sharon if (trans->cfg->use_tfh) 498e0498146SSara Sharon tfd_sz = trans_pcie->tfd_size * slots_num; 499e0498146SSara Sharon 500e99e88a9SKees Cook timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0); 501e705c121SKalle Valo txq->trans_pcie = trans_pcie; 502e705c121SKalle Valo 503bb98ecd4SSara Sharon txq->n_window = slots_num; 504e705c121SKalle Valo 505e705c121SKalle Valo txq->entries = kcalloc(slots_num, 506e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 507e705c121SKalle Valo GFP_KERNEL); 508e705c121SKalle Valo 509e705c121SKalle Valo if (!txq->entries) 510e705c121SKalle Valo goto error; 511e705c121SKalle Valo 512b8e8d7ceSSara Sharon if (cmd_queue) 513e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 514e705c121SKalle Valo txq->entries[i].cmd = 515e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 516e705c121SKalle Valo GFP_KERNEL); 517e705c121SKalle Valo if (!txq->entries[i].cmd) 518e705c121SKalle Valo goto error; 519e705c121SKalle Valo } 520e705c121SKalle Valo 521e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 522e705c121SKalle Valo * shared with device */ 523e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 524bb98ecd4SSara Sharon &txq->dma_addr, GFP_KERNEL); 525e705c121SKalle Valo if (!txq->tfds) 526e705c121SKalle Valo goto error; 527e705c121SKalle Valo 5288de437c7SSara Sharon BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 529e705c121SKalle Valo 5308de437c7SSara Sharon tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 531e705c121SKalle Valo 5328de437c7SSara Sharon txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 5338de437c7SSara Sharon &txq->first_tb_dma, 534e705c121SKalle Valo GFP_KERNEL); 5358de437c7SSara Sharon if (!txq->first_tb_bufs) 536e705c121SKalle Valo goto err_free_tfds; 537e705c121SKalle Valo 538e705c121SKalle Valo return 0; 539e705c121SKalle Valo err_free_tfds: 540bb98ecd4SSara Sharon dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 541e705c121SKalle Valo error: 542b8e8d7ceSSara Sharon if (txq->entries && cmd_queue) 543e705c121SKalle Valo for (i = 0; i < slots_num; i++) 544e705c121SKalle Valo kfree(txq->entries[i].cmd); 545e705c121SKalle Valo kfree(txq->entries); 546e705c121SKalle Valo txq->entries = NULL; 547e705c121SKalle Valo 548e705c121SKalle Valo return -ENOMEM; 549e705c121SKalle Valo 550e705c121SKalle Valo } 551e705c121SKalle Valo 55213a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 553b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 554e705c121SKalle Valo { 555e705c121SKalle Valo int ret; 5567b3e42eaSGolan Ben Ami u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size; 557e705c121SKalle Valo 558e705c121SKalle Valo txq->need_update = false; 559e705c121SKalle Valo 5607b3e42eaSGolan Ben Ami /* max_tfd_queue_size must be power-of-two size, otherwise 561e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 5627b3e42eaSGolan Ben Ami if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1), 5637b3e42eaSGolan Ben Ami "Max tfd queue size must be a power of two, but is %d", 5647b3e42eaSGolan Ben Ami tfd_queue_max_size)) 5657b3e42eaSGolan Ben Ami return -EINVAL; 566e705c121SKalle Valo 567e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 568b8e8d7ceSSara Sharon ret = iwl_queue_init(txq, slots_num); 569e705c121SKalle Valo if (ret) 570e705c121SKalle Valo return ret; 571e705c121SKalle Valo 572e705c121SKalle Valo spin_lock_init(&txq->lock); 573faead41cSJohannes Berg 574b8e8d7ceSSara Sharon if (cmd_queue) { 575faead41cSJohannes Berg static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 576faead41cSJohannes Berg 577faead41cSJohannes Berg lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 578faead41cSJohannes Berg } 579faead41cSJohannes Berg 5803955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 581e705c121SKalle Valo 582e705c121SKalle Valo return 0; 583e705c121SKalle Valo } 584e705c121SKalle Valo 5859bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 58621cb3222SJohannes Berg struct sk_buff *skb) 5876eb5e529SEmmanuel Grumbach { 58821cb3222SJohannes Berg struct page **page_ptr; 5896eb5e529SEmmanuel Grumbach 59021cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 5916eb5e529SEmmanuel Grumbach 59221cb3222SJohannes Berg if (*page_ptr) { 59321cb3222SJohannes Berg __free_page(*page_ptr); 59421cb3222SJohannes Berg *page_ptr = NULL; 5956eb5e529SEmmanuel Grumbach } 5966eb5e529SEmmanuel Grumbach } 5976eb5e529SEmmanuel Grumbach 59801d11cd1SSara Sharon static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 59901d11cd1SSara Sharon { 60001d11cd1SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 60101d11cd1SSara Sharon 60201d11cd1SSara Sharon lockdep_assert_held(&trans_pcie->reg_lock); 60301d11cd1SSara Sharon 60401d11cd1SSara Sharon if (trans_pcie->ref_cmd_in_flight) { 60501d11cd1SSara Sharon trans_pcie->ref_cmd_in_flight = false; 60601d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 607c24c7f58SLuca Coelho iwl_trans_unref(trans); 60801d11cd1SSara Sharon } 60901d11cd1SSara Sharon 61001d11cd1SSara Sharon if (!trans->cfg->base_params->apmg_wake_up_wa) 61101d11cd1SSara Sharon return; 61201d11cd1SSara Sharon if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 61301d11cd1SSara Sharon return; 61401d11cd1SSara Sharon 61501d11cd1SSara Sharon trans_pcie->cmd_hold_nic_awake = false; 61601d11cd1SSara Sharon __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 617a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 61801d11cd1SSara Sharon } 61901d11cd1SSara Sharon 620e705c121SKalle Valo /* 621e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 622e705c121SKalle Valo */ 623e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 624e705c121SKalle Valo { 625e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 626b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 627e705c121SKalle Valo 628e705c121SKalle Valo spin_lock_bh(&txq->lock); 629bb98ecd4SSara Sharon while (txq->write_ptr != txq->read_ptr) { 630e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 631bb98ecd4SSara Sharon txq_id, txq->read_ptr); 6326eb5e529SEmmanuel Grumbach 6336eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 634bb98ecd4SSara Sharon struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 6356eb5e529SEmmanuel Grumbach 6366eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6376eb5e529SEmmanuel Grumbach continue; 6386eb5e529SEmmanuel Grumbach 63921cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 6406eb5e529SEmmanuel Grumbach } 641e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 6427b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 64301d11cd1SSara Sharon 644bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 64501d11cd1SSara Sharon unsigned long flags; 64601d11cd1SSara Sharon 64701d11cd1SSara Sharon spin_lock_irqsave(&trans_pcie->reg_lock, flags); 64801d11cd1SSara Sharon if (txq_id != trans_pcie->cmd_queue) { 64901d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 650bb98ecd4SSara Sharon txq->id); 651c24c7f58SLuca Coelho iwl_trans_unref(trans); 65201d11cd1SSara Sharon } else { 65301d11cd1SSara Sharon iwl_pcie_clear_cmd_in_flight(trans); 65401d11cd1SSara Sharon } 65501d11cd1SSara Sharon spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 65601d11cd1SSara Sharon } 657e705c121SKalle Valo } 6583955525dSEmmanuel Grumbach 6593955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 6603955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 6613955525dSEmmanuel Grumbach 6623955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 6633955525dSEmmanuel Grumbach } 6643955525dSEmmanuel Grumbach 665e705c121SKalle Valo spin_unlock_bh(&txq->lock); 666e705c121SKalle Valo 667e705c121SKalle Valo /* just in case - this queue may have been stopped */ 668e705c121SKalle Valo iwl_wake_queue(trans, txq); 669e705c121SKalle Valo } 670e705c121SKalle Valo 671e705c121SKalle Valo /* 672e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 673e705c121SKalle Valo * @txq: Transmit queue to deallocate. 674e705c121SKalle Valo * 675e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 676e705c121SKalle Valo * Free all buffers. 677e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 678e705c121SKalle Valo */ 679e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 680e705c121SKalle Valo { 681e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 682b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 683e705c121SKalle Valo struct device *dev = trans->dev; 684e705c121SKalle Valo int i; 685e705c121SKalle Valo 686e705c121SKalle Valo if (WARN_ON(!txq)) 687e705c121SKalle Valo return; 688e705c121SKalle Valo 689e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 690e705c121SKalle Valo 691e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 692e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 693bb98ecd4SSara Sharon for (i = 0; i < txq->n_window; i++) { 694e705c121SKalle Valo kzfree(txq->entries[i].cmd); 695e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 696e705c121SKalle Valo } 697e705c121SKalle Valo 698e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 699e705c121SKalle Valo if (txq->tfds) { 700e705c121SKalle Valo dma_free_coherent(dev, 7017b3e42eaSGolan Ben Ami trans_pcie->tfd_size * 7027b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 703bb98ecd4SSara Sharon txq->tfds, txq->dma_addr); 704bb98ecd4SSara Sharon txq->dma_addr = 0; 705e705c121SKalle Valo txq->tfds = NULL; 706e705c121SKalle Valo 707e705c121SKalle Valo dma_free_coherent(dev, 708bb98ecd4SSara Sharon sizeof(*txq->first_tb_bufs) * txq->n_window, 7098de437c7SSara Sharon txq->first_tb_bufs, txq->first_tb_dma); 710e705c121SKalle Valo } 711e705c121SKalle Valo 712e705c121SKalle Valo kfree(txq->entries); 713e705c121SKalle Valo txq->entries = NULL; 714e705c121SKalle Valo 715e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 716e705c121SKalle Valo 717e705c121SKalle Valo /* 0-fill queue descriptor structure */ 718e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 719e705c121SKalle Valo } 720e705c121SKalle Valo 721e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 722e705c121SKalle Valo { 723e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 725e705c121SKalle Valo int chan; 726e705c121SKalle Valo u32 reg_val; 727e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 728e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 729e705c121SKalle Valo 730e705c121SKalle Valo /* make sure all queue are not stopped/used */ 731e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 732e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 733e705c121SKalle Valo 734e705c121SKalle Valo trans_pcie->scd_base_addr = 735e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 736e705c121SKalle Valo 737e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 738e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 739e705c121SKalle Valo 740e705c121SKalle Valo /* reset context data, TX status and translation data */ 741e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 742e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 743e705c121SKalle Valo NULL, clear_dwords); 744e705c121SKalle Valo 745e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 746e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 747e705c121SKalle Valo 748e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 749e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 750e705c121SKalle Valo */ 751e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 752e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 753e705c121SKalle Valo 754e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 755e705c121SKalle Valo trans_pcie->cmd_fifo, 756e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 757e705c121SKalle Valo 758e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 759e705c121SKalle Valo iwl_scd_activate_fifos(trans); 760e705c121SKalle Valo 761e705c121SKalle Valo /* Enable DMA channel */ 762e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 763e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 764e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 765e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 766e705c121SKalle Valo 767e705c121SKalle Valo /* Update FH chicken bits */ 768e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 769e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 770e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 771e705c121SKalle Valo 772e705c121SKalle Valo /* Enable L1-Active */ 7736e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 774e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 775e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 776e705c121SKalle Valo } 777e705c121SKalle Valo 778e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 779e705c121SKalle Valo { 780e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 781e705c121SKalle Valo int txq_id; 782e705c121SKalle Valo 78313a3a390SSara Sharon /* 78413a3a390SSara Sharon * we should never get here in gen2 trans mode return early to avoid 78513a3a390SSara Sharon * having invalid accesses 78613a3a390SSara Sharon */ 78713a3a390SSara Sharon if (WARN_ON_ONCE(trans->cfg->gen2)) 78813a3a390SSara Sharon return; 78913a3a390SSara Sharon 790e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 791e705c121SKalle Valo txq_id++) { 792b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 793e22744afSSara Sharon if (trans->cfg->use_tfh) 794e22744afSSara Sharon iwl_write_direct64(trans, 795e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 796bb98ecd4SSara Sharon txq->dma_addr); 797e22744afSSara Sharon else 798e22744afSSara Sharon iwl_write_direct32(trans, 799e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 800bb98ecd4SSara Sharon txq->dma_addr >> 8); 801e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 802bb98ecd4SSara Sharon txq->read_ptr = 0; 803bb98ecd4SSara Sharon txq->write_ptr = 0; 804e705c121SKalle Valo } 805e705c121SKalle Valo 806e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 807e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 808e705c121SKalle Valo trans_pcie->kw.dma >> 4); 809e705c121SKalle Valo 810e705c121SKalle Valo /* 811e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 812e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 813e705c121SKalle Valo * contain garbage. 814e705c121SKalle Valo */ 815e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 816e705c121SKalle Valo } 817e705c121SKalle Valo 818e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 819e705c121SKalle Valo { 820e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 821e705c121SKalle Valo unsigned long flags; 822e705c121SKalle Valo int ch, ret; 823e705c121SKalle Valo u32 mask = 0; 824e705c121SKalle Valo 825e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 826e705c121SKalle Valo 82723ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 828e705c121SKalle Valo goto out; 829e705c121SKalle Valo 830e705c121SKalle Valo /* Stop each Tx DMA channel */ 831e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 832e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 833e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 834e705c121SKalle Valo } 835e705c121SKalle Valo 836e705c121SKalle Valo /* Wait for DMA channels to be idle */ 837e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 838e705c121SKalle Valo if (ret < 0) 839e705c121SKalle Valo IWL_ERR(trans, 840e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 841e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 842e705c121SKalle Valo 843e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 844e705c121SKalle Valo 845e705c121SKalle Valo out: 846e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 847e705c121SKalle Valo } 848e705c121SKalle Valo 849e705c121SKalle Valo /* 850e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 851e705c121SKalle Valo */ 852e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 853e705c121SKalle Valo { 854e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 855e705c121SKalle Valo int txq_id; 856e705c121SKalle Valo 857e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 858e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 859e705c121SKalle Valo 860e705c121SKalle Valo /* Turn off all Tx DMA channels */ 861e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 862e705c121SKalle Valo 863e705c121SKalle Valo /* 864e705c121SKalle Valo * This function can be called before the op_mode disabled the 865e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 866e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 867e705c121SKalle Valo */ 868e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 869e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 870e705c121SKalle Valo 871e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 872b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 873e705c121SKalle Valo return 0; 874e705c121SKalle Valo 875e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 876e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 877e705c121SKalle Valo txq_id++) 878e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 879e705c121SKalle Valo 880e705c121SKalle Valo return 0; 881e705c121SKalle Valo } 882e705c121SKalle Valo 883e705c121SKalle Valo /* 884e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 885e705c121SKalle Valo * 886e705c121SKalle Valo * Destroy all TX DMA queues and structures 887e705c121SKalle Valo */ 888e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 889e705c121SKalle Valo { 890e705c121SKalle Valo int txq_id; 891e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 892e705c121SKalle Valo 893de74c455SSara Sharon memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 894de74c455SSara Sharon 895e705c121SKalle Valo /* Tx queues */ 896b2a3b1c1SSara Sharon if (trans_pcie->txq_memory) { 897e705c121SKalle Valo for (txq_id = 0; 898b2a3b1c1SSara Sharon txq_id < trans->cfg->base_params->num_of_queues; 899b2a3b1c1SSara Sharon txq_id++) { 900e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 901b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = NULL; 902b2a3b1c1SSara Sharon } 903e705c121SKalle Valo } 904e705c121SKalle Valo 905b2a3b1c1SSara Sharon kfree(trans_pcie->txq_memory); 906b2a3b1c1SSara Sharon trans_pcie->txq_memory = NULL; 907e705c121SKalle Valo 908e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 909e705c121SKalle Valo 910e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 911e705c121SKalle Valo } 912e705c121SKalle Valo 913e705c121SKalle Valo /* 914e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 915e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 916e705c121SKalle Valo */ 917e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 918e705c121SKalle Valo { 919e705c121SKalle Valo int ret; 920e705c121SKalle Valo int txq_id, slots_num; 921e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 9227b3e42eaSGolan Ben Ami u16 bc_tbls_size = trans->cfg->base_params->num_of_queues; 923e705c121SKalle Valo 9247b3e42eaSGolan Ben Ami bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 9257b3e42eaSGolan Ben Ami sizeof(struct iwl_gen3_bc_tbl) : 926e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 927e705c121SKalle Valo 928e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 929e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 930b2a3b1c1SSara Sharon if (WARN_ON(trans_pcie->txq_memory)) { 931e705c121SKalle Valo ret = -EINVAL; 932e705c121SKalle Valo goto error; 933e705c121SKalle Valo } 934e705c121SKalle Valo 935e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 9367b3e42eaSGolan Ben Ami bc_tbls_size); 937e705c121SKalle Valo if (ret) { 938e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 939e705c121SKalle Valo goto error; 940e705c121SKalle Valo } 941e705c121SKalle Valo 942e705c121SKalle Valo /* Alloc keep-warm buffer */ 943e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 944e705c121SKalle Valo if (ret) { 945e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 946e705c121SKalle Valo goto error; 947e705c121SKalle Valo } 948e705c121SKalle Valo 949b2a3b1c1SSara Sharon trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 950e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 951b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 952e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 953e705c121SKalle Valo ret = -ENOMEM; 954e705c121SKalle Valo goto error; 955e705c121SKalle Valo } 956e705c121SKalle Valo 957e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 958e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 959e705c121SKalle Valo txq_id++) { 960b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 961b8e8d7ceSSara Sharon 96201302f5bSSara Sharon slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 963b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 964b2a3b1c1SSara Sharon ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 965b8e8d7ceSSara Sharon slots_num, cmd_queue); 966e705c121SKalle Valo if (ret) { 967e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 968e705c121SKalle Valo goto error; 969e705c121SKalle Valo } 970b8e8d7ceSSara Sharon trans_pcie->txq[txq_id]->id = txq_id; 971e705c121SKalle Valo } 972e705c121SKalle Valo 973e705c121SKalle Valo return 0; 974e705c121SKalle Valo 975e705c121SKalle Valo error: 976e705c121SKalle Valo iwl_pcie_tx_free(trans); 977e705c121SKalle Valo 978e705c121SKalle Valo return ret; 979e705c121SKalle Valo } 980eda50cdeSSara Sharon 981e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 982e705c121SKalle Valo { 983e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 984e705c121SKalle Valo int ret; 985e705c121SKalle Valo int txq_id, slots_num; 986e705c121SKalle Valo bool alloc = false; 987e705c121SKalle Valo 988b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 989e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 990e705c121SKalle Valo if (ret) 991e705c121SKalle Valo goto error; 992e705c121SKalle Valo alloc = true; 993e705c121SKalle Valo } 994e705c121SKalle Valo 995e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 996e705c121SKalle Valo 997e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 998e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 999e705c121SKalle Valo 1000e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 1001e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1002e705c121SKalle Valo trans_pcie->kw.dma >> 4); 1003e705c121SKalle Valo 1004e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1005e705c121SKalle Valo 1006e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1007e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1008e705c121SKalle Valo txq_id++) { 1009b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1010b8e8d7ceSSara Sharon 101101302f5bSSara Sharon slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1012b2a3b1c1SSara Sharon ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1013b8e8d7ceSSara Sharon slots_num, cmd_queue); 1014e705c121SKalle Valo if (ret) { 1015e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1016e705c121SKalle Valo goto error; 1017e705c121SKalle Valo } 1018e705c121SKalle Valo 1019eda50cdeSSara Sharon /* 1020eda50cdeSSara Sharon * Tell nic where to find circular buffer of TFDs for a 1021eda50cdeSSara Sharon * given Tx queue, and enable the DMA channel used for that 1022eda50cdeSSara Sharon * queue. 1023eda50cdeSSara Sharon * Circular buffer (TFD queue in DRAM) physical base address 1024eda50cdeSSara Sharon */ 1025eda50cdeSSara Sharon iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1026b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->dma_addr >> 8); 1027ae79785fSSara Sharon } 1028e22744afSSara Sharon 1029e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1030e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 1031e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 1032e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 1033e705c121SKalle Valo 1034e705c121SKalle Valo return 0; 1035e705c121SKalle Valo error: 1036e705c121SKalle Valo /*Upon error, free only if we allocated something */ 1037e705c121SKalle Valo if (alloc) 1038e705c121SKalle Valo iwl_pcie_tx_free(trans); 1039e705c121SKalle Valo return ret; 1040e705c121SKalle Valo } 1041e705c121SKalle Valo 1042e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1043e705c121SKalle Valo { 1044e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1045e705c121SKalle Valo 1046e705c121SKalle Valo if (!txq->wd_timeout) 1047e705c121SKalle Valo return; 1048e705c121SKalle Valo 1049e705c121SKalle Valo /* 1050e705c121SKalle Valo * station is asleep and we send data - that must 1051e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 1052e705c121SKalle Valo */ 1053e705c121SKalle Valo if (txq->frozen) 1054e705c121SKalle Valo return; 1055e705c121SKalle Valo 1056e705c121SKalle Valo /* 1057e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 1058e705c121SKalle Valo * since we're making progress on this queue 1059e705c121SKalle Valo */ 1060bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 1061e705c121SKalle Valo del_timer(&txq->stuck_timer); 1062e705c121SKalle Valo else 1063e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1064e705c121SKalle Valo } 1065e705c121SKalle Valo 1066e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1067e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1068e705c121SKalle Valo struct sk_buff_head *skbs) 1069e705c121SKalle Valo { 1070e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1071b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 10727b3e42eaSGolan Ben Ami int tfd_num = iwl_pcie_get_cmd_index(txq, ssn); 10737b3e42eaSGolan Ben Ami int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1074e705c121SKalle Valo int last_to_free; 1075e705c121SKalle Valo 1076e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1077e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1078e705c121SKalle Valo return; 1079e705c121SKalle Valo 1080e705c121SKalle Valo spin_lock_bh(&txq->lock); 1081e705c121SKalle Valo 1082de74c455SSara Sharon if (!test_bit(txq_id, trans_pcie->queue_used)) { 1083e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1084e705c121SKalle Valo txq_id, ssn); 1085e705c121SKalle Valo goto out; 1086e705c121SKalle Valo } 1087e705c121SKalle Valo 10887b3e42eaSGolan Ben Ami if (read_ptr == tfd_num) 1089e705c121SKalle Valo goto out; 1090e705c121SKalle Valo 1091e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1092bb98ecd4SSara Sharon txq_id, txq->read_ptr, tfd_num, ssn); 1093e705c121SKalle Valo 1094e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1095e705c121SKalle Valo * the last we will free. This one must be used */ 10967b3e42eaSGolan Ben Ami last_to_free = iwl_queue_dec_wrap(trans, tfd_num); 1097e705c121SKalle Valo 1098bb98ecd4SSara Sharon if (!iwl_queue_used(txq, last_to_free)) { 1099e705c121SKalle Valo IWL_ERR(trans, 110081f0c661SGolan Ben Ami "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 11017b3e42eaSGolan Ben Ami __func__, txq_id, last_to_free, 11027b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1103bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1104e705c121SKalle Valo goto out; 1105e705c121SKalle Valo } 1106e705c121SKalle Valo 1107e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1108e705c121SKalle Valo goto out; 1109e705c121SKalle Valo 1110e705c121SKalle Valo for (; 11117b3e42eaSGolan Ben Ami read_ptr != tfd_num; 11127b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr), 11137b3e42eaSGolan Ben Ami read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) { 11147b3e42eaSGolan Ben Ami struct sk_buff *skb = txq->entries[read_ptr].skb; 1115e705c121SKalle Valo 11166eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1117e705c121SKalle Valo continue; 1118e705c121SKalle Valo 111921cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 11206eb5e529SEmmanuel Grumbach 11216eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1122e705c121SKalle Valo 11237b3e42eaSGolan Ben Ami txq->entries[read_ptr].skb = NULL; 1124e705c121SKalle Valo 11254fe10bc6SSara Sharon if (!trans->cfg->use_tfh) 1126e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1127e705c121SKalle Valo 1128e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1129e705c121SKalle Valo } 1130e705c121SKalle Valo 1131e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1132e705c121SKalle Valo 11337b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark && 11343955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1135685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 11363955525dSEmmanuel Grumbach 1137685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1138685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 11393955525dSEmmanuel Grumbach 11403955525dSEmmanuel Grumbach /* 11413955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 11423955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 11433955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 11443955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 11453955525dSEmmanuel Grumbach * later. 11463955525dSEmmanuel Grumbach */ 11473955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 11483955525dSEmmanuel Grumbach 1149685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1150685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 115121cb3222SJohannes Berg struct iwl_device_cmd *dev_cmd_ptr; 115221cb3222SJohannes Berg 115321cb3222SJohannes Berg dev_cmd_ptr = *(void **)((u8 *)skb->cb + 115421cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 11553955525dSEmmanuel Grumbach 11563955525dSEmmanuel Grumbach /* 11573955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 11583955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 11593955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 11603955525dSEmmanuel Grumbach */ 1161f79b8f9dSEmmanuel Grumbach iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id); 11623955525dSEmmanuel Grumbach } 11633955525dSEmmanuel Grumbach 11647b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark) 1165e705c121SKalle Valo iwl_wake_queue(trans, txq); 116636817294SSara Sharon 116736817294SSara Sharon spin_lock_bh(&txq->lock); 11683955525dSEmmanuel Grumbach } 1169e705c121SKalle Valo 1170bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1171bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); 1172c24c7f58SLuca Coelho iwl_trans_unref(trans); 1173e705c121SKalle Valo } 1174e705c121SKalle Valo 1175e705c121SKalle Valo out: 1176e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1177e705c121SKalle Valo } 1178e705c121SKalle Valo 1179e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1180e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1181e705c121SKalle Valo { 1182e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1183a8cbb46fSGolan Ben Ami const struct iwl_cfg *cfg = trans->cfg; 1184e705c121SKalle Valo int ret; 1185e705c121SKalle Valo 1186e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1187e705c121SKalle Valo 11882b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 1189f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1190f60c9e59SEmmanuel Grumbach return -ENODEV; 11912b3fae66SMatt Chen 1192e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1193e705c121SKalle Valo !trans_pcie->ref_cmd_in_flight) { 1194e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = true; 1195e705c121SKalle Valo IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1196c24c7f58SLuca Coelho iwl_trans_ref(trans); 1197e705c121SKalle Valo } 1198e705c121SKalle Valo 1199e705c121SKalle Valo /* 1200e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1201e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1202e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1203e705c121SKalle Valo * apmg_wake_up_wa set. 1204e705c121SKalle Valo */ 1205a8cbb46fSGolan Ben Ami if (cfg->base_params->apmg_wake_up_wa && 1206e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1207e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1208a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1209e705c121SKalle Valo 1210e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1211a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_val_mac_access_en), 1212a8cbb46fSGolan Ben Ami (BIT(cfg->csr->flag_mac_clock_ready) | 1213e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1214e705c121SKalle Valo 15000); 1215e705c121SKalle Valo if (ret < 0) { 1216e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1217a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1218e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1219e705c121SKalle Valo return -EIO; 1220e705c121SKalle Valo } 1221e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1222e705c121SKalle Valo } 1223e705c121SKalle Valo 1224e705c121SKalle Valo return 0; 1225e705c121SKalle Valo } 1226e705c121SKalle Valo 1227e705c121SKalle Valo /* 1228e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1229e705c121SKalle Valo * 1230e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1231e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1232e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1233e705c121SKalle Valo */ 123489d5e833SGolan Ben Ami void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1235e705c121SKalle Valo { 1236e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1238e705c121SKalle Valo unsigned long flags; 1239e705c121SKalle Valo int nfreed = 0; 1240f5955a6cSGolan Ben Ami u16 r; 1241e705c121SKalle Valo 1242e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1243e705c121SKalle Valo 1244f5955a6cSGolan Ben Ami idx = iwl_pcie_get_cmd_index(txq, idx); 1245f5955a6cSGolan Ben Ami r = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1246f5955a6cSGolan Ben Ami 12477b3e42eaSGolan Ben Ami if (idx >= trans->cfg->base_params->max_tfd_queue_size || 12487b3e42eaSGolan Ben Ami (!iwl_queue_used(txq, idx))) { 12490916224eSSara Sharon WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used), 1250e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 12517b3e42eaSGolan Ben Ami __func__, txq_id, idx, 12527b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1253bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1254e705c121SKalle Valo return; 1255e705c121SKalle Valo } 1256e705c121SKalle Valo 12577b3e42eaSGolan Ben Ami for (idx = iwl_queue_inc_wrap(trans, idx); r != idx; 12587b3e42eaSGolan Ben Ami r = iwl_queue_inc_wrap(trans, r)) { 12597b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1260e705c121SKalle Valo 1261e705c121SKalle Valo if (nfreed++ > 0) { 1262e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1263f5955a6cSGolan Ben Ami idx, txq->write_ptr, r); 1264e705c121SKalle Valo iwl_force_nmi(trans); 1265e705c121SKalle Valo } 1266e705c121SKalle Valo } 1267e705c121SKalle Valo 1268bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1269e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1270e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1271e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1272e705c121SKalle Valo } 1273e705c121SKalle Valo 1274e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1275e705c121SKalle Valo } 1276e705c121SKalle Valo 1277e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1278e705c121SKalle Valo u16 txq_id) 1279e705c121SKalle Valo { 1280e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1281e705c121SKalle Valo u32 tbl_dw_addr; 1282e705c121SKalle Valo u32 tbl_dw; 1283e705c121SKalle Valo u16 scd_q2ratid; 1284e705c121SKalle Valo 1285e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1286e705c121SKalle Valo 1287e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1288e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1289e705c121SKalle Valo 1290e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1291e705c121SKalle Valo 1292e705c121SKalle Valo if (txq_id & 0x1) 1293e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1294e705c121SKalle Valo else 1295e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1296e705c121SKalle Valo 1297e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1298e705c121SKalle Valo 1299e705c121SKalle Valo return 0; 1300e705c121SKalle Valo } 1301e705c121SKalle Valo 1302e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1303e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1304e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1305e705c121SKalle Valo 1306dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1307e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1308e705c121SKalle Valo unsigned int wdg_timeout) 1309e705c121SKalle Valo { 1310e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1311b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1312e705c121SKalle Valo int fifo = -1; 1313dcfbd67bSEmmanuel Grumbach bool scd_bug = false; 1314e705c121SKalle Valo 1315e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1316e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1317e705c121SKalle Valo 1318e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1319e705c121SKalle Valo 1320e705c121SKalle Valo if (cfg) { 1321e705c121SKalle Valo fifo = cfg->fifo; 1322e705c121SKalle Valo 1323e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1324e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1325e705c121SKalle Valo trans_pcie->scd_set_active) 1326e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1327e705c121SKalle Valo 1328e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1329e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1330e705c121SKalle Valo 1331e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1332e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1333e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1334e705c121SKalle Valo 1335e705c121SKalle Valo if (cfg->aggregate) { 1336e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1337e705c121SKalle Valo 1338e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1339e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1340e705c121SKalle Valo 1341e705c121SKalle Valo /* enable aggregations for the queue */ 1342e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1343e705c121SKalle Valo txq->ampdu = true; 1344e705c121SKalle Valo } else { 1345e705c121SKalle Valo /* 1346e705c121SKalle Valo * disable aggregations for the queue, this will also 1347e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1348e705c121SKalle Valo * since it is now a non-AGG queue. 1349e705c121SKalle Valo */ 1350e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1351e705c121SKalle Valo 1352bb98ecd4SSara Sharon ssn = txq->read_ptr; 1353e705c121SKalle Valo } 1354dcfbd67bSEmmanuel Grumbach } else { 1355dcfbd67bSEmmanuel Grumbach /* 1356dcfbd67bSEmmanuel Grumbach * If we need to move the SCD write pointer by steps of 1357dcfbd67bSEmmanuel Grumbach * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1358dcfbd67bSEmmanuel Grumbach * the op_mode know by returning true later. 1359dcfbd67bSEmmanuel Grumbach * Do this only in case cfg is NULL since this trick can 1360dcfbd67bSEmmanuel Grumbach * be done only if we have DQA enabled which is true for mvm 1361dcfbd67bSEmmanuel Grumbach * only. And mvm never sets a cfg pointer. 1362dcfbd67bSEmmanuel Grumbach * This is really ugly, but this is the easiest way out for 1363dcfbd67bSEmmanuel Grumbach * this sad hardware issue. 1364dcfbd67bSEmmanuel Grumbach * This bug has been fixed on devices 9000 and up. 1365dcfbd67bSEmmanuel Grumbach */ 1366dcfbd67bSEmmanuel Grumbach scd_bug = !trans->cfg->mq_rx_supported && 1367dcfbd67bSEmmanuel Grumbach !((ssn - txq->write_ptr) & 0x3f) && 1368dcfbd67bSEmmanuel Grumbach (ssn != txq->write_ptr); 1369dcfbd67bSEmmanuel Grumbach if (scd_bug) 1370dcfbd67bSEmmanuel Grumbach ssn++; 1371e705c121SKalle Valo } 1372e705c121SKalle Valo 1373e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1374e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1375bb98ecd4SSara Sharon txq->read_ptr = (ssn & 0xff); 1376bb98ecd4SSara Sharon txq->write_ptr = (ssn & 0xff); 1377e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1378e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1379e705c121SKalle Valo 1380e705c121SKalle Valo if (cfg) { 1381e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1382e705c121SKalle Valo 1383e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1384e705c121SKalle Valo 1385e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1386e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1387e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1388e705c121SKalle Valo iwl_trans_write_mem32(trans, 1389e705c121SKalle Valo trans_pcie->scd_base_addr + 1390e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1391f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1392f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1393e705c121SKalle Valo 1394e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1395e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1396e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1397e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1398e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1399e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1400e705c121SKalle Valo 1401e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1402e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1403e705c121SKalle Valo trans_pcie->scd_set_active) 1404e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1405e705c121SKalle Valo 1406e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1407e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1408e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1409e705c121SKalle Valo } else { 1410e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1411e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1412e705c121SKalle Valo txq_id, ssn & 0xff); 1413e705c121SKalle Valo } 1414dcfbd67bSEmmanuel Grumbach 1415dcfbd67bSEmmanuel Grumbach return scd_bug; 1416e705c121SKalle Valo } 1417e705c121SKalle Valo 141842db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 141942db09c1SLiad Kaufman bool shared_mode) 142042db09c1SLiad Kaufman { 142142db09c1SLiad Kaufman struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1422b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 142342db09c1SLiad Kaufman 142442db09c1SLiad Kaufman txq->ampdu = !shared_mode; 142542db09c1SLiad Kaufman } 142642db09c1SLiad Kaufman 1427e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1428e705c121SKalle Valo bool configure_scd) 1429e705c121SKalle Valo { 1430e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1431e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1432e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1433e705c121SKalle Valo static const u32 zero_val[4] = {}; 1434e705c121SKalle Valo 1435b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1436b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen = false; 1437e705c121SKalle Valo 1438e705c121SKalle Valo /* 1439e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1440e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1441e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1442e705c121SKalle Valo * stop_device. 1443e705c121SKalle Valo */ 1444e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1445e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1446e705c121SKalle Valo "queue %d not used", txq_id); 1447e705c121SKalle Valo return; 1448e705c121SKalle Valo } 1449e705c121SKalle Valo 1450e705c121SKalle Valo if (configure_scd) { 1451e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1452e705c121SKalle Valo 1453e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1454e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1455e705c121SKalle Valo } 1456e705c121SKalle Valo 1457e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1458b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->ampdu = false; 1459e705c121SKalle Valo 1460e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1461e705c121SKalle Valo } 1462e705c121SKalle Valo 1463e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1464e705c121SKalle Valo 1465e705c121SKalle Valo /* 1466e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1467e705c121SKalle Valo * @priv: device private data point 1468e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1469e705c121SKalle Valo * 1470e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1471e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1472e705c121SKalle Valo * command queue. 1473e705c121SKalle Valo */ 1474e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1475e705c121SKalle Valo struct iwl_host_cmd *cmd) 1476e705c121SKalle Valo { 1477e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1478b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1479e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1480e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1481e705c121SKalle Valo unsigned long flags; 1482e705c121SKalle Valo void *dup_buf = NULL; 1483e705c121SKalle Valo dma_addr_t phys_addr; 1484e705c121SKalle Valo int idx; 14858de437c7SSara Sharon u16 copy_size, cmd_size, tb0_size; 1486e705c121SKalle Valo bool had_nocopy = false; 1487e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1488e705c121SKalle Valo int i, ret; 1489e705c121SKalle Valo u32 cmd_pos; 1490e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1491e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1492e705c121SKalle Valo 14935b88792cSSara Sharon if (WARN(!trans->wide_cmd_header && 1494e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1495e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1496e705c121SKalle Valo return -EINVAL; 1497e705c121SKalle Valo 1498e705c121SKalle Valo if (group_id != 0) { 1499e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1500e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1501e705c121SKalle Valo } else { 1502e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1503e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1504e705c121SKalle Valo } 1505e705c121SKalle Valo 1506e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1507e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1508e705c121SKalle Valo 1509e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1510e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1511e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1512e705c121SKalle Valo 1513e705c121SKalle Valo if (!cmd->len[i]) 1514e705c121SKalle Valo continue; 1515e705c121SKalle Valo 15168de437c7SSara Sharon /* need at least IWL_FIRST_TB_SIZE copied */ 15178de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 15188de437c7SSara Sharon int copy = IWL_FIRST_TB_SIZE - copy_size; 1519e705c121SKalle Valo 1520e705c121SKalle Valo if (copy > cmdlen[i]) 1521e705c121SKalle Valo copy = cmdlen[i]; 1522e705c121SKalle Valo cmdlen[i] -= copy; 1523e705c121SKalle Valo cmddata[i] += copy; 1524e705c121SKalle Valo copy_size += copy; 1525e705c121SKalle Valo } 1526e705c121SKalle Valo 1527e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1528e705c121SKalle Valo had_nocopy = true; 1529e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1530e705c121SKalle Valo idx = -EINVAL; 1531e705c121SKalle Valo goto free_dup_buf; 1532e705c121SKalle Valo } 1533e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1534e705c121SKalle Valo /* 1535e705c121SKalle Valo * This is also a chunk that isn't copied 1536e705c121SKalle Valo * to the static buffer so set had_nocopy. 1537e705c121SKalle Valo */ 1538e705c121SKalle Valo had_nocopy = true; 1539e705c121SKalle Valo 1540e705c121SKalle Valo /* only allowed once */ 1541e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1542e705c121SKalle Valo idx = -EINVAL; 1543e705c121SKalle Valo goto free_dup_buf; 1544e705c121SKalle Valo } 1545e705c121SKalle Valo 1546e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1547e705c121SKalle Valo GFP_ATOMIC); 1548e705c121SKalle Valo if (!dup_buf) 1549e705c121SKalle Valo return -ENOMEM; 1550e705c121SKalle Valo } else { 1551e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1552e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1553e705c121SKalle Valo idx = -EINVAL; 1554e705c121SKalle Valo goto free_dup_buf; 1555e705c121SKalle Valo } 1556e705c121SKalle Valo copy_size += cmdlen[i]; 1557e705c121SKalle Valo } 1558e705c121SKalle Valo cmd_size += cmd->len[i]; 1559e705c121SKalle Valo } 1560e705c121SKalle Valo 1561e705c121SKalle Valo /* 1562e705c121SKalle Valo * If any of the command structures end up being larger than 1563e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1564e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1565e705c121SKalle Valo * increase the size of the buffers. 1566e705c121SKalle Valo */ 1567e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1568e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 156939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 157039bdb17eSSharon Dvir cmd->id, copy_size)) { 1571e705c121SKalle Valo idx = -EINVAL; 1572e705c121SKalle Valo goto free_dup_buf; 1573e705c121SKalle Valo } 1574e705c121SKalle Valo 1575e705c121SKalle Valo spin_lock_bh(&txq->lock); 1576e705c121SKalle Valo 15777b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1578e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1579e705c121SKalle Valo 1580e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1581e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1582e705c121SKalle Valo idx = -ENOSPC; 1583e705c121SKalle Valo goto free_dup_buf; 1584e705c121SKalle Valo } 1585e705c121SKalle Valo 15864ecab561SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1587e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1588e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1589e705c121SKalle Valo 1590e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1591e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1592e705c121SKalle Valo out_meta->source = cmd; 1593e705c121SKalle Valo 1594e705c121SKalle Valo /* set up the header */ 1595e705c121SKalle Valo if (group_id != 0) { 1596e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1597e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1598e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1599e705c121SKalle Valo out_cmd->hdr_wide.length = 1600e705c121SKalle Valo cpu_to_le16(cmd_size - 1601e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1602e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1603e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1604e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1605bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1606e705c121SKalle Valo 1607e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1608e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1609e705c121SKalle Valo } else { 1610e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1611e705c121SKalle Valo out_cmd->hdr.sequence = 1612e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1613bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1614e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1615e705c121SKalle Valo 1616e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1617e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1618e705c121SKalle Valo } 1619e705c121SKalle Valo 1620e705c121SKalle Valo /* and copy the data that needs to be copied */ 1621e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1622e705c121SKalle Valo int copy; 1623e705c121SKalle Valo 1624e705c121SKalle Valo if (!cmd->len[i]) 1625e705c121SKalle Valo continue; 1626e705c121SKalle Valo 1627e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1628e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1629e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1630e705c121SKalle Valo copy = cmd->len[i]; 1631e705c121SKalle Valo 1632e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1633e705c121SKalle Valo cmd_pos += copy; 1634e705c121SKalle Valo copy_size += copy; 1635e705c121SKalle Valo continue; 1636e705c121SKalle Valo } 1637e705c121SKalle Valo 1638e705c121SKalle Valo /* 16398de437c7SSara Sharon * Otherwise we need at least IWL_FIRST_TB_SIZE copied 16408de437c7SSara Sharon * in total (for bi-directional DMA), but copy up to what 1641e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1642e705c121SKalle Valo */ 1643e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1644e705c121SKalle Valo 1645e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1646e705c121SKalle Valo cmd_pos += copy; 1647e705c121SKalle Valo 1648e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 16498de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 16508de437c7SSara Sharon copy = IWL_FIRST_TB_SIZE - copy_size; 1651e705c121SKalle Valo 1652e705c121SKalle Valo if (copy > cmd->len[i]) 1653e705c121SKalle Valo copy = cmd->len[i]; 1654e705c121SKalle Valo copy_size += copy; 1655e705c121SKalle Valo } 1656e705c121SKalle Valo } 1657e705c121SKalle Valo 1658e705c121SKalle Valo IWL_DEBUG_HC(trans, 1659e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 166039bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1661e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1662e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1663bb98ecd4SSara Sharon cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1664e705c121SKalle Valo 16658de437c7SSara Sharon /* start the TFD with the minimum copy bytes */ 16668de437c7SSara Sharon tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 16678de437c7SSara Sharon memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1668e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 16698de437c7SSara Sharon iwl_pcie_get_first_tb_dma(txq, idx), 16708de437c7SSara Sharon tb0_size, true); 1671e705c121SKalle Valo 1672e705c121SKalle Valo /* map first command fragment, if any remains */ 16738de437c7SSara Sharon if (copy_size > tb0_size) { 1674e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 16758de437c7SSara Sharon ((u8 *)&out_cmd->hdr) + tb0_size, 16768de437c7SSara Sharon copy_size - tb0_size, 1677e705c121SKalle Valo DMA_TO_DEVICE); 1678e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1679bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1680bb98ecd4SSara Sharon txq->write_ptr); 1681e705c121SKalle Valo idx = -ENOMEM; 1682e705c121SKalle Valo goto out; 1683e705c121SKalle Valo } 1684e705c121SKalle Valo 1685e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 16868de437c7SSara Sharon copy_size - tb0_size, false); 1687e705c121SKalle Valo } 1688e705c121SKalle Valo 1689e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1690e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1691e705c121SKalle Valo const void *data = cmddata[i]; 1692e705c121SKalle Valo 1693e705c121SKalle Valo if (!cmdlen[i]) 1694e705c121SKalle Valo continue; 1695e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1696e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1697e705c121SKalle Valo continue; 1698e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1699e705c121SKalle Valo data = dup_buf; 1700e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1701e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1702e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1703bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1704bb98ecd4SSara Sharon txq->write_ptr); 1705e705c121SKalle Valo idx = -ENOMEM; 1706e705c121SKalle Valo goto out; 1707e705c121SKalle Valo } 1708e705c121SKalle Valo 1709e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1710e705c121SKalle Valo } 1711e705c121SKalle Valo 17123cd1980bSSara Sharon BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1713e705c121SKalle Valo out_meta->flags = cmd->flags; 1714e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1715e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1716e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1717e705c121SKalle Valo 1718e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1719e705c121SKalle Valo 1720e705c121SKalle Valo /* start timer if queue currently empty */ 1721bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1722e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1723e705c121SKalle Valo 1724e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1725e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1726e705c121SKalle Valo if (ret < 0) { 1727e705c121SKalle Valo idx = ret; 1728e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1729e705c121SKalle Valo goto out; 1730e705c121SKalle Valo } 1731e705c121SKalle Valo 1732e705c121SKalle Valo /* Increment and update queue's write index */ 17337b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 1734e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1735e705c121SKalle Valo 1736e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1737e705c121SKalle Valo 1738e705c121SKalle Valo out: 1739e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1740e705c121SKalle Valo free_dup_buf: 1741e705c121SKalle Valo if (idx < 0) 1742e705c121SKalle Valo kfree(dup_buf); 1743e705c121SKalle Valo return idx; 1744e705c121SKalle Valo } 1745e705c121SKalle Valo 1746e705c121SKalle Valo /* 1747e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1748e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1749e705c121SKalle Valo */ 1750e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1751e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1752e705c121SKalle Valo { 1753e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1754e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1755d490e097SJohannes Berg u8 group_id; 175639bdb17eSSharon Dvir u32 cmd_id; 1757e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1758e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1759e705c121SKalle Valo int cmd_index; 1760e705c121SKalle Valo struct iwl_device_cmd *cmd; 1761e705c121SKalle Valo struct iwl_cmd_meta *meta; 1762e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1763b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1764e705c121SKalle Valo 1765e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1766e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1767e705c121SKalle Valo * in the queue management code. */ 1768e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1769e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1770b2a3b1c1SSara Sharon txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1771b2a3b1c1SSara Sharon txq->write_ptr)) { 1772e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1773e705c121SKalle Valo return; 1774e705c121SKalle Valo } 1775e705c121SKalle Valo 1776e705c121SKalle Valo spin_lock_bh(&txq->lock); 1777e705c121SKalle Valo 17784ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1779e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1780e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 1781d490e097SJohannes Berg group_id = cmd->hdr.group_id; 178239bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1783e705c121SKalle Valo 17846983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, meta, txq, index); 1785e705c121SKalle Valo 1786e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1787e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1788e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1789e705c121SKalle Valo 1790e705c121SKalle Valo meta->source->resp_pkt = pkt; 1791e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1792e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1793e705c121SKalle Valo } 1794e705c121SKalle Valo 1795dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1796dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1797dcbb4746SEmmanuel Grumbach 1798e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1799e705c121SKalle Valo 1800e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1801e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1802e705c121SKalle Valo IWL_WARN(trans, 1803e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 180439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1805e705c121SKalle Valo } 1806e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1807e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 180839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1809e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1810e705c121SKalle Valo } 1811e705c121SKalle Valo 18124cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 18134cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 18144cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18154cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 18164cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18174cbb8e50SLuciano Coelho } 18184cbb8e50SLuciano Coelho 18194cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 18204cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 18214cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18224cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 18234cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18244cbb8e50SLuciano Coelho } 18254cbb8e50SLuciano Coelho 1826e705c121SKalle Valo meta->flags = 0; 1827e705c121SKalle Valo 1828e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1829e705c121SKalle Valo } 1830e705c121SKalle Valo 1831e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1832e705c121SKalle Valo 1833e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1834e705c121SKalle Valo struct iwl_host_cmd *cmd) 1835e705c121SKalle Valo { 1836e705c121SKalle Valo int ret; 1837e705c121SKalle Valo 1838e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1839e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1840e705c121SKalle Valo return -EINVAL; 1841e705c121SKalle Valo 1842e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1843e705c121SKalle Valo if (ret < 0) { 1844e705c121SKalle Valo IWL_ERR(trans, 1845e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 184639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1847e705c121SKalle Valo return ret; 1848e705c121SKalle Valo } 1849e705c121SKalle Valo return 0; 1850e705c121SKalle Valo } 1851e705c121SKalle Valo 1852e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1853e705c121SKalle Valo struct iwl_host_cmd *cmd) 1854e705c121SKalle Valo { 1855e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1856b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1857e705c121SKalle Valo int cmd_idx; 1858e705c121SKalle Valo int ret; 1859e705c121SKalle Valo 1860e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 186139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1862e705c121SKalle Valo 1863e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1864e705c121SKalle Valo &trans->status), 1865e705c121SKalle Valo "Command %s: a command is already active!\n", 186639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1867e705c121SKalle Valo return -EIO; 1868e705c121SKalle Valo 1869e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 187039bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1871e705c121SKalle Valo 187271b1230cSLuca Coelho if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 187371b1230cSLuca Coelho ret = wait_event_timeout(trans_pcie->d0i3_waitq, 187471b1230cSLuca Coelho pm_runtime_active(&trans_pcie->pci_dev->dev), 187571b1230cSLuca Coelho msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 187671b1230cSLuca Coelho if (!ret) { 187771b1230cSLuca Coelho IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 187871b1230cSLuca Coelho return -ETIMEDOUT; 187971b1230cSLuca Coelho } 188071b1230cSLuca Coelho } 188171b1230cSLuca Coelho 1882e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1883e705c121SKalle Valo if (cmd_idx < 0) { 1884e705c121SKalle Valo ret = cmd_idx; 1885e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1886e705c121SKalle Valo IWL_ERR(trans, 1887e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 188839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1889e705c121SKalle Valo return ret; 1890e705c121SKalle Valo } 1891e705c121SKalle Valo 1892e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1893e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1894e705c121SKalle Valo &trans->status), 1895e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1896e705c121SKalle Valo if (!ret) { 1897e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 189839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1899e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1900e705c121SKalle Valo 1901e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1902bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 1903e705c121SKalle Valo 1904e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1905e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 190639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1907e705c121SKalle Valo ret = -ETIMEDOUT; 1908e705c121SKalle Valo 1909e705c121SKalle Valo iwl_force_nmi(trans); 1910e705c121SKalle Valo iwl_trans_fw_error(trans); 1911e705c121SKalle Valo 1912e705c121SKalle Valo goto cancel; 1913e705c121SKalle Valo } 1914e705c121SKalle Valo 1915e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 19164290eaadSJohannes Berg iwl_trans_pcie_dump_regs(trans); 1917e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 191839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1919e705c121SKalle Valo dump_stack(); 1920e705c121SKalle Valo ret = -EIO; 1921e705c121SKalle Valo goto cancel; 1922e705c121SKalle Valo } 1923e705c121SKalle Valo 1924e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1925326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1926e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1927e705c121SKalle Valo ret = -ERFKILL; 1928e705c121SKalle Valo goto cancel; 1929e705c121SKalle Valo } 1930e705c121SKalle Valo 1931e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1932e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 193339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1934e705c121SKalle Valo ret = -EIO; 1935e705c121SKalle Valo goto cancel; 1936e705c121SKalle Valo } 1937e705c121SKalle Valo 1938e705c121SKalle Valo return 0; 1939e705c121SKalle Valo 1940e705c121SKalle Valo cancel: 1941e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1942e705c121SKalle Valo /* 1943e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1944e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1945e705c121SKalle Valo * in later, it will possibly set an invalid 1946e705c121SKalle Valo * address (cmd->meta.source). 1947e705c121SKalle Valo */ 1948b2a3b1c1SSara Sharon txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1949e705c121SKalle Valo } 1950e705c121SKalle Valo 1951e705c121SKalle Valo if (cmd->resp_pkt) { 1952e705c121SKalle Valo iwl_free_resp(cmd); 1953e705c121SKalle Valo cmd->resp_pkt = NULL; 1954e705c121SKalle Valo } 1955e705c121SKalle Valo 1956e705c121SKalle Valo return ret; 1957e705c121SKalle Valo } 1958e705c121SKalle Valo 1959e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1960e705c121SKalle Valo { 19612b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 1962f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1963f60c9e59SEmmanuel Grumbach return -ENODEV; 19642b3fae66SMatt Chen 1965e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1966326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1967e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1968e705c121SKalle Valo cmd->id); 1969e705c121SKalle Valo return -ERFKILL; 1970e705c121SKalle Valo } 1971e705c121SKalle Valo 1972e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 1973e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 1974e705c121SKalle Valo 1975e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 1976e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 1977e705c121SKalle Valo } 1978e705c121SKalle Valo 19793a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 19803a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 1981bb03927eSJohannes Berg struct iwl_cmd_meta *out_meta) 19823a0b2a42SEmmanuel Grumbach { 1983bb03927eSJohannes Berg u16 head_tb_len; 19843a0b2a42SEmmanuel Grumbach int i; 19853a0b2a42SEmmanuel Grumbach 19863a0b2a42SEmmanuel Grumbach /* 19873a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 19883a0b2a42SEmmanuel Grumbach * of skb's head, if any 19893a0b2a42SEmmanuel Grumbach */ 1990bb03927eSJohannes Berg head_tb_len = skb_headlen(skb) - hdr_len; 19913a0b2a42SEmmanuel Grumbach 1992bb03927eSJohannes Berg if (head_tb_len > 0) { 1993bb03927eSJohannes Berg dma_addr_t tb_phys = dma_map_single(trans->dev, 19943a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 1995bb03927eSJohannes Berg head_tb_len, DMA_TO_DEVICE); 1996bb03927eSJohannes Berg if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 19973a0b2a42SEmmanuel Grumbach return -EINVAL; 1998bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, 1999bf77ee2eSSara Sharon skb->data + hdr_len, 2000bf77ee2eSSara Sharon head_tb_len); 2001bb03927eSJohannes Berg iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false); 20023a0b2a42SEmmanuel Grumbach } 20033a0b2a42SEmmanuel Grumbach 20043a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 20053a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 20063a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 20073a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 20083a0b2a42SEmmanuel Grumbach int tb_idx; 20093a0b2a42SEmmanuel Grumbach 20103a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 20113a0b2a42SEmmanuel Grumbach continue; 20123a0b2a42SEmmanuel Grumbach 20133a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 20143a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 20153a0b2a42SEmmanuel Grumbach 20167d50d76eSJohannes Berg if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 20173a0b2a42SEmmanuel Grumbach return -EINVAL; 2018bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, 2019bf77ee2eSSara Sharon skb_frag_address(frag), 2020bf77ee2eSSara Sharon skb_frag_size(frag)); 20213a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 20223a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 20236e00a237SJohannes Berg if (tb_idx < 0) 20246e00a237SJohannes Berg return tb_idx; 20253a0b2a42SEmmanuel Grumbach 20263cd1980bSSara Sharon out_meta->tbs |= BIT(tb_idx); 20273a0b2a42SEmmanuel Grumbach } 20283a0b2a42SEmmanuel Grumbach 20293a0b2a42SEmmanuel Grumbach return 0; 20303a0b2a42SEmmanuel Grumbach } 20313a0b2a42SEmmanuel Grumbach 20326eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 20336ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 20346eb5e529SEmmanuel Grumbach { 20356eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20366eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 20376eb5e529SEmmanuel Grumbach 20386eb5e529SEmmanuel Grumbach if (!p->page) 20396eb5e529SEmmanuel Grumbach goto alloc; 20406eb5e529SEmmanuel Grumbach 20416eb5e529SEmmanuel Grumbach /* enough room on this page */ 20426eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 20436eb5e529SEmmanuel Grumbach return p; 20446eb5e529SEmmanuel Grumbach 20456eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 20466eb5e529SEmmanuel Grumbach __free_page(p->page); 20476eb5e529SEmmanuel Grumbach 20486eb5e529SEmmanuel Grumbach alloc: 20496eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 20506eb5e529SEmmanuel Grumbach if (!p->page) 20516eb5e529SEmmanuel Grumbach return NULL; 20526eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 20536eb5e529SEmmanuel Grumbach return p; 20546eb5e529SEmmanuel Grumbach } 20556eb5e529SEmmanuel Grumbach 20566eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 20576eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 20586eb5e529SEmmanuel Grumbach { 20596eb5e529SEmmanuel Grumbach if (ipv6) { 20606eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 20616eb5e529SEmmanuel Grumbach 20626eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 20636eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20646eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20656eb5e529SEmmanuel Grumbach } else { 20666eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 20676eb5e529SEmmanuel Grumbach 20686eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 20696eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 20706eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20716eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20726eb5e529SEmmanuel Grumbach } 20736eb5e529SEmmanuel Grumbach } 20746eb5e529SEmmanuel Grumbach 2075066fd29aSSara Sharon static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 20766eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 20776eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 20786eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 20796eb5e529SEmmanuel Grumbach { 208005e5a7e5SJohannes Berg struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 20816eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 20826eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 20836eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 20846eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 20856eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 20866eb5e529SEmmanuel Grumbach u8 *start_hdr; 20876eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 208821cb3222SJohannes Berg struct page **page_ptr; 20896eb5e529SEmmanuel Grumbach struct tso_t tso; 20906eb5e529SEmmanuel Grumbach 20916eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 20926eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 20936eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 20946eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 20956eb5e529SEmmanuel Grumbach 20966eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2097943309d4SEmmanuel Grumbach iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 20986983ba69SSara Sharon trans_pcie->tfd_size, 20998790fce4SJohannes Berg &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 21006eb5e529SEmmanuel Grumbach 21016eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 21026eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 21036eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 21046eb5e529SEmmanuel Grumbach amsdu_pad = 0; 21056eb5e529SEmmanuel Grumbach 21066eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 21076eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 21086eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 21096eb5e529SEmmanuel Grumbach 21106eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 21116eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 21126eb5e529SEmmanuel Grumbach if (!hdr_page) 21136eb5e529SEmmanuel Grumbach return -ENOMEM; 21146eb5e529SEmmanuel Grumbach 21156eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 21166eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 211721cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 211821cb3222SJohannes Berg *page_ptr = hdr_page->page; 21196eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 21206eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 21216eb5e529SEmmanuel Grumbach 21226eb5e529SEmmanuel Grumbach /* 21236eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 21246eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 21256eb5e529SEmmanuel Grumbach */ 21266eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 21276eb5e529SEmmanuel Grumbach 212805e5a7e5SJohannes Berg /* 212905e5a7e5SJohannes Berg * Remove the length of all the headers that we don't actually 213005e5a7e5SJohannes Berg * have in the MPDU by themselves, but that we duplicate into 213105e5a7e5SJohannes Berg * all the different MSDUs inside the A-MSDU. 213205e5a7e5SJohannes Berg */ 213305e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 213405e5a7e5SJohannes Berg 21356eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 21366eb5e529SEmmanuel Grumbach 21376eb5e529SEmmanuel Grumbach while (total_len) { 21386eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 21396eb5e529SEmmanuel Grumbach unsigned int data_left = 21406eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 21416eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 21426eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 21436eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 21446eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 214505e5a7e5SJohannes Berg u8 *iph, *subf_hdrs_start = hdr_page->pos; 21466eb5e529SEmmanuel Grumbach 21476eb5e529SEmmanuel Grumbach total_len -= data_left; 21486eb5e529SEmmanuel Grumbach 21496eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 21506eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 21516eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 21526eb5e529SEmmanuel Grumbach data_left)) & 0x3; 21536eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 21546eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21556eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 21566eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21576eb5e529SEmmanuel Grumbach 21586eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 21596eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 21606eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 21616eb5e529SEmmanuel Grumbach 21626eb5e529SEmmanuel Grumbach /* 21636eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 21646eb5e529SEmmanuel Grumbach * as MAC header. 21656eb5e529SEmmanuel Grumbach */ 21666eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 21676eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 21686eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 21696eb5e529SEmmanuel Grumbach 21706eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 21716eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 21726eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 21736eb5e529SEmmanuel Grumbach GFP_ATOMIC); 21747d50d76eSJohannes Berg if (!csum_skb) 21757d50d76eSJohannes Berg return -ENOMEM; 21766eb5e529SEmmanuel Grumbach 21776eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 21786eb5e529SEmmanuel Grumbach skb->protocol == 21796eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 21806eb5e529SEmmanuel Grumbach data_left); 21816eb5e529SEmmanuel Grumbach 218259ae1d12SJohannes Berg skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2183a52a8a4dSZhang Shengju skb_reset_transport_header(csum_skb); 21846eb5e529SEmmanuel Grumbach csum_skb->csum_start = 21856eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 21866eb5e529SEmmanuel Grumbach csum_skb->head; 21876eb5e529SEmmanuel Grumbach } 21886eb5e529SEmmanuel Grumbach 21896eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 21906eb5e529SEmmanuel Grumbach 21916eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 21926eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 21936eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 21946eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 21956eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 21967d50d76eSJohannes Berg return -EINVAL; 21976eb5e529SEmmanuel Grumbach } 21986eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 21996eb5e529SEmmanuel Grumbach hdr_tb_len, false); 2200bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, 22016eb5e529SEmmanuel Grumbach hdr_tb_len); 220205e5a7e5SJohannes Berg /* add this subframe's headers' length to the tx_cmd */ 220305e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 22046eb5e529SEmmanuel Grumbach 22056eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 22066eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 22076eb5e529SEmmanuel Grumbach 22086eb5e529SEmmanuel Grumbach /* put the payload */ 22096eb5e529SEmmanuel Grumbach while (data_left) { 22106eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 22116eb5e529SEmmanuel Grumbach data_left); 22126eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 22136eb5e529SEmmanuel Grumbach 22146eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 221559ae1d12SJohannes Berg skb_put_data(csum_skb, tso.data, size); 22166eb5e529SEmmanuel Grumbach 22176eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 22186eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 22196eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 22206eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22217d50d76eSJohannes Berg return -EINVAL; 22226eb5e529SEmmanuel Grumbach } 22236eb5e529SEmmanuel Grumbach 22246eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 22256eb5e529SEmmanuel Grumbach size, false); 2226bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 22276eb5e529SEmmanuel Grumbach size); 22286eb5e529SEmmanuel Grumbach 22296eb5e529SEmmanuel Grumbach data_left -= size; 22306eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 22316eb5e529SEmmanuel Grumbach } 22326eb5e529SEmmanuel Grumbach 22336eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 22346eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22356eb5e529SEmmanuel Grumbach __wsum csum; 22366eb5e529SEmmanuel Grumbach 22376eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 22386eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22396eb5e529SEmmanuel Grumbach csum_skb->len - 22406eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22416eb5e529SEmmanuel Grumbach 0); 22426eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22436eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 22446eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22456eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 22466eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 22476eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22486eb5e529SEmmanuel Grumbach } 22496eb5e529SEmmanuel Grumbach } 22506eb5e529SEmmanuel Grumbach 22516eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 22526eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 22536eb5e529SEmmanuel Grumbach 22546eb5e529SEmmanuel Grumbach return 0; 22556eb5e529SEmmanuel Grumbach } 22566eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 22576eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 22586eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 22596eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 22606eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 22616eb5e529SEmmanuel Grumbach { 22626eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 22636eb5e529SEmmanuel Grumbach WARN_ON(1); 22646eb5e529SEmmanuel Grumbach 22656eb5e529SEmmanuel Grumbach return -1; 22666eb5e529SEmmanuel Grumbach } 22676eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 22686eb5e529SEmmanuel Grumbach 2269e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2270e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2271e705c121SKalle Valo { 2272e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2273e705c121SKalle Valo struct ieee80211_hdr *hdr; 2274e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2275e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2276e705c121SKalle Valo struct iwl_txq *txq; 2277e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2278e705c121SKalle Valo void *tb1_addr; 22794fe10bc6SSara Sharon void *tfd; 22803a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2281e705c121SKalle Valo bool wait_write_ptr; 2282e705c121SKalle Valo __le16 fc; 2283e705c121SKalle Valo u8 hdr_len; 2284e705c121SKalle Valo u16 wifi_seq; 2285c772a3d3SSara Sharon bool amsdu; 2286e705c121SKalle Valo 2287b2a3b1c1SSara Sharon txq = trans_pcie->txq[txq_id]; 2288e705c121SKalle Valo 2289e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2290e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2291e705c121SKalle Valo return -EINVAL; 2292e705c121SKalle Valo 229341837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 229441837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 229541837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 229641837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 229741837ca9SEmmanuel Grumbach __wsum csum; 229841837ca9SEmmanuel Grumbach 229941837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 230041837ca9SEmmanuel Grumbach return -1; 230141837ca9SEmmanuel Grumbach 230241837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 230341837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 23043955525dSEmmanuel Grumbach 23053955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 230641837ca9SEmmanuel Grumbach } 230741837ca9SEmmanuel Grumbach 2308e705c121SKalle Valo if (skb_is_nonlinear(skb) && 23093cd1980bSSara Sharon skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2310e705c121SKalle Valo __skb_linearize(skb)) 2311e705c121SKalle Valo return -ENOMEM; 2312e705c121SKalle Valo 2313e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2314e705c121SKalle Valo * so there's no need to check if it's readable there 2315e705c121SKalle Valo */ 2316e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2317e705c121SKalle Valo fc = hdr->frame_control; 2318e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2319e705c121SKalle Valo 2320e705c121SKalle Valo spin_lock(&txq->lock); 2321e705c121SKalle Valo 23227b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < txq->high_mark) { 23233955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 23243955525dSEmmanuel Grumbach 23253955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 23267b3e42eaSGolan Ben Ami if (unlikely(iwl_queue_space(trans, txq) < 3)) { 232721cb3222SJohannes Berg struct iwl_device_cmd **dev_cmd_ptr; 23283955525dSEmmanuel Grumbach 232921cb3222SJohannes Berg dev_cmd_ptr = (void *)((u8 *)skb->cb + 233021cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 233121cb3222SJohannes Berg 233221cb3222SJohannes Berg *dev_cmd_ptr = dev_cmd; 23333955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 23343955525dSEmmanuel Grumbach 23353955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 23363955525dSEmmanuel Grumbach return 0; 23373955525dSEmmanuel Grumbach } 23383955525dSEmmanuel Grumbach } 23393955525dSEmmanuel Grumbach 2340e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2341e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2342e705c121SKalle Valo * the BA. 2343e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2344e705c121SKalle Valo */ 2345e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2346e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2347bb98ecd4SSara Sharon (wifi_seq & 0xff) != txq->write_ptr, 2348e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2349bb98ecd4SSara Sharon txq_id, wifi_seq, txq->write_ptr); 2350e705c121SKalle Valo 2351e705c121SKalle Valo /* Set up driver data for this TFD */ 2352bb98ecd4SSara Sharon txq->entries[txq->write_ptr].skb = skb; 2353bb98ecd4SSara Sharon txq->entries[txq->write_ptr].cmd = dev_cmd; 2354e705c121SKalle Valo 2355e705c121SKalle Valo dev_cmd->hdr.sequence = 2356e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2357bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr))); 2358e705c121SKalle Valo 2359bb98ecd4SSara Sharon tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2360e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2361e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2362e705c121SKalle Valo 2363e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2364e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2365e705c121SKalle Valo 2366e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2367bb98ecd4SSara Sharon out_meta = &txq->entries[txq->write_ptr].meta; 2368e705c121SKalle Valo out_meta->flags = 0; 2369e705c121SKalle Valo 2370e705c121SKalle Valo /* 2371e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2372e705c121SKalle Valo * and the 802.11 header - dword aligned size 2373e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2374e705c121SKalle Valo * setup of the first TB) 2375e705c121SKalle Valo */ 2376e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 23778de437c7SSara Sharon hdr_len - IWL_FIRST_TB_SIZE; 2378c772a3d3SSara Sharon /* do not align A-MSDU to dword as the subframe header aligns it */ 2379c772a3d3SSara Sharon amsdu = ieee80211_is_data_qos(fc) && 2380c772a3d3SSara Sharon (*ieee80211_get_qos_ctl(hdr) & 2381c772a3d3SSara Sharon IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2382c772a3d3SSara Sharon if (trans_pcie->sw_csum_tx || !amsdu) { 2383e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2384e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2385e705c121SKalle Valo if (tb1_len != len) 2386d172a5efSJohannes Berg tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2387c772a3d3SSara Sharon } else { 2388c772a3d3SSara Sharon tb1_len = len; 2389c772a3d3SSara Sharon } 2390e705c121SKalle Valo 239105e5a7e5SJohannes Berg /* 239205e5a7e5SJohannes Berg * The first TB points to bi-directional DMA data, we'll 239305e5a7e5SJohannes Berg * memcpy the data into it later. 239405e5a7e5SJohannes Berg */ 2395e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 23968de437c7SSara Sharon IWL_FIRST_TB_SIZE, true); 2397e705c121SKalle Valo 2398e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 23998de437c7SSara Sharon BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2400e705c121SKalle Valo 2401e705c121SKalle Valo /* map the data for TB1 */ 24028de437c7SSara Sharon tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2403e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2404e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2405e705c121SKalle Valo goto out_err; 2406e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2407e705c121SKalle Valo 2408bf77ee2eSSara Sharon trace_iwlwifi_dev_tx(trans->dev, skb, 2409bf77ee2eSSara Sharon iwl_pcie_get_tfd(trans, txq, 2410bf77ee2eSSara Sharon txq->write_ptr), 2411bf77ee2eSSara Sharon trans_pcie->tfd_size, 2412bf77ee2eSSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2413bf77ee2eSSara Sharon hdr_len); 2414bf77ee2eSSara Sharon 2415bf1ad897SEliad Peller /* 2416bf1ad897SEliad Peller * If gso_size wasn't set, don't give the frame "amsdu treatment" 2417bf1ad897SEliad Peller * (adding subframes, etc.). 2418bf1ad897SEliad Peller * This can happen in some testing flows when the amsdu was already 2419bf1ad897SEliad Peller * pre-built, and we just need to send the resulting skb. 2420bf1ad897SEliad Peller */ 2421bf1ad897SEliad Peller if (amsdu && skb_shinfo(skb)->gso_size) { 24226eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 24236eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 24246eb5e529SEmmanuel Grumbach tb1_len))) 2425e705c121SKalle Valo goto out_err; 2426bb03927eSJohannes Berg } else { 24270044f171SJohannes Berg struct sk_buff *frag; 24280044f171SJohannes Berg 2429bb03927eSJohannes Berg if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2430bb03927eSJohannes Berg out_meta))) 24316eb5e529SEmmanuel Grumbach goto out_err; 2432bb03927eSJohannes Berg 24330044f171SJohannes Berg skb_walk_frags(skb, frag) { 24340044f171SJohannes Berg if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0, 24350044f171SJohannes Berg out_meta))) 24360044f171SJohannes Berg goto out_err; 24370044f171SJohannes Berg } 24386eb5e529SEmmanuel Grumbach } 2439e705c121SKalle Valo 244005e5a7e5SJohannes Berg /* building the A-MSDU might have changed this data, so memcpy it now */ 244105e5a7e5SJohannes Berg memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 244205e5a7e5SJohannes Berg IWL_FIRST_TB_SIZE); 244305e5a7e5SJohannes Berg 2444943309d4SEmmanuel Grumbach tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 2445e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 24464fe10bc6SSara Sharon iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 24474fe10bc6SSara Sharon iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2448e705c121SKalle Valo 2449e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2450e705c121SKalle Valo 2451e705c121SKalle Valo /* start timer if queue currently empty */ 2452bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 2453e705c121SKalle Valo if (txq->wd_timeout) { 2454e705c121SKalle Valo /* 2455e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2456e705c121SKalle Valo * set the timer in remainder so that the timer will 2457e705c121SKalle Valo * be armed with the right value when the station will 2458e705c121SKalle Valo * wake up. 2459e705c121SKalle Valo */ 2460e705c121SKalle Valo if (!txq->frozen) 2461e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2462e705c121SKalle Valo jiffies + txq->wd_timeout); 2463e705c121SKalle Valo else 2464e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2465e705c121SKalle Valo } 2466bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 2467c24c7f58SLuca Coelho iwl_trans_ref(trans); 2468e705c121SKalle Valo } 2469e705c121SKalle Valo 2470e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 24717b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 2472e705c121SKalle Valo if (!wait_write_ptr) 2473e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2474e705c121SKalle Valo 2475e705c121SKalle Valo /* 2476e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2477e705c121SKalle Valo * and we will get a TX status notification eventually. 2478e705c121SKalle Valo */ 2479e705c121SKalle Valo spin_unlock(&txq->lock); 2480e705c121SKalle Valo return 0; 2481e705c121SKalle Valo out_err: 24827d50d76eSJohannes Berg iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 2483e705c121SKalle Valo spin_unlock(&txq->lock); 2484e705c121SKalle Valo return -1; 2485e705c121SKalle Valo } 2486