1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 44cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 5eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 6a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 7e705c121SKalle Valo * 8e705c121SKalle Valo * Portions of this file are derived from the ipw3945 project, as well 9e705c121SKalle Valo * as portions of the ieee80211 subsystem header files. 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 12e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 16e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 18e705c121SKalle Valo * more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License along with 21e705c121SKalle Valo * this program; if not, write to the Free Software Foundation, Inc., 22e705c121SKalle Valo * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 23e705c121SKalle Valo * 24e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 25e705c121SKalle Valo * file called LICENSE. 26e705c121SKalle Valo * 27e705c121SKalle Valo * Contact Information: 28cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 29e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30e705c121SKalle Valo * 31e705c121SKalle Valo *****************************************************************************/ 32e705c121SKalle Valo #include <linux/etherdevice.h> 336eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 34e705c121SKalle Valo #include <linux/slab.h> 35e705c121SKalle Valo #include <linux/sched.h> 3671b1230cSLuca Coelho #include <linux/pm_runtime.h> 376eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 386eb5e529SEmmanuel Grumbach #include <net/tso.h> 39e705c121SKalle Valo 40e705c121SKalle Valo #include "iwl-debug.h" 41e705c121SKalle Valo #include "iwl-csr.h" 42e705c121SKalle Valo #include "iwl-prph.h" 43e705c121SKalle Valo #include "iwl-io.h" 44e705c121SKalle Valo #include "iwl-scd.h" 45e705c121SKalle Valo #include "iwl-op-mode.h" 46e705c121SKalle Valo #include "internal.h" 47d172a5efSJohannes Berg #include "fw/api/tx.h" 48e705c121SKalle Valo 49e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 50e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 51e705c121SKalle Valo 52e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 53e705c121SKalle Valo * DMA services 54e705c121SKalle Valo * 55e705c121SKalle Valo * Theory of operation 56e705c121SKalle Valo * 57e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 58e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 59e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 60e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 61e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 62e705c121SKalle Valo * queue states. 63e705c121SKalle Valo * 64e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 65e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 66e705c121SKalle Valo * 67e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 68e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 69e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 70e705c121SKalle Valo * Tx queue resumed. 71e705c121SKalle Valo * 72e705c121SKalle Valo ***************************************************/ 73e22744afSSara Sharon 747b3e42eaSGolan Ben Ami int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q) 75e705c121SKalle Valo { 76e705c121SKalle Valo unsigned int max; 77e705c121SKalle Valo unsigned int used; 78e705c121SKalle Valo 79e705c121SKalle Valo /* 80e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 817b3e42eaSGolan Ben Ami * should always be less than max_tfd_queue_size elements in the queue. 827b3e42eaSGolan Ben Ami * If q->n_window is smaller than max_tfd_queue_size, there is no need 83e705c121SKalle Valo * to reserve any queue entries for this purpose. 84e705c121SKalle Valo */ 857b3e42eaSGolan Ben Ami if (q->n_window < trans->cfg->base_params->max_tfd_queue_size) 86e705c121SKalle Valo max = q->n_window; 87e705c121SKalle Valo else 887b3e42eaSGolan Ben Ami max = trans->cfg->base_params->max_tfd_queue_size - 1; 89e705c121SKalle Valo 90e705c121SKalle Valo /* 917b3e42eaSGolan Ben Ami * max_tfd_queue_size is a power of 2, so the following is equivalent to 927b3e42eaSGolan Ben Ami * modulo by max_tfd_queue_size and is well defined. 93e705c121SKalle Valo */ 947b3e42eaSGolan Ben Ami used = (q->write_ptr - q->read_ptr) & 957b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1); 96e705c121SKalle Valo 97e705c121SKalle Valo if (WARN_ON(used > max)) 98e705c121SKalle Valo return 0; 99e705c121SKalle Valo 100e705c121SKalle Valo return max - used; 101e705c121SKalle Valo } 102e705c121SKalle Valo 103e705c121SKalle Valo /* 104e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 105e705c121SKalle Valo */ 106b8e8d7ceSSara Sharon static int iwl_queue_init(struct iwl_txq *q, int slots_num) 107e705c121SKalle Valo { 108e705c121SKalle Valo q->n_window = slots_num; 109e705c121SKalle Valo 110e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 1114ecab561SEmmanuel Grumbach * iwl_pcie_get_cmd_index is broken. */ 112e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 113e705c121SKalle Valo return -EINVAL; 114e705c121SKalle Valo 115e705c121SKalle Valo q->low_mark = q->n_window / 4; 116e705c121SKalle Valo if (q->low_mark < 4) 117e705c121SKalle Valo q->low_mark = 4; 118e705c121SKalle Valo 119e705c121SKalle Valo q->high_mark = q->n_window / 8; 120e705c121SKalle Valo if (q->high_mark < 2) 121e705c121SKalle Valo q->high_mark = 2; 122e705c121SKalle Valo 123e705c121SKalle Valo q->write_ptr = 0; 124e705c121SKalle Valo q->read_ptr = 0; 125e705c121SKalle Valo 126e705c121SKalle Valo return 0; 127e705c121SKalle Valo } 128e705c121SKalle Valo 12913a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 130e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 131e705c121SKalle Valo { 132e705c121SKalle Valo if (WARN_ON(ptr->addr)) 133e705c121SKalle Valo return -EINVAL; 134e705c121SKalle Valo 135e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 136e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 137e705c121SKalle Valo if (!ptr->addr) 138e705c121SKalle Valo return -ENOMEM; 139e705c121SKalle Valo ptr->size = size; 140e705c121SKalle Valo return 0; 141e705c121SKalle Valo } 142e705c121SKalle Valo 14313a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 144e705c121SKalle Valo { 145e705c121SKalle Valo if (unlikely(!ptr->addr)) 146e705c121SKalle Valo return; 147e705c121SKalle Valo 148e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 149e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 150e705c121SKalle Valo } 151e705c121SKalle Valo 152e99e88a9SKees Cook static void iwl_pcie_txq_stuck_timer(struct timer_list *t) 153e705c121SKalle Valo { 154e99e88a9SKees Cook struct iwl_txq *txq = from_timer(txq, t, stuck_timer); 155e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 156e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 157e705c121SKalle Valo 158e705c121SKalle Valo spin_lock(&txq->lock); 159e705c121SKalle Valo /* check if triggered erroneously */ 160bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 161e705c121SKalle Valo spin_unlock(&txq->lock); 162e705c121SKalle Valo return; 163e705c121SKalle Valo } 164e705c121SKalle Valo spin_unlock(&txq->lock); 165e705c121SKalle Valo 16638398efbSSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 167e705c121SKalle Valo 168e705c121SKalle Valo iwl_force_nmi(trans); 169e705c121SKalle Valo } 170e705c121SKalle Valo 171e705c121SKalle Valo /* 172e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 173e705c121SKalle Valo */ 174e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 1754fe10bc6SSara Sharon struct iwl_txq *txq, u16 byte_cnt, 1764fe10bc6SSara Sharon int num_tbs) 177e705c121SKalle Valo { 178e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 179e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 180bb98ecd4SSara Sharon int write_ptr = txq->write_ptr; 181bb98ecd4SSara Sharon int txq_id = txq->id; 182e705c121SKalle Valo u8 sec_ctl = 0; 183e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 184e705c121SKalle Valo __le16 bc_ent; 185e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 186bb98ecd4SSara Sharon (void *)txq->entries[txq->write_ptr].cmd->payload; 187ab6c6445SSara Sharon u8 sta_id = tx_cmd->sta_id; 188e705c121SKalle Valo 189e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 190e705c121SKalle Valo 191e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 192e705c121SKalle Valo 193e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 194e705c121SKalle Valo case TX_CMD_SEC_CCM: 195e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 196e705c121SKalle Valo break; 197e705c121SKalle Valo case TX_CMD_SEC_TKIP: 198e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 199e705c121SKalle Valo break; 200e705c121SKalle Valo case TX_CMD_SEC_WEP: 201e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 202e705c121SKalle Valo break; 203e705c121SKalle Valo } 204e705c121SKalle Valo if (trans_pcie->bc_table_dword) 205e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 206e705c121SKalle Valo 207e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 208e705c121SKalle Valo return; 209e705c121SKalle Valo 210e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 211e705c121SKalle Valo 212e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 213e705c121SKalle Valo 214e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 215e705c121SKalle Valo scd_bc_tbl[txq_id]. 216e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 217e705c121SKalle Valo } 218e705c121SKalle Valo 219e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 220e705c121SKalle Valo struct iwl_txq *txq) 221e705c121SKalle Valo { 222e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 223e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 224e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 225bb98ecd4SSara Sharon int txq_id = txq->id; 226bb98ecd4SSara Sharon int read_ptr = txq->read_ptr; 227e705c121SKalle Valo u8 sta_id = 0; 228e705c121SKalle Valo __le16 bc_ent; 229e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 230bb98ecd4SSara Sharon (void *)txq->entries[read_ptr].cmd->payload; 231e705c121SKalle Valo 232e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 233e705c121SKalle Valo 234e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 235e705c121SKalle Valo sta_id = tx_cmd->sta_id; 236e705c121SKalle Valo 237e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 2384fe10bc6SSara Sharon 239e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 240e705c121SKalle Valo 241e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 242e705c121SKalle Valo scd_bc_tbl[txq_id]. 243e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 244e705c121SKalle Valo } 245e705c121SKalle Valo 246e705c121SKalle Valo /* 247e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 248e705c121SKalle Valo */ 249e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 250e705c121SKalle Valo struct iwl_txq *txq) 251e705c121SKalle Valo { 252e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 253e705c121SKalle Valo u32 reg = 0; 254bb98ecd4SSara Sharon int txq_id = txq->id; 255e705c121SKalle Valo 256e705c121SKalle Valo lockdep_assert_held(&txq->lock); 257e705c121SKalle Valo 258e705c121SKalle Valo /* 259e705c121SKalle Valo * explicitly wake up the NIC if: 260e705c121SKalle Valo * 1. shadow registers aren't enabled 261e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 262e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 263e705c121SKalle Valo */ 264e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 265e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 266e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 267e705c121SKalle Valo /* 268e705c121SKalle Valo * wake up nic if it's powered down ... 269e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 270e705c121SKalle Valo * time we'll skip this part. 271e705c121SKalle Valo */ 272e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 273e705c121SKalle Valo 274e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 275e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 276e705c121SKalle Valo txq_id, reg); 277e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 278a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 279e705c121SKalle Valo txq->need_update = true; 280e705c121SKalle Valo return; 281e705c121SKalle Valo } 282e705c121SKalle Valo } 283e705c121SKalle Valo 284e705c121SKalle Valo /* 285e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 286e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 287e705c121SKalle Valo */ 288bb98ecd4SSara Sharon IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 2890cd58eaaSEmmanuel Grumbach if (!txq->block) 2900cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 291bb98ecd4SSara Sharon txq->write_ptr | (txq_id << 8)); 292e705c121SKalle Valo } 293e705c121SKalle Valo 294e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 295e705c121SKalle Valo { 296e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 297e705c121SKalle Valo int i; 298e705c121SKalle Valo 299e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 300b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 301e705c121SKalle Valo 302f6eac740SMordechai Goodstein if (!test_bit(i, trans_pcie->queue_used)) 303f6eac740SMordechai Goodstein continue; 304f6eac740SMordechai Goodstein 305e705c121SKalle Valo spin_lock_bh(&txq->lock); 306b2a3b1c1SSara Sharon if (txq->need_update) { 307e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 308b2a3b1c1SSara Sharon txq->need_update = false; 309e705c121SKalle Valo } 310e705c121SKalle Valo spin_unlock_bh(&txq->lock); 311e705c121SKalle Valo } 312e705c121SKalle Valo } 313e705c121SKalle Valo 3146983ba69SSara Sharon static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 315cc2f41f8SJohannes Berg void *_tfd, u8 idx) 3166983ba69SSara Sharon { 3176983ba69SSara Sharon 3186983ba69SSara Sharon if (trans->cfg->use_tfh) { 319cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 320cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 3216983ba69SSara Sharon 3226983ba69SSara Sharon return (dma_addr_t)(le64_to_cpu(tb->addr)); 323cc2f41f8SJohannes Berg } else { 324cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 325cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 326cc2f41f8SJohannes Berg dma_addr_t addr = get_unaligned_le32(&tb->lo); 327cc2f41f8SJohannes Berg dma_addr_t hi_len; 3286983ba69SSara Sharon 329cc2f41f8SJohannes Berg if (sizeof(dma_addr_t) <= sizeof(u32)) 330e705c121SKalle Valo return addr; 331cc2f41f8SJohannes Berg 332cc2f41f8SJohannes Berg hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 333cc2f41f8SJohannes Berg 334cc2f41f8SJohannes Berg /* 335cc2f41f8SJohannes Berg * shift by 16 twice to avoid warnings on 32-bit 336cc2f41f8SJohannes Berg * (where this code never runs anyway due to the 337cc2f41f8SJohannes Berg * if statement above) 338cc2f41f8SJohannes Berg */ 339cc2f41f8SJohannes Berg return addr | ((hi_len << 16) << 16); 340cc2f41f8SJohannes Berg } 341e705c121SKalle Valo } 342e705c121SKalle Valo 3436983ba69SSara Sharon static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 3446983ba69SSara Sharon u8 idx, dma_addr_t addr, u16 len) 345e705c121SKalle Valo { 3466983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 3476983ba69SSara Sharon struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 3486983ba69SSara Sharon 349e705c121SKalle Valo u16 hi_n_len = len << 4; 350e705c121SKalle Valo 351e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 3527abf6fdeSJohannes Berg hi_n_len |= iwl_get_dma_hi_addr(addr); 353e705c121SKalle Valo 354e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 355e705c121SKalle Valo 3566983ba69SSara Sharon tfd_fh->num_tbs = idx + 1; 3576983ba69SSara Sharon } 358e705c121SKalle Valo 359cc2f41f8SJohannes Berg static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 360e705c121SKalle Valo { 3616983ba69SSara Sharon if (trans->cfg->use_tfh) { 362cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 3636983ba69SSara Sharon 364cc2f41f8SJohannes Berg return le16_to_cpu(tfd->num_tbs) & 0x1f; 365cc2f41f8SJohannes Berg } else { 366cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 367cc2f41f8SJohannes Berg 368cc2f41f8SJohannes Berg return tfd->num_tbs & 0x1f; 3696983ba69SSara Sharon } 370e705c121SKalle Valo } 371e705c121SKalle Valo 372e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 373e705c121SKalle Valo struct iwl_cmd_meta *meta, 3746983ba69SSara Sharon struct iwl_txq *txq, int index) 375e705c121SKalle Valo { 3763cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3773cd1980bSSara Sharon int i, num_tbs; 378943309d4SEmmanuel Grumbach void *tfd = iwl_pcie_get_tfd(trans, txq, index); 379e705c121SKalle Valo 380e705c121SKalle Valo /* Sanity check on number of chunks */ 3816983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 382e705c121SKalle Valo 3834437ba7eSEmmanuel Grumbach if (num_tbs > trans_pcie->max_tbs) { 384e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 385e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo 3898de437c7SSara Sharon /* first TB is never freed - it's the bidirectional DMA data */ 390e705c121SKalle Valo 391e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 3923cd1980bSSara Sharon if (meta->tbs & BIT(i)) 393e705c121SKalle Valo dma_unmap_page(trans->dev, 3946983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 3956983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, i), 396e705c121SKalle Valo DMA_TO_DEVICE); 397e705c121SKalle Valo else 398e705c121SKalle Valo dma_unmap_single(trans->dev, 3996983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, 4006983ba69SSara Sharon i), 4016983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, 4026983ba69SSara Sharon i), 403e705c121SKalle Valo DMA_TO_DEVICE); 404e705c121SKalle Valo } 4056983ba69SSara Sharon 4066983ba69SSara Sharon if (trans->cfg->use_tfh) { 4076983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4086983ba69SSara Sharon 4096983ba69SSara Sharon tfd_fh->num_tbs = 0; 4106983ba69SSara Sharon } else { 4116983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 4126983ba69SSara Sharon 4136983ba69SSara Sharon tfd_fh->num_tbs = 0; 4146983ba69SSara Sharon } 4156983ba69SSara Sharon 416e705c121SKalle Valo } 417e705c121SKalle Valo 418e705c121SKalle Valo /* 419e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 420e705c121SKalle Valo * @trans - transport private data 421e705c121SKalle Valo * @txq - tx queue 422e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 423e705c121SKalle Valo * 424e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 425e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 426e705c121SKalle Valo */ 4276b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 428e705c121SKalle Valo { 429e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 430e705c121SKalle Valo * idx is bounded by n_window 431e705c121SKalle Valo */ 432bb98ecd4SSara Sharon int rd_ptr = txq->read_ptr; 4334ecab561SEmmanuel Grumbach int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 434e705c121SKalle Valo 435e705c121SKalle Valo lockdep_assert_held(&txq->lock); 436e705c121SKalle Valo 437e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 438e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 439e705c121SKalle Valo */ 4406983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 441e705c121SKalle Valo 442e705c121SKalle Valo /* free SKB */ 443e705c121SKalle Valo if (txq->entries) { 444e705c121SKalle Valo struct sk_buff *skb; 445e705c121SKalle Valo 446e705c121SKalle Valo skb = txq->entries[idx].skb; 447e705c121SKalle Valo 448e705c121SKalle Valo /* Can be called from irqs-disabled context 449e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 450e705c121SKalle Valo * freed and that the queue is not empty - free the skb 451e705c121SKalle Valo */ 452e705c121SKalle Valo if (skb) { 453e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 454e705c121SKalle Valo txq->entries[idx].skb = NULL; 455e705c121SKalle Valo } 456e705c121SKalle Valo } 457e705c121SKalle Valo } 458e705c121SKalle Valo 459e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 460e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 461e705c121SKalle Valo { 4623cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4636983ba69SSara Sharon void *tfd; 464e705c121SKalle Valo u32 num_tbs; 465e705c121SKalle Valo 466bb98ecd4SSara Sharon tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 467e705c121SKalle Valo 468e705c121SKalle Valo if (reset) 4696983ba69SSara Sharon memset(tfd, 0, trans_pcie->tfd_size); 470e705c121SKalle Valo 4716983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 472e705c121SKalle Valo 4736983ba69SSara Sharon /* Each TFD can point to a maximum max_tbs Tx buffers */ 4743cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 475e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 4763cd1980bSSara Sharon trans_pcie->max_tbs); 477e705c121SKalle Valo return -EINVAL; 478e705c121SKalle Valo } 479e705c121SKalle Valo 480e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 481e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 482e705c121SKalle Valo return -EINVAL; 483e705c121SKalle Valo 4846983ba69SSara Sharon iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 485e705c121SKalle Valo 486e705c121SKalle Valo return num_tbs; 487e705c121SKalle Valo } 488e705c121SKalle Valo 48913a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 490b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 491e705c121SKalle Valo { 492e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4937b3e42eaSGolan Ben Ami size_t tfd_sz = trans_pcie->tfd_size * 4947b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size; 4958de437c7SSara Sharon size_t tb0_buf_sz; 496e705c121SKalle Valo int i; 497e705c121SKalle Valo 498e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 499e705c121SKalle Valo return -EINVAL; 500e705c121SKalle Valo 501e0498146SSara Sharon if (trans->cfg->use_tfh) 502e0498146SSara Sharon tfd_sz = trans_pcie->tfd_size * slots_num; 503e0498146SSara Sharon 504e99e88a9SKees Cook timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0); 505e705c121SKalle Valo txq->trans_pcie = trans_pcie; 506e705c121SKalle Valo 507bb98ecd4SSara Sharon txq->n_window = slots_num; 508e705c121SKalle Valo 509e705c121SKalle Valo txq->entries = kcalloc(slots_num, 510e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 511e705c121SKalle Valo GFP_KERNEL); 512e705c121SKalle Valo 513e705c121SKalle Valo if (!txq->entries) 514e705c121SKalle Valo goto error; 515e705c121SKalle Valo 516b8e8d7ceSSara Sharon if (cmd_queue) 517e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 518e705c121SKalle Valo txq->entries[i].cmd = 519e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 520e705c121SKalle Valo GFP_KERNEL); 521e705c121SKalle Valo if (!txq->entries[i].cmd) 522e705c121SKalle Valo goto error; 523e705c121SKalle Valo } 524e705c121SKalle Valo 525e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 526e705c121SKalle Valo * shared with device */ 527e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 528bb98ecd4SSara Sharon &txq->dma_addr, GFP_KERNEL); 529e705c121SKalle Valo if (!txq->tfds) 530e705c121SKalle Valo goto error; 531e705c121SKalle Valo 5328de437c7SSara Sharon BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 533e705c121SKalle Valo 5348de437c7SSara Sharon tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 535e705c121SKalle Valo 5368de437c7SSara Sharon txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 5378de437c7SSara Sharon &txq->first_tb_dma, 538e705c121SKalle Valo GFP_KERNEL); 5398de437c7SSara Sharon if (!txq->first_tb_bufs) 540e705c121SKalle Valo goto err_free_tfds; 541e705c121SKalle Valo 542e705c121SKalle Valo return 0; 543e705c121SKalle Valo err_free_tfds: 544bb98ecd4SSara Sharon dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 545e705c121SKalle Valo error: 546b8e8d7ceSSara Sharon if (txq->entries && cmd_queue) 547e705c121SKalle Valo for (i = 0; i < slots_num; i++) 548e705c121SKalle Valo kfree(txq->entries[i].cmd); 549e705c121SKalle Valo kfree(txq->entries); 550e705c121SKalle Valo txq->entries = NULL; 551e705c121SKalle Valo 552e705c121SKalle Valo return -ENOMEM; 553e705c121SKalle Valo 554e705c121SKalle Valo } 555e705c121SKalle Valo 55613a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 557b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 558e705c121SKalle Valo { 559e705c121SKalle Valo int ret; 5607b3e42eaSGolan Ben Ami u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size; 561e705c121SKalle Valo 562e705c121SKalle Valo txq->need_update = false; 563e705c121SKalle Valo 5647b3e42eaSGolan Ben Ami /* max_tfd_queue_size must be power-of-two size, otherwise 565e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 5667b3e42eaSGolan Ben Ami if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1), 5677b3e42eaSGolan Ben Ami "Max tfd queue size must be a power of two, but is %d", 5687b3e42eaSGolan Ben Ami tfd_queue_max_size)) 5697b3e42eaSGolan Ben Ami return -EINVAL; 570e705c121SKalle Valo 571e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 572b8e8d7ceSSara Sharon ret = iwl_queue_init(txq, slots_num); 573e705c121SKalle Valo if (ret) 574e705c121SKalle Valo return ret; 575e705c121SKalle Valo 576e705c121SKalle Valo spin_lock_init(&txq->lock); 577faead41cSJohannes Berg 578b8e8d7ceSSara Sharon if (cmd_queue) { 579faead41cSJohannes Berg static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 580faead41cSJohannes Berg 581faead41cSJohannes Berg lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 582faead41cSJohannes Berg } 583faead41cSJohannes Berg 5843955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 585e705c121SKalle Valo 586e705c121SKalle Valo return 0; 587e705c121SKalle Valo } 588e705c121SKalle Valo 5899bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 59021cb3222SJohannes Berg struct sk_buff *skb) 5916eb5e529SEmmanuel Grumbach { 59221cb3222SJohannes Berg struct page **page_ptr; 5936eb5e529SEmmanuel Grumbach 59421cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 5956eb5e529SEmmanuel Grumbach 59621cb3222SJohannes Berg if (*page_ptr) { 59721cb3222SJohannes Berg __free_page(*page_ptr); 59821cb3222SJohannes Berg *page_ptr = NULL; 5996eb5e529SEmmanuel Grumbach } 6006eb5e529SEmmanuel Grumbach } 6016eb5e529SEmmanuel Grumbach 60201d11cd1SSara Sharon static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 60301d11cd1SSara Sharon { 60401d11cd1SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 60501d11cd1SSara Sharon 60601d11cd1SSara Sharon lockdep_assert_held(&trans_pcie->reg_lock); 60701d11cd1SSara Sharon 60801d11cd1SSara Sharon if (trans_pcie->ref_cmd_in_flight) { 60901d11cd1SSara Sharon trans_pcie->ref_cmd_in_flight = false; 61001d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n"); 611c24c7f58SLuca Coelho iwl_trans_unref(trans); 61201d11cd1SSara Sharon } 61301d11cd1SSara Sharon 61401d11cd1SSara Sharon if (!trans->cfg->base_params->apmg_wake_up_wa) 61501d11cd1SSara Sharon return; 61601d11cd1SSara Sharon if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 61701d11cd1SSara Sharon return; 61801d11cd1SSara Sharon 61901d11cd1SSara Sharon trans_pcie->cmd_hold_nic_awake = false; 62001d11cd1SSara Sharon __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 621a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 62201d11cd1SSara Sharon } 62301d11cd1SSara Sharon 624e705c121SKalle Valo /* 625e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 626e705c121SKalle Valo */ 627e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 628e705c121SKalle Valo { 629e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 630b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 631e705c121SKalle Valo 632e705c121SKalle Valo spin_lock_bh(&txq->lock); 633bb98ecd4SSara Sharon while (txq->write_ptr != txq->read_ptr) { 634e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 635bb98ecd4SSara Sharon txq_id, txq->read_ptr); 6366eb5e529SEmmanuel Grumbach 6376eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 638bb98ecd4SSara Sharon struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 6396eb5e529SEmmanuel Grumbach 6406eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6416eb5e529SEmmanuel Grumbach continue; 6426eb5e529SEmmanuel Grumbach 64321cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 6446eb5e529SEmmanuel Grumbach } 645e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 6467b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 64701d11cd1SSara Sharon 648bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 64901d11cd1SSara Sharon unsigned long flags; 65001d11cd1SSara Sharon 65101d11cd1SSara Sharon spin_lock_irqsave(&trans_pcie->reg_lock, flags); 65201d11cd1SSara Sharon if (txq_id != trans_pcie->cmd_queue) { 65301d11cd1SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 654bb98ecd4SSara Sharon txq->id); 655c24c7f58SLuca Coelho iwl_trans_unref(trans); 65601d11cd1SSara Sharon } else { 65701d11cd1SSara Sharon iwl_pcie_clear_cmd_in_flight(trans); 65801d11cd1SSara Sharon } 65901d11cd1SSara Sharon spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 66001d11cd1SSara Sharon } 661e705c121SKalle Valo } 6623955525dSEmmanuel Grumbach 6633955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 6643955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 6653955525dSEmmanuel Grumbach 6663955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 6673955525dSEmmanuel Grumbach } 6683955525dSEmmanuel Grumbach 669e705c121SKalle Valo spin_unlock_bh(&txq->lock); 670e705c121SKalle Valo 671e705c121SKalle Valo /* just in case - this queue may have been stopped */ 672e705c121SKalle Valo iwl_wake_queue(trans, txq); 673e705c121SKalle Valo } 674e705c121SKalle Valo 675e705c121SKalle Valo /* 676e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 677e705c121SKalle Valo * @txq: Transmit queue to deallocate. 678e705c121SKalle Valo * 679e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 680e705c121SKalle Valo * Free all buffers. 681e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 682e705c121SKalle Valo */ 683e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 684e705c121SKalle Valo { 685e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 686b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 687e705c121SKalle Valo struct device *dev = trans->dev; 688e705c121SKalle Valo int i; 689e705c121SKalle Valo 690e705c121SKalle Valo if (WARN_ON(!txq)) 691e705c121SKalle Valo return; 692e705c121SKalle Valo 693e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 694e705c121SKalle Valo 695e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 696e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 697bb98ecd4SSara Sharon for (i = 0; i < txq->n_window; i++) { 698e705c121SKalle Valo kzfree(txq->entries[i].cmd); 699e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 700e705c121SKalle Valo } 701e705c121SKalle Valo 702e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 703e705c121SKalle Valo if (txq->tfds) { 704e705c121SKalle Valo dma_free_coherent(dev, 7057b3e42eaSGolan Ben Ami trans_pcie->tfd_size * 7067b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 707bb98ecd4SSara Sharon txq->tfds, txq->dma_addr); 708bb98ecd4SSara Sharon txq->dma_addr = 0; 709e705c121SKalle Valo txq->tfds = NULL; 710e705c121SKalle Valo 711e705c121SKalle Valo dma_free_coherent(dev, 712bb98ecd4SSara Sharon sizeof(*txq->first_tb_bufs) * txq->n_window, 7138de437c7SSara Sharon txq->first_tb_bufs, txq->first_tb_dma); 714e705c121SKalle Valo } 715e705c121SKalle Valo 716e705c121SKalle Valo kfree(txq->entries); 717e705c121SKalle Valo txq->entries = NULL; 718e705c121SKalle Valo 719e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 720e705c121SKalle Valo 721e705c121SKalle Valo /* 0-fill queue descriptor structure */ 722e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 723e705c121SKalle Valo } 724e705c121SKalle Valo 725e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 726e705c121SKalle Valo { 727e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 728e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 729e705c121SKalle Valo int chan; 730e705c121SKalle Valo u32 reg_val; 731e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 732e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 733e705c121SKalle Valo 734e705c121SKalle Valo /* make sure all queue are not stopped/used */ 735e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 736e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 737e705c121SKalle Valo 738e705c121SKalle Valo trans_pcie->scd_base_addr = 739e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 740e705c121SKalle Valo 741e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 742e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 743e705c121SKalle Valo 744e705c121SKalle Valo /* reset context data, TX status and translation data */ 745e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 746e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 747e705c121SKalle Valo NULL, clear_dwords); 748e705c121SKalle Valo 749e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 750e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 751e705c121SKalle Valo 752e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 753e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 754e705c121SKalle Valo */ 755e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 756e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 757e705c121SKalle Valo 758e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 759e705c121SKalle Valo trans_pcie->cmd_fifo, 760e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 761e705c121SKalle Valo 762e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 763e705c121SKalle Valo iwl_scd_activate_fifos(trans); 764e705c121SKalle Valo 765e705c121SKalle Valo /* Enable DMA channel */ 766e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 767e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 768e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 769e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 770e705c121SKalle Valo 771e705c121SKalle Valo /* Update FH chicken bits */ 772e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 773e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 774e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 775e705c121SKalle Valo 776e705c121SKalle Valo /* Enable L1-Active */ 7776e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 778e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 779e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 780e705c121SKalle Valo } 781e705c121SKalle Valo 782e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 783e705c121SKalle Valo { 784e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 785e705c121SKalle Valo int txq_id; 786e705c121SKalle Valo 78713a3a390SSara Sharon /* 78813a3a390SSara Sharon * we should never get here in gen2 trans mode return early to avoid 78913a3a390SSara Sharon * having invalid accesses 79013a3a390SSara Sharon */ 79113a3a390SSara Sharon if (WARN_ON_ONCE(trans->cfg->gen2)) 79213a3a390SSara Sharon return; 79313a3a390SSara Sharon 794e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 795e705c121SKalle Valo txq_id++) { 796b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 797e22744afSSara Sharon if (trans->cfg->use_tfh) 798e22744afSSara Sharon iwl_write_direct64(trans, 799e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 800bb98ecd4SSara Sharon txq->dma_addr); 801e22744afSSara Sharon else 802e22744afSSara Sharon iwl_write_direct32(trans, 803e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 804bb98ecd4SSara Sharon txq->dma_addr >> 8); 805e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 806bb98ecd4SSara Sharon txq->read_ptr = 0; 807bb98ecd4SSara Sharon txq->write_ptr = 0; 808e705c121SKalle Valo } 809e705c121SKalle Valo 810e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 811e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 812e705c121SKalle Valo trans_pcie->kw.dma >> 4); 813e705c121SKalle Valo 814e705c121SKalle Valo /* 815e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 816e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 817e705c121SKalle Valo * contain garbage. 818e705c121SKalle Valo */ 819e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 820e705c121SKalle Valo } 821e705c121SKalle Valo 822e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 823e705c121SKalle Valo { 824e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 825e705c121SKalle Valo unsigned long flags; 826e705c121SKalle Valo int ch, ret; 827e705c121SKalle Valo u32 mask = 0; 828e705c121SKalle Valo 829e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 830e705c121SKalle Valo 83123ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 832e705c121SKalle Valo goto out; 833e705c121SKalle Valo 834e705c121SKalle Valo /* Stop each Tx DMA channel */ 835e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 836e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 837e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 838e705c121SKalle Valo } 839e705c121SKalle Valo 840e705c121SKalle Valo /* Wait for DMA channels to be idle */ 841e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 842e705c121SKalle Valo if (ret < 0) 843e705c121SKalle Valo IWL_ERR(trans, 844e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 845e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 846e705c121SKalle Valo 847e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 848e705c121SKalle Valo 849e705c121SKalle Valo out: 850e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 851e705c121SKalle Valo } 852e705c121SKalle Valo 853e705c121SKalle Valo /* 854e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 855e705c121SKalle Valo */ 856e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 857e705c121SKalle Valo { 858e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 859e705c121SKalle Valo int txq_id; 860e705c121SKalle Valo 861e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 862e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 863e705c121SKalle Valo 864e705c121SKalle Valo /* Turn off all Tx DMA channels */ 865e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 866e705c121SKalle Valo 867e705c121SKalle Valo /* 868e705c121SKalle Valo * This function can be called before the op_mode disabled the 869e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 870e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 871e705c121SKalle Valo */ 872e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 873e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 874e705c121SKalle Valo 875e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 876b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 877e705c121SKalle Valo return 0; 878e705c121SKalle Valo 879e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 880e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 881e705c121SKalle Valo txq_id++) 882e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 883e705c121SKalle Valo 884e705c121SKalle Valo return 0; 885e705c121SKalle Valo } 886e705c121SKalle Valo 887e705c121SKalle Valo /* 888e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 889e705c121SKalle Valo * 890e705c121SKalle Valo * Destroy all TX DMA queues and structures 891e705c121SKalle Valo */ 892e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 893e705c121SKalle Valo { 894e705c121SKalle Valo int txq_id; 895e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 896e705c121SKalle Valo 897de74c455SSara Sharon memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 898de74c455SSara Sharon 899e705c121SKalle Valo /* Tx queues */ 900b2a3b1c1SSara Sharon if (trans_pcie->txq_memory) { 901e705c121SKalle Valo for (txq_id = 0; 902b2a3b1c1SSara Sharon txq_id < trans->cfg->base_params->num_of_queues; 903b2a3b1c1SSara Sharon txq_id++) { 904e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 905b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = NULL; 906b2a3b1c1SSara Sharon } 907e705c121SKalle Valo } 908e705c121SKalle Valo 909b2a3b1c1SSara Sharon kfree(trans_pcie->txq_memory); 910b2a3b1c1SSara Sharon trans_pcie->txq_memory = NULL; 911e705c121SKalle Valo 912e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 913e705c121SKalle Valo 914e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 915e705c121SKalle Valo } 916e705c121SKalle Valo 917e705c121SKalle Valo /* 918e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 919e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 920e705c121SKalle Valo */ 921e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 922e705c121SKalle Valo { 923e705c121SKalle Valo int ret; 924e705c121SKalle Valo int txq_id, slots_num; 925e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 9267b3e42eaSGolan Ben Ami u16 bc_tbls_size = trans->cfg->base_params->num_of_queues; 927e705c121SKalle Valo 9287b3e42eaSGolan Ben Ami bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 9297b3e42eaSGolan Ben Ami sizeof(struct iwl_gen3_bc_tbl) : 930e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 931e705c121SKalle Valo 932e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 933e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 934b2a3b1c1SSara Sharon if (WARN_ON(trans_pcie->txq_memory)) { 935e705c121SKalle Valo ret = -EINVAL; 936e705c121SKalle Valo goto error; 937e705c121SKalle Valo } 938e705c121SKalle Valo 939e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 9407b3e42eaSGolan Ben Ami bc_tbls_size); 941e705c121SKalle Valo if (ret) { 942e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 943e705c121SKalle Valo goto error; 944e705c121SKalle Valo } 945e705c121SKalle Valo 946e705c121SKalle Valo /* Alloc keep-warm buffer */ 947e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 948e705c121SKalle Valo if (ret) { 949e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 950e705c121SKalle Valo goto error; 951e705c121SKalle Valo } 952e705c121SKalle Valo 953b2a3b1c1SSara Sharon trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 954e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 955b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 956e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 957e705c121SKalle Valo ret = -ENOMEM; 958e705c121SKalle Valo goto error; 959e705c121SKalle Valo } 960e705c121SKalle Valo 961e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 962e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 963e705c121SKalle Valo txq_id++) { 964b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 965b8e8d7ceSSara Sharon 96601302f5bSSara Sharon slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 967b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 968b2a3b1c1SSara Sharon ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 969b8e8d7ceSSara Sharon slots_num, cmd_queue); 970e705c121SKalle Valo if (ret) { 971e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 972e705c121SKalle Valo goto error; 973e705c121SKalle Valo } 974b8e8d7ceSSara Sharon trans_pcie->txq[txq_id]->id = txq_id; 975e705c121SKalle Valo } 976e705c121SKalle Valo 977e705c121SKalle Valo return 0; 978e705c121SKalle Valo 979e705c121SKalle Valo error: 980e705c121SKalle Valo iwl_pcie_tx_free(trans); 981e705c121SKalle Valo 982e705c121SKalle Valo return ret; 983e705c121SKalle Valo } 984eda50cdeSSara Sharon 985e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 986e705c121SKalle Valo { 987e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 988e705c121SKalle Valo int ret; 989e705c121SKalle Valo int txq_id, slots_num; 990e705c121SKalle Valo bool alloc = false; 991e705c121SKalle Valo 992b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 993e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 994e705c121SKalle Valo if (ret) 995e705c121SKalle Valo goto error; 996e705c121SKalle Valo alloc = true; 997e705c121SKalle Valo } 998e705c121SKalle Valo 999e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1000e705c121SKalle Valo 1001e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 1002e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 1003e705c121SKalle Valo 1004e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 1005e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1006e705c121SKalle Valo trans_pcie->kw.dma >> 4); 1007e705c121SKalle Valo 1008e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1009e705c121SKalle Valo 1010e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1011e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1012e705c121SKalle Valo txq_id++) { 1013b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1014b8e8d7ceSSara Sharon 101501302f5bSSara Sharon slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 1016b2a3b1c1SSara Sharon ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1017b8e8d7ceSSara Sharon slots_num, cmd_queue); 1018e705c121SKalle Valo if (ret) { 1019e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1020e705c121SKalle Valo goto error; 1021e705c121SKalle Valo } 1022e705c121SKalle Valo 1023eda50cdeSSara Sharon /* 1024eda50cdeSSara Sharon * Tell nic where to find circular buffer of TFDs for a 1025eda50cdeSSara Sharon * given Tx queue, and enable the DMA channel used for that 1026eda50cdeSSara Sharon * queue. 1027eda50cdeSSara Sharon * Circular buffer (TFD queue in DRAM) physical base address 1028eda50cdeSSara Sharon */ 1029eda50cdeSSara Sharon iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1030b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->dma_addr >> 8); 1031ae79785fSSara Sharon } 1032e22744afSSara Sharon 1033e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1034e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 1035e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 1036e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 1037e705c121SKalle Valo 1038e705c121SKalle Valo return 0; 1039e705c121SKalle Valo error: 1040e705c121SKalle Valo /*Upon error, free only if we allocated something */ 1041e705c121SKalle Valo if (alloc) 1042e705c121SKalle Valo iwl_pcie_tx_free(trans); 1043e705c121SKalle Valo return ret; 1044e705c121SKalle Valo } 1045e705c121SKalle Valo 1046e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1047e705c121SKalle Valo { 1048e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1049e705c121SKalle Valo 1050e705c121SKalle Valo if (!txq->wd_timeout) 1051e705c121SKalle Valo return; 1052e705c121SKalle Valo 1053e705c121SKalle Valo /* 1054e705c121SKalle Valo * station is asleep and we send data - that must 1055e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 1056e705c121SKalle Valo */ 1057e705c121SKalle Valo if (txq->frozen) 1058e705c121SKalle Valo return; 1059e705c121SKalle Valo 1060e705c121SKalle Valo /* 1061e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 1062e705c121SKalle Valo * since we're making progress on this queue 1063e705c121SKalle Valo */ 1064bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 1065e705c121SKalle Valo del_timer(&txq->stuck_timer); 1066e705c121SKalle Valo else 1067e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1068e705c121SKalle Valo } 1069e705c121SKalle Valo 1070e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1071e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1072e705c121SKalle Valo struct sk_buff_head *skbs) 1073e705c121SKalle Valo { 1074e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1075b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 10767b3e42eaSGolan Ben Ami int tfd_num = iwl_pcie_get_cmd_index(txq, ssn); 10777b3e42eaSGolan Ben Ami int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1078e705c121SKalle Valo int last_to_free; 1079e705c121SKalle Valo 1080e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1081e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1082e705c121SKalle Valo return; 1083e705c121SKalle Valo 1084e705c121SKalle Valo spin_lock_bh(&txq->lock); 1085e705c121SKalle Valo 1086de74c455SSara Sharon if (!test_bit(txq_id, trans_pcie->queue_used)) { 1087e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1088e705c121SKalle Valo txq_id, ssn); 1089e705c121SKalle Valo goto out; 1090e705c121SKalle Valo } 1091e705c121SKalle Valo 10927b3e42eaSGolan Ben Ami if (read_ptr == tfd_num) 1093e705c121SKalle Valo goto out; 1094e705c121SKalle Valo 1095e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1096bb98ecd4SSara Sharon txq_id, txq->read_ptr, tfd_num, ssn); 1097e705c121SKalle Valo 1098e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1099e705c121SKalle Valo * the last we will free. This one must be used */ 11007b3e42eaSGolan Ben Ami last_to_free = iwl_queue_dec_wrap(trans, tfd_num); 1101e705c121SKalle Valo 1102bb98ecd4SSara Sharon if (!iwl_queue_used(txq, last_to_free)) { 1103e705c121SKalle Valo IWL_ERR(trans, 1104e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 11057b3e42eaSGolan Ben Ami __func__, txq_id, last_to_free, 11067b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1107bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1108e705c121SKalle Valo goto out; 1109e705c121SKalle Valo } 1110e705c121SKalle Valo 1111e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1112e705c121SKalle Valo goto out; 1113e705c121SKalle Valo 1114e705c121SKalle Valo for (; 11157b3e42eaSGolan Ben Ami read_ptr != tfd_num; 11167b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr), 11177b3e42eaSGolan Ben Ami read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) { 11187b3e42eaSGolan Ben Ami struct sk_buff *skb = txq->entries[read_ptr].skb; 1119e705c121SKalle Valo 11206eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1121e705c121SKalle Valo continue; 1122e705c121SKalle Valo 112321cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 11246eb5e529SEmmanuel Grumbach 11256eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1126e705c121SKalle Valo 11277b3e42eaSGolan Ben Ami txq->entries[read_ptr].skb = NULL; 1128e705c121SKalle Valo 11294fe10bc6SSara Sharon if (!trans->cfg->use_tfh) 1130e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1131e705c121SKalle Valo 1132e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1133e705c121SKalle Valo } 1134e705c121SKalle Valo 1135e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1136e705c121SKalle Valo 11377b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark && 11383955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1139685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 11403955525dSEmmanuel Grumbach 1141685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1142685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 11433955525dSEmmanuel Grumbach 11443955525dSEmmanuel Grumbach /* 11453955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 11463955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 11473955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 11483955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 11493955525dSEmmanuel Grumbach * later. 11503955525dSEmmanuel Grumbach */ 11513955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 11523955525dSEmmanuel Grumbach 1153685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1154685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 115521cb3222SJohannes Berg struct iwl_device_cmd *dev_cmd_ptr; 115621cb3222SJohannes Berg 115721cb3222SJohannes Berg dev_cmd_ptr = *(void **)((u8 *)skb->cb + 115821cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 11593955525dSEmmanuel Grumbach 11603955525dSEmmanuel Grumbach /* 11613955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 11623955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 11633955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 11643955525dSEmmanuel Grumbach */ 1165f79b8f9dSEmmanuel Grumbach iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id); 11663955525dSEmmanuel Grumbach } 11673955525dSEmmanuel Grumbach spin_lock_bh(&txq->lock); 11683955525dSEmmanuel Grumbach 11697b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark) 1170e705c121SKalle Valo iwl_wake_queue(trans, txq); 11713955525dSEmmanuel Grumbach } 1172e705c121SKalle Valo 1173bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1174bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id); 1175c24c7f58SLuca Coelho iwl_trans_unref(trans); 1176e705c121SKalle Valo } 1177e705c121SKalle Valo 1178e705c121SKalle Valo out: 1179e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1180e705c121SKalle Valo } 1181e705c121SKalle Valo 1182e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1183e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1184e705c121SKalle Valo { 1185e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1186a8cbb46fSGolan Ben Ami const struct iwl_cfg *cfg = trans->cfg; 1187e705c121SKalle Valo int ret; 1188e705c121SKalle Valo 1189e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1190e705c121SKalle Valo 11912b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 11922b3fae66SMatt Chen if (trans_pcie->scheduled_for_removal) 11932b3fae66SMatt Chen return -EIO; 11942b3fae66SMatt Chen 1195e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_IDLE) && 1196e705c121SKalle Valo !trans_pcie->ref_cmd_in_flight) { 1197e705c121SKalle Valo trans_pcie->ref_cmd_in_flight = true; 1198e705c121SKalle Valo IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 1199c24c7f58SLuca Coelho iwl_trans_ref(trans); 1200e705c121SKalle Valo } 1201e705c121SKalle Valo 1202e705c121SKalle Valo /* 1203e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1204e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1205e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1206e705c121SKalle Valo * apmg_wake_up_wa set. 1207e705c121SKalle Valo */ 1208a8cbb46fSGolan Ben Ami if (cfg->base_params->apmg_wake_up_wa && 1209e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1210e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1211a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1212e705c121SKalle Valo 1213e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1214a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_val_mac_access_en), 1215a8cbb46fSGolan Ben Ami (BIT(cfg->csr->flag_mac_clock_ready) | 1216e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1217e705c121SKalle Valo 15000); 1218e705c121SKalle Valo if (ret < 0) { 1219e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1220a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1221e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1222e705c121SKalle Valo return -EIO; 1223e705c121SKalle Valo } 1224e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1225e705c121SKalle Valo } 1226e705c121SKalle Valo 1227e705c121SKalle Valo return 0; 1228e705c121SKalle Valo } 1229e705c121SKalle Valo 1230e705c121SKalle Valo /* 1231e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1232e705c121SKalle Valo * 1233e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1234e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1235e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1236e705c121SKalle Valo */ 123789d5e833SGolan Ben Ami void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1238e705c121SKalle Valo { 1239e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1240b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1241e705c121SKalle Valo unsigned long flags; 1242e705c121SKalle Valo int nfreed = 0; 1243f5955a6cSGolan Ben Ami u16 r; 1244e705c121SKalle Valo 1245e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1246e705c121SKalle Valo 1247f5955a6cSGolan Ben Ami idx = iwl_pcie_get_cmd_index(txq, idx); 1248f5955a6cSGolan Ben Ami r = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1249f5955a6cSGolan Ben Ami 12507b3e42eaSGolan Ben Ami if (idx >= trans->cfg->base_params->max_tfd_queue_size || 12517b3e42eaSGolan Ben Ami (!iwl_queue_used(txq, idx))) { 1252e705c121SKalle Valo IWL_ERR(trans, 1253e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 12547b3e42eaSGolan Ben Ami __func__, txq_id, idx, 12557b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1256bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1257e705c121SKalle Valo return; 1258e705c121SKalle Valo } 1259e705c121SKalle Valo 12607b3e42eaSGolan Ben Ami for (idx = iwl_queue_inc_wrap(trans, idx); r != idx; 12617b3e42eaSGolan Ben Ami r = iwl_queue_inc_wrap(trans, r)) { 12627b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1263e705c121SKalle Valo 1264e705c121SKalle Valo if (nfreed++ > 0) { 1265e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1266f5955a6cSGolan Ben Ami idx, txq->write_ptr, r); 1267e705c121SKalle Valo iwl_force_nmi(trans); 1268e705c121SKalle Valo } 1269e705c121SKalle Valo } 1270e705c121SKalle Valo 1271bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1272e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1273e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1274e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1275e705c121SKalle Valo } 1276e705c121SKalle Valo 1277e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1278e705c121SKalle Valo } 1279e705c121SKalle Valo 1280e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1281e705c121SKalle Valo u16 txq_id) 1282e705c121SKalle Valo { 1283e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1284e705c121SKalle Valo u32 tbl_dw_addr; 1285e705c121SKalle Valo u32 tbl_dw; 1286e705c121SKalle Valo u16 scd_q2ratid; 1287e705c121SKalle Valo 1288e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1289e705c121SKalle Valo 1290e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1291e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1292e705c121SKalle Valo 1293e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1294e705c121SKalle Valo 1295e705c121SKalle Valo if (txq_id & 0x1) 1296e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1297e705c121SKalle Valo else 1298e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1299e705c121SKalle Valo 1300e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1301e705c121SKalle Valo 1302e705c121SKalle Valo return 0; 1303e705c121SKalle Valo } 1304e705c121SKalle Valo 1305e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1306e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1307e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1308e705c121SKalle Valo 1309dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1310e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1311e705c121SKalle Valo unsigned int wdg_timeout) 1312e705c121SKalle Valo { 1313e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1314b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1315e705c121SKalle Valo int fifo = -1; 1316dcfbd67bSEmmanuel Grumbach bool scd_bug = false; 1317e705c121SKalle Valo 1318e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1319e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1320e705c121SKalle Valo 1321e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1322e705c121SKalle Valo 1323e705c121SKalle Valo if (cfg) { 1324e705c121SKalle Valo fifo = cfg->fifo; 1325e705c121SKalle Valo 1326e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1327e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1328e705c121SKalle Valo trans_pcie->scd_set_active) 1329e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1330e705c121SKalle Valo 1331e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1332e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1333e705c121SKalle Valo 1334e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1335e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1336e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1337e705c121SKalle Valo 1338e705c121SKalle Valo if (cfg->aggregate) { 1339e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1340e705c121SKalle Valo 1341e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1342e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1343e705c121SKalle Valo 1344e705c121SKalle Valo /* enable aggregations for the queue */ 1345e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1346e705c121SKalle Valo txq->ampdu = true; 1347e705c121SKalle Valo } else { 1348e705c121SKalle Valo /* 1349e705c121SKalle Valo * disable aggregations for the queue, this will also 1350e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1351e705c121SKalle Valo * since it is now a non-AGG queue. 1352e705c121SKalle Valo */ 1353e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1354e705c121SKalle Valo 1355bb98ecd4SSara Sharon ssn = txq->read_ptr; 1356e705c121SKalle Valo } 1357dcfbd67bSEmmanuel Grumbach } else { 1358dcfbd67bSEmmanuel Grumbach /* 1359dcfbd67bSEmmanuel Grumbach * If we need to move the SCD write pointer by steps of 1360dcfbd67bSEmmanuel Grumbach * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1361dcfbd67bSEmmanuel Grumbach * the op_mode know by returning true later. 1362dcfbd67bSEmmanuel Grumbach * Do this only in case cfg is NULL since this trick can 1363dcfbd67bSEmmanuel Grumbach * be done only if we have DQA enabled which is true for mvm 1364dcfbd67bSEmmanuel Grumbach * only. And mvm never sets a cfg pointer. 1365dcfbd67bSEmmanuel Grumbach * This is really ugly, but this is the easiest way out for 1366dcfbd67bSEmmanuel Grumbach * this sad hardware issue. 1367dcfbd67bSEmmanuel Grumbach * This bug has been fixed on devices 9000 and up. 1368dcfbd67bSEmmanuel Grumbach */ 1369dcfbd67bSEmmanuel Grumbach scd_bug = !trans->cfg->mq_rx_supported && 1370dcfbd67bSEmmanuel Grumbach !((ssn - txq->write_ptr) & 0x3f) && 1371dcfbd67bSEmmanuel Grumbach (ssn != txq->write_ptr); 1372dcfbd67bSEmmanuel Grumbach if (scd_bug) 1373dcfbd67bSEmmanuel Grumbach ssn++; 1374e705c121SKalle Valo } 1375e705c121SKalle Valo 1376e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1377e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1378bb98ecd4SSara Sharon txq->read_ptr = (ssn & 0xff); 1379bb98ecd4SSara Sharon txq->write_ptr = (ssn & 0xff); 1380e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1381e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1382e705c121SKalle Valo 1383e705c121SKalle Valo if (cfg) { 1384e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1385e705c121SKalle Valo 1386e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1387e705c121SKalle Valo 1388e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1389e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1390e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1391e705c121SKalle Valo iwl_trans_write_mem32(trans, 1392e705c121SKalle Valo trans_pcie->scd_base_addr + 1393e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1394f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1395f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1396e705c121SKalle Valo 1397e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1398e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1399e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1400e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1401e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1402e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1403e705c121SKalle Valo 1404e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1405e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1406e705c121SKalle Valo trans_pcie->scd_set_active) 1407e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1408e705c121SKalle Valo 1409e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1410e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1411e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1412e705c121SKalle Valo } else { 1413e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1414e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1415e705c121SKalle Valo txq_id, ssn & 0xff); 1416e705c121SKalle Valo } 1417dcfbd67bSEmmanuel Grumbach 1418dcfbd67bSEmmanuel Grumbach return scd_bug; 1419e705c121SKalle Valo } 1420e705c121SKalle Valo 142142db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 142242db09c1SLiad Kaufman bool shared_mode) 142342db09c1SLiad Kaufman { 142442db09c1SLiad Kaufman struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1425b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 142642db09c1SLiad Kaufman 142742db09c1SLiad Kaufman txq->ampdu = !shared_mode; 142842db09c1SLiad Kaufman } 142942db09c1SLiad Kaufman 1430e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1431e705c121SKalle Valo bool configure_scd) 1432e705c121SKalle Valo { 1433e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1434e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1435e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1436e705c121SKalle Valo static const u32 zero_val[4] = {}; 1437e705c121SKalle Valo 1438b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1439b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen = false; 1440e705c121SKalle Valo 1441e705c121SKalle Valo /* 1442e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1443e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1444e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1445e705c121SKalle Valo * stop_device. 1446e705c121SKalle Valo */ 1447e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1448e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1449e705c121SKalle Valo "queue %d not used", txq_id); 1450e705c121SKalle Valo return; 1451e705c121SKalle Valo } 1452e705c121SKalle Valo 1453e705c121SKalle Valo if (configure_scd) { 1454e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1455e705c121SKalle Valo 1456e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1457e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1458e705c121SKalle Valo } 1459e705c121SKalle Valo 1460e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1461b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->ampdu = false; 1462e705c121SKalle Valo 1463e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1464e705c121SKalle Valo } 1465e705c121SKalle Valo 1466e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1467e705c121SKalle Valo 1468e705c121SKalle Valo /* 1469e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1470e705c121SKalle Valo * @priv: device private data point 1471e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1472e705c121SKalle Valo * 1473e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1474e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1475e705c121SKalle Valo * command queue. 1476e705c121SKalle Valo */ 1477e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1478e705c121SKalle Valo struct iwl_host_cmd *cmd) 1479e705c121SKalle Valo { 1480e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1481b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1482e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1483e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1484e705c121SKalle Valo unsigned long flags; 1485e705c121SKalle Valo void *dup_buf = NULL; 1486e705c121SKalle Valo dma_addr_t phys_addr; 1487e705c121SKalle Valo int idx; 14888de437c7SSara Sharon u16 copy_size, cmd_size, tb0_size; 1489e705c121SKalle Valo bool had_nocopy = false; 1490e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1491e705c121SKalle Valo int i, ret; 1492e705c121SKalle Valo u32 cmd_pos; 1493e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1494e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1495e705c121SKalle Valo 14965b88792cSSara Sharon if (WARN(!trans->wide_cmd_header && 1497e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1498e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1499e705c121SKalle Valo return -EINVAL; 1500e705c121SKalle Valo 1501e705c121SKalle Valo if (group_id != 0) { 1502e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1503e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1504e705c121SKalle Valo } else { 1505e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1506e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1507e705c121SKalle Valo } 1508e705c121SKalle Valo 1509e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1510e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1511e705c121SKalle Valo 1512e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1513e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1514e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1515e705c121SKalle Valo 1516e705c121SKalle Valo if (!cmd->len[i]) 1517e705c121SKalle Valo continue; 1518e705c121SKalle Valo 15198de437c7SSara Sharon /* need at least IWL_FIRST_TB_SIZE copied */ 15208de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 15218de437c7SSara Sharon int copy = IWL_FIRST_TB_SIZE - copy_size; 1522e705c121SKalle Valo 1523e705c121SKalle Valo if (copy > cmdlen[i]) 1524e705c121SKalle Valo copy = cmdlen[i]; 1525e705c121SKalle Valo cmdlen[i] -= copy; 1526e705c121SKalle Valo cmddata[i] += copy; 1527e705c121SKalle Valo copy_size += copy; 1528e705c121SKalle Valo } 1529e705c121SKalle Valo 1530e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1531e705c121SKalle Valo had_nocopy = true; 1532e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1533e705c121SKalle Valo idx = -EINVAL; 1534e705c121SKalle Valo goto free_dup_buf; 1535e705c121SKalle Valo } 1536e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1537e705c121SKalle Valo /* 1538e705c121SKalle Valo * This is also a chunk that isn't copied 1539e705c121SKalle Valo * to the static buffer so set had_nocopy. 1540e705c121SKalle Valo */ 1541e705c121SKalle Valo had_nocopy = true; 1542e705c121SKalle Valo 1543e705c121SKalle Valo /* only allowed once */ 1544e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1545e705c121SKalle Valo idx = -EINVAL; 1546e705c121SKalle Valo goto free_dup_buf; 1547e705c121SKalle Valo } 1548e705c121SKalle Valo 1549e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1550e705c121SKalle Valo GFP_ATOMIC); 1551e705c121SKalle Valo if (!dup_buf) 1552e705c121SKalle Valo return -ENOMEM; 1553e705c121SKalle Valo } else { 1554e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1555e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1556e705c121SKalle Valo idx = -EINVAL; 1557e705c121SKalle Valo goto free_dup_buf; 1558e705c121SKalle Valo } 1559e705c121SKalle Valo copy_size += cmdlen[i]; 1560e705c121SKalle Valo } 1561e705c121SKalle Valo cmd_size += cmd->len[i]; 1562e705c121SKalle Valo } 1563e705c121SKalle Valo 1564e705c121SKalle Valo /* 1565e705c121SKalle Valo * If any of the command structures end up being larger than 1566e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1567e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1568e705c121SKalle Valo * increase the size of the buffers. 1569e705c121SKalle Valo */ 1570e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1571e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 157239bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 157339bdb17eSSharon Dvir cmd->id, copy_size)) { 1574e705c121SKalle Valo idx = -EINVAL; 1575e705c121SKalle Valo goto free_dup_buf; 1576e705c121SKalle Valo } 1577e705c121SKalle Valo 1578e705c121SKalle Valo spin_lock_bh(&txq->lock); 1579e705c121SKalle Valo 15807b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1581e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1582e705c121SKalle Valo 1583e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1584e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1585e705c121SKalle Valo idx = -ENOSPC; 1586e705c121SKalle Valo goto free_dup_buf; 1587e705c121SKalle Valo } 1588e705c121SKalle Valo 15894ecab561SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1590e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1591e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1592e705c121SKalle Valo 1593e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1594e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1595e705c121SKalle Valo out_meta->source = cmd; 1596e705c121SKalle Valo 1597e705c121SKalle Valo /* set up the header */ 1598e705c121SKalle Valo if (group_id != 0) { 1599e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1600e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1601e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1602e705c121SKalle Valo out_cmd->hdr_wide.length = 1603e705c121SKalle Valo cpu_to_le16(cmd_size - 1604e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1605e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1606e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1607e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1608bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1609e705c121SKalle Valo 1610e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1611e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1612e705c121SKalle Valo } else { 1613e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1614e705c121SKalle Valo out_cmd->hdr.sequence = 1615e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1616bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1617e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1618e705c121SKalle Valo 1619e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1620e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1621e705c121SKalle Valo } 1622e705c121SKalle Valo 1623e705c121SKalle Valo /* and copy the data that needs to be copied */ 1624e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1625e705c121SKalle Valo int copy; 1626e705c121SKalle Valo 1627e705c121SKalle Valo if (!cmd->len[i]) 1628e705c121SKalle Valo continue; 1629e705c121SKalle Valo 1630e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1631e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1632e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1633e705c121SKalle Valo copy = cmd->len[i]; 1634e705c121SKalle Valo 1635e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1636e705c121SKalle Valo cmd_pos += copy; 1637e705c121SKalle Valo copy_size += copy; 1638e705c121SKalle Valo continue; 1639e705c121SKalle Valo } 1640e705c121SKalle Valo 1641e705c121SKalle Valo /* 16428de437c7SSara Sharon * Otherwise we need at least IWL_FIRST_TB_SIZE copied 16438de437c7SSara Sharon * in total (for bi-directional DMA), but copy up to what 1644e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1645e705c121SKalle Valo */ 1646e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1647e705c121SKalle Valo 1648e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1649e705c121SKalle Valo cmd_pos += copy; 1650e705c121SKalle Valo 1651e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 16528de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 16538de437c7SSara Sharon copy = IWL_FIRST_TB_SIZE - copy_size; 1654e705c121SKalle Valo 1655e705c121SKalle Valo if (copy > cmd->len[i]) 1656e705c121SKalle Valo copy = cmd->len[i]; 1657e705c121SKalle Valo copy_size += copy; 1658e705c121SKalle Valo } 1659e705c121SKalle Valo } 1660e705c121SKalle Valo 1661e705c121SKalle Valo IWL_DEBUG_HC(trans, 1662e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 166339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1664e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1665e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1666bb98ecd4SSara Sharon cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1667e705c121SKalle Valo 16688de437c7SSara Sharon /* start the TFD with the minimum copy bytes */ 16698de437c7SSara Sharon tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 16708de437c7SSara Sharon memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1671e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 16728de437c7SSara Sharon iwl_pcie_get_first_tb_dma(txq, idx), 16738de437c7SSara Sharon tb0_size, true); 1674e705c121SKalle Valo 1675e705c121SKalle Valo /* map first command fragment, if any remains */ 16768de437c7SSara Sharon if (copy_size > tb0_size) { 1677e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 16788de437c7SSara Sharon ((u8 *)&out_cmd->hdr) + tb0_size, 16798de437c7SSara Sharon copy_size - tb0_size, 1680e705c121SKalle Valo DMA_TO_DEVICE); 1681e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1682bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1683bb98ecd4SSara Sharon txq->write_ptr); 1684e705c121SKalle Valo idx = -ENOMEM; 1685e705c121SKalle Valo goto out; 1686e705c121SKalle Valo } 1687e705c121SKalle Valo 1688e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 16898de437c7SSara Sharon copy_size - tb0_size, false); 1690e705c121SKalle Valo } 1691e705c121SKalle Valo 1692e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1693e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1694e705c121SKalle Valo const void *data = cmddata[i]; 1695e705c121SKalle Valo 1696e705c121SKalle Valo if (!cmdlen[i]) 1697e705c121SKalle Valo continue; 1698e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1699e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1700e705c121SKalle Valo continue; 1701e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1702e705c121SKalle Valo data = dup_buf; 1703e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1704e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1705e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1706bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1707bb98ecd4SSara Sharon txq->write_ptr); 1708e705c121SKalle Valo idx = -ENOMEM; 1709e705c121SKalle Valo goto out; 1710e705c121SKalle Valo } 1711e705c121SKalle Valo 1712e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1713e705c121SKalle Valo } 1714e705c121SKalle Valo 17153cd1980bSSara Sharon BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1716e705c121SKalle Valo out_meta->flags = cmd->flags; 1717e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1718e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1719e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1720e705c121SKalle Valo 1721e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1722e705c121SKalle Valo 1723e705c121SKalle Valo /* start timer if queue currently empty */ 1724bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1725e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1726e705c121SKalle Valo 1727e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1728e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1729e705c121SKalle Valo if (ret < 0) { 1730e705c121SKalle Valo idx = ret; 1731e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1732e705c121SKalle Valo goto out; 1733e705c121SKalle Valo } 1734e705c121SKalle Valo 1735e705c121SKalle Valo /* Increment and update queue's write index */ 17367b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 1737e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1738e705c121SKalle Valo 1739e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1740e705c121SKalle Valo 1741e705c121SKalle Valo out: 1742e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1743e705c121SKalle Valo free_dup_buf: 1744e705c121SKalle Valo if (idx < 0) 1745e705c121SKalle Valo kfree(dup_buf); 1746e705c121SKalle Valo return idx; 1747e705c121SKalle Valo } 1748e705c121SKalle Valo 1749e705c121SKalle Valo /* 1750e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1751e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1752e705c121SKalle Valo */ 1753e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1754e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1755e705c121SKalle Valo { 1756e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1757e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1758d490e097SJohannes Berg u8 group_id; 175939bdb17eSSharon Dvir u32 cmd_id; 1760e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1761e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1762e705c121SKalle Valo int cmd_index; 1763e705c121SKalle Valo struct iwl_device_cmd *cmd; 1764e705c121SKalle Valo struct iwl_cmd_meta *meta; 1765e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1766b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1767e705c121SKalle Valo 1768e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1769e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1770e705c121SKalle Valo * in the queue management code. */ 1771e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1772e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1773b2a3b1c1SSara Sharon txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1774b2a3b1c1SSara Sharon txq->write_ptr)) { 1775e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1776e705c121SKalle Valo return; 1777e705c121SKalle Valo } 1778e705c121SKalle Valo 1779e705c121SKalle Valo spin_lock_bh(&txq->lock); 1780e705c121SKalle Valo 17814ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1782e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1783e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 1784d490e097SJohannes Berg group_id = cmd->hdr.group_id; 178539bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1786e705c121SKalle Valo 17876983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, meta, txq, index); 1788e705c121SKalle Valo 1789e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1790e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1791e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1792e705c121SKalle Valo 1793e705c121SKalle Valo meta->source->resp_pkt = pkt; 1794e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1795e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1796e705c121SKalle Valo } 1797e705c121SKalle Valo 1798dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1799dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1800dcbb4746SEmmanuel Grumbach 1801e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1802e705c121SKalle Valo 1803e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1804e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1805e705c121SKalle Valo IWL_WARN(trans, 1806e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 180739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1808e705c121SKalle Valo } 1809e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1810e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 181139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1812e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 18154cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 18164cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 18174cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18184cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 18194cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18204cbb8e50SLuciano Coelho } 18214cbb8e50SLuciano Coelho 18224cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 18234cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 18244cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18254cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 18264cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18274cbb8e50SLuciano Coelho } 18284cbb8e50SLuciano Coelho 1829e705c121SKalle Valo meta->flags = 0; 1830e705c121SKalle Valo 1831e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1832e705c121SKalle Valo } 1833e705c121SKalle Valo 1834e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1835e705c121SKalle Valo 1836e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1837e705c121SKalle Valo struct iwl_host_cmd *cmd) 1838e705c121SKalle Valo { 1839e705c121SKalle Valo int ret; 1840e705c121SKalle Valo 1841e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1842e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1843e705c121SKalle Valo return -EINVAL; 1844e705c121SKalle Valo 1845e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1846e705c121SKalle Valo if (ret < 0) { 1847e705c121SKalle Valo IWL_ERR(trans, 1848e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 184939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1850e705c121SKalle Valo return ret; 1851e705c121SKalle Valo } 1852e705c121SKalle Valo return 0; 1853e705c121SKalle Valo } 1854e705c121SKalle Valo 1855e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1856e705c121SKalle Valo struct iwl_host_cmd *cmd) 1857e705c121SKalle Valo { 1858e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1859b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1860e705c121SKalle Valo int cmd_idx; 1861e705c121SKalle Valo int ret; 1862e705c121SKalle Valo 1863e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 186439bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1865e705c121SKalle Valo 1866e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1867e705c121SKalle Valo &trans->status), 1868e705c121SKalle Valo "Command %s: a command is already active!\n", 186939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1870e705c121SKalle Valo return -EIO; 1871e705c121SKalle Valo 1872e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 187339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1874e705c121SKalle Valo 187571b1230cSLuca Coelho if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 187671b1230cSLuca Coelho ret = wait_event_timeout(trans_pcie->d0i3_waitq, 187771b1230cSLuca Coelho pm_runtime_active(&trans_pcie->pci_dev->dev), 187871b1230cSLuca Coelho msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 187971b1230cSLuca Coelho if (!ret) { 188071b1230cSLuca Coelho IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 188171b1230cSLuca Coelho return -ETIMEDOUT; 188271b1230cSLuca Coelho } 188371b1230cSLuca Coelho } 188471b1230cSLuca Coelho 1885e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1886e705c121SKalle Valo if (cmd_idx < 0) { 1887e705c121SKalle Valo ret = cmd_idx; 1888e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1889e705c121SKalle Valo IWL_ERR(trans, 1890e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 189139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1892e705c121SKalle Valo return ret; 1893e705c121SKalle Valo } 1894e705c121SKalle Valo 1895e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1896e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1897e705c121SKalle Valo &trans->status), 1898e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1899e705c121SKalle Valo if (!ret) { 1900e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 190139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1902e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1903e705c121SKalle Valo 1904e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1905bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 1906e705c121SKalle Valo 1907e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1908e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 190939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1910e705c121SKalle Valo ret = -ETIMEDOUT; 1911e705c121SKalle Valo 1912e705c121SKalle Valo iwl_force_nmi(trans); 1913e705c121SKalle Valo iwl_trans_fw_error(trans); 1914e705c121SKalle Valo 1915e705c121SKalle Valo goto cancel; 1916e705c121SKalle Valo } 1917e705c121SKalle Valo 1918e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 19194290eaadSJohannes Berg iwl_trans_pcie_dump_regs(trans); 1920e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 192139bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1922e705c121SKalle Valo dump_stack(); 1923e705c121SKalle Valo ret = -EIO; 1924e705c121SKalle Valo goto cancel; 1925e705c121SKalle Valo } 1926e705c121SKalle Valo 1927e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1928326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1929e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1930e705c121SKalle Valo ret = -ERFKILL; 1931e705c121SKalle Valo goto cancel; 1932e705c121SKalle Valo } 1933e705c121SKalle Valo 1934e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1935e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 193639bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1937e705c121SKalle Valo ret = -EIO; 1938e705c121SKalle Valo goto cancel; 1939e705c121SKalle Valo } 1940e705c121SKalle Valo 1941e705c121SKalle Valo return 0; 1942e705c121SKalle Valo 1943e705c121SKalle Valo cancel: 1944e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1945e705c121SKalle Valo /* 1946e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1947e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1948e705c121SKalle Valo * in later, it will possibly set an invalid 1949e705c121SKalle Valo * address (cmd->meta.source). 1950e705c121SKalle Valo */ 1951b2a3b1c1SSara Sharon txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1952e705c121SKalle Valo } 1953e705c121SKalle Valo 1954e705c121SKalle Valo if (cmd->resp_pkt) { 1955e705c121SKalle Valo iwl_free_resp(cmd); 1956e705c121SKalle Valo cmd->resp_pkt = NULL; 1957e705c121SKalle Valo } 1958e705c121SKalle Valo 1959e705c121SKalle Valo return ret; 1960e705c121SKalle Valo } 1961e705c121SKalle Valo 1962e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 1963e705c121SKalle Valo { 19642b3fae66SMatt Chen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19652b3fae66SMatt Chen 19662b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 19672b3fae66SMatt Chen if (trans_pcie->scheduled_for_removal) 19682b3fae66SMatt Chen return -EIO; 19692b3fae66SMatt Chen 1970e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1971326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1972e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1973e705c121SKalle Valo cmd->id); 1974e705c121SKalle Valo return -ERFKILL; 1975e705c121SKalle Valo } 1976e705c121SKalle Valo 1977e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 1978e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 1979e705c121SKalle Valo 1980e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 1981e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 1982e705c121SKalle Valo } 1983e705c121SKalle Valo 19843a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 19853a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 19863a0b2a42SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 19873a0b2a42SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 19883a0b2a42SEmmanuel Grumbach { 19896983ba69SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19903a0b2a42SEmmanuel Grumbach u16 tb2_len; 19913a0b2a42SEmmanuel Grumbach int i; 19923a0b2a42SEmmanuel Grumbach 19933a0b2a42SEmmanuel Grumbach /* 19943a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 19953a0b2a42SEmmanuel Grumbach * of skb's head, if any 19963a0b2a42SEmmanuel Grumbach */ 19973a0b2a42SEmmanuel Grumbach tb2_len = skb_headlen(skb) - hdr_len; 19983a0b2a42SEmmanuel Grumbach 19993a0b2a42SEmmanuel Grumbach if (tb2_len > 0) { 20003a0b2a42SEmmanuel Grumbach dma_addr_t tb2_phys = dma_map_single(trans->dev, 20013a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 20023a0b2a42SEmmanuel Grumbach tb2_len, DMA_TO_DEVICE); 20033a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { 2004bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 2005bb98ecd4SSara Sharon txq->write_ptr); 20063a0b2a42SEmmanuel Grumbach return -EINVAL; 20073a0b2a42SEmmanuel Grumbach } 20083a0b2a42SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false); 20093a0b2a42SEmmanuel Grumbach } 20103a0b2a42SEmmanuel Grumbach 20113a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 20123a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 20133a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 20143a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 20153a0b2a42SEmmanuel Grumbach int tb_idx; 20163a0b2a42SEmmanuel Grumbach 20173a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 20183a0b2a42SEmmanuel Grumbach continue; 20193a0b2a42SEmmanuel Grumbach 20203a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 20213a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 20223a0b2a42SEmmanuel Grumbach 20233a0b2a42SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 2024bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 2025bb98ecd4SSara Sharon txq->write_ptr); 20263a0b2a42SEmmanuel Grumbach return -EINVAL; 20273a0b2a42SEmmanuel Grumbach } 20283a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 20293a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 20303a0b2a42SEmmanuel Grumbach 20313cd1980bSSara Sharon out_meta->tbs |= BIT(tb_idx); 20323a0b2a42SEmmanuel Grumbach } 20333a0b2a42SEmmanuel Grumbach 20343a0b2a42SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2035943309d4SEmmanuel Grumbach iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 20366983ba69SSara Sharon trans_pcie->tfd_size, 20378de437c7SSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 20388790fce4SJohannes Berg hdr_len); 203978c1acf3SJohannes Berg trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len); 20403a0b2a42SEmmanuel Grumbach return 0; 20413a0b2a42SEmmanuel Grumbach } 20423a0b2a42SEmmanuel Grumbach 20436eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 20446ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 20456eb5e529SEmmanuel Grumbach { 20466eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20476eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 20486eb5e529SEmmanuel Grumbach 20496eb5e529SEmmanuel Grumbach if (!p->page) 20506eb5e529SEmmanuel Grumbach goto alloc; 20516eb5e529SEmmanuel Grumbach 20526eb5e529SEmmanuel Grumbach /* enough room on this page */ 20536eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 20546eb5e529SEmmanuel Grumbach return p; 20556eb5e529SEmmanuel Grumbach 20566eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 20576eb5e529SEmmanuel Grumbach __free_page(p->page); 20586eb5e529SEmmanuel Grumbach 20596eb5e529SEmmanuel Grumbach alloc: 20606eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 20616eb5e529SEmmanuel Grumbach if (!p->page) 20626eb5e529SEmmanuel Grumbach return NULL; 20636eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 20646eb5e529SEmmanuel Grumbach return p; 20656eb5e529SEmmanuel Grumbach } 20666eb5e529SEmmanuel Grumbach 20676eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 20686eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 20696eb5e529SEmmanuel Grumbach { 20706eb5e529SEmmanuel Grumbach if (ipv6) { 20716eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 20726eb5e529SEmmanuel Grumbach 20736eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 20746eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20756eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20766eb5e529SEmmanuel Grumbach } else { 20776eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 20786eb5e529SEmmanuel Grumbach 20796eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 20806eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 20816eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 20826eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 20836eb5e529SEmmanuel Grumbach } 20846eb5e529SEmmanuel Grumbach } 20856eb5e529SEmmanuel Grumbach 2086066fd29aSSara Sharon static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 20876eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 20886eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 20896eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 20906eb5e529SEmmanuel Grumbach { 209105e5a7e5SJohannes Berg struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 20926eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 20936eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 20946eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 20956eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 20966eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 20976eb5e529SEmmanuel Grumbach u8 *start_hdr; 20986eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 209921cb3222SJohannes Berg struct page **page_ptr; 21006eb5e529SEmmanuel Grumbach int ret; 21016eb5e529SEmmanuel Grumbach struct tso_t tso; 21026eb5e529SEmmanuel Grumbach 21036eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 21046eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 21056eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 21066eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 21076eb5e529SEmmanuel Grumbach 21086eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2109943309d4SEmmanuel Grumbach iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 21106983ba69SSara Sharon trans_pcie->tfd_size, 21118790fce4SJohannes Berg &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 21126eb5e529SEmmanuel Grumbach 21136eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 21146eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 21156eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 21166eb5e529SEmmanuel Grumbach amsdu_pad = 0; 21176eb5e529SEmmanuel Grumbach 21186eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 21196eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 21206eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 21216eb5e529SEmmanuel Grumbach 21226eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 21236eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 21246eb5e529SEmmanuel Grumbach if (!hdr_page) 21256eb5e529SEmmanuel Grumbach return -ENOMEM; 21266eb5e529SEmmanuel Grumbach 21276eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 21286eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 212921cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 213021cb3222SJohannes Berg *page_ptr = hdr_page->page; 21316eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 21326eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 21336eb5e529SEmmanuel Grumbach 21346eb5e529SEmmanuel Grumbach /* 21356eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 21366eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 21376eb5e529SEmmanuel Grumbach */ 21386eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 21396eb5e529SEmmanuel Grumbach 214005e5a7e5SJohannes Berg /* 214105e5a7e5SJohannes Berg * Remove the length of all the headers that we don't actually 214205e5a7e5SJohannes Berg * have in the MPDU by themselves, but that we duplicate into 214305e5a7e5SJohannes Berg * all the different MSDUs inside the A-MSDU. 214405e5a7e5SJohannes Berg */ 214505e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 214605e5a7e5SJohannes Berg 21476eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 21486eb5e529SEmmanuel Grumbach 21496eb5e529SEmmanuel Grumbach while (total_len) { 21506eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 21516eb5e529SEmmanuel Grumbach unsigned int data_left = 21526eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 21536eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 21546eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 21556eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 21566eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 215705e5a7e5SJohannes Berg u8 *iph, *subf_hdrs_start = hdr_page->pos; 21586eb5e529SEmmanuel Grumbach 21596eb5e529SEmmanuel Grumbach total_len -= data_left; 21606eb5e529SEmmanuel Grumbach 21616eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 21626eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 21636eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 21646eb5e529SEmmanuel Grumbach data_left)) & 0x3; 21656eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 21666eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21676eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 21686eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 21696eb5e529SEmmanuel Grumbach 21706eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 21716eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 21726eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 21736eb5e529SEmmanuel Grumbach 21746eb5e529SEmmanuel Grumbach /* 21756eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 21766eb5e529SEmmanuel Grumbach * as MAC header. 21776eb5e529SEmmanuel Grumbach */ 21786eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 21796eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 21806eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 21816eb5e529SEmmanuel Grumbach 21826eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 21836eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 21846eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 21856eb5e529SEmmanuel Grumbach GFP_ATOMIC); 21866eb5e529SEmmanuel Grumbach if (!csum_skb) { 21876eb5e529SEmmanuel Grumbach ret = -ENOMEM; 21886eb5e529SEmmanuel Grumbach goto out_unmap; 21896eb5e529SEmmanuel Grumbach } 21906eb5e529SEmmanuel Grumbach 21916eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 21926eb5e529SEmmanuel Grumbach skb->protocol == 21936eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 21946eb5e529SEmmanuel Grumbach data_left); 21956eb5e529SEmmanuel Grumbach 219659ae1d12SJohannes Berg skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2197a52a8a4dSZhang Shengju skb_reset_transport_header(csum_skb); 21986eb5e529SEmmanuel Grumbach csum_skb->csum_start = 21996eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 22006eb5e529SEmmanuel Grumbach csum_skb->head; 22016eb5e529SEmmanuel Grumbach } 22026eb5e529SEmmanuel Grumbach 22036eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 22046eb5e529SEmmanuel Grumbach 22056eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 22066eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 22076eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22086eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 22096eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22106eb5e529SEmmanuel Grumbach ret = -EINVAL; 22116eb5e529SEmmanuel Grumbach goto out_unmap; 22126eb5e529SEmmanuel Grumbach } 22136eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 22146eb5e529SEmmanuel Grumbach hdr_tb_len, false); 22156eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, 22166eb5e529SEmmanuel Grumbach hdr_tb_len); 221705e5a7e5SJohannes Berg /* add this subframe's headers' length to the tx_cmd */ 221805e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 22196eb5e529SEmmanuel Grumbach 22206eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 22216eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 22226eb5e529SEmmanuel Grumbach 22236eb5e529SEmmanuel Grumbach /* put the payload */ 22246eb5e529SEmmanuel Grumbach while (data_left) { 22256eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 22266eb5e529SEmmanuel Grumbach data_left); 22276eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 22286eb5e529SEmmanuel Grumbach 22296eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 223059ae1d12SJohannes Berg skb_put_data(csum_skb, tso.data, size); 22316eb5e529SEmmanuel Grumbach 22326eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 22336eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 22346eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 22356eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22366eb5e529SEmmanuel Grumbach ret = -EINVAL; 22376eb5e529SEmmanuel Grumbach goto out_unmap; 22386eb5e529SEmmanuel Grumbach } 22396eb5e529SEmmanuel Grumbach 22406eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 22416eb5e529SEmmanuel Grumbach size, false); 22426eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 22436eb5e529SEmmanuel Grumbach size); 22446eb5e529SEmmanuel Grumbach 22456eb5e529SEmmanuel Grumbach data_left -= size; 22466eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 22476eb5e529SEmmanuel Grumbach } 22486eb5e529SEmmanuel Grumbach 22496eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 22506eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22516eb5e529SEmmanuel Grumbach __wsum csum; 22526eb5e529SEmmanuel Grumbach 22536eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 22546eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22556eb5e529SEmmanuel Grumbach csum_skb->len - 22566eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22576eb5e529SEmmanuel Grumbach 0); 22586eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22596eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 22606eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22616eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 22626eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 22636eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22646eb5e529SEmmanuel Grumbach } 22656eb5e529SEmmanuel Grumbach } 22666eb5e529SEmmanuel Grumbach 22676eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 22686eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 22696eb5e529SEmmanuel Grumbach 22706eb5e529SEmmanuel Grumbach return 0; 22716eb5e529SEmmanuel Grumbach 22726eb5e529SEmmanuel Grumbach out_unmap: 2273bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 22746eb5e529SEmmanuel Grumbach return ret; 22756eb5e529SEmmanuel Grumbach } 22766eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 22776eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 22786eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 22796eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 22806eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 22816eb5e529SEmmanuel Grumbach { 22826eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 22836eb5e529SEmmanuel Grumbach WARN_ON(1); 22846eb5e529SEmmanuel Grumbach 22856eb5e529SEmmanuel Grumbach return -1; 22866eb5e529SEmmanuel Grumbach } 22876eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 22886eb5e529SEmmanuel Grumbach 2289e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2290e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2291e705c121SKalle Valo { 2292e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2293e705c121SKalle Valo struct ieee80211_hdr *hdr; 2294e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2295e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2296e705c121SKalle Valo struct iwl_txq *txq; 2297e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2298e705c121SKalle Valo void *tb1_addr; 22994fe10bc6SSara Sharon void *tfd; 23003a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2301e705c121SKalle Valo bool wait_write_ptr; 2302e705c121SKalle Valo __le16 fc; 2303e705c121SKalle Valo u8 hdr_len; 2304e705c121SKalle Valo u16 wifi_seq; 2305c772a3d3SSara Sharon bool amsdu; 2306e705c121SKalle Valo 2307b2a3b1c1SSara Sharon txq = trans_pcie->txq[txq_id]; 2308e705c121SKalle Valo 2309e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2310e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2311e705c121SKalle Valo return -EINVAL; 2312e705c121SKalle Valo 231341837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 231441837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 231541837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 231641837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 231741837ca9SEmmanuel Grumbach __wsum csum; 231841837ca9SEmmanuel Grumbach 231941837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 232041837ca9SEmmanuel Grumbach return -1; 232141837ca9SEmmanuel Grumbach 232241837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 232341837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 23243955525dSEmmanuel Grumbach 23253955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 232641837ca9SEmmanuel Grumbach } 232741837ca9SEmmanuel Grumbach 2328e705c121SKalle Valo if (skb_is_nonlinear(skb) && 23293cd1980bSSara Sharon skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2330e705c121SKalle Valo __skb_linearize(skb)) 2331e705c121SKalle Valo return -ENOMEM; 2332e705c121SKalle Valo 2333e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2334e705c121SKalle Valo * so there's no need to check if it's readable there 2335e705c121SKalle Valo */ 2336e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2337e705c121SKalle Valo fc = hdr->frame_control; 2338e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2339e705c121SKalle Valo 2340e705c121SKalle Valo spin_lock(&txq->lock); 2341e705c121SKalle Valo 23427b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < txq->high_mark) { 23433955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 23443955525dSEmmanuel Grumbach 23453955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 23467b3e42eaSGolan Ben Ami if (unlikely(iwl_queue_space(trans, txq) < 3)) { 234721cb3222SJohannes Berg struct iwl_device_cmd **dev_cmd_ptr; 23483955525dSEmmanuel Grumbach 234921cb3222SJohannes Berg dev_cmd_ptr = (void *)((u8 *)skb->cb + 235021cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 235121cb3222SJohannes Berg 235221cb3222SJohannes Berg *dev_cmd_ptr = dev_cmd; 23533955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 23543955525dSEmmanuel Grumbach 23553955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 23563955525dSEmmanuel Grumbach return 0; 23573955525dSEmmanuel Grumbach } 23583955525dSEmmanuel Grumbach } 23593955525dSEmmanuel Grumbach 2360e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2361e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2362e705c121SKalle Valo * the BA. 2363e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2364e705c121SKalle Valo */ 2365e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2366e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2367bb98ecd4SSara Sharon (wifi_seq & 0xff) != txq->write_ptr, 2368e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2369bb98ecd4SSara Sharon txq_id, wifi_seq, txq->write_ptr); 2370e705c121SKalle Valo 2371e705c121SKalle Valo /* Set up driver data for this TFD */ 2372bb98ecd4SSara Sharon txq->entries[txq->write_ptr].skb = skb; 2373bb98ecd4SSara Sharon txq->entries[txq->write_ptr].cmd = dev_cmd; 2374e705c121SKalle Valo 2375e705c121SKalle Valo dev_cmd->hdr.sequence = 2376e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2377bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr))); 2378e705c121SKalle Valo 2379bb98ecd4SSara Sharon tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2380e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2381e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2382e705c121SKalle Valo 2383e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2384e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2385e705c121SKalle Valo 2386e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2387bb98ecd4SSara Sharon out_meta = &txq->entries[txq->write_ptr].meta; 2388e705c121SKalle Valo out_meta->flags = 0; 2389e705c121SKalle Valo 2390e705c121SKalle Valo /* 2391e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2392e705c121SKalle Valo * and the 802.11 header - dword aligned size 2393e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2394e705c121SKalle Valo * setup of the first TB) 2395e705c121SKalle Valo */ 2396e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 23978de437c7SSara Sharon hdr_len - IWL_FIRST_TB_SIZE; 2398c772a3d3SSara Sharon /* do not align A-MSDU to dword as the subframe header aligns it */ 2399c772a3d3SSara Sharon amsdu = ieee80211_is_data_qos(fc) && 2400c772a3d3SSara Sharon (*ieee80211_get_qos_ctl(hdr) & 2401c772a3d3SSara Sharon IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2402c772a3d3SSara Sharon if (trans_pcie->sw_csum_tx || !amsdu) { 2403e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2404e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2405e705c121SKalle Valo if (tb1_len != len) 2406d172a5efSJohannes Berg tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2407c772a3d3SSara Sharon } else { 2408c772a3d3SSara Sharon tb1_len = len; 2409c772a3d3SSara Sharon } 2410e705c121SKalle Valo 241105e5a7e5SJohannes Berg /* 241205e5a7e5SJohannes Berg * The first TB points to bi-directional DMA data, we'll 241305e5a7e5SJohannes Berg * memcpy the data into it later. 241405e5a7e5SJohannes Berg */ 2415e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 24168de437c7SSara Sharon IWL_FIRST_TB_SIZE, true); 2417e705c121SKalle Valo 2418e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 24198de437c7SSara Sharon BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2420e705c121SKalle Valo 2421e705c121SKalle Valo /* map the data for TB1 */ 24228de437c7SSara Sharon tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2423e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2424e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2425e705c121SKalle Valo goto out_err; 2426e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2427e705c121SKalle Valo 2428bf1ad897SEliad Peller /* 2429bf1ad897SEliad Peller * If gso_size wasn't set, don't give the frame "amsdu treatment" 2430bf1ad897SEliad Peller * (adding subframes, etc.). 2431bf1ad897SEliad Peller * This can happen in some testing flows when the amsdu was already 2432bf1ad897SEliad Peller * pre-built, and we just need to send the resulting skb. 2433bf1ad897SEliad Peller */ 2434bf1ad897SEliad Peller if (amsdu && skb_shinfo(skb)->gso_size) { 24356eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 24366eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 24376eb5e529SEmmanuel Grumbach tb1_len))) 2438e705c121SKalle Valo goto out_err; 24396eb5e529SEmmanuel Grumbach } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 24406eb5e529SEmmanuel Grumbach out_meta, dev_cmd, tb1_len))) { 24416eb5e529SEmmanuel Grumbach goto out_err; 24426eb5e529SEmmanuel Grumbach } 2443e705c121SKalle Valo 244405e5a7e5SJohannes Berg /* building the A-MSDU might have changed this data, so memcpy it now */ 244505e5a7e5SJohannes Berg memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 244605e5a7e5SJohannes Berg IWL_FIRST_TB_SIZE); 244705e5a7e5SJohannes Berg 2448943309d4SEmmanuel Grumbach tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 2449e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 24504fe10bc6SSara Sharon iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 24514fe10bc6SSara Sharon iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2452e705c121SKalle Valo 2453e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2454e705c121SKalle Valo 2455e705c121SKalle Valo /* start timer if queue currently empty */ 2456bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 2457e705c121SKalle Valo if (txq->wd_timeout) { 2458e705c121SKalle Valo /* 2459e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2460e705c121SKalle Valo * set the timer in remainder so that the timer will 2461e705c121SKalle Valo * be armed with the right value when the station will 2462e705c121SKalle Valo * wake up. 2463e705c121SKalle Valo */ 2464e705c121SKalle Valo if (!txq->frozen) 2465e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2466e705c121SKalle Valo jiffies + txq->wd_timeout); 2467e705c121SKalle Valo else 2468e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2469e705c121SKalle Valo } 2470bb98ecd4SSara Sharon IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 2471c24c7f58SLuca Coelho iwl_trans_ref(trans); 2472e705c121SKalle Valo } 2473e705c121SKalle Valo 2474e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 24757b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 2476e705c121SKalle Valo if (!wait_write_ptr) 2477e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2478e705c121SKalle Valo 2479e705c121SKalle Valo /* 2480e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2481e705c121SKalle Valo * and we will get a TX status notification eventually. 2482e705c121SKalle Valo */ 2483e705c121SKalle Valo spin_unlock(&txq->lock); 2484e705c121SKalle Valo return 0; 2485e705c121SKalle Valo out_err: 2486e705c121SKalle Valo spin_unlock(&txq->lock); 2487e705c121SKalle Valo return -1; 2488e705c121SKalle Valo } 2489