1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3cefec29eSJohannes Berg * This file is provided under a dual BSD/GPLv2 license. When using or 4cefec29eSJohannes Berg * redistributing this file, you may do so under either license. 5cefec29eSJohannes Berg * 6cefec29eSJohannes Berg * GPL LICENSE SUMMARY 7cefec29eSJohannes Berg * 8e705c121SKalle Valo * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 94cbb8e50SLuciano Coelho * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10eda50cdeSSara Sharon * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11b8a7547dSShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify it 14e705c121SKalle Valo * under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but WITHOUT 18e705c121SKalle Valo * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19e705c121SKalle Valo * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20e705c121SKalle Valo * more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution in the 23cefec29eSJohannes Berg * file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29cefec29eSJohannes Berg * BSD LICENSE 30cefec29eSJohannes Berg * 31cefec29eSJohannes Berg * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved. 32cefec29eSJohannes Berg * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33cefec29eSJohannes Berg * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34b8a7547dSShahar S Matityahu * Copyright(c) 2018 - 2019 Intel Corporation 35cefec29eSJohannes Berg * All rights reserved. 36cefec29eSJohannes Berg * 37cefec29eSJohannes Berg * Redistribution and use in source and binary forms, with or without 38cefec29eSJohannes Berg * modification, are permitted provided that the following conditions 39cefec29eSJohannes Berg * are met: 40cefec29eSJohannes Berg * 41cefec29eSJohannes Berg * * Redistributions of source code must retain the above copyright 42cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer. 43cefec29eSJohannes Berg * * Redistributions in binary form must reproduce the above copyright 44cefec29eSJohannes Berg * notice, this list of conditions and the following disclaimer in 45cefec29eSJohannes Berg * the documentation and/or other materials provided with the 46cefec29eSJohannes Berg * distribution. 47cefec29eSJohannes Berg * * Neither the name Intel Corporation nor the names of its 48cefec29eSJohannes Berg * contributors may be used to endorse or promote products derived 49cefec29eSJohannes Berg * from this software without specific prior written permission. 50cefec29eSJohannes Berg * 51cefec29eSJohannes Berg * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52cefec29eSJohannes Berg * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53cefec29eSJohannes Berg * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54cefec29eSJohannes Berg * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55cefec29eSJohannes Berg * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56cefec29eSJohannes Berg * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57cefec29eSJohannes Berg * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58cefec29eSJohannes Berg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59cefec29eSJohannes Berg * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60cefec29eSJohannes Berg * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61cefec29eSJohannes Berg * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62cefec29eSJohannes Berg * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/etherdevice.h> 656eb5e529SEmmanuel Grumbach #include <linux/ieee80211.h> 66e705c121SKalle Valo #include <linux/slab.h> 67e705c121SKalle Valo #include <linux/sched.h> 6871b1230cSLuca Coelho #include <linux/pm_runtime.h> 696eb5e529SEmmanuel Grumbach #include <net/ip6_checksum.h> 706eb5e529SEmmanuel Grumbach #include <net/tso.h> 71e705c121SKalle Valo 72e705c121SKalle Valo #include "iwl-debug.h" 73e705c121SKalle Valo #include "iwl-csr.h" 74e705c121SKalle Valo #include "iwl-prph.h" 75e705c121SKalle Valo #include "iwl-io.h" 76e705c121SKalle Valo #include "iwl-scd.h" 77e705c121SKalle Valo #include "iwl-op-mode.h" 78e705c121SKalle Valo #include "internal.h" 79d172a5efSJohannes Berg #include "fw/api/tx.h" 80e705c121SKalle Valo 81e705c121SKalle Valo #define IWL_TX_CRC_SIZE 4 82e705c121SKalle Valo #define IWL_TX_DELIMITER_SIZE 4 83e705c121SKalle Valo 84e705c121SKalle Valo /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** 85e705c121SKalle Valo * DMA services 86e705c121SKalle Valo * 87e705c121SKalle Valo * Theory of operation 88e705c121SKalle Valo * 89e705c121SKalle Valo * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer 90e705c121SKalle Valo * of buffer descriptors, each of which points to one or more data buffers for 91e705c121SKalle Valo * the device to read from or fill. Driver and device exchange status of each 92e705c121SKalle Valo * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty 93e705c121SKalle Valo * entries in each circular buffer, to protect against confusing empty and full 94e705c121SKalle Valo * queue states. 95e705c121SKalle Valo * 96e705c121SKalle Valo * The device reads or writes the data in the queues via the device's several 97e705c121SKalle Valo * DMA/FIFO channels. Each queue is mapped to a single DMA channel. 98e705c121SKalle Valo * 99e705c121SKalle Valo * For Tx queue, there are low mark and high mark limits. If, after queuing 100e705c121SKalle Valo * the packet for Tx, free space become < low mark, Tx queue stopped. When 101e705c121SKalle Valo * reclaiming packets (on 'tx done IRQ), if free space become > high mark, 102e705c121SKalle Valo * Tx queue resumed. 103e705c121SKalle Valo * 104e705c121SKalle Valo ***************************************************/ 105e22744afSSara Sharon 1067b3e42eaSGolan Ben Ami int iwl_queue_space(struct iwl_trans *trans, const struct iwl_txq *q) 107e705c121SKalle Valo { 108e705c121SKalle Valo unsigned int max; 109e705c121SKalle Valo unsigned int used; 110e705c121SKalle Valo 111e705c121SKalle Valo /* 112e705c121SKalle Valo * To avoid ambiguity between empty and completely full queues, there 1137b3e42eaSGolan Ben Ami * should always be less than max_tfd_queue_size elements in the queue. 1147b3e42eaSGolan Ben Ami * If q->n_window is smaller than max_tfd_queue_size, there is no need 115e705c121SKalle Valo * to reserve any queue entries for this purpose. 116e705c121SKalle Valo */ 1177b3e42eaSGolan Ben Ami if (q->n_window < trans->cfg->base_params->max_tfd_queue_size) 118e705c121SKalle Valo max = q->n_window; 119e705c121SKalle Valo else 1207b3e42eaSGolan Ben Ami max = trans->cfg->base_params->max_tfd_queue_size - 1; 121e705c121SKalle Valo 122e705c121SKalle Valo /* 1237b3e42eaSGolan Ben Ami * max_tfd_queue_size is a power of 2, so the following is equivalent to 1247b3e42eaSGolan Ben Ami * modulo by max_tfd_queue_size and is well defined. 125e705c121SKalle Valo */ 1267b3e42eaSGolan Ben Ami used = (q->write_ptr - q->read_ptr) & 1277b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1); 128e705c121SKalle Valo 129e705c121SKalle Valo if (WARN_ON(used > max)) 130e705c121SKalle Valo return 0; 131e705c121SKalle Valo 132e705c121SKalle Valo return max - used; 133e705c121SKalle Valo } 134e705c121SKalle Valo 135e705c121SKalle Valo /* 136e705c121SKalle Valo * iwl_queue_init - Initialize queue's high/low-water and read/write indexes 137e705c121SKalle Valo */ 138b8e8d7ceSSara Sharon static int iwl_queue_init(struct iwl_txq *q, int slots_num) 139e705c121SKalle Valo { 140e705c121SKalle Valo q->n_window = slots_num; 141e705c121SKalle Valo 142e705c121SKalle Valo /* slots_num must be power-of-two size, otherwise 1434ecab561SEmmanuel Grumbach * iwl_pcie_get_cmd_index is broken. */ 144e705c121SKalle Valo if (WARN_ON(!is_power_of_2(slots_num))) 145e705c121SKalle Valo return -EINVAL; 146e705c121SKalle Valo 147e705c121SKalle Valo q->low_mark = q->n_window / 4; 148e705c121SKalle Valo if (q->low_mark < 4) 149e705c121SKalle Valo q->low_mark = 4; 150e705c121SKalle Valo 151e705c121SKalle Valo q->high_mark = q->n_window / 8; 152e705c121SKalle Valo if (q->high_mark < 2) 153e705c121SKalle Valo q->high_mark = 2; 154e705c121SKalle Valo 155e705c121SKalle Valo q->write_ptr = 0; 156e705c121SKalle Valo q->read_ptr = 0; 157e705c121SKalle Valo 158e705c121SKalle Valo return 0; 159e705c121SKalle Valo } 160e705c121SKalle Valo 16113a3a390SSara Sharon int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 162e705c121SKalle Valo struct iwl_dma_ptr *ptr, size_t size) 163e705c121SKalle Valo { 164e705c121SKalle Valo if (WARN_ON(ptr->addr)) 165e705c121SKalle Valo return -EINVAL; 166e705c121SKalle Valo 167e705c121SKalle Valo ptr->addr = dma_alloc_coherent(trans->dev, size, 168e705c121SKalle Valo &ptr->dma, GFP_KERNEL); 169e705c121SKalle Valo if (!ptr->addr) 170e705c121SKalle Valo return -ENOMEM; 171e705c121SKalle Valo ptr->size = size; 172e705c121SKalle Valo return 0; 173e705c121SKalle Valo } 174e705c121SKalle Valo 17513a3a390SSara Sharon void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr) 176e705c121SKalle Valo { 177e705c121SKalle Valo if (unlikely(!ptr->addr)) 178e705c121SKalle Valo return; 179e705c121SKalle Valo 180e705c121SKalle Valo dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); 181e705c121SKalle Valo memset(ptr, 0, sizeof(*ptr)); 182e705c121SKalle Valo } 183e705c121SKalle Valo 184e99e88a9SKees Cook static void iwl_pcie_txq_stuck_timer(struct timer_list *t) 185e705c121SKalle Valo { 186e99e88a9SKees Cook struct iwl_txq *txq = from_timer(txq, t, stuck_timer); 187e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 188e705c121SKalle Valo struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 189e705c121SKalle Valo 190e705c121SKalle Valo spin_lock(&txq->lock); 191e705c121SKalle Valo /* check if triggered erroneously */ 192bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 193e705c121SKalle Valo spin_unlock(&txq->lock); 194e705c121SKalle Valo return; 195e705c121SKalle Valo } 196e705c121SKalle Valo spin_unlock(&txq->lock); 197e705c121SKalle Valo 19838398efbSSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 199e705c121SKalle Valo 200e705c121SKalle Valo iwl_force_nmi(trans); 201e705c121SKalle Valo } 202e705c121SKalle Valo 203e705c121SKalle Valo /* 204e705c121SKalle Valo * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array 205e705c121SKalle Valo */ 206e705c121SKalle Valo static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, 2074fe10bc6SSara Sharon struct iwl_txq *txq, u16 byte_cnt, 2084fe10bc6SSara Sharon int num_tbs) 209e705c121SKalle Valo { 210e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl; 211e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 212bb98ecd4SSara Sharon int write_ptr = txq->write_ptr; 213bb98ecd4SSara Sharon int txq_id = txq->id; 214e705c121SKalle Valo u8 sec_ctl = 0; 215e705c121SKalle Valo u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; 216e705c121SKalle Valo __le16 bc_ent; 217e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 218bb98ecd4SSara Sharon (void *)txq->entries[txq->write_ptr].cmd->payload; 219ab6c6445SSara Sharon u8 sta_id = tx_cmd->sta_id; 220e705c121SKalle Valo 221e705c121SKalle Valo scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 222e705c121SKalle Valo 223e705c121SKalle Valo sec_ctl = tx_cmd->sec_ctl; 224e705c121SKalle Valo 225e705c121SKalle Valo switch (sec_ctl & TX_CMD_SEC_MSK) { 226e705c121SKalle Valo case TX_CMD_SEC_CCM: 227e705c121SKalle Valo len += IEEE80211_CCMP_MIC_LEN; 228e705c121SKalle Valo break; 229e705c121SKalle Valo case TX_CMD_SEC_TKIP: 230e705c121SKalle Valo len += IEEE80211_TKIP_ICV_LEN; 231e705c121SKalle Valo break; 232e705c121SKalle Valo case TX_CMD_SEC_WEP: 233e705c121SKalle Valo len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; 234e705c121SKalle Valo break; 235e705c121SKalle Valo } 236e705c121SKalle Valo if (trans_pcie->bc_table_dword) 237e705c121SKalle Valo len = DIV_ROUND_UP(len, 4); 238e705c121SKalle Valo 239e705c121SKalle Valo if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 240e705c121SKalle Valo return; 241e705c121SKalle Valo 242e705c121SKalle Valo bc_ent = cpu_to_le16(len | (sta_id << 12)); 243e705c121SKalle Valo 244e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; 245e705c121SKalle Valo 246e705c121SKalle Valo if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) 247e705c121SKalle Valo scd_bc_tbl[txq_id]. 248e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; 249e705c121SKalle Valo } 250e705c121SKalle Valo 251e705c121SKalle Valo static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, 252e705c121SKalle Valo struct iwl_txq *txq) 253e705c121SKalle Valo { 254e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = 255e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 256e705c121SKalle Valo struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; 257bb98ecd4SSara Sharon int txq_id = txq->id; 258bb98ecd4SSara Sharon int read_ptr = txq->read_ptr; 259e705c121SKalle Valo u8 sta_id = 0; 260e705c121SKalle Valo __le16 bc_ent; 261e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = 262bb98ecd4SSara Sharon (void *)txq->entries[read_ptr].cmd->payload; 263e705c121SKalle Valo 264e705c121SKalle Valo WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); 265e705c121SKalle Valo 266e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 267e705c121SKalle Valo sta_id = tx_cmd->sta_id; 268e705c121SKalle Valo 269e705c121SKalle Valo bc_ent = cpu_to_le16(1 | (sta_id << 12)); 2704fe10bc6SSara Sharon 271e705c121SKalle Valo scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; 272e705c121SKalle Valo 273e705c121SKalle Valo if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) 274e705c121SKalle Valo scd_bc_tbl[txq_id]. 275e705c121SKalle Valo tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; 276e705c121SKalle Valo } 277e705c121SKalle Valo 278e705c121SKalle Valo /* 279e705c121SKalle Valo * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware 280e705c121SKalle Valo */ 281e705c121SKalle Valo static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, 282e705c121SKalle Valo struct iwl_txq *txq) 283e705c121SKalle Valo { 284e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 285e705c121SKalle Valo u32 reg = 0; 286bb98ecd4SSara Sharon int txq_id = txq->id; 287e705c121SKalle Valo 288e705c121SKalle Valo lockdep_assert_held(&txq->lock); 289e705c121SKalle Valo 290e705c121SKalle Valo /* 291e705c121SKalle Valo * explicitly wake up the NIC if: 292e705c121SKalle Valo * 1. shadow registers aren't enabled 293e705c121SKalle Valo * 2. NIC is woken up for CMD regardless of shadow outside this function 294e705c121SKalle Valo * 3. there is a chance that the NIC is asleep 295e705c121SKalle Valo */ 296e705c121SKalle Valo if (!trans->cfg->base_params->shadow_reg_enable && 297e705c121SKalle Valo txq_id != trans_pcie->cmd_queue && 298e705c121SKalle Valo test_bit(STATUS_TPOWER_PMI, &trans->status)) { 299e705c121SKalle Valo /* 300e705c121SKalle Valo * wake up nic if it's powered down ... 301e705c121SKalle Valo * uCode will wake up, and interrupt us again, so next 302e705c121SKalle Valo * time we'll skip this part. 303e705c121SKalle Valo */ 304e705c121SKalle Valo reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); 305e705c121SKalle Valo 306e705c121SKalle Valo if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { 307e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n", 308e705c121SKalle Valo txq_id, reg); 309e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 310a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 311e705c121SKalle Valo txq->need_update = true; 312e705c121SKalle Valo return; 313e705c121SKalle Valo } 314e705c121SKalle Valo } 315e705c121SKalle Valo 316e705c121SKalle Valo /* 317e705c121SKalle Valo * if not in power-save mode, uCode will never sleep when we're 318e705c121SKalle Valo * trying to tx (during RFKILL, we're not trying to tx). 319e705c121SKalle Valo */ 320bb98ecd4SSara Sharon IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr); 3210cd58eaaSEmmanuel Grumbach if (!txq->block) 3220cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 323bb98ecd4SSara Sharon txq->write_ptr | (txq_id << 8)); 324e705c121SKalle Valo } 325e705c121SKalle Valo 326e705c121SKalle Valo void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans) 327e705c121SKalle Valo { 328e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 329e705c121SKalle Valo int i; 330e705c121SKalle Valo 331e705c121SKalle Valo for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 332b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 333e705c121SKalle Valo 334f6eac740SMordechai Goodstein if (!test_bit(i, trans_pcie->queue_used)) 335f6eac740SMordechai Goodstein continue; 336f6eac740SMordechai Goodstein 337e705c121SKalle Valo spin_lock_bh(&txq->lock); 338b2a3b1c1SSara Sharon if (txq->need_update) { 339e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 340b2a3b1c1SSara Sharon txq->need_update = false; 341e705c121SKalle Valo } 342e705c121SKalle Valo spin_unlock_bh(&txq->lock); 343e705c121SKalle Valo } 344e705c121SKalle Valo } 345e705c121SKalle Valo 3466983ba69SSara Sharon static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans, 347cc2f41f8SJohannes Berg void *_tfd, u8 idx) 3486983ba69SSara Sharon { 3496983ba69SSara Sharon 3506983ba69SSara Sharon if (trans->cfg->use_tfh) { 351cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 352cc2f41f8SJohannes Berg struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 3536983ba69SSara Sharon 3546983ba69SSara Sharon return (dma_addr_t)(le64_to_cpu(tb->addr)); 355cc2f41f8SJohannes Berg } else { 356cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 357cc2f41f8SJohannes Berg struct iwl_tfd_tb *tb = &tfd->tbs[idx]; 358cc2f41f8SJohannes Berg dma_addr_t addr = get_unaligned_le32(&tb->lo); 359cc2f41f8SJohannes Berg dma_addr_t hi_len; 3606983ba69SSara Sharon 361cc2f41f8SJohannes Berg if (sizeof(dma_addr_t) <= sizeof(u32)) 362e705c121SKalle Valo return addr; 363cc2f41f8SJohannes Berg 364cc2f41f8SJohannes Berg hi_len = le16_to_cpu(tb->hi_n_len) & 0xF; 365cc2f41f8SJohannes Berg 366cc2f41f8SJohannes Berg /* 367cc2f41f8SJohannes Berg * shift by 16 twice to avoid warnings on 32-bit 368cc2f41f8SJohannes Berg * (where this code never runs anyway due to the 369cc2f41f8SJohannes Berg * if statement above) 370cc2f41f8SJohannes Berg */ 371cc2f41f8SJohannes Berg return addr | ((hi_len << 16) << 16); 372cc2f41f8SJohannes Berg } 373e705c121SKalle Valo } 374e705c121SKalle Valo 3756983ba69SSara Sharon static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd, 3766983ba69SSara Sharon u8 idx, dma_addr_t addr, u16 len) 377e705c121SKalle Valo { 3786983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 3796983ba69SSara Sharon struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx]; 3806983ba69SSara Sharon 381e705c121SKalle Valo u16 hi_n_len = len << 4; 382e705c121SKalle Valo 383e705c121SKalle Valo put_unaligned_le32(addr, &tb->lo); 3847abf6fdeSJohannes Berg hi_n_len |= iwl_get_dma_hi_addr(addr); 385e705c121SKalle Valo 386e705c121SKalle Valo tb->hi_n_len = cpu_to_le16(hi_n_len); 387e705c121SKalle Valo 3886983ba69SSara Sharon tfd_fh->num_tbs = idx + 1; 3896983ba69SSara Sharon } 390e705c121SKalle Valo 391cc2f41f8SJohannes Berg static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd) 392e705c121SKalle Valo { 3936983ba69SSara Sharon if (trans->cfg->use_tfh) { 394cc2f41f8SJohannes Berg struct iwl_tfh_tfd *tfd = _tfd; 3956983ba69SSara Sharon 396cc2f41f8SJohannes Berg return le16_to_cpu(tfd->num_tbs) & 0x1f; 397cc2f41f8SJohannes Berg } else { 398cc2f41f8SJohannes Berg struct iwl_tfd *tfd = _tfd; 399cc2f41f8SJohannes Berg 400cc2f41f8SJohannes Berg return tfd->num_tbs & 0x1f; 4016983ba69SSara Sharon } 402e705c121SKalle Valo } 403e705c121SKalle Valo 404e705c121SKalle Valo static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, 405e705c121SKalle Valo struct iwl_cmd_meta *meta, 4066983ba69SSara Sharon struct iwl_txq *txq, int index) 407e705c121SKalle Valo { 4083cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4093cd1980bSSara Sharon int i, num_tbs; 410943309d4SEmmanuel Grumbach void *tfd = iwl_pcie_get_tfd(trans, txq, index); 411e705c121SKalle Valo 412e705c121SKalle Valo /* Sanity check on number of chunks */ 4136983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 414e705c121SKalle Valo 4154437ba7eSEmmanuel Grumbach if (num_tbs > trans_pcie->max_tbs) { 416e705c121SKalle Valo IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 417e705c121SKalle Valo /* @todo issue fatal error, it is quite serious situation */ 418e705c121SKalle Valo return; 419e705c121SKalle Valo } 420e705c121SKalle Valo 4218de437c7SSara Sharon /* first TB is never freed - it's the bidirectional DMA data */ 422e705c121SKalle Valo 423e705c121SKalle Valo for (i = 1; i < num_tbs; i++) { 4243cd1980bSSara Sharon if (meta->tbs & BIT(i)) 425e705c121SKalle Valo dma_unmap_page(trans->dev, 4266983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, i), 4276983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, i), 428e705c121SKalle Valo DMA_TO_DEVICE); 429e705c121SKalle Valo else 430e705c121SKalle Valo dma_unmap_single(trans->dev, 4316983ba69SSara Sharon iwl_pcie_tfd_tb_get_addr(trans, tfd, 4326983ba69SSara Sharon i), 4336983ba69SSara Sharon iwl_pcie_tfd_tb_get_len(trans, tfd, 4346983ba69SSara Sharon i), 435e705c121SKalle Valo DMA_TO_DEVICE); 436e705c121SKalle Valo } 4376983ba69SSara Sharon 43887e7e25aSEmmanuel Grumbach meta->tbs = 0; 43987e7e25aSEmmanuel Grumbach 4406983ba69SSara Sharon if (trans->cfg->use_tfh) { 4416983ba69SSara Sharon struct iwl_tfh_tfd *tfd_fh = (void *)tfd; 4426983ba69SSara Sharon 4436983ba69SSara Sharon tfd_fh->num_tbs = 0; 4446983ba69SSara Sharon } else { 4456983ba69SSara Sharon struct iwl_tfd *tfd_fh = (void *)tfd; 4466983ba69SSara Sharon 4476983ba69SSara Sharon tfd_fh->num_tbs = 0; 4486983ba69SSara Sharon } 4496983ba69SSara Sharon 450e705c121SKalle Valo } 451e705c121SKalle Valo 452e705c121SKalle Valo /* 453e705c121SKalle Valo * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 454e705c121SKalle Valo * @trans - transport private data 455e705c121SKalle Valo * @txq - tx queue 456e705c121SKalle Valo * @dma_dir - the direction of the DMA mapping 457e705c121SKalle Valo * 458e705c121SKalle Valo * Does NOT advance any TFD circular buffer read/write indexes 459e705c121SKalle Valo * Does NOT free the TFD itself (which is within circular buffer) 460e705c121SKalle Valo */ 4616b35ff91SSara Sharon void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 462e705c121SKalle Valo { 463e705c121SKalle Valo /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 464e705c121SKalle Valo * idx is bounded by n_window 465e705c121SKalle Valo */ 466bb98ecd4SSara Sharon int rd_ptr = txq->read_ptr; 4674ecab561SEmmanuel Grumbach int idx = iwl_pcie_get_cmd_index(txq, rd_ptr); 468e705c121SKalle Valo 469e705c121SKalle Valo lockdep_assert_held(&txq->lock); 470e705c121SKalle Valo 471e705c121SKalle Valo /* We have only q->n_window txq->entries, but we use 472e705c121SKalle Valo * TFD_QUEUE_SIZE_MAX tfds 473e705c121SKalle Valo */ 4746983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr); 475e705c121SKalle Valo 476e705c121SKalle Valo /* free SKB */ 477e705c121SKalle Valo if (txq->entries) { 478e705c121SKalle Valo struct sk_buff *skb; 479e705c121SKalle Valo 480e705c121SKalle Valo skb = txq->entries[idx].skb; 481e705c121SKalle Valo 482e705c121SKalle Valo /* Can be called from irqs-disabled context 483e705c121SKalle Valo * If skb is not NULL, it means that the whole queue is being 484e705c121SKalle Valo * freed and that the queue is not empty - free the skb 485e705c121SKalle Valo */ 486e705c121SKalle Valo if (skb) { 487e705c121SKalle Valo iwl_op_mode_free_skb(trans->op_mode, skb); 488e705c121SKalle Valo txq->entries[idx].skb = NULL; 489e705c121SKalle Valo } 490e705c121SKalle Valo } 491e705c121SKalle Valo } 492e705c121SKalle Valo 493e705c121SKalle Valo static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, 494e705c121SKalle Valo dma_addr_t addr, u16 len, bool reset) 495e705c121SKalle Valo { 4963cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4976983ba69SSara Sharon void *tfd; 498e705c121SKalle Valo u32 num_tbs; 499e705c121SKalle Valo 500bb98ecd4SSara Sharon tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr; 501e705c121SKalle Valo 502e705c121SKalle Valo if (reset) 5036983ba69SSara Sharon memset(tfd, 0, trans_pcie->tfd_size); 504e705c121SKalle Valo 5056983ba69SSara Sharon num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd); 506e705c121SKalle Valo 5076983ba69SSara Sharon /* Each TFD can point to a maximum max_tbs Tx buffers */ 5083cd1980bSSara Sharon if (num_tbs >= trans_pcie->max_tbs) { 509e705c121SKalle Valo IWL_ERR(trans, "Error can not send more than %d chunks\n", 5103cd1980bSSara Sharon trans_pcie->max_tbs); 511e705c121SKalle Valo return -EINVAL; 512e705c121SKalle Valo } 513e705c121SKalle Valo 514e705c121SKalle Valo if (WARN(addr & ~IWL_TX_DMA_MASK, 515e705c121SKalle Valo "Unaligned address = %llx\n", (unsigned long long)addr)) 516e705c121SKalle Valo return -EINVAL; 517e705c121SKalle Valo 5186983ba69SSara Sharon iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len); 519e705c121SKalle Valo 520e705c121SKalle Valo return num_tbs; 521e705c121SKalle Valo } 522e705c121SKalle Valo 52313a3a390SSara Sharon int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 524b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 525e705c121SKalle Valo { 526e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 5277b3e42eaSGolan Ben Ami size_t tfd_sz = trans_pcie->tfd_size * 5287b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size; 5298de437c7SSara Sharon size_t tb0_buf_sz; 530e705c121SKalle Valo int i; 531e705c121SKalle Valo 532e705c121SKalle Valo if (WARN_ON(txq->entries || txq->tfds)) 533e705c121SKalle Valo return -EINVAL; 534e705c121SKalle Valo 535e0498146SSara Sharon if (trans->cfg->use_tfh) 536e0498146SSara Sharon tfd_sz = trans_pcie->tfd_size * slots_num; 537e0498146SSara Sharon 538e99e88a9SKees Cook timer_setup(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, 0); 539e705c121SKalle Valo txq->trans_pcie = trans_pcie; 540e705c121SKalle Valo 541bb98ecd4SSara Sharon txq->n_window = slots_num; 542e705c121SKalle Valo 543e705c121SKalle Valo txq->entries = kcalloc(slots_num, 544e705c121SKalle Valo sizeof(struct iwl_pcie_txq_entry), 545e705c121SKalle Valo GFP_KERNEL); 546e705c121SKalle Valo 547e705c121SKalle Valo if (!txq->entries) 548e705c121SKalle Valo goto error; 549e705c121SKalle Valo 550b8e8d7ceSSara Sharon if (cmd_queue) 551e705c121SKalle Valo for (i = 0; i < slots_num; i++) { 552e705c121SKalle Valo txq->entries[i].cmd = 553e705c121SKalle Valo kmalloc(sizeof(struct iwl_device_cmd), 554e705c121SKalle Valo GFP_KERNEL); 555e705c121SKalle Valo if (!txq->entries[i].cmd) 556e705c121SKalle Valo goto error; 557e705c121SKalle Valo } 558e705c121SKalle Valo 559e705c121SKalle Valo /* Circular buffer of transmit frame descriptors (TFDs), 560e705c121SKalle Valo * shared with device */ 561e705c121SKalle Valo txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, 562bb98ecd4SSara Sharon &txq->dma_addr, GFP_KERNEL); 563e705c121SKalle Valo if (!txq->tfds) 564e705c121SKalle Valo goto error; 565e705c121SKalle Valo 5668de437c7SSara Sharon BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs)); 567e705c121SKalle Valo 5688de437c7SSara Sharon tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num; 569e705c121SKalle Valo 5708de437c7SSara Sharon txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz, 5718de437c7SSara Sharon &txq->first_tb_dma, 572e705c121SKalle Valo GFP_KERNEL); 5738de437c7SSara Sharon if (!txq->first_tb_bufs) 574e705c121SKalle Valo goto err_free_tfds; 575e705c121SKalle Valo 576e705c121SKalle Valo return 0; 577e705c121SKalle Valo err_free_tfds: 578bb98ecd4SSara Sharon dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr); 579e705c121SKalle Valo error: 580b8e8d7ceSSara Sharon if (txq->entries && cmd_queue) 581e705c121SKalle Valo for (i = 0; i < slots_num; i++) 582e705c121SKalle Valo kfree(txq->entries[i].cmd); 583e705c121SKalle Valo kfree(txq->entries); 584e705c121SKalle Valo txq->entries = NULL; 585e705c121SKalle Valo 586e705c121SKalle Valo return -ENOMEM; 587e705c121SKalle Valo 588e705c121SKalle Valo } 589e705c121SKalle Valo 59013a3a390SSara Sharon int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 591b8e8d7ceSSara Sharon int slots_num, bool cmd_queue) 592e705c121SKalle Valo { 593e705c121SKalle Valo int ret; 5947b3e42eaSGolan Ben Ami u32 tfd_queue_max_size = trans->cfg->base_params->max_tfd_queue_size; 595e705c121SKalle Valo 596e705c121SKalle Valo txq->need_update = false; 597e705c121SKalle Valo 5987b3e42eaSGolan Ben Ami /* max_tfd_queue_size must be power-of-two size, otherwise 599e705c121SKalle Valo * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ 6007b3e42eaSGolan Ben Ami if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1), 6017b3e42eaSGolan Ben Ami "Max tfd queue size must be a power of two, but is %d", 6027b3e42eaSGolan Ben Ami tfd_queue_max_size)) 6037b3e42eaSGolan Ben Ami return -EINVAL; 604e705c121SKalle Valo 605e705c121SKalle Valo /* Initialize queue's high/low-water marks, and head/tail indexes */ 606b8e8d7ceSSara Sharon ret = iwl_queue_init(txq, slots_num); 607e705c121SKalle Valo if (ret) 608e705c121SKalle Valo return ret; 609e705c121SKalle Valo 610e705c121SKalle Valo spin_lock_init(&txq->lock); 611faead41cSJohannes Berg 612b8e8d7ceSSara Sharon if (cmd_queue) { 613faead41cSJohannes Berg static struct lock_class_key iwl_pcie_cmd_queue_lock_class; 614faead41cSJohannes Berg 615faead41cSJohannes Berg lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class); 616faead41cSJohannes Berg } 617faead41cSJohannes Berg 6183955525dSEmmanuel Grumbach __skb_queue_head_init(&txq->overflow_q); 619e705c121SKalle Valo 620e705c121SKalle Valo return 0; 621e705c121SKalle Valo } 622e705c121SKalle Valo 6239bb3d5a0SEmmanuel Grumbach void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie, 62421cb3222SJohannes Berg struct sk_buff *skb) 6256eb5e529SEmmanuel Grumbach { 62621cb3222SJohannes Berg struct page **page_ptr; 6276eb5e529SEmmanuel Grumbach 62821cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 6296eb5e529SEmmanuel Grumbach 63021cb3222SJohannes Berg if (*page_ptr) { 63121cb3222SJohannes Berg __free_page(*page_ptr); 63221cb3222SJohannes Berg *page_ptr = NULL; 6336eb5e529SEmmanuel Grumbach } 6346eb5e529SEmmanuel Grumbach } 6356eb5e529SEmmanuel Grumbach 63601d11cd1SSara Sharon static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans) 63701d11cd1SSara Sharon { 63801d11cd1SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 63901d11cd1SSara Sharon 64001d11cd1SSara Sharon lockdep_assert_held(&trans_pcie->reg_lock); 64101d11cd1SSara Sharon 64201d11cd1SSara Sharon if (!trans->cfg->base_params->apmg_wake_up_wa) 64301d11cd1SSara Sharon return; 64401d11cd1SSara Sharon if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) 64501d11cd1SSara Sharon return; 64601d11cd1SSara Sharon 64701d11cd1SSara Sharon trans_pcie->cmd_hold_nic_awake = false; 64801d11cd1SSara Sharon __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 649a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 65001d11cd1SSara Sharon } 65101d11cd1SSara Sharon 652e705c121SKalle Valo /* 653e705c121SKalle Valo * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's 654e705c121SKalle Valo */ 655e705c121SKalle Valo static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) 656e705c121SKalle Valo { 657e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 658b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 659e705c121SKalle Valo 660e705c121SKalle Valo spin_lock_bh(&txq->lock); 661bb98ecd4SSara Sharon while (txq->write_ptr != txq->read_ptr) { 662e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 663bb98ecd4SSara Sharon txq_id, txq->read_ptr); 6646eb5e529SEmmanuel Grumbach 6656eb5e529SEmmanuel Grumbach if (txq_id != trans_pcie->cmd_queue) { 666bb98ecd4SSara Sharon struct sk_buff *skb = txq->entries[txq->read_ptr].skb; 6676eb5e529SEmmanuel Grumbach 6686eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 6696eb5e529SEmmanuel Grumbach continue; 6706eb5e529SEmmanuel Grumbach 67121cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 6726eb5e529SEmmanuel Grumbach } 673e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 6747b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 67501d11cd1SSara Sharon 676bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 67701d11cd1SSara Sharon unsigned long flags; 67801d11cd1SSara Sharon 67901d11cd1SSara Sharon spin_lock_irqsave(&trans_pcie->reg_lock, flags); 6800d52497aSEmmanuel Grumbach if (txq_id == trans_pcie->cmd_queue) 68101d11cd1SSara Sharon iwl_pcie_clear_cmd_in_flight(trans); 68201d11cd1SSara Sharon spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 68301d11cd1SSara Sharon } 684e705c121SKalle Valo } 6853955525dSEmmanuel Grumbach 6863955525dSEmmanuel Grumbach while (!skb_queue_empty(&txq->overflow_q)) { 6873955525dSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 6883955525dSEmmanuel Grumbach 6893955525dSEmmanuel Grumbach iwl_op_mode_free_skb(trans->op_mode, skb); 6903955525dSEmmanuel Grumbach } 6913955525dSEmmanuel Grumbach 692e705c121SKalle Valo spin_unlock_bh(&txq->lock); 693e705c121SKalle Valo 694e705c121SKalle Valo /* just in case - this queue may have been stopped */ 695e705c121SKalle Valo iwl_wake_queue(trans, txq); 696e705c121SKalle Valo } 697e705c121SKalle Valo 698e705c121SKalle Valo /* 699e705c121SKalle Valo * iwl_pcie_txq_free - Deallocate DMA queue. 700e705c121SKalle Valo * @txq: Transmit queue to deallocate. 701e705c121SKalle Valo * 702e705c121SKalle Valo * Empty queue by removing and destroying all BD's. 703e705c121SKalle Valo * Free all buffers. 704e705c121SKalle Valo * 0-fill, but do not free "txq" descriptor structure. 705e705c121SKalle Valo */ 706e705c121SKalle Valo static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) 707e705c121SKalle Valo { 708e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 709b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 710e705c121SKalle Valo struct device *dev = trans->dev; 711e705c121SKalle Valo int i; 712e705c121SKalle Valo 713e705c121SKalle Valo if (WARN_ON(!txq)) 714e705c121SKalle Valo return; 715e705c121SKalle Valo 716e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 717e705c121SKalle Valo 718e705c121SKalle Valo /* De-alloc array of command/tx buffers */ 719e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue) 720bb98ecd4SSara Sharon for (i = 0; i < txq->n_window; i++) { 721e705c121SKalle Valo kzfree(txq->entries[i].cmd); 722e705c121SKalle Valo kzfree(txq->entries[i].free_buf); 723e705c121SKalle Valo } 724e705c121SKalle Valo 725e705c121SKalle Valo /* De-alloc circular buffer of TFDs */ 726e705c121SKalle Valo if (txq->tfds) { 727e705c121SKalle Valo dma_free_coherent(dev, 7287b3e42eaSGolan Ben Ami trans_pcie->tfd_size * 7297b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 730bb98ecd4SSara Sharon txq->tfds, txq->dma_addr); 731bb98ecd4SSara Sharon txq->dma_addr = 0; 732e705c121SKalle Valo txq->tfds = NULL; 733e705c121SKalle Valo 734e705c121SKalle Valo dma_free_coherent(dev, 735bb98ecd4SSara Sharon sizeof(*txq->first_tb_bufs) * txq->n_window, 7368de437c7SSara Sharon txq->first_tb_bufs, txq->first_tb_dma); 737e705c121SKalle Valo } 738e705c121SKalle Valo 739e705c121SKalle Valo kfree(txq->entries); 740e705c121SKalle Valo txq->entries = NULL; 741e705c121SKalle Valo 742e705c121SKalle Valo del_timer_sync(&txq->stuck_timer); 743e705c121SKalle Valo 744e705c121SKalle Valo /* 0-fill queue descriptor structure */ 745e705c121SKalle Valo memset(txq, 0, sizeof(*txq)); 746e705c121SKalle Valo } 747e705c121SKalle Valo 748e705c121SKalle Valo void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) 749e705c121SKalle Valo { 750e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 751e705c121SKalle Valo int nq = trans->cfg->base_params->num_of_queues; 752e705c121SKalle Valo int chan; 753e705c121SKalle Valo u32 reg_val; 754e705c121SKalle Valo int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - 755e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); 756e705c121SKalle Valo 757e705c121SKalle Valo /* make sure all queue are not stopped/used */ 758e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 759e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 760e705c121SKalle Valo 761e705c121SKalle Valo trans_pcie->scd_base_addr = 762e705c121SKalle Valo iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); 763e705c121SKalle Valo 764e705c121SKalle Valo WARN_ON(scd_base_addr != 0 && 765e705c121SKalle Valo scd_base_addr != trans_pcie->scd_base_addr); 766e705c121SKalle Valo 767e705c121SKalle Valo /* reset context data, TX status and translation data */ 768e705c121SKalle Valo iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + 769e705c121SKalle Valo SCD_CONTEXT_MEM_LOWER_BOUND, 770e705c121SKalle Valo NULL, clear_dwords); 771e705c121SKalle Valo 772e705c121SKalle Valo iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 773e705c121SKalle Valo trans_pcie->scd_bc_tbls.dma >> 10); 774e705c121SKalle Valo 775e705c121SKalle Valo /* The chain extension of the SCD doesn't work well. This feature is 776e705c121SKalle Valo * enabled by default by the HW, so we need to disable it manually. 777e705c121SKalle Valo */ 778e705c121SKalle Valo if (trans->cfg->base_params->scd_chain_ext_wa) 779e705c121SKalle Valo iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); 780e705c121SKalle Valo 781e705c121SKalle Valo iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, 782e705c121SKalle Valo trans_pcie->cmd_fifo, 783e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout); 784e705c121SKalle Valo 785e705c121SKalle Valo /* Activate all Tx DMA/FIFO channels */ 786e705c121SKalle Valo iwl_scd_activate_fifos(trans); 787e705c121SKalle Valo 788e705c121SKalle Valo /* Enable DMA channel */ 789e705c121SKalle Valo for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) 790e705c121SKalle Valo iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), 791e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 792e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 793e705c121SKalle Valo 794e705c121SKalle Valo /* Update FH chicken bits */ 795e705c121SKalle Valo reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); 796e705c121SKalle Valo iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, 797e705c121SKalle Valo reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 798e705c121SKalle Valo 799e705c121SKalle Valo /* Enable L1-Active */ 8006e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 801e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 802e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 803e705c121SKalle Valo } 804e705c121SKalle Valo 805e705c121SKalle Valo void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) 806e705c121SKalle Valo { 807e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 808e705c121SKalle Valo int txq_id; 809e705c121SKalle Valo 81013a3a390SSara Sharon /* 81113a3a390SSara Sharon * we should never get here in gen2 trans mode return early to avoid 81213a3a390SSara Sharon * having invalid accesses 81313a3a390SSara Sharon */ 81413a3a390SSara Sharon if (WARN_ON_ONCE(trans->cfg->gen2)) 81513a3a390SSara Sharon return; 81613a3a390SSara Sharon 817e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 818e705c121SKalle Valo txq_id++) { 819b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 820e22744afSSara Sharon if (trans->cfg->use_tfh) 821e22744afSSara Sharon iwl_write_direct64(trans, 822e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 823bb98ecd4SSara Sharon txq->dma_addr); 824e22744afSSara Sharon else 825e22744afSSara Sharon iwl_write_direct32(trans, 826e22744afSSara Sharon FH_MEM_CBBC_QUEUE(trans, txq_id), 827bb98ecd4SSara Sharon txq->dma_addr >> 8); 828e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 829bb98ecd4SSara Sharon txq->read_ptr = 0; 830bb98ecd4SSara Sharon txq->write_ptr = 0; 831e705c121SKalle Valo } 832e705c121SKalle Valo 833e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 834e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 835e705c121SKalle Valo trans_pcie->kw.dma >> 4); 836e705c121SKalle Valo 837e705c121SKalle Valo /* 838e705c121SKalle Valo * Send 0 as the scd_base_addr since the device may have be reset 839e705c121SKalle Valo * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will 840e705c121SKalle Valo * contain garbage. 841e705c121SKalle Valo */ 842e705c121SKalle Valo iwl_pcie_tx_start(trans, 0); 843e705c121SKalle Valo } 844e705c121SKalle Valo 845e705c121SKalle Valo static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans) 846e705c121SKalle Valo { 847e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 848e705c121SKalle Valo unsigned long flags; 849e705c121SKalle Valo int ch, ret; 850e705c121SKalle Valo u32 mask = 0; 851e705c121SKalle Valo 852e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 853e705c121SKalle Valo 85423ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 855e705c121SKalle Valo goto out; 856e705c121SKalle Valo 857e705c121SKalle Valo /* Stop each Tx DMA channel */ 858e705c121SKalle Valo for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { 859e705c121SKalle Valo iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 860e705c121SKalle Valo mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch); 861e705c121SKalle Valo } 862e705c121SKalle Valo 863e705c121SKalle Valo /* Wait for DMA channels to be idle */ 864e705c121SKalle Valo ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000); 865e705c121SKalle Valo if (ret < 0) 866e705c121SKalle Valo IWL_ERR(trans, 867e705c121SKalle Valo "Failing on timeout while stopping DMA channel %d [0x%08x]\n", 868e705c121SKalle Valo ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG)); 869e705c121SKalle Valo 870e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 871e705c121SKalle Valo 872e705c121SKalle Valo out: 873e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 874e705c121SKalle Valo } 875e705c121SKalle Valo 876e705c121SKalle Valo /* 877e705c121SKalle Valo * iwl_pcie_tx_stop - Stop all Tx DMA channels 878e705c121SKalle Valo */ 879e705c121SKalle Valo int iwl_pcie_tx_stop(struct iwl_trans *trans) 880e705c121SKalle Valo { 881e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 882e705c121SKalle Valo int txq_id; 883e705c121SKalle Valo 884e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 885e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 886e705c121SKalle Valo 887e705c121SKalle Valo /* Turn off all Tx DMA channels */ 888e705c121SKalle Valo iwl_pcie_tx_stop_fh(trans); 889e705c121SKalle Valo 890e705c121SKalle Valo /* 891e705c121SKalle Valo * This function can be called before the op_mode disabled the 892e705c121SKalle Valo * queues. This happens when we have an rfkill interrupt. 893e705c121SKalle Valo * Since we stop Tx altogether - mark the queues as stopped. 894e705c121SKalle Valo */ 895e705c121SKalle Valo memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 896e705c121SKalle Valo memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 897e705c121SKalle Valo 898e705c121SKalle Valo /* This can happen: start_hw, stop_device */ 899b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 900e705c121SKalle Valo return 0; 901e705c121SKalle Valo 902e705c121SKalle Valo /* Unmap DMA from host system and free skb's */ 903e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 904e705c121SKalle Valo txq_id++) 905e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 906e705c121SKalle Valo 907e705c121SKalle Valo return 0; 908e705c121SKalle Valo } 909e705c121SKalle Valo 910e705c121SKalle Valo /* 911e705c121SKalle Valo * iwl_trans_tx_free - Free TXQ Context 912e705c121SKalle Valo * 913e705c121SKalle Valo * Destroy all TX DMA queues and structures 914e705c121SKalle Valo */ 915e705c121SKalle Valo void iwl_pcie_tx_free(struct iwl_trans *trans) 916e705c121SKalle Valo { 917e705c121SKalle Valo int txq_id; 918e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 919e705c121SKalle Valo 920de74c455SSara Sharon memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 921de74c455SSara Sharon 922e705c121SKalle Valo /* Tx queues */ 923b2a3b1c1SSara Sharon if (trans_pcie->txq_memory) { 924e705c121SKalle Valo for (txq_id = 0; 925b2a3b1c1SSara Sharon txq_id < trans->cfg->base_params->num_of_queues; 926b2a3b1c1SSara Sharon txq_id++) { 927e705c121SKalle Valo iwl_pcie_txq_free(trans, txq_id); 928b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = NULL; 929b2a3b1c1SSara Sharon } 930e705c121SKalle Valo } 931e705c121SKalle Valo 932b2a3b1c1SSara Sharon kfree(trans_pcie->txq_memory); 933b2a3b1c1SSara Sharon trans_pcie->txq_memory = NULL; 934e705c121SKalle Valo 935e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); 936e705c121SKalle Valo 937e705c121SKalle Valo iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); 938e705c121SKalle Valo } 939e705c121SKalle Valo 940e705c121SKalle Valo /* 941e705c121SKalle Valo * iwl_pcie_tx_alloc - allocate TX context 942e705c121SKalle Valo * Allocate all Tx DMA structures and initialize them 943e705c121SKalle Valo */ 944e705c121SKalle Valo static int iwl_pcie_tx_alloc(struct iwl_trans *trans) 945e705c121SKalle Valo { 946e705c121SKalle Valo int ret; 947e705c121SKalle Valo int txq_id, slots_num; 948e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 9497b3e42eaSGolan Ben Ami u16 bc_tbls_size = trans->cfg->base_params->num_of_queues; 950e705c121SKalle Valo 9517b3e42eaSGolan Ben Ami bc_tbls_size *= (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ? 9527b3e42eaSGolan Ben Ami sizeof(struct iwl_gen3_bc_tbl) : 953e705c121SKalle Valo sizeof(struct iwlagn_scd_bc_tbl); 954e705c121SKalle Valo 955e705c121SKalle Valo /*It is not allowed to alloc twice, so warn when this happens. 956e705c121SKalle Valo * We cannot rely on the previous allocation, so free and fail */ 957b2a3b1c1SSara Sharon if (WARN_ON(trans_pcie->txq_memory)) { 958e705c121SKalle Valo ret = -EINVAL; 959e705c121SKalle Valo goto error; 960e705c121SKalle Valo } 961e705c121SKalle Valo 962e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, 9637b3e42eaSGolan Ben Ami bc_tbls_size); 964e705c121SKalle Valo if (ret) { 965e705c121SKalle Valo IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 966e705c121SKalle Valo goto error; 967e705c121SKalle Valo } 968e705c121SKalle Valo 969e705c121SKalle Valo /* Alloc keep-warm buffer */ 970e705c121SKalle Valo ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); 971e705c121SKalle Valo if (ret) { 972e705c121SKalle Valo IWL_ERR(trans, "Keep Warm allocation failed\n"); 973e705c121SKalle Valo goto error; 974e705c121SKalle Valo } 975e705c121SKalle Valo 976b2a3b1c1SSara Sharon trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues, 977e705c121SKalle Valo sizeof(struct iwl_txq), GFP_KERNEL); 978b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 979e705c121SKalle Valo IWL_ERR(trans, "Not enough memory for txq\n"); 980e705c121SKalle Valo ret = -ENOMEM; 981e705c121SKalle Valo goto error; 982e705c121SKalle Valo } 983e705c121SKalle Valo 984e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 985e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 986e705c121SKalle Valo txq_id++) { 987b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 988b8e8d7ceSSara Sharon 989ff911dcaSShaul Triebitz if (cmd_queue) 990718a8b23SShaul Triebitz slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 991ff911dcaSShaul Triebitz trans->cfg->min_txq_size); 992ff911dcaSShaul Triebitz else 993718a8b23SShaul Triebitz slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 994c30aef01SShaul Triebitz trans->cfg->min_256_ba_txq_size); 995b2a3b1c1SSara Sharon trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id]; 996b2a3b1c1SSara Sharon ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id], 997b8e8d7ceSSara Sharon slots_num, cmd_queue); 998e705c121SKalle Valo if (ret) { 999e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 1000e705c121SKalle Valo goto error; 1001e705c121SKalle Valo } 1002b8e8d7ceSSara Sharon trans_pcie->txq[txq_id]->id = txq_id; 1003e705c121SKalle Valo } 1004e705c121SKalle Valo 1005e705c121SKalle Valo return 0; 1006e705c121SKalle Valo 1007e705c121SKalle Valo error: 1008e705c121SKalle Valo iwl_pcie_tx_free(trans); 1009e705c121SKalle Valo 1010e705c121SKalle Valo return ret; 1011e705c121SKalle Valo } 1012eda50cdeSSara Sharon 1013e705c121SKalle Valo int iwl_pcie_tx_init(struct iwl_trans *trans) 1014e705c121SKalle Valo { 1015e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1016e705c121SKalle Valo int ret; 1017e705c121SKalle Valo int txq_id, slots_num; 1018e705c121SKalle Valo bool alloc = false; 1019e705c121SKalle Valo 1020b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) { 1021e705c121SKalle Valo ret = iwl_pcie_tx_alloc(trans); 1022e705c121SKalle Valo if (ret) 1023e705c121SKalle Valo goto error; 1024e705c121SKalle Valo alloc = true; 1025e705c121SKalle Valo } 1026e705c121SKalle Valo 1027e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1028e705c121SKalle Valo 1029e705c121SKalle Valo /* Turn off all Tx DMA fifos */ 1030e705c121SKalle Valo iwl_scd_deactivate_fifos(trans); 1031e705c121SKalle Valo 1032e705c121SKalle Valo /* Tell NIC where to find the "keep warm" buffer */ 1033e705c121SKalle Valo iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, 1034e705c121SKalle Valo trans_pcie->kw.dma >> 4); 1035e705c121SKalle Valo 1036e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1037e705c121SKalle Valo 1038e705c121SKalle Valo /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 1039e705c121SKalle Valo for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; 1040e705c121SKalle Valo txq_id++) { 1041b8e8d7ceSSara Sharon bool cmd_queue = (txq_id == trans_pcie->cmd_queue); 1042b8e8d7ceSSara Sharon 1043ff911dcaSShaul Triebitz if (cmd_queue) 1044718a8b23SShaul Triebitz slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE, 1045ff911dcaSShaul Triebitz trans->cfg->min_txq_size); 1046ff911dcaSShaul Triebitz else 1047718a8b23SShaul Triebitz slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE, 1048c30aef01SShaul Triebitz trans->cfg->min_256_ba_txq_size); 1049b2a3b1c1SSara Sharon ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id], 1050b8e8d7ceSSara Sharon slots_num, cmd_queue); 1051e705c121SKalle Valo if (ret) { 1052e705c121SKalle Valo IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1053e705c121SKalle Valo goto error; 1054e705c121SKalle Valo } 1055e705c121SKalle Valo 1056eda50cdeSSara Sharon /* 1057eda50cdeSSara Sharon * Tell nic where to find circular buffer of TFDs for a 1058eda50cdeSSara Sharon * given Tx queue, and enable the DMA channel used for that 1059eda50cdeSSara Sharon * queue. 1060eda50cdeSSara Sharon * Circular buffer (TFD queue in DRAM) physical base address 1061eda50cdeSSara Sharon */ 1062eda50cdeSSara Sharon iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id), 1063b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->dma_addr >> 8); 1064ae79785fSSara Sharon } 1065e22744afSSara Sharon 1066e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE); 1067e705c121SKalle Valo if (trans->cfg->base_params->num_of_queues > 20) 1068e705c121SKalle Valo iwl_set_bits_prph(trans, SCD_GP_CTRL, 1069e705c121SKalle Valo SCD_GP_CTRL_ENABLE_31_QUEUES); 1070e705c121SKalle Valo 1071e705c121SKalle Valo return 0; 1072e705c121SKalle Valo error: 1073e705c121SKalle Valo /*Upon error, free only if we allocated something */ 1074e705c121SKalle Valo if (alloc) 1075e705c121SKalle Valo iwl_pcie_tx_free(trans); 1076e705c121SKalle Valo return ret; 1077e705c121SKalle Valo } 1078e705c121SKalle Valo 1079e705c121SKalle Valo static inline void iwl_pcie_txq_progress(struct iwl_txq *txq) 1080e705c121SKalle Valo { 1081e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1082e705c121SKalle Valo 1083e705c121SKalle Valo if (!txq->wd_timeout) 1084e705c121SKalle Valo return; 1085e705c121SKalle Valo 1086e705c121SKalle Valo /* 1087e705c121SKalle Valo * station is asleep and we send data - that must 1088e705c121SKalle Valo * be uAPSD or PS-Poll. Don't rearm the timer. 1089e705c121SKalle Valo */ 1090e705c121SKalle Valo if (txq->frozen) 1091e705c121SKalle Valo return; 1092e705c121SKalle Valo 1093e705c121SKalle Valo /* 1094e705c121SKalle Valo * if empty delete timer, otherwise move timer forward 1095e705c121SKalle Valo * since we're making progress on this queue 1096e705c121SKalle Valo */ 1097bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 1098e705c121SKalle Valo del_timer(&txq->stuck_timer); 1099e705c121SKalle Valo else 1100e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1101e705c121SKalle Valo } 1102e705c121SKalle Valo 1103e705c121SKalle Valo /* Frees buffers until index _not_ inclusive */ 1104e705c121SKalle Valo void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 1105e705c121SKalle Valo struct sk_buff_head *skbs) 1106e705c121SKalle Valo { 1107e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1108b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 11097b3e42eaSGolan Ben Ami int tfd_num = iwl_pcie_get_cmd_index(txq, ssn); 11107b3e42eaSGolan Ben Ami int read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1111e705c121SKalle Valo int last_to_free; 1112e705c121SKalle Valo 1113e705c121SKalle Valo /* This function is not meant to release cmd queue*/ 1114e705c121SKalle Valo if (WARN_ON(txq_id == trans_pcie->cmd_queue)) 1115e705c121SKalle Valo return; 1116e705c121SKalle Valo 1117e705c121SKalle Valo spin_lock_bh(&txq->lock); 1118e705c121SKalle Valo 1119de74c455SSara Sharon if (!test_bit(txq_id, trans_pcie->queue_used)) { 1120e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", 1121e705c121SKalle Valo txq_id, ssn); 1122e705c121SKalle Valo goto out; 1123e705c121SKalle Valo } 1124e705c121SKalle Valo 11257b3e42eaSGolan Ben Ami if (read_ptr == tfd_num) 1126e705c121SKalle Valo goto out; 1127e705c121SKalle Valo 1128e705c121SKalle Valo IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", 1129bb98ecd4SSara Sharon txq_id, txq->read_ptr, tfd_num, ssn); 1130e705c121SKalle Valo 1131e705c121SKalle Valo /*Since we free until index _not_ inclusive, the one before index is 1132e705c121SKalle Valo * the last we will free. This one must be used */ 11337b3e42eaSGolan Ben Ami last_to_free = iwl_queue_dec_wrap(trans, tfd_num); 1134e705c121SKalle Valo 1135bb98ecd4SSara Sharon if (!iwl_queue_used(txq, last_to_free)) { 1136e705c121SKalle Valo IWL_ERR(trans, 113781f0c661SGolan Ben Ami "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", 11387b3e42eaSGolan Ben Ami __func__, txq_id, last_to_free, 11397b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1140bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1141e705c121SKalle Valo goto out; 1142e705c121SKalle Valo } 1143e705c121SKalle Valo 1144e705c121SKalle Valo if (WARN_ON(!skb_queue_empty(skbs))) 1145e705c121SKalle Valo goto out; 1146e705c121SKalle Valo 1147e705c121SKalle Valo for (; 11487b3e42eaSGolan Ben Ami read_ptr != tfd_num; 11497b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr), 11507b3e42eaSGolan Ben Ami read_ptr = iwl_pcie_get_cmd_index(txq, txq->read_ptr)) { 11517b3e42eaSGolan Ben Ami struct sk_buff *skb = txq->entries[read_ptr].skb; 1152e705c121SKalle Valo 11536eb5e529SEmmanuel Grumbach if (WARN_ON_ONCE(!skb)) 1154e705c121SKalle Valo continue; 1155e705c121SKalle Valo 115621cb3222SJohannes Berg iwl_pcie_free_tso_page(trans_pcie, skb); 11576eb5e529SEmmanuel Grumbach 11586eb5e529SEmmanuel Grumbach __skb_queue_tail(skbs, skb); 1159e705c121SKalle Valo 11607b3e42eaSGolan Ben Ami txq->entries[read_ptr].skb = NULL; 1161e705c121SKalle Valo 11624fe10bc6SSara Sharon if (!trans->cfg->use_tfh) 1163e705c121SKalle Valo iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); 1164e705c121SKalle Valo 1165e705c121SKalle Valo iwl_pcie_txq_free_tfd(trans, txq); 1166e705c121SKalle Valo } 1167e705c121SKalle Valo 1168e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1169e705c121SKalle Valo 11707b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark && 11713955525dSEmmanuel Grumbach test_bit(txq_id, trans_pcie->queue_stopped)) { 1172685b346cSEmmanuel Grumbach struct sk_buff_head overflow_skbs; 11733955525dSEmmanuel Grumbach 1174685b346cSEmmanuel Grumbach __skb_queue_head_init(&overflow_skbs); 1175685b346cSEmmanuel Grumbach skb_queue_splice_init(&txq->overflow_q, &overflow_skbs); 11763955525dSEmmanuel Grumbach 11773955525dSEmmanuel Grumbach /* 11782ae48edcSSara Sharon * We are going to transmit from the overflow queue. 11792ae48edcSSara Sharon * Remember this state so that wait_for_txq_empty will know we 11802ae48edcSSara Sharon * are adding more packets to the TFD queue. It cannot rely on 11812ae48edcSSara Sharon * the state of &txq->overflow_q, as we just emptied it, but 11822ae48edcSSara Sharon * haven't TXed the content yet. 11832ae48edcSSara Sharon */ 11842ae48edcSSara Sharon txq->overflow_tx = true; 11852ae48edcSSara Sharon 11862ae48edcSSara Sharon /* 11873955525dSEmmanuel Grumbach * This is tricky: we are in reclaim path which is non 11883955525dSEmmanuel Grumbach * re-entrant, so noone will try to take the access the 11893955525dSEmmanuel Grumbach * txq data from that path. We stopped tx, so we can't 11903955525dSEmmanuel Grumbach * have tx as well. Bottom line, we can unlock and re-lock 11913955525dSEmmanuel Grumbach * later. 11923955525dSEmmanuel Grumbach */ 11933955525dSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 11943955525dSEmmanuel Grumbach 1195685b346cSEmmanuel Grumbach while (!skb_queue_empty(&overflow_skbs)) { 1196685b346cSEmmanuel Grumbach struct sk_buff *skb = __skb_dequeue(&overflow_skbs); 119721cb3222SJohannes Berg struct iwl_device_cmd *dev_cmd_ptr; 119821cb3222SJohannes Berg 119921cb3222SJohannes Berg dev_cmd_ptr = *(void **)((u8 *)skb->cb + 120021cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 12013955525dSEmmanuel Grumbach 12023955525dSEmmanuel Grumbach /* 12033955525dSEmmanuel Grumbach * Note that we can very well be overflowing again. 12043955525dSEmmanuel Grumbach * In that case, iwl_queue_space will be small again 12053955525dSEmmanuel Grumbach * and we won't wake mac80211's queue. 12063955525dSEmmanuel Grumbach */ 1207f79b8f9dSEmmanuel Grumbach iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id); 12083955525dSEmmanuel Grumbach } 12093955525dSEmmanuel Grumbach 12107b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) > txq->low_mark) 1211e705c121SKalle Valo iwl_wake_queue(trans, txq); 121236817294SSara Sharon 121336817294SSara Sharon spin_lock_bh(&txq->lock); 12142ae48edcSSara Sharon txq->overflow_tx = false; 12153955525dSEmmanuel Grumbach } 1216e705c121SKalle Valo 1217e705c121SKalle Valo out: 1218e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1219e705c121SKalle Valo } 1220e705c121SKalle Valo 1221ba7136f3SAlex Malamud /* Set wr_ptr of specific device and txq */ 1222ba7136f3SAlex Malamud void iwl_trans_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr) 1223ba7136f3SAlex Malamud { 1224ba7136f3SAlex Malamud struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1225ba7136f3SAlex Malamud struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1226ba7136f3SAlex Malamud 1227ba7136f3SAlex Malamud spin_lock_bh(&txq->lock); 1228ba7136f3SAlex Malamud 1229ba7136f3SAlex Malamud txq->write_ptr = ptr; 1230ba7136f3SAlex Malamud txq->read_ptr = txq->write_ptr; 1231ba7136f3SAlex Malamud 1232ba7136f3SAlex Malamud spin_unlock_bh(&txq->lock); 1233ba7136f3SAlex Malamud } 1234ba7136f3SAlex Malamud 1235e705c121SKalle Valo static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans, 1236e705c121SKalle Valo const struct iwl_host_cmd *cmd) 1237e705c121SKalle Valo { 1238e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1239a8cbb46fSGolan Ben Ami const struct iwl_cfg *cfg = trans->cfg; 1240e705c121SKalle Valo int ret; 1241e705c121SKalle Valo 1242e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1243e705c121SKalle Valo 12442b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 1245f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1246f60c9e59SEmmanuel Grumbach return -ENODEV; 12472b3fae66SMatt Chen 1248e705c121SKalle Valo /* 1249e705c121SKalle Valo * wake up the NIC to make sure that the firmware will see the host 1250e705c121SKalle Valo * command - we will let the NIC sleep once all the host commands 1251e705c121SKalle Valo * returned. This needs to be done only on NICs that have 1252e705c121SKalle Valo * apmg_wake_up_wa set. 1253e705c121SKalle Valo */ 1254a8cbb46fSGolan Ben Ami if (cfg->base_params->apmg_wake_up_wa && 1255e705c121SKalle Valo !trans_pcie->cmd_hold_nic_awake) { 1256e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1257a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1258e705c121SKalle Valo 1259e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1260a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_val_mac_access_en), 1261a8cbb46fSGolan Ben Ami (BIT(cfg->csr->flag_mac_clock_ready) | 1262e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 1263e705c121SKalle Valo 15000); 1264e705c121SKalle Valo if (ret < 0) { 1265e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1266a8cbb46fSGolan Ben Ami BIT(cfg->csr->flag_mac_access_req)); 1267e705c121SKalle Valo IWL_ERR(trans, "Failed to wake NIC for hcmd\n"); 1268e705c121SKalle Valo return -EIO; 1269e705c121SKalle Valo } 1270e705c121SKalle Valo trans_pcie->cmd_hold_nic_awake = true; 1271e705c121SKalle Valo } 1272e705c121SKalle Valo 1273e705c121SKalle Valo return 0; 1274e705c121SKalle Valo } 1275e705c121SKalle Valo 1276e705c121SKalle Valo /* 1277e705c121SKalle Valo * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd 1278e705c121SKalle Valo * 1279e705c121SKalle Valo * When FW advances 'R' index, all entries between old and new 'R' index 1280e705c121SKalle Valo * need to be reclaimed. As result, some free space forms. If there is 1281e705c121SKalle Valo * enough free space (> low mark), wake the stack that feeds us. 1282e705c121SKalle Valo */ 128389d5e833SGolan Ben Ami void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) 1284e705c121SKalle Valo { 1285e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1286b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1287e705c121SKalle Valo unsigned long flags; 1288e705c121SKalle Valo int nfreed = 0; 1289f5955a6cSGolan Ben Ami u16 r; 1290e705c121SKalle Valo 1291e705c121SKalle Valo lockdep_assert_held(&txq->lock); 1292e705c121SKalle Valo 1293f5955a6cSGolan Ben Ami idx = iwl_pcie_get_cmd_index(txq, idx); 1294f5955a6cSGolan Ben Ami r = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1295f5955a6cSGolan Ben Ami 12967b3e42eaSGolan Ben Ami if (idx >= trans->cfg->base_params->max_tfd_queue_size || 12977b3e42eaSGolan Ben Ami (!iwl_queue_used(txq, idx))) { 12980916224eSSara Sharon WARN_ONCE(test_bit(txq_id, trans_pcie->queue_used), 1299e705c121SKalle Valo "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", 13007b3e42eaSGolan Ben Ami __func__, txq_id, idx, 13017b3e42eaSGolan Ben Ami trans->cfg->base_params->max_tfd_queue_size, 1302bb98ecd4SSara Sharon txq->write_ptr, txq->read_ptr); 1303e705c121SKalle Valo return; 1304e705c121SKalle Valo } 1305e705c121SKalle Valo 13067b3e42eaSGolan Ben Ami for (idx = iwl_queue_inc_wrap(trans, idx); r != idx; 13077b3e42eaSGolan Ben Ami r = iwl_queue_inc_wrap(trans, r)) { 13087b3e42eaSGolan Ben Ami txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1309e705c121SKalle Valo 1310e705c121SKalle Valo if (nfreed++ > 0) { 1311e705c121SKalle Valo IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", 1312f5955a6cSGolan Ben Ami idx, txq->write_ptr, r); 1313e705c121SKalle Valo iwl_force_nmi(trans); 1314e705c121SKalle Valo } 1315e705c121SKalle Valo } 1316e705c121SKalle Valo 1317bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) { 1318e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1319e705c121SKalle Valo iwl_pcie_clear_cmd_in_flight(trans); 1320e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1321e705c121SKalle Valo } 1322e705c121SKalle Valo 1323e705c121SKalle Valo iwl_pcie_txq_progress(txq); 1324e705c121SKalle Valo } 1325e705c121SKalle Valo 1326e705c121SKalle Valo static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, 1327e705c121SKalle Valo u16 txq_id) 1328e705c121SKalle Valo { 1329e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1330e705c121SKalle Valo u32 tbl_dw_addr; 1331e705c121SKalle Valo u32 tbl_dw; 1332e705c121SKalle Valo u16 scd_q2ratid; 1333e705c121SKalle Valo 1334e705c121SKalle Valo scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; 1335e705c121SKalle Valo 1336e705c121SKalle Valo tbl_dw_addr = trans_pcie->scd_base_addr + 1337e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); 1338e705c121SKalle Valo 1339e705c121SKalle Valo tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); 1340e705c121SKalle Valo 1341e705c121SKalle Valo if (txq_id & 0x1) 1342e705c121SKalle Valo tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 1343e705c121SKalle Valo else 1344e705c121SKalle Valo tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 1345e705c121SKalle Valo 1346e705c121SKalle Valo iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); 1347e705c121SKalle Valo 1348e705c121SKalle Valo return 0; 1349e705c121SKalle Valo } 1350e705c121SKalle Valo 1351e705c121SKalle Valo /* Receiver address (actually, Rx station's index into station table), 1352e705c121SKalle Valo * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ 1353e705c121SKalle Valo #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) 1354e705c121SKalle Valo 1355dcfbd67bSEmmanuel Grumbach bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn, 1356e705c121SKalle Valo const struct iwl_trans_txq_scd_cfg *cfg, 1357e705c121SKalle Valo unsigned int wdg_timeout) 1358e705c121SKalle Valo { 1359e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1360b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1361e705c121SKalle Valo int fifo = -1; 1362dcfbd67bSEmmanuel Grumbach bool scd_bug = false; 1363e705c121SKalle Valo 1364e705c121SKalle Valo if (test_and_set_bit(txq_id, trans_pcie->queue_used)) 1365e705c121SKalle Valo WARN_ONCE(1, "queue %d already used - expect issues", txq_id); 1366e705c121SKalle Valo 1367e705c121SKalle Valo txq->wd_timeout = msecs_to_jiffies(wdg_timeout); 1368e705c121SKalle Valo 1369e705c121SKalle Valo if (cfg) { 1370e705c121SKalle Valo fifo = cfg->fifo; 1371e705c121SKalle Valo 1372e705c121SKalle Valo /* Disable the scheduler prior configuring the cmd queue */ 1373e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1374e705c121SKalle Valo trans_pcie->scd_set_active) 1375e705c121SKalle Valo iwl_scd_enable_set_active(trans, 0); 1376e705c121SKalle Valo 1377e705c121SKalle Valo /* Stop this Tx queue before configuring it */ 1378e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1379e705c121SKalle Valo 1380e705c121SKalle Valo /* Set this queue as a chain-building queue unless it is CMD */ 1381e705c121SKalle Valo if (txq_id != trans_pcie->cmd_queue) 1382e705c121SKalle Valo iwl_scd_txq_set_chain(trans, txq_id); 1383e705c121SKalle Valo 1384e705c121SKalle Valo if (cfg->aggregate) { 1385e705c121SKalle Valo u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid); 1386e705c121SKalle Valo 1387e705c121SKalle Valo /* Map receiver-address / traffic-ID to this queue */ 1388e705c121SKalle Valo iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); 1389e705c121SKalle Valo 1390e705c121SKalle Valo /* enable aggregations for the queue */ 1391e705c121SKalle Valo iwl_scd_txq_enable_agg(trans, txq_id); 1392e705c121SKalle Valo txq->ampdu = true; 1393e705c121SKalle Valo } else { 1394e705c121SKalle Valo /* 1395e705c121SKalle Valo * disable aggregations for the queue, this will also 1396e705c121SKalle Valo * make the ra_tid mapping configuration irrelevant 1397e705c121SKalle Valo * since it is now a non-AGG queue. 1398e705c121SKalle Valo */ 1399e705c121SKalle Valo iwl_scd_txq_disable_agg(trans, txq_id); 1400e705c121SKalle Valo 1401bb98ecd4SSara Sharon ssn = txq->read_ptr; 1402e705c121SKalle Valo } 1403dcfbd67bSEmmanuel Grumbach } else { 1404dcfbd67bSEmmanuel Grumbach /* 1405dcfbd67bSEmmanuel Grumbach * If we need to move the SCD write pointer by steps of 1406dcfbd67bSEmmanuel Grumbach * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let 1407dcfbd67bSEmmanuel Grumbach * the op_mode know by returning true later. 1408dcfbd67bSEmmanuel Grumbach * Do this only in case cfg is NULL since this trick can 1409dcfbd67bSEmmanuel Grumbach * be done only if we have DQA enabled which is true for mvm 1410dcfbd67bSEmmanuel Grumbach * only. And mvm never sets a cfg pointer. 1411dcfbd67bSEmmanuel Grumbach * This is really ugly, but this is the easiest way out for 1412dcfbd67bSEmmanuel Grumbach * this sad hardware issue. 1413dcfbd67bSEmmanuel Grumbach * This bug has been fixed on devices 9000 and up. 1414dcfbd67bSEmmanuel Grumbach */ 1415dcfbd67bSEmmanuel Grumbach scd_bug = !trans->cfg->mq_rx_supported && 1416dcfbd67bSEmmanuel Grumbach !((ssn - txq->write_ptr) & 0x3f) && 1417dcfbd67bSEmmanuel Grumbach (ssn != txq->write_ptr); 1418dcfbd67bSEmmanuel Grumbach if (scd_bug) 1419dcfbd67bSEmmanuel Grumbach ssn++; 1420e705c121SKalle Valo } 1421e705c121SKalle Valo 1422e705c121SKalle Valo /* Place first TFD at index corresponding to start sequence number. 1423e705c121SKalle Valo * Assumes that ssn_idx is valid (!= 0xFFF) */ 1424bb98ecd4SSara Sharon txq->read_ptr = (ssn & 0xff); 1425bb98ecd4SSara Sharon txq->write_ptr = (ssn & 0xff); 1426e705c121SKalle Valo iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1427e705c121SKalle Valo (ssn & 0xff) | (txq_id << 8)); 1428e705c121SKalle Valo 1429e705c121SKalle Valo if (cfg) { 1430e705c121SKalle Valo u8 frame_limit = cfg->frame_limit; 1431e705c121SKalle Valo 1432e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); 1433e705c121SKalle Valo 1434e705c121SKalle Valo /* Set up Tx window size and frame limit for this queue */ 1435e705c121SKalle Valo iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + 1436e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); 1437e705c121SKalle Valo iwl_trans_write_mem32(trans, 1438e705c121SKalle Valo trans_pcie->scd_base_addr + 1439e705c121SKalle Valo SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 1440f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) | 1441f3779f47SJohannes Berg SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit)); 1442e705c121SKalle Valo 1443e705c121SKalle Valo /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */ 1444e705c121SKalle Valo iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), 1445e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1446e705c121SKalle Valo (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) | 1447e705c121SKalle Valo (1 << SCD_QUEUE_STTS_REG_POS_WSL) | 1448e705c121SKalle Valo SCD_QUEUE_STTS_REG_MSK); 1449e705c121SKalle Valo 1450e705c121SKalle Valo /* enable the scheduler for this queue (only) */ 1451e705c121SKalle Valo if (txq_id == trans_pcie->cmd_queue && 1452e705c121SKalle Valo trans_pcie->scd_set_active) 1453e705c121SKalle Valo iwl_scd_enable_set_active(trans, BIT(txq_id)); 1454e705c121SKalle Valo 1455e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1456e705c121SKalle Valo "Activate queue %d on FIFO %d WrPtr: %d\n", 1457e705c121SKalle Valo txq_id, fifo, ssn & 0xff); 1458e705c121SKalle Valo } else { 1459e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, 1460e705c121SKalle Valo "Activate queue %d WrPtr: %d\n", 1461e705c121SKalle Valo txq_id, ssn & 0xff); 1462e705c121SKalle Valo } 1463dcfbd67bSEmmanuel Grumbach 1464dcfbd67bSEmmanuel Grumbach return scd_bug; 1465e705c121SKalle Valo } 1466e705c121SKalle Valo 146742db09c1SLiad Kaufman void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 146842db09c1SLiad Kaufman bool shared_mode) 146942db09c1SLiad Kaufman { 147042db09c1SLiad Kaufman struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1471b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[txq_id]; 147242db09c1SLiad Kaufman 147342db09c1SLiad Kaufman txq->ampdu = !shared_mode; 147442db09c1SLiad Kaufman } 147542db09c1SLiad Kaufman 1476e705c121SKalle Valo void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id, 1477e705c121SKalle Valo bool configure_scd) 1478e705c121SKalle Valo { 1479e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1480e705c121SKalle Valo u32 stts_addr = trans_pcie->scd_base_addr + 1481e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq_id); 1482e705c121SKalle Valo static const u32 zero_val[4] = {}; 1483e705c121SKalle Valo 1484b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0; 1485b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->frozen = false; 1486e705c121SKalle Valo 1487e705c121SKalle Valo /* 1488e705c121SKalle Valo * Upon HW Rfkill - we stop the device, and then stop the queues 1489e705c121SKalle Valo * in the op_mode. Just for the sake of the simplicity of the op_mode, 1490e705c121SKalle Valo * allow the op_mode to call txq_disable after it already called 1491e705c121SKalle Valo * stop_device. 1492e705c121SKalle Valo */ 1493e705c121SKalle Valo if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { 1494e705c121SKalle Valo WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1495e705c121SKalle Valo "queue %d not used", txq_id); 1496e705c121SKalle Valo return; 1497e705c121SKalle Valo } 1498e705c121SKalle Valo 1499e705c121SKalle Valo if (configure_scd) { 1500e705c121SKalle Valo iwl_scd_txq_set_inactive(trans, txq_id); 1501e705c121SKalle Valo 1502e705c121SKalle Valo iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, 1503e705c121SKalle Valo ARRAY_SIZE(zero_val)); 1504e705c121SKalle Valo } 1505e705c121SKalle Valo 1506e705c121SKalle Valo iwl_pcie_txq_unmap(trans, txq_id); 1507b2a3b1c1SSara Sharon trans_pcie->txq[txq_id]->ampdu = false; 1508e705c121SKalle Valo 1509e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); 1510e705c121SKalle Valo } 1511e705c121SKalle Valo 1512e705c121SKalle Valo /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 1513e705c121SKalle Valo 1514e705c121SKalle Valo /* 1515e705c121SKalle Valo * iwl_pcie_enqueue_hcmd - enqueue a uCode command 1516e705c121SKalle Valo * @priv: device private data point 1517e705c121SKalle Valo * @cmd: a pointer to the ucode command structure 1518e705c121SKalle Valo * 1519e705c121SKalle Valo * The function returns < 0 values to indicate the operation 1520e705c121SKalle Valo * failed. On success, it returns the index (>= 0) of command in the 1521e705c121SKalle Valo * command queue. 1522e705c121SKalle Valo */ 1523e705c121SKalle Valo static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1524e705c121SKalle Valo struct iwl_host_cmd *cmd) 1525e705c121SKalle Valo { 1526e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1527b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1528e705c121SKalle Valo struct iwl_device_cmd *out_cmd; 1529e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 1530e705c121SKalle Valo unsigned long flags; 1531e705c121SKalle Valo void *dup_buf = NULL; 1532e705c121SKalle Valo dma_addr_t phys_addr; 1533e705c121SKalle Valo int idx; 15348de437c7SSara Sharon u16 copy_size, cmd_size, tb0_size; 1535e705c121SKalle Valo bool had_nocopy = false; 1536e705c121SKalle Valo u8 group_id = iwl_cmd_groupid(cmd->id); 1537e705c121SKalle Valo int i, ret; 1538e705c121SKalle Valo u32 cmd_pos; 1539e705c121SKalle Valo const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 1540e705c121SKalle Valo u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 1541e705c121SKalle Valo 15425b88792cSSara Sharon if (WARN(!trans->wide_cmd_header && 1543e705c121SKalle Valo group_id > IWL_ALWAYS_LONG_GROUP, 1544e705c121SKalle Valo "unsupported wide command %#x\n", cmd->id)) 1545e705c121SKalle Valo return -EINVAL; 1546e705c121SKalle Valo 1547e705c121SKalle Valo if (group_id != 0) { 1548e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1549e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header_wide); 1550e705c121SKalle Valo } else { 1551e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1552e705c121SKalle Valo cmd_size = sizeof(struct iwl_cmd_header); 1553e705c121SKalle Valo } 1554e705c121SKalle Valo 1555e705c121SKalle Valo /* need one for the header if the first is NOCOPY */ 1556e705c121SKalle Valo BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); 1557e705c121SKalle Valo 1558e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1559e705c121SKalle Valo cmddata[i] = cmd->data[i]; 1560e705c121SKalle Valo cmdlen[i] = cmd->len[i]; 1561e705c121SKalle Valo 1562e705c121SKalle Valo if (!cmd->len[i]) 1563e705c121SKalle Valo continue; 1564e705c121SKalle Valo 15658de437c7SSara Sharon /* need at least IWL_FIRST_TB_SIZE copied */ 15668de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 15678de437c7SSara Sharon int copy = IWL_FIRST_TB_SIZE - copy_size; 1568e705c121SKalle Valo 1569e705c121SKalle Valo if (copy > cmdlen[i]) 1570e705c121SKalle Valo copy = cmdlen[i]; 1571e705c121SKalle Valo cmdlen[i] -= copy; 1572e705c121SKalle Valo cmddata[i] += copy; 1573e705c121SKalle Valo copy_size += copy; 1574e705c121SKalle Valo } 1575e705c121SKalle Valo 1576e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 1577e705c121SKalle Valo had_nocopy = true; 1578e705c121SKalle Valo if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 1579e705c121SKalle Valo idx = -EINVAL; 1580e705c121SKalle Valo goto free_dup_buf; 1581e705c121SKalle Valo } 1582e705c121SKalle Valo } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 1583e705c121SKalle Valo /* 1584e705c121SKalle Valo * This is also a chunk that isn't copied 1585e705c121SKalle Valo * to the static buffer so set had_nocopy. 1586e705c121SKalle Valo */ 1587e705c121SKalle Valo had_nocopy = true; 1588e705c121SKalle Valo 1589e705c121SKalle Valo /* only allowed once */ 1590e705c121SKalle Valo if (WARN_ON(dup_buf)) { 1591e705c121SKalle Valo idx = -EINVAL; 1592e705c121SKalle Valo goto free_dup_buf; 1593e705c121SKalle Valo } 1594e705c121SKalle Valo 1595e705c121SKalle Valo dup_buf = kmemdup(cmddata[i], cmdlen[i], 1596e705c121SKalle Valo GFP_ATOMIC); 1597e705c121SKalle Valo if (!dup_buf) 1598e705c121SKalle Valo return -ENOMEM; 1599e705c121SKalle Valo } else { 1600e705c121SKalle Valo /* NOCOPY must not be followed by normal! */ 1601e705c121SKalle Valo if (WARN_ON(had_nocopy)) { 1602e705c121SKalle Valo idx = -EINVAL; 1603e705c121SKalle Valo goto free_dup_buf; 1604e705c121SKalle Valo } 1605e705c121SKalle Valo copy_size += cmdlen[i]; 1606e705c121SKalle Valo } 1607e705c121SKalle Valo cmd_size += cmd->len[i]; 1608e705c121SKalle Valo } 1609e705c121SKalle Valo 1610e705c121SKalle Valo /* 1611e705c121SKalle Valo * If any of the command structures end up being larger than 1612e705c121SKalle Valo * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically 1613e705c121SKalle Valo * allocated into separate TFDs, then we will need to 1614e705c121SKalle Valo * increase the size of the buffers. 1615e705c121SKalle Valo */ 1616e705c121SKalle Valo if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 1617e705c121SKalle Valo "Command %s (%#x) is too large (%d bytes)\n", 161839bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 161939bdb17eSSharon Dvir cmd->id, copy_size)) { 1620e705c121SKalle Valo idx = -EINVAL; 1621e705c121SKalle Valo goto free_dup_buf; 1622e705c121SKalle Valo } 1623e705c121SKalle Valo 1624e705c121SKalle Valo spin_lock_bh(&txq->lock); 1625e705c121SKalle Valo 16267b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 1627e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1628e705c121SKalle Valo 1629e705c121SKalle Valo IWL_ERR(trans, "No space in command queue\n"); 1630e705c121SKalle Valo iwl_op_mode_cmd_queue_full(trans->op_mode); 1631e705c121SKalle Valo idx = -ENOSPC; 1632e705c121SKalle Valo goto free_dup_buf; 1633e705c121SKalle Valo } 1634e705c121SKalle Valo 16354ecab561SEmmanuel Grumbach idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 1636e705c121SKalle Valo out_cmd = txq->entries[idx].cmd; 1637e705c121SKalle Valo out_meta = &txq->entries[idx].meta; 1638e705c121SKalle Valo 1639e705c121SKalle Valo memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ 1640e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) 1641e705c121SKalle Valo out_meta->source = cmd; 1642e705c121SKalle Valo 1643e705c121SKalle Valo /* set up the header */ 1644e705c121SKalle Valo if (group_id != 0) { 1645e705c121SKalle Valo out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 1646e705c121SKalle Valo out_cmd->hdr_wide.group_id = group_id; 1647e705c121SKalle Valo out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 1648e705c121SKalle Valo out_cmd->hdr_wide.length = 1649e705c121SKalle Valo cpu_to_le16(cmd_size - 1650e705c121SKalle Valo sizeof(struct iwl_cmd_header_wide)); 1651e705c121SKalle Valo out_cmd->hdr_wide.reserved = 0; 1652e705c121SKalle Valo out_cmd->hdr_wide.sequence = 1653e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1654bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1655e705c121SKalle Valo 1656e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header_wide); 1657e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header_wide); 1658e705c121SKalle Valo } else { 1659e705c121SKalle Valo out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id); 1660e705c121SKalle Valo out_cmd->hdr.sequence = 1661e705c121SKalle Valo cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 1662bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr)); 1663e705c121SKalle Valo out_cmd->hdr.group_id = 0; 1664e705c121SKalle Valo 1665e705c121SKalle Valo cmd_pos = sizeof(struct iwl_cmd_header); 1666e705c121SKalle Valo copy_size = sizeof(struct iwl_cmd_header); 1667e705c121SKalle Valo } 1668e705c121SKalle Valo 1669e705c121SKalle Valo /* and copy the data that needs to be copied */ 1670e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1671e705c121SKalle Valo int copy; 1672e705c121SKalle Valo 1673e705c121SKalle Valo if (!cmd->len[i]) 1674e705c121SKalle Valo continue; 1675e705c121SKalle Valo 1676e705c121SKalle Valo /* copy everything if not nocopy/dup */ 1677e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1678e705c121SKalle Valo IWL_HCMD_DFL_DUP))) { 1679e705c121SKalle Valo copy = cmd->len[i]; 1680e705c121SKalle Valo 1681e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1682e705c121SKalle Valo cmd_pos += copy; 1683e705c121SKalle Valo copy_size += copy; 1684e705c121SKalle Valo continue; 1685e705c121SKalle Valo } 1686e705c121SKalle Valo 1687e705c121SKalle Valo /* 16888de437c7SSara Sharon * Otherwise we need at least IWL_FIRST_TB_SIZE copied 16898de437c7SSara Sharon * in total (for bi-directional DMA), but copy up to what 1690e705c121SKalle Valo * we can fit into the payload for debug dump purposes. 1691e705c121SKalle Valo */ 1692e705c121SKalle Valo copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 1693e705c121SKalle Valo 1694e705c121SKalle Valo memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 1695e705c121SKalle Valo cmd_pos += copy; 1696e705c121SKalle Valo 1697e705c121SKalle Valo /* However, treat copy_size the proper way, we need it below */ 16988de437c7SSara Sharon if (copy_size < IWL_FIRST_TB_SIZE) { 16998de437c7SSara Sharon copy = IWL_FIRST_TB_SIZE - copy_size; 1700e705c121SKalle Valo 1701e705c121SKalle Valo if (copy > cmd->len[i]) 1702e705c121SKalle Valo copy = cmd->len[i]; 1703e705c121SKalle Valo copy_size += copy; 1704e705c121SKalle Valo } 1705e705c121SKalle Valo } 1706e705c121SKalle Valo 1707e705c121SKalle Valo IWL_DEBUG_HC(trans, 1708e705c121SKalle Valo "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 170939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1710e705c121SKalle Valo group_id, out_cmd->hdr.cmd, 1711e705c121SKalle Valo le16_to_cpu(out_cmd->hdr.sequence), 1712bb98ecd4SSara Sharon cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 1713e705c121SKalle Valo 17148de437c7SSara Sharon /* start the TFD with the minimum copy bytes */ 17158de437c7SSara Sharon tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 17168de437c7SSara Sharon memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 1717e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, 17188de437c7SSara Sharon iwl_pcie_get_first_tb_dma(txq, idx), 17198de437c7SSara Sharon tb0_size, true); 1720e705c121SKalle Valo 1721e705c121SKalle Valo /* map first command fragment, if any remains */ 17228de437c7SSara Sharon if (copy_size > tb0_size) { 1723e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, 17248de437c7SSara Sharon ((u8 *)&out_cmd->hdr) + tb0_size, 17258de437c7SSara Sharon copy_size - tb0_size, 1726e705c121SKalle Valo DMA_TO_DEVICE); 1727e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1728bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1729bb98ecd4SSara Sharon txq->write_ptr); 1730e705c121SKalle Valo idx = -ENOMEM; 1731e705c121SKalle Valo goto out; 1732e705c121SKalle Valo } 1733e705c121SKalle Valo 1734e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, 17358de437c7SSara Sharon copy_size - tb0_size, false); 1736e705c121SKalle Valo } 1737e705c121SKalle Valo 1738e705c121SKalle Valo /* map the remaining (adjusted) nocopy/dup fragments */ 1739e705c121SKalle Valo for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 1740e705c121SKalle Valo const void *data = cmddata[i]; 1741e705c121SKalle Valo 1742e705c121SKalle Valo if (!cmdlen[i]) 1743e705c121SKalle Valo continue; 1744e705c121SKalle Valo if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 1745e705c121SKalle Valo IWL_HCMD_DFL_DUP))) 1746e705c121SKalle Valo continue; 1747e705c121SKalle Valo if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 1748e705c121SKalle Valo data = dup_buf; 1749e705c121SKalle Valo phys_addr = dma_map_single(trans->dev, (void *)data, 1750e705c121SKalle Valo cmdlen[i], DMA_TO_DEVICE); 1751e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys_addr)) { 1752bb98ecd4SSara Sharon iwl_pcie_tfd_unmap(trans, out_meta, txq, 1753bb98ecd4SSara Sharon txq->write_ptr); 1754e705c121SKalle Valo idx = -ENOMEM; 1755e705c121SKalle Valo goto out; 1756e705c121SKalle Valo } 1757e705c121SKalle Valo 1758e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false); 1759e705c121SKalle Valo } 1760e705c121SKalle Valo 17613cd1980bSSara Sharon BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 1762e705c121SKalle Valo out_meta->flags = cmd->flags; 1763e705c121SKalle Valo if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 1764e705c121SKalle Valo kzfree(txq->entries[idx].free_buf); 1765e705c121SKalle Valo txq->entries[idx].free_buf = dup_buf; 1766e705c121SKalle Valo 1767e705c121SKalle Valo trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 1768e705c121SKalle Valo 1769e705c121SKalle Valo /* start timer if queue currently empty */ 1770bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 1771e705c121SKalle Valo mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 1772e705c121SKalle Valo 1773e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1774e705c121SKalle Valo ret = iwl_pcie_set_cmd_in_flight(trans, cmd); 1775e705c121SKalle Valo if (ret < 0) { 1776e705c121SKalle Valo idx = ret; 1777e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1778e705c121SKalle Valo goto out; 1779e705c121SKalle Valo } 1780e705c121SKalle Valo 1781e705c121SKalle Valo /* Increment and update queue's write index */ 17827b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 1783e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 1784e705c121SKalle Valo 1785e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1786e705c121SKalle Valo 1787e705c121SKalle Valo out: 1788e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1789e705c121SKalle Valo free_dup_buf: 1790e705c121SKalle Valo if (idx < 0) 1791e705c121SKalle Valo kfree(dup_buf); 1792e705c121SKalle Valo return idx; 1793e705c121SKalle Valo } 1794e705c121SKalle Valo 1795e705c121SKalle Valo /* 1796e705c121SKalle Valo * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them 1797e705c121SKalle Valo * @rxb: Rx buffer to reclaim 1798e705c121SKalle Valo */ 1799e705c121SKalle Valo void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 1800e705c121SKalle Valo struct iwl_rx_cmd_buffer *rxb) 1801e705c121SKalle Valo { 1802e705c121SKalle Valo struct iwl_rx_packet *pkt = rxb_addr(rxb); 1803e705c121SKalle Valo u16 sequence = le16_to_cpu(pkt->hdr.sequence); 1804d490e097SJohannes Berg u8 group_id; 180539bdb17eSSharon Dvir u32 cmd_id; 1806e705c121SKalle Valo int txq_id = SEQ_TO_QUEUE(sequence); 1807e705c121SKalle Valo int index = SEQ_TO_INDEX(sequence); 1808e705c121SKalle Valo int cmd_index; 1809e705c121SKalle Valo struct iwl_device_cmd *cmd; 1810e705c121SKalle Valo struct iwl_cmd_meta *meta; 1811e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1812b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1813e705c121SKalle Valo 1814e705c121SKalle Valo /* If a Tx command is being handled and it isn't in the actual 1815e705c121SKalle Valo * command queue then there a command routing bug has been introduced 1816e705c121SKalle Valo * in the queue management code. */ 1817e705c121SKalle Valo if (WARN(txq_id != trans_pcie->cmd_queue, 1818e705c121SKalle Valo "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", 1819b2a3b1c1SSara Sharon txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr, 1820b2a3b1c1SSara Sharon txq->write_ptr)) { 1821e705c121SKalle Valo iwl_print_hex_error(trans, pkt, 32); 1822e705c121SKalle Valo return; 1823e705c121SKalle Valo } 1824e705c121SKalle Valo 1825e705c121SKalle Valo spin_lock_bh(&txq->lock); 1826e705c121SKalle Valo 18274ecab561SEmmanuel Grumbach cmd_index = iwl_pcie_get_cmd_index(txq, index); 1828e705c121SKalle Valo cmd = txq->entries[cmd_index].cmd; 1829e705c121SKalle Valo meta = &txq->entries[cmd_index].meta; 1830d490e097SJohannes Berg group_id = cmd->hdr.group_id; 183139bdb17eSSharon Dvir cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0); 1832e705c121SKalle Valo 18336983ba69SSara Sharon iwl_pcie_tfd_unmap(trans, meta, txq, index); 1834e705c121SKalle Valo 1835e705c121SKalle Valo /* Input error checking is done when commands are added to queue. */ 1836e705c121SKalle Valo if (meta->flags & CMD_WANT_SKB) { 1837e705c121SKalle Valo struct page *p = rxb_steal_page(rxb); 1838e705c121SKalle Valo 1839e705c121SKalle Valo meta->source->resp_pkt = pkt; 1840e705c121SKalle Valo meta->source->_rx_page_addr = (unsigned long)page_address(p); 1841e705c121SKalle Valo meta->source->_rx_page_order = trans_pcie->rx_page_order; 1842e705c121SKalle Valo } 1843e705c121SKalle Valo 1844dcbb4746SEmmanuel Grumbach if (meta->flags & CMD_WANT_ASYNC_CALLBACK) 1845dcbb4746SEmmanuel Grumbach iwl_op_mode_async_cb(trans->op_mode, cmd); 1846dcbb4746SEmmanuel Grumbach 1847e705c121SKalle Valo iwl_pcie_cmdq_reclaim(trans, txq_id, index); 1848e705c121SKalle Valo 1849e705c121SKalle Valo if (!(meta->flags & CMD_ASYNC)) { 1850e705c121SKalle Valo if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) { 1851e705c121SKalle Valo IWL_WARN(trans, 1852e705c121SKalle Valo "HCMD_ACTIVE already clear for command %s\n", 185339bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1854e705c121SKalle Valo } 1855e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1856e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 185739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd_id)); 1858e705c121SKalle Valo wake_up(&trans_pcie->wait_command_queue); 1859e705c121SKalle Valo } 1860e705c121SKalle Valo 18614cbb8e50SLuciano Coelho if (meta->flags & CMD_MAKE_TRANS_IDLE) { 18624cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n", 18634cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18644cbb8e50SLuciano Coelho set_bit(STATUS_TRANS_IDLE, &trans->status); 18654cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18664cbb8e50SLuciano Coelho } 18674cbb8e50SLuciano Coelho 18684cbb8e50SLuciano Coelho if (meta->flags & CMD_WAKE_UP_TRANS) { 18694cbb8e50SLuciano Coelho IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n", 18704cbb8e50SLuciano Coelho iwl_get_cmd_string(trans, cmd->hdr.cmd)); 18714cbb8e50SLuciano Coelho clear_bit(STATUS_TRANS_IDLE, &trans->status); 18724cbb8e50SLuciano Coelho wake_up(&trans_pcie->d0i3_waitq); 18734cbb8e50SLuciano Coelho } 18744cbb8e50SLuciano Coelho 1875e705c121SKalle Valo meta->flags = 0; 1876e705c121SKalle Valo 1877e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1878e705c121SKalle Valo } 1879e705c121SKalle Valo 1880e705c121SKalle Valo #define HOST_COMPLETE_TIMEOUT (2 * HZ) 1881e705c121SKalle Valo 1882e705c121SKalle Valo static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, 1883e705c121SKalle Valo struct iwl_host_cmd *cmd) 1884e705c121SKalle Valo { 1885e705c121SKalle Valo int ret; 1886e705c121SKalle Valo 1887e705c121SKalle Valo /* An asynchronous command can not expect an SKB to be set. */ 1888e705c121SKalle Valo if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1889e705c121SKalle Valo return -EINVAL; 1890e705c121SKalle Valo 1891e705c121SKalle Valo ret = iwl_pcie_enqueue_hcmd(trans, cmd); 1892e705c121SKalle Valo if (ret < 0) { 1893e705c121SKalle Valo IWL_ERR(trans, 1894e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 189539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1896e705c121SKalle Valo return ret; 1897e705c121SKalle Valo } 1898e705c121SKalle Valo return 0; 1899e705c121SKalle Valo } 1900e705c121SKalle Valo 1901e705c121SKalle Valo static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, 1902e705c121SKalle Valo struct iwl_host_cmd *cmd) 1903e705c121SKalle Valo { 1904e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1905b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 1906e705c121SKalle Valo int cmd_idx; 1907e705c121SKalle Valo int ret; 1908e705c121SKalle Valo 1909e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", 191039bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1911e705c121SKalle Valo 1912e705c121SKalle Valo if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 1913e705c121SKalle Valo &trans->status), 1914e705c121SKalle Valo "Command %s: a command is already active!\n", 191539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id))) 1916e705c121SKalle Valo return -EIO; 1917e705c121SKalle Valo 1918e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", 191939bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1920e705c121SKalle Valo 192171b1230cSLuca Coelho if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 192271b1230cSLuca Coelho ret = wait_event_timeout(trans_pcie->d0i3_waitq, 192371b1230cSLuca Coelho pm_runtime_active(&trans_pcie->pci_dev->dev), 192471b1230cSLuca Coelho msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 192571b1230cSLuca Coelho if (!ret) { 192671b1230cSLuca Coelho IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 192771b1230cSLuca Coelho return -ETIMEDOUT; 192871b1230cSLuca Coelho } 192971b1230cSLuca Coelho } 193071b1230cSLuca Coelho 1931e705c121SKalle Valo cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); 1932e705c121SKalle Valo if (cmd_idx < 0) { 1933e705c121SKalle Valo ret = cmd_idx; 1934e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1935e705c121SKalle Valo IWL_ERR(trans, 1936e705c121SKalle Valo "Error sending %s: enqueue_hcmd failed: %d\n", 193739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), ret); 1938e705c121SKalle Valo return ret; 1939e705c121SKalle Valo } 1940e705c121SKalle Valo 1941e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->wait_command_queue, 1942e705c121SKalle Valo !test_bit(STATUS_SYNC_HCMD_ACTIVE, 1943e705c121SKalle Valo &trans->status), 1944e705c121SKalle Valo HOST_COMPLETE_TIMEOUT); 1945e705c121SKalle Valo if (!ret) { 1946e705c121SKalle Valo IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 194739bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id), 1948e705c121SKalle Valo jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 1949e705c121SKalle Valo 1950e705c121SKalle Valo IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 1951bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 1952e705c121SKalle Valo 1953e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1954e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 195539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1956e705c121SKalle Valo ret = -ETIMEDOUT; 1957e705c121SKalle Valo 1958d1967ce6SShahar S Matityahu iwl_trans_pcie_sync_nmi(trans); 1959e705c121SKalle Valo goto cancel; 1960e705c121SKalle Valo } 1961e705c121SKalle Valo 1962e705c121SKalle Valo if (test_bit(STATUS_FW_ERROR, &trans->status)) { 19634290eaadSJohannes Berg iwl_trans_pcie_dump_regs(trans); 1964e705c121SKalle Valo IWL_ERR(trans, "FW error in SYNC CMD %s\n", 196539bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1966e705c121SKalle Valo dump_stack(); 1967e705c121SKalle Valo ret = -EIO; 1968e705c121SKalle Valo goto cancel; 1969e705c121SKalle Valo } 1970e705c121SKalle Valo 1971e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1972326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1973e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 1974e705c121SKalle Valo ret = -ERFKILL; 1975e705c121SKalle Valo goto cancel; 1976e705c121SKalle Valo } 1977e705c121SKalle Valo 1978e705c121SKalle Valo if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 1979e705c121SKalle Valo IWL_ERR(trans, "Error: Response NULL in '%s'\n", 198039bdb17eSSharon Dvir iwl_get_cmd_string(trans, cmd->id)); 1981e705c121SKalle Valo ret = -EIO; 1982e705c121SKalle Valo goto cancel; 1983e705c121SKalle Valo } 1984e705c121SKalle Valo 1985e705c121SKalle Valo return 0; 1986e705c121SKalle Valo 1987e705c121SKalle Valo cancel: 1988e705c121SKalle Valo if (cmd->flags & CMD_WANT_SKB) { 1989e705c121SKalle Valo /* 1990e705c121SKalle Valo * Cancel the CMD_WANT_SKB flag for the cmd in the 1991e705c121SKalle Valo * TX cmd queue. Otherwise in case the cmd comes 1992e705c121SKalle Valo * in later, it will possibly set an invalid 1993e705c121SKalle Valo * address (cmd->meta.source). 1994e705c121SKalle Valo */ 1995b2a3b1c1SSara Sharon txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 1996e705c121SKalle Valo } 1997e705c121SKalle Valo 1998e705c121SKalle Valo if (cmd->resp_pkt) { 1999e705c121SKalle Valo iwl_free_resp(cmd); 2000e705c121SKalle Valo cmd->resp_pkt = NULL; 2001e705c121SKalle Valo } 2002e705c121SKalle Valo 2003e705c121SKalle Valo return ret; 2004e705c121SKalle Valo } 2005e705c121SKalle Valo 2006e705c121SKalle Valo int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) 2007e705c121SKalle Valo { 20082b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2009f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2010f60c9e59SEmmanuel Grumbach return -ENODEV; 20112b3fae66SMatt Chen 2012e705c121SKalle Valo if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 2013326477e4SJohannes Berg test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 2014e705c121SKalle Valo IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 2015e705c121SKalle Valo cmd->id); 2016e705c121SKalle Valo return -ERFKILL; 2017e705c121SKalle Valo } 2018e705c121SKalle Valo 2019e705c121SKalle Valo if (cmd->flags & CMD_ASYNC) 2020e705c121SKalle Valo return iwl_pcie_send_hcmd_async(trans, cmd); 2021e705c121SKalle Valo 2022e705c121SKalle Valo /* We still can fail on RFKILL that can be asserted while we wait */ 2023e705c121SKalle Valo return iwl_pcie_send_hcmd_sync(trans, cmd); 2024e705c121SKalle Valo } 2025e705c121SKalle Valo 20263a0b2a42SEmmanuel Grumbach static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb, 20273a0b2a42SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 2028bb03927eSJohannes Berg struct iwl_cmd_meta *out_meta) 20293a0b2a42SEmmanuel Grumbach { 2030bb03927eSJohannes Berg u16 head_tb_len; 20313a0b2a42SEmmanuel Grumbach int i; 20323a0b2a42SEmmanuel Grumbach 20333a0b2a42SEmmanuel Grumbach /* 20343a0b2a42SEmmanuel Grumbach * Set up TFD's third entry to point directly to remainder 20353a0b2a42SEmmanuel Grumbach * of skb's head, if any 20363a0b2a42SEmmanuel Grumbach */ 2037bb03927eSJohannes Berg head_tb_len = skb_headlen(skb) - hdr_len; 20383a0b2a42SEmmanuel Grumbach 2039bb03927eSJohannes Berg if (head_tb_len > 0) { 2040bb03927eSJohannes Berg dma_addr_t tb_phys = dma_map_single(trans->dev, 20413a0b2a42SEmmanuel Grumbach skb->data + hdr_len, 2042bb03927eSJohannes Berg head_tb_len, DMA_TO_DEVICE); 2043bb03927eSJohannes Berg if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 20443a0b2a42SEmmanuel Grumbach return -EINVAL; 2045bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, 2046bf77ee2eSSara Sharon skb->data + hdr_len, 2047bf77ee2eSSara Sharon head_tb_len); 2048bb03927eSJohannes Berg iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false); 20493a0b2a42SEmmanuel Grumbach } 20503a0b2a42SEmmanuel Grumbach 20513a0b2a42SEmmanuel Grumbach /* set up the remaining entries to point to the data */ 20523a0b2a42SEmmanuel Grumbach for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 20533a0b2a42SEmmanuel Grumbach const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 20543a0b2a42SEmmanuel Grumbach dma_addr_t tb_phys; 20553a0b2a42SEmmanuel Grumbach int tb_idx; 20563a0b2a42SEmmanuel Grumbach 20573a0b2a42SEmmanuel Grumbach if (!skb_frag_size(frag)) 20583a0b2a42SEmmanuel Grumbach continue; 20593a0b2a42SEmmanuel Grumbach 20603a0b2a42SEmmanuel Grumbach tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 20613a0b2a42SEmmanuel Grumbach skb_frag_size(frag), DMA_TO_DEVICE); 20623a0b2a42SEmmanuel Grumbach 20637d50d76eSJohannes Berg if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 20643a0b2a42SEmmanuel Grumbach return -EINVAL; 2065bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, 2066bf77ee2eSSara Sharon skb_frag_address(frag), 2067bf77ee2eSSara Sharon skb_frag_size(frag)); 20683a0b2a42SEmmanuel Grumbach tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 20693a0b2a42SEmmanuel Grumbach skb_frag_size(frag), false); 20706e00a237SJohannes Berg if (tb_idx < 0) 20716e00a237SJohannes Berg return tb_idx; 20723a0b2a42SEmmanuel Grumbach 20733cd1980bSSara Sharon out_meta->tbs |= BIT(tb_idx); 20743a0b2a42SEmmanuel Grumbach } 20753a0b2a42SEmmanuel Grumbach 20763a0b2a42SEmmanuel Grumbach return 0; 20773a0b2a42SEmmanuel Grumbach } 20783a0b2a42SEmmanuel Grumbach 20796eb5e529SEmmanuel Grumbach #ifdef CONFIG_INET 20806ffe5de3SSara Sharon struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len) 20816eb5e529SEmmanuel Grumbach { 20826eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20836eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page); 20846eb5e529SEmmanuel Grumbach 20856eb5e529SEmmanuel Grumbach if (!p->page) 20866eb5e529SEmmanuel Grumbach goto alloc; 20876eb5e529SEmmanuel Grumbach 20886eb5e529SEmmanuel Grumbach /* enough room on this page */ 20896eb5e529SEmmanuel Grumbach if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE) 20906eb5e529SEmmanuel Grumbach return p; 20916eb5e529SEmmanuel Grumbach 20926eb5e529SEmmanuel Grumbach /* We don't have enough room on this page, get a new one. */ 20936eb5e529SEmmanuel Grumbach __free_page(p->page); 20946eb5e529SEmmanuel Grumbach 20956eb5e529SEmmanuel Grumbach alloc: 20966eb5e529SEmmanuel Grumbach p->page = alloc_page(GFP_ATOMIC); 20976eb5e529SEmmanuel Grumbach if (!p->page) 20986eb5e529SEmmanuel Grumbach return NULL; 20996eb5e529SEmmanuel Grumbach p->pos = page_address(p->page); 21006eb5e529SEmmanuel Grumbach return p; 21016eb5e529SEmmanuel Grumbach } 21026eb5e529SEmmanuel Grumbach 21036eb5e529SEmmanuel Grumbach static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph, 21046eb5e529SEmmanuel Grumbach bool ipv6, unsigned int len) 21056eb5e529SEmmanuel Grumbach { 21066eb5e529SEmmanuel Grumbach if (ipv6) { 21076eb5e529SEmmanuel Grumbach struct ipv6hdr *iphv6 = iph; 21086eb5e529SEmmanuel Grumbach 21096eb5e529SEmmanuel Grumbach tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr, 21106eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 21116eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 21126eb5e529SEmmanuel Grumbach } else { 21136eb5e529SEmmanuel Grumbach struct iphdr *iphv4 = iph; 21146eb5e529SEmmanuel Grumbach 21156eb5e529SEmmanuel Grumbach ip_send_check(iphv4); 21166eb5e529SEmmanuel Grumbach tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr, 21176eb5e529SEmmanuel Grumbach len + tcph->doff * 4, 21186eb5e529SEmmanuel Grumbach IPPROTO_TCP, 0); 21196eb5e529SEmmanuel Grumbach } 21206eb5e529SEmmanuel Grumbach } 21216eb5e529SEmmanuel Grumbach 2122066fd29aSSara Sharon static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 21236eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 21246eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 21256eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 21266eb5e529SEmmanuel Grumbach { 212705e5a7e5SJohannes Berg struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 21286eb5e529SEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; 21296eb5e529SEmmanuel Grumbach struct ieee80211_hdr *hdr = (void *)skb->data; 21306eb5e529SEmmanuel Grumbach unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 21316eb5e529SEmmanuel Grumbach unsigned int mss = skb_shinfo(skb)->gso_size; 21326eb5e529SEmmanuel Grumbach u16 length, iv_len, amsdu_pad; 21336eb5e529SEmmanuel Grumbach u8 *start_hdr; 21346eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *hdr_page; 213521cb3222SJohannes Berg struct page **page_ptr; 21366eb5e529SEmmanuel Grumbach struct tso_t tso; 21376eb5e529SEmmanuel Grumbach 21386eb5e529SEmmanuel Grumbach /* if the packet is protected, then it must be CCMP or GCMP */ 21396eb5e529SEmmanuel Grumbach BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN); 21406eb5e529SEmmanuel Grumbach iv_len = ieee80211_has_protected(hdr->frame_control) ? 21416eb5e529SEmmanuel Grumbach IEEE80211_CCMP_HDR_LEN : 0; 21426eb5e529SEmmanuel Grumbach 21436eb5e529SEmmanuel Grumbach trace_iwlwifi_dev_tx(trans->dev, skb, 2144943309d4SEmmanuel Grumbach iwl_pcie_get_tfd(trans, txq, txq->write_ptr), 21456983ba69SSara Sharon trans_pcie->tfd_size, 21468790fce4SJohannes Berg &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0); 21476eb5e529SEmmanuel Grumbach 21486eb5e529SEmmanuel Grumbach ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 21496eb5e529SEmmanuel Grumbach snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 21506eb5e529SEmmanuel Grumbach total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 21516eb5e529SEmmanuel Grumbach amsdu_pad = 0; 21526eb5e529SEmmanuel Grumbach 21536eb5e529SEmmanuel Grumbach /* total amount of header we may need for this A-MSDU */ 21546eb5e529SEmmanuel Grumbach hdr_room = DIV_ROUND_UP(total_len, mss) * 21556eb5e529SEmmanuel Grumbach (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 21566eb5e529SEmmanuel Grumbach 21576eb5e529SEmmanuel Grumbach /* Our device supports 9 segments at most, it will fit in 1 page */ 21586eb5e529SEmmanuel Grumbach hdr_page = get_page_hdr(trans, hdr_room); 21596eb5e529SEmmanuel Grumbach if (!hdr_page) 21606eb5e529SEmmanuel Grumbach return -ENOMEM; 21616eb5e529SEmmanuel Grumbach 21626eb5e529SEmmanuel Grumbach get_page(hdr_page->page); 21636eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 216421cb3222SJohannes Berg page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 216521cb3222SJohannes Berg *page_ptr = hdr_page->page; 21666eb5e529SEmmanuel Grumbach memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 21676eb5e529SEmmanuel Grumbach hdr_page->pos += iv_len; 21686eb5e529SEmmanuel Grumbach 21696eb5e529SEmmanuel Grumbach /* 21706eb5e529SEmmanuel Grumbach * Pull the ieee80211 header + IV to be able to use TSO core, 21716eb5e529SEmmanuel Grumbach * we will restore it for the tx_status flow. 21726eb5e529SEmmanuel Grumbach */ 21736eb5e529SEmmanuel Grumbach skb_pull(skb, hdr_len + iv_len); 21746eb5e529SEmmanuel Grumbach 217505e5a7e5SJohannes Berg /* 217605e5a7e5SJohannes Berg * Remove the length of all the headers that we don't actually 217705e5a7e5SJohannes Berg * have in the MPDU by themselves, but that we duplicate into 217805e5a7e5SJohannes Berg * all the different MSDUs inside the A-MSDU. 217905e5a7e5SJohannes Berg */ 218005e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 218105e5a7e5SJohannes Berg 21826eb5e529SEmmanuel Grumbach tso_start(skb, &tso); 21836eb5e529SEmmanuel Grumbach 21846eb5e529SEmmanuel Grumbach while (total_len) { 21856eb5e529SEmmanuel Grumbach /* this is the data left for this subframe */ 21866eb5e529SEmmanuel Grumbach unsigned int data_left = 21876eb5e529SEmmanuel Grumbach min_t(unsigned int, mss, total_len); 21886eb5e529SEmmanuel Grumbach struct sk_buff *csum_skb = NULL; 21896eb5e529SEmmanuel Grumbach unsigned int hdr_tb_len; 21906eb5e529SEmmanuel Grumbach dma_addr_t hdr_tb_phys; 21916eb5e529SEmmanuel Grumbach struct tcphdr *tcph; 219205e5a7e5SJohannes Berg u8 *iph, *subf_hdrs_start = hdr_page->pos; 21936eb5e529SEmmanuel Grumbach 21946eb5e529SEmmanuel Grumbach total_len -= data_left; 21956eb5e529SEmmanuel Grumbach 21966eb5e529SEmmanuel Grumbach memset(hdr_page->pos, 0, amsdu_pad); 21976eb5e529SEmmanuel Grumbach hdr_page->pos += amsdu_pad; 21986eb5e529SEmmanuel Grumbach amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 21996eb5e529SEmmanuel Grumbach data_left)) & 0x3; 22006eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 22016eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 22026eb5e529SEmmanuel Grumbach ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 22036eb5e529SEmmanuel Grumbach hdr_page->pos += ETH_ALEN; 22046eb5e529SEmmanuel Grumbach 22056eb5e529SEmmanuel Grumbach length = snap_ip_tcp_hdrlen + data_left; 22066eb5e529SEmmanuel Grumbach *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 22076eb5e529SEmmanuel Grumbach hdr_page->pos += sizeof(length); 22086eb5e529SEmmanuel Grumbach 22096eb5e529SEmmanuel Grumbach /* 22106eb5e529SEmmanuel Grumbach * This will copy the SNAP as well which will be considered 22116eb5e529SEmmanuel Grumbach * as MAC header. 22126eb5e529SEmmanuel Grumbach */ 22136eb5e529SEmmanuel Grumbach tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 22146eb5e529SEmmanuel Grumbach iph = hdr_page->pos + 8; 22156eb5e529SEmmanuel Grumbach tcph = (void *)(iph + ip_hdrlen); 22166eb5e529SEmmanuel Grumbach 22176eb5e529SEmmanuel Grumbach /* For testing on current hardware only */ 22186eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22196eb5e529SEmmanuel Grumbach csum_skb = alloc_skb(data_left + tcp_hdrlen(skb), 22206eb5e529SEmmanuel Grumbach GFP_ATOMIC); 22217d50d76eSJohannes Berg if (!csum_skb) 22227d50d76eSJohannes Berg return -ENOMEM; 22236eb5e529SEmmanuel Grumbach 22246eb5e529SEmmanuel Grumbach iwl_compute_pseudo_hdr_csum(iph, tcph, 22256eb5e529SEmmanuel Grumbach skb->protocol == 22266eb5e529SEmmanuel Grumbach htons(ETH_P_IPV6), 22276eb5e529SEmmanuel Grumbach data_left); 22286eb5e529SEmmanuel Grumbach 222959ae1d12SJohannes Berg skb_put_data(csum_skb, tcph, tcp_hdrlen(skb)); 2230a52a8a4dSZhang Shengju skb_reset_transport_header(csum_skb); 22316eb5e529SEmmanuel Grumbach csum_skb->csum_start = 22326eb5e529SEmmanuel Grumbach (unsigned char *)tcp_hdr(csum_skb) - 22336eb5e529SEmmanuel Grumbach csum_skb->head; 22346eb5e529SEmmanuel Grumbach } 22356eb5e529SEmmanuel Grumbach 22366eb5e529SEmmanuel Grumbach hdr_page->pos += snap_ip_tcp_hdrlen; 22376eb5e529SEmmanuel Grumbach 22386eb5e529SEmmanuel Grumbach hdr_tb_len = hdr_page->pos - start_hdr; 22396eb5e529SEmmanuel Grumbach hdr_tb_phys = dma_map_single(trans->dev, start_hdr, 22406eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22416eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) { 22426eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22437d50d76eSJohannes Berg return -EINVAL; 22446eb5e529SEmmanuel Grumbach } 22456eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys, 22466eb5e529SEmmanuel Grumbach hdr_tb_len, false); 2247bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, 22486eb5e529SEmmanuel Grumbach hdr_tb_len); 224905e5a7e5SJohannes Berg /* add this subframe's headers' length to the tx_cmd */ 225005e5a7e5SJohannes Berg le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 22516eb5e529SEmmanuel Grumbach 22526eb5e529SEmmanuel Grumbach /* prepare the start_hdr for the next subframe */ 22536eb5e529SEmmanuel Grumbach start_hdr = hdr_page->pos; 22546eb5e529SEmmanuel Grumbach 22556eb5e529SEmmanuel Grumbach /* put the payload */ 22566eb5e529SEmmanuel Grumbach while (data_left) { 22576eb5e529SEmmanuel Grumbach unsigned int size = min_t(unsigned int, tso.size, 22586eb5e529SEmmanuel Grumbach data_left); 22596eb5e529SEmmanuel Grumbach dma_addr_t tb_phys; 22606eb5e529SEmmanuel Grumbach 22616eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) 226259ae1d12SJohannes Berg skb_put_data(csum_skb, tso.data, size); 22636eb5e529SEmmanuel Grumbach 22646eb5e529SEmmanuel Grumbach tb_phys = dma_map_single(trans->dev, tso.data, 22656eb5e529SEmmanuel Grumbach size, DMA_TO_DEVICE); 22666eb5e529SEmmanuel Grumbach if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 22676eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22687d50d76eSJohannes Berg return -EINVAL; 22696eb5e529SEmmanuel Grumbach } 22706eb5e529SEmmanuel Grumbach 22716eb5e529SEmmanuel Grumbach iwl_pcie_txq_build_tfd(trans, txq, tb_phys, 22726eb5e529SEmmanuel Grumbach size, false); 2273bf77ee2eSSara Sharon trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 22746eb5e529SEmmanuel Grumbach size); 22756eb5e529SEmmanuel Grumbach 22766eb5e529SEmmanuel Grumbach data_left -= size; 22776eb5e529SEmmanuel Grumbach tso_build_data(skb, &tso, size); 22786eb5e529SEmmanuel Grumbach } 22796eb5e529SEmmanuel Grumbach 22806eb5e529SEmmanuel Grumbach /* For testing on early hardware only */ 22816eb5e529SEmmanuel Grumbach if (trans_pcie->sw_csum_tx) { 22826eb5e529SEmmanuel Grumbach __wsum csum; 22836eb5e529SEmmanuel Grumbach 22846eb5e529SEmmanuel Grumbach csum = skb_checksum(csum_skb, 22856eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22866eb5e529SEmmanuel Grumbach csum_skb->len - 22876eb5e529SEmmanuel Grumbach skb_checksum_start_offset(csum_skb), 22886eb5e529SEmmanuel Grumbach 0); 22896eb5e529SEmmanuel Grumbach dev_kfree_skb(csum_skb); 22906eb5e529SEmmanuel Grumbach dma_sync_single_for_cpu(trans->dev, hdr_tb_phys, 22916eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22926eb5e529SEmmanuel Grumbach tcph->check = csum_fold(csum); 22936eb5e529SEmmanuel Grumbach dma_sync_single_for_device(trans->dev, hdr_tb_phys, 22946eb5e529SEmmanuel Grumbach hdr_tb_len, DMA_TO_DEVICE); 22956eb5e529SEmmanuel Grumbach } 22966eb5e529SEmmanuel Grumbach } 22976eb5e529SEmmanuel Grumbach 22986eb5e529SEmmanuel Grumbach /* re -add the WiFi header and IV */ 22996eb5e529SEmmanuel Grumbach skb_push(skb, hdr_len + iv_len); 23006eb5e529SEmmanuel Grumbach 23016eb5e529SEmmanuel Grumbach return 0; 23026eb5e529SEmmanuel Grumbach } 23036eb5e529SEmmanuel Grumbach #else /* CONFIG_INET */ 23046eb5e529SEmmanuel Grumbach static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb, 23056eb5e529SEmmanuel Grumbach struct iwl_txq *txq, u8 hdr_len, 23066eb5e529SEmmanuel Grumbach struct iwl_cmd_meta *out_meta, 23076eb5e529SEmmanuel Grumbach struct iwl_device_cmd *dev_cmd, u16 tb1_len) 23086eb5e529SEmmanuel Grumbach { 23096eb5e529SEmmanuel Grumbach /* No A-MSDU without CONFIG_INET */ 23106eb5e529SEmmanuel Grumbach WARN_ON(1); 23116eb5e529SEmmanuel Grumbach 23126eb5e529SEmmanuel Grumbach return -1; 23136eb5e529SEmmanuel Grumbach } 23146eb5e529SEmmanuel Grumbach #endif /* CONFIG_INET */ 23156eb5e529SEmmanuel Grumbach 2316e705c121SKalle Valo int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 2317e705c121SKalle Valo struct iwl_device_cmd *dev_cmd, int txq_id) 2318e705c121SKalle Valo { 2319e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2320e705c121SKalle Valo struct ieee80211_hdr *hdr; 2321e705c121SKalle Valo struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; 2322e705c121SKalle Valo struct iwl_cmd_meta *out_meta; 2323e705c121SKalle Valo struct iwl_txq *txq; 2324e705c121SKalle Valo dma_addr_t tb0_phys, tb1_phys, scratch_phys; 2325e705c121SKalle Valo void *tb1_addr; 23264fe10bc6SSara Sharon void *tfd; 23273a0b2a42SEmmanuel Grumbach u16 len, tb1_len; 2328e705c121SKalle Valo bool wait_write_ptr; 2329e705c121SKalle Valo __le16 fc; 2330e705c121SKalle Valo u8 hdr_len; 2331e705c121SKalle Valo u16 wifi_seq; 2332c772a3d3SSara Sharon bool amsdu; 2333e705c121SKalle Valo 2334b2a3b1c1SSara Sharon txq = trans_pcie->txq[txq_id]; 2335e705c121SKalle Valo 2336e705c121SKalle Valo if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 2337e705c121SKalle Valo "TX on unused queue %d\n", txq_id)) 2338e705c121SKalle Valo return -EINVAL; 2339e705c121SKalle Valo 234041837ca9SEmmanuel Grumbach if (unlikely(trans_pcie->sw_csum_tx && 234141837ca9SEmmanuel Grumbach skb->ip_summed == CHECKSUM_PARTIAL)) { 234241837ca9SEmmanuel Grumbach int offs = skb_checksum_start_offset(skb); 234341837ca9SEmmanuel Grumbach int csum_offs = offs + skb->csum_offset; 234441837ca9SEmmanuel Grumbach __wsum csum; 234541837ca9SEmmanuel Grumbach 234641837ca9SEmmanuel Grumbach if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16))) 234741837ca9SEmmanuel Grumbach return -1; 234841837ca9SEmmanuel Grumbach 234941837ca9SEmmanuel Grumbach csum = skb_checksum(skb, offs, skb->len - offs, 0); 235041837ca9SEmmanuel Grumbach *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum); 23513955525dSEmmanuel Grumbach 23523955525dSEmmanuel Grumbach skb->ip_summed = CHECKSUM_UNNECESSARY; 235341837ca9SEmmanuel Grumbach } 235441837ca9SEmmanuel Grumbach 2355e705c121SKalle Valo if (skb_is_nonlinear(skb) && 23563cd1980bSSara Sharon skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 2357e705c121SKalle Valo __skb_linearize(skb)) 2358e705c121SKalle Valo return -ENOMEM; 2359e705c121SKalle Valo 2360e705c121SKalle Valo /* mac80211 always puts the full header into the SKB's head, 2361e705c121SKalle Valo * so there's no need to check if it's readable there 2362e705c121SKalle Valo */ 2363e705c121SKalle Valo hdr = (struct ieee80211_hdr *)skb->data; 2364e705c121SKalle Valo fc = hdr->frame_control; 2365e705c121SKalle Valo hdr_len = ieee80211_hdrlen(fc); 2366e705c121SKalle Valo 2367e705c121SKalle Valo spin_lock(&txq->lock); 2368e705c121SKalle Valo 23697b3e42eaSGolan Ben Ami if (iwl_queue_space(trans, txq) < txq->high_mark) { 23703955525dSEmmanuel Grumbach iwl_stop_queue(trans, txq); 23713955525dSEmmanuel Grumbach 23723955525dSEmmanuel Grumbach /* don't put the packet on the ring, if there is no room */ 23737b3e42eaSGolan Ben Ami if (unlikely(iwl_queue_space(trans, txq) < 3)) { 237421cb3222SJohannes Berg struct iwl_device_cmd **dev_cmd_ptr; 23753955525dSEmmanuel Grumbach 237621cb3222SJohannes Berg dev_cmd_ptr = (void *)((u8 *)skb->cb + 237721cb3222SJohannes Berg trans_pcie->dev_cmd_offs); 237821cb3222SJohannes Berg 237921cb3222SJohannes Berg *dev_cmd_ptr = dev_cmd; 23803955525dSEmmanuel Grumbach __skb_queue_tail(&txq->overflow_q, skb); 23813955525dSEmmanuel Grumbach 23823955525dSEmmanuel Grumbach spin_unlock(&txq->lock); 23833955525dSEmmanuel Grumbach return 0; 23843955525dSEmmanuel Grumbach } 23853955525dSEmmanuel Grumbach } 23863955525dSEmmanuel Grumbach 2387e705c121SKalle Valo /* In AGG mode, the index in the ring must correspond to the WiFi 2388e705c121SKalle Valo * sequence number. This is a HW requirements to help the SCD to parse 2389e705c121SKalle Valo * the BA. 2390e705c121SKalle Valo * Check here that the packets are in the right place on the ring. 2391e705c121SKalle Valo */ 2392e705c121SKalle Valo wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); 2393e705c121SKalle Valo WARN_ONCE(txq->ampdu && 2394bb98ecd4SSara Sharon (wifi_seq & 0xff) != txq->write_ptr, 2395e705c121SKalle Valo "Q: %d WiFi Seq %d tfdNum %d", 2396bb98ecd4SSara Sharon txq_id, wifi_seq, txq->write_ptr); 2397e705c121SKalle Valo 2398e705c121SKalle Valo /* Set up driver data for this TFD */ 2399bb98ecd4SSara Sharon txq->entries[txq->write_ptr].skb = skb; 2400bb98ecd4SSara Sharon txq->entries[txq->write_ptr].cmd = dev_cmd; 2401e705c121SKalle Valo 2402e705c121SKalle Valo dev_cmd->hdr.sequence = 2403e705c121SKalle Valo cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 2404bb98ecd4SSara Sharon INDEX_TO_SEQ(txq->write_ptr))); 2405e705c121SKalle Valo 2406bb98ecd4SSara Sharon tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 2407e705c121SKalle Valo scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + 2408e705c121SKalle Valo offsetof(struct iwl_tx_cmd, scratch); 2409e705c121SKalle Valo 2410e705c121SKalle Valo tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 2411e705c121SKalle Valo tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); 2412e705c121SKalle Valo 2413e705c121SKalle Valo /* Set up first empty entry in queue's array of Tx/cmd buffers */ 2414bb98ecd4SSara Sharon out_meta = &txq->entries[txq->write_ptr].meta; 2415e705c121SKalle Valo out_meta->flags = 0; 2416e705c121SKalle Valo 2417e705c121SKalle Valo /* 2418e705c121SKalle Valo * The second TB (tb1) points to the remainder of the TX command 2419e705c121SKalle Valo * and the 802.11 header - dword aligned size 2420e705c121SKalle Valo * (This calculation modifies the TX command, so do it before the 2421e705c121SKalle Valo * setup of the first TB) 2422e705c121SKalle Valo */ 2423e705c121SKalle Valo len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + 24248de437c7SSara Sharon hdr_len - IWL_FIRST_TB_SIZE; 2425c772a3d3SSara Sharon /* do not align A-MSDU to dword as the subframe header aligns it */ 2426c772a3d3SSara Sharon amsdu = ieee80211_is_data_qos(fc) && 2427c772a3d3SSara Sharon (*ieee80211_get_qos_ctl(hdr) & 2428c772a3d3SSara Sharon IEEE80211_QOS_CTL_A_MSDU_PRESENT); 2429c772a3d3SSara Sharon if (trans_pcie->sw_csum_tx || !amsdu) { 2430e705c121SKalle Valo tb1_len = ALIGN(len, 4); 2431e705c121SKalle Valo /* Tell NIC about any 2-byte padding after MAC header */ 2432e705c121SKalle Valo if (tb1_len != len) 2433d172a5efSJohannes Berg tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD); 2434c772a3d3SSara Sharon } else { 2435c772a3d3SSara Sharon tb1_len = len; 2436c772a3d3SSara Sharon } 2437e705c121SKalle Valo 243805e5a7e5SJohannes Berg /* 243905e5a7e5SJohannes Berg * The first TB points to bi-directional DMA data, we'll 244005e5a7e5SJohannes Berg * memcpy the data into it later. 244105e5a7e5SJohannes Berg */ 2442e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, 24438de437c7SSara Sharon IWL_FIRST_TB_SIZE, true); 2444e705c121SKalle Valo 2445e705c121SKalle Valo /* there must be data left over for TB1 or this code must be changed */ 24468de437c7SSara Sharon BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE); 2447e705c121SKalle Valo 2448e705c121SKalle Valo /* map the data for TB1 */ 24498de437c7SSara Sharon tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 2450e705c121SKalle Valo tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 2451e705c121SKalle Valo if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) 2452e705c121SKalle Valo goto out_err; 2453e705c121SKalle Valo iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false); 2454e705c121SKalle Valo 2455bf77ee2eSSara Sharon trace_iwlwifi_dev_tx(trans->dev, skb, 2456bf77ee2eSSara Sharon iwl_pcie_get_tfd(trans, txq, 2457bf77ee2eSSara Sharon txq->write_ptr), 2458bf77ee2eSSara Sharon trans_pcie->tfd_size, 2459bf77ee2eSSara Sharon &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 2460bf77ee2eSSara Sharon hdr_len); 2461bf77ee2eSSara Sharon 2462bf1ad897SEliad Peller /* 2463bf1ad897SEliad Peller * If gso_size wasn't set, don't give the frame "amsdu treatment" 2464bf1ad897SEliad Peller * (adding subframes, etc.). 2465bf1ad897SEliad Peller * This can happen in some testing flows when the amsdu was already 2466bf1ad897SEliad Peller * pre-built, and we just need to send the resulting skb. 2467bf1ad897SEliad Peller */ 2468bf1ad897SEliad Peller if (amsdu && skb_shinfo(skb)->gso_size) { 24696eb5e529SEmmanuel Grumbach if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len, 24706eb5e529SEmmanuel Grumbach out_meta, dev_cmd, 24716eb5e529SEmmanuel Grumbach tb1_len))) 2472e705c121SKalle Valo goto out_err; 2473bb03927eSJohannes Berg } else { 24740044f171SJohannes Berg struct sk_buff *frag; 24750044f171SJohannes Berg 2476bb03927eSJohannes Berg if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len, 2477bb03927eSJohannes Berg out_meta))) 24786eb5e529SEmmanuel Grumbach goto out_err; 2479bb03927eSJohannes Berg 24800044f171SJohannes Berg skb_walk_frags(skb, frag) { 24810044f171SJohannes Berg if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0, 24820044f171SJohannes Berg out_meta))) 24830044f171SJohannes Berg goto out_err; 24840044f171SJohannes Berg } 24856eb5e529SEmmanuel Grumbach } 2486e705c121SKalle Valo 248705e5a7e5SJohannes Berg /* building the A-MSDU might have changed this data, so memcpy it now */ 2488c1f33442SLiad Kaufman memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE); 248905e5a7e5SJohannes Berg 2490943309d4SEmmanuel Grumbach tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 2491e705c121SKalle Valo /* Set up entry for this TFD in Tx byte-count array */ 24924fe10bc6SSara Sharon iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len), 24934fe10bc6SSara Sharon iwl_pcie_tfd_get_num_tbs(trans, tfd)); 2494e705c121SKalle Valo 2495e705c121SKalle Valo wait_write_ptr = ieee80211_has_morefrags(fc); 2496e705c121SKalle Valo 2497e705c121SKalle Valo /* start timer if queue currently empty */ 24980d52497aSEmmanuel Grumbach if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) { 2499e705c121SKalle Valo /* 2500e705c121SKalle Valo * If the TXQ is active, then set the timer, if not, 2501e705c121SKalle Valo * set the timer in remainder so that the timer will 2502e705c121SKalle Valo * be armed with the right value when the station will 2503e705c121SKalle Valo * wake up. 2504e705c121SKalle Valo */ 2505e705c121SKalle Valo if (!txq->frozen) 2506e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2507e705c121SKalle Valo jiffies + txq->wd_timeout); 2508e705c121SKalle Valo else 2509e705c121SKalle Valo txq->frozen_expiry_remainder = txq->wd_timeout; 2510e705c121SKalle Valo } 2511e705c121SKalle Valo 2512e705c121SKalle Valo /* Tell device the write index *just past* this latest filled TFD */ 25137b3e42eaSGolan Ben Ami txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 2514e705c121SKalle Valo if (!wait_write_ptr) 2515e705c121SKalle Valo iwl_pcie_txq_inc_wr_ptr(trans, txq); 2516e705c121SKalle Valo 2517e705c121SKalle Valo /* 2518e705c121SKalle Valo * At this point the frame is "transmitted" successfully 2519e705c121SKalle Valo * and we will get a TX status notification eventually. 2520e705c121SKalle Valo */ 2521e705c121SKalle Valo spin_unlock(&txq->lock); 2522e705c121SKalle Valo return 0; 2523e705c121SKalle Valo out_err: 25247d50d76eSJohannes Berg iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr); 2525e705c121SKalle Valo spin_unlock(&txq->lock); 2526e705c121SKalle Valo return -1; 2527e705c121SKalle Valo } 2528