1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2017 Intel Deutschland GmbH 9 * Copyright(c) 2018 - 2019 Intel Corporation 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Copyright(c) 2017 Intel Deutschland GmbH 23 * Copyright(c) 2018 - 2019 Intel Corporation 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 *****************************************************************************/ 53 #include <net/tso.h> 54 #include <linux/tcp.h> 55 56 #include "iwl-debug.h" 57 #include "iwl-csr.h" 58 #include "iwl-io.h" 59 #include "internal.h" 60 #include "fw/api/tx.h" 61 62 /* 63 * iwl_pcie_gen2_tx_stop - Stop all Tx DMA channels 64 */ 65 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans) 66 { 67 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 68 int txq_id; 69 70 /* 71 * This function can be called before the op_mode disabled the 72 * queues. This happens when we have an rfkill interrupt. 73 * Since we stop Tx altogether - mark the queues as stopped. 74 */ 75 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 76 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 77 78 /* Unmap DMA from host system and free skb's */ 79 for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) { 80 if (!trans_pcie->txq[txq_id]) 81 continue; 82 iwl_pcie_gen2_txq_unmap(trans, txq_id); 83 } 84 } 85 86 /* 87 * iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array 88 */ 89 void iwl_pcie_gen2_update_byte_tbl(struct iwl_trans_pcie *trans_pcie, 90 struct iwl_txq *txq, u16 byte_cnt, 91 int num_tbs) 92 { 93 struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr; 94 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); 95 struct iwl_gen3_bc_tbl *scd_bc_tbl_gen3 = txq->bc_tbl.addr; 96 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 97 u8 filled_tfd_size, num_fetch_chunks; 98 u16 len = byte_cnt; 99 __le16 bc_ent; 100 101 if (WARN(idx >= txq->n_window, "%d >= %d\n", idx, txq->n_window)) 102 return; 103 104 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) + 105 num_tbs * sizeof(struct iwl_tfh_tb); 106 /* 107 * filled_tfd_size contains the number of filled bytes in the TFD. 108 * Dividing it by 64 will give the number of chunks to fetch 109 * to SRAM- 0 for one chunk, 1 for 2 and so on. 110 * If, for example, TFD contains only 3 TBs then 32 bytes 111 * of the TFD are used, and only one chunk of 64 bytes should 112 * be fetched 113 */ 114 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1; 115 116 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 117 /* Starting from 22560, the HW expects bytes */ 118 WARN_ON(trans_pcie->bc_table_dword); 119 WARN_ON(len > 0x3FFF); 120 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 14)); 121 scd_bc_tbl_gen3->tfd_offset[idx] = bc_ent; 122 } else { 123 /* Until 22560, the HW expects DW */ 124 WARN_ON(!trans_pcie->bc_table_dword); 125 len = DIV_ROUND_UP(len, 4); 126 WARN_ON(len > 0xFFF); 127 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12)); 128 scd_bc_tbl->tfd_offset[idx] = bc_ent; 129 } 130 } 131 132 /* 133 * iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware 134 */ 135 void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 136 struct iwl_txq *txq) 137 { 138 lockdep_assert_held(&txq->lock); 139 140 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr); 141 142 /* 143 * if not in power-save mode, uCode will never sleep when we're 144 * trying to tx (during RFKILL, we're not trying to tx). 145 */ 146 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16)); 147 } 148 149 static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans, 150 struct iwl_tfh_tfd *tfd) 151 { 152 return le16_to_cpu(tfd->num_tbs) & 0x1f; 153 } 154 155 static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans, 156 struct iwl_cmd_meta *meta, 157 struct iwl_tfh_tfd *tfd) 158 { 159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 160 int i, num_tbs; 161 162 /* Sanity check on number of chunks */ 163 num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd); 164 165 if (num_tbs > trans_pcie->max_tbs) { 166 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 167 return; 168 } 169 170 /* first TB is never freed - it's the bidirectional DMA data */ 171 for (i = 1; i < num_tbs; i++) { 172 if (meta->tbs & BIT(i)) 173 dma_unmap_page(trans->dev, 174 le64_to_cpu(tfd->tbs[i].addr), 175 le16_to_cpu(tfd->tbs[i].tb_len), 176 DMA_TO_DEVICE); 177 else 178 dma_unmap_single(trans->dev, 179 le64_to_cpu(tfd->tbs[i].addr), 180 le16_to_cpu(tfd->tbs[i].tb_len), 181 DMA_TO_DEVICE); 182 } 183 184 tfd->num_tbs = 0; 185 } 186 187 static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 188 { 189 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 190 * idx is bounded by n_window 191 */ 192 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 193 194 lockdep_assert_held(&txq->lock); 195 196 iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta, 197 iwl_pcie_get_tfd(trans, txq, idx)); 198 199 /* free SKB */ 200 if (txq->entries) { 201 struct sk_buff *skb; 202 203 skb = txq->entries[idx].skb; 204 205 /* Can be called from irqs-disabled context 206 * If skb is not NULL, it means that the whole queue is being 207 * freed and that the queue is not empty - free the skb 208 */ 209 if (skb) { 210 iwl_op_mode_free_skb(trans->op_mode, skb); 211 txq->entries[idx].skb = NULL; 212 } 213 } 214 } 215 216 static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans, 217 struct iwl_tfh_tfd *tfd, dma_addr_t addr, 218 u16 len) 219 { 220 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 221 int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd); 222 struct iwl_tfh_tb *tb; 223 224 if (WARN_ON(idx >= IWL_TFH_NUM_TBS)) 225 return -EINVAL; 226 tb = &tfd->tbs[idx]; 227 228 /* Each TFD can point to a maximum max_tbs Tx buffers */ 229 if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) { 230 IWL_ERR(trans, "Error can not send more than %d chunks\n", 231 trans_pcie->max_tbs); 232 return -EINVAL; 233 } 234 235 put_unaligned_le64(addr, &tb->addr); 236 tb->tb_len = cpu_to_le16(len); 237 238 tfd->num_tbs = cpu_to_le16(idx + 1); 239 240 return idx; 241 } 242 243 static int iwl_pcie_gen2_build_amsdu(struct iwl_trans *trans, 244 struct sk_buff *skb, 245 struct iwl_tfh_tfd *tfd, int start_len, 246 u8 hdr_len, struct iwl_device_cmd *dev_cmd) 247 { 248 #ifdef CONFIG_INET 249 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 250 struct iwl_tx_cmd_gen2 *tx_cmd = (void *)dev_cmd->payload; 251 struct ieee80211_hdr *hdr = (void *)skb->data; 252 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 253 unsigned int mss = skb_shinfo(skb)->gso_size; 254 u16 length, iv_len, amsdu_pad; 255 u8 *start_hdr; 256 struct iwl_tso_hdr_page *hdr_page; 257 struct page **page_ptr; 258 struct tso_t tso; 259 260 /* if the packet is protected, then it must be CCMP or GCMP */ 261 iv_len = ieee80211_has_protected(hdr->frame_control) ? 262 IEEE80211_CCMP_HDR_LEN : 0; 263 264 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), 265 &dev_cmd->hdr, start_len, 0); 266 267 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 268 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 269 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 270 amsdu_pad = 0; 271 272 /* total amount of header we may need for this A-MSDU */ 273 hdr_room = DIV_ROUND_UP(total_len, mss) * 274 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 275 276 /* Our device supports 9 segments at most, it will fit in 1 page */ 277 hdr_page = get_page_hdr(trans, hdr_room); 278 if (!hdr_page) 279 return -ENOMEM; 280 281 get_page(hdr_page->page); 282 start_hdr = hdr_page->pos; 283 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 284 *page_ptr = hdr_page->page; 285 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 286 hdr_page->pos += iv_len; 287 288 /* 289 * Pull the ieee80211 header + IV to be able to use TSO core, 290 * we will restore it for the tx_status flow. 291 */ 292 skb_pull(skb, hdr_len + iv_len); 293 294 /* 295 * Remove the length of all the headers that we don't actually 296 * have in the MPDU by themselves, but that we duplicate into 297 * all the different MSDUs inside the A-MSDU. 298 */ 299 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 300 301 tso_start(skb, &tso); 302 303 while (total_len) { 304 /* this is the data left for this subframe */ 305 unsigned int data_left = min_t(unsigned int, mss, total_len); 306 struct sk_buff *csum_skb = NULL; 307 unsigned int tb_len; 308 dma_addr_t tb_phys; 309 u8 *subf_hdrs_start = hdr_page->pos; 310 311 total_len -= data_left; 312 313 memset(hdr_page->pos, 0, amsdu_pad); 314 hdr_page->pos += amsdu_pad; 315 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 316 data_left)) & 0x3; 317 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 318 hdr_page->pos += ETH_ALEN; 319 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 320 hdr_page->pos += ETH_ALEN; 321 322 length = snap_ip_tcp_hdrlen + data_left; 323 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 324 hdr_page->pos += sizeof(length); 325 326 /* 327 * This will copy the SNAP as well which will be considered 328 * as MAC header. 329 */ 330 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 331 332 hdr_page->pos += snap_ip_tcp_hdrlen; 333 334 tb_len = hdr_page->pos - start_hdr; 335 tb_phys = dma_map_single(trans->dev, start_hdr, 336 tb_len, DMA_TO_DEVICE); 337 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 338 dev_kfree_skb(csum_skb); 339 goto out_err; 340 } 341 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len); 342 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr, tb_len); 343 /* add this subframe's headers' length to the tx_cmd */ 344 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 345 346 /* prepare the start_hdr for the next subframe */ 347 start_hdr = hdr_page->pos; 348 349 /* put the payload */ 350 while (data_left) { 351 tb_len = min_t(unsigned int, tso.size, data_left); 352 tb_phys = dma_map_single(trans->dev, tso.data, 353 tb_len, DMA_TO_DEVICE); 354 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 355 dev_kfree_skb(csum_skb); 356 goto out_err; 357 } 358 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len); 359 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data, 360 tb_len); 361 362 data_left -= tb_len; 363 tso_build_data(skb, &tso, tb_len); 364 } 365 } 366 367 /* re -add the WiFi header and IV */ 368 skb_push(skb, hdr_len + iv_len); 369 370 return 0; 371 372 out_err: 373 #endif 374 return -EINVAL; 375 } 376 377 static struct 378 iwl_tfh_tfd *iwl_pcie_gen2_build_tx_amsdu(struct iwl_trans *trans, 379 struct iwl_txq *txq, 380 struct iwl_device_cmd *dev_cmd, 381 struct sk_buff *skb, 382 struct iwl_cmd_meta *out_meta, 383 int hdr_len, 384 int tx_cmd_len) 385 { 386 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 387 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx); 388 dma_addr_t tb_phys; 389 int len; 390 void *tb1_addr; 391 392 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx); 393 394 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE); 395 396 /* 397 * The second TB (tb1) points to the remainder of the TX command 398 * and the 802.11 header - dword aligned size 399 * (This calculation modifies the TX command, so do it before the 400 * setup of the first TB) 401 */ 402 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len - 403 IWL_FIRST_TB_SIZE; 404 405 /* do not align A-MSDU to dword as the subframe header aligns it */ 406 407 /* map the data for TB1 */ 408 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 409 tb_phys = dma_map_single(trans->dev, tb1_addr, len, DMA_TO_DEVICE); 410 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 411 goto out_err; 412 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, len); 413 414 if (iwl_pcie_gen2_build_amsdu(trans, skb, tfd, 415 len + IWL_FIRST_TB_SIZE, 416 hdr_len, dev_cmd)) 417 goto out_err; 418 419 /* building the A-MSDU might have changed this data, memcpy it now */ 420 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE); 421 return tfd; 422 423 out_err: 424 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 425 return NULL; 426 } 427 428 static int iwl_pcie_gen2_tx_add_frags(struct iwl_trans *trans, 429 struct sk_buff *skb, 430 struct iwl_tfh_tfd *tfd, 431 struct iwl_cmd_meta *out_meta) 432 { 433 int i; 434 435 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 436 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 437 dma_addr_t tb_phys; 438 int tb_idx; 439 440 if (!skb_frag_size(frag)) 441 continue; 442 443 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 444 skb_frag_size(frag), DMA_TO_DEVICE); 445 446 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 447 return -ENOMEM; 448 tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, 449 skb_frag_size(frag)); 450 trace_iwlwifi_dev_tx_tb(trans->dev, skb, 451 skb_frag_address(frag), 452 skb_frag_size(frag)); 453 if (tb_idx < 0) 454 return tb_idx; 455 456 out_meta->tbs |= BIT(tb_idx); 457 } 458 459 return 0; 460 } 461 462 static struct 463 iwl_tfh_tfd *iwl_pcie_gen2_build_tx(struct iwl_trans *trans, 464 struct iwl_txq *txq, 465 struct iwl_device_cmd *dev_cmd, 466 struct sk_buff *skb, 467 struct iwl_cmd_meta *out_meta, 468 int hdr_len, 469 int tx_cmd_len, 470 bool pad) 471 { 472 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 473 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx); 474 dma_addr_t tb_phys; 475 int len, tb1_len, tb2_len; 476 void *tb1_addr; 477 478 tb_phys = iwl_pcie_get_first_tb_dma(txq, idx); 479 480 /* The first TB points to bi-directional DMA data */ 481 memcpy(&txq->first_tb_bufs[idx], dev_cmd, IWL_FIRST_TB_SIZE); 482 483 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE); 484 485 /* 486 * The second TB (tb1) points to the remainder of the TX command 487 * and the 802.11 header - dword aligned size 488 * (This calculation modifies the TX command, so do it before the 489 * setup of the first TB) 490 */ 491 len = tx_cmd_len + sizeof(struct iwl_cmd_header) + hdr_len - 492 IWL_FIRST_TB_SIZE; 493 494 if (pad) 495 tb1_len = ALIGN(len, 4); 496 else 497 tb1_len = len; 498 499 /* map the data for TB1 */ 500 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 501 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 502 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 503 goto out_err; 504 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len); 505 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr, 506 IWL_FIRST_TB_SIZE + tb1_len, hdr_len); 507 508 /* set up TFD's third entry to point to remainder of skb's head */ 509 tb2_len = skb_headlen(skb) - hdr_len; 510 511 if (tb2_len > 0) { 512 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len, 513 tb2_len, DMA_TO_DEVICE); 514 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 515 goto out_err; 516 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len); 517 trace_iwlwifi_dev_tx_tb(trans->dev, skb, 518 skb->data + hdr_len, 519 tb2_len); 520 } 521 522 if (iwl_pcie_gen2_tx_add_frags(trans, skb, tfd, out_meta)) 523 goto out_err; 524 525 return tfd; 526 527 out_err: 528 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 529 return NULL; 530 } 531 532 static 533 struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans, 534 struct iwl_txq *txq, 535 struct iwl_device_cmd *dev_cmd, 536 struct sk_buff *skb, 537 struct iwl_cmd_meta *out_meta) 538 { 539 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 540 int idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 541 struct iwl_tfh_tfd *tfd = iwl_pcie_get_tfd(trans, txq, idx); 542 int len, hdr_len; 543 bool amsdu; 544 545 /* There must be data left over for TB1 or this code must be changed */ 546 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE); 547 548 memset(tfd, 0, sizeof(*tfd)); 549 550 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_22560) 551 len = sizeof(struct iwl_tx_cmd_gen2); 552 else 553 len = sizeof(struct iwl_tx_cmd_gen3); 554 555 amsdu = ieee80211_is_data_qos(hdr->frame_control) && 556 (*ieee80211_get_qos_ctl(hdr) & 557 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 558 559 hdr_len = ieee80211_hdrlen(hdr->frame_control); 560 561 /* 562 * Only build A-MSDUs here if doing so by GSO, otherwise it may be 563 * an A-MSDU for other reasons, e.g. NAN or an A-MSDU having been 564 * built in the higher layers already. 565 */ 566 if (amsdu && skb_shinfo(skb)->gso_size) 567 return iwl_pcie_gen2_build_tx_amsdu(trans, txq, dev_cmd, skb, 568 out_meta, hdr_len, len); 569 570 return iwl_pcie_gen2_build_tx(trans, txq, dev_cmd, skb, out_meta, 571 hdr_len, len, !amsdu); 572 } 573 574 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 575 struct iwl_device_cmd *dev_cmd, int txq_id) 576 { 577 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 578 struct iwl_cmd_meta *out_meta; 579 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 580 u16 cmd_len; 581 int idx; 582 void *tfd; 583 584 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 585 "TX on unused queue %d\n", txq_id)) 586 return -EINVAL; 587 588 if (skb_is_nonlinear(skb) && 589 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 590 __skb_linearize(skb)) 591 return -ENOMEM; 592 593 spin_lock(&txq->lock); 594 595 if (iwl_queue_space(trans, txq) < txq->high_mark) { 596 iwl_stop_queue(trans, txq); 597 598 /* don't put the packet on the ring, if there is no room */ 599 if (unlikely(iwl_queue_space(trans, txq) < 3)) { 600 struct iwl_device_cmd **dev_cmd_ptr; 601 602 dev_cmd_ptr = (void *)((u8 *)skb->cb + 603 trans_pcie->dev_cmd_offs); 604 605 *dev_cmd_ptr = dev_cmd; 606 __skb_queue_tail(&txq->overflow_q, skb); 607 spin_unlock(&txq->lock); 608 return 0; 609 } 610 } 611 612 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 613 614 /* Set up driver data for this TFD */ 615 txq->entries[idx].skb = skb; 616 txq->entries[idx].cmd = dev_cmd; 617 618 dev_cmd->hdr.sequence = 619 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 620 INDEX_TO_SEQ(idx))); 621 622 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 623 out_meta = &txq->entries[idx].meta; 624 out_meta->flags = 0; 625 626 tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta); 627 if (!tfd) { 628 spin_unlock(&txq->lock); 629 return -1; 630 } 631 632 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_22560) { 633 struct iwl_tx_cmd_gen3 *tx_cmd_gen3 = 634 (void *)dev_cmd->payload; 635 636 cmd_len = le16_to_cpu(tx_cmd_gen3->len); 637 } else { 638 struct iwl_tx_cmd_gen2 *tx_cmd_gen2 = 639 (void *)dev_cmd->payload; 640 641 cmd_len = le16_to_cpu(tx_cmd_gen2->len); 642 } 643 644 /* Set up entry for this TFD in Tx byte-count array */ 645 iwl_pcie_gen2_update_byte_tbl(trans_pcie, txq, cmd_len, 646 iwl_pcie_gen2_get_num_tbs(trans, tfd)); 647 648 /* start timer if queue currently empty */ 649 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 650 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 651 652 /* Tell device the write index *just past* this latest filled TFD */ 653 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 654 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq); 655 /* 656 * At this point the frame is "transmitted" successfully 657 * and we will get a TX status notification eventually. 658 */ 659 spin_unlock(&txq->lock); 660 return 0; 661 } 662 663 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 664 665 /* 666 * iwl_pcie_gen2_enqueue_hcmd - enqueue a uCode command 667 * @priv: device private data point 668 * @cmd: a pointer to the ucode command structure 669 * 670 * The function returns < 0 values to indicate the operation 671 * failed. On success, it returns the index (>= 0) of command in the 672 * command queue. 673 */ 674 static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans, 675 struct iwl_host_cmd *cmd) 676 { 677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 678 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 679 struct iwl_device_cmd *out_cmd; 680 struct iwl_cmd_meta *out_meta; 681 unsigned long flags; 682 void *dup_buf = NULL; 683 dma_addr_t phys_addr; 684 int i, cmd_pos, idx; 685 u16 copy_size, cmd_size, tb0_size; 686 bool had_nocopy = false; 687 u8 group_id = iwl_cmd_groupid(cmd->id); 688 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 689 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 690 struct iwl_tfh_tfd *tfd; 691 692 copy_size = sizeof(struct iwl_cmd_header_wide); 693 cmd_size = sizeof(struct iwl_cmd_header_wide); 694 695 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 696 cmddata[i] = cmd->data[i]; 697 cmdlen[i] = cmd->len[i]; 698 699 if (!cmd->len[i]) 700 continue; 701 702 /* need at least IWL_FIRST_TB_SIZE copied */ 703 if (copy_size < IWL_FIRST_TB_SIZE) { 704 int copy = IWL_FIRST_TB_SIZE - copy_size; 705 706 if (copy > cmdlen[i]) 707 copy = cmdlen[i]; 708 cmdlen[i] -= copy; 709 cmddata[i] += copy; 710 copy_size += copy; 711 } 712 713 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 714 had_nocopy = true; 715 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 716 idx = -EINVAL; 717 goto free_dup_buf; 718 } 719 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 720 /* 721 * This is also a chunk that isn't copied 722 * to the static buffer so set had_nocopy. 723 */ 724 had_nocopy = true; 725 726 /* only allowed once */ 727 if (WARN_ON(dup_buf)) { 728 idx = -EINVAL; 729 goto free_dup_buf; 730 } 731 732 dup_buf = kmemdup(cmddata[i], cmdlen[i], 733 GFP_ATOMIC); 734 if (!dup_buf) 735 return -ENOMEM; 736 } else { 737 /* NOCOPY must not be followed by normal! */ 738 if (WARN_ON(had_nocopy)) { 739 idx = -EINVAL; 740 goto free_dup_buf; 741 } 742 copy_size += cmdlen[i]; 743 } 744 cmd_size += cmd->len[i]; 745 } 746 747 /* 748 * If any of the command structures end up being larger than the 749 * TFD_MAX_PAYLOAD_SIZE and they aren't dynamically allocated into 750 * separate TFDs, then we will need to increase the size of the buffers 751 */ 752 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 753 "Command %s (%#x) is too large (%d bytes)\n", 754 iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) { 755 idx = -EINVAL; 756 goto free_dup_buf; 757 } 758 759 spin_lock_bh(&txq->lock); 760 761 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr); 762 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr); 763 memset(tfd, 0, sizeof(*tfd)); 764 765 if (iwl_queue_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 766 spin_unlock_bh(&txq->lock); 767 768 IWL_ERR(trans, "No space in command queue\n"); 769 iwl_op_mode_cmd_queue_full(trans->op_mode); 770 idx = -ENOSPC; 771 goto free_dup_buf; 772 } 773 774 out_cmd = txq->entries[idx].cmd; 775 out_meta = &txq->entries[idx].meta; 776 777 /* re-initialize to NULL */ 778 memset(out_meta, 0, sizeof(*out_meta)); 779 if (cmd->flags & CMD_WANT_SKB) 780 out_meta->source = cmd; 781 782 /* set up the header */ 783 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 784 out_cmd->hdr_wide.group_id = group_id; 785 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 786 out_cmd->hdr_wide.length = 787 cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide)); 788 out_cmd->hdr_wide.reserved = 0; 789 out_cmd->hdr_wide.sequence = 790 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 791 INDEX_TO_SEQ(txq->write_ptr)); 792 793 cmd_pos = sizeof(struct iwl_cmd_header_wide); 794 copy_size = sizeof(struct iwl_cmd_header_wide); 795 796 /* and copy the data that needs to be copied */ 797 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 798 int copy; 799 800 if (!cmd->len[i]) 801 continue; 802 803 /* copy everything if not nocopy/dup */ 804 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 805 IWL_HCMD_DFL_DUP))) { 806 copy = cmd->len[i]; 807 808 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 809 cmd_pos += copy; 810 copy_size += copy; 811 continue; 812 } 813 814 /* 815 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 816 * in total (for bi-directional DMA), but copy up to what 817 * we can fit into the payload for debug dump purposes. 818 */ 819 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 820 821 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 822 cmd_pos += copy; 823 824 /* However, treat copy_size the proper way, we need it below */ 825 if (copy_size < IWL_FIRST_TB_SIZE) { 826 copy = IWL_FIRST_TB_SIZE - copy_size; 827 828 if (copy > cmd->len[i]) 829 copy = cmd->len[i]; 830 copy_size += copy; 831 } 832 } 833 834 IWL_DEBUG_HC(trans, 835 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 836 iwl_get_cmd_string(trans, cmd->id), group_id, 837 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), 838 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 839 840 /* start the TFD with the minimum copy bytes */ 841 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 842 memcpy(&txq->first_tb_bufs[idx], out_cmd, tb0_size); 843 iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx), 844 tb0_size); 845 846 /* map first command fragment, if any remains */ 847 if (copy_size > tb0_size) { 848 phys_addr = dma_map_single(trans->dev, 849 (u8 *)out_cmd + tb0_size, 850 copy_size - tb0_size, 851 DMA_TO_DEVICE); 852 if (dma_mapping_error(trans->dev, phys_addr)) { 853 idx = -ENOMEM; 854 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 855 goto out; 856 } 857 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, 858 copy_size - tb0_size); 859 } 860 861 /* map the remaining (adjusted) nocopy/dup fragments */ 862 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 863 const void *data = cmddata[i]; 864 865 if (!cmdlen[i]) 866 continue; 867 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 868 IWL_HCMD_DFL_DUP))) 869 continue; 870 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 871 data = dup_buf; 872 phys_addr = dma_map_single(trans->dev, (void *)data, 873 cmdlen[i], DMA_TO_DEVICE); 874 if (dma_mapping_error(trans->dev, phys_addr)) { 875 idx = -ENOMEM; 876 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 877 goto out; 878 } 879 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]); 880 } 881 882 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 883 out_meta->flags = cmd->flags; 884 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 885 kzfree(txq->entries[idx].free_buf); 886 txq->entries[idx].free_buf = dup_buf; 887 888 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 889 890 /* start timer if queue currently empty */ 891 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 892 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 893 894 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 895 /* Increment and update queue's write index */ 896 txq->write_ptr = iwl_queue_inc_wrap(trans, txq->write_ptr); 897 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq); 898 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 899 900 out: 901 spin_unlock_bh(&txq->lock); 902 free_dup_buf: 903 if (idx < 0) 904 kfree(dup_buf); 905 return idx; 906 } 907 908 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 909 910 static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans, 911 struct iwl_host_cmd *cmd) 912 { 913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 914 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id); 915 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 916 int cmd_idx; 917 int ret; 918 919 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str); 920 921 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 922 &trans->status), 923 "Command %s: a command is already active!\n", cmd_str)) 924 return -EIO; 925 926 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str); 927 928 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd); 929 if (cmd_idx < 0) { 930 ret = cmd_idx; 931 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 932 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n", 933 cmd_str, ret); 934 return ret; 935 } 936 937 ret = wait_event_timeout(trans_pcie->wait_command_queue, 938 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 939 &trans->status), 940 HOST_COMPLETE_TIMEOUT); 941 if (!ret) { 942 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 943 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 944 945 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 946 txq->read_ptr, txq->write_ptr); 947 948 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 949 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 950 cmd_str); 951 ret = -ETIMEDOUT; 952 953 iwl_trans_pcie_sync_nmi(trans); 954 goto cancel; 955 } 956 957 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 958 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str); 959 dump_stack(); 960 ret = -EIO; 961 goto cancel; 962 } 963 964 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 965 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 966 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 967 ret = -ERFKILL; 968 goto cancel; 969 } 970 971 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 972 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str); 973 ret = -EIO; 974 goto cancel; 975 } 976 977 return 0; 978 979 cancel: 980 if (cmd->flags & CMD_WANT_SKB) { 981 /* 982 * Cancel the CMD_WANT_SKB flag for the cmd in the 983 * TX cmd queue. Otherwise in case the cmd comes 984 * in later, it will possibly set an invalid 985 * address (cmd->meta.source). 986 */ 987 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 988 } 989 990 if (cmd->resp_pkt) { 991 iwl_free_resp(cmd); 992 cmd->resp_pkt = NULL; 993 } 994 995 return ret; 996 } 997 998 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 999 struct iwl_host_cmd *cmd) 1000 { 1001 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 1002 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 1003 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 1004 cmd->id); 1005 return -ERFKILL; 1006 } 1007 1008 if (cmd->flags & CMD_ASYNC) { 1009 int ret; 1010 1011 /* An asynchronous command can not expect an SKB to be set. */ 1012 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 1013 return -EINVAL; 1014 1015 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd); 1016 if (ret < 0) { 1017 IWL_ERR(trans, 1018 "Error sending %s: enqueue_hcmd failed: %d\n", 1019 iwl_get_cmd_string(trans, cmd->id), ret); 1020 return ret; 1021 } 1022 return 0; 1023 } 1024 1025 return iwl_pcie_gen2_send_hcmd_sync(trans, cmd); 1026 } 1027 1028 /* 1029 * iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's 1030 */ 1031 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id) 1032 { 1033 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1034 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1035 1036 spin_lock_bh(&txq->lock); 1037 while (txq->write_ptr != txq->read_ptr) { 1038 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 1039 txq_id, txq->read_ptr); 1040 1041 if (txq_id != trans_pcie->cmd_queue) { 1042 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr); 1043 struct sk_buff *skb = txq->entries[idx].skb; 1044 1045 if (WARN_ON_ONCE(!skb)) 1046 continue; 1047 1048 iwl_pcie_free_tso_page(trans_pcie, skb); 1049 } 1050 iwl_pcie_gen2_free_tfd(trans, txq); 1051 txq->read_ptr = iwl_queue_inc_wrap(trans, txq->read_ptr); 1052 } 1053 1054 while (!skb_queue_empty(&txq->overflow_q)) { 1055 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q); 1056 1057 iwl_op_mode_free_skb(trans->op_mode, skb); 1058 } 1059 1060 spin_unlock_bh(&txq->lock); 1061 1062 /* just in case - this queue may have been stopped */ 1063 iwl_wake_queue(trans, txq); 1064 } 1065 1066 void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 1067 struct iwl_txq *txq) 1068 { 1069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1070 struct device *dev = trans->dev; 1071 1072 /* De-alloc circular buffer of TFDs */ 1073 if (txq->tfds) { 1074 dma_free_coherent(dev, 1075 trans_pcie->tfd_size * txq->n_window, 1076 txq->tfds, txq->dma_addr); 1077 dma_free_coherent(dev, 1078 sizeof(*txq->first_tb_bufs) * txq->n_window, 1079 txq->first_tb_bufs, txq->first_tb_dma); 1080 } 1081 1082 kfree(txq->entries); 1083 iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl); 1084 kfree(txq); 1085 } 1086 1087 /* 1088 * iwl_pcie_txq_free - Deallocate DMA queue. 1089 * @txq: Transmit queue to deallocate. 1090 * 1091 * Empty queue by removing and destroying all BD's. 1092 * Free all buffers. 1093 * 0-fill, but do not free "txq" descriptor structure. 1094 */ 1095 static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id) 1096 { 1097 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1098 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 1099 int i; 1100 1101 if (WARN_ON(!txq)) 1102 return; 1103 1104 iwl_pcie_gen2_txq_unmap(trans, txq_id); 1105 1106 /* De-alloc array of command/tx buffers */ 1107 if (txq_id == trans_pcie->cmd_queue) 1108 for (i = 0; i < txq->n_window; i++) { 1109 kzfree(txq->entries[i].cmd); 1110 kzfree(txq->entries[i].free_buf); 1111 } 1112 del_timer_sync(&txq->stuck_timer); 1113 1114 iwl_pcie_gen2_txq_free_memory(trans, txq); 1115 1116 trans_pcie->txq[txq_id] = NULL; 1117 1118 clear_bit(txq_id, trans_pcie->queue_used); 1119 } 1120 1121 int iwl_trans_pcie_dyn_txq_alloc_dma(struct iwl_trans *trans, 1122 struct iwl_txq **intxq, int size, 1123 unsigned int timeout) 1124 { 1125 int ret; 1126 1127 struct iwl_txq *txq; 1128 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 1129 if (!txq) 1130 return -ENOMEM; 1131 ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl, 1132 (trans->trans_cfg->device_family >= 1133 IWL_DEVICE_FAMILY_22560) ? 1134 sizeof(struct iwl_gen3_bc_tbl) : 1135 sizeof(struct iwlagn_scd_bc_tbl)); 1136 if (ret) { 1137 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 1138 kfree(txq); 1139 return -ENOMEM; 1140 } 1141 1142 ret = iwl_pcie_txq_alloc(trans, txq, size, false); 1143 if (ret) { 1144 IWL_ERR(trans, "Tx queue alloc failed\n"); 1145 goto error; 1146 } 1147 ret = iwl_pcie_txq_init(trans, txq, size, false); 1148 if (ret) { 1149 IWL_ERR(trans, "Tx queue init failed\n"); 1150 goto error; 1151 } 1152 1153 txq->wd_timeout = msecs_to_jiffies(timeout); 1154 1155 *intxq = txq; 1156 return 0; 1157 1158 error: 1159 iwl_pcie_gen2_txq_free_memory(trans, txq); 1160 return ret; 1161 } 1162 1163 int iwl_trans_pcie_txq_alloc_response(struct iwl_trans *trans, 1164 struct iwl_txq *txq, 1165 struct iwl_host_cmd *hcmd) 1166 { 1167 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1168 struct iwl_tx_queue_cfg_rsp *rsp; 1169 int ret, qid; 1170 u32 wr_ptr; 1171 1172 if (WARN_ON(iwl_rx_packet_payload_len(hcmd->resp_pkt) != 1173 sizeof(*rsp))) { 1174 ret = -EINVAL; 1175 goto error_free_resp; 1176 } 1177 1178 rsp = (void *)hcmd->resp_pkt->data; 1179 qid = le16_to_cpu(rsp->queue_number); 1180 wr_ptr = le16_to_cpu(rsp->write_pointer); 1181 1182 if (qid >= ARRAY_SIZE(trans_pcie->txq)) { 1183 WARN_ONCE(1, "queue index %d unsupported", qid); 1184 ret = -EIO; 1185 goto error_free_resp; 1186 } 1187 1188 if (test_and_set_bit(qid, trans_pcie->queue_used)) { 1189 WARN_ONCE(1, "queue %d already used", qid); 1190 ret = -EIO; 1191 goto error_free_resp; 1192 } 1193 1194 txq->id = qid; 1195 trans_pcie->txq[qid] = txq; 1196 wr_ptr &= (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 1197 1198 /* Place first TFD at index corresponding to start sequence number */ 1199 txq->read_ptr = wr_ptr; 1200 txq->write_ptr = wr_ptr; 1201 1202 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid); 1203 1204 iwl_free_resp(hcmd); 1205 return qid; 1206 1207 error_free_resp: 1208 iwl_free_resp(hcmd); 1209 iwl_pcie_gen2_txq_free_memory(trans, txq); 1210 return ret; 1211 } 1212 1213 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1214 __le16 flags, u8 sta_id, u8 tid, 1215 int cmd_id, int size, 1216 unsigned int timeout) 1217 { 1218 struct iwl_txq *txq = NULL; 1219 struct iwl_tx_queue_cfg_cmd cmd = { 1220 .flags = flags, 1221 .sta_id = sta_id, 1222 .tid = tid, 1223 }; 1224 struct iwl_host_cmd hcmd = { 1225 .id = cmd_id, 1226 .len = { sizeof(cmd) }, 1227 .data = { &cmd, }, 1228 .flags = CMD_WANT_SKB, 1229 }; 1230 int ret; 1231 1232 ret = iwl_trans_pcie_dyn_txq_alloc_dma(trans, &txq, size, timeout); 1233 if (ret) 1234 return ret; 1235 1236 cmd.tfdq_addr = cpu_to_le64(txq->dma_addr); 1237 cmd.byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma); 1238 cmd.cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(size)); 1239 1240 ret = iwl_trans_send_cmd(trans, &hcmd); 1241 if (ret) 1242 goto error; 1243 1244 return iwl_trans_pcie_txq_alloc_response(trans, txq, &hcmd); 1245 1246 error: 1247 iwl_pcie_gen2_txq_free_memory(trans, txq); 1248 return ret; 1249 } 1250 1251 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue) 1252 { 1253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1254 1255 /* 1256 * Upon HW Rfkill - we stop the device, and then stop the queues 1257 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1258 * allow the op_mode to call txq_disable after it already called 1259 * stop_device. 1260 */ 1261 if (!test_and_clear_bit(queue, trans_pcie->queue_used)) { 1262 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1263 "queue %d not used", queue); 1264 return; 1265 } 1266 1267 iwl_pcie_gen2_txq_unmap(trans, queue); 1268 1269 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue); 1270 } 1271 1272 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans) 1273 { 1274 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1275 int i; 1276 1277 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 1278 1279 /* Free all TX queues */ 1280 for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) { 1281 if (!trans_pcie->txq[i]) 1282 continue; 1283 1284 iwl_pcie_gen2_txq_free(trans, i); 1285 } 1286 } 1287 1288 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans, int txq_id, int queue_size) 1289 { 1290 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1291 struct iwl_txq *queue; 1292 int ret; 1293 1294 /* alloc and init the tx queue */ 1295 if (!trans_pcie->txq[txq_id]) { 1296 queue = kzalloc(sizeof(*queue), GFP_KERNEL); 1297 if (!queue) { 1298 IWL_ERR(trans, "Not enough memory for tx queue\n"); 1299 return -ENOMEM; 1300 } 1301 trans_pcie->txq[txq_id] = queue; 1302 ret = iwl_pcie_txq_alloc(trans, queue, queue_size, true); 1303 if (ret) { 1304 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1305 goto error; 1306 } 1307 } else { 1308 queue = trans_pcie->txq[txq_id]; 1309 } 1310 1311 ret = iwl_pcie_txq_init(trans, queue, queue_size, 1312 (txq_id == trans_pcie->cmd_queue)); 1313 if (ret) { 1314 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 1315 goto error; 1316 } 1317 trans_pcie->txq[txq_id]->id = txq_id; 1318 set_bit(txq_id, trans_pcie->queue_used); 1319 1320 return 0; 1321 1322 error: 1323 iwl_pcie_gen2_tx_free(trans); 1324 return ret; 1325 } 1326 1327