1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2017 Intel Deutschland GmbH 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * BSD LICENSE 20 * 21 * Copyright(c) 2017 Intel Deutschland GmbH 22 * All rights reserved. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 28 * * Redistributions of source code must retain the above copyright 29 * notice, this list of conditions and the following disclaimer. 30 * * Redistributions in binary form must reproduce the above copyright 31 * notice, this list of conditions and the following disclaimer in 32 * the documentation and/or other materials provided with the 33 * distribution. 34 * * Neither the name Intel Corporation nor the names of its 35 * contributors may be used to endorse or promote products derived 36 * from this software without specific prior written permission. 37 * 38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 39 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 40 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 41 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 42 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 43 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 44 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 * 50 *****************************************************************************/ 51 #include <linux/pm_runtime.h> 52 #include <net/tso.h> 53 54 #include "iwl-debug.h" 55 #include "iwl-csr.h" 56 #include "iwl-io.h" 57 #include "internal.h" 58 #include "mvm/fw-api.h" 59 60 /* 61 * iwl_pcie_gen2_tx_stop - Stop all Tx DMA channels 62 */ 63 void iwl_pcie_gen2_tx_stop(struct iwl_trans *trans) 64 { 65 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 66 int txq_id; 67 68 /* 69 * This function can be called before the op_mode disabled the 70 * queues. This happens when we have an rfkill interrupt. 71 * Since we stop Tx altogether - mark the queues as stopped. 72 */ 73 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 74 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 75 76 /* Unmap DMA from host system and free skb's */ 77 for (txq_id = 0; txq_id < ARRAY_SIZE(trans_pcie->txq); txq_id++) { 78 if (!trans_pcie->txq[txq_id]) 79 continue; 80 iwl_pcie_gen2_txq_unmap(trans, txq_id); 81 } 82 } 83 84 /* 85 * iwl_pcie_txq_update_byte_tbl - Set up entry in Tx byte-count array 86 */ 87 static void iwl_pcie_gen2_update_byte_tbl(struct iwl_txq *txq, u16 byte_cnt, 88 int num_tbs) 89 { 90 struct iwlagn_scd_bc_tbl *scd_bc_tbl = txq->bc_tbl.addr; 91 int write_ptr = txq->write_ptr; 92 u8 filled_tfd_size, num_fetch_chunks; 93 u16 len = byte_cnt; 94 __le16 bc_ent; 95 96 len = DIV_ROUND_UP(len, 4); 97 98 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX)) 99 return; 100 101 filled_tfd_size = offsetof(struct iwl_tfh_tfd, tbs) + 102 num_tbs * sizeof(struct iwl_tfh_tb); 103 /* 104 * filled_tfd_size contains the number of filled bytes in the TFD. 105 * Dividing it by 64 will give the number of chunks to fetch 106 * to SRAM- 0 for one chunk, 1 for 2 and so on. 107 * If, for example, TFD contains only 3 TBs then 32 bytes 108 * of the TFD are used, and only one chunk of 64 bytes should 109 * be fetched 110 */ 111 num_fetch_chunks = DIV_ROUND_UP(filled_tfd_size, 64) - 1; 112 113 bc_ent = cpu_to_le16(len | (num_fetch_chunks << 12)); 114 scd_bc_tbl->tfd_offset[write_ptr] = bc_ent; 115 } 116 117 /* 118 * iwl_pcie_gen2_txq_inc_wr_ptr - Send new write index to hardware 119 */ 120 static void iwl_pcie_gen2_txq_inc_wr_ptr(struct iwl_trans *trans, 121 struct iwl_txq *txq) 122 { 123 lockdep_assert_held(&txq->lock); 124 125 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq->id, txq->write_ptr); 126 127 /* 128 * if not in power-save mode, uCode will never sleep when we're 129 * trying to tx (during RFKILL, we're not trying to tx). 130 */ 131 iwl_write32(trans, HBUS_TARG_WRPTR, txq->write_ptr | (txq->id << 16)); 132 } 133 134 static u8 iwl_pcie_gen2_get_num_tbs(struct iwl_trans *trans, 135 struct iwl_tfh_tfd *tfd) 136 { 137 return le16_to_cpu(tfd->num_tbs) & 0x1f; 138 } 139 140 static void iwl_pcie_gen2_tfd_unmap(struct iwl_trans *trans, 141 struct iwl_cmd_meta *meta, 142 struct iwl_tfh_tfd *tfd) 143 { 144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 145 int i, num_tbs; 146 147 /* Sanity check on number of chunks */ 148 num_tbs = iwl_pcie_gen2_get_num_tbs(trans, tfd); 149 150 if (num_tbs >= trans_pcie->max_tbs) { 151 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); 152 return; 153 } 154 155 /* first TB is never freed - it's the bidirectional DMA data */ 156 for (i = 1; i < num_tbs; i++) { 157 if (meta->tbs & BIT(i)) 158 dma_unmap_page(trans->dev, 159 le64_to_cpu(tfd->tbs[i].addr), 160 le16_to_cpu(tfd->tbs[i].tb_len), 161 DMA_TO_DEVICE); 162 else 163 dma_unmap_single(trans->dev, 164 le64_to_cpu(tfd->tbs[i].addr), 165 le16_to_cpu(tfd->tbs[i].tb_len), 166 DMA_TO_DEVICE); 167 } 168 169 tfd->num_tbs = 0; 170 } 171 172 static void iwl_pcie_gen2_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) 173 { 174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 175 176 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and 177 * idx is bounded by n_window 178 */ 179 int rd_ptr = txq->read_ptr; 180 int idx = get_cmd_index(txq, rd_ptr); 181 182 lockdep_assert_held(&txq->lock); 183 184 /* We have only q->n_window txq->entries, but we use 185 * TFD_QUEUE_SIZE_MAX tfds 186 */ 187 iwl_pcie_gen2_tfd_unmap(trans, &txq->entries[idx].meta, 188 iwl_pcie_get_tfd(trans_pcie, txq, rd_ptr)); 189 190 /* free SKB */ 191 if (txq->entries) { 192 struct sk_buff *skb; 193 194 skb = txq->entries[idx].skb; 195 196 /* Can be called from irqs-disabled context 197 * If skb is not NULL, it means that the whole queue is being 198 * freed and that the queue is not empty - free the skb 199 */ 200 if (skb) { 201 iwl_op_mode_free_skb(trans->op_mode, skb); 202 txq->entries[idx].skb = NULL; 203 } 204 } 205 } 206 207 static int iwl_pcie_gen2_set_tb(struct iwl_trans *trans, 208 struct iwl_tfh_tfd *tfd, dma_addr_t addr, 209 u16 len) 210 { 211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 212 int idx = iwl_pcie_gen2_get_num_tbs(trans, tfd); 213 struct iwl_tfh_tb *tb = &tfd->tbs[idx]; 214 215 /* Each TFD can point to a maximum max_tbs Tx buffers */ 216 if (le16_to_cpu(tfd->num_tbs) >= trans_pcie->max_tbs) { 217 IWL_ERR(trans, "Error can not send more than %d chunks\n", 218 trans_pcie->max_tbs); 219 return -EINVAL; 220 } 221 222 put_unaligned_le64(addr, &tb->addr); 223 tb->tb_len = cpu_to_le16(len); 224 225 tfd->num_tbs = cpu_to_le16(idx + 1); 226 227 return idx; 228 } 229 230 static int iwl_pcie_gen2_build_amsdu(struct iwl_trans *trans, 231 struct sk_buff *skb, 232 struct iwl_tfh_tfd *tfd, int start_len, 233 u8 hdr_len, struct iwl_device_cmd *dev_cmd) 234 { 235 #ifdef CONFIG_INET 236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 237 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload; 238 struct ieee80211_hdr *hdr = (void *)skb->data; 239 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room; 240 unsigned int mss = skb_shinfo(skb)->gso_size; 241 u16 length, iv_len, amsdu_pad; 242 u8 *start_hdr; 243 struct iwl_tso_hdr_page *hdr_page; 244 struct page **page_ptr; 245 struct tso_t tso; 246 247 /* if the packet is protected, then it must be CCMP or GCMP */ 248 iv_len = ieee80211_has_protected(hdr->frame_control) ? 249 IEEE80211_CCMP_HDR_LEN : 0; 250 251 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), 252 &dev_cmd->hdr, start_len, 0); 253 254 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb); 255 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb); 256 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len; 257 amsdu_pad = 0; 258 259 /* total amount of header we may need for this A-MSDU */ 260 hdr_room = DIV_ROUND_UP(total_len, mss) * 261 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len; 262 263 /* Our device supports 9 segments at most, it will fit in 1 page */ 264 hdr_page = get_page_hdr(trans, hdr_room); 265 if (!hdr_page) 266 return -ENOMEM; 267 268 get_page(hdr_page->page); 269 start_hdr = hdr_page->pos; 270 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs); 271 *page_ptr = hdr_page->page; 272 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len); 273 hdr_page->pos += iv_len; 274 275 /* 276 * Pull the ieee80211 header + IV to be able to use TSO core, 277 * we will restore it for the tx_status flow. 278 */ 279 skb_pull(skb, hdr_len + iv_len); 280 281 /* 282 * Remove the length of all the headers that we don't actually 283 * have in the MPDU by themselves, but that we duplicate into 284 * all the different MSDUs inside the A-MSDU. 285 */ 286 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen); 287 288 tso_start(skb, &tso); 289 290 while (total_len) { 291 /* this is the data left for this subframe */ 292 unsigned int data_left = min_t(unsigned int, mss, total_len); 293 struct sk_buff *csum_skb = NULL; 294 unsigned int tb_len; 295 dma_addr_t tb_phys; 296 struct tcphdr *tcph; 297 u8 *iph, *subf_hdrs_start = hdr_page->pos; 298 299 total_len -= data_left; 300 301 memset(hdr_page->pos, 0, amsdu_pad); 302 hdr_page->pos += amsdu_pad; 303 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen + 304 data_left)) & 0x3; 305 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr)); 306 hdr_page->pos += ETH_ALEN; 307 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr)); 308 hdr_page->pos += ETH_ALEN; 309 310 length = snap_ip_tcp_hdrlen + data_left; 311 *((__be16 *)hdr_page->pos) = cpu_to_be16(length); 312 hdr_page->pos += sizeof(length); 313 314 /* 315 * This will copy the SNAP as well which will be considered 316 * as MAC header. 317 */ 318 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len); 319 iph = hdr_page->pos + 8; 320 tcph = (void *)(iph + ip_hdrlen); 321 322 hdr_page->pos += snap_ip_tcp_hdrlen; 323 324 tb_len = hdr_page->pos - start_hdr; 325 tb_phys = dma_map_single(trans->dev, start_hdr, 326 tb_len, DMA_TO_DEVICE); 327 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 328 dev_kfree_skb(csum_skb); 329 goto out_err; 330 } 331 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len); 332 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr, tb_len); 333 /* add this subframe's headers' length to the tx_cmd */ 334 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start); 335 336 /* prepare the start_hdr for the next subframe */ 337 start_hdr = hdr_page->pos; 338 339 /* put the payload */ 340 while (data_left) { 341 tb_len = min_t(unsigned int, tso.size, data_left); 342 tb_phys = dma_map_single(trans->dev, tso.data, 343 tb_len, DMA_TO_DEVICE); 344 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) { 345 dev_kfree_skb(csum_skb); 346 goto out_err; 347 } 348 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb_len); 349 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data, 350 tb_len); 351 352 data_left -= tb_len; 353 tso_build_data(skb, &tso, tb_len); 354 } 355 } 356 357 /* re -add the WiFi header and IV */ 358 skb_push(skb, hdr_len + iv_len); 359 360 return 0; 361 362 out_err: 363 #endif 364 return -EINVAL; 365 } 366 367 static 368 struct iwl_tfh_tfd *iwl_pcie_gen2_build_tfd(struct iwl_trans *trans, 369 struct iwl_txq *txq, 370 struct iwl_device_cmd *dev_cmd, 371 struct sk_buff *skb, 372 struct iwl_cmd_meta *out_meta) 373 { 374 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 375 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 376 struct iwl_tfh_tfd *tfd = 377 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr); 378 dma_addr_t tb_phys; 379 bool amsdu; 380 int i, len, tb1_len, tb2_len, hdr_len; 381 void *tb1_addr; 382 383 memset(tfd, 0, sizeof(*tfd)); 384 385 amsdu = ieee80211_is_data_qos(hdr->frame_control) && 386 (*ieee80211_get_qos_ctl(hdr) & 387 IEEE80211_QOS_CTL_A_MSDU_PRESENT); 388 389 tb_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr); 390 /* The first TB points to bi-directional DMA data */ 391 if (!amsdu) 392 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 393 IWL_FIRST_TB_SIZE); 394 395 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, IWL_FIRST_TB_SIZE); 396 397 /* there must be data left over for TB1 or this code must be changed */ 398 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_gen2) < IWL_FIRST_TB_SIZE); 399 400 /* 401 * The second TB (tb1) points to the remainder of the TX command 402 * and the 802.11 header - dword aligned size 403 * (This calculation modifies the TX command, so do it before the 404 * setup of the first TB) 405 */ 406 len = sizeof(struct iwl_tx_cmd_gen2) + sizeof(struct iwl_cmd_header) + 407 ieee80211_hdrlen(hdr->frame_control) - IWL_FIRST_TB_SIZE; 408 409 /* do not align A-MSDU to dword as the subframe header aligns it */ 410 if (amsdu) 411 tb1_len = len; 412 else 413 tb1_len = ALIGN(len, 4); 414 415 /* map the data for TB1 */ 416 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE; 417 tb_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); 418 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 419 goto out_err; 420 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb1_len); 421 422 hdr_len = ieee80211_hdrlen(hdr->frame_control); 423 424 if (amsdu) { 425 if (!iwl_pcie_gen2_build_amsdu(trans, skb, tfd, 426 tb1_len + IWL_FIRST_TB_SIZE, 427 hdr_len, dev_cmd)) 428 goto out_err; 429 430 /* 431 * building the A-MSDU might have changed this data, so memcpy 432 * it now 433 */ 434 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr, 435 IWL_FIRST_TB_SIZE); 436 return tfd; 437 } 438 439 /* set up TFD's third entry to point to remainder of skb's head */ 440 tb2_len = skb_headlen(skb) - hdr_len; 441 442 if (tb2_len > 0) { 443 tb_phys = dma_map_single(trans->dev, skb->data + hdr_len, 444 tb2_len, DMA_TO_DEVICE); 445 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 446 goto out_err; 447 iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, tb2_len); 448 } 449 450 /* set up the remaining entries to point to the data */ 451 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 452 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 453 int tb_idx; 454 455 if (!skb_frag_size(frag)) 456 continue; 457 458 tb_phys = skb_frag_dma_map(trans->dev, frag, 0, 459 skb_frag_size(frag), DMA_TO_DEVICE); 460 461 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) 462 goto out_err; 463 tb_idx = iwl_pcie_gen2_set_tb(trans, tfd, tb_phys, 464 skb_frag_size(frag)); 465 466 out_meta->tbs |= BIT(tb_idx); 467 } 468 469 trace_iwlwifi_dev_tx(trans->dev, skb, tfd, sizeof(*tfd), &dev_cmd->hdr, 470 IWL_FIRST_TB_SIZE + tb1_len, hdr_len); 471 trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len); 472 473 return tfd; 474 475 out_err: 476 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 477 return NULL; 478 } 479 480 int iwl_trans_pcie_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 481 struct iwl_device_cmd *dev_cmd, int txq_id) 482 { 483 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 484 struct iwl_tx_cmd_gen2 *tx_cmd = (void *)dev_cmd->payload; 485 struct iwl_cmd_meta *out_meta; 486 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 487 void *tfd; 488 489 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), 490 "TX on unused queue %d\n", txq_id)) 491 return -EINVAL; 492 493 if (skb_is_nonlinear(skb) && 494 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) && 495 __skb_linearize(skb)) 496 return -ENOMEM; 497 498 spin_lock(&txq->lock); 499 500 /* Set up driver data for this TFD */ 501 txq->entries[txq->write_ptr].skb = skb; 502 txq->entries[txq->write_ptr].cmd = dev_cmd; 503 504 dev_cmd->hdr.sequence = 505 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | 506 INDEX_TO_SEQ(txq->write_ptr))); 507 508 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 509 out_meta = &txq->entries[txq->write_ptr].meta; 510 out_meta->flags = 0; 511 512 tfd = iwl_pcie_gen2_build_tfd(trans, txq, dev_cmd, skb, out_meta); 513 if (!tfd) { 514 spin_unlock(&txq->lock); 515 return -1; 516 } 517 518 /* Set up entry for this TFD in Tx byte-count array */ 519 iwl_pcie_gen2_update_byte_tbl(txq, le16_to_cpu(tx_cmd->len), 520 iwl_pcie_gen2_get_num_tbs(trans, tfd)); 521 522 /* start timer if queue currently empty */ 523 if (txq->read_ptr == txq->write_ptr) { 524 if (txq->wd_timeout) 525 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 526 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id); 527 iwl_trans_ref(trans); 528 } 529 530 /* Tell device the write index *just past* this latest filled TFD */ 531 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 532 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq); 533 if (iwl_queue_space(txq) < txq->high_mark) 534 iwl_stop_queue(trans, txq); 535 536 /* 537 * At this point the frame is "transmitted" successfully 538 * and we will get a TX status notification eventually. 539 */ 540 spin_unlock(&txq->lock); 541 return 0; 542 } 543 544 /*************** HOST COMMAND QUEUE FUNCTIONS *****/ 545 546 /* 547 * iwl_pcie_gen2_enqueue_hcmd - enqueue a uCode command 548 * @priv: device private data point 549 * @cmd: a pointer to the ucode command structure 550 * 551 * The function returns < 0 values to indicate the operation 552 * failed. On success, it returns the index (>= 0) of command in the 553 * command queue. 554 */ 555 static int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans, 556 struct iwl_host_cmd *cmd) 557 { 558 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 559 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 560 struct iwl_device_cmd *out_cmd; 561 struct iwl_cmd_meta *out_meta; 562 unsigned long flags; 563 void *dup_buf = NULL; 564 dma_addr_t phys_addr; 565 int idx, i, cmd_pos; 566 u16 copy_size, cmd_size, tb0_size; 567 bool had_nocopy = false; 568 u8 group_id = iwl_cmd_groupid(cmd->id); 569 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; 570 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; 571 struct iwl_tfh_tfd *tfd = 572 iwl_pcie_get_tfd(trans_pcie, txq, txq->write_ptr); 573 574 memset(tfd, 0, sizeof(*tfd)); 575 576 copy_size = sizeof(struct iwl_cmd_header_wide); 577 cmd_size = sizeof(struct iwl_cmd_header_wide); 578 579 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 580 cmddata[i] = cmd->data[i]; 581 cmdlen[i] = cmd->len[i]; 582 583 if (!cmd->len[i]) 584 continue; 585 586 /* need at least IWL_FIRST_TB_SIZE copied */ 587 if (copy_size < IWL_FIRST_TB_SIZE) { 588 int copy = IWL_FIRST_TB_SIZE - copy_size; 589 590 if (copy > cmdlen[i]) 591 copy = cmdlen[i]; 592 cmdlen[i] -= copy; 593 cmddata[i] += copy; 594 copy_size += copy; 595 } 596 597 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { 598 had_nocopy = true; 599 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { 600 idx = -EINVAL; 601 goto free_dup_buf; 602 } 603 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { 604 /* 605 * This is also a chunk that isn't copied 606 * to the static buffer so set had_nocopy. 607 */ 608 had_nocopy = true; 609 610 /* only allowed once */ 611 if (WARN_ON(dup_buf)) { 612 idx = -EINVAL; 613 goto free_dup_buf; 614 } 615 616 dup_buf = kmemdup(cmddata[i], cmdlen[i], 617 GFP_ATOMIC); 618 if (!dup_buf) 619 return -ENOMEM; 620 } else { 621 /* NOCOPY must not be followed by normal! */ 622 if (WARN_ON(had_nocopy)) { 623 idx = -EINVAL; 624 goto free_dup_buf; 625 } 626 copy_size += cmdlen[i]; 627 } 628 cmd_size += cmd->len[i]; 629 } 630 631 /* 632 * If any of the command structures end up being larger than the 633 * TFD_MAX_PAYLOAD_SIZE and they aren't dynamically allocated into 634 * separate TFDs, then we will need to increase the size of the buffers 635 */ 636 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, 637 "Command %s (%#x) is too large (%d bytes)\n", 638 iwl_get_cmd_string(trans, cmd->id), cmd->id, copy_size)) { 639 idx = -EINVAL; 640 goto free_dup_buf; 641 } 642 643 spin_lock_bh(&txq->lock); 644 645 if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { 646 spin_unlock_bh(&txq->lock); 647 648 IWL_ERR(trans, "No space in command queue\n"); 649 iwl_op_mode_cmd_queue_full(trans->op_mode); 650 idx = -ENOSPC; 651 goto free_dup_buf; 652 } 653 654 idx = get_cmd_index(txq, txq->write_ptr); 655 out_cmd = txq->entries[idx].cmd; 656 out_meta = &txq->entries[idx].meta; 657 658 /* re-initialize to NULL */ 659 memset(out_meta, 0, sizeof(*out_meta)); 660 if (cmd->flags & CMD_WANT_SKB) 661 out_meta->source = cmd; 662 663 /* set up the header */ 664 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id); 665 out_cmd->hdr_wide.group_id = group_id; 666 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id); 667 out_cmd->hdr_wide.length = 668 cpu_to_le16(cmd_size - sizeof(struct iwl_cmd_header_wide)); 669 out_cmd->hdr_wide.reserved = 0; 670 out_cmd->hdr_wide.sequence = 671 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | 672 INDEX_TO_SEQ(txq->write_ptr)); 673 674 cmd_pos = sizeof(struct iwl_cmd_header_wide); 675 copy_size = sizeof(struct iwl_cmd_header_wide); 676 677 /* and copy the data that needs to be copied */ 678 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 679 int copy; 680 681 if (!cmd->len[i]) 682 continue; 683 684 /* copy everything if not nocopy/dup */ 685 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 686 IWL_HCMD_DFL_DUP))) { 687 copy = cmd->len[i]; 688 689 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 690 cmd_pos += copy; 691 copy_size += copy; 692 continue; 693 } 694 695 /* 696 * Otherwise we need at least IWL_FIRST_TB_SIZE copied 697 * in total (for bi-directional DMA), but copy up to what 698 * we can fit into the payload for debug dump purposes. 699 */ 700 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]); 701 702 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); 703 cmd_pos += copy; 704 705 /* However, treat copy_size the proper way, we need it below */ 706 if (copy_size < IWL_FIRST_TB_SIZE) { 707 copy = IWL_FIRST_TB_SIZE - copy_size; 708 709 if (copy > cmd->len[i]) 710 copy = cmd->len[i]; 711 copy_size += copy; 712 } 713 } 714 715 IWL_DEBUG_HC(trans, 716 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", 717 iwl_get_cmd_string(trans, cmd->id), group_id, 718 out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), 719 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue); 720 721 /* start the TFD with the minimum copy bytes */ 722 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE); 723 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size); 724 iwl_pcie_gen2_set_tb(trans, tfd, iwl_pcie_get_first_tb_dma(txq, idx), 725 tb0_size); 726 727 /* map first command fragment, if any remains */ 728 if (copy_size > tb0_size) { 729 phys_addr = dma_map_single(trans->dev, 730 ((u8 *)&out_cmd->hdr) + tb0_size, 731 copy_size - tb0_size, 732 DMA_TO_DEVICE); 733 if (dma_mapping_error(trans->dev, phys_addr)) { 734 idx = -ENOMEM; 735 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 736 goto out; 737 } 738 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, 739 copy_size - tb0_size); 740 } 741 742 /* map the remaining (adjusted) nocopy/dup fragments */ 743 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { 744 const void *data = cmddata[i]; 745 746 if (!cmdlen[i]) 747 continue; 748 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | 749 IWL_HCMD_DFL_DUP))) 750 continue; 751 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) 752 data = dup_buf; 753 phys_addr = dma_map_single(trans->dev, (void *)data, 754 cmdlen[i], DMA_TO_DEVICE); 755 if (dma_mapping_error(trans->dev, phys_addr)) { 756 idx = -ENOMEM; 757 iwl_pcie_gen2_tfd_unmap(trans, out_meta, tfd); 758 goto out; 759 } 760 iwl_pcie_gen2_set_tb(trans, tfd, phys_addr, cmdlen[i]); 761 } 762 763 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE); 764 out_meta->flags = cmd->flags; 765 if (WARN_ON_ONCE(txq->entries[idx].free_buf)) 766 kzfree(txq->entries[idx].free_buf); 767 txq->entries[idx].free_buf = dup_buf; 768 769 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide); 770 771 /* start timer if queue currently empty */ 772 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) 773 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout); 774 775 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 776 if (!(cmd->flags & CMD_SEND_IN_IDLE) && 777 !trans_pcie->ref_cmd_in_flight) { 778 trans_pcie->ref_cmd_in_flight = true; 779 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n"); 780 iwl_trans_ref(trans); 781 } 782 /* Increment and update queue's write index */ 783 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr); 784 iwl_pcie_gen2_txq_inc_wr_ptr(trans, txq); 785 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 786 787 out: 788 spin_unlock_bh(&txq->lock); 789 free_dup_buf: 790 if (idx < 0) 791 kfree(dup_buf); 792 return idx; 793 } 794 795 #define HOST_COMPLETE_TIMEOUT (2 * HZ) 796 797 static int iwl_pcie_gen2_send_hcmd_sync(struct iwl_trans *trans, 798 struct iwl_host_cmd *cmd) 799 { 800 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 801 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id); 802 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue]; 803 int cmd_idx; 804 int ret; 805 806 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str); 807 808 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE, 809 &trans->status), 810 "Command %s: a command is already active!\n", cmd_str)) 811 return -EIO; 812 813 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str); 814 815 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) { 816 ret = wait_event_timeout(trans_pcie->d0i3_waitq, 817 pm_runtime_active(&trans_pcie->pci_dev->dev), 818 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT)); 819 if (!ret) { 820 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n"); 821 return -ETIMEDOUT; 822 } 823 } 824 825 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd); 826 if (cmd_idx < 0) { 827 ret = cmd_idx; 828 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 829 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n", 830 cmd_str, ret); 831 return ret; 832 } 833 834 ret = wait_event_timeout(trans_pcie->wait_command_queue, 835 !test_bit(STATUS_SYNC_HCMD_ACTIVE, 836 &trans->status), 837 HOST_COMPLETE_TIMEOUT); 838 if (!ret) { 839 IWL_ERR(trans, "Error sending %s: time out after %dms.\n", 840 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); 841 842 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n", 843 txq->read_ptr, txq->write_ptr); 844 845 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 846 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", 847 cmd_str); 848 ret = -ETIMEDOUT; 849 850 iwl_force_nmi(trans); 851 iwl_trans_fw_error(trans); 852 853 goto cancel; 854 } 855 856 if (test_bit(STATUS_FW_ERROR, &trans->status)) { 857 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str); 858 dump_stack(); 859 ret = -EIO; 860 goto cancel; 861 } 862 863 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 864 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 865 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); 866 ret = -ERFKILL; 867 goto cancel; 868 } 869 870 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { 871 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str); 872 ret = -EIO; 873 goto cancel; 874 } 875 876 return 0; 877 878 cancel: 879 if (cmd->flags & CMD_WANT_SKB) { 880 /* 881 * Cancel the CMD_WANT_SKB flag for the cmd in the 882 * TX cmd queue. Otherwise in case the cmd comes 883 * in later, it will possibly set an invalid 884 * address (cmd->meta.source). 885 */ 886 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; 887 } 888 889 if (cmd->resp_pkt) { 890 iwl_free_resp(cmd); 891 cmd->resp_pkt = NULL; 892 } 893 894 return ret; 895 } 896 897 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 898 struct iwl_host_cmd *cmd) 899 { 900 if (!(cmd->flags & CMD_SEND_IN_RFKILL) && 901 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) { 902 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", 903 cmd->id); 904 return -ERFKILL; 905 } 906 907 if (cmd->flags & CMD_ASYNC) { 908 int ret; 909 910 /* An asynchronous command can not expect an SKB to be set. */ 911 if (WARN_ON(cmd->flags & CMD_WANT_SKB)) 912 return -EINVAL; 913 914 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd); 915 if (ret < 0) { 916 IWL_ERR(trans, 917 "Error sending %s: enqueue_hcmd failed: %d\n", 918 iwl_get_cmd_string(trans, cmd->id), ret); 919 return ret; 920 } 921 return 0; 922 } 923 924 return iwl_pcie_gen2_send_hcmd_sync(trans, cmd); 925 } 926 927 /* 928 * iwl_pcie_gen2_txq_unmap - Unmap any remaining DMA mappings and free skb's 929 */ 930 void iwl_pcie_gen2_txq_unmap(struct iwl_trans *trans, int txq_id) 931 { 932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 933 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 934 935 spin_lock_bh(&txq->lock); 936 while (txq->write_ptr != txq->read_ptr) { 937 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", 938 txq_id, txq->read_ptr); 939 940 iwl_pcie_gen2_free_tfd(trans, txq); 941 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr); 942 943 if (txq->read_ptr == txq->write_ptr) { 944 unsigned long flags; 945 946 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 947 if (txq_id != trans_pcie->cmd_queue) { 948 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n", 949 txq->id); 950 iwl_trans_unref(trans); 951 } else if (trans_pcie->ref_cmd_in_flight) { 952 trans_pcie->ref_cmd_in_flight = false; 953 IWL_DEBUG_RPM(trans, 954 "clear ref_cmd_in_flight\n"); 955 iwl_trans_unref(trans); 956 } 957 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 958 } 959 } 960 spin_unlock_bh(&txq->lock); 961 962 /* just in case - this queue may have been stopped */ 963 iwl_wake_queue(trans, txq); 964 } 965 966 static void iwl_pcie_gen2_txq_free_memory(struct iwl_trans *trans, 967 struct iwl_txq *txq) 968 { 969 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 970 struct device *dev = trans->dev; 971 972 /* De-alloc circular buffer of TFDs */ 973 if (txq->tfds) { 974 dma_free_coherent(dev, 975 trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX, 976 txq->tfds, txq->dma_addr); 977 dma_free_coherent(dev, 978 sizeof(*txq->first_tb_bufs) * txq->n_window, 979 txq->first_tb_bufs, txq->first_tb_dma); 980 } 981 982 kfree(txq->entries); 983 iwl_pcie_free_dma_ptr(trans, &txq->bc_tbl); 984 kfree(txq); 985 } 986 987 /* 988 * iwl_pcie_txq_free - Deallocate DMA queue. 989 * @txq: Transmit queue to deallocate. 990 * 991 * Empty queue by removing and destroying all BD's. 992 * Free all buffers. 993 * 0-fill, but do not free "txq" descriptor structure. 994 */ 995 static void iwl_pcie_gen2_txq_free(struct iwl_trans *trans, int txq_id) 996 { 997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 998 struct iwl_txq *txq = trans_pcie->txq[txq_id]; 999 int i; 1000 1001 if (WARN_ON(!txq)) 1002 return; 1003 1004 iwl_pcie_gen2_txq_unmap(trans, txq_id); 1005 1006 /* De-alloc array of command/tx buffers */ 1007 if (txq_id == trans_pcie->cmd_queue) 1008 for (i = 0; i < txq->n_window; i++) { 1009 kzfree(txq->entries[i].cmd); 1010 kzfree(txq->entries[i].free_buf); 1011 } 1012 del_timer_sync(&txq->stuck_timer); 1013 1014 iwl_pcie_gen2_txq_free_memory(trans, txq); 1015 1016 trans_pcie->txq[txq_id] = NULL; 1017 1018 clear_bit(txq_id, trans_pcie->queue_used); 1019 } 1020 1021 int iwl_trans_pcie_dyn_txq_alloc(struct iwl_trans *trans, 1022 struct iwl_tx_queue_cfg_cmd *cmd, 1023 int cmd_id, 1024 unsigned int timeout) 1025 { 1026 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1027 struct iwl_tx_queue_cfg_rsp *rsp; 1028 struct iwl_txq *txq; 1029 struct iwl_host_cmd hcmd = { 1030 .id = cmd_id, 1031 .len = { sizeof(*cmd) }, 1032 .data = { cmd, }, 1033 .flags = CMD_WANT_SKB, 1034 }; 1035 int ret, qid; 1036 1037 txq = kzalloc(sizeof(*txq), GFP_KERNEL); 1038 if (!txq) 1039 return -ENOMEM; 1040 ret = iwl_pcie_alloc_dma_ptr(trans, &txq->bc_tbl, 1041 sizeof(struct iwlagn_scd_bc_tbl)); 1042 if (ret) { 1043 IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); 1044 kfree(txq); 1045 return -ENOMEM; 1046 } 1047 1048 ret = iwl_pcie_txq_alloc(trans, txq, TFD_TX_CMD_SLOTS, false); 1049 if (ret) { 1050 IWL_ERR(trans, "Tx queue alloc failed\n"); 1051 goto error; 1052 } 1053 ret = iwl_pcie_txq_init(trans, txq, TFD_TX_CMD_SLOTS, false); 1054 if (ret) { 1055 IWL_ERR(trans, "Tx queue init failed\n"); 1056 goto error; 1057 } 1058 1059 txq->wd_timeout = msecs_to_jiffies(timeout); 1060 1061 cmd->tfdq_addr = cpu_to_le64(txq->dma_addr); 1062 cmd->byte_cnt_addr = cpu_to_le64(txq->bc_tbl.dma); 1063 cmd->cb_size = cpu_to_le32(TFD_QUEUE_CB_SIZE(TFD_QUEUE_SIZE_MAX)); 1064 1065 ret = iwl_trans_send_cmd(trans, &hcmd); 1066 if (ret) 1067 goto error; 1068 1069 if (WARN_ON(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp))) { 1070 ret = -EINVAL; 1071 goto error_free_resp; 1072 } 1073 1074 rsp = (void *)hcmd.resp_pkt->data; 1075 qid = le16_to_cpu(rsp->queue_number); 1076 1077 if (qid >= ARRAY_SIZE(trans_pcie->txq)) { 1078 WARN_ONCE(1, "queue index %d unsupported", qid); 1079 ret = -EIO; 1080 goto error_free_resp; 1081 } 1082 1083 if (test_and_set_bit(qid, trans_pcie->queue_used)) { 1084 WARN_ONCE(1, "queue %d already used", qid); 1085 ret = -EIO; 1086 goto error_free_resp; 1087 } 1088 1089 txq->id = qid; 1090 trans_pcie->txq[qid] = txq; 1091 1092 /* Place first TFD at index corresponding to start sequence number */ 1093 txq->read_ptr = le16_to_cpu(rsp->write_pointer); 1094 txq->write_ptr = le16_to_cpu(rsp->write_pointer); 1095 iwl_write_direct32(trans, HBUS_TARG_WRPTR, 1096 (txq->write_ptr) | (qid << 16)); 1097 IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d\n", qid); 1098 1099 iwl_free_resp(&hcmd); 1100 return qid; 1101 1102 error_free_resp: 1103 iwl_free_resp(&hcmd); 1104 error: 1105 iwl_pcie_gen2_txq_free_memory(trans, txq); 1106 return ret; 1107 } 1108 1109 void iwl_trans_pcie_dyn_txq_free(struct iwl_trans *trans, int queue) 1110 { 1111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1112 1113 /* 1114 * Upon HW Rfkill - we stop the device, and then stop the queues 1115 * in the op_mode. Just for the sake of the simplicity of the op_mode, 1116 * allow the op_mode to call txq_disable after it already called 1117 * stop_device. 1118 */ 1119 if (!test_and_clear_bit(queue, trans_pcie->queue_used)) { 1120 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status), 1121 "queue %d not used", queue); 1122 return; 1123 } 1124 1125 iwl_pcie_gen2_txq_unmap(trans, queue); 1126 1127 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", queue); 1128 } 1129 1130 void iwl_pcie_gen2_tx_free(struct iwl_trans *trans) 1131 { 1132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1133 int i; 1134 1135 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 1136 1137 /* Free all TX queues */ 1138 for (i = 0; i < ARRAY_SIZE(trans_pcie->txq); i++) { 1139 if (!trans_pcie->txq[i]) 1140 continue; 1141 1142 iwl_pcie_gen2_txq_free(trans, i); 1143 } 1144 } 1145 1146 int iwl_pcie_gen2_tx_init(struct iwl_trans *trans) 1147 { 1148 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1149 struct iwl_txq *cmd_queue; 1150 int txq_id = trans_pcie->cmd_queue, ret; 1151 1152 /* alloc and init the command queue */ 1153 if (!trans_pcie->txq[txq_id]) { 1154 cmd_queue = kzalloc(sizeof(*cmd_queue), GFP_KERNEL); 1155 if (!cmd_queue) { 1156 IWL_ERR(trans, "Not enough memory for command queue\n"); 1157 return -ENOMEM; 1158 } 1159 trans_pcie->txq[txq_id] = cmd_queue; 1160 ret = iwl_pcie_txq_alloc(trans, cmd_queue, TFD_CMD_SLOTS, true); 1161 if (ret) { 1162 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); 1163 goto error; 1164 } 1165 } else { 1166 cmd_queue = trans_pcie->txq[txq_id]; 1167 } 1168 1169 ret = iwl_pcie_txq_init(trans, cmd_queue, TFD_CMD_SLOTS, true); 1170 if (ret) { 1171 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); 1172 goto error; 1173 } 1174 trans_pcie->txq[txq_id]->id = txq_id; 1175 set_bit(txq_id, trans_pcie->queue_used); 1176 1177 return 0; 1178 1179 error: 1180 iwl_pcie_gen2_tx_free(trans); 1181 return ret; 1182 } 1183 1184