1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/pci.h> 65 #include <linux/pci-aspm.h> 66 #include <linux/interrupt.h> 67 #include <linux/debugfs.h> 68 #include <linux/sched.h> 69 #include <linux/bitops.h> 70 #include <linux/gfp.h> 71 #include <linux/vmalloc.h> 72 #include <linux/pm_runtime.h> 73 #include <linux/module.h> 74 #include <linux/wait.h> 75 76 #include "iwl-drv.h" 77 #include "iwl-trans.h" 78 #include "iwl-csr.h" 79 #include "iwl-prph.h" 80 #include "iwl-scd.h" 81 #include "iwl-agn-hw.h" 82 #include "fw/error-dump.h" 83 #include "fw/dbg.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92 { 93 #define PCI_DUMP_SIZE 352 94 #define PCI_MEM_DUMP_SIZE 64 95 #define PCI_PARENT_DUMP_SIZE 524 96 #define PREFIX_LEN 32 97 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 98 struct pci_dev *pdev = trans_pcie->pci_dev; 99 u32 i, pos, alloc_size, *ptr, *buf; 100 char *prefix; 101 102 if (trans_pcie->pcie_dbg_dumped_once) 103 return; 104 105 /* Should be a multiple of 4 */ 106 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 107 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 108 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 109 110 /* Alloc a max size buffer */ 111 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 112 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 113 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 114 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 115 116 buf = kmalloc(alloc_size, GFP_ATOMIC); 117 if (!buf) 118 return; 119 prefix = (char *)buf + alloc_size - PREFIX_LEN; 120 121 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 122 123 /* Print wifi device registers */ 124 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 125 IWL_ERR(trans, "iwlwifi device config registers:\n"); 126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127 if (pci_read_config_dword(pdev, i, ptr)) 128 goto err_read; 129 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 130 131 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 132 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 133 *ptr = iwl_read32(trans, i); 134 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 135 136 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137 if (pos) { 138 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 139 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 140 if (pci_read_config_dword(pdev, pos + i, ptr)) 141 goto err_read; 142 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 143 32, 4, buf, i, 0); 144 } 145 146 /* Print parent device registers next */ 147 if (!pdev->bus->self) 148 goto out; 149 150 pdev = pdev->bus->self; 151 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 152 153 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 154 pci_name(pdev)); 155 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 156 if (pci_read_config_dword(pdev, i, ptr)) 157 goto err_read; 158 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 159 160 /* Print root port AER registers */ 161 pos = 0; 162 pdev = pcie_find_root_port(pdev); 163 if (pdev) 164 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 165 if (pos) { 166 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 167 pci_name(pdev)); 168 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 169 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 170 if (pci_read_config_dword(pdev, pos + i, ptr)) 171 goto err_read; 172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 173 4, buf, i, 0); 174 } 175 goto out; 176 177 err_read: 178 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 179 IWL_ERR(trans, "Read failed at 0x%X\n", i); 180 out: 181 trans_pcie->pcie_dbg_dumped_once = 1; 182 kfree(buf); 183 } 184 185 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 186 { 187 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 188 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 189 BIT(trans->cfg->csr->flag_sw_reset)); 190 usleep_range(5000, 6000); 191 } 192 193 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 194 { 195 int i; 196 197 for (i = 0; i < trans->dbg.num_blocks; i++) { 198 dma_free_coherent(trans->dev, trans->dbg.fw_mon[i].size, 199 trans->dbg.fw_mon[i].block, 200 trans->dbg.fw_mon[i].physical); 201 trans->dbg.fw_mon[i].block = NULL; 202 trans->dbg.fw_mon[i].physical = 0; 203 trans->dbg.fw_mon[i].size = 0; 204 trans->dbg.num_blocks--; 205 } 206 } 207 208 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 209 u8 max_power, u8 min_power) 210 { 211 void *cpu_addr = NULL; 212 dma_addr_t phys = 0; 213 u32 size = 0; 214 u8 power; 215 216 for (power = max_power; power >= min_power; power--) { 217 size = BIT(power); 218 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 219 GFP_KERNEL | __GFP_NOWARN | 220 __GFP_ZERO | __GFP_COMP); 221 if (!cpu_addr) 222 continue; 223 224 IWL_INFO(trans, 225 "Allocated 0x%08x bytes for firmware monitor.\n", 226 size); 227 break; 228 } 229 230 if (WARN_ON_ONCE(!cpu_addr)) 231 return; 232 233 if (power != max_power) 234 IWL_ERR(trans, 235 "Sorry - debug buffer is only %luK while you requested %luK\n", 236 (unsigned long)BIT(power - 10), 237 (unsigned long)BIT(max_power - 10)); 238 239 trans->dbg.fw_mon[trans->dbg.num_blocks].block = cpu_addr; 240 trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys; 241 trans->dbg.fw_mon[trans->dbg.num_blocks].size = size; 242 trans->dbg.num_blocks++; 243 } 244 245 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 246 { 247 if (!max_power) { 248 /* default max_power is maximum */ 249 max_power = 26; 250 } else { 251 max_power += 11; 252 } 253 254 if (WARN(max_power > 26, 255 "External buffer size for monitor is too big %d, check the FW TLV\n", 256 max_power)) 257 return; 258 259 /* 260 * This function allocats the default fw monitor. 261 * The optional additional ones will be allocated in runtime 262 */ 263 if (trans->dbg.num_blocks) 264 return; 265 266 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 267 } 268 269 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 270 { 271 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 272 ((reg & 0x0000ffff) | (2 << 28))); 273 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 274 } 275 276 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 277 { 278 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 279 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 280 ((reg & 0x0000ffff) | (3 << 28))); 281 } 282 283 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 284 { 285 if (trans->cfg->apmg_not_supported) 286 return; 287 288 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 289 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 290 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 291 ~APMG_PS_CTRL_MSK_PWR_SRC); 292 else 293 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 294 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 295 ~APMG_PS_CTRL_MSK_PWR_SRC); 296 } 297 298 /* PCI registers */ 299 #define PCI_CFG_RETRY_TIMEOUT 0x041 300 301 void iwl_pcie_apm_config(struct iwl_trans *trans) 302 { 303 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 304 u16 lctl; 305 u16 cap; 306 307 /* 308 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 309 * Check if BIOS (or OS) enabled L1-ASPM on this device. 310 * If so (likely), disable L0S, so device moves directly L0->L1; 311 * costs negligible amount of power savings. 312 * If not (unlikely), enable L0S, so there is at least some 313 * power savings, even without L1. 314 */ 315 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 316 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 317 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 318 else 319 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 320 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 321 322 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 323 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 324 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 325 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 326 trans->ltr_enabled ? "En" : "Dis"); 327 } 328 329 /* 330 * Start up NIC's basic functionality after it has been reset 331 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 332 * NOTE: This does not load uCode nor start the embedded processor 333 */ 334 static int iwl_pcie_apm_init(struct iwl_trans *trans) 335 { 336 int ret; 337 338 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 339 340 /* 341 * Use "set_bit" below rather than "write", to preserve any hardware 342 * bits already set by default after reset. 343 */ 344 345 /* Disable L0S exit timer (platform NMI Work/Around) */ 346 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 347 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 348 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 349 350 /* 351 * Disable L0s without affecting L1; 352 * don't wait for ICH L0s (ICH bug W/A) 353 */ 354 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 355 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 356 357 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 358 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 359 360 /* 361 * Enable HAP INTA (interrupt from management bus) to 362 * wake device's PCI Express link L1a -> L0s 363 */ 364 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 365 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 366 367 iwl_pcie_apm_config(trans); 368 369 /* Configure analog phase-lock-loop before activating to D0A */ 370 if (trans->cfg->base_params->pll_cfg) 371 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 372 373 ret = iwl_finish_nic_init(trans); 374 if (ret) 375 return ret; 376 377 if (trans->cfg->host_interrupt_operation_mode) { 378 /* 379 * This is a bit of an abuse - This is needed for 7260 / 3160 380 * only check host_interrupt_operation_mode even if this is 381 * not related to host_interrupt_operation_mode. 382 * 383 * Enable the oscillator to count wake up time for L1 exit. This 384 * consumes slightly more power (100uA) - but allows to be sure 385 * that we wake up from L1 on time. 386 * 387 * This looks weird: read twice the same register, discard the 388 * value, set a bit, and yet again, read that same register 389 * just to discard the value. But that's the way the hardware 390 * seems to like it. 391 */ 392 iwl_read_prph(trans, OSC_CLK); 393 iwl_read_prph(trans, OSC_CLK); 394 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 395 iwl_read_prph(trans, OSC_CLK); 396 iwl_read_prph(trans, OSC_CLK); 397 } 398 399 /* 400 * Enable DMA clock and wait for it to stabilize. 401 * 402 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 403 * bits do not disable clocks. This preserves any hardware 404 * bits already set by default in "CLK_CTRL_REG" after reset. 405 */ 406 if (!trans->cfg->apmg_not_supported) { 407 iwl_write_prph(trans, APMG_CLK_EN_REG, 408 APMG_CLK_VAL_DMA_CLK_RQT); 409 udelay(20); 410 411 /* Disable L1-Active */ 412 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 413 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 414 415 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 416 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 417 APMG_RTC_INT_STT_RFKILL); 418 } 419 420 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 421 422 return 0; 423 } 424 425 /* 426 * Enable LP XTAL to avoid HW bug where device may consume much power if 427 * FW is not loaded after device reset. LP XTAL is disabled by default 428 * after device HW reset. Do it only if XTAL is fed by internal source. 429 * Configure device's "persistence" mode to avoid resetting XTAL again when 430 * SHRD_HW_RST occurs in S3. 431 */ 432 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 433 { 434 int ret; 435 u32 apmg_gp1_reg; 436 u32 apmg_xtal_cfg_reg; 437 u32 dl_cfg_reg; 438 439 /* Force XTAL ON */ 440 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 441 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 442 443 iwl_trans_pcie_sw_reset(trans); 444 445 ret = iwl_finish_nic_init(trans); 446 if (WARN_ON(ret)) { 447 /* Release XTAL ON request */ 448 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 449 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 450 return; 451 } 452 453 /* 454 * Clear "disable persistence" to avoid LP XTAL resetting when 455 * SHRD_HW_RST is applied in S3. 456 */ 457 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 458 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 459 460 /* 461 * Force APMG XTAL to be active to prevent its disabling by HW 462 * caused by APMG idle state. 463 */ 464 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 465 SHR_APMG_XTAL_CFG_REG); 466 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 467 apmg_xtal_cfg_reg | 468 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 469 470 iwl_trans_pcie_sw_reset(trans); 471 472 /* Enable LP XTAL by indirect access through CSR */ 473 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 474 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 475 SHR_APMG_GP1_WF_XTAL_LP_EN | 476 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 477 478 /* Clear delay line clock power up */ 479 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 480 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 481 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 482 483 /* 484 * Enable persistence mode to avoid LP XTAL resetting when 485 * SHRD_HW_RST is applied in S3. 486 */ 487 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 488 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 489 490 /* 491 * Clear "initialization complete" bit to move adapter from 492 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 493 */ 494 iwl_clear_bit(trans, CSR_GP_CNTRL, 495 BIT(trans->cfg->csr->flag_init_done)); 496 497 /* Activates XTAL resources monitor */ 498 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 499 CSR_MONITOR_XTAL_RESOURCES); 500 501 /* Release XTAL ON request */ 502 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 503 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 504 udelay(10); 505 506 /* Release APMG XTAL */ 507 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 508 apmg_xtal_cfg_reg & 509 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 510 } 511 512 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 513 { 514 int ret; 515 516 /* stop device's busmaster DMA activity */ 517 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 518 BIT(trans->cfg->csr->flag_stop_master)); 519 520 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 521 BIT(trans->cfg->csr->flag_master_dis), 522 BIT(trans->cfg->csr->flag_master_dis), 100); 523 if (ret < 0) 524 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 525 526 IWL_DEBUG_INFO(trans, "stop master\n"); 527 } 528 529 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 530 { 531 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 532 533 if (op_mode_leave) { 534 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 535 iwl_pcie_apm_init(trans); 536 537 /* inform ME that we are leaving */ 538 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 539 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 540 APMG_PCIDEV_STT_VAL_WAKE_ME); 541 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 542 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543 CSR_RESET_LINK_PWR_MGMT_DISABLED); 544 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 545 CSR_HW_IF_CONFIG_REG_PREPARE | 546 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 547 mdelay(1); 548 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 549 CSR_RESET_LINK_PWR_MGMT_DISABLED); 550 } 551 mdelay(5); 552 } 553 554 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 555 556 /* Stop device's DMA activity */ 557 iwl_pcie_apm_stop_master(trans); 558 559 if (trans->cfg->lp_xtal_workaround) { 560 iwl_pcie_apm_lp_xtal_enable(trans); 561 return; 562 } 563 564 iwl_trans_pcie_sw_reset(trans); 565 566 /* 567 * Clear "initialization complete" bit to move adapter from 568 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 569 */ 570 iwl_clear_bit(trans, CSR_GP_CNTRL, 571 BIT(trans->cfg->csr->flag_init_done)); 572 } 573 574 static int iwl_pcie_nic_init(struct iwl_trans *trans) 575 { 576 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 577 int ret; 578 579 /* nic_init */ 580 spin_lock(&trans_pcie->irq_lock); 581 ret = iwl_pcie_apm_init(trans); 582 spin_unlock(&trans_pcie->irq_lock); 583 584 if (ret) 585 return ret; 586 587 iwl_pcie_set_pwr(trans, false); 588 589 iwl_op_mode_nic_config(trans->op_mode); 590 591 /* Allocate the RX queue, or reset if it is already allocated */ 592 iwl_pcie_rx_init(trans); 593 594 /* Allocate or reset and init all Tx and Command queues */ 595 if (iwl_pcie_tx_init(trans)) 596 return -ENOMEM; 597 598 if (trans->cfg->base_params->shadow_reg_enable) { 599 /* enable shadow regs in HW */ 600 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 601 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 602 } 603 604 return 0; 605 } 606 607 #define HW_READY_TIMEOUT (50) 608 609 /* Note: returns poll_bit return value, which is >= 0 if success */ 610 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 611 { 612 int ret; 613 614 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 615 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 616 617 /* See if we got it */ 618 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 619 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 620 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 621 HW_READY_TIMEOUT); 622 623 if (ret >= 0) 624 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 625 626 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 627 return ret; 628 } 629 630 /* Note: returns standard 0/-ERROR code */ 631 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 632 { 633 int ret; 634 int t = 0; 635 int iter; 636 637 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 638 639 ret = iwl_pcie_set_hw_ready(trans); 640 /* If the card is ready, exit 0 */ 641 if (ret >= 0) 642 return 0; 643 644 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 645 CSR_RESET_LINK_PWR_MGMT_DISABLED); 646 usleep_range(1000, 2000); 647 648 for (iter = 0; iter < 10; iter++) { 649 /* If HW is not ready, prepare the conditions to check again */ 650 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 651 CSR_HW_IF_CONFIG_REG_PREPARE); 652 653 do { 654 ret = iwl_pcie_set_hw_ready(trans); 655 if (ret >= 0) 656 return 0; 657 658 usleep_range(200, 1000); 659 t += 200; 660 } while (t < 150000); 661 msleep(25); 662 } 663 664 IWL_ERR(trans, "Couldn't prepare the card\n"); 665 666 return ret; 667 } 668 669 /* 670 * ucode 671 */ 672 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 673 u32 dst_addr, dma_addr_t phy_addr, 674 u32 byte_cnt) 675 { 676 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 677 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 678 679 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 680 dst_addr); 681 682 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 683 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 684 685 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 686 (iwl_get_dma_hi_addr(phy_addr) 687 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 688 689 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 690 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 691 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 692 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 693 694 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 695 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 696 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 697 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 698 } 699 700 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 701 u32 dst_addr, dma_addr_t phy_addr, 702 u32 byte_cnt) 703 { 704 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 705 unsigned long flags; 706 int ret; 707 708 trans_pcie->ucode_write_complete = false; 709 710 if (!iwl_trans_grab_nic_access(trans, &flags)) 711 return -EIO; 712 713 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 714 byte_cnt); 715 iwl_trans_release_nic_access(trans, &flags); 716 717 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 718 trans_pcie->ucode_write_complete, 5 * HZ); 719 if (!ret) { 720 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 721 iwl_trans_pcie_dump_regs(trans); 722 return -ETIMEDOUT; 723 } 724 725 return 0; 726 } 727 728 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 729 const struct fw_desc *section) 730 { 731 u8 *v_addr; 732 dma_addr_t p_addr; 733 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 734 int ret = 0; 735 736 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 737 section_num); 738 739 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 740 GFP_KERNEL | __GFP_NOWARN); 741 if (!v_addr) { 742 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 743 chunk_sz = PAGE_SIZE; 744 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 745 &p_addr, GFP_KERNEL); 746 if (!v_addr) 747 return -ENOMEM; 748 } 749 750 for (offset = 0; offset < section->len; offset += chunk_sz) { 751 u32 copy_size, dst_addr; 752 bool extended_addr = false; 753 754 copy_size = min_t(u32, chunk_sz, section->len - offset); 755 dst_addr = section->offset + offset; 756 757 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 758 dst_addr <= IWL_FW_MEM_EXTENDED_END) 759 extended_addr = true; 760 761 if (extended_addr) 762 iwl_set_bits_prph(trans, LMPM_CHICK, 763 LMPM_CHICK_EXTENDED_ADDR_SPACE); 764 765 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 766 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 767 copy_size); 768 769 if (extended_addr) 770 iwl_clear_bits_prph(trans, LMPM_CHICK, 771 LMPM_CHICK_EXTENDED_ADDR_SPACE); 772 773 if (ret) { 774 IWL_ERR(trans, 775 "Could not load the [%d] uCode section\n", 776 section_num); 777 break; 778 } 779 } 780 781 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 782 return ret; 783 } 784 785 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 786 const struct fw_img *image, 787 int cpu, 788 int *first_ucode_section) 789 { 790 int shift_param; 791 int i, ret = 0, sec_num = 0x1; 792 u32 val, last_read_idx = 0; 793 794 if (cpu == 1) { 795 shift_param = 0; 796 *first_ucode_section = 0; 797 } else { 798 shift_param = 16; 799 (*first_ucode_section)++; 800 } 801 802 for (i = *first_ucode_section; i < image->num_sec; i++) { 803 last_read_idx = i; 804 805 /* 806 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 807 * CPU1 to CPU2. 808 * PAGING_SEPARATOR_SECTION delimiter - separate between 809 * CPU2 non paged to CPU2 paging sec. 810 */ 811 if (!image->sec[i].data || 812 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 813 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 814 IWL_DEBUG_FW(trans, 815 "Break since Data not valid or Empty section, sec = %d\n", 816 i); 817 break; 818 } 819 820 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 821 if (ret) 822 return ret; 823 824 /* Notify ucode of loaded section number and status */ 825 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 826 val = val | (sec_num << shift_param); 827 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 828 829 sec_num = (sec_num << 1) | 0x1; 830 } 831 832 *first_ucode_section = last_read_idx; 833 834 iwl_enable_interrupts(trans); 835 836 if (trans->cfg->use_tfh) { 837 if (cpu == 1) 838 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 839 0xFFFF); 840 else 841 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 842 0xFFFFFFFF); 843 } else { 844 if (cpu == 1) 845 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 846 0xFFFF); 847 else 848 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 849 0xFFFFFFFF); 850 } 851 852 return 0; 853 } 854 855 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 856 const struct fw_img *image, 857 int cpu, 858 int *first_ucode_section) 859 { 860 int i, ret = 0; 861 u32 last_read_idx = 0; 862 863 if (cpu == 1) 864 *first_ucode_section = 0; 865 else 866 (*first_ucode_section)++; 867 868 for (i = *first_ucode_section; i < image->num_sec; i++) { 869 last_read_idx = i; 870 871 /* 872 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 873 * CPU1 to CPU2. 874 * PAGING_SEPARATOR_SECTION delimiter - separate between 875 * CPU2 non paged to CPU2 paging sec. 876 */ 877 if (!image->sec[i].data || 878 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 879 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 880 IWL_DEBUG_FW(trans, 881 "Break since Data not valid or Empty section, sec = %d\n", 882 i); 883 break; 884 } 885 886 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 887 if (ret) 888 return ret; 889 } 890 891 *first_ucode_section = last_read_idx; 892 893 return 0; 894 } 895 896 void iwl_pcie_apply_destination(struct iwl_trans *trans) 897 { 898 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 899 int i; 900 901 if (trans->dbg.ini_valid) { 902 if (!trans->dbg.num_blocks) 903 return; 904 905 IWL_DEBUG_FW(trans, 906 "WRT: applying DRAM buffer[0] destination\n"); 907 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 908 trans->dbg.fw_mon[0].physical >> 909 MON_BUFF_SHIFT_VER2); 910 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 911 (trans->dbg.fw_mon[0].physical + 912 trans->dbg.fw_mon[0].size - 256) >> 913 MON_BUFF_SHIFT_VER2); 914 return; 915 } 916 917 IWL_INFO(trans, "Applying debug destination %s\n", 918 get_fw_dbg_mode_string(dest->monitor_mode)); 919 920 if (dest->monitor_mode == EXTERNAL_MODE) 921 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 922 else 923 IWL_WARN(trans, "PCI should have external buffer debug\n"); 924 925 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 926 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 927 u32 val = le32_to_cpu(dest->reg_ops[i].val); 928 929 switch (dest->reg_ops[i].op) { 930 case CSR_ASSIGN: 931 iwl_write32(trans, addr, val); 932 break; 933 case CSR_SETBIT: 934 iwl_set_bit(trans, addr, BIT(val)); 935 break; 936 case CSR_CLEARBIT: 937 iwl_clear_bit(trans, addr, BIT(val)); 938 break; 939 case PRPH_ASSIGN: 940 iwl_write_prph(trans, addr, val); 941 break; 942 case PRPH_SETBIT: 943 iwl_set_bits_prph(trans, addr, BIT(val)); 944 break; 945 case PRPH_CLEARBIT: 946 iwl_clear_bits_prph(trans, addr, BIT(val)); 947 break; 948 case PRPH_BLOCKBIT: 949 if (iwl_read_prph(trans, addr) & BIT(val)) { 950 IWL_ERR(trans, 951 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 952 val, addr); 953 goto monitor; 954 } 955 break; 956 default: 957 IWL_ERR(trans, "FW debug - unknown OP %d\n", 958 dest->reg_ops[i].op); 959 break; 960 } 961 } 962 963 monitor: 964 if (dest->monitor_mode == EXTERNAL_MODE && trans->dbg.fw_mon[0].size) { 965 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 966 trans->dbg.fw_mon[0].physical >> 967 dest->base_shift); 968 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 970 (trans->dbg.fw_mon[0].physical + 971 trans->dbg.fw_mon[0].size - 256) >> 972 dest->end_shift); 973 else 974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 975 (trans->dbg.fw_mon[0].physical + 976 trans->dbg.fw_mon[0].size) >> 977 dest->end_shift); 978 } 979 } 980 981 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 982 const struct fw_img *image) 983 { 984 int ret = 0; 985 int first_ucode_section; 986 987 IWL_DEBUG_FW(trans, "working with %s CPU\n", 988 image->is_dual_cpus ? "Dual" : "Single"); 989 990 /* load to FW the binary non secured sections of CPU1 */ 991 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 992 if (ret) 993 return ret; 994 995 if (image->is_dual_cpus) { 996 /* set CPU2 header address */ 997 iwl_write_prph(trans, 998 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 999 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1000 1001 /* load to FW the binary sections of CPU2 */ 1002 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1003 &first_ucode_section); 1004 if (ret) 1005 return ret; 1006 } 1007 1008 /* supported for 7000 only for the moment */ 1009 if (iwlwifi_mod_params.fw_monitor && 1010 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1011 iwl_pcie_alloc_fw_monitor(trans, 0); 1012 1013 if (trans->dbg.fw_mon[0].size) { 1014 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1015 trans->dbg.fw_mon[0].physical >> 4); 1016 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1017 (trans->dbg.fw_mon[0].physical + 1018 trans->dbg.fw_mon[0].size) >> 4); 1019 } 1020 } else if (iwl_pcie_dbg_on(trans)) { 1021 iwl_pcie_apply_destination(trans); 1022 } 1023 1024 iwl_enable_interrupts(trans); 1025 1026 /* release CPU reset */ 1027 iwl_write32(trans, CSR_RESET, 0); 1028 1029 return 0; 1030 } 1031 1032 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1033 const struct fw_img *image) 1034 { 1035 int ret = 0; 1036 int first_ucode_section; 1037 1038 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1039 image->is_dual_cpus ? "Dual" : "Single"); 1040 1041 if (iwl_pcie_dbg_on(trans)) 1042 iwl_pcie_apply_destination(trans); 1043 1044 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1045 iwl_read_prph(trans, WFPM_GP2)); 1046 1047 /* 1048 * Set default value. On resume reading the values that were 1049 * zeored can provide debug data on the resume flow. 1050 * This is for debugging only and has no functional impact. 1051 */ 1052 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1053 1054 /* configure the ucode to be ready to get the secured image */ 1055 /* release CPU reset */ 1056 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1057 1058 /* load to FW the binary Secured sections of CPU1 */ 1059 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1060 &first_ucode_section); 1061 if (ret) 1062 return ret; 1063 1064 /* load to FW the binary sections of CPU2 */ 1065 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1066 &first_ucode_section); 1067 } 1068 1069 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1070 { 1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1072 bool hw_rfkill = iwl_is_rfkill_set(trans); 1073 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1074 bool report; 1075 1076 if (hw_rfkill) { 1077 set_bit(STATUS_RFKILL_HW, &trans->status); 1078 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1079 } else { 1080 clear_bit(STATUS_RFKILL_HW, &trans->status); 1081 if (trans_pcie->opmode_down) 1082 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083 } 1084 1085 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1086 1087 if (prev != report) 1088 iwl_trans_pcie_rf_kill(trans, report); 1089 1090 return hw_rfkill; 1091 } 1092 1093 struct iwl_causes_list { 1094 u32 cause_num; 1095 u32 mask_reg; 1096 u8 addr; 1097 }; 1098 1099 static struct iwl_causes_list causes_list[] = { 1100 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1101 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1102 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1103 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1104 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1105 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1106 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1107 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1108 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1109 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1110 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1111 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1112 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1113 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1114 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1115 }; 1116 1117 static struct iwl_causes_list causes_list_v2[] = { 1118 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1119 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1120 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1121 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1122 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1123 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1124 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 1125 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1126 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1127 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1128 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1129 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1130 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1131 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1132 }; 1133 1134 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1135 { 1136 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1137 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1138 int i, arr_size = 1139 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 1140 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 1141 1142 /* 1143 * Access all non RX causes and map them to the default irq. 1144 * In case we are missing at least one interrupt vector, 1145 * the first interrupt vector will serve non-RX and FBQ causes. 1146 */ 1147 for (i = 0; i < arr_size; i++) { 1148 struct iwl_causes_list *causes = 1149 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 1150 causes_list : causes_list_v2; 1151 1152 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1153 iwl_clear_bit(trans, causes[i].mask_reg, 1154 causes[i].cause_num); 1155 } 1156 } 1157 1158 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1159 { 1160 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1161 u32 offset = 1162 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1163 u32 val, idx; 1164 1165 /* 1166 * The first RX queue - fallback queue, which is designated for 1167 * management frame, command responses etc, is always mapped to the 1168 * first interrupt vector. The other RX queues are mapped to 1169 * the other (N - 2) interrupt vectors. 1170 */ 1171 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1172 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1173 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1174 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1175 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1176 } 1177 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1178 1179 val = MSIX_FH_INT_CAUSES_Q(0); 1180 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1181 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1182 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1183 1184 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1185 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1186 } 1187 1188 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1189 { 1190 struct iwl_trans *trans = trans_pcie->trans; 1191 1192 if (!trans_pcie->msix_enabled) { 1193 if (trans->cfg->mq_rx_supported && 1194 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1195 iwl_write_umac_prph(trans, UREG_CHICK, 1196 UREG_CHICK_MSI_ENABLE); 1197 return; 1198 } 1199 /* 1200 * The IVAR table needs to be configured again after reset, 1201 * but if the device is disabled, we can't write to 1202 * prph. 1203 */ 1204 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1205 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1206 1207 /* 1208 * Each cause from the causes list above and the RX causes is 1209 * represented as a byte in the IVAR table. The first nibble 1210 * represents the bound interrupt vector of the cause, the second 1211 * represents no auto clear for this cause. This will be set if its 1212 * interrupt vector is bound to serve other causes. 1213 */ 1214 iwl_pcie_map_rx_causes(trans); 1215 1216 iwl_pcie_map_non_rx_causes(trans); 1217 } 1218 1219 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1220 { 1221 struct iwl_trans *trans = trans_pcie->trans; 1222 1223 iwl_pcie_conf_msix_hw(trans_pcie); 1224 1225 if (!trans_pcie->msix_enabled) 1226 return; 1227 1228 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1229 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1230 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1231 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1232 } 1233 1234 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1235 { 1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237 1238 lockdep_assert_held(&trans_pcie->mutex); 1239 1240 if (trans_pcie->is_down) 1241 return; 1242 1243 trans_pcie->is_down = true; 1244 1245 /* tell the device to stop sending interrupts */ 1246 iwl_disable_interrupts(trans); 1247 1248 /* device going down, Stop using ICT table */ 1249 iwl_pcie_disable_ict(trans); 1250 1251 /* 1252 * If a HW restart happens during firmware loading, 1253 * then the firmware loading might call this function 1254 * and later it might be called again due to the 1255 * restart. So don't process again if the device is 1256 * already dead. 1257 */ 1258 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1259 IWL_DEBUG_INFO(trans, 1260 "DEVICE_ENABLED bit was set and is now cleared\n"); 1261 iwl_pcie_tx_stop(trans); 1262 iwl_pcie_rx_stop(trans); 1263 1264 /* Power-down device's busmaster DMA clocks */ 1265 if (!trans->cfg->apmg_not_supported) { 1266 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1267 APMG_CLK_VAL_DMA_CLK_RQT); 1268 udelay(5); 1269 } 1270 } 1271 1272 /* Make sure (redundant) we've released our request to stay awake */ 1273 iwl_clear_bit(trans, CSR_GP_CNTRL, 1274 BIT(trans->cfg->csr->flag_mac_access_req)); 1275 1276 /* Stop the device, and put it in low power state */ 1277 iwl_pcie_apm_stop(trans, false); 1278 1279 iwl_trans_pcie_sw_reset(trans); 1280 1281 /* 1282 * Upon stop, the IVAR table gets erased, so msi-x won't 1283 * work. This causes a bug in RF-KILL flows, since the interrupt 1284 * that enables radio won't fire on the correct irq, and the 1285 * driver won't be able to handle the interrupt. 1286 * Configure the IVAR table again after reset. 1287 */ 1288 iwl_pcie_conf_msix_hw(trans_pcie); 1289 1290 /* 1291 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1292 * This is a bug in certain verions of the hardware. 1293 * Certain devices also keep sending HW RF kill interrupt all 1294 * the time, unless the interrupt is ACKed even if the interrupt 1295 * should be masked. Re-ACK all the interrupts here. 1296 */ 1297 iwl_disable_interrupts(trans); 1298 1299 /* clear all status bits */ 1300 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1301 clear_bit(STATUS_INT_ENABLED, &trans->status); 1302 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1303 1304 /* 1305 * Even if we stop the HW, we still want the RF kill 1306 * interrupt 1307 */ 1308 iwl_enable_rfkill_int(trans); 1309 1310 /* re-take ownership to prevent other users from stealing the device */ 1311 iwl_pcie_prepare_card_hw(trans); 1312 } 1313 1314 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1315 { 1316 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1317 1318 if (trans_pcie->msix_enabled) { 1319 int i; 1320 1321 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1322 synchronize_irq(trans_pcie->msix_entries[i].vector); 1323 } else { 1324 synchronize_irq(trans_pcie->pci_dev->irq); 1325 } 1326 } 1327 1328 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1329 const struct fw_img *fw, bool run_in_rfkill) 1330 { 1331 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1332 bool hw_rfkill; 1333 int ret; 1334 1335 /* This may fail if AMT took ownership of the device */ 1336 if (iwl_pcie_prepare_card_hw(trans)) { 1337 IWL_WARN(trans, "Exit HW not ready\n"); 1338 ret = -EIO; 1339 goto out; 1340 } 1341 1342 iwl_enable_rfkill_int(trans); 1343 1344 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1345 1346 /* 1347 * We enabled the RF-Kill interrupt and the handler may very 1348 * well be running. Disable the interrupts to make sure no other 1349 * interrupt can be fired. 1350 */ 1351 iwl_disable_interrupts(trans); 1352 1353 /* Make sure it finished running */ 1354 iwl_pcie_synchronize_irqs(trans); 1355 1356 mutex_lock(&trans_pcie->mutex); 1357 1358 /* If platform's RF_KILL switch is NOT set to KILL */ 1359 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1360 if (hw_rfkill && !run_in_rfkill) { 1361 ret = -ERFKILL; 1362 goto out; 1363 } 1364 1365 /* Someone called stop_device, don't try to start_fw */ 1366 if (trans_pcie->is_down) { 1367 IWL_WARN(trans, 1368 "Can't start_fw since the HW hasn't been started\n"); 1369 ret = -EIO; 1370 goto out; 1371 } 1372 1373 /* make sure rfkill handshake bits are cleared */ 1374 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1375 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1376 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1377 1378 /* clear (again), then enable host interrupts */ 1379 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1380 1381 ret = iwl_pcie_nic_init(trans); 1382 if (ret) { 1383 IWL_ERR(trans, "Unable to init nic\n"); 1384 goto out; 1385 } 1386 1387 /* 1388 * Now, we load the firmware and don't want to be interrupted, even 1389 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1390 * FH_TX interrupt which is needed to load the firmware). If the 1391 * RF-Kill switch is toggled, we will find out after having loaded 1392 * the firmware and return the proper value to the caller. 1393 */ 1394 iwl_enable_fw_load_int(trans); 1395 1396 /* really make sure rfkill handshake bits are cleared */ 1397 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1398 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1399 1400 /* Load the given image to the HW */ 1401 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1402 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1403 else 1404 ret = iwl_pcie_load_given_ucode(trans, fw); 1405 1406 /* re-check RF-Kill state since we may have missed the interrupt */ 1407 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1408 if (hw_rfkill && !run_in_rfkill) 1409 ret = -ERFKILL; 1410 1411 out: 1412 mutex_unlock(&trans_pcie->mutex); 1413 return ret; 1414 } 1415 1416 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1417 { 1418 iwl_pcie_reset_ict(trans); 1419 iwl_pcie_tx_start(trans, scd_addr); 1420 } 1421 1422 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1423 bool was_in_rfkill) 1424 { 1425 bool hw_rfkill; 1426 1427 /* 1428 * Check again since the RF kill state may have changed while 1429 * all the interrupts were disabled, in this case we couldn't 1430 * receive the RF kill interrupt and update the state in the 1431 * op_mode. 1432 * Don't call the op_mode if the rkfill state hasn't changed. 1433 * This allows the op_mode to call stop_device from the rfkill 1434 * notification without endless recursion. Under very rare 1435 * circumstances, we might have a small recursion if the rfkill 1436 * state changed exactly now while we were called from stop_device. 1437 * This is very unlikely but can happen and is supported. 1438 */ 1439 hw_rfkill = iwl_is_rfkill_set(trans); 1440 if (hw_rfkill) { 1441 set_bit(STATUS_RFKILL_HW, &trans->status); 1442 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1443 } else { 1444 clear_bit(STATUS_RFKILL_HW, &trans->status); 1445 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1446 } 1447 if (hw_rfkill != was_in_rfkill) 1448 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1449 } 1450 1451 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1452 { 1453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1454 bool was_in_rfkill; 1455 1456 mutex_lock(&trans_pcie->mutex); 1457 trans_pcie->opmode_down = true; 1458 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1459 _iwl_trans_pcie_stop_device(trans, low_power); 1460 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1461 mutex_unlock(&trans_pcie->mutex); 1462 } 1463 1464 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1465 { 1466 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1467 IWL_TRANS_GET_PCIE_TRANS(trans); 1468 1469 lockdep_assert_held(&trans_pcie->mutex); 1470 1471 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1472 state ? "disabled" : "enabled"); 1473 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1474 if (trans->cfg->gen2) 1475 _iwl_trans_pcie_gen2_stop_device(trans, true); 1476 else 1477 _iwl_trans_pcie_stop_device(trans, true); 1478 } 1479 } 1480 1481 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1482 bool reset) 1483 { 1484 if (!reset) { 1485 /* Enable persistence mode to avoid reset */ 1486 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1487 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1488 } 1489 1490 iwl_disable_interrupts(trans); 1491 1492 /* 1493 * in testing mode, the host stays awake and the 1494 * hardware won't be reset (not even partially) 1495 */ 1496 if (test) 1497 return; 1498 1499 iwl_pcie_disable_ict(trans); 1500 1501 iwl_pcie_synchronize_irqs(trans); 1502 1503 iwl_clear_bit(trans, CSR_GP_CNTRL, 1504 BIT(trans->cfg->csr->flag_mac_access_req)); 1505 iwl_clear_bit(trans, CSR_GP_CNTRL, 1506 BIT(trans->cfg->csr->flag_init_done)); 1507 1508 if (reset) { 1509 /* 1510 * reset TX queues -- some of their registers reset during S3 1511 * so if we don't reset everything here the D3 image would try 1512 * to execute some invalid memory upon resume 1513 */ 1514 iwl_trans_pcie_tx_reset(trans); 1515 } 1516 1517 iwl_pcie_set_pwr(trans, true); 1518 } 1519 1520 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1521 enum iwl_d3_status *status, 1522 bool test, bool reset) 1523 { 1524 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1525 u32 val; 1526 int ret; 1527 1528 if (test) { 1529 iwl_enable_interrupts(trans); 1530 *status = IWL_D3_STATUS_ALIVE; 1531 return 0; 1532 } 1533 1534 iwl_set_bit(trans, CSR_GP_CNTRL, 1535 BIT(trans->cfg->csr->flag_mac_access_req)); 1536 1537 ret = iwl_finish_nic_init(trans); 1538 if (ret) 1539 return ret; 1540 1541 /* 1542 * Reconfigure IVAR table in case of MSIX or reset ict table in 1543 * MSI mode since HW reset erased it. 1544 * Also enables interrupts - none will happen as 1545 * the device doesn't know we're waking it up, only when 1546 * the opmode actually tells it after this call. 1547 */ 1548 iwl_pcie_conf_msix_hw(trans_pcie); 1549 if (!trans_pcie->msix_enabled) 1550 iwl_pcie_reset_ict(trans); 1551 iwl_enable_interrupts(trans); 1552 1553 iwl_pcie_set_pwr(trans, false); 1554 1555 if (!reset) { 1556 iwl_clear_bit(trans, CSR_GP_CNTRL, 1557 BIT(trans->cfg->csr->flag_mac_access_req)); 1558 } else { 1559 iwl_trans_pcie_tx_reset(trans); 1560 1561 ret = iwl_pcie_rx_init(trans); 1562 if (ret) { 1563 IWL_ERR(trans, 1564 "Failed to resume the device (RX reset)\n"); 1565 return ret; 1566 } 1567 } 1568 1569 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1570 iwl_read_umac_prph(trans, WFPM_GP2)); 1571 1572 val = iwl_read32(trans, CSR_RESET); 1573 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1574 *status = IWL_D3_STATUS_RESET; 1575 else 1576 *status = IWL_D3_STATUS_ALIVE; 1577 1578 return 0; 1579 } 1580 1581 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1582 struct iwl_trans *trans) 1583 { 1584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1585 int max_irqs, num_irqs, i, ret; 1586 u16 pci_cmd; 1587 1588 if (!trans->cfg->mq_rx_supported) 1589 goto enable_msi; 1590 1591 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 1592 for (i = 0; i < max_irqs; i++) 1593 trans_pcie->msix_entries[i].entry = i; 1594 1595 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1596 MSIX_MIN_INTERRUPT_VECTORS, 1597 max_irqs); 1598 if (num_irqs < 0) { 1599 IWL_DEBUG_INFO(trans, 1600 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1601 num_irqs); 1602 goto enable_msi; 1603 } 1604 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1605 1606 IWL_DEBUG_INFO(trans, 1607 "MSI-X enabled. %d interrupt vectors were allocated\n", 1608 num_irqs); 1609 1610 /* 1611 * In case the OS provides fewer interrupts than requested, different 1612 * causes will share the same interrupt vector as follows: 1613 * One interrupt less: non rx causes shared with FBQ. 1614 * Two interrupts less: non rx causes shared with FBQ and RSS. 1615 * More than two interrupts: we will use fewer RSS queues. 1616 */ 1617 if (num_irqs <= max_irqs - 2) { 1618 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1619 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1620 IWL_SHARED_IRQ_FIRST_RSS; 1621 } else if (num_irqs == max_irqs - 1) { 1622 trans_pcie->trans->num_rx_queues = num_irqs; 1623 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1624 } else { 1625 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1626 } 1627 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1628 1629 trans_pcie->alloc_vecs = num_irqs; 1630 trans_pcie->msix_enabled = true; 1631 return; 1632 1633 enable_msi: 1634 ret = pci_enable_msi(pdev); 1635 if (ret) { 1636 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1637 /* enable rfkill interrupt: hw bug w/a */ 1638 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1639 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1640 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1641 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1642 } 1643 } 1644 } 1645 1646 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1647 { 1648 int iter_rx_q, i, ret, cpu, offset; 1649 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1650 1651 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1652 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1653 offset = 1 + i; 1654 for (; i < iter_rx_q ; i++) { 1655 /* 1656 * Get the cpu prior to the place to search 1657 * (i.e. return will be > i - 1). 1658 */ 1659 cpu = cpumask_next(i - offset, cpu_online_mask); 1660 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1661 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1662 &trans_pcie->affinity_mask[i]); 1663 if (ret) 1664 IWL_ERR(trans_pcie->trans, 1665 "Failed to set affinity mask for IRQ %d\n", 1666 i); 1667 } 1668 } 1669 1670 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1671 struct iwl_trans_pcie *trans_pcie) 1672 { 1673 int i; 1674 1675 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1676 int ret; 1677 struct msix_entry *msix_entry; 1678 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1679 1680 if (!qname) 1681 return -ENOMEM; 1682 1683 msix_entry = &trans_pcie->msix_entries[i]; 1684 ret = devm_request_threaded_irq(&pdev->dev, 1685 msix_entry->vector, 1686 iwl_pcie_msix_isr, 1687 (i == trans_pcie->def_irq) ? 1688 iwl_pcie_irq_msix_handler : 1689 iwl_pcie_irq_rx_msix_handler, 1690 IRQF_SHARED, 1691 qname, 1692 msix_entry); 1693 if (ret) { 1694 IWL_ERR(trans_pcie->trans, 1695 "Error allocating IRQ %d\n", i); 1696 1697 return ret; 1698 } 1699 } 1700 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1701 1702 return 0; 1703 } 1704 1705 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1706 { 1707 u32 hpm, wprot; 1708 1709 switch (trans->cfg->device_family) { 1710 case IWL_DEVICE_FAMILY_9000: 1711 wprot = PREG_PRPH_WPROT_9000; 1712 break; 1713 case IWL_DEVICE_FAMILY_22000: 1714 wprot = PREG_PRPH_WPROT_22000; 1715 break; 1716 default: 1717 return 0; 1718 } 1719 1720 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1721 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1722 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1723 1724 if (wprot_val & PREG_WFPM_ACCESS) { 1725 IWL_ERR(trans, 1726 "Error, can not clear persistence bit\n"); 1727 return -EPERM; 1728 } 1729 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1730 hpm & ~PERSISTENCE_BIT); 1731 } 1732 1733 return 0; 1734 } 1735 1736 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1737 { 1738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1739 int err; 1740 1741 lockdep_assert_held(&trans_pcie->mutex); 1742 1743 err = iwl_pcie_prepare_card_hw(trans); 1744 if (err) { 1745 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1746 return err; 1747 } 1748 1749 err = iwl_trans_pcie_clear_persistence_bit(trans); 1750 if (err) 1751 return err; 1752 1753 iwl_trans_pcie_sw_reset(trans); 1754 1755 err = iwl_pcie_apm_init(trans); 1756 if (err) 1757 return err; 1758 1759 iwl_pcie_init_msix(trans_pcie); 1760 1761 /* From now on, the op_mode will be kept updated about RF kill state */ 1762 iwl_enable_rfkill_int(trans); 1763 1764 trans_pcie->opmode_down = false; 1765 1766 /* Set is_down to false here so that...*/ 1767 trans_pcie->is_down = false; 1768 1769 /* ...rfkill can call stop_device and set it false if needed */ 1770 iwl_pcie_check_hw_rf_kill(trans); 1771 1772 /* Make sure we sync here, because we'll need full access later */ 1773 if (low_power) 1774 pm_runtime_resume(trans->dev); 1775 1776 return 0; 1777 } 1778 1779 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1780 { 1781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1782 int ret; 1783 1784 mutex_lock(&trans_pcie->mutex); 1785 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1786 mutex_unlock(&trans_pcie->mutex); 1787 1788 return ret; 1789 } 1790 1791 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1792 { 1793 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1794 1795 mutex_lock(&trans_pcie->mutex); 1796 1797 /* disable interrupts - don't enable HW RF kill interrupt */ 1798 iwl_disable_interrupts(trans); 1799 1800 iwl_pcie_apm_stop(trans, true); 1801 1802 iwl_disable_interrupts(trans); 1803 1804 iwl_pcie_disable_ict(trans); 1805 1806 mutex_unlock(&trans_pcie->mutex); 1807 1808 iwl_pcie_synchronize_irqs(trans); 1809 } 1810 1811 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1812 { 1813 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1814 } 1815 1816 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1817 { 1818 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1819 } 1820 1821 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1822 { 1823 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1824 } 1825 1826 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1827 { 1828 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 1829 return 0x00FFFFFF; 1830 else 1831 return 0x000FFFFF; 1832 } 1833 1834 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1835 { 1836 u32 mask = iwl_trans_pcie_prph_msk(trans); 1837 1838 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1839 ((reg & mask) | (3 << 24))); 1840 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1841 } 1842 1843 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1844 u32 val) 1845 { 1846 u32 mask = iwl_trans_pcie_prph_msk(trans); 1847 1848 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1849 ((addr & mask) | (3 << 24))); 1850 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1851 } 1852 1853 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1854 const struct iwl_trans_config *trans_cfg) 1855 { 1856 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1857 1858 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1859 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1860 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1861 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1862 trans_pcie->n_no_reclaim_cmds = 0; 1863 else 1864 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1865 if (trans_pcie->n_no_reclaim_cmds) 1866 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1867 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1868 1869 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1870 trans_pcie->rx_page_order = 1871 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1872 1873 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1874 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1875 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1876 1877 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1878 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1879 1880 trans->command_groups = trans_cfg->command_groups; 1881 trans->command_groups_size = trans_cfg->command_groups_size; 1882 1883 /* Initialize NAPI here - it should be before registering to mac80211 1884 * in the opmode but after the HW struct is allocated. 1885 * As this function may be called again in some corner cases don't 1886 * do anything if NAPI was already initialized. 1887 */ 1888 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1889 init_dummy_netdev(&trans_pcie->napi_dev); 1890 } 1891 1892 void iwl_trans_pcie_free(struct iwl_trans *trans) 1893 { 1894 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1895 int i; 1896 1897 iwl_pcie_synchronize_irqs(trans); 1898 1899 if (trans->cfg->gen2) 1900 iwl_pcie_gen2_tx_free(trans); 1901 else 1902 iwl_pcie_tx_free(trans); 1903 iwl_pcie_rx_free(trans); 1904 1905 if (trans_pcie->rba.alloc_wq) { 1906 destroy_workqueue(trans_pcie->rba.alloc_wq); 1907 trans_pcie->rba.alloc_wq = NULL; 1908 } 1909 1910 if (trans_pcie->msix_enabled) { 1911 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1912 irq_set_affinity_hint( 1913 trans_pcie->msix_entries[i].vector, 1914 NULL); 1915 } 1916 1917 trans_pcie->msix_enabled = false; 1918 } else { 1919 iwl_pcie_free_ict(trans); 1920 } 1921 1922 iwl_pcie_free_fw_monitor(trans); 1923 1924 for_each_possible_cpu(i) { 1925 struct iwl_tso_hdr_page *p = 1926 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1927 1928 if (p->page) 1929 __free_page(p->page); 1930 } 1931 1932 free_percpu(trans_pcie->tso_hdr_page); 1933 mutex_destroy(&trans_pcie->mutex); 1934 iwl_trans_free(trans); 1935 } 1936 1937 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1938 { 1939 if (state) 1940 set_bit(STATUS_TPOWER_PMI, &trans->status); 1941 else 1942 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1943 } 1944 1945 struct iwl_trans_pcie_removal { 1946 struct pci_dev *pdev; 1947 struct work_struct work; 1948 }; 1949 1950 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 1951 { 1952 struct iwl_trans_pcie_removal *removal = 1953 container_of(wk, struct iwl_trans_pcie_removal, work); 1954 struct pci_dev *pdev = removal->pdev; 1955 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 1956 1957 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 1958 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 1959 pci_lock_rescan_remove(); 1960 pci_dev_put(pdev); 1961 pci_stop_and_remove_bus_device(pdev); 1962 pci_unlock_rescan_remove(); 1963 1964 kfree(removal); 1965 module_put(THIS_MODULE); 1966 } 1967 1968 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1969 unsigned long *flags) 1970 { 1971 int ret; 1972 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1973 1974 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1975 1976 if (trans_pcie->cmd_hold_nic_awake) 1977 goto out; 1978 1979 /* this bit wakes up the NIC */ 1980 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1981 BIT(trans->cfg->csr->flag_mac_access_req)); 1982 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1983 udelay(2); 1984 1985 /* 1986 * These bits say the device is running, and should keep running for 1987 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1988 * but they do not indicate that embedded SRAM is restored yet; 1989 * HW with volatile SRAM must save/restore contents to/from 1990 * host DRAM when sleeping/waking for power-saving. 1991 * Each direction takes approximately 1/4 millisecond; with this 1992 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1993 * series of register accesses are expected (e.g. reading Event Log), 1994 * to keep device from sleeping. 1995 * 1996 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1997 * SRAM is okay/restored. We don't check that here because this call 1998 * is just for hardware register access; but GP1 MAC_SLEEP 1999 * check is a good idea before accessing the SRAM of HW with 2000 * volatile SRAM (e.g. reading Event Log). 2001 * 2002 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2003 * and do not save/restore SRAM when power cycling. 2004 */ 2005 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2006 BIT(trans->cfg->csr->flag_val_mac_access_en), 2007 (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2008 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2009 if (unlikely(ret < 0)) { 2010 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2011 2012 WARN_ONCE(1, 2013 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2014 cntrl); 2015 2016 iwl_trans_pcie_dump_regs(trans); 2017 2018 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2019 struct iwl_trans_pcie_removal *removal; 2020 2021 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2022 goto err; 2023 2024 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2025 2026 /* 2027 * get a module reference to avoid doing this 2028 * while unloading anyway and to avoid 2029 * scheduling a work with code that's being 2030 * removed. 2031 */ 2032 if (!try_module_get(THIS_MODULE)) { 2033 IWL_ERR(trans, 2034 "Module is being unloaded - abort\n"); 2035 goto err; 2036 } 2037 2038 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2039 if (!removal) { 2040 module_put(THIS_MODULE); 2041 goto err; 2042 } 2043 /* 2044 * we don't need to clear this flag, because 2045 * the trans will be freed and reallocated. 2046 */ 2047 set_bit(STATUS_TRANS_DEAD, &trans->status); 2048 2049 removal->pdev = to_pci_dev(trans->dev); 2050 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2051 pci_dev_get(removal->pdev); 2052 schedule_work(&removal->work); 2053 } else { 2054 iwl_write32(trans, CSR_RESET, 2055 CSR_RESET_REG_FLAG_FORCE_NMI); 2056 } 2057 2058 err: 2059 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2060 return false; 2061 } 2062 2063 out: 2064 /* 2065 * Fool sparse by faking we release the lock - sparse will 2066 * track nic_access anyway. 2067 */ 2068 __release(&trans_pcie->reg_lock); 2069 return true; 2070 } 2071 2072 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2073 unsigned long *flags) 2074 { 2075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2076 2077 lockdep_assert_held(&trans_pcie->reg_lock); 2078 2079 /* 2080 * Fool sparse by faking we acquiring the lock - sparse will 2081 * track nic_access anyway. 2082 */ 2083 __acquire(&trans_pcie->reg_lock); 2084 2085 if (trans_pcie->cmd_hold_nic_awake) 2086 goto out; 2087 2088 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2089 BIT(trans->cfg->csr->flag_mac_access_req)); 2090 /* 2091 * Above we read the CSR_GP_CNTRL register, which will flush 2092 * any previous writes, but we need the write that clears the 2093 * MAC_ACCESS_REQ bit to be performed before any other writes 2094 * scheduled on different CPUs (after we drop reg_lock). 2095 */ 2096 out: 2097 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2098 } 2099 2100 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2101 void *buf, int dwords) 2102 { 2103 unsigned long flags; 2104 int offs, ret = 0; 2105 u32 *vals = buf; 2106 2107 if (iwl_trans_grab_nic_access(trans, &flags)) { 2108 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2109 for (offs = 0; offs < dwords; offs++) 2110 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2111 iwl_trans_release_nic_access(trans, &flags); 2112 } else { 2113 ret = -EBUSY; 2114 } 2115 return ret; 2116 } 2117 2118 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2119 const void *buf, int dwords) 2120 { 2121 unsigned long flags; 2122 int offs, ret = 0; 2123 const u32 *vals = buf; 2124 2125 if (iwl_trans_grab_nic_access(trans, &flags)) { 2126 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2127 for (offs = 0; offs < dwords; offs++) 2128 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2129 vals ? vals[offs] : 0); 2130 iwl_trans_release_nic_access(trans, &flags); 2131 } else { 2132 ret = -EBUSY; 2133 } 2134 return ret; 2135 } 2136 2137 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2138 unsigned long txqs, 2139 bool freeze) 2140 { 2141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2142 int queue; 2143 2144 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2145 struct iwl_txq *txq = trans_pcie->txq[queue]; 2146 unsigned long now; 2147 2148 spin_lock_bh(&txq->lock); 2149 2150 now = jiffies; 2151 2152 if (txq->frozen == freeze) 2153 goto next_queue; 2154 2155 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2156 freeze ? "Freezing" : "Waking", queue); 2157 2158 txq->frozen = freeze; 2159 2160 if (txq->read_ptr == txq->write_ptr) 2161 goto next_queue; 2162 2163 if (freeze) { 2164 if (unlikely(time_after(now, 2165 txq->stuck_timer.expires))) { 2166 /* 2167 * The timer should have fired, maybe it is 2168 * spinning right now on the lock. 2169 */ 2170 goto next_queue; 2171 } 2172 /* remember how long until the timer fires */ 2173 txq->frozen_expiry_remainder = 2174 txq->stuck_timer.expires - now; 2175 del_timer(&txq->stuck_timer); 2176 goto next_queue; 2177 } 2178 2179 /* 2180 * Wake a non-empty queue -> arm timer with the 2181 * remainder before it froze 2182 */ 2183 mod_timer(&txq->stuck_timer, 2184 now + txq->frozen_expiry_remainder); 2185 2186 next_queue: 2187 spin_unlock_bh(&txq->lock); 2188 } 2189 } 2190 2191 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2192 { 2193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2194 int i; 2195 2196 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2197 struct iwl_txq *txq = trans_pcie->txq[i]; 2198 2199 if (i == trans_pcie->cmd_queue) 2200 continue; 2201 2202 spin_lock_bh(&txq->lock); 2203 2204 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2205 txq->block--; 2206 if (!txq->block) { 2207 iwl_write32(trans, HBUS_TARG_WRPTR, 2208 txq->write_ptr | (i << 8)); 2209 } 2210 } else if (block) { 2211 txq->block++; 2212 } 2213 2214 spin_unlock_bh(&txq->lock); 2215 } 2216 } 2217 2218 #define IWL_FLUSH_WAIT_MS 2000 2219 2220 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2221 { 2222 u32 txq_id = txq->id; 2223 u32 status; 2224 bool active; 2225 u8 fifo; 2226 2227 if (trans->cfg->use_tfh) { 2228 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2229 txq->read_ptr, txq->write_ptr); 2230 /* TODO: access new SCD registers and dump them */ 2231 return; 2232 } 2233 2234 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2235 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2236 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2237 2238 IWL_ERR(trans, 2239 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2240 txq_id, active ? "" : "in", fifo, 2241 jiffies_to_msecs(txq->wd_timeout), 2242 txq->read_ptr, txq->write_ptr, 2243 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2244 (trans->cfg->base_params->max_tfd_queue_size - 1), 2245 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2246 (trans->cfg->base_params->max_tfd_queue_size - 1), 2247 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2248 } 2249 2250 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2251 struct iwl_trans_rxq_dma_data *data) 2252 { 2253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2254 2255 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2256 return -EINVAL; 2257 2258 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2259 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2260 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2261 data->fr_bd_wid = 0; 2262 2263 return 0; 2264 } 2265 2266 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2267 { 2268 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2269 struct iwl_txq *txq; 2270 unsigned long now = jiffies; 2271 bool overflow_tx; 2272 u8 wr_ptr; 2273 2274 /* Make sure the NIC is still alive in the bus */ 2275 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2276 return -ENODEV; 2277 2278 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2279 return -EINVAL; 2280 2281 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2282 txq = trans_pcie->txq[txq_idx]; 2283 2284 spin_lock_bh(&txq->lock); 2285 overflow_tx = txq->overflow_tx || 2286 !skb_queue_empty(&txq->overflow_q); 2287 spin_unlock_bh(&txq->lock); 2288 2289 wr_ptr = READ_ONCE(txq->write_ptr); 2290 2291 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2292 overflow_tx) && 2293 !time_after(jiffies, 2294 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2295 u8 write_ptr = READ_ONCE(txq->write_ptr); 2296 2297 /* 2298 * If write pointer moved during the wait, warn only 2299 * if the TX came from op mode. In case TX came from 2300 * trans layer (overflow TX) don't warn. 2301 */ 2302 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2303 "WR pointer moved while flushing %d -> %d\n", 2304 wr_ptr, write_ptr)) 2305 return -ETIMEDOUT; 2306 wr_ptr = write_ptr; 2307 2308 usleep_range(1000, 2000); 2309 2310 spin_lock_bh(&txq->lock); 2311 overflow_tx = txq->overflow_tx || 2312 !skb_queue_empty(&txq->overflow_q); 2313 spin_unlock_bh(&txq->lock); 2314 } 2315 2316 if (txq->read_ptr != txq->write_ptr) { 2317 IWL_ERR(trans, 2318 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2319 iwl_trans_pcie_log_scd_error(trans, txq); 2320 return -ETIMEDOUT; 2321 } 2322 2323 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2324 2325 return 0; 2326 } 2327 2328 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2329 { 2330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2331 int cnt; 2332 int ret = 0; 2333 2334 /* waiting for all the tx frames complete might take a while */ 2335 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2336 2337 if (cnt == trans_pcie->cmd_queue) 2338 continue; 2339 if (!test_bit(cnt, trans_pcie->queue_used)) 2340 continue; 2341 if (!(BIT(cnt) & txq_bm)) 2342 continue; 2343 2344 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2345 if (ret) 2346 break; 2347 } 2348 2349 return ret; 2350 } 2351 2352 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2353 u32 mask, u32 value) 2354 { 2355 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2356 unsigned long flags; 2357 2358 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2359 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2360 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2361 } 2362 2363 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2364 { 2365 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2366 2367 if (iwlwifi_mod_params.d0i3_disable) 2368 return; 2369 2370 pm_runtime_get(&trans_pcie->pci_dev->dev); 2371 2372 #ifdef CONFIG_PM 2373 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2374 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2375 #endif /* CONFIG_PM */ 2376 } 2377 2378 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2379 { 2380 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2381 2382 if (iwlwifi_mod_params.d0i3_disable) 2383 return; 2384 2385 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2386 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2387 2388 #ifdef CONFIG_PM 2389 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2390 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2391 #endif /* CONFIG_PM */ 2392 } 2393 2394 static const char *get_csr_string(int cmd) 2395 { 2396 #define IWL_CMD(x) case x: return #x 2397 switch (cmd) { 2398 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2399 IWL_CMD(CSR_INT_COALESCING); 2400 IWL_CMD(CSR_INT); 2401 IWL_CMD(CSR_INT_MASK); 2402 IWL_CMD(CSR_FH_INT_STATUS); 2403 IWL_CMD(CSR_GPIO_IN); 2404 IWL_CMD(CSR_RESET); 2405 IWL_CMD(CSR_GP_CNTRL); 2406 IWL_CMD(CSR_HW_REV); 2407 IWL_CMD(CSR_EEPROM_REG); 2408 IWL_CMD(CSR_EEPROM_GP); 2409 IWL_CMD(CSR_OTP_GP_REG); 2410 IWL_CMD(CSR_GIO_REG); 2411 IWL_CMD(CSR_GP_UCODE_REG); 2412 IWL_CMD(CSR_GP_DRIVER_REG); 2413 IWL_CMD(CSR_UCODE_DRV_GP1); 2414 IWL_CMD(CSR_UCODE_DRV_GP2); 2415 IWL_CMD(CSR_LED_REG); 2416 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2417 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2418 IWL_CMD(CSR_ANA_PLL_CFG); 2419 IWL_CMD(CSR_HW_REV_WA_REG); 2420 IWL_CMD(CSR_MONITOR_STATUS_REG); 2421 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2422 default: 2423 return "UNKNOWN"; 2424 } 2425 #undef IWL_CMD 2426 } 2427 2428 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2429 { 2430 int i; 2431 static const u32 csr_tbl[] = { 2432 CSR_HW_IF_CONFIG_REG, 2433 CSR_INT_COALESCING, 2434 CSR_INT, 2435 CSR_INT_MASK, 2436 CSR_FH_INT_STATUS, 2437 CSR_GPIO_IN, 2438 CSR_RESET, 2439 CSR_GP_CNTRL, 2440 CSR_HW_REV, 2441 CSR_EEPROM_REG, 2442 CSR_EEPROM_GP, 2443 CSR_OTP_GP_REG, 2444 CSR_GIO_REG, 2445 CSR_GP_UCODE_REG, 2446 CSR_GP_DRIVER_REG, 2447 CSR_UCODE_DRV_GP1, 2448 CSR_UCODE_DRV_GP2, 2449 CSR_LED_REG, 2450 CSR_DRAM_INT_TBL_REG, 2451 CSR_GIO_CHICKEN_BITS, 2452 CSR_ANA_PLL_CFG, 2453 CSR_MONITOR_STATUS_REG, 2454 CSR_HW_REV_WA_REG, 2455 CSR_DBG_HPET_MEM_REG 2456 }; 2457 IWL_ERR(trans, "CSR values:\n"); 2458 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2459 "CSR_INT_PERIODIC_REG)\n"); 2460 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2461 IWL_ERR(trans, " %25s: 0X%08x\n", 2462 get_csr_string(csr_tbl[i]), 2463 iwl_read32(trans, csr_tbl[i])); 2464 } 2465 } 2466 2467 #ifdef CONFIG_IWLWIFI_DEBUGFS 2468 /* create and remove of files */ 2469 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2470 debugfs_create_file(#name, mode, parent, trans, \ 2471 &iwl_dbgfs_##name##_ops); \ 2472 } while (0) 2473 2474 /* file operation */ 2475 #define DEBUGFS_READ_FILE_OPS(name) \ 2476 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2477 .read = iwl_dbgfs_##name##_read, \ 2478 .open = simple_open, \ 2479 .llseek = generic_file_llseek, \ 2480 }; 2481 2482 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2483 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2484 .write = iwl_dbgfs_##name##_write, \ 2485 .open = simple_open, \ 2486 .llseek = generic_file_llseek, \ 2487 }; 2488 2489 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2490 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2491 .write = iwl_dbgfs_##name##_write, \ 2492 .read = iwl_dbgfs_##name##_read, \ 2493 .open = simple_open, \ 2494 .llseek = generic_file_llseek, \ 2495 }; 2496 2497 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2498 char __user *user_buf, 2499 size_t count, loff_t *ppos) 2500 { 2501 struct iwl_trans *trans = file->private_data; 2502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2503 struct iwl_txq *txq; 2504 char *buf; 2505 int pos = 0; 2506 int cnt; 2507 int ret; 2508 size_t bufsz; 2509 2510 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2511 2512 if (!trans_pcie->txq_memory) 2513 return -EAGAIN; 2514 2515 buf = kzalloc(bufsz, GFP_KERNEL); 2516 if (!buf) 2517 return -ENOMEM; 2518 2519 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2520 txq = trans_pcie->txq[cnt]; 2521 pos += scnprintf(buf + pos, bufsz - pos, 2522 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2523 cnt, txq->read_ptr, txq->write_ptr, 2524 !!test_bit(cnt, trans_pcie->queue_used), 2525 !!test_bit(cnt, trans_pcie->queue_stopped), 2526 txq->need_update, txq->frozen, 2527 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2528 } 2529 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2530 kfree(buf); 2531 return ret; 2532 } 2533 2534 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2535 char __user *user_buf, 2536 size_t count, loff_t *ppos) 2537 { 2538 struct iwl_trans *trans = file->private_data; 2539 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2540 char *buf; 2541 int pos = 0, i, ret; 2542 size_t bufsz = sizeof(buf); 2543 2544 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2545 2546 if (!trans_pcie->rxq) 2547 return -EAGAIN; 2548 2549 buf = kzalloc(bufsz, GFP_KERNEL); 2550 if (!buf) 2551 return -ENOMEM; 2552 2553 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2554 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2555 2556 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2557 i); 2558 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2559 rxq->read); 2560 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2561 rxq->write); 2562 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2563 rxq->write_actual); 2564 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2565 rxq->need_update); 2566 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2567 rxq->free_count); 2568 if (rxq->rb_stts) { 2569 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2570 rxq)); 2571 pos += scnprintf(buf + pos, bufsz - pos, 2572 "\tclosed_rb_num: %u\n", 2573 r & 0x0FFF); 2574 } else { 2575 pos += scnprintf(buf + pos, bufsz - pos, 2576 "\tclosed_rb_num: Not Allocated\n"); 2577 } 2578 } 2579 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2580 kfree(buf); 2581 2582 return ret; 2583 } 2584 2585 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2586 char __user *user_buf, 2587 size_t count, loff_t *ppos) 2588 { 2589 struct iwl_trans *trans = file->private_data; 2590 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2591 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2592 2593 int pos = 0; 2594 char *buf; 2595 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2596 ssize_t ret; 2597 2598 buf = kzalloc(bufsz, GFP_KERNEL); 2599 if (!buf) 2600 return -ENOMEM; 2601 2602 pos += scnprintf(buf + pos, bufsz - pos, 2603 "Interrupt Statistics Report:\n"); 2604 2605 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2606 isr_stats->hw); 2607 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2608 isr_stats->sw); 2609 if (isr_stats->sw || isr_stats->hw) { 2610 pos += scnprintf(buf + pos, bufsz - pos, 2611 "\tLast Restarting Code: 0x%X\n", 2612 isr_stats->err_code); 2613 } 2614 #ifdef CONFIG_IWLWIFI_DEBUG 2615 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2616 isr_stats->sch); 2617 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2618 isr_stats->alive); 2619 #endif 2620 pos += scnprintf(buf + pos, bufsz - pos, 2621 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2622 2623 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2624 isr_stats->ctkill); 2625 2626 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2627 isr_stats->wakeup); 2628 2629 pos += scnprintf(buf + pos, bufsz - pos, 2630 "Rx command responses:\t\t %u\n", isr_stats->rx); 2631 2632 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2633 isr_stats->tx); 2634 2635 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2636 isr_stats->unhandled); 2637 2638 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2639 kfree(buf); 2640 return ret; 2641 } 2642 2643 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2644 const char __user *user_buf, 2645 size_t count, loff_t *ppos) 2646 { 2647 struct iwl_trans *trans = file->private_data; 2648 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2649 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2650 u32 reset_flag; 2651 int ret; 2652 2653 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2654 if (ret) 2655 return ret; 2656 if (reset_flag == 0) 2657 memset(isr_stats, 0, sizeof(*isr_stats)); 2658 2659 return count; 2660 } 2661 2662 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2663 const char __user *user_buf, 2664 size_t count, loff_t *ppos) 2665 { 2666 struct iwl_trans *trans = file->private_data; 2667 2668 iwl_pcie_dump_csr(trans); 2669 2670 return count; 2671 } 2672 2673 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2674 char __user *user_buf, 2675 size_t count, loff_t *ppos) 2676 { 2677 struct iwl_trans *trans = file->private_data; 2678 char *buf = NULL; 2679 ssize_t ret; 2680 2681 ret = iwl_dump_fh(trans, &buf); 2682 if (ret < 0) 2683 return ret; 2684 if (!buf) 2685 return -EINVAL; 2686 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2687 kfree(buf); 2688 return ret; 2689 } 2690 2691 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2692 char __user *user_buf, 2693 size_t count, loff_t *ppos) 2694 { 2695 struct iwl_trans *trans = file->private_data; 2696 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2697 char buf[100]; 2698 int pos; 2699 2700 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2701 trans_pcie->debug_rfkill, 2702 !(iwl_read32(trans, CSR_GP_CNTRL) & 2703 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2704 2705 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2706 } 2707 2708 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2709 const char __user *user_buf, 2710 size_t count, loff_t *ppos) 2711 { 2712 struct iwl_trans *trans = file->private_data; 2713 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2714 bool new_value; 2715 int ret; 2716 2717 ret = kstrtobool_from_user(user_buf, count, &new_value); 2718 if (ret) 2719 return ret; 2720 if (new_value == trans_pcie->debug_rfkill) 2721 return count; 2722 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2723 trans_pcie->debug_rfkill, new_value); 2724 trans_pcie->debug_rfkill = new_value; 2725 iwl_pcie_handle_rfkill_irq(trans); 2726 2727 return count; 2728 } 2729 2730 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2731 struct file *file) 2732 { 2733 struct iwl_trans *trans = inode->i_private; 2734 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2735 2736 if (!trans->dbg.dest_tlv || 2737 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2738 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2739 return -ENOENT; 2740 } 2741 2742 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2743 return -EBUSY; 2744 2745 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2746 return simple_open(inode, file); 2747 } 2748 2749 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2750 struct file *file) 2751 { 2752 struct iwl_trans_pcie *trans_pcie = 2753 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2754 2755 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2756 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2757 return 0; 2758 } 2759 2760 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2761 void *buf, ssize_t *size, 2762 ssize_t *bytes_copied) 2763 { 2764 int buf_size_left = count - *bytes_copied; 2765 2766 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2767 if (*size > buf_size_left) 2768 *size = buf_size_left; 2769 2770 *size -= copy_to_user(user_buf, buf, *size); 2771 *bytes_copied += *size; 2772 2773 if (buf_size_left == *size) 2774 return true; 2775 return false; 2776 } 2777 2778 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2779 char __user *user_buf, 2780 size_t count, loff_t *ppos) 2781 { 2782 struct iwl_trans *trans = file->private_data; 2783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2784 void *cpu_addr = (void *)trans->dbg.fw_mon[0].block, *curr_buf; 2785 struct cont_rec *data = &trans_pcie->fw_mon_data; 2786 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2787 ssize_t size, bytes_copied = 0; 2788 bool b_full; 2789 2790 if (trans->dbg.dest_tlv) { 2791 write_ptr_addr = 2792 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2793 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2794 } else { 2795 write_ptr_addr = MON_BUFF_WRPTR; 2796 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2797 } 2798 2799 if (unlikely(!trans->dbg.rec_on)) 2800 return 0; 2801 2802 mutex_lock(&data->mutex); 2803 if (data->state == 2804 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2805 mutex_unlock(&data->mutex); 2806 return 0; 2807 } 2808 2809 /* write_ptr position in bytes rather then DW */ 2810 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2811 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2812 2813 if (data->prev_wrap_cnt == wrap_cnt) { 2814 size = write_ptr - data->prev_wr_ptr; 2815 curr_buf = cpu_addr + data->prev_wr_ptr; 2816 b_full = iwl_write_to_user_buf(user_buf, count, 2817 curr_buf, &size, 2818 &bytes_copied); 2819 data->prev_wr_ptr += size; 2820 2821 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2822 write_ptr < data->prev_wr_ptr) { 2823 size = trans->dbg.fw_mon[0].size - data->prev_wr_ptr; 2824 curr_buf = cpu_addr + data->prev_wr_ptr; 2825 b_full = iwl_write_to_user_buf(user_buf, count, 2826 curr_buf, &size, 2827 &bytes_copied); 2828 data->prev_wr_ptr += size; 2829 2830 if (!b_full) { 2831 size = write_ptr; 2832 b_full = iwl_write_to_user_buf(user_buf, count, 2833 cpu_addr, &size, 2834 &bytes_copied); 2835 data->prev_wr_ptr = size; 2836 data->prev_wrap_cnt++; 2837 } 2838 } else { 2839 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2840 write_ptr > data->prev_wr_ptr) 2841 IWL_WARN(trans, 2842 "write pointer passed previous write pointer, start copying from the beginning\n"); 2843 else if (!unlikely(data->prev_wrap_cnt == 0 && 2844 data->prev_wr_ptr == 0)) 2845 IWL_WARN(trans, 2846 "monitor data is out of sync, start copying from the beginning\n"); 2847 2848 size = write_ptr; 2849 b_full = iwl_write_to_user_buf(user_buf, count, 2850 cpu_addr, &size, 2851 &bytes_copied); 2852 data->prev_wr_ptr = size; 2853 data->prev_wrap_cnt = wrap_cnt; 2854 } 2855 2856 mutex_unlock(&data->mutex); 2857 2858 return bytes_copied; 2859 } 2860 2861 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2862 DEBUGFS_READ_FILE_OPS(fh_reg); 2863 DEBUGFS_READ_FILE_OPS(rx_queue); 2864 DEBUGFS_READ_FILE_OPS(tx_queue); 2865 DEBUGFS_WRITE_FILE_OPS(csr); 2866 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2867 2868 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2869 .read = iwl_dbgfs_monitor_data_read, 2870 .open = iwl_dbgfs_monitor_data_open, 2871 .release = iwl_dbgfs_monitor_data_release, 2872 }; 2873 2874 /* Create the debugfs files and directories */ 2875 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2876 { 2877 struct dentry *dir = trans->dbgfs_dir; 2878 2879 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2880 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2881 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2882 DEBUGFS_ADD_FILE(csr, dir, 0200); 2883 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2884 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2885 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2886 } 2887 2888 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2889 { 2890 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2891 struct cont_rec *data = &trans_pcie->fw_mon_data; 2892 2893 mutex_lock(&data->mutex); 2894 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2895 mutex_unlock(&data->mutex); 2896 } 2897 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2898 2899 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2900 { 2901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2902 u32 cmdlen = 0; 2903 int i; 2904 2905 for (i = 0; i < trans_pcie->max_tbs; i++) 2906 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2907 2908 return cmdlen; 2909 } 2910 2911 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2912 struct iwl_fw_error_dump_data **data, 2913 int allocated_rb_nums) 2914 { 2915 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2916 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2917 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2918 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2919 u32 i, r, j, rb_len = 0; 2920 2921 spin_lock(&rxq->lock); 2922 2923 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2924 2925 for (i = rxq->read, j = 0; 2926 i != r && j < allocated_rb_nums; 2927 i = (i + 1) & RX_QUEUE_MASK, j++) { 2928 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2929 struct iwl_fw_error_dump_rb *rb; 2930 2931 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2932 DMA_FROM_DEVICE); 2933 2934 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2935 2936 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2937 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2938 rb = (void *)(*data)->data; 2939 rb->index = cpu_to_le32(i); 2940 memcpy(rb->data, page_address(rxb->page), max_len); 2941 /* remap the page for the free benefit */ 2942 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2943 max_len, 2944 DMA_FROM_DEVICE); 2945 2946 *data = iwl_fw_error_next_data(*data); 2947 } 2948 2949 spin_unlock(&rxq->lock); 2950 2951 return rb_len; 2952 } 2953 #define IWL_CSR_TO_DUMP (0x250) 2954 2955 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2956 struct iwl_fw_error_dump_data **data) 2957 { 2958 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2959 __le32 *val; 2960 int i; 2961 2962 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2963 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2964 val = (void *)(*data)->data; 2965 2966 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2967 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2968 2969 *data = iwl_fw_error_next_data(*data); 2970 2971 return csr_len; 2972 } 2973 2974 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2975 struct iwl_fw_error_dump_data **data) 2976 { 2977 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2978 unsigned long flags; 2979 __le32 *val; 2980 int i; 2981 2982 if (!iwl_trans_grab_nic_access(trans, &flags)) 2983 return 0; 2984 2985 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2986 (*data)->len = cpu_to_le32(fh_regs_len); 2987 val = (void *)(*data)->data; 2988 2989 if (!trans->cfg->gen2) 2990 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2991 i += sizeof(u32)) 2992 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2993 else 2994 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2995 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2996 i += sizeof(u32)) 2997 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2998 i)); 2999 3000 iwl_trans_release_nic_access(trans, &flags); 3001 3002 *data = iwl_fw_error_next_data(*data); 3003 3004 return sizeof(**data) + fh_regs_len; 3005 } 3006 3007 static u32 3008 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3009 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3010 u32 monitor_len) 3011 { 3012 u32 buf_size_in_dwords = (monitor_len >> 2); 3013 u32 *buffer = (u32 *)fw_mon_data->data; 3014 unsigned long flags; 3015 u32 i; 3016 3017 if (!iwl_trans_grab_nic_access(trans, &flags)) 3018 return 0; 3019 3020 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3021 for (i = 0; i < buf_size_in_dwords; i++) 3022 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3023 MON_DMARB_RD_DATA_ADDR); 3024 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3025 3026 iwl_trans_release_nic_access(trans, &flags); 3027 3028 return monitor_len; 3029 } 3030 3031 static void 3032 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3033 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3034 { 3035 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3036 3037 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3038 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3039 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3040 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3041 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3042 } else if (trans->dbg.dest_tlv) { 3043 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3044 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3045 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3046 } else { 3047 base = MON_BUFF_BASE_ADDR; 3048 write_ptr = MON_BUFF_WRPTR; 3049 wrap_cnt = MON_BUFF_CYCLE_CNT; 3050 } 3051 3052 write_ptr_val = iwl_read_prph(trans, write_ptr); 3053 fw_mon_data->fw_mon_cycle_cnt = 3054 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3055 fw_mon_data->fw_mon_base_ptr = 3056 cpu_to_le32(iwl_read_prph(trans, base)); 3057 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3058 fw_mon_data->fw_mon_base_high_ptr = 3059 cpu_to_le32(iwl_read_prph(trans, base_high)); 3060 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3061 } 3062 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3063 } 3064 3065 static u32 3066 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3067 struct iwl_fw_error_dump_data **data, 3068 u32 monitor_len) 3069 { 3070 u32 len = 0; 3071 3072 if (trans->dbg.dest_tlv || 3073 (trans->dbg.num_blocks && 3074 (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3075 trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3076 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3077 3078 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3079 fw_mon_data = (void *)(*data)->data; 3080 3081 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3082 3083 len += sizeof(**data) + sizeof(*fw_mon_data); 3084 if (trans->dbg.num_blocks) { 3085 memcpy(fw_mon_data->data, 3086 trans->dbg.fw_mon[0].block, 3087 trans->dbg.fw_mon[0].size); 3088 3089 monitor_len = trans->dbg.fw_mon[0].size; 3090 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3091 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3092 /* 3093 * Update pointers to reflect actual values after 3094 * shifting 3095 */ 3096 if (trans->dbg.dest_tlv->version) { 3097 base = (iwl_read_prph(trans, base) & 3098 IWL_LDBG_M2S_BUF_BA_MSK) << 3099 trans->dbg.dest_tlv->base_shift; 3100 base *= IWL_M2S_UNIT_SIZE; 3101 base += trans->cfg->smem_offset; 3102 } else { 3103 base = iwl_read_prph(trans, base) << 3104 trans->dbg.dest_tlv->base_shift; 3105 } 3106 3107 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3108 monitor_len / sizeof(u32)); 3109 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3110 monitor_len = 3111 iwl_trans_pci_dump_marbh_monitor(trans, 3112 fw_mon_data, 3113 monitor_len); 3114 } else { 3115 /* Didn't match anything - output no monitor data */ 3116 monitor_len = 0; 3117 } 3118 3119 len += monitor_len; 3120 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3121 } 3122 3123 return len; 3124 } 3125 3126 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3127 { 3128 if (trans->dbg.num_blocks) { 3129 *len += sizeof(struct iwl_fw_error_dump_data) + 3130 sizeof(struct iwl_fw_error_dump_fw_mon) + 3131 trans->dbg.fw_mon[0].size; 3132 return trans->dbg.fw_mon[0].size; 3133 } else if (trans->dbg.dest_tlv) { 3134 u32 base, end, cfg_reg, monitor_len; 3135 3136 if (trans->dbg.dest_tlv->version == 1) { 3137 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3138 cfg_reg = iwl_read_prph(trans, cfg_reg); 3139 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3140 trans->dbg.dest_tlv->base_shift; 3141 base *= IWL_M2S_UNIT_SIZE; 3142 base += trans->cfg->smem_offset; 3143 3144 monitor_len = 3145 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3146 trans->dbg.dest_tlv->end_shift; 3147 monitor_len *= IWL_M2S_UNIT_SIZE; 3148 } else { 3149 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3150 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3151 3152 base = iwl_read_prph(trans, base) << 3153 trans->dbg.dest_tlv->base_shift; 3154 end = iwl_read_prph(trans, end) << 3155 trans->dbg.dest_tlv->end_shift; 3156 3157 /* Make "end" point to the actual end */ 3158 if (trans->cfg->device_family >= 3159 IWL_DEVICE_FAMILY_8000 || 3160 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3161 end += (1 << trans->dbg.dest_tlv->end_shift); 3162 monitor_len = end - base; 3163 } 3164 *len += sizeof(struct iwl_fw_error_dump_data) + 3165 sizeof(struct iwl_fw_error_dump_fw_mon) + 3166 monitor_len; 3167 return monitor_len; 3168 } 3169 return 0; 3170 } 3171 3172 static struct iwl_trans_dump_data 3173 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3174 u32 dump_mask) 3175 { 3176 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3177 struct iwl_fw_error_dump_data *data; 3178 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3179 struct iwl_fw_error_dump_txcmd *txcmd; 3180 struct iwl_trans_dump_data *dump_data; 3181 u32 len, num_rbs = 0, monitor_len = 0; 3182 int i, ptr; 3183 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3184 !trans->cfg->mq_rx_supported && 3185 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3186 3187 if (!dump_mask) 3188 return NULL; 3189 3190 /* transport dump header */ 3191 len = sizeof(*dump_data); 3192 3193 /* host commands */ 3194 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3195 len += sizeof(*data) + 3196 cmdq->n_window * (sizeof(*txcmd) + 3197 TFD_MAX_PAYLOAD_SIZE); 3198 3199 /* FW monitor */ 3200 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3201 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3202 3203 /* CSR registers */ 3204 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3205 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3206 3207 /* FH registers */ 3208 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3209 if (trans->cfg->gen2) 3210 len += sizeof(*data) + 3211 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3212 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3213 else 3214 len += sizeof(*data) + 3215 (FH_MEM_UPPER_BOUND - 3216 FH_MEM_LOWER_BOUND); 3217 } 3218 3219 if (dump_rbs) { 3220 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3221 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3222 /* RBs */ 3223 num_rbs = 3224 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3225 & 0x0FFF; 3226 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3227 len += num_rbs * (sizeof(*data) + 3228 sizeof(struct iwl_fw_error_dump_rb) + 3229 (PAGE_SIZE << trans_pcie->rx_page_order)); 3230 } 3231 3232 /* Paged memory for gen2 HW */ 3233 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3234 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3235 len += sizeof(*data) + 3236 sizeof(struct iwl_fw_error_dump_paging) + 3237 trans->init_dram.paging[i].size; 3238 3239 dump_data = vzalloc(len); 3240 if (!dump_data) 3241 return NULL; 3242 3243 len = 0; 3244 data = (void *)dump_data->data; 3245 3246 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3247 u16 tfd_size = trans_pcie->tfd_size; 3248 3249 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3250 txcmd = (void *)data->data; 3251 spin_lock_bh(&cmdq->lock); 3252 ptr = cmdq->write_ptr; 3253 for (i = 0; i < cmdq->n_window; i++) { 3254 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3255 u32 caplen, cmdlen; 3256 3257 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3258 cmdq->tfds + 3259 tfd_size * ptr); 3260 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3261 3262 if (cmdlen) { 3263 len += sizeof(*txcmd) + caplen; 3264 txcmd->cmdlen = cpu_to_le32(cmdlen); 3265 txcmd->caplen = cpu_to_le32(caplen); 3266 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3267 caplen); 3268 txcmd = (void *)((u8 *)txcmd->data + caplen); 3269 } 3270 3271 ptr = iwl_queue_dec_wrap(trans, ptr); 3272 } 3273 spin_unlock_bh(&cmdq->lock); 3274 3275 data->len = cpu_to_le32(len); 3276 len += sizeof(*data); 3277 data = iwl_fw_error_next_data(data); 3278 } 3279 3280 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3281 len += iwl_trans_pcie_dump_csr(trans, &data); 3282 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3283 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3284 if (dump_rbs) 3285 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3286 3287 /* Paged memory for gen2 HW */ 3288 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3289 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3290 struct iwl_fw_error_dump_paging *paging; 3291 u32 page_len = trans->init_dram.paging[i].size; 3292 3293 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3294 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3295 paging = (void *)data->data; 3296 paging->index = cpu_to_le32(i); 3297 memcpy(paging->data, 3298 trans->init_dram.paging[i].block, page_len); 3299 data = iwl_fw_error_next_data(data); 3300 3301 len += sizeof(*data) + sizeof(*paging) + page_len; 3302 } 3303 } 3304 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3305 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3306 3307 dump_data->len = len; 3308 3309 return dump_data; 3310 } 3311 3312 #ifdef CONFIG_PM_SLEEP 3313 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3314 { 3315 return 0; 3316 } 3317 3318 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3319 { 3320 } 3321 #endif /* CONFIG_PM_SLEEP */ 3322 3323 #define IWL_TRANS_COMMON_OPS \ 3324 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3325 .write8 = iwl_trans_pcie_write8, \ 3326 .write32 = iwl_trans_pcie_write32, \ 3327 .read32 = iwl_trans_pcie_read32, \ 3328 .read_prph = iwl_trans_pcie_read_prph, \ 3329 .write_prph = iwl_trans_pcie_write_prph, \ 3330 .read_mem = iwl_trans_pcie_read_mem, \ 3331 .write_mem = iwl_trans_pcie_write_mem, \ 3332 .configure = iwl_trans_pcie_configure, \ 3333 .set_pmi = iwl_trans_pcie_set_pmi, \ 3334 .sw_reset = iwl_trans_pcie_sw_reset, \ 3335 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3336 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3337 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3338 .ref = iwl_trans_pcie_ref, \ 3339 .unref = iwl_trans_pcie_unref, \ 3340 .dump_data = iwl_trans_pcie_dump_data, \ 3341 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3342 .d3_resume = iwl_trans_pcie_d3_resume, \ 3343 .sync_nmi = iwl_trans_pcie_sync_nmi 3344 3345 #ifdef CONFIG_PM_SLEEP 3346 #define IWL_TRANS_PM_OPS \ 3347 .suspend = iwl_trans_pcie_suspend, \ 3348 .resume = iwl_trans_pcie_resume, 3349 #else 3350 #define IWL_TRANS_PM_OPS 3351 #endif /* CONFIG_PM_SLEEP */ 3352 3353 static const struct iwl_trans_ops trans_ops_pcie = { 3354 IWL_TRANS_COMMON_OPS, 3355 IWL_TRANS_PM_OPS 3356 .start_hw = iwl_trans_pcie_start_hw, 3357 .fw_alive = iwl_trans_pcie_fw_alive, 3358 .start_fw = iwl_trans_pcie_start_fw, 3359 .stop_device = iwl_trans_pcie_stop_device, 3360 3361 .send_cmd = iwl_trans_pcie_send_hcmd, 3362 3363 .tx = iwl_trans_pcie_tx, 3364 .reclaim = iwl_trans_pcie_reclaim, 3365 3366 .txq_disable = iwl_trans_pcie_txq_disable, 3367 .txq_enable = iwl_trans_pcie_txq_enable, 3368 3369 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3370 3371 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3372 3373 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3374 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3375 #ifdef CONFIG_IWLWIFI_DEBUGFS 3376 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3377 #endif 3378 }; 3379 3380 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3381 IWL_TRANS_COMMON_OPS, 3382 IWL_TRANS_PM_OPS 3383 .start_hw = iwl_trans_pcie_start_hw, 3384 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3385 .start_fw = iwl_trans_pcie_gen2_start_fw, 3386 .stop_device = iwl_trans_pcie_gen2_stop_device, 3387 3388 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3389 3390 .tx = iwl_trans_pcie_gen2_tx, 3391 .reclaim = iwl_trans_pcie_reclaim, 3392 3393 .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3394 3395 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3396 .txq_free = iwl_trans_pcie_dyn_txq_free, 3397 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3398 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3399 #ifdef CONFIG_IWLWIFI_DEBUGFS 3400 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3401 #endif 3402 }; 3403 3404 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3405 const struct pci_device_id *ent, 3406 const struct iwl_cfg *cfg) 3407 { 3408 struct iwl_trans_pcie *trans_pcie; 3409 struct iwl_trans *trans; 3410 int ret, addr_size; 3411 3412 ret = pcim_enable_device(pdev); 3413 if (ret) 3414 return ERR_PTR(ret); 3415 3416 if (cfg->gen2) 3417 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3418 &pdev->dev, cfg, &trans_ops_pcie_gen2); 3419 else 3420 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3421 &pdev->dev, cfg, &trans_ops_pcie); 3422 if (!trans) 3423 return ERR_PTR(-ENOMEM); 3424 3425 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3426 3427 trans_pcie->trans = trans; 3428 trans_pcie->opmode_down = true; 3429 spin_lock_init(&trans_pcie->irq_lock); 3430 spin_lock_init(&trans_pcie->reg_lock); 3431 mutex_init(&trans_pcie->mutex); 3432 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3433 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3434 if (!trans_pcie->tso_hdr_page) { 3435 ret = -ENOMEM; 3436 goto out_no_pci; 3437 } 3438 trans_pcie->debug_rfkill = -1; 3439 3440 if (!cfg->base_params->pcie_l1_allowed) { 3441 /* 3442 * W/A - seems to solve weird behavior. We need to remove this 3443 * if we don't want to stay in L1 all the time. This wastes a 3444 * lot of power. 3445 */ 3446 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3447 PCIE_LINK_STATE_L1 | 3448 PCIE_LINK_STATE_CLKPM); 3449 } 3450 3451 trans_pcie->def_rx_queue = 0; 3452 3453 if (cfg->use_tfh) { 3454 addr_size = 64; 3455 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3456 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3457 } else { 3458 addr_size = 36; 3459 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3460 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3461 } 3462 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3463 3464 pci_set_master(pdev); 3465 3466 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3467 if (!ret) 3468 ret = pci_set_consistent_dma_mask(pdev, 3469 DMA_BIT_MASK(addr_size)); 3470 if (ret) { 3471 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3472 if (!ret) 3473 ret = pci_set_consistent_dma_mask(pdev, 3474 DMA_BIT_MASK(32)); 3475 /* both attempts failed: */ 3476 if (ret) { 3477 dev_err(&pdev->dev, "No suitable DMA available\n"); 3478 goto out_no_pci; 3479 } 3480 } 3481 3482 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3483 if (ret) { 3484 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3485 goto out_no_pci; 3486 } 3487 3488 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3489 if (!trans_pcie->hw_base) { 3490 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3491 ret = -ENODEV; 3492 goto out_no_pci; 3493 } 3494 3495 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3496 * PCI Tx retries from interfering with C3 CPU state */ 3497 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3498 3499 trans_pcie->pci_dev = pdev; 3500 iwl_disable_interrupts(trans); 3501 3502 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3503 if (trans->hw_rev == 0xffffffff) { 3504 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3505 ret = -EIO; 3506 goto out_no_pci; 3507 } 3508 3509 /* 3510 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3511 * changed, and now the revision step also includes bit 0-1 (no more 3512 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3513 * in the old format. 3514 */ 3515 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3516 unsigned long flags; 3517 3518 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3519 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3520 3521 ret = iwl_pcie_prepare_card_hw(trans); 3522 if (ret) { 3523 IWL_WARN(trans, "Exit HW not ready\n"); 3524 goto out_no_pci; 3525 } 3526 3527 /* 3528 * in-order to recognize C step driver should read chip version 3529 * id located at the AUX bus MISC address space. 3530 */ 3531 ret = iwl_finish_nic_init(trans); 3532 if (ret) 3533 goto out_no_pci; 3534 3535 if (iwl_trans_grab_nic_access(trans, &flags)) { 3536 u32 hw_step; 3537 3538 hw_step = iwl_read_umac_prph_no_grab(trans, 3539 WFPM_CTRL_REG); 3540 hw_step |= ENABLE_WFPM; 3541 iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, 3542 hw_step); 3543 hw_step = iwl_read_prph_no_grab(trans, 3544 CNVI_AUX_MISC_CHIP); 3545 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3546 if (hw_step == 0x3) 3547 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3548 (SILICON_C_STEP << 2); 3549 iwl_trans_release_nic_access(trans, &flags); 3550 } 3551 } 3552 3553 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3554 3555 #if IS_ENABLED(CONFIG_IWLMVM) 3556 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3557 3558 if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { 3559 if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { 3560 trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; 3561 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3562 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3563 trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; 3564 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3565 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { 3566 trans->cfg = &iwlax211_2ax_cfg_so_gf_a0; 3567 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3568 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) { 3569 trans->cfg = &iwlax411_2ax_cfg_so_gf4_a0; 3570 } 3571 } else if (cfg == &iwl_ax101_cfg_qu_hr) { 3572 if ((CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3573 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3574 trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) || 3575 (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3576 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR1))) { 3577 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3578 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3579 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3580 trans->cfg = &iwl_ax101_cfg_qu_hr; 3581 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3582 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3583 trans->cfg = &iwl22000_2ax_cfg_jf; 3584 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3585 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3586 IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3587 ret = -EINVAL; 3588 goto out_no_pci; 3589 } else { 3590 IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3591 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3592 ret = -EINVAL; 3593 goto out_no_pci; 3594 } 3595 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3596 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3597 trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) { 3598 u32 hw_status; 3599 3600 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3601 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 3602 /* 3603 * b step fw is the same for physical card and fpga 3604 */ 3605 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3606 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 3607 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 3608 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 3609 } else { 3610 /* 3611 * a step no FPGA 3612 */ 3613 trans->cfg = &iwl22000_2ac_cfg_hr; 3614 } 3615 } 3616 #endif 3617 3618 iwl_pcie_set_interrupt_capa(pdev, trans); 3619 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3620 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3621 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3622 3623 /* Initialize the wait queue for commands */ 3624 init_waitqueue_head(&trans_pcie->wait_command_queue); 3625 3626 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3627 3628 if (trans_pcie->msix_enabled) { 3629 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3630 if (ret) 3631 goto out_no_pci; 3632 } else { 3633 ret = iwl_pcie_alloc_ict(trans); 3634 if (ret) 3635 goto out_no_pci; 3636 3637 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3638 iwl_pcie_isr, 3639 iwl_pcie_irq_handler, 3640 IRQF_SHARED, DRV_NAME, trans); 3641 if (ret) { 3642 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3643 goto out_free_ict; 3644 } 3645 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3646 } 3647 3648 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3649 WQ_HIGHPRI | WQ_UNBOUND, 1); 3650 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3651 3652 #ifdef CONFIG_IWLWIFI_DEBUGFS 3653 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3654 mutex_init(&trans_pcie->fw_mon_data.mutex); 3655 #endif 3656 3657 return trans; 3658 3659 out_free_ict: 3660 iwl_pcie_free_ict(trans); 3661 out_no_pci: 3662 free_percpu(trans_pcie->tso_hdr_page); 3663 iwl_trans_free(trans); 3664 return ERR_PTR(ret); 3665 } 3666 3667 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3668 { 3669 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3670 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3671 bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 3672 u32 inta_addr, sw_err_bit; 3673 3674 if (trans_pcie->msix_enabled) { 3675 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3676 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3677 } else { 3678 inta_addr = CSR_INT; 3679 sw_err_bit = CSR_INT_BIT_SW_ERR; 3680 } 3681 3682 /* if the interrupts were already disabled, there is no point in 3683 * calling iwl_disable_interrupts 3684 */ 3685 if (interrupts_enabled) 3686 iwl_disable_interrupts(trans); 3687 3688 iwl_force_nmi(trans); 3689 while (time_after(timeout, jiffies)) { 3690 u32 inta_hw = iwl_read32(trans, inta_addr); 3691 3692 /* Error detected by uCode */ 3693 if (inta_hw & sw_err_bit) { 3694 /* Clear causes register */ 3695 iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3696 break; 3697 } 3698 3699 mdelay(1); 3700 } 3701 3702 /* enable interrupts only if there were already enabled before this 3703 * function to avoid a case were the driver enable interrupts before 3704 * proper configurations were made 3705 */ 3706 if (interrupts_enabled) 3707 iwl_enable_interrupts(trans); 3708 3709 iwl_trans_fw_error(trans); 3710 } 3711