1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 - 2019 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 - 2019 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/pci.h> 65 #include <linux/pci-aspm.h> 66 #include <linux/interrupt.h> 67 #include <linux/debugfs.h> 68 #include <linux/sched.h> 69 #include <linux/bitops.h> 70 #include <linux/gfp.h> 71 #include <linux/vmalloc.h> 72 #include <linux/pm_runtime.h> 73 #include <linux/module.h> 74 #include <linux/wait.h> 75 76 #include "iwl-drv.h" 77 #include "iwl-trans.h" 78 #include "iwl-csr.h" 79 #include "iwl-prph.h" 80 #include "iwl-scd.h" 81 #include "iwl-agn-hw.h" 82 #include "fw/error-dump.h" 83 #include "fw/dbg.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92 { 93 #define PCI_DUMP_SIZE 64 94 #define PREFIX_LEN 32 95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96 struct pci_dev *pdev = trans_pcie->pci_dev; 97 u32 i, pos, alloc_size, *ptr, *buf; 98 char *prefix; 99 100 if (trans_pcie->pcie_dbg_dumped_once) 101 return; 102 103 /* Should be a multiple of 4 */ 104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105 /* Alloc a max size buffer */ 106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108 else 109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110 buf = kmalloc(alloc_size, GFP_ATOMIC); 111 if (!buf) 112 return; 113 prefix = (char *)buf + alloc_size - PREFIX_LEN; 114 115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116 117 /* Print wifi device registers */ 118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119 IWL_ERR(trans, "iwlwifi device config registers:\n"); 120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121 if (pci_read_config_dword(pdev, i, ptr)) 122 goto err_read; 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127 *ptr = iwl_read32(trans, i); 128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129 130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131 if (pos) { 132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134 if (pci_read_config_dword(pdev, pos + i, ptr)) 135 goto err_read; 136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137 32, 4, buf, i, 0); 138 } 139 140 /* Print parent device registers next */ 141 if (!pdev->bus->self) 142 goto out; 143 144 pdev = pdev->bus->self; 145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146 147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148 pci_name(pdev)); 149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150 if (pci_read_config_dword(pdev, i, ptr)) 151 goto err_read; 152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153 154 /* Print root port AER registers */ 155 pos = 0; 156 pdev = pcie_find_root_port(pdev); 157 if (pdev) 158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159 if (pos) { 160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161 pci_name(pdev)); 162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164 if (pci_read_config_dword(pdev, pos + i, ptr)) 165 goto err_read; 166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167 4, buf, i, 0); 168 } 169 goto out; 170 171 err_read: 172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173 IWL_ERR(trans, "Read failed at 0x%X\n", i); 174 out: 175 trans_pcie->pcie_dbg_dumped_once = 1; 176 kfree(buf); 177 } 178 179 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 180 { 181 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 182 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 183 BIT(trans->cfg->csr->flag_sw_reset)); 184 usleep_range(5000, 6000); 185 } 186 187 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 188 { 189 int i; 190 191 for (i = 0; i < trans->num_blocks; i++) { 192 dma_free_coherent(trans->dev, trans->fw_mon[i].size, 193 trans->fw_mon[i].block, 194 trans->fw_mon[i].physical); 195 trans->fw_mon[i].block = NULL; 196 trans->fw_mon[i].physical = 0; 197 trans->fw_mon[i].size = 0; 198 trans->num_blocks--; 199 } 200 } 201 202 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 203 u8 max_power, u8 min_power) 204 { 205 void *cpu_addr = NULL; 206 dma_addr_t phys = 0; 207 u32 size = 0; 208 u8 power; 209 210 for (power = max_power; power >= min_power; power--) { 211 size = BIT(power); 212 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 213 GFP_KERNEL | __GFP_NOWARN | 214 __GFP_ZERO | __GFP_COMP); 215 if (!cpu_addr) 216 continue; 217 218 IWL_INFO(trans, 219 "Allocated 0x%08x bytes for firmware monitor.\n", 220 size); 221 break; 222 } 223 224 if (WARN_ON_ONCE(!cpu_addr)) 225 return; 226 227 if (power != max_power) 228 IWL_ERR(trans, 229 "Sorry - debug buffer is only %luK while you requested %luK\n", 230 (unsigned long)BIT(power - 10), 231 (unsigned long)BIT(max_power - 10)); 232 233 trans->fw_mon[trans->num_blocks].block = cpu_addr; 234 trans->fw_mon[trans->num_blocks].physical = phys; 235 trans->fw_mon[trans->num_blocks].size = size; 236 trans->num_blocks++; 237 } 238 239 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 240 { 241 if (!max_power) { 242 /* default max_power is maximum */ 243 max_power = 26; 244 } else { 245 max_power += 11; 246 } 247 248 if (WARN(max_power > 26, 249 "External buffer size for monitor is too big %d, check the FW TLV\n", 250 max_power)) 251 return; 252 253 /* 254 * This function allocats the default fw monitor. 255 * The optional additional ones will be allocated in runtime 256 */ 257 if (trans->num_blocks) 258 return; 259 260 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 261 } 262 263 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 264 { 265 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 266 ((reg & 0x0000ffff) | (2 << 28))); 267 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 268 } 269 270 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 271 { 272 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 273 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274 ((reg & 0x0000ffff) | (3 << 28))); 275 } 276 277 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 278 { 279 if (trans->cfg->apmg_not_supported) 280 return; 281 282 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 283 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 284 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 285 ~APMG_PS_CTRL_MSK_PWR_SRC); 286 else 287 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 288 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 289 ~APMG_PS_CTRL_MSK_PWR_SRC); 290 } 291 292 /* PCI registers */ 293 #define PCI_CFG_RETRY_TIMEOUT 0x041 294 295 void iwl_pcie_apm_config(struct iwl_trans *trans) 296 { 297 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 298 u16 lctl; 299 u16 cap; 300 301 /* 302 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 303 * Check if BIOS (or OS) enabled L1-ASPM on this device. 304 * If so (likely), disable L0S, so device moves directly L0->L1; 305 * costs negligible amount of power savings. 306 * If not (unlikely), enable L0S, so there is at least some 307 * power savings, even without L1. 308 */ 309 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 310 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 311 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 312 else 313 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 314 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 315 316 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 317 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 318 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 319 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 320 trans->ltr_enabled ? "En" : "Dis"); 321 } 322 323 /* 324 * Start up NIC's basic functionality after it has been reset 325 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 326 * NOTE: This does not load uCode nor start the embedded processor 327 */ 328 static int iwl_pcie_apm_init(struct iwl_trans *trans) 329 { 330 int ret; 331 332 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 333 334 /* 335 * Use "set_bit" below rather than "write", to preserve any hardware 336 * bits already set by default after reset. 337 */ 338 339 /* Disable L0S exit timer (platform NMI Work/Around) */ 340 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 341 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 342 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 343 344 /* 345 * Disable L0s without affecting L1; 346 * don't wait for ICH L0s (ICH bug W/A) 347 */ 348 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 349 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 350 351 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 352 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 353 354 /* 355 * Enable HAP INTA (interrupt from management bus) to 356 * wake device's PCI Express link L1a -> L0s 357 */ 358 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 359 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 360 361 iwl_pcie_apm_config(trans); 362 363 /* Configure analog phase-lock-loop before activating to D0A */ 364 if (trans->cfg->base_params->pll_cfg) 365 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 366 367 ret = iwl_finish_nic_init(trans); 368 if (ret) 369 return ret; 370 371 if (trans->cfg->host_interrupt_operation_mode) { 372 /* 373 * This is a bit of an abuse - This is needed for 7260 / 3160 374 * only check host_interrupt_operation_mode even if this is 375 * not related to host_interrupt_operation_mode. 376 * 377 * Enable the oscillator to count wake up time for L1 exit. This 378 * consumes slightly more power (100uA) - but allows to be sure 379 * that we wake up from L1 on time. 380 * 381 * This looks weird: read twice the same register, discard the 382 * value, set a bit, and yet again, read that same register 383 * just to discard the value. But that's the way the hardware 384 * seems to like it. 385 */ 386 iwl_read_prph(trans, OSC_CLK); 387 iwl_read_prph(trans, OSC_CLK); 388 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 389 iwl_read_prph(trans, OSC_CLK); 390 iwl_read_prph(trans, OSC_CLK); 391 } 392 393 /* 394 * Enable DMA clock and wait for it to stabilize. 395 * 396 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 397 * bits do not disable clocks. This preserves any hardware 398 * bits already set by default in "CLK_CTRL_REG" after reset. 399 */ 400 if (!trans->cfg->apmg_not_supported) { 401 iwl_write_prph(trans, APMG_CLK_EN_REG, 402 APMG_CLK_VAL_DMA_CLK_RQT); 403 udelay(20); 404 405 /* Disable L1-Active */ 406 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 407 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 408 409 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 410 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 411 APMG_RTC_INT_STT_RFKILL); 412 } 413 414 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 415 416 return 0; 417 } 418 419 /* 420 * Enable LP XTAL to avoid HW bug where device may consume much power if 421 * FW is not loaded after device reset. LP XTAL is disabled by default 422 * after device HW reset. Do it only if XTAL is fed by internal source. 423 * Configure device's "persistence" mode to avoid resetting XTAL again when 424 * SHRD_HW_RST occurs in S3. 425 */ 426 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 427 { 428 int ret; 429 u32 apmg_gp1_reg; 430 u32 apmg_xtal_cfg_reg; 431 u32 dl_cfg_reg; 432 433 /* Force XTAL ON */ 434 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 435 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 436 437 iwl_trans_pcie_sw_reset(trans); 438 439 ret = iwl_finish_nic_init(trans); 440 if (WARN_ON(ret)) { 441 /* Release XTAL ON request */ 442 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 443 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 444 return; 445 } 446 447 /* 448 * Clear "disable persistence" to avoid LP XTAL resetting when 449 * SHRD_HW_RST is applied in S3. 450 */ 451 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 452 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 453 454 /* 455 * Force APMG XTAL to be active to prevent its disabling by HW 456 * caused by APMG idle state. 457 */ 458 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 459 SHR_APMG_XTAL_CFG_REG); 460 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 461 apmg_xtal_cfg_reg | 462 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 463 464 iwl_trans_pcie_sw_reset(trans); 465 466 /* Enable LP XTAL by indirect access through CSR */ 467 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 468 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 469 SHR_APMG_GP1_WF_XTAL_LP_EN | 470 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 471 472 /* Clear delay line clock power up */ 473 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 474 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 475 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 476 477 /* 478 * Enable persistence mode to avoid LP XTAL resetting when 479 * SHRD_HW_RST is applied in S3. 480 */ 481 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 482 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 483 484 /* 485 * Clear "initialization complete" bit to move adapter from 486 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 487 */ 488 iwl_clear_bit(trans, CSR_GP_CNTRL, 489 BIT(trans->cfg->csr->flag_init_done)); 490 491 /* Activates XTAL resources monitor */ 492 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 493 CSR_MONITOR_XTAL_RESOURCES); 494 495 /* Release XTAL ON request */ 496 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 497 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 498 udelay(10); 499 500 /* Release APMG XTAL */ 501 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 502 apmg_xtal_cfg_reg & 503 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 504 } 505 506 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 507 { 508 int ret; 509 510 /* stop device's busmaster DMA activity */ 511 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 512 BIT(trans->cfg->csr->flag_stop_master)); 513 514 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 515 BIT(trans->cfg->csr->flag_master_dis), 516 BIT(trans->cfg->csr->flag_master_dis), 100); 517 if (ret < 0) 518 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 519 520 IWL_DEBUG_INFO(trans, "stop master\n"); 521 } 522 523 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 524 { 525 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 526 527 if (op_mode_leave) { 528 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 529 iwl_pcie_apm_init(trans); 530 531 /* inform ME that we are leaving */ 532 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 533 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 534 APMG_PCIDEV_STT_VAL_WAKE_ME); 535 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 536 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 537 CSR_RESET_LINK_PWR_MGMT_DISABLED); 538 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 539 CSR_HW_IF_CONFIG_REG_PREPARE | 540 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 541 mdelay(1); 542 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543 CSR_RESET_LINK_PWR_MGMT_DISABLED); 544 } 545 mdelay(5); 546 } 547 548 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 549 550 /* Stop device's DMA activity */ 551 iwl_pcie_apm_stop_master(trans); 552 553 if (trans->cfg->lp_xtal_workaround) { 554 iwl_pcie_apm_lp_xtal_enable(trans); 555 return; 556 } 557 558 iwl_trans_pcie_sw_reset(trans); 559 560 /* 561 * Clear "initialization complete" bit to move adapter from 562 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 563 */ 564 iwl_clear_bit(trans, CSR_GP_CNTRL, 565 BIT(trans->cfg->csr->flag_init_done)); 566 } 567 568 static int iwl_pcie_nic_init(struct iwl_trans *trans) 569 { 570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 571 int ret; 572 573 /* nic_init */ 574 spin_lock(&trans_pcie->irq_lock); 575 ret = iwl_pcie_apm_init(trans); 576 spin_unlock(&trans_pcie->irq_lock); 577 578 if (ret) 579 return ret; 580 581 iwl_pcie_set_pwr(trans, false); 582 583 iwl_op_mode_nic_config(trans->op_mode); 584 585 /* Allocate the RX queue, or reset if it is already allocated */ 586 iwl_pcie_rx_init(trans); 587 588 /* Allocate or reset and init all Tx and Command queues */ 589 if (iwl_pcie_tx_init(trans)) 590 return -ENOMEM; 591 592 if (trans->cfg->base_params->shadow_reg_enable) { 593 /* enable shadow regs in HW */ 594 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 595 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 596 } 597 598 return 0; 599 } 600 601 #define HW_READY_TIMEOUT (50) 602 603 /* Note: returns poll_bit return value, which is >= 0 if success */ 604 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 605 { 606 int ret; 607 608 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 609 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 610 611 /* See if we got it */ 612 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 613 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 614 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 615 HW_READY_TIMEOUT); 616 617 if (ret >= 0) 618 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 619 620 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 621 return ret; 622 } 623 624 /* Note: returns standard 0/-ERROR code */ 625 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 626 { 627 int ret; 628 int t = 0; 629 int iter; 630 631 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 632 633 ret = iwl_pcie_set_hw_ready(trans); 634 /* If the card is ready, exit 0 */ 635 if (ret >= 0) 636 return 0; 637 638 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 639 CSR_RESET_LINK_PWR_MGMT_DISABLED); 640 usleep_range(1000, 2000); 641 642 for (iter = 0; iter < 10; iter++) { 643 /* If HW is not ready, prepare the conditions to check again */ 644 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 645 CSR_HW_IF_CONFIG_REG_PREPARE); 646 647 do { 648 ret = iwl_pcie_set_hw_ready(trans); 649 if (ret >= 0) 650 return 0; 651 652 usleep_range(200, 1000); 653 t += 200; 654 } while (t < 150000); 655 msleep(25); 656 } 657 658 IWL_ERR(trans, "Couldn't prepare the card\n"); 659 660 return ret; 661 } 662 663 /* 664 * ucode 665 */ 666 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 667 u32 dst_addr, dma_addr_t phy_addr, 668 u32 byte_cnt) 669 { 670 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 671 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 672 673 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 674 dst_addr); 675 676 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 677 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 678 679 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 680 (iwl_get_dma_hi_addr(phy_addr) 681 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 682 683 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 684 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 685 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 686 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 687 688 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 689 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 690 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 691 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 692 } 693 694 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 695 u32 dst_addr, dma_addr_t phy_addr, 696 u32 byte_cnt) 697 { 698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 699 unsigned long flags; 700 int ret; 701 702 trans_pcie->ucode_write_complete = false; 703 704 if (!iwl_trans_grab_nic_access(trans, &flags)) 705 return -EIO; 706 707 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 708 byte_cnt); 709 iwl_trans_release_nic_access(trans, &flags); 710 711 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 712 trans_pcie->ucode_write_complete, 5 * HZ); 713 if (!ret) { 714 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 715 iwl_trans_pcie_dump_regs(trans); 716 return -ETIMEDOUT; 717 } 718 719 return 0; 720 } 721 722 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 723 const struct fw_desc *section) 724 { 725 u8 *v_addr; 726 dma_addr_t p_addr; 727 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 728 int ret = 0; 729 730 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 731 section_num); 732 733 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 734 GFP_KERNEL | __GFP_NOWARN); 735 if (!v_addr) { 736 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 737 chunk_sz = PAGE_SIZE; 738 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 739 &p_addr, GFP_KERNEL); 740 if (!v_addr) 741 return -ENOMEM; 742 } 743 744 for (offset = 0; offset < section->len; offset += chunk_sz) { 745 u32 copy_size, dst_addr; 746 bool extended_addr = false; 747 748 copy_size = min_t(u32, chunk_sz, section->len - offset); 749 dst_addr = section->offset + offset; 750 751 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 752 dst_addr <= IWL_FW_MEM_EXTENDED_END) 753 extended_addr = true; 754 755 if (extended_addr) 756 iwl_set_bits_prph(trans, LMPM_CHICK, 757 LMPM_CHICK_EXTENDED_ADDR_SPACE); 758 759 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 760 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 761 copy_size); 762 763 if (extended_addr) 764 iwl_clear_bits_prph(trans, LMPM_CHICK, 765 LMPM_CHICK_EXTENDED_ADDR_SPACE); 766 767 if (ret) { 768 IWL_ERR(trans, 769 "Could not load the [%d] uCode section\n", 770 section_num); 771 break; 772 } 773 } 774 775 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 776 return ret; 777 } 778 779 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 780 const struct fw_img *image, 781 int cpu, 782 int *first_ucode_section) 783 { 784 int shift_param; 785 int i, ret = 0, sec_num = 0x1; 786 u32 val, last_read_idx = 0; 787 788 if (cpu == 1) { 789 shift_param = 0; 790 *first_ucode_section = 0; 791 } else { 792 shift_param = 16; 793 (*first_ucode_section)++; 794 } 795 796 for (i = *first_ucode_section; i < image->num_sec; i++) { 797 last_read_idx = i; 798 799 /* 800 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 801 * CPU1 to CPU2. 802 * PAGING_SEPARATOR_SECTION delimiter - separate between 803 * CPU2 non paged to CPU2 paging sec. 804 */ 805 if (!image->sec[i].data || 806 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 807 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 808 IWL_DEBUG_FW(trans, 809 "Break since Data not valid or Empty section, sec = %d\n", 810 i); 811 break; 812 } 813 814 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 815 if (ret) 816 return ret; 817 818 /* Notify ucode of loaded section number and status */ 819 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 820 val = val | (sec_num << shift_param); 821 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 822 823 sec_num = (sec_num << 1) | 0x1; 824 } 825 826 *first_ucode_section = last_read_idx; 827 828 iwl_enable_interrupts(trans); 829 830 if (trans->cfg->use_tfh) { 831 if (cpu == 1) 832 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 833 0xFFFF); 834 else 835 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 836 0xFFFFFFFF); 837 } else { 838 if (cpu == 1) 839 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 840 0xFFFF); 841 else 842 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 843 0xFFFFFFFF); 844 } 845 846 return 0; 847 } 848 849 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 850 const struct fw_img *image, 851 int cpu, 852 int *first_ucode_section) 853 { 854 int i, ret = 0; 855 u32 last_read_idx = 0; 856 857 if (cpu == 1) 858 *first_ucode_section = 0; 859 else 860 (*first_ucode_section)++; 861 862 for (i = *first_ucode_section; i < image->num_sec; i++) { 863 last_read_idx = i; 864 865 /* 866 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 867 * CPU1 to CPU2. 868 * PAGING_SEPARATOR_SECTION delimiter - separate between 869 * CPU2 non paged to CPU2 paging sec. 870 */ 871 if (!image->sec[i].data || 872 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 873 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 874 IWL_DEBUG_FW(trans, 875 "Break since Data not valid or Empty section, sec = %d\n", 876 i); 877 break; 878 } 879 880 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 881 if (ret) 882 return ret; 883 } 884 885 *first_ucode_section = last_read_idx; 886 887 return 0; 888 } 889 890 void iwl_pcie_apply_destination(struct iwl_trans *trans) 891 { 892 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 893 int i; 894 895 if (trans->ini_valid) { 896 if (!trans->num_blocks) 897 return; 898 899 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 900 trans->fw_mon[0].physical >> 901 MON_BUFF_SHIFT_VER2); 902 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 903 (trans->fw_mon[0].physical + 904 trans->fw_mon[0].size - 256) >> 905 MON_BUFF_SHIFT_VER2); 906 return; 907 } 908 909 IWL_INFO(trans, "Applying debug destination %s\n", 910 get_fw_dbg_mode_string(dest->monitor_mode)); 911 912 if (dest->monitor_mode == EXTERNAL_MODE) 913 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 914 else 915 IWL_WARN(trans, "PCI should have external buffer debug\n"); 916 917 for (i = 0; i < trans->dbg_n_dest_reg; i++) { 918 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 919 u32 val = le32_to_cpu(dest->reg_ops[i].val); 920 921 switch (dest->reg_ops[i].op) { 922 case CSR_ASSIGN: 923 iwl_write32(trans, addr, val); 924 break; 925 case CSR_SETBIT: 926 iwl_set_bit(trans, addr, BIT(val)); 927 break; 928 case CSR_CLEARBIT: 929 iwl_clear_bit(trans, addr, BIT(val)); 930 break; 931 case PRPH_ASSIGN: 932 iwl_write_prph(trans, addr, val); 933 break; 934 case PRPH_SETBIT: 935 iwl_set_bits_prph(trans, addr, BIT(val)); 936 break; 937 case PRPH_CLEARBIT: 938 iwl_clear_bits_prph(trans, addr, BIT(val)); 939 break; 940 case PRPH_BLOCKBIT: 941 if (iwl_read_prph(trans, addr) & BIT(val)) { 942 IWL_ERR(trans, 943 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 944 val, addr); 945 goto monitor; 946 } 947 break; 948 default: 949 IWL_ERR(trans, "FW debug - unknown OP %d\n", 950 dest->reg_ops[i].op); 951 break; 952 } 953 } 954 955 monitor: 956 if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { 957 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 958 trans->fw_mon[0].physical >> dest->base_shift); 959 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 960 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 961 (trans->fw_mon[0].physical + 962 trans->fw_mon[0].size - 256) >> 963 dest->end_shift); 964 else 965 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 966 (trans->fw_mon[0].physical + 967 trans->fw_mon[0].size) >> 968 dest->end_shift); 969 } 970 } 971 972 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 973 const struct fw_img *image) 974 { 975 int ret = 0; 976 int first_ucode_section; 977 978 IWL_DEBUG_FW(trans, "working with %s CPU\n", 979 image->is_dual_cpus ? "Dual" : "Single"); 980 981 /* load to FW the binary non secured sections of CPU1 */ 982 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 983 if (ret) 984 return ret; 985 986 if (image->is_dual_cpus) { 987 /* set CPU2 header address */ 988 iwl_write_prph(trans, 989 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 990 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 991 992 /* load to FW the binary sections of CPU2 */ 993 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 994 &first_ucode_section); 995 if (ret) 996 return ret; 997 } 998 999 /* supported for 7000 only for the moment */ 1000 if (iwlwifi_mod_params.fw_monitor && 1001 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1002 iwl_pcie_alloc_fw_monitor(trans, 0); 1003 1004 if (trans->fw_mon[0].size) { 1005 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1006 trans->fw_mon[0].physical >> 4); 1007 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1008 (trans->fw_mon[0].physical + 1009 trans->fw_mon[0].size) >> 4); 1010 } 1011 } else if (iwl_pcie_dbg_on(trans)) { 1012 iwl_pcie_apply_destination(trans); 1013 } 1014 1015 iwl_enable_interrupts(trans); 1016 1017 /* release CPU reset */ 1018 iwl_write32(trans, CSR_RESET, 0); 1019 1020 return 0; 1021 } 1022 1023 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1024 const struct fw_img *image) 1025 { 1026 int ret = 0; 1027 int first_ucode_section; 1028 1029 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1030 image->is_dual_cpus ? "Dual" : "Single"); 1031 1032 if (iwl_pcie_dbg_on(trans)) 1033 iwl_pcie_apply_destination(trans); 1034 1035 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1036 iwl_read_prph(trans, WFPM_GP2)); 1037 1038 /* 1039 * Set default value. On resume reading the values that were 1040 * zeored can provide debug data on the resume flow. 1041 * This is for debugging only and has no functional impact. 1042 */ 1043 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1044 1045 /* configure the ucode to be ready to get the secured image */ 1046 /* release CPU reset */ 1047 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1048 1049 /* load to FW the binary Secured sections of CPU1 */ 1050 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1051 &first_ucode_section); 1052 if (ret) 1053 return ret; 1054 1055 /* load to FW the binary sections of CPU2 */ 1056 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1057 &first_ucode_section); 1058 } 1059 1060 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1061 { 1062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1063 bool hw_rfkill = iwl_is_rfkill_set(trans); 1064 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1065 bool report; 1066 1067 if (hw_rfkill) { 1068 set_bit(STATUS_RFKILL_HW, &trans->status); 1069 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1070 } else { 1071 clear_bit(STATUS_RFKILL_HW, &trans->status); 1072 if (trans_pcie->opmode_down) 1073 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1074 } 1075 1076 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1077 1078 if (prev != report) 1079 iwl_trans_pcie_rf_kill(trans, report); 1080 1081 return hw_rfkill; 1082 } 1083 1084 struct iwl_causes_list { 1085 u32 cause_num; 1086 u32 mask_reg; 1087 u8 addr; 1088 }; 1089 1090 static struct iwl_causes_list causes_list[] = { 1091 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1092 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1093 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1094 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1095 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1096 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1097 {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1098 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1099 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1100 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1101 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1102 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1103 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1104 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1105 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1106 }; 1107 1108 static struct iwl_causes_list causes_list_v2[] = { 1109 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1110 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1111 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1112 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1113 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1114 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1115 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 1116 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1117 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1118 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1119 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1120 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1121 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1122 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1123 }; 1124 1125 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1126 { 1127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1128 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1129 int i, arr_size = 1130 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 1131 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 1132 1133 /* 1134 * Access all non RX causes and map them to the default irq. 1135 * In case we are missing at least one interrupt vector, 1136 * the first interrupt vector will serve non-RX and FBQ causes. 1137 */ 1138 for (i = 0; i < arr_size; i++) { 1139 struct iwl_causes_list *causes = 1140 (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 1141 causes_list : causes_list_v2; 1142 1143 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1144 iwl_clear_bit(trans, causes[i].mask_reg, 1145 causes[i].cause_num); 1146 } 1147 } 1148 1149 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1150 { 1151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1152 u32 offset = 1153 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1154 u32 val, idx; 1155 1156 /* 1157 * The first RX queue - fallback queue, which is designated for 1158 * management frame, command responses etc, is always mapped to the 1159 * first interrupt vector. The other RX queues are mapped to 1160 * the other (N - 2) interrupt vectors. 1161 */ 1162 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1163 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1164 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1165 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1166 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1167 } 1168 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1169 1170 val = MSIX_FH_INT_CAUSES_Q(0); 1171 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1172 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1173 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1174 1175 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1176 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1177 } 1178 1179 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1180 { 1181 struct iwl_trans *trans = trans_pcie->trans; 1182 1183 if (!trans_pcie->msix_enabled) { 1184 if (trans->cfg->mq_rx_supported && 1185 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1186 iwl_write_umac_prph(trans, UREG_CHICK, 1187 UREG_CHICK_MSI_ENABLE); 1188 return; 1189 } 1190 /* 1191 * The IVAR table needs to be configured again after reset, 1192 * but if the device is disabled, we can't write to 1193 * prph. 1194 */ 1195 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1196 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1197 1198 /* 1199 * Each cause from the causes list above and the RX causes is 1200 * represented as a byte in the IVAR table. The first nibble 1201 * represents the bound interrupt vector of the cause, the second 1202 * represents no auto clear for this cause. This will be set if its 1203 * interrupt vector is bound to serve other causes. 1204 */ 1205 iwl_pcie_map_rx_causes(trans); 1206 1207 iwl_pcie_map_non_rx_causes(trans); 1208 } 1209 1210 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1211 { 1212 struct iwl_trans *trans = trans_pcie->trans; 1213 1214 iwl_pcie_conf_msix_hw(trans_pcie); 1215 1216 if (!trans_pcie->msix_enabled) 1217 return; 1218 1219 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1220 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1221 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1222 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1223 } 1224 1225 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1226 { 1227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1228 1229 lockdep_assert_held(&trans_pcie->mutex); 1230 1231 if (trans_pcie->is_down) 1232 return; 1233 1234 trans_pcie->is_down = true; 1235 1236 /* Stop dbgc before stopping device */ 1237 _iwl_fw_dbg_stop_recording(trans, NULL); 1238 1239 /* tell the device to stop sending interrupts */ 1240 iwl_disable_interrupts(trans); 1241 1242 /* device going down, Stop using ICT table */ 1243 iwl_pcie_disable_ict(trans); 1244 1245 /* 1246 * If a HW restart happens during firmware loading, 1247 * then the firmware loading might call this function 1248 * and later it might be called again due to the 1249 * restart. So don't process again if the device is 1250 * already dead. 1251 */ 1252 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1253 IWL_DEBUG_INFO(trans, 1254 "DEVICE_ENABLED bit was set and is now cleared\n"); 1255 iwl_pcie_tx_stop(trans); 1256 iwl_pcie_rx_stop(trans); 1257 1258 /* Power-down device's busmaster DMA clocks */ 1259 if (!trans->cfg->apmg_not_supported) { 1260 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1261 APMG_CLK_VAL_DMA_CLK_RQT); 1262 udelay(5); 1263 } 1264 } 1265 1266 /* Make sure (redundant) we've released our request to stay awake */ 1267 iwl_clear_bit(trans, CSR_GP_CNTRL, 1268 BIT(trans->cfg->csr->flag_mac_access_req)); 1269 1270 /* Stop the device, and put it in low power state */ 1271 iwl_pcie_apm_stop(trans, false); 1272 1273 iwl_trans_pcie_sw_reset(trans); 1274 1275 /* 1276 * Upon stop, the IVAR table gets erased, so msi-x won't 1277 * work. This causes a bug in RF-KILL flows, since the interrupt 1278 * that enables radio won't fire on the correct irq, and the 1279 * driver won't be able to handle the interrupt. 1280 * Configure the IVAR table again after reset. 1281 */ 1282 iwl_pcie_conf_msix_hw(trans_pcie); 1283 1284 /* 1285 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1286 * This is a bug in certain verions of the hardware. 1287 * Certain devices also keep sending HW RF kill interrupt all 1288 * the time, unless the interrupt is ACKed even if the interrupt 1289 * should be masked. Re-ACK all the interrupts here. 1290 */ 1291 iwl_disable_interrupts(trans); 1292 1293 /* clear all status bits */ 1294 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1295 clear_bit(STATUS_INT_ENABLED, &trans->status); 1296 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1297 1298 /* 1299 * Even if we stop the HW, we still want the RF kill 1300 * interrupt 1301 */ 1302 iwl_enable_rfkill_int(trans); 1303 1304 /* re-take ownership to prevent other users from stealing the device */ 1305 iwl_pcie_prepare_card_hw(trans); 1306 } 1307 1308 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1309 { 1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1311 1312 if (trans_pcie->msix_enabled) { 1313 int i; 1314 1315 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1316 synchronize_irq(trans_pcie->msix_entries[i].vector); 1317 } else { 1318 synchronize_irq(trans_pcie->pci_dev->irq); 1319 } 1320 } 1321 1322 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1323 const struct fw_img *fw, bool run_in_rfkill) 1324 { 1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1326 bool hw_rfkill; 1327 int ret; 1328 1329 /* This may fail if AMT took ownership of the device */ 1330 if (iwl_pcie_prepare_card_hw(trans)) { 1331 IWL_WARN(trans, "Exit HW not ready\n"); 1332 ret = -EIO; 1333 goto out; 1334 } 1335 1336 iwl_enable_rfkill_int(trans); 1337 1338 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1339 1340 /* 1341 * We enabled the RF-Kill interrupt and the handler may very 1342 * well be running. Disable the interrupts to make sure no other 1343 * interrupt can be fired. 1344 */ 1345 iwl_disable_interrupts(trans); 1346 1347 /* Make sure it finished running */ 1348 iwl_pcie_synchronize_irqs(trans); 1349 1350 mutex_lock(&trans_pcie->mutex); 1351 1352 /* If platform's RF_KILL switch is NOT set to KILL */ 1353 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1354 if (hw_rfkill && !run_in_rfkill) { 1355 ret = -ERFKILL; 1356 goto out; 1357 } 1358 1359 /* Someone called stop_device, don't try to start_fw */ 1360 if (trans_pcie->is_down) { 1361 IWL_WARN(trans, 1362 "Can't start_fw since the HW hasn't been started\n"); 1363 ret = -EIO; 1364 goto out; 1365 } 1366 1367 /* make sure rfkill handshake bits are cleared */ 1368 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1369 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1370 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1371 1372 /* clear (again), then enable host interrupts */ 1373 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1374 1375 ret = iwl_pcie_nic_init(trans); 1376 if (ret) { 1377 IWL_ERR(trans, "Unable to init nic\n"); 1378 goto out; 1379 } 1380 1381 /* 1382 * Now, we load the firmware and don't want to be interrupted, even 1383 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1384 * FH_TX interrupt which is needed to load the firmware). If the 1385 * RF-Kill switch is toggled, we will find out after having loaded 1386 * the firmware and return the proper value to the caller. 1387 */ 1388 iwl_enable_fw_load_int(trans); 1389 1390 /* really make sure rfkill handshake bits are cleared */ 1391 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1392 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1393 1394 /* Load the given image to the HW */ 1395 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1396 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1397 else 1398 ret = iwl_pcie_load_given_ucode(trans, fw); 1399 1400 /* re-check RF-Kill state since we may have missed the interrupt */ 1401 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1402 if (hw_rfkill && !run_in_rfkill) 1403 ret = -ERFKILL; 1404 1405 out: 1406 mutex_unlock(&trans_pcie->mutex); 1407 return ret; 1408 } 1409 1410 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1411 { 1412 iwl_pcie_reset_ict(trans); 1413 iwl_pcie_tx_start(trans, scd_addr); 1414 } 1415 1416 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1417 bool was_in_rfkill) 1418 { 1419 bool hw_rfkill; 1420 1421 /* 1422 * Check again since the RF kill state may have changed while 1423 * all the interrupts were disabled, in this case we couldn't 1424 * receive the RF kill interrupt and update the state in the 1425 * op_mode. 1426 * Don't call the op_mode if the rkfill state hasn't changed. 1427 * This allows the op_mode to call stop_device from the rfkill 1428 * notification without endless recursion. Under very rare 1429 * circumstances, we might have a small recursion if the rfkill 1430 * state changed exactly now while we were called from stop_device. 1431 * This is very unlikely but can happen and is supported. 1432 */ 1433 hw_rfkill = iwl_is_rfkill_set(trans); 1434 if (hw_rfkill) { 1435 set_bit(STATUS_RFKILL_HW, &trans->status); 1436 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1437 } else { 1438 clear_bit(STATUS_RFKILL_HW, &trans->status); 1439 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1440 } 1441 if (hw_rfkill != was_in_rfkill) 1442 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1443 } 1444 1445 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1446 { 1447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1448 bool was_in_rfkill; 1449 1450 mutex_lock(&trans_pcie->mutex); 1451 trans_pcie->opmode_down = true; 1452 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1453 _iwl_trans_pcie_stop_device(trans, low_power); 1454 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1455 mutex_unlock(&trans_pcie->mutex); 1456 } 1457 1458 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1459 { 1460 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1461 IWL_TRANS_GET_PCIE_TRANS(trans); 1462 1463 lockdep_assert_held(&trans_pcie->mutex); 1464 1465 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1466 state ? "disabled" : "enabled"); 1467 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1468 if (trans->cfg->gen2) 1469 _iwl_trans_pcie_gen2_stop_device(trans, true); 1470 else 1471 _iwl_trans_pcie_stop_device(trans, true); 1472 } 1473 } 1474 1475 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1476 bool reset) 1477 { 1478 if (!reset) { 1479 /* Enable persistence mode to avoid reset */ 1480 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1481 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1482 } 1483 1484 iwl_disable_interrupts(trans); 1485 1486 /* 1487 * in testing mode, the host stays awake and the 1488 * hardware won't be reset (not even partially) 1489 */ 1490 if (test) 1491 return; 1492 1493 iwl_pcie_disable_ict(trans); 1494 1495 iwl_pcie_synchronize_irqs(trans); 1496 1497 iwl_clear_bit(trans, CSR_GP_CNTRL, 1498 BIT(trans->cfg->csr->flag_mac_access_req)); 1499 iwl_clear_bit(trans, CSR_GP_CNTRL, 1500 BIT(trans->cfg->csr->flag_init_done)); 1501 1502 if (reset) { 1503 /* 1504 * reset TX queues -- some of their registers reset during S3 1505 * so if we don't reset everything here the D3 image would try 1506 * to execute some invalid memory upon resume 1507 */ 1508 iwl_trans_pcie_tx_reset(trans); 1509 } 1510 1511 iwl_pcie_set_pwr(trans, true); 1512 } 1513 1514 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1515 enum iwl_d3_status *status, 1516 bool test, bool reset) 1517 { 1518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1519 u32 val; 1520 int ret; 1521 1522 if (test) { 1523 iwl_enable_interrupts(trans); 1524 *status = IWL_D3_STATUS_ALIVE; 1525 return 0; 1526 } 1527 1528 iwl_set_bit(trans, CSR_GP_CNTRL, 1529 BIT(trans->cfg->csr->flag_mac_access_req)); 1530 1531 ret = iwl_finish_nic_init(trans); 1532 if (ret) 1533 return ret; 1534 1535 /* 1536 * Reconfigure IVAR table in case of MSIX or reset ict table in 1537 * MSI mode since HW reset erased it. 1538 * Also enables interrupts - none will happen as 1539 * the device doesn't know we're waking it up, only when 1540 * the opmode actually tells it after this call. 1541 */ 1542 iwl_pcie_conf_msix_hw(trans_pcie); 1543 if (!trans_pcie->msix_enabled) 1544 iwl_pcie_reset_ict(trans); 1545 iwl_enable_interrupts(trans); 1546 1547 iwl_pcie_set_pwr(trans, false); 1548 1549 if (!reset) { 1550 iwl_clear_bit(trans, CSR_GP_CNTRL, 1551 BIT(trans->cfg->csr->flag_mac_access_req)); 1552 } else { 1553 iwl_trans_pcie_tx_reset(trans); 1554 1555 ret = iwl_pcie_rx_init(trans); 1556 if (ret) { 1557 IWL_ERR(trans, 1558 "Failed to resume the device (RX reset)\n"); 1559 return ret; 1560 } 1561 } 1562 1563 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1564 iwl_read_umac_prph(trans, WFPM_GP2)); 1565 1566 val = iwl_read32(trans, CSR_RESET); 1567 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1568 *status = IWL_D3_STATUS_RESET; 1569 else 1570 *status = IWL_D3_STATUS_ALIVE; 1571 1572 return 0; 1573 } 1574 1575 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1576 struct iwl_trans *trans) 1577 { 1578 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1579 int max_irqs, num_irqs, i, ret; 1580 u16 pci_cmd; 1581 1582 if (!trans->cfg->mq_rx_supported) 1583 goto enable_msi; 1584 1585 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 1586 for (i = 0; i < max_irqs; i++) 1587 trans_pcie->msix_entries[i].entry = i; 1588 1589 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1590 MSIX_MIN_INTERRUPT_VECTORS, 1591 max_irqs); 1592 if (num_irqs < 0) { 1593 IWL_DEBUG_INFO(trans, 1594 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1595 num_irqs); 1596 goto enable_msi; 1597 } 1598 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1599 1600 IWL_DEBUG_INFO(trans, 1601 "MSI-X enabled. %d interrupt vectors were allocated\n", 1602 num_irqs); 1603 1604 /* 1605 * In case the OS provides fewer interrupts than requested, different 1606 * causes will share the same interrupt vector as follows: 1607 * One interrupt less: non rx causes shared with FBQ. 1608 * Two interrupts less: non rx causes shared with FBQ and RSS. 1609 * More than two interrupts: we will use fewer RSS queues. 1610 */ 1611 if (num_irqs <= max_irqs - 2) { 1612 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1613 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1614 IWL_SHARED_IRQ_FIRST_RSS; 1615 } else if (num_irqs == max_irqs - 1) { 1616 trans_pcie->trans->num_rx_queues = num_irqs; 1617 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1618 } else { 1619 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1620 } 1621 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1622 1623 trans_pcie->alloc_vecs = num_irqs; 1624 trans_pcie->msix_enabled = true; 1625 return; 1626 1627 enable_msi: 1628 ret = pci_enable_msi(pdev); 1629 if (ret) { 1630 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1631 /* enable rfkill interrupt: hw bug w/a */ 1632 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1633 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1634 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1635 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1636 } 1637 } 1638 } 1639 1640 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1641 { 1642 int iter_rx_q, i, ret, cpu, offset; 1643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1644 1645 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1646 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1647 offset = 1 + i; 1648 for (; i < iter_rx_q ; i++) { 1649 /* 1650 * Get the cpu prior to the place to search 1651 * (i.e. return will be > i - 1). 1652 */ 1653 cpu = cpumask_next(i - offset, cpu_online_mask); 1654 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1655 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1656 &trans_pcie->affinity_mask[i]); 1657 if (ret) 1658 IWL_ERR(trans_pcie->trans, 1659 "Failed to set affinity mask for IRQ %d\n", 1660 i); 1661 } 1662 } 1663 1664 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1665 struct iwl_trans_pcie *trans_pcie) 1666 { 1667 int i; 1668 1669 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1670 int ret; 1671 struct msix_entry *msix_entry; 1672 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1673 1674 if (!qname) 1675 return -ENOMEM; 1676 1677 msix_entry = &trans_pcie->msix_entries[i]; 1678 ret = devm_request_threaded_irq(&pdev->dev, 1679 msix_entry->vector, 1680 iwl_pcie_msix_isr, 1681 (i == trans_pcie->def_irq) ? 1682 iwl_pcie_irq_msix_handler : 1683 iwl_pcie_irq_rx_msix_handler, 1684 IRQF_SHARED, 1685 qname, 1686 msix_entry); 1687 if (ret) { 1688 IWL_ERR(trans_pcie->trans, 1689 "Error allocating IRQ %d\n", i); 1690 1691 return ret; 1692 } 1693 } 1694 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1695 1696 return 0; 1697 } 1698 1699 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1700 { 1701 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1702 u32 hpm; 1703 int err; 1704 1705 lockdep_assert_held(&trans_pcie->mutex); 1706 1707 err = iwl_pcie_prepare_card_hw(trans); 1708 if (err) { 1709 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1710 return err; 1711 } 1712 1713 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1714 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1715 int wfpm_val = iwl_read_umac_prph_no_grab(trans, 1716 PREG_PRPH_WPROT_0); 1717 1718 if (wfpm_val & PREG_WFPM_ACCESS) { 1719 IWL_ERR(trans, 1720 "Error, can not clear persistence bit\n"); 1721 return -EPERM; 1722 } 1723 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1724 hpm & ~PERSISTENCE_BIT); 1725 } 1726 1727 iwl_trans_pcie_sw_reset(trans); 1728 1729 err = iwl_pcie_apm_init(trans); 1730 if (err) 1731 return err; 1732 1733 iwl_pcie_init_msix(trans_pcie); 1734 1735 /* From now on, the op_mode will be kept updated about RF kill state */ 1736 iwl_enable_rfkill_int(trans); 1737 1738 trans_pcie->opmode_down = false; 1739 1740 /* Set is_down to false here so that...*/ 1741 trans_pcie->is_down = false; 1742 1743 /* ...rfkill can call stop_device and set it false if needed */ 1744 iwl_pcie_check_hw_rf_kill(trans); 1745 1746 /* Make sure we sync here, because we'll need full access later */ 1747 if (low_power) 1748 pm_runtime_resume(trans->dev); 1749 1750 return 0; 1751 } 1752 1753 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1754 { 1755 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1756 int ret; 1757 1758 mutex_lock(&trans_pcie->mutex); 1759 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1760 mutex_unlock(&trans_pcie->mutex); 1761 1762 return ret; 1763 } 1764 1765 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1766 { 1767 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1768 1769 mutex_lock(&trans_pcie->mutex); 1770 1771 /* disable interrupts - don't enable HW RF kill interrupt */ 1772 iwl_disable_interrupts(trans); 1773 1774 iwl_pcie_apm_stop(trans, true); 1775 1776 iwl_disable_interrupts(trans); 1777 1778 iwl_pcie_disable_ict(trans); 1779 1780 mutex_unlock(&trans_pcie->mutex); 1781 1782 iwl_pcie_synchronize_irqs(trans); 1783 } 1784 1785 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1786 { 1787 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1788 } 1789 1790 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1791 { 1792 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1793 } 1794 1795 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1796 { 1797 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1798 } 1799 1800 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1801 { 1802 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 1803 return 0x00FFFFFF; 1804 else 1805 return 0x000FFFFF; 1806 } 1807 1808 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1809 { 1810 u32 mask = iwl_trans_pcie_prph_msk(trans); 1811 1812 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1813 ((reg & mask) | (3 << 24))); 1814 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1815 } 1816 1817 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1818 u32 val) 1819 { 1820 u32 mask = iwl_trans_pcie_prph_msk(trans); 1821 1822 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1823 ((addr & mask) | (3 << 24))); 1824 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1825 } 1826 1827 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1828 const struct iwl_trans_config *trans_cfg) 1829 { 1830 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831 1832 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1833 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1834 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1835 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1836 trans_pcie->n_no_reclaim_cmds = 0; 1837 else 1838 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1839 if (trans_pcie->n_no_reclaim_cmds) 1840 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1841 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1842 1843 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1844 trans_pcie->rx_page_order = 1845 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1846 1847 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1848 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1849 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1850 1851 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1852 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1853 1854 trans->command_groups = trans_cfg->command_groups; 1855 trans->command_groups_size = trans_cfg->command_groups_size; 1856 1857 /* Initialize NAPI here - it should be before registering to mac80211 1858 * in the opmode but after the HW struct is allocated. 1859 * As this function may be called again in some corner cases don't 1860 * do anything if NAPI was already initialized. 1861 */ 1862 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1863 init_dummy_netdev(&trans_pcie->napi_dev); 1864 } 1865 1866 void iwl_trans_pcie_free(struct iwl_trans *trans) 1867 { 1868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1869 int i; 1870 1871 iwl_pcie_synchronize_irqs(trans); 1872 1873 if (trans->cfg->gen2) 1874 iwl_pcie_gen2_tx_free(trans); 1875 else 1876 iwl_pcie_tx_free(trans); 1877 iwl_pcie_rx_free(trans); 1878 1879 if (trans_pcie->rba.alloc_wq) { 1880 destroy_workqueue(trans_pcie->rba.alloc_wq); 1881 trans_pcie->rba.alloc_wq = NULL; 1882 } 1883 1884 if (trans_pcie->msix_enabled) { 1885 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1886 irq_set_affinity_hint( 1887 trans_pcie->msix_entries[i].vector, 1888 NULL); 1889 } 1890 1891 trans_pcie->msix_enabled = false; 1892 } else { 1893 iwl_pcie_free_ict(trans); 1894 } 1895 1896 iwl_pcie_free_fw_monitor(trans); 1897 1898 for_each_possible_cpu(i) { 1899 struct iwl_tso_hdr_page *p = 1900 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1901 1902 if (p->page) 1903 __free_page(p->page); 1904 } 1905 1906 free_percpu(trans_pcie->tso_hdr_page); 1907 mutex_destroy(&trans_pcie->mutex); 1908 iwl_trans_free(trans); 1909 } 1910 1911 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1912 { 1913 if (state) 1914 set_bit(STATUS_TPOWER_PMI, &trans->status); 1915 else 1916 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1917 } 1918 1919 struct iwl_trans_pcie_removal { 1920 struct pci_dev *pdev; 1921 struct work_struct work; 1922 }; 1923 1924 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 1925 { 1926 struct iwl_trans_pcie_removal *removal = 1927 container_of(wk, struct iwl_trans_pcie_removal, work); 1928 struct pci_dev *pdev = removal->pdev; 1929 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 1930 1931 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 1932 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 1933 pci_lock_rescan_remove(); 1934 pci_dev_put(pdev); 1935 pci_stop_and_remove_bus_device(pdev); 1936 pci_unlock_rescan_remove(); 1937 1938 kfree(removal); 1939 module_put(THIS_MODULE); 1940 } 1941 1942 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1943 unsigned long *flags) 1944 { 1945 int ret; 1946 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1947 1948 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1949 1950 if (trans_pcie->cmd_hold_nic_awake) 1951 goto out; 1952 1953 /* this bit wakes up the NIC */ 1954 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1955 BIT(trans->cfg->csr->flag_mac_access_req)); 1956 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1957 udelay(2); 1958 1959 /* 1960 * These bits say the device is running, and should keep running for 1961 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1962 * but they do not indicate that embedded SRAM is restored yet; 1963 * HW with volatile SRAM must save/restore contents to/from 1964 * host DRAM when sleeping/waking for power-saving. 1965 * Each direction takes approximately 1/4 millisecond; with this 1966 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1967 * series of register accesses are expected (e.g. reading Event Log), 1968 * to keep device from sleeping. 1969 * 1970 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1971 * SRAM is okay/restored. We don't check that here because this call 1972 * is just for hardware register access; but GP1 MAC_SLEEP 1973 * check is a good idea before accessing the SRAM of HW with 1974 * volatile SRAM (e.g. reading Event Log). 1975 * 1976 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1977 * and do not save/restore SRAM when power cycling. 1978 */ 1979 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1980 BIT(trans->cfg->csr->flag_val_mac_access_en), 1981 (BIT(trans->cfg->csr->flag_mac_clock_ready) | 1982 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1983 if (unlikely(ret < 0)) { 1984 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 1985 1986 WARN_ONCE(1, 1987 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1988 cntrl); 1989 1990 iwl_trans_pcie_dump_regs(trans); 1991 1992 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 1993 struct iwl_trans_pcie_removal *removal; 1994 1995 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1996 goto err; 1997 1998 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 1999 2000 /* 2001 * get a module reference to avoid doing this 2002 * while unloading anyway and to avoid 2003 * scheduling a work with code that's being 2004 * removed. 2005 */ 2006 if (!try_module_get(THIS_MODULE)) { 2007 IWL_ERR(trans, 2008 "Module is being unloaded - abort\n"); 2009 goto err; 2010 } 2011 2012 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2013 if (!removal) { 2014 module_put(THIS_MODULE); 2015 goto err; 2016 } 2017 /* 2018 * we don't need to clear this flag, because 2019 * the trans will be freed and reallocated. 2020 */ 2021 set_bit(STATUS_TRANS_DEAD, &trans->status); 2022 2023 removal->pdev = to_pci_dev(trans->dev); 2024 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2025 pci_dev_get(removal->pdev); 2026 schedule_work(&removal->work); 2027 } else { 2028 iwl_write32(trans, CSR_RESET, 2029 CSR_RESET_REG_FLAG_FORCE_NMI); 2030 } 2031 2032 err: 2033 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2034 return false; 2035 } 2036 2037 out: 2038 /* 2039 * Fool sparse by faking we release the lock - sparse will 2040 * track nic_access anyway. 2041 */ 2042 __release(&trans_pcie->reg_lock); 2043 return true; 2044 } 2045 2046 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2047 unsigned long *flags) 2048 { 2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2050 2051 lockdep_assert_held(&trans_pcie->reg_lock); 2052 2053 /* 2054 * Fool sparse by faking we acquiring the lock - sparse will 2055 * track nic_access anyway. 2056 */ 2057 __acquire(&trans_pcie->reg_lock); 2058 2059 if (trans_pcie->cmd_hold_nic_awake) 2060 goto out; 2061 2062 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2063 BIT(trans->cfg->csr->flag_mac_access_req)); 2064 /* 2065 * Above we read the CSR_GP_CNTRL register, which will flush 2066 * any previous writes, but we need the write that clears the 2067 * MAC_ACCESS_REQ bit to be performed before any other writes 2068 * scheduled on different CPUs (after we drop reg_lock). 2069 */ 2070 mmiowb(); 2071 out: 2072 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2073 } 2074 2075 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2076 void *buf, int dwords) 2077 { 2078 unsigned long flags; 2079 int offs, ret = 0; 2080 u32 *vals = buf; 2081 2082 if (iwl_trans_grab_nic_access(trans, &flags)) { 2083 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2084 for (offs = 0; offs < dwords; offs++) 2085 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2086 iwl_trans_release_nic_access(trans, &flags); 2087 } else { 2088 ret = -EBUSY; 2089 } 2090 return ret; 2091 } 2092 2093 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2094 const void *buf, int dwords) 2095 { 2096 unsigned long flags; 2097 int offs, ret = 0; 2098 const u32 *vals = buf; 2099 2100 if (iwl_trans_grab_nic_access(trans, &flags)) { 2101 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2102 for (offs = 0; offs < dwords; offs++) 2103 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2104 vals ? vals[offs] : 0); 2105 iwl_trans_release_nic_access(trans, &flags); 2106 } else { 2107 ret = -EBUSY; 2108 } 2109 return ret; 2110 } 2111 2112 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2113 unsigned long txqs, 2114 bool freeze) 2115 { 2116 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2117 int queue; 2118 2119 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2120 struct iwl_txq *txq = trans_pcie->txq[queue]; 2121 unsigned long now; 2122 2123 spin_lock_bh(&txq->lock); 2124 2125 now = jiffies; 2126 2127 if (txq->frozen == freeze) 2128 goto next_queue; 2129 2130 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2131 freeze ? "Freezing" : "Waking", queue); 2132 2133 txq->frozen = freeze; 2134 2135 if (txq->read_ptr == txq->write_ptr) 2136 goto next_queue; 2137 2138 if (freeze) { 2139 if (unlikely(time_after(now, 2140 txq->stuck_timer.expires))) { 2141 /* 2142 * The timer should have fired, maybe it is 2143 * spinning right now on the lock. 2144 */ 2145 goto next_queue; 2146 } 2147 /* remember how long until the timer fires */ 2148 txq->frozen_expiry_remainder = 2149 txq->stuck_timer.expires - now; 2150 del_timer(&txq->stuck_timer); 2151 goto next_queue; 2152 } 2153 2154 /* 2155 * Wake a non-empty queue -> arm timer with the 2156 * remainder before it froze 2157 */ 2158 mod_timer(&txq->stuck_timer, 2159 now + txq->frozen_expiry_remainder); 2160 2161 next_queue: 2162 spin_unlock_bh(&txq->lock); 2163 } 2164 } 2165 2166 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2167 { 2168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2169 int i; 2170 2171 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2172 struct iwl_txq *txq = trans_pcie->txq[i]; 2173 2174 if (i == trans_pcie->cmd_queue) 2175 continue; 2176 2177 spin_lock_bh(&txq->lock); 2178 2179 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2180 txq->block--; 2181 if (!txq->block) { 2182 iwl_write32(trans, HBUS_TARG_WRPTR, 2183 txq->write_ptr | (i << 8)); 2184 } 2185 } else if (block) { 2186 txq->block++; 2187 } 2188 2189 spin_unlock_bh(&txq->lock); 2190 } 2191 } 2192 2193 #define IWL_FLUSH_WAIT_MS 2000 2194 2195 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2196 { 2197 u32 txq_id = txq->id; 2198 u32 status; 2199 bool active; 2200 u8 fifo; 2201 2202 if (trans->cfg->use_tfh) { 2203 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2204 txq->read_ptr, txq->write_ptr); 2205 /* TODO: access new SCD registers and dump them */ 2206 return; 2207 } 2208 2209 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2210 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2211 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2212 2213 IWL_ERR(trans, 2214 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2215 txq_id, active ? "" : "in", fifo, 2216 jiffies_to_msecs(txq->wd_timeout), 2217 txq->read_ptr, txq->write_ptr, 2218 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2219 (trans->cfg->base_params->max_tfd_queue_size - 1), 2220 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2221 (trans->cfg->base_params->max_tfd_queue_size - 1), 2222 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2223 } 2224 2225 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2226 struct iwl_trans_rxq_dma_data *data) 2227 { 2228 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2229 2230 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2231 return -EINVAL; 2232 2233 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2234 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2235 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2236 data->fr_bd_wid = 0; 2237 2238 return 0; 2239 } 2240 2241 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2242 { 2243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2244 struct iwl_txq *txq; 2245 unsigned long now = jiffies; 2246 bool overflow_tx; 2247 u8 wr_ptr; 2248 2249 /* Make sure the NIC is still alive in the bus */ 2250 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2251 return -ENODEV; 2252 2253 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2254 return -EINVAL; 2255 2256 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2257 txq = trans_pcie->txq[txq_idx]; 2258 2259 spin_lock_bh(&txq->lock); 2260 overflow_tx = txq->overflow_tx || 2261 !skb_queue_empty(&txq->overflow_q); 2262 spin_unlock_bh(&txq->lock); 2263 2264 wr_ptr = READ_ONCE(txq->write_ptr); 2265 2266 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2267 overflow_tx) && 2268 !time_after(jiffies, 2269 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2270 u8 write_ptr = READ_ONCE(txq->write_ptr); 2271 2272 /* 2273 * If write pointer moved during the wait, warn only 2274 * if the TX came from op mode. In case TX came from 2275 * trans layer (overflow TX) don't warn. 2276 */ 2277 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2278 "WR pointer moved while flushing %d -> %d\n", 2279 wr_ptr, write_ptr)) 2280 return -ETIMEDOUT; 2281 wr_ptr = write_ptr; 2282 2283 usleep_range(1000, 2000); 2284 2285 spin_lock_bh(&txq->lock); 2286 overflow_tx = txq->overflow_tx || 2287 !skb_queue_empty(&txq->overflow_q); 2288 spin_unlock_bh(&txq->lock); 2289 } 2290 2291 if (txq->read_ptr != txq->write_ptr) { 2292 IWL_ERR(trans, 2293 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2294 iwl_trans_pcie_log_scd_error(trans, txq); 2295 return -ETIMEDOUT; 2296 } 2297 2298 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2299 2300 return 0; 2301 } 2302 2303 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2304 { 2305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2306 int cnt; 2307 int ret = 0; 2308 2309 /* waiting for all the tx frames complete might take a while */ 2310 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2311 2312 if (cnt == trans_pcie->cmd_queue) 2313 continue; 2314 if (!test_bit(cnt, trans_pcie->queue_used)) 2315 continue; 2316 if (!(BIT(cnt) & txq_bm)) 2317 continue; 2318 2319 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2320 if (ret) 2321 break; 2322 } 2323 2324 return ret; 2325 } 2326 2327 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2328 u32 mask, u32 value) 2329 { 2330 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2331 unsigned long flags; 2332 2333 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2334 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2335 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2336 } 2337 2338 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2339 { 2340 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2341 2342 if (iwlwifi_mod_params.d0i3_disable) 2343 return; 2344 2345 pm_runtime_get(&trans_pcie->pci_dev->dev); 2346 2347 #ifdef CONFIG_PM 2348 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2349 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2350 #endif /* CONFIG_PM */ 2351 } 2352 2353 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2354 { 2355 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2356 2357 if (iwlwifi_mod_params.d0i3_disable) 2358 return; 2359 2360 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2361 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2362 2363 #ifdef CONFIG_PM 2364 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2365 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2366 #endif /* CONFIG_PM */ 2367 } 2368 2369 static const char *get_csr_string(int cmd) 2370 { 2371 #define IWL_CMD(x) case x: return #x 2372 switch (cmd) { 2373 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2374 IWL_CMD(CSR_INT_COALESCING); 2375 IWL_CMD(CSR_INT); 2376 IWL_CMD(CSR_INT_MASK); 2377 IWL_CMD(CSR_FH_INT_STATUS); 2378 IWL_CMD(CSR_GPIO_IN); 2379 IWL_CMD(CSR_RESET); 2380 IWL_CMD(CSR_GP_CNTRL); 2381 IWL_CMD(CSR_HW_REV); 2382 IWL_CMD(CSR_EEPROM_REG); 2383 IWL_CMD(CSR_EEPROM_GP); 2384 IWL_CMD(CSR_OTP_GP_REG); 2385 IWL_CMD(CSR_GIO_REG); 2386 IWL_CMD(CSR_GP_UCODE_REG); 2387 IWL_CMD(CSR_GP_DRIVER_REG); 2388 IWL_CMD(CSR_UCODE_DRV_GP1); 2389 IWL_CMD(CSR_UCODE_DRV_GP2); 2390 IWL_CMD(CSR_LED_REG); 2391 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2392 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2393 IWL_CMD(CSR_ANA_PLL_CFG); 2394 IWL_CMD(CSR_HW_REV_WA_REG); 2395 IWL_CMD(CSR_MONITOR_STATUS_REG); 2396 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2397 default: 2398 return "UNKNOWN"; 2399 } 2400 #undef IWL_CMD 2401 } 2402 2403 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2404 { 2405 int i; 2406 static const u32 csr_tbl[] = { 2407 CSR_HW_IF_CONFIG_REG, 2408 CSR_INT_COALESCING, 2409 CSR_INT, 2410 CSR_INT_MASK, 2411 CSR_FH_INT_STATUS, 2412 CSR_GPIO_IN, 2413 CSR_RESET, 2414 CSR_GP_CNTRL, 2415 CSR_HW_REV, 2416 CSR_EEPROM_REG, 2417 CSR_EEPROM_GP, 2418 CSR_OTP_GP_REG, 2419 CSR_GIO_REG, 2420 CSR_GP_UCODE_REG, 2421 CSR_GP_DRIVER_REG, 2422 CSR_UCODE_DRV_GP1, 2423 CSR_UCODE_DRV_GP2, 2424 CSR_LED_REG, 2425 CSR_DRAM_INT_TBL_REG, 2426 CSR_GIO_CHICKEN_BITS, 2427 CSR_ANA_PLL_CFG, 2428 CSR_MONITOR_STATUS_REG, 2429 CSR_HW_REV_WA_REG, 2430 CSR_DBG_HPET_MEM_REG 2431 }; 2432 IWL_ERR(trans, "CSR values:\n"); 2433 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2434 "CSR_INT_PERIODIC_REG)\n"); 2435 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2436 IWL_ERR(trans, " %25s: 0X%08x\n", 2437 get_csr_string(csr_tbl[i]), 2438 iwl_read32(trans, csr_tbl[i])); 2439 } 2440 } 2441 2442 #ifdef CONFIG_IWLWIFI_DEBUGFS 2443 /* create and remove of files */ 2444 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2445 if (!debugfs_create_file(#name, mode, parent, trans, \ 2446 &iwl_dbgfs_##name##_ops)) \ 2447 goto err; \ 2448 } while (0) 2449 2450 /* file operation */ 2451 #define DEBUGFS_READ_FILE_OPS(name) \ 2452 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2453 .read = iwl_dbgfs_##name##_read, \ 2454 .open = simple_open, \ 2455 .llseek = generic_file_llseek, \ 2456 }; 2457 2458 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2459 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2460 .write = iwl_dbgfs_##name##_write, \ 2461 .open = simple_open, \ 2462 .llseek = generic_file_llseek, \ 2463 }; 2464 2465 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2466 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2467 .write = iwl_dbgfs_##name##_write, \ 2468 .read = iwl_dbgfs_##name##_read, \ 2469 .open = simple_open, \ 2470 .llseek = generic_file_llseek, \ 2471 }; 2472 2473 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2474 char __user *user_buf, 2475 size_t count, loff_t *ppos) 2476 { 2477 struct iwl_trans *trans = file->private_data; 2478 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2479 struct iwl_txq *txq; 2480 char *buf; 2481 int pos = 0; 2482 int cnt; 2483 int ret; 2484 size_t bufsz; 2485 2486 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2487 2488 if (!trans_pcie->txq_memory) 2489 return -EAGAIN; 2490 2491 buf = kzalloc(bufsz, GFP_KERNEL); 2492 if (!buf) 2493 return -ENOMEM; 2494 2495 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2496 txq = trans_pcie->txq[cnt]; 2497 pos += scnprintf(buf + pos, bufsz - pos, 2498 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2499 cnt, txq->read_ptr, txq->write_ptr, 2500 !!test_bit(cnt, trans_pcie->queue_used), 2501 !!test_bit(cnt, trans_pcie->queue_stopped), 2502 txq->need_update, txq->frozen, 2503 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2504 } 2505 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2506 kfree(buf); 2507 return ret; 2508 } 2509 2510 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2511 char __user *user_buf, 2512 size_t count, loff_t *ppos) 2513 { 2514 struct iwl_trans *trans = file->private_data; 2515 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2516 char *buf; 2517 int pos = 0, i, ret; 2518 size_t bufsz = sizeof(buf); 2519 2520 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2521 2522 if (!trans_pcie->rxq) 2523 return -EAGAIN; 2524 2525 buf = kzalloc(bufsz, GFP_KERNEL); 2526 if (!buf) 2527 return -ENOMEM; 2528 2529 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2530 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2531 2532 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2533 i); 2534 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2535 rxq->read); 2536 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2537 rxq->write); 2538 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2539 rxq->write_actual); 2540 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2541 rxq->need_update); 2542 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2543 rxq->free_count); 2544 if (rxq->rb_stts) { 2545 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2546 rxq)); 2547 pos += scnprintf(buf + pos, bufsz - pos, 2548 "\tclosed_rb_num: %u\n", 2549 r & 0x0FFF); 2550 } else { 2551 pos += scnprintf(buf + pos, bufsz - pos, 2552 "\tclosed_rb_num: Not Allocated\n"); 2553 } 2554 } 2555 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2556 kfree(buf); 2557 2558 return ret; 2559 } 2560 2561 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2562 char __user *user_buf, 2563 size_t count, loff_t *ppos) 2564 { 2565 struct iwl_trans *trans = file->private_data; 2566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2567 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2568 2569 int pos = 0; 2570 char *buf; 2571 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2572 ssize_t ret; 2573 2574 buf = kzalloc(bufsz, GFP_KERNEL); 2575 if (!buf) 2576 return -ENOMEM; 2577 2578 pos += scnprintf(buf + pos, bufsz - pos, 2579 "Interrupt Statistics Report:\n"); 2580 2581 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2582 isr_stats->hw); 2583 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2584 isr_stats->sw); 2585 if (isr_stats->sw || isr_stats->hw) { 2586 pos += scnprintf(buf + pos, bufsz - pos, 2587 "\tLast Restarting Code: 0x%X\n", 2588 isr_stats->err_code); 2589 } 2590 #ifdef CONFIG_IWLWIFI_DEBUG 2591 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2592 isr_stats->sch); 2593 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2594 isr_stats->alive); 2595 #endif 2596 pos += scnprintf(buf + pos, bufsz - pos, 2597 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2598 2599 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2600 isr_stats->ctkill); 2601 2602 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2603 isr_stats->wakeup); 2604 2605 pos += scnprintf(buf + pos, bufsz - pos, 2606 "Rx command responses:\t\t %u\n", isr_stats->rx); 2607 2608 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2609 isr_stats->tx); 2610 2611 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2612 isr_stats->unhandled); 2613 2614 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2615 kfree(buf); 2616 return ret; 2617 } 2618 2619 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2620 const char __user *user_buf, 2621 size_t count, loff_t *ppos) 2622 { 2623 struct iwl_trans *trans = file->private_data; 2624 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2625 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2626 u32 reset_flag; 2627 int ret; 2628 2629 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2630 if (ret) 2631 return ret; 2632 if (reset_flag == 0) 2633 memset(isr_stats, 0, sizeof(*isr_stats)); 2634 2635 return count; 2636 } 2637 2638 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2639 const char __user *user_buf, 2640 size_t count, loff_t *ppos) 2641 { 2642 struct iwl_trans *trans = file->private_data; 2643 2644 iwl_pcie_dump_csr(trans); 2645 2646 return count; 2647 } 2648 2649 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2650 char __user *user_buf, 2651 size_t count, loff_t *ppos) 2652 { 2653 struct iwl_trans *trans = file->private_data; 2654 char *buf = NULL; 2655 ssize_t ret; 2656 2657 ret = iwl_dump_fh(trans, &buf); 2658 if (ret < 0) 2659 return ret; 2660 if (!buf) 2661 return -EINVAL; 2662 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2663 kfree(buf); 2664 return ret; 2665 } 2666 2667 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2668 char __user *user_buf, 2669 size_t count, loff_t *ppos) 2670 { 2671 struct iwl_trans *trans = file->private_data; 2672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2673 char buf[100]; 2674 int pos; 2675 2676 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2677 trans_pcie->debug_rfkill, 2678 !(iwl_read32(trans, CSR_GP_CNTRL) & 2679 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2680 2681 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2682 } 2683 2684 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2685 const char __user *user_buf, 2686 size_t count, loff_t *ppos) 2687 { 2688 struct iwl_trans *trans = file->private_data; 2689 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2690 bool old = trans_pcie->debug_rfkill; 2691 int ret; 2692 2693 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2694 if (ret) 2695 return ret; 2696 if (old == trans_pcie->debug_rfkill) 2697 return count; 2698 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2699 old, trans_pcie->debug_rfkill); 2700 iwl_pcie_handle_rfkill_irq(trans); 2701 2702 return count; 2703 } 2704 2705 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2706 struct file *file) 2707 { 2708 struct iwl_trans *trans = inode->i_private; 2709 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2710 2711 if (!trans->dbg_dest_tlv || 2712 trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) { 2713 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2714 return -ENOENT; 2715 } 2716 2717 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2718 return -EBUSY; 2719 2720 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2721 return simple_open(inode, file); 2722 } 2723 2724 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2725 struct file *file) 2726 { 2727 struct iwl_trans_pcie *trans_pcie = 2728 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2729 2730 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2731 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2732 return 0; 2733 } 2734 2735 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2736 void *buf, ssize_t *size, 2737 ssize_t *bytes_copied) 2738 { 2739 int buf_size_left = count - *bytes_copied; 2740 2741 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2742 if (*size > buf_size_left) 2743 *size = buf_size_left; 2744 2745 *size -= copy_to_user(user_buf, buf, *size); 2746 *bytes_copied += *size; 2747 2748 if (buf_size_left == *size) 2749 return true; 2750 return false; 2751 } 2752 2753 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2754 char __user *user_buf, 2755 size_t count, loff_t *ppos) 2756 { 2757 struct iwl_trans *trans = file->private_data; 2758 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2759 void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf; 2760 struct cont_rec *data = &trans_pcie->fw_mon_data; 2761 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2762 ssize_t size, bytes_copied = 0; 2763 bool b_full; 2764 2765 if (trans->dbg_dest_tlv) { 2766 write_ptr_addr = 2767 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2768 wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2769 } else { 2770 write_ptr_addr = MON_BUFF_WRPTR; 2771 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2772 } 2773 2774 if (unlikely(!trans->dbg_rec_on)) 2775 return 0; 2776 2777 mutex_lock(&data->mutex); 2778 if (data->state == 2779 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2780 mutex_unlock(&data->mutex); 2781 return 0; 2782 } 2783 2784 /* write_ptr position in bytes rather then DW */ 2785 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2786 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2787 2788 if (data->prev_wrap_cnt == wrap_cnt) { 2789 size = write_ptr - data->prev_wr_ptr; 2790 curr_buf = cpu_addr + data->prev_wr_ptr; 2791 b_full = iwl_write_to_user_buf(user_buf, count, 2792 curr_buf, &size, 2793 &bytes_copied); 2794 data->prev_wr_ptr += size; 2795 2796 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2797 write_ptr < data->prev_wr_ptr) { 2798 size = trans->fw_mon[0].size - data->prev_wr_ptr; 2799 curr_buf = cpu_addr + data->prev_wr_ptr; 2800 b_full = iwl_write_to_user_buf(user_buf, count, 2801 curr_buf, &size, 2802 &bytes_copied); 2803 data->prev_wr_ptr += size; 2804 2805 if (!b_full) { 2806 size = write_ptr; 2807 b_full = iwl_write_to_user_buf(user_buf, count, 2808 cpu_addr, &size, 2809 &bytes_copied); 2810 data->prev_wr_ptr = size; 2811 data->prev_wrap_cnt++; 2812 } 2813 } else { 2814 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2815 write_ptr > data->prev_wr_ptr) 2816 IWL_WARN(trans, 2817 "write pointer passed previous write pointer, start copying from the beginning\n"); 2818 else if (!unlikely(data->prev_wrap_cnt == 0 && 2819 data->prev_wr_ptr == 0)) 2820 IWL_WARN(trans, 2821 "monitor data is out of sync, start copying from the beginning\n"); 2822 2823 size = write_ptr; 2824 b_full = iwl_write_to_user_buf(user_buf, count, 2825 cpu_addr, &size, 2826 &bytes_copied); 2827 data->prev_wr_ptr = size; 2828 data->prev_wrap_cnt = wrap_cnt; 2829 } 2830 2831 mutex_unlock(&data->mutex); 2832 2833 return bytes_copied; 2834 } 2835 2836 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2837 DEBUGFS_READ_FILE_OPS(fh_reg); 2838 DEBUGFS_READ_FILE_OPS(rx_queue); 2839 DEBUGFS_READ_FILE_OPS(tx_queue); 2840 DEBUGFS_WRITE_FILE_OPS(csr); 2841 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2842 2843 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2844 .read = iwl_dbgfs_monitor_data_read, 2845 .open = iwl_dbgfs_monitor_data_open, 2846 .release = iwl_dbgfs_monitor_data_release, 2847 }; 2848 2849 /* Create the debugfs files and directories */ 2850 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2851 { 2852 struct dentry *dir = trans->dbgfs_dir; 2853 2854 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2855 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2856 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2857 DEBUGFS_ADD_FILE(csr, dir, 0200); 2858 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2859 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2860 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2861 return 0; 2862 2863 err: 2864 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2865 return -ENOMEM; 2866 } 2867 2868 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2869 { 2870 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2871 struct cont_rec *data = &trans_pcie->fw_mon_data; 2872 2873 mutex_lock(&data->mutex); 2874 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2875 mutex_unlock(&data->mutex); 2876 } 2877 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2878 2879 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2880 { 2881 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2882 u32 cmdlen = 0; 2883 int i; 2884 2885 for (i = 0; i < trans_pcie->max_tbs; i++) 2886 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2887 2888 return cmdlen; 2889 } 2890 2891 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2892 struct iwl_fw_error_dump_data **data, 2893 int allocated_rb_nums) 2894 { 2895 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2896 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2897 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2898 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2899 u32 i, r, j, rb_len = 0; 2900 2901 spin_lock(&rxq->lock); 2902 2903 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2904 2905 for (i = rxq->read, j = 0; 2906 i != r && j < allocated_rb_nums; 2907 i = (i + 1) & RX_QUEUE_MASK, j++) { 2908 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2909 struct iwl_fw_error_dump_rb *rb; 2910 2911 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2912 DMA_FROM_DEVICE); 2913 2914 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2915 2916 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2917 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2918 rb = (void *)(*data)->data; 2919 rb->index = cpu_to_le32(i); 2920 memcpy(rb->data, page_address(rxb->page), max_len); 2921 /* remap the page for the free benefit */ 2922 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2923 max_len, 2924 DMA_FROM_DEVICE); 2925 2926 *data = iwl_fw_error_next_data(*data); 2927 } 2928 2929 spin_unlock(&rxq->lock); 2930 2931 return rb_len; 2932 } 2933 #define IWL_CSR_TO_DUMP (0x250) 2934 2935 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2936 struct iwl_fw_error_dump_data **data) 2937 { 2938 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2939 __le32 *val; 2940 int i; 2941 2942 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2943 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2944 val = (void *)(*data)->data; 2945 2946 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2947 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2948 2949 *data = iwl_fw_error_next_data(*data); 2950 2951 return csr_len; 2952 } 2953 2954 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2955 struct iwl_fw_error_dump_data **data) 2956 { 2957 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2958 unsigned long flags; 2959 __le32 *val; 2960 int i; 2961 2962 if (!iwl_trans_grab_nic_access(trans, &flags)) 2963 return 0; 2964 2965 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2966 (*data)->len = cpu_to_le32(fh_regs_len); 2967 val = (void *)(*data)->data; 2968 2969 if (!trans->cfg->gen2) 2970 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2971 i += sizeof(u32)) 2972 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2973 else 2974 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2975 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2976 i += sizeof(u32)) 2977 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2978 i)); 2979 2980 iwl_trans_release_nic_access(trans, &flags); 2981 2982 *data = iwl_fw_error_next_data(*data); 2983 2984 return sizeof(**data) + fh_regs_len; 2985 } 2986 2987 static u32 2988 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2989 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2990 u32 monitor_len) 2991 { 2992 u32 buf_size_in_dwords = (monitor_len >> 2); 2993 u32 *buffer = (u32 *)fw_mon_data->data; 2994 unsigned long flags; 2995 u32 i; 2996 2997 if (!iwl_trans_grab_nic_access(trans, &flags)) 2998 return 0; 2999 3000 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3001 for (i = 0; i < buf_size_in_dwords; i++) 3002 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3003 MON_DMARB_RD_DATA_ADDR); 3004 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3005 3006 iwl_trans_release_nic_access(trans, &flags); 3007 3008 return monitor_len; 3009 } 3010 3011 static void 3012 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3013 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3014 { 3015 u32 base, write_ptr, wrap_cnt; 3016 3017 /* If there was a dest TLV - use the values from there */ 3018 if (trans->ini_valid) { 3019 base = iwl_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2); 3020 write_ptr = iwl_umac_prph(trans, MON_BUFF_WRPTR_VER2); 3021 wrap_cnt = iwl_umac_prph(trans, MON_BUFF_CYCLE_CNT_VER2); 3022 } else if (trans->dbg_dest_tlv) { 3023 write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 3024 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 3025 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3026 } else { 3027 base = MON_BUFF_BASE_ADDR; 3028 write_ptr = MON_BUFF_WRPTR; 3029 wrap_cnt = MON_BUFF_CYCLE_CNT; 3030 } 3031 fw_mon_data->fw_mon_wr_ptr = 3032 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 3033 fw_mon_data->fw_mon_cycle_cnt = 3034 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3035 fw_mon_data->fw_mon_base_ptr = 3036 cpu_to_le32(iwl_read_prph(trans, base)); 3037 } 3038 3039 static u32 3040 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3041 struct iwl_fw_error_dump_data **data, 3042 u32 monitor_len) 3043 { 3044 u32 len = 0; 3045 3046 if ((trans->num_blocks && 3047 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 3048 (trans->dbg_dest_tlv && !trans->ini_valid) || 3049 (trans->ini_valid && trans->num_blocks)) { 3050 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3051 3052 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3053 fw_mon_data = (void *)(*data)->data; 3054 3055 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3056 3057 len += sizeof(**data) + sizeof(*fw_mon_data); 3058 if (trans->num_blocks) { 3059 memcpy(fw_mon_data->data, 3060 trans->fw_mon[0].block, 3061 trans->fw_mon[0].size); 3062 3063 monitor_len = trans->fw_mon[0].size; 3064 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 3065 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3066 /* 3067 * Update pointers to reflect actual values after 3068 * shifting 3069 */ 3070 if (trans->dbg_dest_tlv->version) { 3071 base = (iwl_read_prph(trans, base) & 3072 IWL_LDBG_M2S_BUF_BA_MSK) << 3073 trans->dbg_dest_tlv->base_shift; 3074 base *= IWL_M2S_UNIT_SIZE; 3075 base += trans->cfg->smem_offset; 3076 } else { 3077 base = iwl_read_prph(trans, base) << 3078 trans->dbg_dest_tlv->base_shift; 3079 } 3080 3081 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3082 monitor_len / sizeof(u32)); 3083 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 3084 monitor_len = 3085 iwl_trans_pci_dump_marbh_monitor(trans, 3086 fw_mon_data, 3087 monitor_len); 3088 } else { 3089 /* Didn't match anything - output no monitor data */ 3090 monitor_len = 0; 3091 } 3092 3093 len += monitor_len; 3094 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3095 } 3096 3097 return len; 3098 } 3099 3100 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3101 { 3102 if (trans->num_blocks) { 3103 *len += sizeof(struct iwl_fw_error_dump_data) + 3104 sizeof(struct iwl_fw_error_dump_fw_mon) + 3105 trans->fw_mon[0].size; 3106 return trans->fw_mon[0].size; 3107 } else if (trans->dbg_dest_tlv) { 3108 u32 base, end, cfg_reg, monitor_len; 3109 3110 if (trans->dbg_dest_tlv->version == 1) { 3111 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3112 cfg_reg = iwl_read_prph(trans, cfg_reg); 3113 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3114 trans->dbg_dest_tlv->base_shift; 3115 base *= IWL_M2S_UNIT_SIZE; 3116 base += trans->cfg->smem_offset; 3117 3118 monitor_len = 3119 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3120 trans->dbg_dest_tlv->end_shift; 3121 monitor_len *= IWL_M2S_UNIT_SIZE; 3122 } else { 3123 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3124 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 3125 3126 base = iwl_read_prph(trans, base) << 3127 trans->dbg_dest_tlv->base_shift; 3128 end = iwl_read_prph(trans, end) << 3129 trans->dbg_dest_tlv->end_shift; 3130 3131 /* Make "end" point to the actual end */ 3132 if (trans->cfg->device_family >= 3133 IWL_DEVICE_FAMILY_8000 || 3134 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 3135 end += (1 << trans->dbg_dest_tlv->end_shift); 3136 monitor_len = end - base; 3137 } 3138 *len += sizeof(struct iwl_fw_error_dump_data) + 3139 sizeof(struct iwl_fw_error_dump_fw_mon) + 3140 monitor_len; 3141 return monitor_len; 3142 } 3143 return 0; 3144 } 3145 3146 static struct iwl_trans_dump_data 3147 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3148 u32 dump_mask) 3149 { 3150 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3151 struct iwl_fw_error_dump_data *data; 3152 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3153 struct iwl_fw_error_dump_txcmd *txcmd; 3154 struct iwl_trans_dump_data *dump_data; 3155 u32 len, num_rbs = 0, monitor_len = 0; 3156 int i, ptr; 3157 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3158 !trans->cfg->mq_rx_supported && 3159 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3160 3161 if (!dump_mask) 3162 return NULL; 3163 3164 /* transport dump header */ 3165 len = sizeof(*dump_data); 3166 3167 /* host commands */ 3168 len += sizeof(*data) + 3169 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 3170 3171 /* FW monitor */ 3172 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3173 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3174 3175 /* CSR registers */ 3176 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3177 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3178 3179 /* FH registers */ 3180 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3181 if (trans->cfg->gen2) 3182 len += sizeof(*data) + 3183 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3184 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3185 else 3186 len += sizeof(*data) + 3187 (FH_MEM_UPPER_BOUND - 3188 FH_MEM_LOWER_BOUND); 3189 } 3190 3191 if (dump_rbs) { 3192 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3193 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3194 /* RBs */ 3195 num_rbs = 3196 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3197 & 0x0FFF; 3198 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3199 len += num_rbs * (sizeof(*data) + 3200 sizeof(struct iwl_fw_error_dump_rb) + 3201 (PAGE_SIZE << trans_pcie->rx_page_order)); 3202 } 3203 3204 /* Paged memory for gen2 HW */ 3205 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3206 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3207 len += sizeof(*data) + 3208 sizeof(struct iwl_fw_error_dump_paging) + 3209 trans->init_dram.paging[i].size; 3210 3211 dump_data = vzalloc(len); 3212 if (!dump_data) 3213 return NULL; 3214 3215 len = 0; 3216 data = (void *)dump_data->data; 3217 3218 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { 3219 u16 tfd_size = trans_pcie->tfd_size; 3220 3221 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3222 txcmd = (void *)data->data; 3223 spin_lock_bh(&cmdq->lock); 3224 ptr = cmdq->write_ptr; 3225 for (i = 0; i < cmdq->n_window; i++) { 3226 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3227 u32 caplen, cmdlen; 3228 3229 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3230 cmdq->tfds + 3231 tfd_size * ptr); 3232 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3233 3234 if (cmdlen) { 3235 len += sizeof(*txcmd) + caplen; 3236 txcmd->cmdlen = cpu_to_le32(cmdlen); 3237 txcmd->caplen = cpu_to_le32(caplen); 3238 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3239 caplen); 3240 txcmd = (void *)((u8 *)txcmd->data + caplen); 3241 } 3242 3243 ptr = iwl_queue_dec_wrap(trans, ptr); 3244 } 3245 spin_unlock_bh(&cmdq->lock); 3246 3247 data->len = cpu_to_le32(len); 3248 len += sizeof(*data); 3249 data = iwl_fw_error_next_data(data); 3250 } 3251 3252 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3253 len += iwl_trans_pcie_dump_csr(trans, &data); 3254 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3255 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3256 if (dump_rbs) 3257 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3258 3259 /* Paged memory for gen2 HW */ 3260 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3261 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3262 struct iwl_fw_error_dump_paging *paging; 3263 u32 page_len = trans->init_dram.paging[i].size; 3264 3265 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3266 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3267 paging = (void *)data->data; 3268 paging->index = cpu_to_le32(i); 3269 memcpy(paging->data, 3270 trans->init_dram.paging[i].block, page_len); 3271 data = iwl_fw_error_next_data(data); 3272 3273 len += sizeof(*data) + sizeof(*paging) + page_len; 3274 } 3275 } 3276 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3277 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3278 3279 dump_data->len = len; 3280 3281 return dump_data; 3282 } 3283 3284 #ifdef CONFIG_PM_SLEEP 3285 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3286 { 3287 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3288 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3289 return iwl_pci_fw_enter_d0i3(trans); 3290 3291 return 0; 3292 } 3293 3294 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3295 { 3296 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3297 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3298 iwl_pci_fw_exit_d0i3(trans); 3299 } 3300 #endif /* CONFIG_PM_SLEEP */ 3301 3302 #define IWL_TRANS_COMMON_OPS \ 3303 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3304 .write8 = iwl_trans_pcie_write8, \ 3305 .write32 = iwl_trans_pcie_write32, \ 3306 .read32 = iwl_trans_pcie_read32, \ 3307 .read_prph = iwl_trans_pcie_read_prph, \ 3308 .write_prph = iwl_trans_pcie_write_prph, \ 3309 .read_mem = iwl_trans_pcie_read_mem, \ 3310 .write_mem = iwl_trans_pcie_write_mem, \ 3311 .configure = iwl_trans_pcie_configure, \ 3312 .set_pmi = iwl_trans_pcie_set_pmi, \ 3313 .sw_reset = iwl_trans_pcie_sw_reset, \ 3314 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3315 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3316 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3317 .ref = iwl_trans_pcie_ref, \ 3318 .unref = iwl_trans_pcie_unref, \ 3319 .dump_data = iwl_trans_pcie_dump_data, \ 3320 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3321 .d3_resume = iwl_trans_pcie_d3_resume 3322 3323 #ifdef CONFIG_PM_SLEEP 3324 #define IWL_TRANS_PM_OPS \ 3325 .suspend = iwl_trans_pcie_suspend, \ 3326 .resume = iwl_trans_pcie_resume, 3327 #else 3328 #define IWL_TRANS_PM_OPS 3329 #endif /* CONFIG_PM_SLEEP */ 3330 3331 static const struct iwl_trans_ops trans_ops_pcie = { 3332 IWL_TRANS_COMMON_OPS, 3333 IWL_TRANS_PM_OPS 3334 .start_hw = iwl_trans_pcie_start_hw, 3335 .fw_alive = iwl_trans_pcie_fw_alive, 3336 .start_fw = iwl_trans_pcie_start_fw, 3337 .stop_device = iwl_trans_pcie_stop_device, 3338 3339 .send_cmd = iwl_trans_pcie_send_hcmd, 3340 3341 .tx = iwl_trans_pcie_tx, 3342 .reclaim = iwl_trans_pcie_reclaim, 3343 3344 .txq_disable = iwl_trans_pcie_txq_disable, 3345 .txq_enable = iwl_trans_pcie_txq_enable, 3346 3347 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3348 3349 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3350 3351 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3352 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3353 #ifdef CONFIG_IWLWIFI_DEBUGFS 3354 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3355 #endif 3356 }; 3357 3358 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3359 IWL_TRANS_COMMON_OPS, 3360 IWL_TRANS_PM_OPS 3361 .start_hw = iwl_trans_pcie_start_hw, 3362 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3363 .start_fw = iwl_trans_pcie_gen2_start_fw, 3364 .stop_device = iwl_trans_pcie_gen2_stop_device, 3365 3366 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3367 3368 .tx = iwl_trans_pcie_gen2_tx, 3369 .reclaim = iwl_trans_pcie_reclaim, 3370 3371 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3372 .txq_free = iwl_trans_pcie_dyn_txq_free, 3373 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3374 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3375 #ifdef CONFIG_IWLWIFI_DEBUGFS 3376 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3377 #endif 3378 }; 3379 3380 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3381 const struct pci_device_id *ent, 3382 const struct iwl_cfg *cfg) 3383 { 3384 struct iwl_trans_pcie *trans_pcie; 3385 struct iwl_trans *trans; 3386 int ret, addr_size; 3387 3388 ret = pcim_enable_device(pdev); 3389 if (ret) 3390 return ERR_PTR(ret); 3391 3392 if (cfg->gen2) 3393 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3394 &pdev->dev, cfg, &trans_ops_pcie_gen2); 3395 else 3396 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3397 &pdev->dev, cfg, &trans_ops_pcie); 3398 if (!trans) 3399 return ERR_PTR(-ENOMEM); 3400 3401 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3402 3403 trans_pcie->trans = trans; 3404 trans_pcie->opmode_down = true; 3405 spin_lock_init(&trans_pcie->irq_lock); 3406 spin_lock_init(&trans_pcie->reg_lock); 3407 mutex_init(&trans_pcie->mutex); 3408 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3409 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3410 if (!trans_pcie->tso_hdr_page) { 3411 ret = -ENOMEM; 3412 goto out_no_pci; 3413 } 3414 3415 3416 if (!cfg->base_params->pcie_l1_allowed) { 3417 /* 3418 * W/A - seems to solve weird behavior. We need to remove this 3419 * if we don't want to stay in L1 all the time. This wastes a 3420 * lot of power. 3421 */ 3422 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3423 PCIE_LINK_STATE_L1 | 3424 PCIE_LINK_STATE_CLKPM); 3425 } 3426 3427 trans_pcie->def_rx_queue = 0; 3428 3429 if (cfg->use_tfh) { 3430 addr_size = 64; 3431 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3432 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3433 } else { 3434 addr_size = 36; 3435 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3436 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3437 } 3438 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3439 3440 pci_set_master(pdev); 3441 3442 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3443 if (!ret) 3444 ret = pci_set_consistent_dma_mask(pdev, 3445 DMA_BIT_MASK(addr_size)); 3446 if (ret) { 3447 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3448 if (!ret) 3449 ret = pci_set_consistent_dma_mask(pdev, 3450 DMA_BIT_MASK(32)); 3451 /* both attempts failed: */ 3452 if (ret) { 3453 dev_err(&pdev->dev, "No suitable DMA available\n"); 3454 goto out_no_pci; 3455 } 3456 } 3457 3458 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3459 if (ret) { 3460 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3461 goto out_no_pci; 3462 } 3463 3464 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3465 if (!trans_pcie->hw_base) { 3466 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3467 ret = -ENODEV; 3468 goto out_no_pci; 3469 } 3470 3471 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3472 * PCI Tx retries from interfering with C3 CPU state */ 3473 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3474 3475 trans_pcie->pci_dev = pdev; 3476 iwl_disable_interrupts(trans); 3477 3478 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3479 if (trans->hw_rev == 0xffffffff) { 3480 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3481 ret = -EIO; 3482 goto out_no_pci; 3483 } 3484 3485 /* 3486 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3487 * changed, and now the revision step also includes bit 0-1 (no more 3488 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3489 * in the old format. 3490 */ 3491 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3492 unsigned long flags; 3493 3494 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3495 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3496 3497 ret = iwl_pcie_prepare_card_hw(trans); 3498 if (ret) { 3499 IWL_WARN(trans, "Exit HW not ready\n"); 3500 goto out_no_pci; 3501 } 3502 3503 /* 3504 * in-order to recognize C step driver should read chip version 3505 * id located at the AUX bus MISC address space. 3506 */ 3507 ret = iwl_finish_nic_init(trans); 3508 if (ret) 3509 goto out_no_pci; 3510 3511 if (iwl_trans_grab_nic_access(trans, &flags)) { 3512 u32 hw_step; 3513 3514 hw_step = iwl_read_umac_prph_no_grab(trans, 3515 WFPM_CTRL_REG); 3516 hw_step |= ENABLE_WFPM; 3517 iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, 3518 hw_step); 3519 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3520 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3521 if (hw_step == 0x3) 3522 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3523 (SILICON_C_STEP << 2); 3524 iwl_trans_release_nic_access(trans, &flags); 3525 } 3526 } 3527 3528 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3529 3530 #if IS_ENABLED(CONFIG_IWLMVM) 3531 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3532 3533 if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { 3534 if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { 3535 trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; 3536 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3537 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3538 trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; 3539 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3540 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { 3541 trans->cfg = &iwlax210_2ax_cfg_so_gf_a0; 3542 } 3543 } else if (cfg == &iwl_ax101_cfg_qu_hr) { 3544 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3545 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3546 trans->cfg = &iwl_ax101_cfg_qu_hr; 3547 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3548 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3549 trans->cfg = &iwl22000_2ax_cfg_jf; 3550 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3551 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3552 IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3553 ret = -EINVAL; 3554 goto out_no_pci; 3555 } else { 3556 IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3557 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3558 ret = -EINVAL; 3559 goto out_no_pci; 3560 } 3561 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3562 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3563 (trans->cfg != &iwl22260_2ax_cfg || 3564 trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) { 3565 u32 hw_status; 3566 3567 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3568 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 3569 /* 3570 * b step fw is the same for physical card and fpga 3571 */ 3572 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3573 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 3574 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 3575 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 3576 } else { 3577 /* 3578 * a step no FPGA 3579 */ 3580 trans->cfg = &iwl22000_2ac_cfg_hr; 3581 } 3582 } 3583 #endif 3584 3585 iwl_pcie_set_interrupt_capa(pdev, trans); 3586 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3587 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3588 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3589 3590 /* Initialize the wait queue for commands */ 3591 init_waitqueue_head(&trans_pcie->wait_command_queue); 3592 3593 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3594 3595 if (trans_pcie->msix_enabled) { 3596 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3597 if (ret) 3598 goto out_no_pci; 3599 } else { 3600 ret = iwl_pcie_alloc_ict(trans); 3601 if (ret) 3602 goto out_no_pci; 3603 3604 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3605 iwl_pcie_isr, 3606 iwl_pcie_irq_handler, 3607 IRQF_SHARED, DRV_NAME, trans); 3608 if (ret) { 3609 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3610 goto out_free_ict; 3611 } 3612 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3613 } 3614 3615 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3616 WQ_HIGHPRI | WQ_UNBOUND, 1); 3617 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3618 3619 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3620 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3621 #else 3622 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3623 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3624 3625 #ifdef CONFIG_IWLWIFI_DEBUGFS 3626 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3627 mutex_init(&trans_pcie->fw_mon_data.mutex); 3628 #endif 3629 3630 return trans; 3631 3632 out_free_ict: 3633 iwl_pcie_free_ict(trans); 3634 out_no_pci: 3635 free_percpu(trans_pcie->tso_hdr_page); 3636 iwl_trans_free(trans); 3637 return ERR_PTR(ret); 3638 } 3639 3640 void iwl_trans_sync_nmi(struct iwl_trans *trans) 3641 { 3642 unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3643 3644 iwl_disable_interrupts(trans); 3645 iwl_force_nmi(trans); 3646 while (time_after(timeout, jiffies)) { 3647 u32 inta_hw = iwl_read32(trans, 3648 CSR_MSIX_HW_INT_CAUSES_AD); 3649 3650 /* Error detected by uCode */ 3651 if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) { 3652 /* Clear causes register */ 3653 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, 3654 inta_hw & 3655 MSIX_HW_INT_CAUSES_REG_SW_ERR); 3656 break; 3657 } 3658 3659 mdelay(1); 3660 } 3661 iwl_enable_interrupts(trans); 3662 iwl_trans_fw_error(trans); 3663 } 3664