1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/debugfs.h>
10 #include <linux/sched.h>
11 #include <linux/bitops.h>
12 #include <linux/gfp.h>
13 #include <linux/vmalloc.h>
14 #include <linux/module.h>
15 #include <linux/wait.h>
16 #include <linux/seq_file.h>
17 
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
25 #include "fw/dbg.h"
26 #include "fw/api/tx.h"
27 #include "internal.h"
28 #include "iwl-fh.h"
29 #include "iwl-context-info-gen3.h"
30 
31 /* extended range in FW SRAM */
32 #define IWL_FW_MEM_EXTENDED_START	0x40000
33 #define IWL_FW_MEM_EXTENDED_END		0x57FFF
34 
35 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
36 {
37 #define PCI_DUMP_SIZE		352
38 #define PCI_MEM_DUMP_SIZE	64
39 #define PCI_PARENT_DUMP_SIZE	524
40 #define PREFIX_LEN		32
41 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
42 	struct pci_dev *pdev = trans_pcie->pci_dev;
43 	u32 i, pos, alloc_size, *ptr, *buf;
44 	char *prefix;
45 
46 	if (trans_pcie->pcie_dbg_dumped_once)
47 		return;
48 
49 	/* Should be a multiple of 4 */
50 	BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
51 	BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
52 	BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
53 
54 	/* Alloc a max size buffer */
55 	alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
56 	alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
57 	alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
58 	alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
59 
60 	buf = kmalloc(alloc_size, GFP_ATOMIC);
61 	if (!buf)
62 		return;
63 	prefix = (char *)buf + alloc_size - PREFIX_LEN;
64 
65 	IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
66 
67 	/* Print wifi device registers */
68 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
69 	IWL_ERR(trans, "iwlwifi device config registers:\n");
70 	for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
71 		if (pci_read_config_dword(pdev, i, ptr))
72 			goto err_read;
73 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
74 
75 	IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
76 	for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
77 		*ptr = iwl_read32(trans, i);
78 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
79 
80 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
81 	if (pos) {
82 		IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
83 		for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
84 			if (pci_read_config_dword(pdev, pos + i, ptr))
85 				goto err_read;
86 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
87 			       32, 4, buf, i, 0);
88 	}
89 
90 	/* Print parent device registers next */
91 	if (!pdev->bus->self)
92 		goto out;
93 
94 	pdev = pdev->bus->self;
95 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
96 
97 	IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
98 		pci_name(pdev));
99 	for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
100 		if (pci_read_config_dword(pdev, i, ptr))
101 			goto err_read;
102 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
103 
104 	/* Print root port AER registers */
105 	pos = 0;
106 	pdev = pcie_find_root_port(pdev);
107 	if (pdev)
108 		pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
109 	if (pos) {
110 		IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
111 			pci_name(pdev));
112 		sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
113 		for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
114 			if (pci_read_config_dword(pdev, pos + i, ptr))
115 				goto err_read;
116 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
117 			       4, buf, i, 0);
118 	}
119 	goto out;
120 
121 err_read:
122 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
123 	IWL_ERR(trans, "Read failed at 0x%X\n", i);
124 out:
125 	trans_pcie->pcie_dbg_dumped_once = 1;
126 	kfree(buf);
127 }
128 
129 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
130 {
131 	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
132 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
133 		iwl_set_bit(trans, CSR_GP_CNTRL,
134 			    CSR_GP_CNTRL_REG_FLAG_SW_RESET);
135 	else
136 		iwl_set_bit(trans, CSR_RESET,
137 			    CSR_RESET_REG_FLAG_SW_RESET);
138 	usleep_range(5000, 6000);
139 }
140 
141 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
142 {
143 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
144 
145 	if (!fw_mon->size)
146 		return;
147 
148 	dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
149 			  fw_mon->physical);
150 
151 	fw_mon->block = NULL;
152 	fw_mon->physical = 0;
153 	fw_mon->size = 0;
154 }
155 
156 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
157 					    u8 max_power, u8 min_power)
158 {
159 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
160 	void *block = NULL;
161 	dma_addr_t physical = 0;
162 	u32 size = 0;
163 	u8 power;
164 
165 	if (fw_mon->size)
166 		return;
167 
168 	for (power = max_power; power >= min_power; power--) {
169 		size = BIT(power);
170 		block = dma_alloc_coherent(trans->dev, size, &physical,
171 					   GFP_KERNEL | __GFP_NOWARN);
172 		if (!block)
173 			continue;
174 
175 		IWL_INFO(trans,
176 			 "Allocated 0x%08x bytes for firmware monitor.\n",
177 			 size);
178 		break;
179 	}
180 
181 	if (WARN_ON_ONCE(!block))
182 		return;
183 
184 	if (power != max_power)
185 		IWL_ERR(trans,
186 			"Sorry - debug buffer is only %luK while you requested %luK\n",
187 			(unsigned long)BIT(power - 10),
188 			(unsigned long)BIT(max_power - 10));
189 
190 	fw_mon->block = block;
191 	fw_mon->physical = physical;
192 	fw_mon->size = size;
193 }
194 
195 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
196 {
197 	if (!max_power) {
198 		/* default max_power is maximum */
199 		max_power = 26;
200 	} else {
201 		max_power += 11;
202 	}
203 
204 	if (WARN(max_power > 26,
205 		 "External buffer size for monitor is too big %d, check the FW TLV\n",
206 		 max_power))
207 		return;
208 
209 	if (trans->dbg.fw_mon.size)
210 		return;
211 
212 	iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
213 }
214 
215 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
216 {
217 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
218 		    ((reg & 0x0000ffff) | (2 << 28)));
219 	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
220 }
221 
222 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
223 {
224 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
225 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
226 		    ((reg & 0x0000ffff) | (3 << 28)));
227 }
228 
229 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
230 {
231 	if (trans->cfg->apmg_not_supported)
232 		return;
233 
234 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
235 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
236 				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
237 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
238 	else
239 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
240 				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
241 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
242 }
243 
244 /* PCI registers */
245 #define PCI_CFG_RETRY_TIMEOUT	0x041
246 
247 void iwl_pcie_apm_config(struct iwl_trans *trans)
248 {
249 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
250 	u16 lctl;
251 	u16 cap;
252 
253 	/*
254 	 * L0S states have been found to be unstable with our devices
255 	 * and in newer hardware they are not officially supported at
256 	 * all, so we must always set the L0S_DISABLED bit.
257 	 */
258 	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
259 
260 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
261 	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
262 
263 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
264 	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
265 	IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
266 			(lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
267 			trans->ltr_enabled ? "En" : "Dis");
268 }
269 
270 /*
271  * Start up NIC's basic functionality after it has been reset
272  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
273  * NOTE:  This does not load uCode nor start the embedded processor
274  */
275 static int iwl_pcie_apm_init(struct iwl_trans *trans)
276 {
277 	int ret;
278 
279 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
280 
281 	/*
282 	 * Use "set_bit" below rather than "write", to preserve any hardware
283 	 * bits already set by default after reset.
284 	 */
285 
286 	/* Disable L0S exit timer (platform NMI Work/Around) */
287 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
288 		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
289 			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
290 
291 	/*
292 	 * Disable L0s without affecting L1;
293 	 *  don't wait for ICH L0s (ICH bug W/A)
294 	 */
295 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
296 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
297 
298 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
299 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
300 
301 	/*
302 	 * Enable HAP INTA (interrupt from management bus) to
303 	 * wake device's PCI Express link L1a -> L0s
304 	 */
305 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
306 		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
307 
308 	iwl_pcie_apm_config(trans);
309 
310 	/* Configure analog phase-lock-loop before activating to D0A */
311 	if (trans->trans_cfg->base_params->pll_cfg)
312 		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
313 
314 	ret = iwl_finish_nic_init(trans);
315 	if (ret)
316 		return ret;
317 
318 	if (trans->cfg->host_interrupt_operation_mode) {
319 		/*
320 		 * This is a bit of an abuse - This is needed for 7260 / 3160
321 		 * only check host_interrupt_operation_mode even if this is
322 		 * not related to host_interrupt_operation_mode.
323 		 *
324 		 * Enable the oscillator to count wake up time for L1 exit. This
325 		 * consumes slightly more power (100uA) - but allows to be sure
326 		 * that we wake up from L1 on time.
327 		 *
328 		 * This looks weird: read twice the same register, discard the
329 		 * value, set a bit, and yet again, read that same register
330 		 * just to discard the value. But that's the way the hardware
331 		 * seems to like it.
332 		 */
333 		iwl_read_prph(trans, OSC_CLK);
334 		iwl_read_prph(trans, OSC_CLK);
335 		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
336 		iwl_read_prph(trans, OSC_CLK);
337 		iwl_read_prph(trans, OSC_CLK);
338 	}
339 
340 	/*
341 	 * Enable DMA clock and wait for it to stabilize.
342 	 *
343 	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
344 	 * bits do not disable clocks.  This preserves any hardware
345 	 * bits already set by default in "CLK_CTRL_REG" after reset.
346 	 */
347 	if (!trans->cfg->apmg_not_supported) {
348 		iwl_write_prph(trans, APMG_CLK_EN_REG,
349 			       APMG_CLK_VAL_DMA_CLK_RQT);
350 		udelay(20);
351 
352 		/* Disable L1-Active */
353 		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
354 				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
355 
356 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
357 		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
358 			       APMG_RTC_INT_STT_RFKILL);
359 	}
360 
361 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
362 
363 	return 0;
364 }
365 
366 /*
367  * Enable LP XTAL to avoid HW bug where device may consume much power if
368  * FW is not loaded after device reset. LP XTAL is disabled by default
369  * after device HW reset. Do it only if XTAL is fed by internal source.
370  * Configure device's "persistence" mode to avoid resetting XTAL again when
371  * SHRD_HW_RST occurs in S3.
372  */
373 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
374 {
375 	int ret;
376 	u32 apmg_gp1_reg;
377 	u32 apmg_xtal_cfg_reg;
378 	u32 dl_cfg_reg;
379 
380 	/* Force XTAL ON */
381 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
382 				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383 
384 	iwl_trans_pcie_sw_reset(trans);
385 
386 	ret = iwl_finish_nic_init(trans);
387 	if (WARN_ON(ret)) {
388 		/* Release XTAL ON request */
389 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
390 					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
391 		return;
392 	}
393 
394 	/*
395 	 * Clear "disable persistence" to avoid LP XTAL resetting when
396 	 * SHRD_HW_RST is applied in S3.
397 	 */
398 	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
399 				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);
400 
401 	/*
402 	 * Force APMG XTAL to be active to prevent its disabling by HW
403 	 * caused by APMG idle state.
404 	 */
405 	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
406 						    SHR_APMG_XTAL_CFG_REG);
407 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
408 				 apmg_xtal_cfg_reg |
409 				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
410 
411 	iwl_trans_pcie_sw_reset(trans);
412 
413 	/* Enable LP XTAL by indirect access through CSR */
414 	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
415 	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
416 				 SHR_APMG_GP1_WF_XTAL_LP_EN |
417 				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
418 
419 	/* Clear delay line clock power up */
420 	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
421 	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
422 				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
423 
424 	/*
425 	 * Enable persistence mode to avoid LP XTAL resetting when
426 	 * SHRD_HW_RST is applied in S3.
427 	 */
428 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
429 		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
430 
431 	/*
432 	 * Clear "initialization complete" bit to move adapter from
433 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
434 	 */
435 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
436 
437 	/* Activates XTAL resources monitor */
438 	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
439 				 CSR_MONITOR_XTAL_RESOURCES);
440 
441 	/* Release XTAL ON request */
442 	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
443 				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
444 	udelay(10);
445 
446 	/* Release APMG XTAL */
447 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
448 				 apmg_xtal_cfg_reg &
449 				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
450 }
451 
452 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
453 {
454 	int ret;
455 
456 	/* stop device's busmaster DMA activity */
457 
458 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
459 		iwl_set_bit(trans, CSR_GP_CNTRL,
460 			    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
461 
462 		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
463 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
464 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
465 				   100);
466 		msleep(100);
467 	} else {
468 		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
469 
470 		ret = iwl_poll_bit(trans, CSR_RESET,
471 				   CSR_RESET_REG_FLAG_MASTER_DISABLED,
472 				   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
473 	}
474 
475 	if (ret < 0)
476 		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
477 
478 	IWL_DEBUG_INFO(trans, "stop master\n");
479 }
480 
481 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
482 {
483 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
484 
485 	if (op_mode_leave) {
486 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
487 			iwl_pcie_apm_init(trans);
488 
489 		/* inform ME that we are leaving */
490 		if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
491 			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
492 					  APMG_PCIDEV_STT_VAL_WAKE_ME);
493 		else if (trans->trans_cfg->device_family >=
494 			 IWL_DEVICE_FAMILY_8000) {
495 			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
496 				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
497 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
498 				    CSR_HW_IF_CONFIG_REG_PREPARE |
499 				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
500 			mdelay(1);
501 			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
502 				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
503 		}
504 		mdelay(5);
505 	}
506 
507 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
508 
509 	/* Stop device's DMA activity */
510 	iwl_pcie_apm_stop_master(trans);
511 
512 	if (trans->cfg->lp_xtal_workaround) {
513 		iwl_pcie_apm_lp_xtal_enable(trans);
514 		return;
515 	}
516 
517 	iwl_trans_pcie_sw_reset(trans);
518 
519 	/*
520 	 * Clear "initialization complete" bit to move adapter from
521 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
522 	 */
523 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
524 }
525 
526 static int iwl_pcie_nic_init(struct iwl_trans *trans)
527 {
528 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
529 	int ret;
530 
531 	/* nic_init */
532 	spin_lock_bh(&trans_pcie->irq_lock);
533 	ret = iwl_pcie_apm_init(trans);
534 	spin_unlock_bh(&trans_pcie->irq_lock);
535 
536 	if (ret)
537 		return ret;
538 
539 	iwl_pcie_set_pwr(trans, false);
540 
541 	iwl_op_mode_nic_config(trans->op_mode);
542 
543 	/* Allocate the RX queue, or reset if it is already allocated */
544 	ret = iwl_pcie_rx_init(trans);
545 	if (ret)
546 		return ret;
547 
548 	/* Allocate or reset and init all Tx and Command queues */
549 	if (iwl_pcie_tx_init(trans)) {
550 		iwl_pcie_rx_free(trans);
551 		return -ENOMEM;
552 	}
553 
554 	if (trans->trans_cfg->base_params->shadow_reg_enable) {
555 		/* enable shadow regs in HW */
556 		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
557 		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
558 	}
559 
560 	return 0;
561 }
562 
563 #define HW_READY_TIMEOUT (50)
564 
565 /* Note: returns poll_bit return value, which is >= 0 if success */
566 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
567 {
568 	int ret;
569 
570 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
571 		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
572 
573 	/* See if we got it */
574 	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
575 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
576 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
577 			   HW_READY_TIMEOUT);
578 
579 	if (ret >= 0)
580 		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
581 
582 	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
583 	return ret;
584 }
585 
586 /* Note: returns standard 0/-ERROR code */
587 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
588 {
589 	int ret;
590 	int t = 0;
591 	int iter;
592 
593 	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
594 
595 	ret = iwl_pcie_set_hw_ready(trans);
596 	/* If the card is ready, exit 0 */
597 	if (ret >= 0)
598 		return 0;
599 
600 	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
601 		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
602 	usleep_range(1000, 2000);
603 
604 	for (iter = 0; iter < 10; iter++) {
605 		/* If HW is not ready, prepare the conditions to check again */
606 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
607 			    CSR_HW_IF_CONFIG_REG_PREPARE);
608 
609 		do {
610 			ret = iwl_pcie_set_hw_ready(trans);
611 			if (ret >= 0)
612 				return 0;
613 
614 			usleep_range(200, 1000);
615 			t += 200;
616 		} while (t < 150000);
617 		msleep(25);
618 	}
619 
620 	IWL_ERR(trans, "Couldn't prepare the card\n");
621 
622 	return ret;
623 }
624 
625 /*
626  * ucode
627  */
628 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
629 					    u32 dst_addr, dma_addr_t phy_addr,
630 					    u32 byte_cnt)
631 {
632 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
633 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
634 
635 	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
636 		    dst_addr);
637 
638 	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
639 		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
640 
641 	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
642 		    (iwl_get_dma_hi_addr(phy_addr)
643 			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
644 
645 	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
646 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
647 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
648 		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
649 
650 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
651 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
652 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
653 		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
654 }
655 
656 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
657 					u32 dst_addr, dma_addr_t phy_addr,
658 					u32 byte_cnt)
659 {
660 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 	int ret;
662 
663 	trans_pcie->ucode_write_complete = false;
664 
665 	if (!iwl_trans_grab_nic_access(trans))
666 		return -EIO;
667 
668 	iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
669 					byte_cnt);
670 	iwl_trans_release_nic_access(trans);
671 
672 	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
673 				 trans_pcie->ucode_write_complete, 5 * HZ);
674 	if (!ret) {
675 		IWL_ERR(trans, "Failed to load firmware chunk!\n");
676 		iwl_trans_pcie_dump_regs(trans);
677 		return -ETIMEDOUT;
678 	}
679 
680 	return 0;
681 }
682 
683 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
684 			    const struct fw_desc *section)
685 {
686 	u8 *v_addr;
687 	dma_addr_t p_addr;
688 	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
689 	int ret = 0;
690 
691 	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
692 		     section_num);
693 
694 	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
695 				    GFP_KERNEL | __GFP_NOWARN);
696 	if (!v_addr) {
697 		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
698 		chunk_sz = PAGE_SIZE;
699 		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
700 					    &p_addr, GFP_KERNEL);
701 		if (!v_addr)
702 			return -ENOMEM;
703 	}
704 
705 	for (offset = 0; offset < section->len; offset += chunk_sz) {
706 		u32 copy_size, dst_addr;
707 		bool extended_addr = false;
708 
709 		copy_size = min_t(u32, chunk_sz, section->len - offset);
710 		dst_addr = section->offset + offset;
711 
712 		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
713 		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
714 			extended_addr = true;
715 
716 		if (extended_addr)
717 			iwl_set_bits_prph(trans, LMPM_CHICK,
718 					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
719 
720 		memcpy(v_addr, (u8 *)section->data + offset, copy_size);
721 		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
722 						   copy_size);
723 
724 		if (extended_addr)
725 			iwl_clear_bits_prph(trans, LMPM_CHICK,
726 					    LMPM_CHICK_EXTENDED_ADDR_SPACE);
727 
728 		if (ret) {
729 			IWL_ERR(trans,
730 				"Could not load the [%d] uCode section\n",
731 				section_num);
732 			break;
733 		}
734 	}
735 
736 	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
737 	return ret;
738 }
739 
740 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
741 					   const struct fw_img *image,
742 					   int cpu,
743 					   int *first_ucode_section)
744 {
745 	int shift_param;
746 	int i, ret = 0, sec_num = 0x1;
747 	u32 val, last_read_idx = 0;
748 
749 	if (cpu == 1) {
750 		shift_param = 0;
751 		*first_ucode_section = 0;
752 	} else {
753 		shift_param = 16;
754 		(*first_ucode_section)++;
755 	}
756 
757 	for (i = *first_ucode_section; i < image->num_sec; i++) {
758 		last_read_idx = i;
759 
760 		/*
761 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
762 		 * CPU1 to CPU2.
763 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
764 		 * CPU2 non paged to CPU2 paging sec.
765 		 */
766 		if (!image->sec[i].data ||
767 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
768 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
769 			IWL_DEBUG_FW(trans,
770 				     "Break since Data not valid or Empty section, sec = %d\n",
771 				     i);
772 			break;
773 		}
774 
775 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
776 		if (ret)
777 			return ret;
778 
779 		/* Notify ucode of loaded section number and status */
780 		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
781 		val = val | (sec_num << shift_param);
782 		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
783 
784 		sec_num = (sec_num << 1) | 0x1;
785 	}
786 
787 	*first_ucode_section = last_read_idx;
788 
789 	iwl_enable_interrupts(trans);
790 
791 	if (trans->trans_cfg->use_tfh) {
792 		if (cpu == 1)
793 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
794 				       0xFFFF);
795 		else
796 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
797 				       0xFFFFFFFF);
798 	} else {
799 		if (cpu == 1)
800 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
801 					   0xFFFF);
802 		else
803 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
804 					   0xFFFFFFFF);
805 	}
806 
807 	return 0;
808 }
809 
810 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
811 				      const struct fw_img *image,
812 				      int cpu,
813 				      int *first_ucode_section)
814 {
815 	int i, ret = 0;
816 	u32 last_read_idx = 0;
817 
818 	if (cpu == 1)
819 		*first_ucode_section = 0;
820 	else
821 		(*first_ucode_section)++;
822 
823 	for (i = *first_ucode_section; i < image->num_sec; i++) {
824 		last_read_idx = i;
825 
826 		/*
827 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
828 		 * CPU1 to CPU2.
829 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
830 		 * CPU2 non paged to CPU2 paging sec.
831 		 */
832 		if (!image->sec[i].data ||
833 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
834 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
835 			IWL_DEBUG_FW(trans,
836 				     "Break since Data not valid or Empty section, sec = %d\n",
837 				     i);
838 			break;
839 		}
840 
841 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
842 		if (ret)
843 			return ret;
844 	}
845 
846 	*first_ucode_section = last_read_idx;
847 
848 	return 0;
849 }
850 
851 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
852 {
853 	enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
854 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
855 		&trans->dbg.fw_mon_cfg[alloc_id];
856 	struct iwl_dram_data *frag;
857 
858 	if (!iwl_trans_dbg_ini_valid(trans))
859 		return;
860 
861 	if (le32_to_cpu(fw_mon_cfg->buf_location) ==
862 	    IWL_FW_INI_LOCATION_SRAM_PATH) {
863 		IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
864 		/* set sram monitor by enabling bit 7 */
865 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
866 			    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
867 
868 		return;
869 	}
870 
871 	if (le32_to_cpu(fw_mon_cfg->buf_location) !=
872 	    IWL_FW_INI_LOCATION_DRAM_PATH ||
873 	    !trans->dbg.fw_mon_ini[alloc_id].num_frags)
874 		return;
875 
876 	frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
877 
878 	IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
879 		     alloc_id);
880 
881 	iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
882 			    frag->physical >> MON_BUFF_SHIFT_VER2);
883 	iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
884 			    (frag->physical + frag->size - 256) >>
885 			    MON_BUFF_SHIFT_VER2);
886 }
887 
888 void iwl_pcie_apply_destination(struct iwl_trans *trans)
889 {
890 	const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
891 	const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
892 	int i;
893 
894 	if (iwl_trans_dbg_ini_valid(trans)) {
895 		iwl_pcie_apply_destination_ini(trans);
896 		return;
897 	}
898 
899 	IWL_INFO(trans, "Applying debug destination %s\n",
900 		 get_fw_dbg_mode_string(dest->monitor_mode));
901 
902 	if (dest->monitor_mode == EXTERNAL_MODE)
903 		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
904 	else
905 		IWL_WARN(trans, "PCI should have external buffer debug\n");
906 
907 	for (i = 0; i < trans->dbg.n_dest_reg; i++) {
908 		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
909 		u32 val = le32_to_cpu(dest->reg_ops[i].val);
910 
911 		switch (dest->reg_ops[i].op) {
912 		case CSR_ASSIGN:
913 			iwl_write32(trans, addr, val);
914 			break;
915 		case CSR_SETBIT:
916 			iwl_set_bit(trans, addr, BIT(val));
917 			break;
918 		case CSR_CLEARBIT:
919 			iwl_clear_bit(trans, addr, BIT(val));
920 			break;
921 		case PRPH_ASSIGN:
922 			iwl_write_prph(trans, addr, val);
923 			break;
924 		case PRPH_SETBIT:
925 			iwl_set_bits_prph(trans, addr, BIT(val));
926 			break;
927 		case PRPH_CLEARBIT:
928 			iwl_clear_bits_prph(trans, addr, BIT(val));
929 			break;
930 		case PRPH_BLOCKBIT:
931 			if (iwl_read_prph(trans, addr) & BIT(val)) {
932 				IWL_ERR(trans,
933 					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
934 					val, addr);
935 				goto monitor;
936 			}
937 			break;
938 		default:
939 			IWL_ERR(trans, "FW debug - unknown OP %d\n",
940 				dest->reg_ops[i].op);
941 			break;
942 		}
943 	}
944 
945 monitor:
946 	if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
947 		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
948 			       fw_mon->physical >> dest->base_shift);
949 		if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
950 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
951 				       (fw_mon->physical + fw_mon->size -
952 					256) >> dest->end_shift);
953 		else
954 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
955 				       (fw_mon->physical + fw_mon->size) >>
956 				       dest->end_shift);
957 	}
958 }
959 
960 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
961 				const struct fw_img *image)
962 {
963 	int ret = 0;
964 	int first_ucode_section;
965 
966 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
967 		     image->is_dual_cpus ? "Dual" : "Single");
968 
969 	/* load to FW the binary non secured sections of CPU1 */
970 	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
971 	if (ret)
972 		return ret;
973 
974 	if (image->is_dual_cpus) {
975 		/* set CPU2 header address */
976 		iwl_write_prph(trans,
977 			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
978 			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
979 
980 		/* load to FW the binary sections of CPU2 */
981 		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
982 						 &first_ucode_section);
983 		if (ret)
984 			return ret;
985 	}
986 
987 	if (iwl_pcie_dbg_on(trans))
988 		iwl_pcie_apply_destination(trans);
989 
990 	iwl_enable_interrupts(trans);
991 
992 	/* release CPU reset */
993 	iwl_write32(trans, CSR_RESET, 0);
994 
995 	return 0;
996 }
997 
998 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
999 					  const struct fw_img *image)
1000 {
1001 	int ret = 0;
1002 	int first_ucode_section;
1003 
1004 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
1005 		     image->is_dual_cpus ? "Dual" : "Single");
1006 
1007 	if (iwl_pcie_dbg_on(trans))
1008 		iwl_pcie_apply_destination(trans);
1009 
1010 	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1011 			iwl_read_prph(trans, WFPM_GP2));
1012 
1013 	/*
1014 	 * Set default value. On resume reading the values that were
1015 	 * zeored can provide debug data on the resume flow.
1016 	 * This is for debugging only and has no functional impact.
1017 	 */
1018 	iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1019 
1020 	/* configure the ucode to be ready to get the secured image */
1021 	/* release CPU reset */
1022 	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1023 
1024 	/* load to FW the binary Secured sections of CPU1 */
1025 	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1026 					      &first_ucode_section);
1027 	if (ret)
1028 		return ret;
1029 
1030 	/* load to FW the binary sections of CPU2 */
1031 	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1032 					       &first_ucode_section);
1033 }
1034 
1035 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1036 {
1037 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1038 	bool hw_rfkill = iwl_is_rfkill_set(trans);
1039 	bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1040 	bool report;
1041 
1042 	if (hw_rfkill) {
1043 		set_bit(STATUS_RFKILL_HW, &trans->status);
1044 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1045 	} else {
1046 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1047 		if (trans_pcie->opmode_down)
1048 			clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1049 	}
1050 
1051 	report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1052 
1053 	if (prev != report)
1054 		iwl_trans_pcie_rf_kill(trans, report);
1055 
1056 	return hw_rfkill;
1057 }
1058 
1059 struct iwl_causes_list {
1060 	u32 cause_num;
1061 	u32 mask_reg;
1062 	u8 addr;
1063 };
1064 
1065 static const struct iwl_causes_list causes_list_common[] = {
1066 	{MSIX_FH_INT_CAUSES_D2S_CH0_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0},
1067 	{MSIX_FH_INT_CAUSES_D2S_CH1_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0x1},
1068 	{MSIX_FH_INT_CAUSES_S2D,		CSR_MSIX_FH_INT_MASK_AD, 0x3},
1069 	{MSIX_FH_INT_CAUSES_FH_ERR,		CSR_MSIX_FH_INT_MASK_AD, 0x5},
1070 	{MSIX_HW_INT_CAUSES_REG_ALIVE,		CSR_MSIX_HW_INT_MASK_AD, 0x10},
1071 	{MSIX_HW_INT_CAUSES_REG_WAKEUP,		CSR_MSIX_HW_INT_MASK_AD, 0x11},
1072 	{MSIX_HW_INT_CAUSES_REG_RESET_DONE,	CSR_MSIX_HW_INT_MASK_AD, 0x12},
1073 	{MSIX_HW_INT_CAUSES_REG_CT_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x16},
1074 	{MSIX_HW_INT_CAUSES_REG_RF_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x17},
1075 	{MSIX_HW_INT_CAUSES_REG_PERIODIC,	CSR_MSIX_HW_INT_MASK_AD, 0x18},
1076 	{MSIX_HW_INT_CAUSES_REG_SCD,		CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1077 	{MSIX_HW_INT_CAUSES_REG_FH_TX,		CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1078 	{MSIX_HW_INT_CAUSES_REG_HW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1079 	{MSIX_HW_INT_CAUSES_REG_HAP,		CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1080 };
1081 
1082 static const struct iwl_causes_list causes_list_pre_bz[] = {
1083 	{MSIX_HW_INT_CAUSES_REG_SW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x29},
1084 };
1085 
1086 static const struct iwl_causes_list causes_list_bz[] = {
1087 	{MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ,	CSR_MSIX_HW_INT_MASK_AD, 0x29},
1088 };
1089 
1090 static void iwl_pcie_map_list(struct iwl_trans *trans,
1091 			      const struct iwl_causes_list *causes,
1092 			      int arr_size, int val)
1093 {
1094 	int i;
1095 
1096 	for (i = 0; i < arr_size; i++) {
1097 		iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1098 		iwl_clear_bit(trans, causes[i].mask_reg,
1099 			      causes[i].cause_num);
1100 	}
1101 }
1102 
1103 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1104 {
1105 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1106 	int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1107 	/*
1108 	 * Access all non RX causes and map them to the default irq.
1109 	 * In case we are missing at least one interrupt vector,
1110 	 * the first interrupt vector will serve non-RX and FBQ causes.
1111 	 */
1112 	iwl_pcie_map_list(trans, causes_list_common,
1113 			  ARRAY_SIZE(causes_list_common), val);
1114 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1115 		iwl_pcie_map_list(trans, causes_list_bz,
1116 				  ARRAY_SIZE(causes_list_bz), val);
1117 	else
1118 		iwl_pcie_map_list(trans, causes_list_pre_bz,
1119 				  ARRAY_SIZE(causes_list_pre_bz), val);
1120 }
1121 
1122 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1123 {
1124 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1125 	u32 offset =
1126 		trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1127 	u32 val, idx;
1128 
1129 	/*
1130 	 * The first RX queue - fallback queue, which is designated for
1131 	 * management frame, command responses etc, is always mapped to the
1132 	 * first interrupt vector. The other RX queues are mapped to
1133 	 * the other (N - 2) interrupt vectors.
1134 	 */
1135 	val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1136 	for (idx = 1; idx < trans->num_rx_queues; idx++) {
1137 		iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1138 			   MSIX_FH_INT_CAUSES_Q(idx - offset));
1139 		val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1140 	}
1141 	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1142 
1143 	val = MSIX_FH_INT_CAUSES_Q(0);
1144 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1145 		val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1146 	iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1147 
1148 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1149 		iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1150 }
1151 
1152 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1153 {
1154 	struct iwl_trans *trans = trans_pcie->trans;
1155 
1156 	if (!trans_pcie->msix_enabled) {
1157 		if (trans->trans_cfg->mq_rx_supported &&
1158 		    test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1159 			iwl_write_umac_prph(trans, UREG_CHICK,
1160 					    UREG_CHICK_MSI_ENABLE);
1161 		return;
1162 	}
1163 	/*
1164 	 * The IVAR table needs to be configured again after reset,
1165 	 * but if the device is disabled, we can't write to
1166 	 * prph.
1167 	 */
1168 	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1169 		iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1170 
1171 	/*
1172 	 * Each cause from the causes list above and the RX causes is
1173 	 * represented as a byte in the IVAR table. The first nibble
1174 	 * represents the bound interrupt vector of the cause, the second
1175 	 * represents no auto clear for this cause. This will be set if its
1176 	 * interrupt vector is bound to serve other causes.
1177 	 */
1178 	iwl_pcie_map_rx_causes(trans);
1179 
1180 	iwl_pcie_map_non_rx_causes(trans);
1181 }
1182 
1183 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1184 {
1185 	struct iwl_trans *trans = trans_pcie->trans;
1186 
1187 	iwl_pcie_conf_msix_hw(trans_pcie);
1188 
1189 	if (!trans_pcie->msix_enabled)
1190 		return;
1191 
1192 	trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1193 	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1194 	trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1195 	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1196 }
1197 
1198 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1199 {
1200 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1201 
1202 	lockdep_assert_held(&trans_pcie->mutex);
1203 
1204 	if (trans_pcie->is_down)
1205 		return;
1206 
1207 	trans_pcie->is_down = true;
1208 
1209 	/* tell the device to stop sending interrupts */
1210 	iwl_disable_interrupts(trans);
1211 
1212 	/* device going down, Stop using ICT table */
1213 	iwl_pcie_disable_ict(trans);
1214 
1215 	/*
1216 	 * If a HW restart happens during firmware loading,
1217 	 * then the firmware loading might call this function
1218 	 * and later it might be called again due to the
1219 	 * restart. So don't process again if the device is
1220 	 * already dead.
1221 	 */
1222 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1223 		IWL_DEBUG_INFO(trans,
1224 			       "DEVICE_ENABLED bit was set and is now cleared\n");
1225 		iwl_pcie_tx_stop(trans);
1226 		iwl_pcie_rx_stop(trans);
1227 
1228 		/* Power-down device's busmaster DMA clocks */
1229 		if (!trans->cfg->apmg_not_supported) {
1230 			iwl_write_prph(trans, APMG_CLK_DIS_REG,
1231 				       APMG_CLK_VAL_DMA_CLK_RQT);
1232 			udelay(5);
1233 		}
1234 	}
1235 
1236 	/* Make sure (redundant) we've released our request to stay awake */
1237 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1238 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1239 			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1240 	else
1241 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1242 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1243 
1244 	/* Stop the device, and put it in low power state */
1245 	iwl_pcie_apm_stop(trans, false);
1246 
1247 	iwl_trans_pcie_sw_reset(trans);
1248 
1249 	/*
1250 	 * Upon stop, the IVAR table gets erased, so msi-x won't
1251 	 * work. This causes a bug in RF-KILL flows, since the interrupt
1252 	 * that enables radio won't fire on the correct irq, and the
1253 	 * driver won't be able to handle the interrupt.
1254 	 * Configure the IVAR table again after reset.
1255 	 */
1256 	iwl_pcie_conf_msix_hw(trans_pcie);
1257 
1258 	/*
1259 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1260 	 * This is a bug in certain verions of the hardware.
1261 	 * Certain devices also keep sending HW RF kill interrupt all
1262 	 * the time, unless the interrupt is ACKed even if the interrupt
1263 	 * should be masked. Re-ACK all the interrupts here.
1264 	 */
1265 	iwl_disable_interrupts(trans);
1266 
1267 	/* clear all status bits */
1268 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1269 	clear_bit(STATUS_INT_ENABLED, &trans->status);
1270 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
1271 
1272 	/*
1273 	 * Even if we stop the HW, we still want the RF kill
1274 	 * interrupt
1275 	 */
1276 	iwl_enable_rfkill_int(trans);
1277 
1278 	/* re-take ownership to prevent other users from stealing the device */
1279 	iwl_pcie_prepare_card_hw(trans);
1280 }
1281 
1282 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1283 {
1284 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1285 
1286 	if (trans_pcie->msix_enabled) {
1287 		int i;
1288 
1289 		for (i = 0; i < trans_pcie->alloc_vecs; i++)
1290 			synchronize_irq(trans_pcie->msix_entries[i].vector);
1291 	} else {
1292 		synchronize_irq(trans_pcie->pci_dev->irq);
1293 	}
1294 }
1295 
1296 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1297 				   const struct fw_img *fw, bool run_in_rfkill)
1298 {
1299 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1300 	bool hw_rfkill;
1301 	int ret;
1302 
1303 	/* This may fail if AMT took ownership of the device */
1304 	if (iwl_pcie_prepare_card_hw(trans)) {
1305 		IWL_WARN(trans, "Exit HW not ready\n");
1306 		ret = -EIO;
1307 		goto out;
1308 	}
1309 
1310 	iwl_enable_rfkill_int(trans);
1311 
1312 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1313 
1314 	/*
1315 	 * We enabled the RF-Kill interrupt and the handler may very
1316 	 * well be running. Disable the interrupts to make sure no other
1317 	 * interrupt can be fired.
1318 	 */
1319 	iwl_disable_interrupts(trans);
1320 
1321 	/* Make sure it finished running */
1322 	iwl_pcie_synchronize_irqs(trans);
1323 
1324 	mutex_lock(&trans_pcie->mutex);
1325 
1326 	/* If platform's RF_KILL switch is NOT set to KILL */
1327 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1328 	if (hw_rfkill && !run_in_rfkill) {
1329 		ret = -ERFKILL;
1330 		goto out;
1331 	}
1332 
1333 	/* Someone called stop_device, don't try to start_fw */
1334 	if (trans_pcie->is_down) {
1335 		IWL_WARN(trans,
1336 			 "Can't start_fw since the HW hasn't been started\n");
1337 		ret = -EIO;
1338 		goto out;
1339 	}
1340 
1341 	/* make sure rfkill handshake bits are cleared */
1342 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1343 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1344 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1345 
1346 	/* clear (again), then enable host interrupts */
1347 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1348 
1349 	ret = iwl_pcie_nic_init(trans);
1350 	if (ret) {
1351 		IWL_ERR(trans, "Unable to init nic\n");
1352 		goto out;
1353 	}
1354 
1355 	/*
1356 	 * Now, we load the firmware and don't want to be interrupted, even
1357 	 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1358 	 * FH_TX interrupt which is needed to load the firmware). If the
1359 	 * RF-Kill switch is toggled, we will find out after having loaded
1360 	 * the firmware and return the proper value to the caller.
1361 	 */
1362 	iwl_enable_fw_load_int(trans);
1363 
1364 	/* really make sure rfkill handshake bits are cleared */
1365 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1366 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1367 
1368 	/* Load the given image to the HW */
1369 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1370 		ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1371 	else
1372 		ret = iwl_pcie_load_given_ucode(trans, fw);
1373 
1374 	/* re-check RF-Kill state since we may have missed the interrupt */
1375 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1376 	if (hw_rfkill && !run_in_rfkill)
1377 		ret = -ERFKILL;
1378 
1379 out:
1380 	mutex_unlock(&trans_pcie->mutex);
1381 	return ret;
1382 }
1383 
1384 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1385 {
1386 	iwl_pcie_reset_ict(trans);
1387 	iwl_pcie_tx_start(trans, scd_addr);
1388 }
1389 
1390 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1391 				       bool was_in_rfkill)
1392 {
1393 	bool hw_rfkill;
1394 
1395 	/*
1396 	 * Check again since the RF kill state may have changed while
1397 	 * all the interrupts were disabled, in this case we couldn't
1398 	 * receive the RF kill interrupt and update the state in the
1399 	 * op_mode.
1400 	 * Don't call the op_mode if the rkfill state hasn't changed.
1401 	 * This allows the op_mode to call stop_device from the rfkill
1402 	 * notification without endless recursion. Under very rare
1403 	 * circumstances, we might have a small recursion if the rfkill
1404 	 * state changed exactly now while we were called from stop_device.
1405 	 * This is very unlikely but can happen and is supported.
1406 	 */
1407 	hw_rfkill = iwl_is_rfkill_set(trans);
1408 	if (hw_rfkill) {
1409 		set_bit(STATUS_RFKILL_HW, &trans->status);
1410 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1411 	} else {
1412 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1413 		clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1414 	}
1415 	if (hw_rfkill != was_in_rfkill)
1416 		iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1417 }
1418 
1419 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1420 {
1421 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1422 	bool was_in_rfkill;
1423 
1424 	iwl_op_mode_time_point(trans->op_mode,
1425 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1426 			       NULL);
1427 
1428 	mutex_lock(&trans_pcie->mutex);
1429 	trans_pcie->opmode_down = true;
1430 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1431 	_iwl_trans_pcie_stop_device(trans);
1432 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1433 	mutex_unlock(&trans_pcie->mutex);
1434 }
1435 
1436 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1437 {
1438 	struct iwl_trans_pcie __maybe_unused *trans_pcie =
1439 		IWL_TRANS_GET_PCIE_TRANS(trans);
1440 
1441 	lockdep_assert_held(&trans_pcie->mutex);
1442 
1443 	IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1444 		 state ? "disabled" : "enabled");
1445 	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1446 		if (trans->trans_cfg->gen2)
1447 			_iwl_trans_pcie_gen2_stop_device(trans);
1448 		else
1449 			_iwl_trans_pcie_stop_device(trans);
1450 	}
1451 }
1452 
1453 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1454 				  bool test, bool reset)
1455 {
1456 	iwl_disable_interrupts(trans);
1457 
1458 	/*
1459 	 * in testing mode, the host stays awake and the
1460 	 * hardware won't be reset (not even partially)
1461 	 */
1462 	if (test)
1463 		return;
1464 
1465 	iwl_pcie_disable_ict(trans);
1466 
1467 	iwl_pcie_synchronize_irqs(trans);
1468 
1469 	iwl_clear_bit(trans, CSR_GP_CNTRL,
1470 		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1471 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1472 
1473 	if (reset) {
1474 		/*
1475 		 * reset TX queues -- some of their registers reset during S3
1476 		 * so if we don't reset everything here the D3 image would try
1477 		 * to execute some invalid memory upon resume
1478 		 */
1479 		iwl_trans_pcie_tx_reset(trans);
1480 	}
1481 
1482 	iwl_pcie_set_pwr(trans, true);
1483 }
1484 
1485 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1486 				     bool reset)
1487 {
1488 	int ret;
1489 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1490 
1491 	if (!reset)
1492 		/* Enable persistence mode to avoid reset */
1493 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1494 			    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1495 
1496 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1497 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1498 				    UREG_DOORBELL_TO_ISR6_SUSPEND);
1499 
1500 		ret = wait_event_timeout(trans_pcie->sx_waitq,
1501 					 trans_pcie->sx_complete, 2 * HZ);
1502 		/*
1503 		 * Invalidate it toward resume.
1504 		 */
1505 		trans_pcie->sx_complete = false;
1506 
1507 		if (!ret) {
1508 			IWL_ERR(trans, "Timeout entering D3\n");
1509 			return -ETIMEDOUT;
1510 		}
1511 	}
1512 	iwl_pcie_d3_complete_suspend(trans, test, reset);
1513 
1514 	return 0;
1515 }
1516 
1517 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1518 				    enum iwl_d3_status *status,
1519 				    bool test,  bool reset)
1520 {
1521 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1522 	u32 val;
1523 	int ret;
1524 
1525 	if (test) {
1526 		iwl_enable_interrupts(trans);
1527 		*status = IWL_D3_STATUS_ALIVE;
1528 		goto out;
1529 	}
1530 
1531 	iwl_set_bit(trans, CSR_GP_CNTRL,
1532 		    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1533 
1534 	ret = iwl_finish_nic_init(trans);
1535 	if (ret)
1536 		return ret;
1537 
1538 	/*
1539 	 * Reconfigure IVAR table in case of MSIX or reset ict table in
1540 	 * MSI mode since HW reset erased it.
1541 	 * Also enables interrupts - none will happen as
1542 	 * the device doesn't know we're waking it up, only when
1543 	 * the opmode actually tells it after this call.
1544 	 */
1545 	iwl_pcie_conf_msix_hw(trans_pcie);
1546 	if (!trans_pcie->msix_enabled)
1547 		iwl_pcie_reset_ict(trans);
1548 	iwl_enable_interrupts(trans);
1549 
1550 	iwl_pcie_set_pwr(trans, false);
1551 
1552 	if (!reset) {
1553 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1554 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1555 	} else {
1556 		iwl_trans_pcie_tx_reset(trans);
1557 
1558 		ret = iwl_pcie_rx_init(trans);
1559 		if (ret) {
1560 			IWL_ERR(trans,
1561 				"Failed to resume the device (RX reset)\n");
1562 			return ret;
1563 		}
1564 	}
1565 
1566 	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1567 			iwl_read_umac_prph(trans, WFPM_GP2));
1568 
1569 	val = iwl_read32(trans, CSR_RESET);
1570 	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1571 		*status = IWL_D3_STATUS_RESET;
1572 	else
1573 		*status = IWL_D3_STATUS_ALIVE;
1574 
1575 out:
1576 	if (*status == IWL_D3_STATUS_ALIVE &&
1577 	    trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
1578 		trans_pcie->sx_complete = false;
1579 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1580 				    UREG_DOORBELL_TO_ISR6_RESUME);
1581 
1582 		ret = wait_event_timeout(trans_pcie->sx_waitq,
1583 					 trans_pcie->sx_complete, 2 * HZ);
1584 		/*
1585 		 * Invalidate it toward next suspend.
1586 		 */
1587 		trans_pcie->sx_complete = false;
1588 
1589 		if (!ret) {
1590 			IWL_ERR(trans, "Timeout exiting D3\n");
1591 			return -ETIMEDOUT;
1592 		}
1593 	}
1594 	return 0;
1595 }
1596 
1597 static void
1598 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1599 			    struct iwl_trans *trans,
1600 			    const struct iwl_cfg_trans_params *cfg_trans)
1601 {
1602 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1603 	int max_irqs, num_irqs, i, ret;
1604 	u16 pci_cmd;
1605 	u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1606 
1607 	if (!cfg_trans->mq_rx_supported)
1608 		goto enable_msi;
1609 
1610 	if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1611 		max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1612 
1613 	max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1614 	for (i = 0; i < max_irqs; i++)
1615 		trans_pcie->msix_entries[i].entry = i;
1616 
1617 	num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1618 					 MSIX_MIN_INTERRUPT_VECTORS,
1619 					 max_irqs);
1620 	if (num_irqs < 0) {
1621 		IWL_DEBUG_INFO(trans,
1622 			       "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1623 			       num_irqs);
1624 		goto enable_msi;
1625 	}
1626 	trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1627 
1628 	IWL_DEBUG_INFO(trans,
1629 		       "MSI-X enabled. %d interrupt vectors were allocated\n",
1630 		       num_irqs);
1631 
1632 	/*
1633 	 * In case the OS provides fewer interrupts than requested, different
1634 	 * causes will share the same interrupt vector as follows:
1635 	 * One interrupt less: non rx causes shared with FBQ.
1636 	 * Two interrupts less: non rx causes shared with FBQ and RSS.
1637 	 * More than two interrupts: we will use fewer RSS queues.
1638 	 */
1639 	if (num_irqs <= max_irqs - 2) {
1640 		trans_pcie->trans->num_rx_queues = num_irqs + 1;
1641 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1642 			IWL_SHARED_IRQ_FIRST_RSS;
1643 	} else if (num_irqs == max_irqs - 1) {
1644 		trans_pcie->trans->num_rx_queues = num_irqs;
1645 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1646 	} else {
1647 		trans_pcie->trans->num_rx_queues = num_irqs - 1;
1648 	}
1649 
1650 	IWL_DEBUG_INFO(trans,
1651 		       "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1652 		       trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1653 
1654 	WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1655 
1656 	trans_pcie->alloc_vecs = num_irqs;
1657 	trans_pcie->msix_enabled = true;
1658 	return;
1659 
1660 enable_msi:
1661 	ret = pci_enable_msi(pdev);
1662 	if (ret) {
1663 		dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1664 		/* enable rfkill interrupt: hw bug w/a */
1665 		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1666 		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1667 			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1668 			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1669 		}
1670 	}
1671 }
1672 
1673 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1674 {
1675 	int iter_rx_q, i, ret, cpu, offset;
1676 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1677 
1678 	i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1679 	iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1680 	offset = 1 + i;
1681 	for (; i < iter_rx_q ; i++) {
1682 		/*
1683 		 * Get the cpu prior to the place to search
1684 		 * (i.e. return will be > i - 1).
1685 		 */
1686 		cpu = cpumask_next(i - offset, cpu_online_mask);
1687 		cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1688 		ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1689 					    &trans_pcie->affinity_mask[i]);
1690 		if (ret)
1691 			IWL_ERR(trans_pcie->trans,
1692 				"Failed to set affinity mask for IRQ %d\n",
1693 				trans_pcie->msix_entries[i].vector);
1694 	}
1695 }
1696 
1697 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1698 				      struct iwl_trans_pcie *trans_pcie)
1699 {
1700 	int i;
1701 
1702 	for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1703 		int ret;
1704 		struct msix_entry *msix_entry;
1705 		const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1706 
1707 		if (!qname)
1708 			return -ENOMEM;
1709 
1710 		msix_entry = &trans_pcie->msix_entries[i];
1711 		ret = devm_request_threaded_irq(&pdev->dev,
1712 						msix_entry->vector,
1713 						iwl_pcie_msix_isr,
1714 						(i == trans_pcie->def_irq) ?
1715 						iwl_pcie_irq_msix_handler :
1716 						iwl_pcie_irq_rx_msix_handler,
1717 						IRQF_SHARED,
1718 						qname,
1719 						msix_entry);
1720 		if (ret) {
1721 			IWL_ERR(trans_pcie->trans,
1722 				"Error allocating IRQ %d\n", i);
1723 
1724 			return ret;
1725 		}
1726 	}
1727 	iwl_pcie_irq_set_affinity(trans_pcie->trans);
1728 
1729 	return 0;
1730 }
1731 
1732 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1733 {
1734 	u32 hpm, wprot;
1735 
1736 	switch (trans->trans_cfg->device_family) {
1737 	case IWL_DEVICE_FAMILY_9000:
1738 		wprot = PREG_PRPH_WPROT_9000;
1739 		break;
1740 	case IWL_DEVICE_FAMILY_22000:
1741 		wprot = PREG_PRPH_WPROT_22000;
1742 		break;
1743 	default:
1744 		return 0;
1745 	}
1746 
1747 	hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1748 	if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1749 		u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1750 
1751 		if (wprot_val & PREG_WFPM_ACCESS) {
1752 			IWL_ERR(trans,
1753 				"Error, can not clear persistence bit\n");
1754 			return -EPERM;
1755 		}
1756 		iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1757 					    hpm & ~PERSISTENCE_BIT);
1758 	}
1759 
1760 	return 0;
1761 }
1762 
1763 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1764 {
1765 	int ret;
1766 
1767 	ret = iwl_finish_nic_init(trans);
1768 	if (ret < 0)
1769 		return ret;
1770 
1771 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1772 			  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1773 	udelay(20);
1774 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1775 			  HPM_HIPM_GEN_CFG_CR_PG_EN |
1776 			  HPM_HIPM_GEN_CFG_CR_SLP_EN);
1777 	udelay(20);
1778 	iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1779 			    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1780 
1781 	iwl_trans_pcie_sw_reset(trans);
1782 
1783 	return 0;
1784 }
1785 
1786 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1787 {
1788 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1789 	int err;
1790 
1791 	lockdep_assert_held(&trans_pcie->mutex);
1792 
1793 	err = iwl_pcie_prepare_card_hw(trans);
1794 	if (err) {
1795 		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1796 		return err;
1797 	}
1798 
1799 	err = iwl_trans_pcie_clear_persistence_bit(trans);
1800 	if (err)
1801 		return err;
1802 
1803 	iwl_trans_pcie_sw_reset(trans);
1804 
1805 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1806 	    trans->trans_cfg->integrated) {
1807 		err = iwl_pcie_gen2_force_power_gating(trans);
1808 		if (err)
1809 			return err;
1810 	}
1811 
1812 	err = iwl_pcie_apm_init(trans);
1813 	if (err)
1814 		return err;
1815 
1816 	iwl_pcie_init_msix(trans_pcie);
1817 
1818 	/* From now on, the op_mode will be kept updated about RF kill state */
1819 	iwl_enable_rfkill_int(trans);
1820 
1821 	trans_pcie->opmode_down = false;
1822 
1823 	/* Set is_down to false here so that...*/
1824 	trans_pcie->is_down = false;
1825 
1826 	/* ...rfkill can call stop_device and set it false if needed */
1827 	iwl_pcie_check_hw_rf_kill(trans);
1828 
1829 	return 0;
1830 }
1831 
1832 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1833 {
1834 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1835 	int ret;
1836 
1837 	mutex_lock(&trans_pcie->mutex);
1838 	ret = _iwl_trans_pcie_start_hw(trans);
1839 	mutex_unlock(&trans_pcie->mutex);
1840 
1841 	return ret;
1842 }
1843 
1844 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1845 {
1846 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1847 
1848 	mutex_lock(&trans_pcie->mutex);
1849 
1850 	/* disable interrupts - don't enable HW RF kill interrupt */
1851 	iwl_disable_interrupts(trans);
1852 
1853 	iwl_pcie_apm_stop(trans, true);
1854 
1855 	iwl_disable_interrupts(trans);
1856 
1857 	iwl_pcie_disable_ict(trans);
1858 
1859 	mutex_unlock(&trans_pcie->mutex);
1860 
1861 	iwl_pcie_synchronize_irqs(trans);
1862 }
1863 
1864 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1865 {
1866 	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1867 }
1868 
1869 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1870 {
1871 	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1872 }
1873 
1874 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1875 {
1876 	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1877 }
1878 
1879 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1880 {
1881 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1882 		return 0x00FFFFFF;
1883 	else
1884 		return 0x000FFFFF;
1885 }
1886 
1887 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1888 {
1889 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1890 
1891 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1892 			       ((reg & mask) | (3 << 24)));
1893 	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1894 }
1895 
1896 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1897 				      u32 val)
1898 {
1899 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1900 
1901 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1902 			       ((addr & mask) | (3 << 24)));
1903 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1904 }
1905 
1906 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1907 				     const struct iwl_trans_config *trans_cfg)
1908 {
1909 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1910 
1911 	/* free all first - we might be reconfigured for a different size */
1912 	iwl_pcie_free_rbs_pool(trans);
1913 
1914 	trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1915 	trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1916 	trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1917 	trans->txqs.page_offs = trans_cfg->cb_data_offs;
1918 	trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1919 
1920 	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1921 		trans_pcie->n_no_reclaim_cmds = 0;
1922 	else
1923 		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1924 	if (trans_pcie->n_no_reclaim_cmds)
1925 		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1926 		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1927 
1928 	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1929 	trans_pcie->rx_page_order =
1930 		iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1931 	trans_pcie->rx_buf_bytes =
1932 		iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1933 	trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1934 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1935 		trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1936 
1937 	trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1938 	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1939 
1940 	trans->command_groups = trans_cfg->command_groups;
1941 	trans->command_groups_size = trans_cfg->command_groups_size;
1942 
1943 	/* Initialize NAPI here - it should be before registering to mac80211
1944 	 * in the opmode but after the HW struct is allocated.
1945 	 * As this function may be called again in some corner cases don't
1946 	 * do anything if NAPI was already initialized.
1947 	 */
1948 	if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1949 		init_dummy_netdev(&trans_pcie->napi_dev);
1950 
1951 	trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1952 }
1953 
1954 void iwl_trans_pcie_free(struct iwl_trans *trans)
1955 {
1956 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1957 	int i;
1958 
1959 	iwl_pcie_synchronize_irqs(trans);
1960 
1961 	if (trans->trans_cfg->gen2)
1962 		iwl_txq_gen2_tx_free(trans);
1963 	else
1964 		iwl_pcie_tx_free(trans);
1965 	iwl_pcie_rx_free(trans);
1966 
1967 	if (trans_pcie->rba.alloc_wq) {
1968 		destroy_workqueue(trans_pcie->rba.alloc_wq);
1969 		trans_pcie->rba.alloc_wq = NULL;
1970 	}
1971 
1972 	if (trans_pcie->msix_enabled) {
1973 		for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1974 			irq_set_affinity_hint(
1975 				trans_pcie->msix_entries[i].vector,
1976 				NULL);
1977 		}
1978 
1979 		trans_pcie->msix_enabled = false;
1980 	} else {
1981 		iwl_pcie_free_ict(trans);
1982 	}
1983 
1984 	iwl_pcie_free_fw_monitor(trans);
1985 
1986 	if (trans_pcie->pnvm_dram.size)
1987 		dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
1988 				  trans_pcie->pnvm_dram.block,
1989 				  trans_pcie->pnvm_dram.physical);
1990 
1991 	if (trans_pcie->reduce_power_dram.size)
1992 		dma_free_coherent(trans->dev,
1993 				  trans_pcie->reduce_power_dram.size,
1994 				  trans_pcie->reduce_power_dram.block,
1995 				  trans_pcie->reduce_power_dram.physical);
1996 
1997 	mutex_destroy(&trans_pcie->mutex);
1998 	iwl_trans_free(trans);
1999 }
2000 
2001 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2002 {
2003 	if (state)
2004 		set_bit(STATUS_TPOWER_PMI, &trans->status);
2005 	else
2006 		clear_bit(STATUS_TPOWER_PMI, &trans->status);
2007 }
2008 
2009 struct iwl_trans_pcie_removal {
2010 	struct pci_dev *pdev;
2011 	struct work_struct work;
2012 };
2013 
2014 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2015 {
2016 	struct iwl_trans_pcie_removal *removal =
2017 		container_of(wk, struct iwl_trans_pcie_removal, work);
2018 	struct pci_dev *pdev = removal->pdev;
2019 	static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2020 
2021 	dev_err(&pdev->dev, "Device gone - attempting removal\n");
2022 	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2023 	pci_lock_rescan_remove();
2024 	pci_dev_put(pdev);
2025 	pci_stop_and_remove_bus_device(pdev);
2026 	pci_unlock_rescan_remove();
2027 
2028 	kfree(removal);
2029 	module_put(THIS_MODULE);
2030 }
2031 
2032 /*
2033  * This version doesn't disable BHs but rather assumes they're
2034  * already disabled.
2035  */
2036 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2037 {
2038 	int ret;
2039 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2040 	u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2041 	u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2042 		   CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2043 	u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2044 
2045 	spin_lock(&trans_pcie->reg_lock);
2046 
2047 	if (trans_pcie->cmd_hold_nic_awake)
2048 		goto out;
2049 
2050 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2051 		write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2052 		mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2053 		poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2054 	}
2055 
2056 	/* this bit wakes up the NIC */
2057 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2058 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2059 		udelay(2);
2060 
2061 	/*
2062 	 * These bits say the device is running, and should keep running for
2063 	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2064 	 * but they do not indicate that embedded SRAM is restored yet;
2065 	 * HW with volatile SRAM must save/restore contents to/from
2066 	 * host DRAM when sleeping/waking for power-saving.
2067 	 * Each direction takes approximately 1/4 millisecond; with this
2068 	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2069 	 * series of register accesses are expected (e.g. reading Event Log),
2070 	 * to keep device from sleeping.
2071 	 *
2072 	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2073 	 * SRAM is okay/restored.  We don't check that here because this call
2074 	 * is just for hardware register access; but GP1 MAC_SLEEP
2075 	 * check is a good idea before accessing the SRAM of HW with
2076 	 * volatile SRAM (e.g. reading Event Log).
2077 	 *
2078 	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2079 	 * and do not save/restore SRAM when power cycling.
2080 	 */
2081 	ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2082 	if (unlikely(ret < 0)) {
2083 		u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2084 
2085 		WARN_ONCE(1,
2086 			  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2087 			  cntrl);
2088 
2089 		iwl_trans_pcie_dump_regs(trans);
2090 
2091 		if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2092 			struct iwl_trans_pcie_removal *removal;
2093 
2094 			if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2095 				goto err;
2096 
2097 			IWL_ERR(trans, "Device gone - scheduling removal!\n");
2098 
2099 			/*
2100 			 * get a module reference to avoid doing this
2101 			 * while unloading anyway and to avoid
2102 			 * scheduling a work with code that's being
2103 			 * removed.
2104 			 */
2105 			if (!try_module_get(THIS_MODULE)) {
2106 				IWL_ERR(trans,
2107 					"Module is being unloaded - abort\n");
2108 				goto err;
2109 			}
2110 
2111 			removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2112 			if (!removal) {
2113 				module_put(THIS_MODULE);
2114 				goto err;
2115 			}
2116 			/*
2117 			 * we don't need to clear this flag, because
2118 			 * the trans will be freed and reallocated.
2119 			*/
2120 			set_bit(STATUS_TRANS_DEAD, &trans->status);
2121 
2122 			removal->pdev = to_pci_dev(trans->dev);
2123 			INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2124 			pci_dev_get(removal->pdev);
2125 			schedule_work(&removal->work);
2126 		} else {
2127 			iwl_write32(trans, CSR_RESET,
2128 				    CSR_RESET_REG_FLAG_FORCE_NMI);
2129 		}
2130 
2131 err:
2132 		spin_unlock(&trans_pcie->reg_lock);
2133 		return false;
2134 	}
2135 
2136 out:
2137 	/*
2138 	 * Fool sparse by faking we release the lock - sparse will
2139 	 * track nic_access anyway.
2140 	 */
2141 	__release(&trans_pcie->reg_lock);
2142 	return true;
2143 }
2144 
2145 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2146 {
2147 	bool ret;
2148 
2149 	local_bh_disable();
2150 	ret = __iwl_trans_pcie_grab_nic_access(trans);
2151 	if (ret) {
2152 		/* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2153 		return ret;
2154 	}
2155 	local_bh_enable();
2156 	return false;
2157 }
2158 
2159 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2160 {
2161 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2162 
2163 	lockdep_assert_held(&trans_pcie->reg_lock);
2164 
2165 	/*
2166 	 * Fool sparse by faking we acquiring the lock - sparse will
2167 	 * track nic_access anyway.
2168 	 */
2169 	__acquire(&trans_pcie->reg_lock);
2170 
2171 	if (trans_pcie->cmd_hold_nic_awake)
2172 		goto out;
2173 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2174 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2175 					   CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2176 	else
2177 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2178 					   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2179 	/*
2180 	 * Above we read the CSR_GP_CNTRL register, which will flush
2181 	 * any previous writes, but we need the write that clears the
2182 	 * MAC_ACCESS_REQ bit to be performed before any other writes
2183 	 * scheduled on different CPUs (after we drop reg_lock).
2184 	 */
2185 out:
2186 	spin_unlock_bh(&trans_pcie->reg_lock);
2187 }
2188 
2189 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2190 				   void *buf, int dwords)
2191 {
2192 	int offs = 0;
2193 	u32 *vals = buf;
2194 
2195 	while (offs < dwords) {
2196 		/* limit the time we spin here under lock to 1/2s */
2197 		unsigned long end = jiffies + HZ / 2;
2198 		bool resched = false;
2199 
2200 		if (iwl_trans_grab_nic_access(trans)) {
2201 			iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2202 				    addr + 4 * offs);
2203 
2204 			while (offs < dwords) {
2205 				vals[offs] = iwl_read32(trans,
2206 							HBUS_TARG_MEM_RDAT);
2207 				offs++;
2208 
2209 				if (time_after(jiffies, end)) {
2210 					resched = true;
2211 					break;
2212 				}
2213 			}
2214 			iwl_trans_release_nic_access(trans);
2215 
2216 			if (resched)
2217 				cond_resched();
2218 		} else {
2219 			return -EBUSY;
2220 		}
2221 	}
2222 
2223 	return 0;
2224 }
2225 
2226 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2227 				    const void *buf, int dwords)
2228 {
2229 	int offs, ret = 0;
2230 	const u32 *vals = buf;
2231 
2232 	if (iwl_trans_grab_nic_access(trans)) {
2233 		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2234 		for (offs = 0; offs < dwords; offs++)
2235 			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2236 				    vals ? vals[offs] : 0);
2237 		iwl_trans_release_nic_access(trans);
2238 	} else {
2239 		ret = -EBUSY;
2240 	}
2241 	return ret;
2242 }
2243 
2244 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2245 					u32 *val)
2246 {
2247 	return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2248 				     ofs, val);
2249 }
2250 
2251 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2252 {
2253 	int i;
2254 
2255 	for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2256 		struct iwl_txq *txq = trans->txqs.txq[i];
2257 
2258 		if (i == trans->txqs.cmd.q_id)
2259 			continue;
2260 
2261 		spin_lock_bh(&txq->lock);
2262 
2263 		if (!block && !(WARN_ON_ONCE(!txq->block))) {
2264 			txq->block--;
2265 			if (!txq->block) {
2266 				iwl_write32(trans, HBUS_TARG_WRPTR,
2267 					    txq->write_ptr | (i << 8));
2268 			}
2269 		} else if (block) {
2270 			txq->block++;
2271 		}
2272 
2273 		spin_unlock_bh(&txq->lock);
2274 	}
2275 }
2276 
2277 #define IWL_FLUSH_WAIT_MS	2000
2278 
2279 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2280 				       struct iwl_trans_rxq_dma_data *data)
2281 {
2282 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2283 
2284 	if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2285 		return -EINVAL;
2286 
2287 	data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2288 	data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2289 	data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2290 	data->fr_bd_wid = 0;
2291 
2292 	return 0;
2293 }
2294 
2295 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2296 {
2297 	struct iwl_txq *txq;
2298 	unsigned long now = jiffies;
2299 	bool overflow_tx;
2300 	u8 wr_ptr;
2301 
2302 	/* Make sure the NIC is still alive in the bus */
2303 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2304 		return -ENODEV;
2305 
2306 	if (!test_bit(txq_idx, trans->txqs.queue_used))
2307 		return -EINVAL;
2308 
2309 	IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2310 	txq = trans->txqs.txq[txq_idx];
2311 
2312 	spin_lock_bh(&txq->lock);
2313 	overflow_tx = txq->overflow_tx ||
2314 		      !skb_queue_empty(&txq->overflow_q);
2315 	spin_unlock_bh(&txq->lock);
2316 
2317 	wr_ptr = READ_ONCE(txq->write_ptr);
2318 
2319 	while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2320 		overflow_tx) &&
2321 	       !time_after(jiffies,
2322 			   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2323 		u8 write_ptr = READ_ONCE(txq->write_ptr);
2324 
2325 		/*
2326 		 * If write pointer moved during the wait, warn only
2327 		 * if the TX came from op mode. In case TX came from
2328 		 * trans layer (overflow TX) don't warn.
2329 		 */
2330 		if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2331 			      "WR pointer moved while flushing %d -> %d\n",
2332 			      wr_ptr, write_ptr))
2333 			return -ETIMEDOUT;
2334 		wr_ptr = write_ptr;
2335 
2336 		usleep_range(1000, 2000);
2337 
2338 		spin_lock_bh(&txq->lock);
2339 		overflow_tx = txq->overflow_tx ||
2340 			      !skb_queue_empty(&txq->overflow_q);
2341 		spin_unlock_bh(&txq->lock);
2342 	}
2343 
2344 	if (txq->read_ptr != txq->write_ptr) {
2345 		IWL_ERR(trans,
2346 			"fail to flush all tx fifo queues Q %d\n", txq_idx);
2347 		iwl_txq_log_scd_error(trans, txq);
2348 		return -ETIMEDOUT;
2349 	}
2350 
2351 	IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2352 
2353 	return 0;
2354 }
2355 
2356 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2357 {
2358 	int cnt;
2359 	int ret = 0;
2360 
2361 	/* waiting for all the tx frames complete might take a while */
2362 	for (cnt = 0;
2363 	     cnt < trans->trans_cfg->base_params->num_of_queues;
2364 	     cnt++) {
2365 
2366 		if (cnt == trans->txqs.cmd.q_id)
2367 			continue;
2368 		if (!test_bit(cnt, trans->txqs.queue_used))
2369 			continue;
2370 		if (!(BIT(cnt) & txq_bm))
2371 			continue;
2372 
2373 		ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2374 		if (ret)
2375 			break;
2376 	}
2377 
2378 	return ret;
2379 }
2380 
2381 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2382 					 u32 mask, u32 value)
2383 {
2384 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2385 
2386 	spin_lock_bh(&trans_pcie->reg_lock);
2387 	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2388 	spin_unlock_bh(&trans_pcie->reg_lock);
2389 }
2390 
2391 static const char *get_csr_string(int cmd)
2392 {
2393 #define IWL_CMD(x) case x: return #x
2394 	switch (cmd) {
2395 	IWL_CMD(CSR_HW_IF_CONFIG_REG);
2396 	IWL_CMD(CSR_INT_COALESCING);
2397 	IWL_CMD(CSR_INT);
2398 	IWL_CMD(CSR_INT_MASK);
2399 	IWL_CMD(CSR_FH_INT_STATUS);
2400 	IWL_CMD(CSR_GPIO_IN);
2401 	IWL_CMD(CSR_RESET);
2402 	IWL_CMD(CSR_GP_CNTRL);
2403 	IWL_CMD(CSR_HW_REV);
2404 	IWL_CMD(CSR_EEPROM_REG);
2405 	IWL_CMD(CSR_EEPROM_GP);
2406 	IWL_CMD(CSR_OTP_GP_REG);
2407 	IWL_CMD(CSR_GIO_REG);
2408 	IWL_CMD(CSR_GP_UCODE_REG);
2409 	IWL_CMD(CSR_GP_DRIVER_REG);
2410 	IWL_CMD(CSR_UCODE_DRV_GP1);
2411 	IWL_CMD(CSR_UCODE_DRV_GP2);
2412 	IWL_CMD(CSR_LED_REG);
2413 	IWL_CMD(CSR_DRAM_INT_TBL_REG);
2414 	IWL_CMD(CSR_GIO_CHICKEN_BITS);
2415 	IWL_CMD(CSR_ANA_PLL_CFG);
2416 	IWL_CMD(CSR_HW_REV_WA_REG);
2417 	IWL_CMD(CSR_MONITOR_STATUS_REG);
2418 	IWL_CMD(CSR_DBG_HPET_MEM_REG);
2419 	default:
2420 		return "UNKNOWN";
2421 	}
2422 #undef IWL_CMD
2423 }
2424 
2425 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2426 {
2427 	int i;
2428 	static const u32 csr_tbl[] = {
2429 		CSR_HW_IF_CONFIG_REG,
2430 		CSR_INT_COALESCING,
2431 		CSR_INT,
2432 		CSR_INT_MASK,
2433 		CSR_FH_INT_STATUS,
2434 		CSR_GPIO_IN,
2435 		CSR_RESET,
2436 		CSR_GP_CNTRL,
2437 		CSR_HW_REV,
2438 		CSR_EEPROM_REG,
2439 		CSR_EEPROM_GP,
2440 		CSR_OTP_GP_REG,
2441 		CSR_GIO_REG,
2442 		CSR_GP_UCODE_REG,
2443 		CSR_GP_DRIVER_REG,
2444 		CSR_UCODE_DRV_GP1,
2445 		CSR_UCODE_DRV_GP2,
2446 		CSR_LED_REG,
2447 		CSR_DRAM_INT_TBL_REG,
2448 		CSR_GIO_CHICKEN_BITS,
2449 		CSR_ANA_PLL_CFG,
2450 		CSR_MONITOR_STATUS_REG,
2451 		CSR_HW_REV_WA_REG,
2452 		CSR_DBG_HPET_MEM_REG
2453 	};
2454 	IWL_ERR(trans, "CSR values:\n");
2455 	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2456 		"CSR_INT_PERIODIC_REG)\n");
2457 	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2458 		IWL_ERR(trans, "  %25s: 0X%08x\n",
2459 			get_csr_string(csr_tbl[i]),
2460 			iwl_read32(trans, csr_tbl[i]));
2461 	}
2462 }
2463 
2464 #ifdef CONFIG_IWLWIFI_DEBUGFS
2465 /* create and remove of files */
2466 #define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
2467 	debugfs_create_file(#name, mode, parent, trans,			\
2468 			    &iwl_dbgfs_##name##_ops);			\
2469 } while (0)
2470 
2471 /* file operation */
2472 #define DEBUGFS_READ_FILE_OPS(name)					\
2473 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2474 	.read = iwl_dbgfs_##name##_read,				\
2475 	.open = simple_open,						\
2476 	.llseek = generic_file_llseek,					\
2477 };
2478 
2479 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2480 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2481 	.write = iwl_dbgfs_##name##_write,                              \
2482 	.open = simple_open,						\
2483 	.llseek = generic_file_llseek,					\
2484 };
2485 
2486 #define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
2487 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2488 	.write = iwl_dbgfs_##name##_write,				\
2489 	.read = iwl_dbgfs_##name##_read,				\
2490 	.open = simple_open,						\
2491 	.llseek = generic_file_llseek,					\
2492 };
2493 
2494 struct iwl_dbgfs_tx_queue_priv {
2495 	struct iwl_trans *trans;
2496 };
2497 
2498 struct iwl_dbgfs_tx_queue_state {
2499 	loff_t pos;
2500 };
2501 
2502 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2503 {
2504 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2505 	struct iwl_dbgfs_tx_queue_state *state;
2506 
2507 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2508 		return NULL;
2509 
2510 	state = kmalloc(sizeof(*state), GFP_KERNEL);
2511 	if (!state)
2512 		return NULL;
2513 	state->pos = *pos;
2514 	return state;
2515 }
2516 
2517 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2518 					 void *v, loff_t *pos)
2519 {
2520 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2521 	struct iwl_dbgfs_tx_queue_state *state = v;
2522 
2523 	*pos = ++state->pos;
2524 
2525 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2526 		return NULL;
2527 
2528 	return state;
2529 }
2530 
2531 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2532 {
2533 	kfree(v);
2534 }
2535 
2536 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2537 {
2538 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2539 	struct iwl_dbgfs_tx_queue_state *state = v;
2540 	struct iwl_trans *trans = priv->trans;
2541 	struct iwl_txq *txq = trans->txqs.txq[state->pos];
2542 
2543 	seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2544 		   (unsigned int)state->pos,
2545 		   !!test_bit(state->pos, trans->txqs.queue_used),
2546 		   !!test_bit(state->pos, trans->txqs.queue_stopped));
2547 	if (txq)
2548 		seq_printf(seq,
2549 			   "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2550 			   txq->read_ptr, txq->write_ptr,
2551 			   txq->need_update, txq->frozen,
2552 			   txq->n_window, txq->ampdu);
2553 	else
2554 		seq_puts(seq, "(unallocated)");
2555 
2556 	if (state->pos == trans->txqs.cmd.q_id)
2557 		seq_puts(seq, " (HCMD)");
2558 	seq_puts(seq, "\n");
2559 
2560 	return 0;
2561 }
2562 
2563 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2564 	.start = iwl_dbgfs_tx_queue_seq_start,
2565 	.next = iwl_dbgfs_tx_queue_seq_next,
2566 	.stop = iwl_dbgfs_tx_queue_seq_stop,
2567 	.show = iwl_dbgfs_tx_queue_seq_show,
2568 };
2569 
2570 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2571 {
2572 	struct iwl_dbgfs_tx_queue_priv *priv;
2573 
2574 	priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2575 				  sizeof(*priv));
2576 
2577 	if (!priv)
2578 		return -ENOMEM;
2579 
2580 	priv->trans = inode->i_private;
2581 	return 0;
2582 }
2583 
2584 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2585 				       char __user *user_buf,
2586 				       size_t count, loff_t *ppos)
2587 {
2588 	struct iwl_trans *trans = file->private_data;
2589 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2590 	char *buf;
2591 	int pos = 0, i, ret;
2592 	size_t bufsz;
2593 
2594 	bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2595 
2596 	if (!trans_pcie->rxq)
2597 		return -EAGAIN;
2598 
2599 	buf = kzalloc(bufsz, GFP_KERNEL);
2600 	if (!buf)
2601 		return -ENOMEM;
2602 
2603 	for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2604 		struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2605 
2606 		pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2607 				 i);
2608 		pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2609 				 rxq->read);
2610 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2611 				 rxq->write);
2612 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2613 				 rxq->write_actual);
2614 		pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2615 				 rxq->need_update);
2616 		pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2617 				 rxq->free_count);
2618 		if (rxq->rb_stts) {
2619 			u32 r =	__le16_to_cpu(iwl_get_closed_rb_stts(trans,
2620 								     rxq));
2621 			pos += scnprintf(buf + pos, bufsz - pos,
2622 					 "\tclosed_rb_num: %u\n",
2623 					 r & 0x0FFF);
2624 		} else {
2625 			pos += scnprintf(buf + pos, bufsz - pos,
2626 					 "\tclosed_rb_num: Not Allocated\n");
2627 		}
2628 	}
2629 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2630 	kfree(buf);
2631 
2632 	return ret;
2633 }
2634 
2635 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2636 					char __user *user_buf,
2637 					size_t count, loff_t *ppos)
2638 {
2639 	struct iwl_trans *trans = file->private_data;
2640 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2641 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2642 
2643 	int pos = 0;
2644 	char *buf;
2645 	int bufsz = 24 * 64; /* 24 items * 64 char per item */
2646 	ssize_t ret;
2647 
2648 	buf = kzalloc(bufsz, GFP_KERNEL);
2649 	if (!buf)
2650 		return -ENOMEM;
2651 
2652 	pos += scnprintf(buf + pos, bufsz - pos,
2653 			"Interrupt Statistics Report:\n");
2654 
2655 	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2656 		isr_stats->hw);
2657 	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2658 		isr_stats->sw);
2659 	if (isr_stats->sw || isr_stats->hw) {
2660 		pos += scnprintf(buf + pos, bufsz - pos,
2661 			"\tLast Restarting Code:  0x%X\n",
2662 			isr_stats->err_code);
2663 	}
2664 #ifdef CONFIG_IWLWIFI_DEBUG
2665 	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2666 		isr_stats->sch);
2667 	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2668 		isr_stats->alive);
2669 #endif
2670 	pos += scnprintf(buf + pos, bufsz - pos,
2671 		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2672 
2673 	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2674 		isr_stats->ctkill);
2675 
2676 	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2677 		isr_stats->wakeup);
2678 
2679 	pos += scnprintf(buf + pos, bufsz - pos,
2680 		"Rx command responses:\t\t %u\n", isr_stats->rx);
2681 
2682 	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2683 		isr_stats->tx);
2684 
2685 	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2686 		isr_stats->unhandled);
2687 
2688 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2689 	kfree(buf);
2690 	return ret;
2691 }
2692 
2693 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2694 					 const char __user *user_buf,
2695 					 size_t count, loff_t *ppos)
2696 {
2697 	struct iwl_trans *trans = file->private_data;
2698 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2699 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2700 	u32 reset_flag;
2701 	int ret;
2702 
2703 	ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2704 	if (ret)
2705 		return ret;
2706 	if (reset_flag == 0)
2707 		memset(isr_stats, 0, sizeof(*isr_stats));
2708 
2709 	return count;
2710 }
2711 
2712 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2713 				   const char __user *user_buf,
2714 				   size_t count, loff_t *ppos)
2715 {
2716 	struct iwl_trans *trans = file->private_data;
2717 
2718 	iwl_pcie_dump_csr(trans);
2719 
2720 	return count;
2721 }
2722 
2723 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2724 				     char __user *user_buf,
2725 				     size_t count, loff_t *ppos)
2726 {
2727 	struct iwl_trans *trans = file->private_data;
2728 	char *buf = NULL;
2729 	ssize_t ret;
2730 
2731 	ret = iwl_dump_fh(trans, &buf);
2732 	if (ret < 0)
2733 		return ret;
2734 	if (!buf)
2735 		return -EINVAL;
2736 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2737 	kfree(buf);
2738 	return ret;
2739 }
2740 
2741 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2742 				     char __user *user_buf,
2743 				     size_t count, loff_t *ppos)
2744 {
2745 	struct iwl_trans *trans = file->private_data;
2746 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2747 	char buf[100];
2748 	int pos;
2749 
2750 	pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2751 			trans_pcie->debug_rfkill,
2752 			!(iwl_read32(trans, CSR_GP_CNTRL) &
2753 				CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2754 
2755 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2756 }
2757 
2758 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2759 				      const char __user *user_buf,
2760 				      size_t count, loff_t *ppos)
2761 {
2762 	struct iwl_trans *trans = file->private_data;
2763 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2764 	bool new_value;
2765 	int ret;
2766 
2767 	ret = kstrtobool_from_user(user_buf, count, &new_value);
2768 	if (ret)
2769 		return ret;
2770 	if (new_value == trans_pcie->debug_rfkill)
2771 		return count;
2772 	IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2773 		 trans_pcie->debug_rfkill, new_value);
2774 	trans_pcie->debug_rfkill = new_value;
2775 	iwl_pcie_handle_rfkill_irq(trans);
2776 
2777 	return count;
2778 }
2779 
2780 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2781 				       struct file *file)
2782 {
2783 	struct iwl_trans *trans = inode->i_private;
2784 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2785 
2786 	if (!trans->dbg.dest_tlv ||
2787 	    trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2788 		IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2789 		return -ENOENT;
2790 	}
2791 
2792 	if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2793 		return -EBUSY;
2794 
2795 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2796 	return simple_open(inode, file);
2797 }
2798 
2799 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2800 					  struct file *file)
2801 {
2802 	struct iwl_trans_pcie *trans_pcie =
2803 		IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2804 
2805 	if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2806 		trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2807 	return 0;
2808 }
2809 
2810 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2811 				  void *buf, ssize_t *size,
2812 				  ssize_t *bytes_copied)
2813 {
2814 	int buf_size_left = count - *bytes_copied;
2815 
2816 	buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2817 	if (*size > buf_size_left)
2818 		*size = buf_size_left;
2819 
2820 	*size -= copy_to_user(user_buf, buf, *size);
2821 	*bytes_copied += *size;
2822 
2823 	if (buf_size_left == *size)
2824 		return true;
2825 	return false;
2826 }
2827 
2828 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2829 					   char __user *user_buf,
2830 					   size_t count, loff_t *ppos)
2831 {
2832 	struct iwl_trans *trans = file->private_data;
2833 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2834 	void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2835 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2836 	u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2837 	ssize_t size, bytes_copied = 0;
2838 	bool b_full;
2839 
2840 	if (trans->dbg.dest_tlv) {
2841 		write_ptr_addr =
2842 			le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2843 		wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2844 	} else {
2845 		write_ptr_addr = MON_BUFF_WRPTR;
2846 		wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2847 	}
2848 
2849 	if (unlikely(!trans->dbg.rec_on))
2850 		return 0;
2851 
2852 	mutex_lock(&data->mutex);
2853 	if (data->state ==
2854 	    IWL_FW_MON_DBGFS_STATE_DISABLED) {
2855 		mutex_unlock(&data->mutex);
2856 		return 0;
2857 	}
2858 
2859 	/* write_ptr position in bytes rather then DW */
2860 	write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2861 	wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2862 
2863 	if (data->prev_wrap_cnt == wrap_cnt) {
2864 		size = write_ptr - data->prev_wr_ptr;
2865 		curr_buf = cpu_addr + data->prev_wr_ptr;
2866 		b_full = iwl_write_to_user_buf(user_buf, count,
2867 					       curr_buf, &size,
2868 					       &bytes_copied);
2869 		data->prev_wr_ptr += size;
2870 
2871 	} else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2872 		   write_ptr < data->prev_wr_ptr) {
2873 		size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2874 		curr_buf = cpu_addr + data->prev_wr_ptr;
2875 		b_full = iwl_write_to_user_buf(user_buf, count,
2876 					       curr_buf, &size,
2877 					       &bytes_copied);
2878 		data->prev_wr_ptr += size;
2879 
2880 		if (!b_full) {
2881 			size = write_ptr;
2882 			b_full = iwl_write_to_user_buf(user_buf, count,
2883 						       cpu_addr, &size,
2884 						       &bytes_copied);
2885 			data->prev_wr_ptr = size;
2886 			data->prev_wrap_cnt++;
2887 		}
2888 	} else {
2889 		if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2890 		    write_ptr > data->prev_wr_ptr)
2891 			IWL_WARN(trans,
2892 				 "write pointer passed previous write pointer, start copying from the beginning\n");
2893 		else if (!unlikely(data->prev_wrap_cnt == 0 &&
2894 				   data->prev_wr_ptr == 0))
2895 			IWL_WARN(trans,
2896 				 "monitor data is out of sync, start copying from the beginning\n");
2897 
2898 		size = write_ptr;
2899 		b_full = iwl_write_to_user_buf(user_buf, count,
2900 					       cpu_addr, &size,
2901 					       &bytes_copied);
2902 		data->prev_wr_ptr = size;
2903 		data->prev_wrap_cnt = wrap_cnt;
2904 	}
2905 
2906 	mutex_unlock(&data->mutex);
2907 
2908 	return bytes_copied;
2909 }
2910 
2911 static ssize_t iwl_dbgfs_rf_read(struct file *file,
2912 				 char __user *user_buf,
2913 				 size_t count, loff_t *ppos)
2914 {
2915 	struct iwl_trans *trans = file->private_data;
2916 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2917 
2918 	if (!trans_pcie->rf_name[0])
2919 		return -ENODEV;
2920 
2921 	return simple_read_from_buffer(user_buf, count, ppos,
2922 				       trans_pcie->rf_name,
2923 				       strlen(trans_pcie->rf_name));
2924 }
2925 
2926 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2927 DEBUGFS_READ_FILE_OPS(fh_reg);
2928 DEBUGFS_READ_FILE_OPS(rx_queue);
2929 DEBUGFS_WRITE_FILE_OPS(csr);
2930 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2931 DEBUGFS_READ_FILE_OPS(rf);
2932 
2933 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2934 	.owner = THIS_MODULE,
2935 	.open = iwl_dbgfs_tx_queue_open,
2936 	.read = seq_read,
2937 	.llseek = seq_lseek,
2938 	.release = seq_release_private,
2939 };
2940 
2941 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2942 	.read = iwl_dbgfs_monitor_data_read,
2943 	.open = iwl_dbgfs_monitor_data_open,
2944 	.release = iwl_dbgfs_monitor_data_release,
2945 };
2946 
2947 /* Create the debugfs files and directories */
2948 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2949 {
2950 	struct dentry *dir = trans->dbgfs_dir;
2951 
2952 	DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2953 	DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2954 	DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2955 	DEBUGFS_ADD_FILE(csr, dir, 0200);
2956 	DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2957 	DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2958 	DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2959 	DEBUGFS_ADD_FILE(rf, dir, 0400);
2960 }
2961 
2962 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2963 {
2964 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2965 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2966 
2967 	mutex_lock(&data->mutex);
2968 	data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
2969 	mutex_unlock(&data->mutex);
2970 }
2971 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2972 
2973 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2974 {
2975 	u32 cmdlen = 0;
2976 	int i;
2977 
2978 	for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
2979 		cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
2980 
2981 	return cmdlen;
2982 }
2983 
2984 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2985 				   struct iwl_fw_error_dump_data **data,
2986 				   int allocated_rb_nums)
2987 {
2988 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2989 	int max_len = trans_pcie->rx_buf_bytes;
2990 	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
2991 	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2992 	u32 i, r, j, rb_len = 0;
2993 
2994 	spin_lock(&rxq->lock);
2995 
2996 	r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2997 
2998 	for (i = rxq->read, j = 0;
2999 	     i != r && j < allocated_rb_nums;
3000 	     i = (i + 1) & RX_QUEUE_MASK, j++) {
3001 		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3002 		struct iwl_fw_error_dump_rb *rb;
3003 
3004 		dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3005 					max_len, DMA_FROM_DEVICE);
3006 
3007 		rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3008 
3009 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3010 		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3011 		rb = (void *)(*data)->data;
3012 		rb->index = cpu_to_le32(i);
3013 		memcpy(rb->data, page_address(rxb->page), max_len);
3014 
3015 		*data = iwl_fw_error_next_data(*data);
3016 	}
3017 
3018 	spin_unlock(&rxq->lock);
3019 
3020 	return rb_len;
3021 }
3022 #define IWL_CSR_TO_DUMP (0x250)
3023 
3024 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3025 				   struct iwl_fw_error_dump_data **data)
3026 {
3027 	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3028 	__le32 *val;
3029 	int i;
3030 
3031 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3032 	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3033 	val = (void *)(*data)->data;
3034 
3035 	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3036 		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3037 
3038 	*data = iwl_fw_error_next_data(*data);
3039 
3040 	return csr_len;
3041 }
3042 
3043 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3044 				       struct iwl_fw_error_dump_data **data)
3045 {
3046 	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3047 	__le32 *val;
3048 	int i;
3049 
3050 	if (!iwl_trans_grab_nic_access(trans))
3051 		return 0;
3052 
3053 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3054 	(*data)->len = cpu_to_le32(fh_regs_len);
3055 	val = (void *)(*data)->data;
3056 
3057 	if (!trans->trans_cfg->gen2)
3058 		for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3059 		     i += sizeof(u32))
3060 			*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3061 	else
3062 		for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3063 		     i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3064 		     i += sizeof(u32))
3065 			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3066 								      i));
3067 
3068 	iwl_trans_release_nic_access(trans);
3069 
3070 	*data = iwl_fw_error_next_data(*data);
3071 
3072 	return sizeof(**data) + fh_regs_len;
3073 }
3074 
3075 static u32
3076 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3077 				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3078 				 u32 monitor_len)
3079 {
3080 	u32 buf_size_in_dwords = (monitor_len >> 2);
3081 	u32 *buffer = (u32 *)fw_mon_data->data;
3082 	u32 i;
3083 
3084 	if (!iwl_trans_grab_nic_access(trans))
3085 		return 0;
3086 
3087 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3088 	for (i = 0; i < buf_size_in_dwords; i++)
3089 		buffer[i] = iwl_read_umac_prph_no_grab(trans,
3090 						       MON_DMARB_RD_DATA_ADDR);
3091 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3092 
3093 	iwl_trans_release_nic_access(trans);
3094 
3095 	return monitor_len;
3096 }
3097 
3098 static void
3099 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3100 			     struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3101 {
3102 	u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3103 
3104 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3105 		base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3106 		base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3107 		write_ptr = DBGC_CUR_DBGBUF_STATUS;
3108 		wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3109 	} else if (trans->dbg.dest_tlv) {
3110 		write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3111 		wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3112 		base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3113 	} else {
3114 		base = MON_BUFF_BASE_ADDR;
3115 		write_ptr = MON_BUFF_WRPTR;
3116 		wrap_cnt = MON_BUFF_CYCLE_CNT;
3117 	}
3118 
3119 	write_ptr_val = iwl_read_prph(trans, write_ptr);
3120 	fw_mon_data->fw_mon_cycle_cnt =
3121 		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3122 	fw_mon_data->fw_mon_base_ptr =
3123 		cpu_to_le32(iwl_read_prph(trans, base));
3124 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3125 		fw_mon_data->fw_mon_base_high_ptr =
3126 			cpu_to_le32(iwl_read_prph(trans, base_high));
3127 		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3128 		/* convert wrtPtr to DWs, to align with all HWs */
3129 		write_ptr_val >>= 2;
3130 	}
3131 	fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3132 }
3133 
3134 static u32
3135 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3136 			    struct iwl_fw_error_dump_data **data,
3137 			    u32 monitor_len)
3138 {
3139 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3140 	u32 len = 0;
3141 
3142 	if (trans->dbg.dest_tlv ||
3143 	    (fw_mon->size &&
3144 	     (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3145 	      trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3146 		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3147 
3148 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3149 		fw_mon_data = (void *)(*data)->data;
3150 
3151 		iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3152 
3153 		len += sizeof(**data) + sizeof(*fw_mon_data);
3154 		if (fw_mon->size) {
3155 			memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3156 			monitor_len = fw_mon->size;
3157 		} else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3158 			u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3159 			/*
3160 			 * Update pointers to reflect actual values after
3161 			 * shifting
3162 			 */
3163 			if (trans->dbg.dest_tlv->version) {
3164 				base = (iwl_read_prph(trans, base) &
3165 					IWL_LDBG_M2S_BUF_BA_MSK) <<
3166 				       trans->dbg.dest_tlv->base_shift;
3167 				base *= IWL_M2S_UNIT_SIZE;
3168 				base += trans->cfg->smem_offset;
3169 			} else {
3170 				base = iwl_read_prph(trans, base) <<
3171 				       trans->dbg.dest_tlv->base_shift;
3172 			}
3173 
3174 			iwl_trans_read_mem(trans, base, fw_mon_data->data,
3175 					   monitor_len / sizeof(u32));
3176 		} else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3177 			monitor_len =
3178 				iwl_trans_pci_dump_marbh_monitor(trans,
3179 								 fw_mon_data,
3180 								 monitor_len);
3181 		} else {
3182 			/* Didn't match anything - output no monitor data */
3183 			monitor_len = 0;
3184 		}
3185 
3186 		len += monitor_len;
3187 		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3188 	}
3189 
3190 	return len;
3191 }
3192 
3193 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3194 {
3195 	if (trans->dbg.fw_mon.size) {
3196 		*len += sizeof(struct iwl_fw_error_dump_data) +
3197 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3198 			trans->dbg.fw_mon.size;
3199 		return trans->dbg.fw_mon.size;
3200 	} else if (trans->dbg.dest_tlv) {
3201 		u32 base, end, cfg_reg, monitor_len;
3202 
3203 		if (trans->dbg.dest_tlv->version == 1) {
3204 			cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3205 			cfg_reg = iwl_read_prph(trans, cfg_reg);
3206 			base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3207 				trans->dbg.dest_tlv->base_shift;
3208 			base *= IWL_M2S_UNIT_SIZE;
3209 			base += trans->cfg->smem_offset;
3210 
3211 			monitor_len =
3212 				(cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3213 				trans->dbg.dest_tlv->end_shift;
3214 			monitor_len *= IWL_M2S_UNIT_SIZE;
3215 		} else {
3216 			base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3217 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3218 
3219 			base = iwl_read_prph(trans, base) <<
3220 			       trans->dbg.dest_tlv->base_shift;
3221 			end = iwl_read_prph(trans, end) <<
3222 			      trans->dbg.dest_tlv->end_shift;
3223 
3224 			/* Make "end" point to the actual end */
3225 			if (trans->trans_cfg->device_family >=
3226 			    IWL_DEVICE_FAMILY_8000 ||
3227 			    trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3228 				end += (1 << trans->dbg.dest_tlv->end_shift);
3229 			monitor_len = end - base;
3230 		}
3231 		*len += sizeof(struct iwl_fw_error_dump_data) +
3232 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3233 			monitor_len;
3234 		return monitor_len;
3235 	}
3236 	return 0;
3237 }
3238 
3239 static struct iwl_trans_dump_data *
3240 iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3241 			 u32 dump_mask,
3242 			 const struct iwl_dump_sanitize_ops *sanitize_ops,
3243 			 void *sanitize_ctx)
3244 {
3245 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3246 	struct iwl_fw_error_dump_data *data;
3247 	struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3248 	struct iwl_fw_error_dump_txcmd *txcmd;
3249 	struct iwl_trans_dump_data *dump_data;
3250 	u32 len, num_rbs = 0, monitor_len = 0;
3251 	int i, ptr;
3252 	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3253 			!trans->trans_cfg->mq_rx_supported &&
3254 			dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3255 
3256 	if (!dump_mask)
3257 		return NULL;
3258 
3259 	/* transport dump header */
3260 	len = sizeof(*dump_data);
3261 
3262 	/* host commands */
3263 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3264 		len += sizeof(*data) +
3265 			cmdq->n_window * (sizeof(*txcmd) +
3266 					  TFD_MAX_PAYLOAD_SIZE);
3267 
3268 	/* FW monitor */
3269 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3270 		monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3271 
3272 	/* CSR registers */
3273 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3274 		len += sizeof(*data) + IWL_CSR_TO_DUMP;
3275 
3276 	/* FH registers */
3277 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3278 		if (trans->trans_cfg->gen2)
3279 			len += sizeof(*data) +
3280 			       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3281 				iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3282 		else
3283 			len += sizeof(*data) +
3284 			       (FH_MEM_UPPER_BOUND -
3285 				FH_MEM_LOWER_BOUND);
3286 	}
3287 
3288 	if (dump_rbs) {
3289 		/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3290 		struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3291 		/* RBs */
3292 		num_rbs =
3293 			le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3294 			& 0x0FFF;
3295 		num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3296 		len += num_rbs * (sizeof(*data) +
3297 				  sizeof(struct iwl_fw_error_dump_rb) +
3298 				  (PAGE_SIZE << trans_pcie->rx_page_order));
3299 	}
3300 
3301 	/* Paged memory for gen2 HW */
3302 	if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3303 		for (i = 0; i < trans->init_dram.paging_cnt; i++)
3304 			len += sizeof(*data) +
3305 			       sizeof(struct iwl_fw_error_dump_paging) +
3306 			       trans->init_dram.paging[i].size;
3307 
3308 	dump_data = vzalloc(len);
3309 	if (!dump_data)
3310 		return NULL;
3311 
3312 	len = 0;
3313 	data = (void *)dump_data->data;
3314 
3315 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3316 		u16 tfd_size = trans->txqs.tfd.size;
3317 
3318 		data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3319 		txcmd = (void *)data->data;
3320 		spin_lock_bh(&cmdq->lock);
3321 		ptr = cmdq->write_ptr;
3322 		for (i = 0; i < cmdq->n_window; i++) {
3323 			u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3324 			u8 tfdidx;
3325 			u32 caplen, cmdlen;
3326 
3327 			if (trans->trans_cfg->use_tfh)
3328 				tfdidx = idx;
3329 			else
3330 				tfdidx = ptr;
3331 
3332 			cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3333 							   (u8 *)cmdq->tfds +
3334 							   tfd_size * tfdidx);
3335 			caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3336 
3337 			if (cmdlen) {
3338 				len += sizeof(*txcmd) + caplen;
3339 				txcmd->cmdlen = cpu_to_le32(cmdlen);
3340 				txcmd->caplen = cpu_to_le32(caplen);
3341 				memcpy(txcmd->data, cmdq->entries[idx].cmd,
3342 				       caplen);
3343 				if (sanitize_ops && sanitize_ops->frob_hcmd)
3344 					sanitize_ops->frob_hcmd(sanitize_ctx,
3345 								txcmd->data,
3346 								caplen);
3347 				txcmd = (void *)((u8 *)txcmd->data + caplen);
3348 			}
3349 
3350 			ptr = iwl_txq_dec_wrap(trans, ptr);
3351 		}
3352 		spin_unlock_bh(&cmdq->lock);
3353 
3354 		data->len = cpu_to_le32(len);
3355 		len += sizeof(*data);
3356 		data = iwl_fw_error_next_data(data);
3357 	}
3358 
3359 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3360 		len += iwl_trans_pcie_dump_csr(trans, &data);
3361 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3362 		len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3363 	if (dump_rbs)
3364 		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3365 
3366 	/* Paged memory for gen2 HW */
3367 	if (trans->trans_cfg->gen2 &&
3368 	    dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3369 		for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3370 			struct iwl_fw_error_dump_paging *paging;
3371 			u32 page_len = trans->init_dram.paging[i].size;
3372 
3373 			data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3374 			data->len = cpu_to_le32(sizeof(*paging) + page_len);
3375 			paging = (void *)data->data;
3376 			paging->index = cpu_to_le32(i);
3377 			memcpy(paging->data,
3378 			       trans->init_dram.paging[i].block, page_len);
3379 			data = iwl_fw_error_next_data(data);
3380 
3381 			len += sizeof(*data) + sizeof(*paging) + page_len;
3382 		}
3383 	}
3384 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3385 		len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3386 
3387 	dump_data->len = len;
3388 
3389 	return dump_data;
3390 }
3391 
3392 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3393 {
3394 	if (enable)
3395 		iwl_enable_interrupts(trans);
3396 	else
3397 		iwl_disable_interrupts(trans);
3398 }
3399 
3400 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3401 {
3402 	u32 inta_addr, sw_err_bit;
3403 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3404 
3405 	if (trans_pcie->msix_enabled) {
3406 		inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3407 		if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3408 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3409 		else
3410 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3411 	} else {
3412 		inta_addr = CSR_INT;
3413 		sw_err_bit = CSR_INT_BIT_SW_ERR;
3414 	}
3415 
3416 	iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3417 }
3418 
3419 #define IWL_TRANS_COMMON_OPS						\
3420 	.op_mode_leave = iwl_trans_pcie_op_mode_leave,			\
3421 	.write8 = iwl_trans_pcie_write8,				\
3422 	.write32 = iwl_trans_pcie_write32,				\
3423 	.read32 = iwl_trans_pcie_read32,				\
3424 	.read_prph = iwl_trans_pcie_read_prph,				\
3425 	.write_prph = iwl_trans_pcie_write_prph,			\
3426 	.read_mem = iwl_trans_pcie_read_mem,				\
3427 	.write_mem = iwl_trans_pcie_write_mem,				\
3428 	.read_config32 = iwl_trans_pcie_read_config32,			\
3429 	.configure = iwl_trans_pcie_configure,				\
3430 	.set_pmi = iwl_trans_pcie_set_pmi,				\
3431 	.sw_reset = iwl_trans_pcie_sw_reset,				\
3432 	.grab_nic_access = iwl_trans_pcie_grab_nic_access,		\
3433 	.release_nic_access = iwl_trans_pcie_release_nic_access,	\
3434 	.set_bits_mask = iwl_trans_pcie_set_bits_mask,			\
3435 	.dump_data = iwl_trans_pcie_dump_data,				\
3436 	.d3_suspend = iwl_trans_pcie_d3_suspend,			\
3437 	.d3_resume = iwl_trans_pcie_d3_resume,				\
3438 	.interrupts = iwl_trans_pci_interrupts,				\
3439 	.sync_nmi = iwl_trans_pcie_sync_nmi				\
3440 
3441 static const struct iwl_trans_ops trans_ops_pcie = {
3442 	IWL_TRANS_COMMON_OPS,
3443 	.start_hw = iwl_trans_pcie_start_hw,
3444 	.fw_alive = iwl_trans_pcie_fw_alive,
3445 	.start_fw = iwl_trans_pcie_start_fw,
3446 	.stop_device = iwl_trans_pcie_stop_device,
3447 
3448 	.send_cmd = iwl_pcie_enqueue_hcmd,
3449 
3450 	.tx = iwl_trans_pcie_tx,
3451 	.reclaim = iwl_txq_reclaim,
3452 
3453 	.txq_disable = iwl_trans_pcie_txq_disable,
3454 	.txq_enable = iwl_trans_pcie_txq_enable,
3455 
3456 	.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3457 
3458 	.wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3459 
3460 	.freeze_txq_timer = iwl_trans_txq_freeze_timer,
3461 	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3462 #ifdef CONFIG_IWLWIFI_DEBUGFS
3463 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3464 #endif
3465 };
3466 
3467 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3468 	IWL_TRANS_COMMON_OPS,
3469 	.start_hw = iwl_trans_pcie_start_hw,
3470 	.fw_alive = iwl_trans_pcie_gen2_fw_alive,
3471 	.start_fw = iwl_trans_pcie_gen2_start_fw,
3472 	.stop_device = iwl_trans_pcie_gen2_stop_device,
3473 
3474 	.send_cmd = iwl_pcie_gen2_enqueue_hcmd,
3475 
3476 	.tx = iwl_txq_gen2_tx,
3477 	.reclaim = iwl_txq_reclaim,
3478 
3479 	.set_q_ptrs = iwl_txq_set_q_ptrs,
3480 
3481 	.txq_alloc = iwl_txq_dyn_alloc,
3482 	.txq_free = iwl_txq_dyn_free,
3483 	.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3484 	.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3485 	.set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3486 	.set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3487 #ifdef CONFIG_IWLWIFI_DEBUGFS
3488 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3489 #endif
3490 };
3491 
3492 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3493 			       const struct pci_device_id *ent,
3494 			       const struct iwl_cfg_trans_params *cfg_trans)
3495 {
3496 	struct iwl_trans_pcie *trans_pcie;
3497 	struct iwl_trans *trans;
3498 	int ret, addr_size;
3499 	const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3500 	void __iomem * const *table;
3501 
3502 	if (!cfg_trans->gen2)
3503 		ops = &trans_ops_pcie;
3504 
3505 	ret = pcim_enable_device(pdev);
3506 	if (ret)
3507 		return ERR_PTR(ret);
3508 
3509 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3510 				cfg_trans);
3511 	if (!trans)
3512 		return ERR_PTR(-ENOMEM);
3513 
3514 	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3515 
3516 	trans_pcie->trans = trans;
3517 	trans_pcie->opmode_down = true;
3518 	spin_lock_init(&trans_pcie->irq_lock);
3519 	spin_lock_init(&trans_pcie->reg_lock);
3520 	spin_lock_init(&trans_pcie->alloc_page_lock);
3521 	mutex_init(&trans_pcie->mutex);
3522 	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3523 	init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3524 
3525 	trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3526 						   WQ_HIGHPRI | WQ_UNBOUND, 1);
3527 	if (!trans_pcie->rba.alloc_wq) {
3528 		ret = -ENOMEM;
3529 		goto out_free_trans;
3530 	}
3531 	INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3532 
3533 	trans_pcie->debug_rfkill = -1;
3534 
3535 	if (!cfg_trans->base_params->pcie_l1_allowed) {
3536 		/*
3537 		 * W/A - seems to solve weird behavior. We need to remove this
3538 		 * if we don't want to stay in L1 all the time. This wastes a
3539 		 * lot of power.
3540 		 */
3541 		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3542 				       PCIE_LINK_STATE_L1 |
3543 				       PCIE_LINK_STATE_CLKPM);
3544 	}
3545 
3546 	trans_pcie->def_rx_queue = 0;
3547 
3548 	pci_set_master(pdev);
3549 
3550 	addr_size = trans->txqs.tfd.addr_size;
3551 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3552 	if (ret) {
3553 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3554 		/* both attempts failed: */
3555 		if (ret) {
3556 			dev_err(&pdev->dev, "No suitable DMA available\n");
3557 			goto out_no_pci;
3558 		}
3559 	}
3560 
3561 	ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3562 	if (ret) {
3563 		dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3564 		goto out_no_pci;
3565 	}
3566 
3567 	table = pcim_iomap_table(pdev);
3568 	if (!table) {
3569 		dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3570 		ret = -ENOMEM;
3571 		goto out_no_pci;
3572 	}
3573 
3574 	trans_pcie->hw_base = table[0];
3575 	if (!trans_pcie->hw_base) {
3576 		dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3577 		ret = -ENODEV;
3578 		goto out_no_pci;
3579 	}
3580 
3581 	/* We disable the RETRY_TIMEOUT register (0x41) to keep
3582 	 * PCI Tx retries from interfering with C3 CPU state */
3583 	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3584 
3585 	trans_pcie->pci_dev = pdev;
3586 	iwl_disable_interrupts(trans);
3587 
3588 	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3589 	if (trans->hw_rev == 0xffffffff) {
3590 		dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3591 		ret = -EIO;
3592 		goto out_no_pci;
3593 	}
3594 
3595 	/*
3596 	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3597 	 * changed, and now the revision step also includes bit 0-1 (no more
3598 	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3599 	 * in the old format.
3600 	 */
3601 	if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
3602 		trans->hw_rev = (trans->hw_rev & 0xfff0) |
3603 				(CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3604 
3605 	IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3606 
3607 	iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3608 	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3609 	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3610 		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3611 
3612 	init_waitqueue_head(&trans_pcie->sx_waitq);
3613 
3614 
3615 	if (trans_pcie->msix_enabled) {
3616 		ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3617 		if (ret)
3618 			goto out_no_pci;
3619 	 } else {
3620 		ret = iwl_pcie_alloc_ict(trans);
3621 		if (ret)
3622 			goto out_no_pci;
3623 
3624 		ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3625 						iwl_pcie_isr,
3626 						iwl_pcie_irq_handler,
3627 						IRQF_SHARED, DRV_NAME, trans);
3628 		if (ret) {
3629 			IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3630 			goto out_free_ict;
3631 		}
3632 	 }
3633 
3634 #ifdef CONFIG_IWLWIFI_DEBUGFS
3635 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3636 	mutex_init(&trans_pcie->fw_mon_data.mutex);
3637 #endif
3638 
3639 	iwl_dbg_tlv_init(trans);
3640 
3641 	return trans;
3642 
3643 out_free_ict:
3644 	iwl_pcie_free_ict(trans);
3645 out_no_pci:
3646 	destroy_workqueue(trans_pcie->rba.alloc_wq);
3647 out_free_trans:
3648 	iwl_trans_free(trans);
3649 	return ERR_PTR(ret);
3650 }
3651