1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "iwl-fw-error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92 { 93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94 95 if (!trans_pcie->fw_mon_page) 96 return; 97 98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100 __free_pages(trans_pcie->fw_mon_page, 101 get_order(trans_pcie->fw_mon_size)); 102 trans_pcie->fw_mon_page = NULL; 103 trans_pcie->fw_mon_phys = 0; 104 trans_pcie->fw_mon_size = 0; 105 } 106 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108 { 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110 struct page *page = NULL; 111 dma_addr_t phys; 112 u32 size = 0; 113 u8 power; 114 115 if (!max_power) { 116 /* default max_power is maximum */ 117 max_power = 26; 118 } else { 119 max_power += 11; 120 } 121 122 if (WARN(max_power > 26, 123 "External buffer size for monitor is too big %d, check the FW TLV\n", 124 max_power)) 125 return; 126 127 if (trans_pcie->fw_mon_page) { 128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129 trans_pcie->fw_mon_size, 130 DMA_FROM_DEVICE); 131 return; 132 } 133 134 phys = 0; 135 for (power = max_power; power >= 11; power--) { 136 int order; 137 138 size = BIT(power); 139 order = get_order(size); 140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141 order); 142 if (!page) 143 continue; 144 145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146 DMA_FROM_DEVICE); 147 if (dma_mapping_error(trans->dev, phys)) { 148 __free_pages(page, order); 149 page = NULL; 150 continue; 151 } 152 IWL_INFO(trans, 153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154 size, order); 155 break; 156 } 157 158 if (WARN_ON_ONCE(!page)) 159 return; 160 161 if (power != max_power) 162 IWL_ERR(trans, 163 "Sorry - debug buffer is only %luK while you requested %luK\n", 164 (unsigned long)BIT(power - 10), 165 (unsigned long)BIT(max_power - 10)); 166 167 trans_pcie->fw_mon_page = page; 168 trans_pcie->fw_mon_phys = phys; 169 trans_pcie->fw_mon_size = size; 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->cfg->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212 * Check if BIOS (or OS) enabled L1-ASPM on this device. 213 * If so (likely), disable L0S, so device moves directly L0->L1; 214 * costs negligible amount of power savings. 215 * If not (unlikely), enable L0S, so there is at least some 216 * power savings, even without L1. 217 */ 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221 else 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224 225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229 trans->ltr_enabled ? "En" : "Dis"); 230 } 231 232 /* 233 * Start up NIC's basic functionality after it has been reset 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235 * NOTE: This does not load uCode nor start the embedded processor 236 */ 237 static int iwl_pcie_apm_init(struct iwl_trans *trans) 238 { 239 int ret = 0; 240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 241 242 /* 243 * Use "set_bit" below rather than "write", to preserve any hardware 244 * bits already set by default after reset. 245 */ 246 247 /* Disable L0S exit timer (platform NMI Work/Around) */ 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 251 252 /* 253 * Disable L0s without affecting L1; 254 * don't wait for ICH L0s (ICH bug W/A) 255 */ 256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 258 259 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 261 262 /* 263 * Enable HAP INTA (interrupt from management bus) to 264 * wake device's PCI Express link L1a -> L0s 265 */ 266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 268 269 iwl_pcie_apm_config(trans); 270 271 /* Configure analog phase-lock-loop before activating to D0A */ 272 if (trans->cfg->base_params->pll_cfg) 273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 274 275 /* 276 * Set "initialization complete" bit to move adapter from 277 * D0U* --> D0A* (powered-up active) state. 278 */ 279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 280 281 /* 282 * Wait for clock stabilization; once stabilized, access to 283 * device-internal resources is supported, e.g. iwl_write_prph() 284 * and accesses to uCode SRAM. 285 */ 286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 289 if (ret < 0) { 290 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 291 goto out; 292 } 293 294 if (trans->cfg->host_interrupt_operation_mode) { 295 /* 296 * This is a bit of an abuse - This is needed for 7260 / 3160 297 * only check host_interrupt_operation_mode even if this is 298 * not related to host_interrupt_operation_mode. 299 * 300 * Enable the oscillator to count wake up time for L1 exit. This 301 * consumes slightly more power (100uA) - but allows to be sure 302 * that we wake up from L1 on time. 303 * 304 * This looks weird: read twice the same register, discard the 305 * value, set a bit, and yet again, read that same register 306 * just to discard the value. But that's the way the hardware 307 * seems to like it. 308 */ 309 iwl_read_prph(trans, OSC_CLK); 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 312 iwl_read_prph(trans, OSC_CLK); 313 iwl_read_prph(trans, OSC_CLK); 314 } 315 316 /* 317 * Enable DMA clock and wait for it to stabilize. 318 * 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 320 * bits do not disable clocks. This preserves any hardware 321 * bits already set by default in "CLK_CTRL_REG" after reset. 322 */ 323 if (!trans->cfg->apmg_not_supported) { 324 iwl_write_prph(trans, APMG_CLK_EN_REG, 325 APMG_CLK_VAL_DMA_CLK_RQT); 326 udelay(20); 327 328 /* Disable L1-Active */ 329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 331 332 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 334 APMG_RTC_INT_STT_RFKILL); 335 } 336 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 338 339 out: 340 return ret; 341 } 342 343 /* 344 * Enable LP XTAL to avoid HW bug where device may consume much power if 345 * FW is not loaded after device reset. LP XTAL is disabled by default 346 * after device HW reset. Do it only if XTAL is fed by internal source. 347 * Configure device's "persistence" mode to avoid resetting XTAL again when 348 * SHRD_HW_RST occurs in S3. 349 */ 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351 { 352 int ret; 353 u32 apmg_gp1_reg; 354 u32 apmg_xtal_cfg_reg; 355 u32 dl_cfg_reg; 356 357 /* Force XTAL ON */ 358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360 361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 363 usleep_range(1000, 2000); 364 365 /* 366 * Set "initialization complete" bit to move adapter from 367 * D0U* --> D0A* (powered-up active) state. 368 */ 369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 370 371 /* 372 * Wait for clock stabilization; once stabilized, access to 373 * device-internal resources is possible. 374 */ 375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378 25000); 379 if (WARN_ON(ret < 0)) { 380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 381 /* Release XTAL ON request */ 382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384 return; 385 } 386 387 /* 388 * Clear "disable persistence" to avoid LP XTAL resetting when 389 * SHRD_HW_RST is applied in S3. 390 */ 391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 392 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 393 394 /* 395 * Force APMG XTAL to be active to prevent its disabling by HW 396 * caused by APMG idle state. 397 */ 398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 399 SHR_APMG_XTAL_CFG_REG); 400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 401 apmg_xtal_cfg_reg | 402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 403 404 /* 405 * Reset entire device again - do controller reset (results in 406 * SHRD_HW_RST). Turn MAC off before proceeding. 407 */ 408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 409 usleep_range(1000, 2000); 410 411 /* Enable LP XTAL by indirect access through CSR */ 412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 414 SHR_APMG_GP1_WF_XTAL_LP_EN | 415 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 416 417 /* Clear delay line clock power up */ 418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 421 422 /* 423 * Enable persistence mode to avoid LP XTAL resetting when 424 * SHRD_HW_RST is applied in S3. 425 */ 426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 428 429 /* 430 * Clear "initialization complete" bit to move adapter from 431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 432 */ 433 iwl_clear_bit(trans, CSR_GP_CNTRL, 434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 435 436 /* Activates XTAL resources monitor */ 437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 438 CSR_MONITOR_XTAL_RESOURCES); 439 440 /* Release XTAL ON request */ 441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 443 udelay(10); 444 445 /* Release APMG XTAL */ 446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 447 apmg_xtal_cfg_reg & 448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 449 } 450 451 int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 452 { 453 int ret = 0; 454 455 /* stop device's busmaster DMA activity */ 456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 457 458 ret = iwl_poll_bit(trans, CSR_RESET, 459 CSR_RESET_REG_FLAG_MASTER_DISABLED, 460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 461 if (ret < 0) 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 463 464 IWL_DEBUG_INFO(trans, "stop master\n"); 465 466 return ret; 467 } 468 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 470 { 471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 472 473 if (op_mode_leave) { 474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 475 iwl_pcie_apm_init(trans); 476 477 /* inform ME that we are leaving */ 478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 480 APMG_PCIDEV_STT_VAL_WAKE_ME); 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 483 CSR_RESET_LINK_PWR_MGMT_DISABLED); 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485 CSR_HW_IF_CONFIG_REG_PREPARE | 486 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 487 mdelay(1); 488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 489 CSR_RESET_LINK_PWR_MGMT_DISABLED); 490 } 491 mdelay(5); 492 } 493 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 495 496 /* Stop device's DMA activity */ 497 iwl_pcie_apm_stop_master(trans); 498 499 if (trans->cfg->lp_xtal_workaround) { 500 iwl_pcie_apm_lp_xtal_enable(trans); 501 return; 502 } 503 504 /* Reset the entire device */ 505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 506 usleep_range(1000, 2000); 507 508 /* 509 * Clear "initialization complete" bit to move adapter from 510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 511 */ 512 iwl_clear_bit(trans, CSR_GP_CNTRL, 513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 514 } 515 516 static int iwl_pcie_nic_init(struct iwl_trans *trans) 517 { 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 519 520 /* nic_init */ 521 spin_lock(&trans_pcie->irq_lock); 522 iwl_pcie_apm_init(trans); 523 524 spin_unlock(&trans_pcie->irq_lock); 525 526 iwl_pcie_set_pwr(trans, false); 527 528 iwl_op_mode_nic_config(trans->op_mode); 529 530 /* Allocate the RX queue, or reset if it is already allocated */ 531 iwl_pcie_rx_init(trans); 532 533 /* Allocate or reset and init all Tx and Command queues */ 534 if (iwl_pcie_tx_init(trans)) 535 return -ENOMEM; 536 537 if (trans->cfg->base_params->shadow_reg_enable) { 538 /* enable shadow regs in HW */ 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 541 } 542 543 return 0; 544 } 545 546 #define HW_READY_TIMEOUT (50) 547 548 /* Note: returns poll_bit return value, which is >= 0 if success */ 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 550 { 551 int ret; 552 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 555 556 /* See if we got it */ 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560 HW_READY_TIMEOUT); 561 562 if (ret >= 0) 563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 564 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 566 return ret; 567 } 568 569 /* Note: returns standard 0/-ERROR code */ 570 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 571 { 572 int ret; 573 int t = 0; 574 int iter; 575 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 577 578 ret = iwl_pcie_set_hw_ready(trans); 579 /* If the card is ready, exit 0 */ 580 if (ret >= 0) 581 return 0; 582 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 584 CSR_RESET_LINK_PWR_MGMT_DISABLED); 585 usleep_range(1000, 2000); 586 587 for (iter = 0; iter < 10; iter++) { 588 /* If HW is not ready, prepare the conditions to check again */ 589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 590 CSR_HW_IF_CONFIG_REG_PREPARE); 591 592 do { 593 ret = iwl_pcie_set_hw_ready(trans); 594 if (ret >= 0) 595 return 0; 596 597 usleep_range(200, 1000); 598 t += 200; 599 } while (t < 150000); 600 msleep(25); 601 } 602 603 IWL_ERR(trans, "Couldn't prepare the card\n"); 604 605 return ret; 606 } 607 608 /* 609 * ucode 610 */ 611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 612 u32 dst_addr, dma_addr_t phy_addr, 613 u32 byte_cnt) 614 { 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 617 618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 619 dst_addr); 620 621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 623 624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 625 (iwl_get_dma_hi_addr(phy_addr) 626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 627 628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 632 633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 637 } 638 639 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 640 u32 dst_addr, dma_addr_t phy_addr, 641 u32 byte_cnt) 642 { 643 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 644 unsigned long flags; 645 int ret; 646 647 trans_pcie->ucode_write_complete = false; 648 649 if (!iwl_trans_grab_nic_access(trans, &flags)) 650 return -EIO; 651 652 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 653 byte_cnt); 654 iwl_trans_release_nic_access(trans, &flags); 655 656 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 657 trans_pcie->ucode_write_complete, 5 * HZ); 658 if (!ret) { 659 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 660 return -ETIMEDOUT; 661 } 662 663 return 0; 664 } 665 666 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 667 const struct fw_desc *section) 668 { 669 u8 *v_addr; 670 dma_addr_t p_addr; 671 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 672 int ret = 0; 673 674 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 675 section_num); 676 677 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 678 GFP_KERNEL | __GFP_NOWARN); 679 if (!v_addr) { 680 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 681 chunk_sz = PAGE_SIZE; 682 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 683 &p_addr, GFP_KERNEL); 684 if (!v_addr) 685 return -ENOMEM; 686 } 687 688 for (offset = 0; offset < section->len; offset += chunk_sz) { 689 u32 copy_size, dst_addr; 690 bool extended_addr = false; 691 692 copy_size = min_t(u32, chunk_sz, section->len - offset); 693 dst_addr = section->offset + offset; 694 695 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 696 dst_addr <= IWL_FW_MEM_EXTENDED_END) 697 extended_addr = true; 698 699 if (extended_addr) 700 iwl_set_bits_prph(trans, LMPM_CHICK, 701 LMPM_CHICK_EXTENDED_ADDR_SPACE); 702 703 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 704 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 705 copy_size); 706 707 if (extended_addr) 708 iwl_clear_bits_prph(trans, LMPM_CHICK, 709 LMPM_CHICK_EXTENDED_ADDR_SPACE); 710 711 if (ret) { 712 IWL_ERR(trans, 713 "Could not load the [%d] uCode section\n", 714 section_num); 715 break; 716 } 717 } 718 719 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 720 return ret; 721 } 722 723 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 724 const struct fw_img *image, 725 int cpu, 726 int *first_ucode_section) 727 { 728 int shift_param; 729 int i, ret = 0, sec_num = 0x1; 730 u32 val, last_read_idx = 0; 731 732 if (cpu == 1) { 733 shift_param = 0; 734 *first_ucode_section = 0; 735 } else { 736 shift_param = 16; 737 (*first_ucode_section)++; 738 } 739 740 for (i = *first_ucode_section; i < image->num_sec; i++) { 741 last_read_idx = i; 742 743 /* 744 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 745 * CPU1 to CPU2. 746 * PAGING_SEPARATOR_SECTION delimiter - separate between 747 * CPU2 non paged to CPU2 paging sec. 748 */ 749 if (!image->sec[i].data || 750 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 751 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 752 IWL_DEBUG_FW(trans, 753 "Break since Data not valid or Empty section, sec = %d\n", 754 i); 755 break; 756 } 757 758 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 759 if (ret) 760 return ret; 761 762 /* Notify ucode of loaded section number and status */ 763 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 764 val = val | (sec_num << shift_param); 765 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 766 767 sec_num = (sec_num << 1) | 0x1; 768 } 769 770 *first_ucode_section = last_read_idx; 771 772 iwl_enable_interrupts(trans); 773 774 if (trans->cfg->use_tfh) { 775 if (cpu == 1) 776 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 777 0xFFFF); 778 else 779 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 780 0xFFFFFFFF); 781 } else { 782 if (cpu == 1) 783 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 784 0xFFFF); 785 else 786 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 787 0xFFFFFFFF); 788 } 789 790 return 0; 791 } 792 793 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 794 const struct fw_img *image, 795 int cpu, 796 int *first_ucode_section) 797 { 798 int i, ret = 0; 799 u32 last_read_idx = 0; 800 801 if (cpu == 1) 802 *first_ucode_section = 0; 803 else 804 (*first_ucode_section)++; 805 806 for (i = *first_ucode_section; i < image->num_sec; i++) { 807 last_read_idx = i; 808 809 /* 810 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 811 * CPU1 to CPU2. 812 * PAGING_SEPARATOR_SECTION delimiter - separate between 813 * CPU2 non paged to CPU2 paging sec. 814 */ 815 if (!image->sec[i].data || 816 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 817 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 818 IWL_DEBUG_FW(trans, 819 "Break since Data not valid or Empty section, sec = %d\n", 820 i); 821 break; 822 } 823 824 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 825 if (ret) 826 return ret; 827 } 828 829 *first_ucode_section = last_read_idx; 830 831 return 0; 832 } 833 834 void iwl_pcie_apply_destination(struct iwl_trans *trans) 835 { 836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 837 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 838 int i; 839 840 if (dest->version) 841 IWL_ERR(trans, 842 "DBG DEST version is %d - expect issues\n", 843 dest->version); 844 845 IWL_INFO(trans, "Applying debug destination %s\n", 846 get_fw_dbg_mode_string(dest->monitor_mode)); 847 848 if (dest->monitor_mode == EXTERNAL_MODE) 849 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 850 else 851 IWL_WARN(trans, "PCI should have external buffer debug\n"); 852 853 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 854 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 855 u32 val = le32_to_cpu(dest->reg_ops[i].val); 856 857 switch (dest->reg_ops[i].op) { 858 case CSR_ASSIGN: 859 iwl_write32(trans, addr, val); 860 break; 861 case CSR_SETBIT: 862 iwl_set_bit(trans, addr, BIT(val)); 863 break; 864 case CSR_CLEARBIT: 865 iwl_clear_bit(trans, addr, BIT(val)); 866 break; 867 case PRPH_ASSIGN: 868 iwl_write_prph(trans, addr, val); 869 break; 870 case PRPH_SETBIT: 871 iwl_set_bits_prph(trans, addr, BIT(val)); 872 break; 873 case PRPH_CLEARBIT: 874 iwl_clear_bits_prph(trans, addr, BIT(val)); 875 break; 876 case PRPH_BLOCKBIT: 877 if (iwl_read_prph(trans, addr) & BIT(val)) { 878 IWL_ERR(trans, 879 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 880 val, addr); 881 goto monitor; 882 } 883 break; 884 default: 885 IWL_ERR(trans, "FW debug - unknown OP %d\n", 886 dest->reg_ops[i].op); 887 break; 888 } 889 } 890 891 monitor: 892 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 893 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 894 trans_pcie->fw_mon_phys >> dest->base_shift); 895 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 896 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 897 (trans_pcie->fw_mon_phys + 898 trans_pcie->fw_mon_size - 256) >> 899 dest->end_shift); 900 else 901 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 902 (trans_pcie->fw_mon_phys + 903 trans_pcie->fw_mon_size) >> 904 dest->end_shift); 905 } 906 } 907 908 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 909 const struct fw_img *image) 910 { 911 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 912 int ret = 0; 913 int first_ucode_section; 914 915 IWL_DEBUG_FW(trans, "working with %s CPU\n", 916 image->is_dual_cpus ? "Dual" : "Single"); 917 918 /* load to FW the binary non secured sections of CPU1 */ 919 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 920 if (ret) 921 return ret; 922 923 if (image->is_dual_cpus) { 924 /* set CPU2 header address */ 925 iwl_write_prph(trans, 926 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 927 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 928 929 /* load to FW the binary sections of CPU2 */ 930 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 931 &first_ucode_section); 932 if (ret) 933 return ret; 934 } 935 936 /* supported for 7000 only for the moment */ 937 if (iwlwifi_mod_params.fw_monitor && 938 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 939 iwl_pcie_alloc_fw_monitor(trans, 0); 940 941 if (trans_pcie->fw_mon_size) { 942 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 943 trans_pcie->fw_mon_phys >> 4); 944 iwl_write_prph(trans, MON_BUFF_END_ADDR, 945 (trans_pcie->fw_mon_phys + 946 trans_pcie->fw_mon_size) >> 4); 947 } 948 } else if (trans->dbg_dest_tlv) { 949 iwl_pcie_apply_destination(trans); 950 } 951 952 iwl_enable_interrupts(trans); 953 954 /* release CPU reset */ 955 iwl_write32(trans, CSR_RESET, 0); 956 957 return 0; 958 } 959 960 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 961 const struct fw_img *image) 962 { 963 int ret = 0; 964 int first_ucode_section; 965 966 IWL_DEBUG_FW(trans, "working with %s CPU\n", 967 image->is_dual_cpus ? "Dual" : "Single"); 968 969 if (trans->dbg_dest_tlv) 970 iwl_pcie_apply_destination(trans); 971 972 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 973 iwl_read_prph(trans, WFPM_GP2)); 974 975 /* 976 * Set default value. On resume reading the values that were 977 * zeored can provide debug data on the resume flow. 978 * This is for debugging only and has no functional impact. 979 */ 980 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 981 982 /* configure the ucode to be ready to get the secured image */ 983 /* release CPU reset */ 984 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 985 986 /* load to FW the binary Secured sections of CPU1 */ 987 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 988 &first_ucode_section); 989 if (ret) 990 return ret; 991 992 /* load to FW the binary sections of CPU2 */ 993 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 994 &first_ucode_section); 995 } 996 997 bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans) 998 { 999 bool hw_rfkill = iwl_is_rfkill_set(trans); 1000 1001 if (hw_rfkill) 1002 set_bit(STATUS_RFKILL, &trans->status); 1003 else 1004 clear_bit(STATUS_RFKILL, &trans->status); 1005 1006 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1007 1008 return hw_rfkill; 1009 } 1010 1011 struct iwl_causes_list { 1012 u32 cause_num; 1013 u32 mask_reg; 1014 u8 addr; 1015 }; 1016 1017 static struct iwl_causes_list causes_list[] = { 1018 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1019 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1020 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1021 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1022 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1023 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1024 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1025 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1026 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1027 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1028 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1029 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1030 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1031 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1032 }; 1033 1034 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1035 { 1036 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1037 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1038 int i; 1039 1040 /* 1041 * Access all non RX causes and map them to the default irq. 1042 * In case we are missing at least one interrupt vector, 1043 * the first interrupt vector will serve non-RX and FBQ causes. 1044 */ 1045 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1046 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1047 iwl_clear_bit(trans, causes_list[i].mask_reg, 1048 causes_list[i].cause_num); 1049 } 1050 } 1051 1052 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1053 { 1054 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1055 u32 offset = 1056 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1057 u32 val, idx; 1058 1059 /* 1060 * The first RX queue - fallback queue, which is designated for 1061 * management frame, command responses etc, is always mapped to the 1062 * first interrupt vector. The other RX queues are mapped to 1063 * the other (N - 2) interrupt vectors. 1064 */ 1065 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1066 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1067 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1068 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1069 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1070 } 1071 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1072 1073 val = MSIX_FH_INT_CAUSES_Q(0); 1074 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1075 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1076 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1077 1078 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1079 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1080 } 1081 1082 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1083 { 1084 struct iwl_trans *trans = trans_pcie->trans; 1085 1086 if (!trans_pcie->msix_enabled) { 1087 if (trans->cfg->mq_rx_supported && 1088 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1089 iwl_write_prph(trans, UREG_CHICK, 1090 UREG_CHICK_MSI_ENABLE); 1091 return; 1092 } 1093 /* 1094 * The IVAR table needs to be configured again after reset, 1095 * but if the device is disabled, we can't write to 1096 * prph. 1097 */ 1098 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1099 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1100 1101 /* 1102 * Each cause from the causes list above and the RX causes is 1103 * represented as a byte in the IVAR table. The first nibble 1104 * represents the bound interrupt vector of the cause, the second 1105 * represents no auto clear for this cause. This will be set if its 1106 * interrupt vector is bound to serve other causes. 1107 */ 1108 iwl_pcie_map_rx_causes(trans); 1109 1110 iwl_pcie_map_non_rx_causes(trans); 1111 } 1112 1113 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1114 { 1115 struct iwl_trans *trans = trans_pcie->trans; 1116 1117 iwl_pcie_conf_msix_hw(trans_pcie); 1118 1119 if (!trans_pcie->msix_enabled) 1120 return; 1121 1122 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1123 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1124 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1125 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1126 } 1127 1128 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1129 { 1130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1131 bool hw_rfkill, was_hw_rfkill; 1132 1133 lockdep_assert_held(&trans_pcie->mutex); 1134 1135 if (trans_pcie->is_down) 1136 return; 1137 1138 trans_pcie->is_down = true; 1139 1140 was_hw_rfkill = iwl_is_rfkill_set(trans); 1141 1142 /* tell the device to stop sending interrupts */ 1143 iwl_disable_interrupts(trans); 1144 1145 /* device going down, Stop using ICT table */ 1146 iwl_pcie_disable_ict(trans); 1147 1148 /* 1149 * If a HW restart happens during firmware loading, 1150 * then the firmware loading might call this function 1151 * and later it might be called again due to the 1152 * restart. So don't process again if the device is 1153 * already dead. 1154 */ 1155 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1156 IWL_DEBUG_INFO(trans, 1157 "DEVICE_ENABLED bit was set and is now cleared\n"); 1158 iwl_pcie_tx_stop(trans); 1159 iwl_pcie_rx_stop(trans); 1160 1161 /* Power-down device's busmaster DMA clocks */ 1162 if (!trans->cfg->apmg_not_supported) { 1163 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1164 APMG_CLK_VAL_DMA_CLK_RQT); 1165 udelay(5); 1166 } 1167 } 1168 1169 /* Make sure (redundant) we've released our request to stay awake */ 1170 iwl_clear_bit(trans, CSR_GP_CNTRL, 1171 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1172 1173 /* Stop the device, and put it in low power state */ 1174 iwl_pcie_apm_stop(trans, false); 1175 1176 /* stop and reset the on-board processor */ 1177 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1178 usleep_range(1000, 2000); 1179 1180 /* 1181 * Upon stop, the IVAR table gets erased, so msi-x won't 1182 * work. This causes a bug in RF-KILL flows, since the interrupt 1183 * that enables radio won't fire on the correct irq, and the 1184 * driver won't be able to handle the interrupt. 1185 * Configure the IVAR table again after reset. 1186 */ 1187 iwl_pcie_conf_msix_hw(trans_pcie); 1188 1189 /* 1190 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1191 * This is a bug in certain verions of the hardware. 1192 * Certain devices also keep sending HW RF kill interrupt all 1193 * the time, unless the interrupt is ACKed even if the interrupt 1194 * should be masked. Re-ACK all the interrupts here. 1195 */ 1196 iwl_disable_interrupts(trans); 1197 1198 /* clear all status bits */ 1199 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1200 clear_bit(STATUS_INT_ENABLED, &trans->status); 1201 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1202 clear_bit(STATUS_RFKILL, &trans->status); 1203 1204 /* 1205 * Even if we stop the HW, we still want the RF kill 1206 * interrupt 1207 */ 1208 iwl_enable_rfkill_int(trans); 1209 1210 /* 1211 * Check again since the RF kill state may have changed while 1212 * all the interrupts were disabled, in this case we couldn't 1213 * receive the RF kill interrupt and update the state in the 1214 * op_mode. 1215 * Don't call the op_mode if the rkfill state hasn't changed. 1216 * This allows the op_mode to call stop_device from the rfkill 1217 * notification without endless recursion. Under very rare 1218 * circumstances, we might have a small recursion if the rfkill 1219 * state changed exactly now while we were called from stop_device. 1220 * This is very unlikely but can happen and is supported. 1221 */ 1222 hw_rfkill = iwl_is_rfkill_set(trans); 1223 if (hw_rfkill) 1224 set_bit(STATUS_RFKILL, &trans->status); 1225 else 1226 clear_bit(STATUS_RFKILL, &trans->status); 1227 if (hw_rfkill != was_hw_rfkill) 1228 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1229 1230 /* re-take ownership to prevent other users from stealing the device */ 1231 iwl_pcie_prepare_card_hw(trans); 1232 } 1233 1234 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1235 { 1236 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237 1238 if (trans_pcie->msix_enabled) { 1239 int i; 1240 1241 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1242 synchronize_irq(trans_pcie->msix_entries[i].vector); 1243 } else { 1244 synchronize_irq(trans_pcie->pci_dev->irq); 1245 } 1246 } 1247 1248 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1249 const struct fw_img *fw, bool run_in_rfkill) 1250 { 1251 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1252 bool hw_rfkill; 1253 int ret; 1254 1255 /* This may fail if AMT took ownership of the device */ 1256 if (iwl_pcie_prepare_card_hw(trans)) { 1257 IWL_WARN(trans, "Exit HW not ready\n"); 1258 ret = -EIO; 1259 goto out; 1260 } 1261 1262 iwl_enable_rfkill_int(trans); 1263 1264 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1265 1266 /* 1267 * We enabled the RF-Kill interrupt and the handler may very 1268 * well be running. Disable the interrupts to make sure no other 1269 * interrupt can be fired. 1270 */ 1271 iwl_disable_interrupts(trans); 1272 1273 /* Make sure it finished running */ 1274 iwl_pcie_synchronize_irqs(trans); 1275 1276 mutex_lock(&trans_pcie->mutex); 1277 1278 /* If platform's RF_KILL switch is NOT set to KILL */ 1279 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1280 if (hw_rfkill && !run_in_rfkill) { 1281 ret = -ERFKILL; 1282 goto out; 1283 } 1284 1285 /* Someone called stop_device, don't try to start_fw */ 1286 if (trans_pcie->is_down) { 1287 IWL_WARN(trans, 1288 "Can't start_fw since the HW hasn't been started\n"); 1289 ret = -EIO; 1290 goto out; 1291 } 1292 1293 /* make sure rfkill handshake bits are cleared */ 1294 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1295 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1296 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1297 1298 /* clear (again), then enable host interrupts */ 1299 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1300 1301 ret = iwl_pcie_nic_init(trans); 1302 if (ret) { 1303 IWL_ERR(trans, "Unable to init nic\n"); 1304 goto out; 1305 } 1306 1307 /* 1308 * Now, we load the firmware and don't want to be interrupted, even 1309 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1310 * FH_TX interrupt which is needed to load the firmware). If the 1311 * RF-Kill switch is toggled, we will find out after having loaded 1312 * the firmware and return the proper value to the caller. 1313 */ 1314 iwl_enable_fw_load_int(trans); 1315 1316 /* really make sure rfkill handshake bits are cleared */ 1317 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1318 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1319 1320 /* Load the given image to the HW */ 1321 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1322 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1323 else 1324 ret = iwl_pcie_load_given_ucode(trans, fw); 1325 1326 /* re-check RF-Kill state since we may have missed the interrupt */ 1327 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1328 if (hw_rfkill && !run_in_rfkill) 1329 ret = -ERFKILL; 1330 1331 out: 1332 mutex_unlock(&trans_pcie->mutex); 1333 return ret; 1334 } 1335 1336 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1337 { 1338 iwl_pcie_reset_ict(trans); 1339 iwl_pcie_tx_start(trans, scd_addr); 1340 } 1341 1342 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1343 { 1344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1345 1346 mutex_lock(&trans_pcie->mutex); 1347 _iwl_trans_pcie_stop_device(trans, low_power); 1348 mutex_unlock(&trans_pcie->mutex); 1349 } 1350 1351 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1352 { 1353 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1354 IWL_TRANS_GET_PCIE_TRANS(trans); 1355 1356 lockdep_assert_held(&trans_pcie->mutex); 1357 1358 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1359 if (trans->cfg->gen2) 1360 _iwl_trans_pcie_gen2_stop_device(trans, true); 1361 else 1362 _iwl_trans_pcie_stop_device(trans, true); 1363 } 1364 } 1365 1366 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1367 bool reset) 1368 { 1369 if (!reset) { 1370 /* Enable persistence mode to avoid reset */ 1371 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1372 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1373 } 1374 1375 iwl_disable_interrupts(trans); 1376 1377 /* 1378 * in testing mode, the host stays awake and the 1379 * hardware won't be reset (not even partially) 1380 */ 1381 if (test) 1382 return; 1383 1384 iwl_pcie_disable_ict(trans); 1385 1386 iwl_pcie_synchronize_irqs(trans); 1387 1388 iwl_clear_bit(trans, CSR_GP_CNTRL, 1389 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1390 iwl_clear_bit(trans, CSR_GP_CNTRL, 1391 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1392 1393 iwl_pcie_enable_rx_wake(trans, false); 1394 1395 if (reset) { 1396 /* 1397 * reset TX queues -- some of their registers reset during S3 1398 * so if we don't reset everything here the D3 image would try 1399 * to execute some invalid memory upon resume 1400 */ 1401 iwl_trans_pcie_tx_reset(trans); 1402 } 1403 1404 iwl_pcie_set_pwr(trans, true); 1405 } 1406 1407 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1408 enum iwl_d3_status *status, 1409 bool test, bool reset) 1410 { 1411 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1412 u32 val; 1413 int ret; 1414 1415 if (test) { 1416 iwl_enable_interrupts(trans); 1417 *status = IWL_D3_STATUS_ALIVE; 1418 return 0; 1419 } 1420 1421 iwl_pcie_enable_rx_wake(trans, true); 1422 1423 /* 1424 * Reconfigure IVAR table in case of MSIX or reset ict table in 1425 * MSI mode since HW reset erased it. 1426 * Also enables interrupts - none will happen as 1427 * the device doesn't know we're waking it up, only when 1428 * the opmode actually tells it after this call. 1429 */ 1430 iwl_pcie_conf_msix_hw(trans_pcie); 1431 if (!trans_pcie->msix_enabled) 1432 iwl_pcie_reset_ict(trans); 1433 iwl_enable_interrupts(trans); 1434 1435 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1436 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1437 1438 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1439 udelay(2); 1440 1441 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1442 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1443 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1444 25000); 1445 if (ret < 0) { 1446 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1447 return ret; 1448 } 1449 1450 iwl_pcie_set_pwr(trans, false); 1451 1452 if (!reset) { 1453 iwl_clear_bit(trans, CSR_GP_CNTRL, 1454 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1455 } else { 1456 iwl_trans_pcie_tx_reset(trans); 1457 1458 ret = iwl_pcie_rx_init(trans); 1459 if (ret) { 1460 IWL_ERR(trans, 1461 "Failed to resume the device (RX reset)\n"); 1462 return ret; 1463 } 1464 } 1465 1466 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1467 iwl_read_prph(trans, WFPM_GP2)); 1468 1469 val = iwl_read32(trans, CSR_RESET); 1470 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1471 *status = IWL_D3_STATUS_RESET; 1472 else 1473 *status = IWL_D3_STATUS_ALIVE; 1474 1475 return 0; 1476 } 1477 1478 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1479 struct iwl_trans *trans) 1480 { 1481 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1482 int max_irqs, num_irqs, i, ret, nr_online_cpus; 1483 u16 pci_cmd; 1484 1485 if (!trans->cfg->mq_rx_supported) 1486 goto enable_msi; 1487 1488 nr_online_cpus = num_online_cpus(); 1489 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 1490 for (i = 0; i < max_irqs; i++) 1491 trans_pcie->msix_entries[i].entry = i; 1492 1493 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1494 MSIX_MIN_INTERRUPT_VECTORS, 1495 max_irqs); 1496 if (num_irqs < 0) { 1497 IWL_DEBUG_INFO(trans, 1498 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1499 num_irqs); 1500 goto enable_msi; 1501 } 1502 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1503 1504 IWL_DEBUG_INFO(trans, 1505 "MSI-X enabled. %d interrupt vectors were allocated\n", 1506 num_irqs); 1507 1508 /* 1509 * In case the OS provides fewer interrupts than requested, different 1510 * causes will share the same interrupt vector as follows: 1511 * One interrupt less: non rx causes shared with FBQ. 1512 * Two interrupts less: non rx causes shared with FBQ and RSS. 1513 * More than two interrupts: we will use fewer RSS queues. 1514 */ 1515 if (num_irqs <= nr_online_cpus) { 1516 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1517 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1518 IWL_SHARED_IRQ_FIRST_RSS; 1519 } else if (num_irqs == nr_online_cpus + 1) { 1520 trans_pcie->trans->num_rx_queues = num_irqs; 1521 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1522 } else { 1523 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1524 } 1525 1526 trans_pcie->alloc_vecs = num_irqs; 1527 trans_pcie->msix_enabled = true; 1528 return; 1529 1530 enable_msi: 1531 ret = pci_enable_msi(pdev); 1532 if (ret) { 1533 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1534 /* enable rfkill interrupt: hw bug w/a */ 1535 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1536 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1537 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1538 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1539 } 1540 } 1541 } 1542 1543 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1544 { 1545 int iter_rx_q, i, ret, cpu, offset; 1546 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1547 1548 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1549 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1550 offset = 1 + i; 1551 for (; i < iter_rx_q ; i++) { 1552 /* 1553 * Get the cpu prior to the place to search 1554 * (i.e. return will be > i - 1). 1555 */ 1556 cpu = cpumask_next(i - offset, cpu_online_mask); 1557 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1558 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1559 &trans_pcie->affinity_mask[i]); 1560 if (ret) 1561 IWL_ERR(trans_pcie->trans, 1562 "Failed to set affinity mask for IRQ %d\n", 1563 i); 1564 } 1565 } 1566 1567 static const char *queue_name(struct device *dev, 1568 struct iwl_trans_pcie *trans_p, int i) 1569 { 1570 if (trans_p->shared_vec_mask) { 1571 int vec = trans_p->shared_vec_mask & 1572 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1573 1574 if (i == 0) 1575 return DRV_NAME ": shared IRQ"; 1576 1577 return devm_kasprintf(dev, GFP_KERNEL, 1578 DRV_NAME ": queue %d", i + vec); 1579 } 1580 if (i == 0) 1581 return DRV_NAME ": default queue"; 1582 1583 if (i == trans_p->alloc_vecs - 1) 1584 return DRV_NAME ": exception"; 1585 1586 return devm_kasprintf(dev, GFP_KERNEL, 1587 DRV_NAME ": queue %d", i); 1588 } 1589 1590 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1591 struct iwl_trans_pcie *trans_pcie) 1592 { 1593 int i; 1594 1595 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1596 int ret; 1597 struct msix_entry *msix_entry; 1598 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1599 1600 if (!qname) 1601 return -ENOMEM; 1602 1603 msix_entry = &trans_pcie->msix_entries[i]; 1604 ret = devm_request_threaded_irq(&pdev->dev, 1605 msix_entry->vector, 1606 iwl_pcie_msix_isr, 1607 (i == trans_pcie->def_irq) ? 1608 iwl_pcie_irq_msix_handler : 1609 iwl_pcie_irq_rx_msix_handler, 1610 IRQF_SHARED, 1611 qname, 1612 msix_entry); 1613 if (ret) { 1614 IWL_ERR(trans_pcie->trans, 1615 "Error allocating IRQ %d\n", i); 1616 1617 return ret; 1618 } 1619 } 1620 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1621 1622 return 0; 1623 } 1624 1625 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1626 { 1627 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1628 int err; 1629 1630 lockdep_assert_held(&trans_pcie->mutex); 1631 1632 err = iwl_pcie_prepare_card_hw(trans); 1633 if (err) { 1634 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1635 return err; 1636 } 1637 1638 /* Reset the entire device */ 1639 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1640 usleep_range(1000, 2000); 1641 1642 iwl_pcie_apm_init(trans); 1643 1644 iwl_pcie_init_msix(trans_pcie); 1645 1646 /* From now on, the op_mode will be kept updated about RF kill state */ 1647 iwl_enable_rfkill_int(trans); 1648 1649 /* Set is_down to false here so that...*/ 1650 trans_pcie->is_down = false; 1651 1652 /* ...rfkill can call stop_device and set it false if needed */ 1653 iwl_trans_check_hw_rf_kill(trans); 1654 1655 /* Make sure we sync here, because we'll need full access later */ 1656 if (low_power) 1657 pm_runtime_resume(trans->dev); 1658 1659 return 0; 1660 } 1661 1662 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1663 { 1664 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1665 int ret; 1666 1667 mutex_lock(&trans_pcie->mutex); 1668 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1669 mutex_unlock(&trans_pcie->mutex); 1670 1671 return ret; 1672 } 1673 1674 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1675 { 1676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1677 1678 mutex_lock(&trans_pcie->mutex); 1679 1680 /* disable interrupts - don't enable HW RF kill interrupt */ 1681 iwl_disable_interrupts(trans); 1682 1683 iwl_pcie_apm_stop(trans, true); 1684 1685 iwl_disable_interrupts(trans); 1686 1687 iwl_pcie_disable_ict(trans); 1688 1689 mutex_unlock(&trans_pcie->mutex); 1690 1691 iwl_pcie_synchronize_irqs(trans); 1692 } 1693 1694 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1695 { 1696 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1697 } 1698 1699 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1700 { 1701 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1702 } 1703 1704 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1705 { 1706 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1707 } 1708 1709 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1710 { 1711 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1712 ((reg & 0x000FFFFF) | (3 << 24))); 1713 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1714 } 1715 1716 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1717 u32 val) 1718 { 1719 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1720 ((addr & 0x000FFFFF) | (3 << 24))); 1721 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1722 } 1723 1724 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1725 const struct iwl_trans_config *trans_cfg) 1726 { 1727 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1728 1729 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1730 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1731 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1732 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1733 trans_pcie->n_no_reclaim_cmds = 0; 1734 else 1735 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1736 if (trans_pcie->n_no_reclaim_cmds) 1737 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1738 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1739 1740 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1741 trans_pcie->rx_page_order = 1742 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1743 1744 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1745 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1746 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1747 1748 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1749 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1750 1751 trans->command_groups = trans_cfg->command_groups; 1752 trans->command_groups_size = trans_cfg->command_groups_size; 1753 1754 /* Initialize NAPI here - it should be before registering to mac80211 1755 * in the opmode but after the HW struct is allocated. 1756 * As this function may be called again in some corner cases don't 1757 * do anything if NAPI was already initialized. 1758 */ 1759 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1760 init_dummy_netdev(&trans_pcie->napi_dev); 1761 } 1762 1763 void iwl_trans_pcie_free(struct iwl_trans *trans) 1764 { 1765 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1766 int i; 1767 1768 iwl_pcie_synchronize_irqs(trans); 1769 1770 if (trans->cfg->gen2) 1771 iwl_pcie_gen2_tx_free(trans); 1772 else 1773 iwl_pcie_tx_free(trans); 1774 iwl_pcie_rx_free(trans); 1775 1776 if (trans_pcie->msix_enabled) { 1777 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1778 irq_set_affinity_hint( 1779 trans_pcie->msix_entries[i].vector, 1780 NULL); 1781 } 1782 1783 trans_pcie->msix_enabled = false; 1784 } else { 1785 iwl_pcie_free_ict(trans); 1786 } 1787 1788 iwl_pcie_free_fw_monitor(trans); 1789 1790 for_each_possible_cpu(i) { 1791 struct iwl_tso_hdr_page *p = 1792 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1793 1794 if (p->page) 1795 __free_page(p->page); 1796 } 1797 1798 free_percpu(trans_pcie->tso_hdr_page); 1799 mutex_destroy(&trans_pcie->mutex); 1800 iwl_trans_free(trans); 1801 } 1802 1803 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1804 { 1805 if (state) 1806 set_bit(STATUS_TPOWER_PMI, &trans->status); 1807 else 1808 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1809 } 1810 1811 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1812 unsigned long *flags) 1813 { 1814 int ret; 1815 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1816 1817 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1818 1819 if (trans_pcie->cmd_hold_nic_awake) 1820 goto out; 1821 1822 /* this bit wakes up the NIC */ 1823 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1824 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1825 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1826 udelay(2); 1827 1828 /* 1829 * These bits say the device is running, and should keep running for 1830 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1831 * but they do not indicate that embedded SRAM is restored yet; 1832 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1833 * to/from host DRAM when sleeping/waking for power-saving. 1834 * Each direction takes approximately 1/4 millisecond; with this 1835 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1836 * series of register accesses are expected (e.g. reading Event Log), 1837 * to keep device from sleeping. 1838 * 1839 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1840 * SRAM is okay/restored. We don't check that here because this call 1841 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1842 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1843 * 1844 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1845 * and do not save/restore SRAM when power cycling. 1846 */ 1847 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1848 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1849 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1850 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1851 if (unlikely(ret < 0)) { 1852 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1853 WARN_ONCE(1, 1854 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1855 iwl_read32(trans, CSR_GP_CNTRL)); 1856 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1857 return false; 1858 } 1859 1860 out: 1861 /* 1862 * Fool sparse by faking we release the lock - sparse will 1863 * track nic_access anyway. 1864 */ 1865 __release(&trans_pcie->reg_lock); 1866 return true; 1867 } 1868 1869 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1870 unsigned long *flags) 1871 { 1872 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1873 1874 lockdep_assert_held(&trans_pcie->reg_lock); 1875 1876 /* 1877 * Fool sparse by faking we acquiring the lock - sparse will 1878 * track nic_access anyway. 1879 */ 1880 __acquire(&trans_pcie->reg_lock); 1881 1882 if (trans_pcie->cmd_hold_nic_awake) 1883 goto out; 1884 1885 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1886 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1887 /* 1888 * Above we read the CSR_GP_CNTRL register, which will flush 1889 * any previous writes, but we need the write that clears the 1890 * MAC_ACCESS_REQ bit to be performed before any other writes 1891 * scheduled on different CPUs (after we drop reg_lock). 1892 */ 1893 mmiowb(); 1894 out: 1895 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1896 } 1897 1898 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1899 void *buf, int dwords) 1900 { 1901 unsigned long flags; 1902 int offs, ret = 0; 1903 u32 *vals = buf; 1904 1905 if (iwl_trans_grab_nic_access(trans, &flags)) { 1906 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1907 for (offs = 0; offs < dwords; offs++) 1908 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1909 iwl_trans_release_nic_access(trans, &flags); 1910 } else { 1911 ret = -EBUSY; 1912 } 1913 return ret; 1914 } 1915 1916 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1917 const void *buf, int dwords) 1918 { 1919 unsigned long flags; 1920 int offs, ret = 0; 1921 const u32 *vals = buf; 1922 1923 if (iwl_trans_grab_nic_access(trans, &flags)) { 1924 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1925 for (offs = 0; offs < dwords; offs++) 1926 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1927 vals ? vals[offs] : 0); 1928 iwl_trans_release_nic_access(trans, &flags); 1929 } else { 1930 ret = -EBUSY; 1931 } 1932 return ret; 1933 } 1934 1935 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1936 unsigned long txqs, 1937 bool freeze) 1938 { 1939 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1940 int queue; 1941 1942 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1943 struct iwl_txq *txq = trans_pcie->txq[queue]; 1944 unsigned long now; 1945 1946 spin_lock_bh(&txq->lock); 1947 1948 now = jiffies; 1949 1950 if (txq->frozen == freeze) 1951 goto next_queue; 1952 1953 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1954 freeze ? "Freezing" : "Waking", queue); 1955 1956 txq->frozen = freeze; 1957 1958 if (txq->read_ptr == txq->write_ptr) 1959 goto next_queue; 1960 1961 if (freeze) { 1962 if (unlikely(time_after(now, 1963 txq->stuck_timer.expires))) { 1964 /* 1965 * The timer should have fired, maybe it is 1966 * spinning right now on the lock. 1967 */ 1968 goto next_queue; 1969 } 1970 /* remember how long until the timer fires */ 1971 txq->frozen_expiry_remainder = 1972 txq->stuck_timer.expires - now; 1973 del_timer(&txq->stuck_timer); 1974 goto next_queue; 1975 } 1976 1977 /* 1978 * Wake a non-empty queue -> arm timer with the 1979 * remainder before it froze 1980 */ 1981 mod_timer(&txq->stuck_timer, 1982 now + txq->frozen_expiry_remainder); 1983 1984 next_queue: 1985 spin_unlock_bh(&txq->lock); 1986 } 1987 } 1988 1989 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 1990 { 1991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1992 int i; 1993 1994 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 1995 struct iwl_txq *txq = trans_pcie->txq[i]; 1996 1997 if (i == trans_pcie->cmd_queue) 1998 continue; 1999 2000 spin_lock_bh(&txq->lock); 2001 2002 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2003 txq->block--; 2004 if (!txq->block) { 2005 iwl_write32(trans, HBUS_TARG_WRPTR, 2006 txq->write_ptr | (i << 8)); 2007 } 2008 } else if (block) { 2009 txq->block++; 2010 } 2011 2012 spin_unlock_bh(&txq->lock); 2013 } 2014 } 2015 2016 #define IWL_FLUSH_WAIT_MS 2000 2017 2018 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2019 { 2020 u32 txq_id = txq->id; 2021 u32 status; 2022 bool active; 2023 u8 fifo; 2024 2025 if (trans->cfg->use_tfh) { 2026 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2027 txq->read_ptr, txq->write_ptr); 2028 /* TODO: access new SCD registers and dump them */ 2029 return; 2030 } 2031 2032 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2033 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2034 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2035 2036 IWL_ERR(trans, 2037 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2038 txq_id, active ? "" : "in", fifo, 2039 jiffies_to_msecs(txq->wd_timeout), 2040 txq->read_ptr, txq->write_ptr, 2041 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2042 (TFD_QUEUE_SIZE_MAX - 1), 2043 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2044 (TFD_QUEUE_SIZE_MAX - 1), 2045 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2046 } 2047 2048 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2049 { 2050 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2051 struct iwl_txq *txq; 2052 unsigned long now = jiffies; 2053 u8 wr_ptr; 2054 2055 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2056 return -EINVAL; 2057 2058 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2059 txq = trans_pcie->txq[txq_idx]; 2060 wr_ptr = ACCESS_ONCE(txq->write_ptr); 2061 2062 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) && 2063 !time_after(jiffies, 2064 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2065 u8 write_ptr = ACCESS_ONCE(txq->write_ptr); 2066 2067 if (WARN_ONCE(wr_ptr != write_ptr, 2068 "WR pointer moved while flushing %d -> %d\n", 2069 wr_ptr, write_ptr)) 2070 return -ETIMEDOUT; 2071 usleep_range(1000, 2000); 2072 } 2073 2074 if (txq->read_ptr != txq->write_ptr) { 2075 IWL_ERR(trans, 2076 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2077 iwl_trans_pcie_log_scd_error(trans, txq); 2078 return -ETIMEDOUT; 2079 } 2080 2081 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2082 2083 return 0; 2084 } 2085 2086 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2087 { 2088 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2089 int cnt; 2090 int ret = 0; 2091 2092 /* waiting for all the tx frames complete might take a while */ 2093 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2094 2095 if (cnt == trans_pcie->cmd_queue) 2096 continue; 2097 if (!test_bit(cnt, trans_pcie->queue_used)) 2098 continue; 2099 if (!(BIT(cnt) & txq_bm)) 2100 continue; 2101 2102 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2103 if (ret) 2104 break; 2105 } 2106 2107 return ret; 2108 } 2109 2110 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2111 u32 mask, u32 value) 2112 { 2113 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2114 unsigned long flags; 2115 2116 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2117 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2118 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2119 } 2120 2121 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2122 { 2123 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2124 2125 if (iwlwifi_mod_params.d0i3_disable) 2126 return; 2127 2128 pm_runtime_get(&trans_pcie->pci_dev->dev); 2129 2130 #ifdef CONFIG_PM 2131 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2132 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2133 #endif /* CONFIG_PM */ 2134 } 2135 2136 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2137 { 2138 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2139 2140 if (iwlwifi_mod_params.d0i3_disable) 2141 return; 2142 2143 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2144 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2145 2146 #ifdef CONFIG_PM 2147 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2148 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2149 #endif /* CONFIG_PM */ 2150 } 2151 2152 static const char *get_csr_string(int cmd) 2153 { 2154 #define IWL_CMD(x) case x: return #x 2155 switch (cmd) { 2156 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2157 IWL_CMD(CSR_INT_COALESCING); 2158 IWL_CMD(CSR_INT); 2159 IWL_CMD(CSR_INT_MASK); 2160 IWL_CMD(CSR_FH_INT_STATUS); 2161 IWL_CMD(CSR_GPIO_IN); 2162 IWL_CMD(CSR_RESET); 2163 IWL_CMD(CSR_GP_CNTRL); 2164 IWL_CMD(CSR_HW_REV); 2165 IWL_CMD(CSR_EEPROM_REG); 2166 IWL_CMD(CSR_EEPROM_GP); 2167 IWL_CMD(CSR_OTP_GP_REG); 2168 IWL_CMD(CSR_GIO_REG); 2169 IWL_CMD(CSR_GP_UCODE_REG); 2170 IWL_CMD(CSR_GP_DRIVER_REG); 2171 IWL_CMD(CSR_UCODE_DRV_GP1); 2172 IWL_CMD(CSR_UCODE_DRV_GP2); 2173 IWL_CMD(CSR_LED_REG); 2174 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2175 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2176 IWL_CMD(CSR_ANA_PLL_CFG); 2177 IWL_CMD(CSR_HW_REV_WA_REG); 2178 IWL_CMD(CSR_MONITOR_STATUS_REG); 2179 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2180 default: 2181 return "UNKNOWN"; 2182 } 2183 #undef IWL_CMD 2184 } 2185 2186 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2187 { 2188 int i; 2189 static const u32 csr_tbl[] = { 2190 CSR_HW_IF_CONFIG_REG, 2191 CSR_INT_COALESCING, 2192 CSR_INT, 2193 CSR_INT_MASK, 2194 CSR_FH_INT_STATUS, 2195 CSR_GPIO_IN, 2196 CSR_RESET, 2197 CSR_GP_CNTRL, 2198 CSR_HW_REV, 2199 CSR_EEPROM_REG, 2200 CSR_EEPROM_GP, 2201 CSR_OTP_GP_REG, 2202 CSR_GIO_REG, 2203 CSR_GP_UCODE_REG, 2204 CSR_GP_DRIVER_REG, 2205 CSR_UCODE_DRV_GP1, 2206 CSR_UCODE_DRV_GP2, 2207 CSR_LED_REG, 2208 CSR_DRAM_INT_TBL_REG, 2209 CSR_GIO_CHICKEN_BITS, 2210 CSR_ANA_PLL_CFG, 2211 CSR_MONITOR_STATUS_REG, 2212 CSR_HW_REV_WA_REG, 2213 CSR_DBG_HPET_MEM_REG 2214 }; 2215 IWL_ERR(trans, "CSR values:\n"); 2216 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2217 "CSR_INT_PERIODIC_REG)\n"); 2218 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2219 IWL_ERR(trans, " %25s: 0X%08x\n", 2220 get_csr_string(csr_tbl[i]), 2221 iwl_read32(trans, csr_tbl[i])); 2222 } 2223 } 2224 2225 #ifdef CONFIG_IWLWIFI_DEBUGFS 2226 /* create and remove of files */ 2227 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2228 if (!debugfs_create_file(#name, mode, parent, trans, \ 2229 &iwl_dbgfs_##name##_ops)) \ 2230 goto err; \ 2231 } while (0) 2232 2233 /* file operation */ 2234 #define DEBUGFS_READ_FILE_OPS(name) \ 2235 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2236 .read = iwl_dbgfs_##name##_read, \ 2237 .open = simple_open, \ 2238 .llseek = generic_file_llseek, \ 2239 }; 2240 2241 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2242 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2243 .write = iwl_dbgfs_##name##_write, \ 2244 .open = simple_open, \ 2245 .llseek = generic_file_llseek, \ 2246 }; 2247 2248 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2249 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2250 .write = iwl_dbgfs_##name##_write, \ 2251 .read = iwl_dbgfs_##name##_read, \ 2252 .open = simple_open, \ 2253 .llseek = generic_file_llseek, \ 2254 }; 2255 2256 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2257 char __user *user_buf, 2258 size_t count, loff_t *ppos) 2259 { 2260 struct iwl_trans *trans = file->private_data; 2261 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2262 struct iwl_txq *txq; 2263 char *buf; 2264 int pos = 0; 2265 int cnt; 2266 int ret; 2267 size_t bufsz; 2268 2269 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2270 2271 if (!trans_pcie->txq_memory) 2272 return -EAGAIN; 2273 2274 buf = kzalloc(bufsz, GFP_KERNEL); 2275 if (!buf) 2276 return -ENOMEM; 2277 2278 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2279 txq = trans_pcie->txq[cnt]; 2280 pos += scnprintf(buf + pos, bufsz - pos, 2281 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2282 cnt, txq->read_ptr, txq->write_ptr, 2283 !!test_bit(cnt, trans_pcie->queue_used), 2284 !!test_bit(cnt, trans_pcie->queue_stopped), 2285 txq->need_update, txq->frozen, 2286 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2287 } 2288 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2289 kfree(buf); 2290 return ret; 2291 } 2292 2293 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2294 char __user *user_buf, 2295 size_t count, loff_t *ppos) 2296 { 2297 struct iwl_trans *trans = file->private_data; 2298 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2299 char *buf; 2300 int pos = 0, i, ret; 2301 size_t bufsz = sizeof(buf); 2302 2303 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2304 2305 if (!trans_pcie->rxq) 2306 return -EAGAIN; 2307 2308 buf = kzalloc(bufsz, GFP_KERNEL); 2309 if (!buf) 2310 return -ENOMEM; 2311 2312 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2313 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2314 2315 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2316 i); 2317 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2318 rxq->read); 2319 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2320 rxq->write); 2321 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2322 rxq->write_actual); 2323 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2324 rxq->need_update); 2325 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2326 rxq->free_count); 2327 if (rxq->rb_stts) { 2328 pos += scnprintf(buf + pos, bufsz - pos, 2329 "\tclosed_rb_num: %u\n", 2330 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2331 0x0FFF); 2332 } else { 2333 pos += scnprintf(buf + pos, bufsz - pos, 2334 "\tclosed_rb_num: Not Allocated\n"); 2335 } 2336 } 2337 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2338 kfree(buf); 2339 2340 return ret; 2341 } 2342 2343 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2344 char __user *user_buf, 2345 size_t count, loff_t *ppos) 2346 { 2347 struct iwl_trans *trans = file->private_data; 2348 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2349 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2350 2351 int pos = 0; 2352 char *buf; 2353 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2354 ssize_t ret; 2355 2356 buf = kzalloc(bufsz, GFP_KERNEL); 2357 if (!buf) 2358 return -ENOMEM; 2359 2360 pos += scnprintf(buf + pos, bufsz - pos, 2361 "Interrupt Statistics Report:\n"); 2362 2363 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2364 isr_stats->hw); 2365 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2366 isr_stats->sw); 2367 if (isr_stats->sw || isr_stats->hw) { 2368 pos += scnprintf(buf + pos, bufsz - pos, 2369 "\tLast Restarting Code: 0x%X\n", 2370 isr_stats->err_code); 2371 } 2372 #ifdef CONFIG_IWLWIFI_DEBUG 2373 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2374 isr_stats->sch); 2375 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2376 isr_stats->alive); 2377 #endif 2378 pos += scnprintf(buf + pos, bufsz - pos, 2379 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2380 2381 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2382 isr_stats->ctkill); 2383 2384 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2385 isr_stats->wakeup); 2386 2387 pos += scnprintf(buf + pos, bufsz - pos, 2388 "Rx command responses:\t\t %u\n", isr_stats->rx); 2389 2390 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2391 isr_stats->tx); 2392 2393 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2394 isr_stats->unhandled); 2395 2396 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2397 kfree(buf); 2398 return ret; 2399 } 2400 2401 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2402 const char __user *user_buf, 2403 size_t count, loff_t *ppos) 2404 { 2405 struct iwl_trans *trans = file->private_data; 2406 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2407 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2408 2409 char buf[8]; 2410 int buf_size; 2411 u32 reset_flag; 2412 2413 memset(buf, 0, sizeof(buf)); 2414 buf_size = min(count, sizeof(buf) - 1); 2415 if (copy_from_user(buf, user_buf, buf_size)) 2416 return -EFAULT; 2417 if (sscanf(buf, "%x", &reset_flag) != 1) 2418 return -EFAULT; 2419 if (reset_flag == 0) 2420 memset(isr_stats, 0, sizeof(*isr_stats)); 2421 2422 return count; 2423 } 2424 2425 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2426 const char __user *user_buf, 2427 size_t count, loff_t *ppos) 2428 { 2429 struct iwl_trans *trans = file->private_data; 2430 char buf[8]; 2431 int buf_size; 2432 int csr; 2433 2434 memset(buf, 0, sizeof(buf)); 2435 buf_size = min(count, sizeof(buf) - 1); 2436 if (copy_from_user(buf, user_buf, buf_size)) 2437 return -EFAULT; 2438 if (sscanf(buf, "%d", &csr) != 1) 2439 return -EFAULT; 2440 2441 iwl_pcie_dump_csr(trans); 2442 2443 return count; 2444 } 2445 2446 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2447 char __user *user_buf, 2448 size_t count, loff_t *ppos) 2449 { 2450 struct iwl_trans *trans = file->private_data; 2451 char *buf = NULL; 2452 ssize_t ret; 2453 2454 ret = iwl_dump_fh(trans, &buf); 2455 if (ret < 0) 2456 return ret; 2457 if (!buf) 2458 return -EINVAL; 2459 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2460 kfree(buf); 2461 return ret; 2462 } 2463 2464 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2465 DEBUGFS_READ_FILE_OPS(fh_reg); 2466 DEBUGFS_READ_FILE_OPS(rx_queue); 2467 DEBUGFS_READ_FILE_OPS(tx_queue); 2468 DEBUGFS_WRITE_FILE_OPS(csr); 2469 2470 /* Create the debugfs files and directories */ 2471 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2472 { 2473 struct dentry *dir = trans->dbgfs_dir; 2474 2475 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2476 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2477 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2478 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2479 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2480 return 0; 2481 2482 err: 2483 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2484 return -ENOMEM; 2485 } 2486 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2487 2488 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2489 { 2490 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2491 u32 cmdlen = 0; 2492 int i; 2493 2494 for (i = 0; i < trans_pcie->max_tbs; i++) 2495 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2496 2497 return cmdlen; 2498 } 2499 2500 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2501 struct iwl_fw_error_dump_data **data, 2502 int allocated_rb_nums) 2503 { 2504 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2505 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2506 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2507 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2508 u32 i, r, j, rb_len = 0; 2509 2510 spin_lock(&rxq->lock); 2511 2512 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2513 2514 for (i = rxq->read, j = 0; 2515 i != r && j < allocated_rb_nums; 2516 i = (i + 1) & RX_QUEUE_MASK, j++) { 2517 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2518 struct iwl_fw_error_dump_rb *rb; 2519 2520 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2521 DMA_FROM_DEVICE); 2522 2523 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2524 2525 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2526 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2527 rb = (void *)(*data)->data; 2528 rb->index = cpu_to_le32(i); 2529 memcpy(rb->data, page_address(rxb->page), max_len); 2530 /* remap the page for the free benefit */ 2531 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2532 max_len, 2533 DMA_FROM_DEVICE); 2534 2535 *data = iwl_fw_error_next_data(*data); 2536 } 2537 2538 spin_unlock(&rxq->lock); 2539 2540 return rb_len; 2541 } 2542 #define IWL_CSR_TO_DUMP (0x250) 2543 2544 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2545 struct iwl_fw_error_dump_data **data) 2546 { 2547 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2548 __le32 *val; 2549 int i; 2550 2551 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2552 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2553 val = (void *)(*data)->data; 2554 2555 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2556 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2557 2558 *data = iwl_fw_error_next_data(*data); 2559 2560 return csr_len; 2561 } 2562 2563 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2564 struct iwl_fw_error_dump_data **data) 2565 { 2566 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2567 unsigned long flags; 2568 __le32 *val; 2569 int i; 2570 2571 if (!iwl_trans_grab_nic_access(trans, &flags)) 2572 return 0; 2573 2574 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2575 (*data)->len = cpu_to_le32(fh_regs_len); 2576 val = (void *)(*data)->data; 2577 2578 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2579 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2580 2581 iwl_trans_release_nic_access(trans, &flags); 2582 2583 *data = iwl_fw_error_next_data(*data); 2584 2585 return sizeof(**data) + fh_regs_len; 2586 } 2587 2588 static u32 2589 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2590 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2591 u32 monitor_len) 2592 { 2593 u32 buf_size_in_dwords = (monitor_len >> 2); 2594 u32 *buffer = (u32 *)fw_mon_data->data; 2595 unsigned long flags; 2596 u32 i; 2597 2598 if (!iwl_trans_grab_nic_access(trans, &flags)) 2599 return 0; 2600 2601 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2602 for (i = 0; i < buf_size_in_dwords; i++) 2603 buffer[i] = iwl_read_prph_no_grab(trans, 2604 MON_DMARB_RD_DATA_ADDR); 2605 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2606 2607 iwl_trans_release_nic_access(trans, &flags); 2608 2609 return monitor_len; 2610 } 2611 2612 static u32 2613 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2614 struct iwl_fw_error_dump_data **data, 2615 u32 monitor_len) 2616 { 2617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2618 u32 len = 0; 2619 2620 if ((trans_pcie->fw_mon_page && 2621 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2622 trans->dbg_dest_tlv) { 2623 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2624 u32 base, write_ptr, wrap_cnt; 2625 2626 /* If there was a dest TLV - use the values from there */ 2627 if (trans->dbg_dest_tlv) { 2628 write_ptr = 2629 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2630 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2631 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2632 } else { 2633 base = MON_BUFF_BASE_ADDR; 2634 write_ptr = MON_BUFF_WRPTR; 2635 wrap_cnt = MON_BUFF_CYCLE_CNT; 2636 } 2637 2638 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2639 fw_mon_data = (void *)(*data)->data; 2640 fw_mon_data->fw_mon_wr_ptr = 2641 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2642 fw_mon_data->fw_mon_cycle_cnt = 2643 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2644 fw_mon_data->fw_mon_base_ptr = 2645 cpu_to_le32(iwl_read_prph(trans, base)); 2646 2647 len += sizeof(**data) + sizeof(*fw_mon_data); 2648 if (trans_pcie->fw_mon_page) { 2649 /* 2650 * The firmware is now asserted, it won't write anything 2651 * to the buffer. CPU can take ownership to fetch the 2652 * data. The buffer will be handed back to the device 2653 * before the firmware will be restarted. 2654 */ 2655 dma_sync_single_for_cpu(trans->dev, 2656 trans_pcie->fw_mon_phys, 2657 trans_pcie->fw_mon_size, 2658 DMA_FROM_DEVICE); 2659 memcpy(fw_mon_data->data, 2660 page_address(trans_pcie->fw_mon_page), 2661 trans_pcie->fw_mon_size); 2662 2663 monitor_len = trans_pcie->fw_mon_size; 2664 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2665 /* 2666 * Update pointers to reflect actual values after 2667 * shifting 2668 */ 2669 base = iwl_read_prph(trans, base) << 2670 trans->dbg_dest_tlv->base_shift; 2671 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2672 monitor_len / sizeof(u32)); 2673 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2674 monitor_len = 2675 iwl_trans_pci_dump_marbh_monitor(trans, 2676 fw_mon_data, 2677 monitor_len); 2678 } else { 2679 /* Didn't match anything - output no monitor data */ 2680 monitor_len = 0; 2681 } 2682 2683 len += monitor_len; 2684 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2685 } 2686 2687 return len; 2688 } 2689 2690 static struct iwl_trans_dump_data 2691 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2692 const struct iwl_fw_dbg_trigger_tlv *trigger) 2693 { 2694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2695 struct iwl_fw_error_dump_data *data; 2696 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2697 struct iwl_fw_error_dump_txcmd *txcmd; 2698 struct iwl_trans_dump_data *dump_data; 2699 u32 len, num_rbs; 2700 u32 monitor_len; 2701 int i, ptr; 2702 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2703 !trans->cfg->mq_rx_supported; 2704 2705 /* transport dump header */ 2706 len = sizeof(*dump_data); 2707 2708 /* host commands */ 2709 len += sizeof(*data) + 2710 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2711 2712 /* FW monitor */ 2713 if (trans_pcie->fw_mon_page) { 2714 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2715 trans_pcie->fw_mon_size; 2716 monitor_len = trans_pcie->fw_mon_size; 2717 } else if (trans->dbg_dest_tlv) { 2718 u32 base, end; 2719 2720 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2721 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2722 2723 base = iwl_read_prph(trans, base) << 2724 trans->dbg_dest_tlv->base_shift; 2725 end = iwl_read_prph(trans, end) << 2726 trans->dbg_dest_tlv->end_shift; 2727 2728 /* Make "end" point to the actual end */ 2729 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2730 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2731 end += (1 << trans->dbg_dest_tlv->end_shift); 2732 monitor_len = end - base; 2733 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2734 monitor_len; 2735 } else { 2736 monitor_len = 0; 2737 } 2738 2739 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2740 dump_data = vzalloc(len); 2741 if (!dump_data) 2742 return NULL; 2743 2744 data = (void *)dump_data->data; 2745 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2746 dump_data->len = len; 2747 2748 return dump_data; 2749 } 2750 2751 /* CSR registers */ 2752 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2753 2754 /* FH registers */ 2755 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2756 2757 if (dump_rbs) { 2758 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2759 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2760 /* RBs */ 2761 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2762 & 0x0FFF; 2763 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2764 len += num_rbs * (sizeof(*data) + 2765 sizeof(struct iwl_fw_error_dump_rb) + 2766 (PAGE_SIZE << trans_pcie->rx_page_order)); 2767 } 2768 2769 /* Paged memory for gen2 HW */ 2770 if (trans->cfg->gen2) 2771 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 2772 len += sizeof(*data) + 2773 sizeof(struct iwl_fw_error_dump_paging) + 2774 trans_pcie->init_dram.paging[i].size; 2775 2776 dump_data = vzalloc(len); 2777 if (!dump_data) 2778 return NULL; 2779 2780 len = 0; 2781 data = (void *)dump_data->data; 2782 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2783 txcmd = (void *)data->data; 2784 spin_lock_bh(&cmdq->lock); 2785 ptr = cmdq->write_ptr; 2786 for (i = 0; i < cmdq->n_window; i++) { 2787 u8 idx = get_cmd_index(cmdq, ptr); 2788 u32 caplen, cmdlen; 2789 2790 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 2791 trans_pcie->tfd_size * ptr); 2792 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2793 2794 if (cmdlen) { 2795 len += sizeof(*txcmd) + caplen; 2796 txcmd->cmdlen = cpu_to_le32(cmdlen); 2797 txcmd->caplen = cpu_to_le32(caplen); 2798 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2799 txcmd = (void *)((u8 *)txcmd->data + caplen); 2800 } 2801 2802 ptr = iwl_queue_dec_wrap(ptr); 2803 } 2804 spin_unlock_bh(&cmdq->lock); 2805 2806 data->len = cpu_to_le32(len); 2807 len += sizeof(*data); 2808 data = iwl_fw_error_next_data(data); 2809 2810 len += iwl_trans_pcie_dump_csr(trans, &data); 2811 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2812 if (dump_rbs) 2813 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2814 2815 /* Paged memory for gen2 HW */ 2816 if (trans->cfg->gen2) { 2817 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 2818 struct iwl_fw_error_dump_paging *paging; 2819 dma_addr_t addr = 2820 trans_pcie->init_dram.paging[i].physical; 2821 u32 page_len = trans_pcie->init_dram.paging[i].size; 2822 2823 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 2824 data->len = cpu_to_le32(sizeof(*paging) + page_len); 2825 paging = (void *)data->data; 2826 paging->index = cpu_to_le32(i); 2827 dma_sync_single_for_cpu(trans->dev, addr, page_len, 2828 DMA_BIDIRECTIONAL); 2829 memcpy(paging->data, 2830 trans_pcie->init_dram.paging[i].block, page_len); 2831 data = iwl_fw_error_next_data(data); 2832 2833 len += sizeof(*data) + sizeof(*paging) + page_len; 2834 } 2835 } 2836 2837 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2838 2839 dump_data->len = len; 2840 2841 return dump_data; 2842 } 2843 2844 #ifdef CONFIG_PM_SLEEP 2845 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2846 { 2847 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2848 return iwl_pci_fw_enter_d0i3(trans); 2849 2850 return 0; 2851 } 2852 2853 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2854 { 2855 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2856 iwl_pci_fw_exit_d0i3(trans); 2857 } 2858 #endif /* CONFIG_PM_SLEEP */ 2859 2860 #define IWL_TRANS_COMMON_OPS \ 2861 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 2862 .write8 = iwl_trans_pcie_write8, \ 2863 .write32 = iwl_trans_pcie_write32, \ 2864 .read32 = iwl_trans_pcie_read32, \ 2865 .read_prph = iwl_trans_pcie_read_prph, \ 2866 .write_prph = iwl_trans_pcie_write_prph, \ 2867 .read_mem = iwl_trans_pcie_read_mem, \ 2868 .write_mem = iwl_trans_pcie_write_mem, \ 2869 .configure = iwl_trans_pcie_configure, \ 2870 .set_pmi = iwl_trans_pcie_set_pmi, \ 2871 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 2872 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 2873 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 2874 .ref = iwl_trans_pcie_ref, \ 2875 .unref = iwl_trans_pcie_unref, \ 2876 .dump_data = iwl_trans_pcie_dump_data, \ 2877 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 2878 .d3_resume = iwl_trans_pcie_d3_resume 2879 2880 #ifdef CONFIG_PM_SLEEP 2881 #define IWL_TRANS_PM_OPS \ 2882 .suspend = iwl_trans_pcie_suspend, \ 2883 .resume = iwl_trans_pcie_resume, 2884 #else 2885 #define IWL_TRANS_PM_OPS 2886 #endif /* CONFIG_PM_SLEEP */ 2887 2888 static const struct iwl_trans_ops trans_ops_pcie = { 2889 IWL_TRANS_COMMON_OPS, 2890 IWL_TRANS_PM_OPS 2891 .start_hw = iwl_trans_pcie_start_hw, 2892 .fw_alive = iwl_trans_pcie_fw_alive, 2893 .start_fw = iwl_trans_pcie_start_fw, 2894 .stop_device = iwl_trans_pcie_stop_device, 2895 2896 .send_cmd = iwl_trans_pcie_send_hcmd, 2897 2898 .tx = iwl_trans_pcie_tx, 2899 .reclaim = iwl_trans_pcie_reclaim, 2900 2901 .txq_disable = iwl_trans_pcie_txq_disable, 2902 .txq_enable = iwl_trans_pcie_txq_enable, 2903 2904 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2905 2906 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 2907 2908 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2909 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2910 }; 2911 2912 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 2913 IWL_TRANS_COMMON_OPS, 2914 IWL_TRANS_PM_OPS 2915 .start_hw = iwl_trans_pcie_start_hw, 2916 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 2917 .start_fw = iwl_trans_pcie_gen2_start_fw, 2918 .stop_device = iwl_trans_pcie_gen2_stop_device, 2919 2920 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 2921 2922 .tx = iwl_trans_pcie_gen2_tx, 2923 .reclaim = iwl_trans_pcie_reclaim, 2924 2925 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 2926 .txq_free = iwl_trans_pcie_dyn_txq_free, 2927 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 2928 }; 2929 2930 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2931 const struct pci_device_id *ent, 2932 const struct iwl_cfg *cfg) 2933 { 2934 struct iwl_trans_pcie *trans_pcie; 2935 struct iwl_trans *trans; 2936 int ret, addr_size; 2937 2938 ret = pcim_enable_device(pdev); 2939 if (ret) 2940 return ERR_PTR(ret); 2941 2942 if (cfg->gen2) 2943 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2944 &pdev->dev, cfg, &trans_ops_pcie_gen2); 2945 else 2946 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2947 &pdev->dev, cfg, &trans_ops_pcie); 2948 if (!trans) 2949 return ERR_PTR(-ENOMEM); 2950 2951 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2952 2953 trans_pcie->trans = trans; 2954 spin_lock_init(&trans_pcie->irq_lock); 2955 spin_lock_init(&trans_pcie->reg_lock); 2956 mutex_init(&trans_pcie->mutex); 2957 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 2958 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 2959 if (!trans_pcie->tso_hdr_page) { 2960 ret = -ENOMEM; 2961 goto out_no_pci; 2962 } 2963 2964 2965 if (!cfg->base_params->pcie_l1_allowed) { 2966 /* 2967 * W/A - seems to solve weird behavior. We need to remove this 2968 * if we don't want to stay in L1 all the time. This wastes a 2969 * lot of power. 2970 */ 2971 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2972 PCIE_LINK_STATE_L1 | 2973 PCIE_LINK_STATE_CLKPM); 2974 } 2975 2976 if (cfg->use_tfh) { 2977 addr_size = 64; 2978 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 2979 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 2980 } else { 2981 addr_size = 36; 2982 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 2983 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 2984 } 2985 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 2986 2987 pci_set_master(pdev); 2988 2989 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2990 if (!ret) 2991 ret = pci_set_consistent_dma_mask(pdev, 2992 DMA_BIT_MASK(addr_size)); 2993 if (ret) { 2994 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2995 if (!ret) 2996 ret = pci_set_consistent_dma_mask(pdev, 2997 DMA_BIT_MASK(32)); 2998 /* both attempts failed: */ 2999 if (ret) { 3000 dev_err(&pdev->dev, "No suitable DMA available\n"); 3001 goto out_no_pci; 3002 } 3003 } 3004 3005 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3006 if (ret) { 3007 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3008 goto out_no_pci; 3009 } 3010 3011 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3012 if (!trans_pcie->hw_base) { 3013 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3014 ret = -ENODEV; 3015 goto out_no_pci; 3016 } 3017 3018 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3019 * PCI Tx retries from interfering with C3 CPU state */ 3020 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3021 3022 trans_pcie->pci_dev = pdev; 3023 iwl_disable_interrupts(trans); 3024 3025 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3026 /* 3027 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3028 * changed, and now the revision step also includes bit 0-1 (no more 3029 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3030 * in the old format. 3031 */ 3032 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 3033 unsigned long flags; 3034 3035 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3036 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3037 3038 ret = iwl_pcie_prepare_card_hw(trans); 3039 if (ret) { 3040 IWL_WARN(trans, "Exit HW not ready\n"); 3041 goto out_no_pci; 3042 } 3043 3044 /* 3045 * in-order to recognize C step driver should read chip version 3046 * id located at the AUX bus MISC address space. 3047 */ 3048 iwl_set_bit(trans, CSR_GP_CNTRL, 3049 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3050 udelay(2); 3051 3052 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3053 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3054 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3055 25000); 3056 if (ret < 0) { 3057 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3058 goto out_no_pci; 3059 } 3060 3061 if (iwl_trans_grab_nic_access(trans, &flags)) { 3062 u32 hw_step; 3063 3064 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3065 hw_step |= ENABLE_WFPM; 3066 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3067 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3068 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3069 if (hw_step == 0x3) 3070 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3071 (SILICON_C_STEP << 2); 3072 iwl_trans_release_nic_access(trans, &flags); 3073 } 3074 } 3075 3076 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3077 3078 iwl_pcie_set_interrupt_capa(pdev, trans); 3079 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3080 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3081 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3082 3083 /* Initialize the wait queue for commands */ 3084 init_waitqueue_head(&trans_pcie->wait_command_queue); 3085 3086 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3087 3088 if (trans_pcie->msix_enabled) { 3089 if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 3090 goto out_no_pci; 3091 } else { 3092 ret = iwl_pcie_alloc_ict(trans); 3093 if (ret) 3094 goto out_no_pci; 3095 3096 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3097 iwl_pcie_isr, 3098 iwl_pcie_irq_handler, 3099 IRQF_SHARED, DRV_NAME, trans); 3100 if (ret) { 3101 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3102 goto out_free_ict; 3103 } 3104 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3105 } 3106 3107 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3108 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3109 #else 3110 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3111 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3112 3113 return trans; 3114 3115 out_free_ict: 3116 iwl_pcie_free_ict(trans); 3117 out_no_pci: 3118 free_percpu(trans_pcie->tso_hdr_page); 3119 iwl_trans_free(trans); 3120 return ERR_PTR(ret); 3121 } 3122