1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "iwl-context-info.h" 84 #include "iwl-fw-error-dump.h" 85 #include "internal.h" 86 #include "iwl-fh.h" 87 88 /* extended range in FW SRAM */ 89 #define IWL_FW_MEM_EXTENDED_START 0x40000 90 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 91 92 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 93 { 94 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 95 96 if (!trans_pcie->fw_mon_page) 97 return; 98 99 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 100 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 101 __free_pages(trans_pcie->fw_mon_page, 102 get_order(trans_pcie->fw_mon_size)); 103 trans_pcie->fw_mon_page = NULL; 104 trans_pcie->fw_mon_phys = 0; 105 trans_pcie->fw_mon_size = 0; 106 } 107 108 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 109 { 110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 111 struct page *page = NULL; 112 dma_addr_t phys; 113 u32 size = 0; 114 u8 power; 115 116 if (!max_power) { 117 /* default max_power is maximum */ 118 max_power = 26; 119 } else { 120 max_power += 11; 121 } 122 123 if (WARN(max_power > 26, 124 "External buffer size for monitor is too big %d, check the FW TLV\n", 125 max_power)) 126 return; 127 128 if (trans_pcie->fw_mon_page) { 129 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 130 trans_pcie->fw_mon_size, 131 DMA_FROM_DEVICE); 132 return; 133 } 134 135 phys = 0; 136 for (power = max_power; power >= 11; power--) { 137 int order; 138 139 size = BIT(power); 140 order = get_order(size); 141 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 142 order); 143 if (!page) 144 continue; 145 146 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 147 DMA_FROM_DEVICE); 148 if (dma_mapping_error(trans->dev, phys)) { 149 __free_pages(page, order); 150 page = NULL; 151 continue; 152 } 153 IWL_INFO(trans, 154 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 155 size, order); 156 break; 157 } 158 159 if (WARN_ON_ONCE(!page)) 160 return; 161 162 if (power != max_power) 163 IWL_ERR(trans, 164 "Sorry - debug buffer is only %luK while you requested %luK\n", 165 (unsigned long)BIT(power - 10), 166 (unsigned long)BIT(max_power - 10)); 167 168 trans_pcie->fw_mon_page = page; 169 trans_pcie->fw_mon_phys = phys; 170 trans_pcie->fw_mon_size = size; 171 } 172 173 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 174 { 175 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 176 ((reg & 0x0000ffff) | (2 << 28))); 177 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 178 } 179 180 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 181 { 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 183 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 184 ((reg & 0x0000ffff) | (3 << 28))); 185 } 186 187 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 188 { 189 if (trans->cfg->apmg_not_supported) 190 return; 191 192 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 193 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 194 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 195 ~APMG_PS_CTRL_MSK_PWR_SRC); 196 else 197 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 198 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 199 ~APMG_PS_CTRL_MSK_PWR_SRC); 200 } 201 202 /* PCI registers */ 203 #define PCI_CFG_RETRY_TIMEOUT 0x041 204 205 void iwl_pcie_apm_config(struct iwl_trans *trans) 206 { 207 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 208 u16 lctl; 209 u16 cap; 210 211 /* 212 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 213 * Check if BIOS (or OS) enabled L1-ASPM on this device. 214 * If so (likely), disable L0S, so device moves directly L0->L1; 215 * costs negligible amount of power savings. 216 * If not (unlikely), enable L0S, so there is at least some 217 * power savings, even without L1. 218 */ 219 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 220 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 221 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 222 else 223 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 224 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 225 226 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 227 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 228 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 229 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 230 trans->ltr_enabled ? "En" : "Dis"); 231 } 232 233 /* 234 * Start up NIC's basic functionality after it has been reset 235 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 236 * NOTE: This does not load uCode nor start the embedded processor 237 */ 238 static int iwl_pcie_apm_init(struct iwl_trans *trans) 239 { 240 int ret = 0; 241 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 242 243 /* 244 * Use "set_bit" below rather than "write", to preserve any hardware 245 * bits already set by default after reset. 246 */ 247 248 /* Disable L0S exit timer (platform NMI Work/Around) */ 249 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 250 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 251 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 252 253 /* 254 * Disable L0s without affecting L1; 255 * don't wait for ICH L0s (ICH bug W/A) 256 */ 257 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 258 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 259 260 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 261 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 262 263 /* 264 * Enable HAP INTA (interrupt from management bus) to 265 * wake device's PCI Express link L1a -> L0s 266 */ 267 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 268 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 269 270 iwl_pcie_apm_config(trans); 271 272 /* Configure analog phase-lock-loop before activating to D0A */ 273 if (trans->cfg->base_params->pll_cfg) 274 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 275 276 /* 277 * Set "initialization complete" bit to move adapter from 278 * D0U* --> D0A* (powered-up active) state. 279 */ 280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 281 282 /* 283 * Wait for clock stabilization; once stabilized, access to 284 * device-internal resources is supported, e.g. iwl_write_prph() 285 * and accesses to uCode SRAM. 286 */ 287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 290 if (ret < 0) { 291 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 292 goto out; 293 } 294 295 if (trans->cfg->host_interrupt_operation_mode) { 296 /* 297 * This is a bit of an abuse - This is needed for 7260 / 3160 298 * only check host_interrupt_operation_mode even if this is 299 * not related to host_interrupt_operation_mode. 300 * 301 * Enable the oscillator to count wake up time for L1 exit. This 302 * consumes slightly more power (100uA) - but allows to be sure 303 * that we wake up from L1 on time. 304 * 305 * This looks weird: read twice the same register, discard the 306 * value, set a bit, and yet again, read that same register 307 * just to discard the value. But that's the way the hardware 308 * seems to like it. 309 */ 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_read_prph(trans, OSC_CLK); 312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 313 iwl_read_prph(trans, OSC_CLK); 314 iwl_read_prph(trans, OSC_CLK); 315 } 316 317 /* 318 * Enable DMA clock and wait for it to stabilize. 319 * 320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 321 * bits do not disable clocks. This preserves any hardware 322 * bits already set by default in "CLK_CTRL_REG" after reset. 323 */ 324 if (!trans->cfg->apmg_not_supported) { 325 iwl_write_prph(trans, APMG_CLK_EN_REG, 326 APMG_CLK_VAL_DMA_CLK_RQT); 327 udelay(20); 328 329 /* Disable L1-Active */ 330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 332 333 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 335 APMG_RTC_INT_STT_RFKILL); 336 } 337 338 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 339 340 out: 341 return ret; 342 } 343 344 /* 345 * Enable LP XTAL to avoid HW bug where device may consume much power if 346 * FW is not loaded after device reset. LP XTAL is disabled by default 347 * after device HW reset. Do it only if XTAL is fed by internal source. 348 * Configure device's "persistence" mode to avoid resetting XTAL again when 349 * SHRD_HW_RST occurs in S3. 350 */ 351 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 352 { 353 int ret; 354 u32 apmg_gp1_reg; 355 u32 apmg_xtal_cfg_reg; 356 u32 dl_cfg_reg; 357 358 /* Force XTAL ON */ 359 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 360 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 361 362 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 363 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 364 usleep_range(1000, 2000); 365 366 /* 367 * Set "initialization complete" bit to move adapter from 368 * D0U* --> D0A* (powered-up active) state. 369 */ 370 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 371 372 /* 373 * Wait for clock stabilization; once stabilized, access to 374 * device-internal resources is possible. 375 */ 376 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 379 25000); 380 if (WARN_ON(ret < 0)) { 381 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 382 /* Release XTAL ON request */ 383 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 384 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 385 return; 386 } 387 388 /* 389 * Clear "disable persistence" to avoid LP XTAL resetting when 390 * SHRD_HW_RST is applied in S3. 391 */ 392 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 393 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 394 395 /* 396 * Force APMG XTAL to be active to prevent its disabling by HW 397 * caused by APMG idle state. 398 */ 399 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 400 SHR_APMG_XTAL_CFG_REG); 401 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 402 apmg_xtal_cfg_reg | 403 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 404 405 /* 406 * Reset entire device again - do controller reset (results in 407 * SHRD_HW_RST). Turn MAC off before proceeding. 408 */ 409 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 410 usleep_range(1000, 2000); 411 412 /* Enable LP XTAL by indirect access through CSR */ 413 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 414 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 415 SHR_APMG_GP1_WF_XTAL_LP_EN | 416 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 417 418 /* Clear delay line clock power up */ 419 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 420 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 421 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 422 423 /* 424 * Enable persistence mode to avoid LP XTAL resetting when 425 * SHRD_HW_RST is applied in S3. 426 */ 427 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 428 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 429 430 /* 431 * Clear "initialization complete" bit to move adapter from 432 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 433 */ 434 iwl_clear_bit(trans, CSR_GP_CNTRL, 435 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 436 437 /* Activates XTAL resources monitor */ 438 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 439 CSR_MONITOR_XTAL_RESOURCES); 440 441 /* Release XTAL ON request */ 442 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 443 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 444 udelay(10); 445 446 /* Release APMG XTAL */ 447 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 448 apmg_xtal_cfg_reg & 449 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 450 } 451 452 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 453 { 454 int ret = 0; 455 456 /* stop device's busmaster DMA activity */ 457 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 458 459 ret = iwl_poll_bit(trans, CSR_RESET, 460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 461 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 462 if (ret < 0) 463 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 464 465 IWL_DEBUG_INFO(trans, "stop master\n"); 466 467 return ret; 468 } 469 470 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 471 { 472 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 473 474 if (op_mode_leave) { 475 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 476 iwl_pcie_apm_init(trans); 477 478 /* inform ME that we are leaving */ 479 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 480 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 481 APMG_PCIDEV_STT_VAL_WAKE_ME); 482 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 483 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 484 CSR_RESET_LINK_PWR_MGMT_DISABLED); 485 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 486 CSR_HW_IF_CONFIG_REG_PREPARE | 487 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 488 mdelay(1); 489 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 490 CSR_RESET_LINK_PWR_MGMT_DISABLED); 491 } 492 mdelay(5); 493 } 494 495 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 496 497 /* Stop device's DMA activity */ 498 iwl_pcie_apm_stop_master(trans); 499 500 if (trans->cfg->lp_xtal_workaround) { 501 iwl_pcie_apm_lp_xtal_enable(trans); 502 return; 503 } 504 505 /* Reset the entire device */ 506 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 507 usleep_range(1000, 2000); 508 509 /* 510 * Clear "initialization complete" bit to move adapter from 511 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 512 */ 513 iwl_clear_bit(trans, CSR_GP_CNTRL, 514 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 515 } 516 517 static int iwl_pcie_nic_init(struct iwl_trans *trans) 518 { 519 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 520 521 /* nic_init */ 522 spin_lock(&trans_pcie->irq_lock); 523 iwl_pcie_apm_init(trans); 524 525 spin_unlock(&trans_pcie->irq_lock); 526 527 iwl_pcie_set_pwr(trans, false); 528 529 iwl_op_mode_nic_config(trans->op_mode); 530 531 /* Allocate the RX queue, or reset if it is already allocated */ 532 iwl_pcie_rx_init(trans); 533 534 /* Allocate or reset and init all Tx and Command queues */ 535 if (iwl_pcie_tx_init(trans)) 536 return -ENOMEM; 537 538 if (trans->cfg->base_params->shadow_reg_enable) { 539 /* enable shadow regs in HW */ 540 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 541 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 542 } 543 544 return 0; 545 } 546 547 #define HW_READY_TIMEOUT (50) 548 549 /* Note: returns poll_bit return value, which is >= 0 if success */ 550 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 551 { 552 int ret; 553 554 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 555 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 556 557 /* See if we got it */ 558 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 561 HW_READY_TIMEOUT); 562 563 if (ret >= 0) 564 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 565 566 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 567 return ret; 568 } 569 570 /* Note: returns standard 0/-ERROR code */ 571 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 572 { 573 int ret; 574 int t = 0; 575 int iter; 576 577 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 578 579 ret = iwl_pcie_set_hw_ready(trans); 580 /* If the card is ready, exit 0 */ 581 if (ret >= 0) 582 return 0; 583 584 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 585 CSR_RESET_LINK_PWR_MGMT_DISABLED); 586 usleep_range(1000, 2000); 587 588 for (iter = 0; iter < 10; iter++) { 589 /* If HW is not ready, prepare the conditions to check again */ 590 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 591 CSR_HW_IF_CONFIG_REG_PREPARE); 592 593 do { 594 ret = iwl_pcie_set_hw_ready(trans); 595 if (ret >= 0) 596 return 0; 597 598 usleep_range(200, 1000); 599 t += 200; 600 } while (t < 150000); 601 msleep(25); 602 } 603 604 IWL_ERR(trans, "Couldn't prepare the card\n"); 605 606 return ret; 607 } 608 609 /* 610 * ucode 611 */ 612 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 613 u32 dst_addr, dma_addr_t phy_addr, 614 u32 byte_cnt) 615 { 616 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 617 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 618 619 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 620 dst_addr); 621 622 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 623 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 624 625 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 626 (iwl_get_dma_hi_addr(phy_addr) 627 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 628 629 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 631 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 632 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 633 634 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 636 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 637 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 638 } 639 640 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 641 u32 dst_addr, dma_addr_t phy_addr, 642 u32 byte_cnt) 643 { 644 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 645 unsigned long flags; 646 int ret; 647 648 trans_pcie->ucode_write_complete = false; 649 650 if (!iwl_trans_grab_nic_access(trans, &flags)) 651 return -EIO; 652 653 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 654 byte_cnt); 655 iwl_trans_release_nic_access(trans, &flags); 656 657 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 658 trans_pcie->ucode_write_complete, 5 * HZ); 659 if (!ret) { 660 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 661 return -ETIMEDOUT; 662 } 663 664 return 0; 665 } 666 667 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 668 const struct fw_desc *section) 669 { 670 u8 *v_addr; 671 dma_addr_t p_addr; 672 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 673 int ret = 0; 674 675 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 676 section_num); 677 678 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 679 GFP_KERNEL | __GFP_NOWARN); 680 if (!v_addr) { 681 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 682 chunk_sz = PAGE_SIZE; 683 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 684 &p_addr, GFP_KERNEL); 685 if (!v_addr) 686 return -ENOMEM; 687 } 688 689 for (offset = 0; offset < section->len; offset += chunk_sz) { 690 u32 copy_size, dst_addr; 691 bool extended_addr = false; 692 693 copy_size = min_t(u32, chunk_sz, section->len - offset); 694 dst_addr = section->offset + offset; 695 696 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 697 dst_addr <= IWL_FW_MEM_EXTENDED_END) 698 extended_addr = true; 699 700 if (extended_addr) 701 iwl_set_bits_prph(trans, LMPM_CHICK, 702 LMPM_CHICK_EXTENDED_ADDR_SPACE); 703 704 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 705 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 706 copy_size); 707 708 if (extended_addr) 709 iwl_clear_bits_prph(trans, LMPM_CHICK, 710 LMPM_CHICK_EXTENDED_ADDR_SPACE); 711 712 if (ret) { 713 IWL_ERR(trans, 714 "Could not load the [%d] uCode section\n", 715 section_num); 716 break; 717 } 718 } 719 720 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 721 return ret; 722 } 723 724 /* 725 * Driver Takes the ownership on secure machine before FW load 726 * and prevent race with the BT load. 727 * W/A for ROM bug. (should be remove in the next Si step) 728 */ 729 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 730 { 731 u32 val, loop = 1000; 732 733 /* 734 * Check the RSA semaphore is accessible. 735 * If the HW isn't locked and the rsa semaphore isn't accessible, 736 * we are in trouble. 737 */ 738 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 739 if (val & (BIT(1) | BIT(17))) { 740 IWL_DEBUG_INFO(trans, 741 "can't access the RSA semaphore it is write protected\n"); 742 return 0; 743 } 744 745 /* take ownership on the AUX IF */ 746 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 747 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 748 749 do { 750 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 751 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 752 if (val == 0x1) { 753 iwl_write_prph(trans, RSA_ENABLE, 0); 754 return 0; 755 } 756 757 udelay(10); 758 loop--; 759 } while (loop > 0); 760 761 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 762 return -EIO; 763 } 764 765 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 766 const struct fw_img *image, 767 int cpu, 768 int *first_ucode_section) 769 { 770 int shift_param; 771 int i, ret = 0, sec_num = 0x1; 772 u32 val, last_read_idx = 0; 773 774 if (cpu == 1) { 775 shift_param = 0; 776 *first_ucode_section = 0; 777 } else { 778 shift_param = 16; 779 (*first_ucode_section)++; 780 } 781 782 for (i = *first_ucode_section; i < image->num_sec; i++) { 783 last_read_idx = i; 784 785 /* 786 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 787 * CPU1 to CPU2. 788 * PAGING_SEPARATOR_SECTION delimiter - separate between 789 * CPU2 non paged to CPU2 paging sec. 790 */ 791 if (!image->sec[i].data || 792 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 793 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 794 IWL_DEBUG_FW(trans, 795 "Break since Data not valid or Empty section, sec = %d\n", 796 i); 797 break; 798 } 799 800 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 801 if (ret) 802 return ret; 803 804 /* Notify ucode of loaded section number and status */ 805 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 806 val = val | (sec_num << shift_param); 807 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 808 809 sec_num = (sec_num << 1) | 0x1; 810 } 811 812 *first_ucode_section = last_read_idx; 813 814 iwl_enable_interrupts(trans); 815 816 if (trans->cfg->use_tfh) { 817 if (cpu == 1) 818 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 819 0xFFFF); 820 else 821 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 822 0xFFFFFFFF); 823 } else { 824 if (cpu == 1) 825 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 826 0xFFFF); 827 else 828 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 829 0xFFFFFFFF); 830 } 831 832 return 0; 833 } 834 835 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 836 const struct fw_img *image, 837 int cpu, 838 int *first_ucode_section) 839 { 840 int i, ret = 0; 841 u32 last_read_idx = 0; 842 843 if (cpu == 1) 844 *first_ucode_section = 0; 845 else 846 (*first_ucode_section)++; 847 848 for (i = *first_ucode_section; i < image->num_sec; i++) { 849 last_read_idx = i; 850 851 /* 852 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 853 * CPU1 to CPU2. 854 * PAGING_SEPARATOR_SECTION delimiter - separate between 855 * CPU2 non paged to CPU2 paging sec. 856 */ 857 if (!image->sec[i].data || 858 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 859 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 860 IWL_DEBUG_FW(trans, 861 "Break since Data not valid or Empty section, sec = %d\n", 862 i); 863 break; 864 } 865 866 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 867 if (ret) 868 return ret; 869 } 870 871 *first_ucode_section = last_read_idx; 872 873 return 0; 874 } 875 876 static void iwl_pcie_apply_destination(struct iwl_trans *trans) 877 { 878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 879 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 880 int i; 881 882 if (dest->version) 883 IWL_ERR(trans, 884 "DBG DEST version is %d - expect issues\n", 885 dest->version); 886 887 IWL_INFO(trans, "Applying debug destination %s\n", 888 get_fw_dbg_mode_string(dest->monitor_mode)); 889 890 if (dest->monitor_mode == EXTERNAL_MODE) 891 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 892 else 893 IWL_WARN(trans, "PCI should have external buffer debug\n"); 894 895 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 896 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 897 u32 val = le32_to_cpu(dest->reg_ops[i].val); 898 899 switch (dest->reg_ops[i].op) { 900 case CSR_ASSIGN: 901 iwl_write32(trans, addr, val); 902 break; 903 case CSR_SETBIT: 904 iwl_set_bit(trans, addr, BIT(val)); 905 break; 906 case CSR_CLEARBIT: 907 iwl_clear_bit(trans, addr, BIT(val)); 908 break; 909 case PRPH_ASSIGN: 910 iwl_write_prph(trans, addr, val); 911 break; 912 case PRPH_SETBIT: 913 iwl_set_bits_prph(trans, addr, BIT(val)); 914 break; 915 case PRPH_CLEARBIT: 916 iwl_clear_bits_prph(trans, addr, BIT(val)); 917 break; 918 case PRPH_BLOCKBIT: 919 if (iwl_read_prph(trans, addr) & BIT(val)) { 920 IWL_ERR(trans, 921 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 922 val, addr); 923 goto monitor; 924 } 925 break; 926 default: 927 IWL_ERR(trans, "FW debug - unknown OP %d\n", 928 dest->reg_ops[i].op); 929 break; 930 } 931 } 932 933 monitor: 934 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 935 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 936 trans_pcie->fw_mon_phys >> dest->base_shift); 937 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 938 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 939 (trans_pcie->fw_mon_phys + 940 trans_pcie->fw_mon_size - 256) >> 941 dest->end_shift); 942 else 943 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 944 (trans_pcie->fw_mon_phys + 945 trans_pcie->fw_mon_size) >> 946 dest->end_shift); 947 } 948 } 949 950 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 951 const struct fw_img *image) 952 { 953 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 954 int ret = 0; 955 int first_ucode_section; 956 957 IWL_DEBUG_FW(trans, "working with %s CPU\n", 958 image->is_dual_cpus ? "Dual" : "Single"); 959 960 /* load to FW the binary non secured sections of CPU1 */ 961 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 962 if (ret) 963 return ret; 964 965 if (image->is_dual_cpus) { 966 /* set CPU2 header address */ 967 iwl_write_prph(trans, 968 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 969 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 970 971 /* load to FW the binary sections of CPU2 */ 972 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 973 &first_ucode_section); 974 if (ret) 975 return ret; 976 } 977 978 /* supported for 7000 only for the moment */ 979 if (iwlwifi_mod_params.fw_monitor && 980 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 981 iwl_pcie_alloc_fw_monitor(trans, 0); 982 983 if (trans_pcie->fw_mon_size) { 984 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 985 trans_pcie->fw_mon_phys >> 4); 986 iwl_write_prph(trans, MON_BUFF_END_ADDR, 987 (trans_pcie->fw_mon_phys + 988 trans_pcie->fw_mon_size) >> 4); 989 } 990 } else if (trans->dbg_dest_tlv) { 991 iwl_pcie_apply_destination(trans); 992 } 993 994 iwl_enable_interrupts(trans); 995 996 /* release CPU reset */ 997 iwl_write32(trans, CSR_RESET, 0); 998 999 return 0; 1000 } 1001 1002 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1003 const struct fw_img *image) 1004 { 1005 int ret = 0; 1006 int first_ucode_section; 1007 1008 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1009 image->is_dual_cpus ? "Dual" : "Single"); 1010 1011 if (trans->dbg_dest_tlv) 1012 iwl_pcie_apply_destination(trans); 1013 1014 /* TODO: remove in the next Si step */ 1015 ret = iwl_pcie_rsa_race_bug_wa(trans); 1016 if (ret) 1017 return ret; 1018 1019 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1020 iwl_read_prph(trans, WFPM_GP2)); 1021 1022 /* 1023 * Set default value. On resume reading the values that were 1024 * zeored can provide debug data on the resume flow. 1025 * This is for debugging only and has no functional impact. 1026 */ 1027 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1028 1029 /* configure the ucode to be ready to get the secured image */ 1030 /* release CPU reset */ 1031 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1032 1033 /* load to FW the binary Secured sections of CPU1 */ 1034 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1035 &first_ucode_section); 1036 if (ret) 1037 return ret; 1038 1039 /* load to FW the binary sections of CPU2 */ 1040 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1041 &first_ucode_section); 1042 } 1043 1044 bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans) 1045 { 1046 bool hw_rfkill = iwl_is_rfkill_set(trans); 1047 1048 if (hw_rfkill) 1049 set_bit(STATUS_RFKILL, &trans->status); 1050 else 1051 clear_bit(STATUS_RFKILL, &trans->status); 1052 1053 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1054 1055 return hw_rfkill; 1056 } 1057 1058 struct iwl_causes_list { 1059 u32 cause_num; 1060 u32 mask_reg; 1061 u8 addr; 1062 }; 1063 1064 static struct iwl_causes_list causes_list[] = { 1065 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1066 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1067 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1068 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1069 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1070 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1071 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1072 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1073 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1074 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1075 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1076 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1077 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1078 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1079 }; 1080 1081 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1082 { 1083 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1084 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1085 int i; 1086 1087 /* 1088 * Access all non RX causes and map them to the default irq. 1089 * In case we are missing at least one interrupt vector, 1090 * the first interrupt vector will serve non-RX and FBQ causes. 1091 */ 1092 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1093 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1094 iwl_clear_bit(trans, causes_list[i].mask_reg, 1095 causes_list[i].cause_num); 1096 } 1097 } 1098 1099 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1100 { 1101 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1102 u32 offset = 1103 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1104 u32 val, idx; 1105 1106 /* 1107 * The first RX queue - fallback queue, which is designated for 1108 * management frame, command responses etc, is always mapped to the 1109 * first interrupt vector. The other RX queues are mapped to 1110 * the other (N - 2) interrupt vectors. 1111 */ 1112 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1113 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1114 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1115 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1116 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1117 } 1118 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1119 1120 val = MSIX_FH_INT_CAUSES_Q(0); 1121 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1122 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1123 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1124 1125 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1126 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1127 } 1128 1129 static void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1130 { 1131 struct iwl_trans *trans = trans_pcie->trans; 1132 1133 if (!trans_pcie->msix_enabled) { 1134 if (trans->cfg->mq_rx_supported && 1135 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1136 iwl_write_prph(trans, UREG_CHICK, 1137 UREG_CHICK_MSI_ENABLE); 1138 return; 1139 } 1140 /* 1141 * The IVAR table needs to be configured again after reset, 1142 * but if the device is disabled, we can't write to 1143 * prph. 1144 */ 1145 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1146 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1147 1148 /* 1149 * Each cause from the causes list above and the RX causes is 1150 * represented as a byte in the IVAR table. The first nibble 1151 * represents the bound interrupt vector of the cause, the second 1152 * represents no auto clear for this cause. This will be set if its 1153 * interrupt vector is bound to serve other causes. 1154 */ 1155 iwl_pcie_map_rx_causes(trans); 1156 1157 iwl_pcie_map_non_rx_causes(trans); 1158 } 1159 1160 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1161 { 1162 struct iwl_trans *trans = trans_pcie->trans; 1163 1164 iwl_pcie_conf_msix_hw(trans_pcie); 1165 1166 if (!trans_pcie->msix_enabled) 1167 return; 1168 1169 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1170 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1171 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1172 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1173 } 1174 1175 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1176 { 1177 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1178 bool hw_rfkill, was_hw_rfkill; 1179 1180 lockdep_assert_held(&trans_pcie->mutex); 1181 1182 if (trans_pcie->is_down) 1183 return; 1184 1185 trans_pcie->is_down = true; 1186 1187 was_hw_rfkill = iwl_is_rfkill_set(trans); 1188 1189 /* tell the device to stop sending interrupts */ 1190 iwl_disable_interrupts(trans); 1191 1192 /* device going down, Stop using ICT table */ 1193 iwl_pcie_disable_ict(trans); 1194 1195 /* 1196 * If a HW restart happens during firmware loading, 1197 * then the firmware loading might call this function 1198 * and later it might be called again due to the 1199 * restart. So don't process again if the device is 1200 * already dead. 1201 */ 1202 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1203 IWL_DEBUG_INFO(trans, 1204 "DEVICE_ENABLED bit was set and is now cleared\n"); 1205 iwl_pcie_tx_stop(trans); 1206 iwl_pcie_rx_stop(trans); 1207 1208 /* Power-down device's busmaster DMA clocks */ 1209 if (!trans->cfg->apmg_not_supported) { 1210 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1211 APMG_CLK_VAL_DMA_CLK_RQT); 1212 udelay(5); 1213 } 1214 } 1215 1216 iwl_pcie_ctxt_info_free_paging(trans); 1217 iwl_pcie_ctxt_info_free(trans); 1218 1219 /* Make sure (redundant) we've released our request to stay awake */ 1220 iwl_clear_bit(trans, CSR_GP_CNTRL, 1221 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1222 1223 /* Stop the device, and put it in low power state */ 1224 iwl_pcie_apm_stop(trans, false); 1225 1226 /* stop and reset the on-board processor */ 1227 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1228 usleep_range(1000, 2000); 1229 1230 /* 1231 * Upon stop, the IVAR table gets erased, so msi-x won't 1232 * work. This causes a bug in RF-KILL flows, since the interrupt 1233 * that enables radio won't fire on the correct irq, and the 1234 * driver won't be able to handle the interrupt. 1235 * Configure the IVAR table again after reset. 1236 */ 1237 iwl_pcie_conf_msix_hw(trans_pcie); 1238 1239 /* 1240 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1241 * This is a bug in certain verions of the hardware. 1242 * Certain devices also keep sending HW RF kill interrupt all 1243 * the time, unless the interrupt is ACKed even if the interrupt 1244 * should be masked. Re-ACK all the interrupts here. 1245 */ 1246 iwl_disable_interrupts(trans); 1247 1248 /* clear all status bits */ 1249 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1250 clear_bit(STATUS_INT_ENABLED, &trans->status); 1251 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1252 clear_bit(STATUS_RFKILL, &trans->status); 1253 1254 /* 1255 * Even if we stop the HW, we still want the RF kill 1256 * interrupt 1257 */ 1258 iwl_enable_rfkill_int(trans); 1259 1260 /* 1261 * Check again since the RF kill state may have changed while 1262 * all the interrupts were disabled, in this case we couldn't 1263 * receive the RF kill interrupt and update the state in the 1264 * op_mode. 1265 * Don't call the op_mode if the rkfill state hasn't changed. 1266 * This allows the op_mode to call stop_device from the rfkill 1267 * notification without endless recursion. Under very rare 1268 * circumstances, we might have a small recursion if the rfkill 1269 * state changed exactly now while we were called from stop_device. 1270 * This is very unlikely but can happen and is supported. 1271 */ 1272 hw_rfkill = iwl_is_rfkill_set(trans); 1273 if (hw_rfkill) 1274 set_bit(STATUS_RFKILL, &trans->status); 1275 else 1276 clear_bit(STATUS_RFKILL, &trans->status); 1277 if (hw_rfkill != was_hw_rfkill) 1278 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1279 1280 /* re-take ownership to prevent other users from stealing the device */ 1281 iwl_pcie_prepare_card_hw(trans); 1282 } 1283 1284 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1285 { 1286 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1287 1288 if (trans_pcie->msix_enabled) { 1289 int i; 1290 1291 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1292 synchronize_irq(trans_pcie->msix_entries[i].vector); 1293 } else { 1294 synchronize_irq(trans_pcie->pci_dev->irq); 1295 } 1296 } 1297 1298 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1299 const struct fw_img *fw, bool run_in_rfkill) 1300 { 1301 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1302 bool hw_rfkill; 1303 int ret; 1304 1305 /* This may fail if AMT took ownership of the device */ 1306 if (iwl_pcie_prepare_card_hw(trans)) { 1307 IWL_WARN(trans, "Exit HW not ready\n"); 1308 ret = -EIO; 1309 goto out; 1310 } 1311 1312 iwl_enable_rfkill_int(trans); 1313 1314 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1315 1316 /* 1317 * We enabled the RF-Kill interrupt and the handler may very 1318 * well be running. Disable the interrupts to make sure no other 1319 * interrupt can be fired. 1320 */ 1321 iwl_disable_interrupts(trans); 1322 1323 /* Make sure it finished running */ 1324 iwl_pcie_synchronize_irqs(trans); 1325 1326 mutex_lock(&trans_pcie->mutex); 1327 1328 /* If platform's RF_KILL switch is NOT set to KILL */ 1329 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1330 if (hw_rfkill && !run_in_rfkill) { 1331 ret = -ERFKILL; 1332 goto out; 1333 } 1334 1335 /* Someone called stop_device, don't try to start_fw */ 1336 if (trans_pcie->is_down) { 1337 IWL_WARN(trans, 1338 "Can't start_fw since the HW hasn't been started\n"); 1339 ret = -EIO; 1340 goto out; 1341 } 1342 1343 /* make sure rfkill handshake bits are cleared */ 1344 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1345 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1346 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1347 1348 /* clear (again), then enable host interrupts */ 1349 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1350 1351 ret = iwl_pcie_nic_init(trans); 1352 if (ret) { 1353 IWL_ERR(trans, "Unable to init nic\n"); 1354 goto out; 1355 } 1356 1357 /* 1358 * Now, we load the firmware and don't want to be interrupted, even 1359 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1360 * FH_TX interrupt which is needed to load the firmware). If the 1361 * RF-Kill switch is toggled, we will find out after having loaded 1362 * the firmware and return the proper value to the caller. 1363 */ 1364 iwl_enable_fw_load_int(trans); 1365 1366 /* really make sure rfkill handshake bits are cleared */ 1367 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1368 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1369 1370 /* Load the given image to the HW */ 1371 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1372 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1373 else 1374 ret = iwl_pcie_load_given_ucode(trans, fw); 1375 1376 /* re-check RF-Kill state since we may have missed the interrupt */ 1377 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1378 if (hw_rfkill && !run_in_rfkill) 1379 ret = -ERFKILL; 1380 1381 out: 1382 mutex_unlock(&trans_pcie->mutex); 1383 return ret; 1384 } 1385 1386 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1387 { 1388 iwl_pcie_reset_ict(trans); 1389 iwl_pcie_tx_start(trans, scd_addr); 1390 } 1391 1392 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1393 { 1394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1395 1396 mutex_lock(&trans_pcie->mutex); 1397 _iwl_trans_pcie_stop_device(trans, low_power); 1398 mutex_unlock(&trans_pcie->mutex); 1399 } 1400 1401 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1402 { 1403 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1404 IWL_TRANS_GET_PCIE_TRANS(trans); 1405 1406 lockdep_assert_held(&trans_pcie->mutex); 1407 1408 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1409 _iwl_trans_pcie_stop_device(trans, true); 1410 } 1411 1412 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1413 bool reset) 1414 { 1415 if (!reset) { 1416 /* Enable persistence mode to avoid reset */ 1417 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1418 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1419 } 1420 1421 iwl_disable_interrupts(trans); 1422 1423 /* 1424 * in testing mode, the host stays awake and the 1425 * hardware won't be reset (not even partially) 1426 */ 1427 if (test) 1428 return; 1429 1430 iwl_pcie_disable_ict(trans); 1431 1432 iwl_pcie_synchronize_irqs(trans); 1433 1434 iwl_clear_bit(trans, CSR_GP_CNTRL, 1435 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1436 iwl_clear_bit(trans, CSR_GP_CNTRL, 1437 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1438 1439 iwl_pcie_enable_rx_wake(trans, false); 1440 1441 if (reset) { 1442 /* 1443 * reset TX queues -- some of their registers reset during S3 1444 * so if we don't reset everything here the D3 image would try 1445 * to execute some invalid memory upon resume 1446 */ 1447 iwl_trans_pcie_tx_reset(trans); 1448 } 1449 1450 iwl_pcie_set_pwr(trans, true); 1451 } 1452 1453 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1454 enum iwl_d3_status *status, 1455 bool test, bool reset) 1456 { 1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1458 u32 val; 1459 int ret; 1460 1461 if (test) { 1462 iwl_enable_interrupts(trans); 1463 *status = IWL_D3_STATUS_ALIVE; 1464 return 0; 1465 } 1466 1467 iwl_pcie_enable_rx_wake(trans, true); 1468 1469 /* 1470 * Reconfigure IVAR table in case of MSIX or reset ict table in 1471 * MSI mode since HW reset erased it. 1472 * Also enables interrupts - none will happen as 1473 * the device doesn't know we're waking it up, only when 1474 * the opmode actually tells it after this call. 1475 */ 1476 iwl_pcie_conf_msix_hw(trans_pcie); 1477 if (!trans_pcie->msix_enabled) 1478 iwl_pcie_reset_ict(trans); 1479 iwl_enable_interrupts(trans); 1480 1481 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1482 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1483 1484 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1485 udelay(2); 1486 1487 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1488 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1489 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1490 25000); 1491 if (ret < 0) { 1492 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1493 return ret; 1494 } 1495 1496 iwl_pcie_set_pwr(trans, false); 1497 1498 if (!reset) { 1499 iwl_clear_bit(trans, CSR_GP_CNTRL, 1500 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1501 } else { 1502 iwl_trans_pcie_tx_reset(trans); 1503 1504 ret = iwl_pcie_rx_init(trans); 1505 if (ret) { 1506 IWL_ERR(trans, 1507 "Failed to resume the device (RX reset)\n"); 1508 return ret; 1509 } 1510 } 1511 1512 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1513 iwl_read_prph(trans, WFPM_GP2)); 1514 1515 val = iwl_read32(trans, CSR_RESET); 1516 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1517 *status = IWL_D3_STATUS_RESET; 1518 else 1519 *status = IWL_D3_STATUS_ALIVE; 1520 1521 return 0; 1522 } 1523 1524 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1525 struct iwl_trans *trans) 1526 { 1527 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1528 int max_irqs, num_irqs, i, ret, nr_online_cpus; 1529 u16 pci_cmd; 1530 1531 if (!trans->cfg->mq_rx_supported) 1532 goto enable_msi; 1533 1534 nr_online_cpus = num_online_cpus(); 1535 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 1536 for (i = 0; i < max_irqs; i++) 1537 trans_pcie->msix_entries[i].entry = i; 1538 1539 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1540 MSIX_MIN_INTERRUPT_VECTORS, 1541 max_irqs); 1542 if (num_irqs < 0) { 1543 IWL_DEBUG_INFO(trans, 1544 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1545 num_irqs); 1546 goto enable_msi; 1547 } 1548 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1549 1550 IWL_DEBUG_INFO(trans, 1551 "MSI-X enabled. %d interrupt vectors were allocated\n", 1552 num_irqs); 1553 1554 /* 1555 * In case the OS provides fewer interrupts than requested, different 1556 * causes will share the same interrupt vector as follows: 1557 * One interrupt less: non rx causes shared with FBQ. 1558 * Two interrupts less: non rx causes shared with FBQ and RSS. 1559 * More than two interrupts: we will use fewer RSS queues. 1560 */ 1561 if (num_irqs <= nr_online_cpus) { 1562 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1563 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1564 IWL_SHARED_IRQ_FIRST_RSS; 1565 } else if (num_irqs == nr_online_cpus + 1) { 1566 trans_pcie->trans->num_rx_queues = num_irqs; 1567 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1568 } else { 1569 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1570 } 1571 1572 trans_pcie->alloc_vecs = num_irqs; 1573 trans_pcie->msix_enabled = true; 1574 return; 1575 1576 enable_msi: 1577 ret = pci_enable_msi(pdev); 1578 if (ret) { 1579 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1580 /* enable rfkill interrupt: hw bug w/a */ 1581 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1582 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1583 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1584 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1585 } 1586 } 1587 } 1588 1589 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1590 { 1591 int iter_rx_q, i, ret, cpu, offset; 1592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1593 1594 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1595 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1596 offset = 1 + i; 1597 for (; i < iter_rx_q ; i++) { 1598 /* 1599 * Get the cpu prior to the place to search 1600 * (i.e. return will be > i - 1). 1601 */ 1602 cpu = cpumask_next(i - offset, cpu_online_mask); 1603 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1604 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1605 &trans_pcie->affinity_mask[i]); 1606 if (ret) 1607 IWL_ERR(trans_pcie->trans, 1608 "Failed to set affinity mask for IRQ %d\n", 1609 i); 1610 } 1611 } 1612 1613 static const char *queue_name(struct device *dev, 1614 struct iwl_trans_pcie *trans_p, int i) 1615 { 1616 if (trans_p->shared_vec_mask) { 1617 int vec = trans_p->shared_vec_mask & 1618 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1619 1620 if (i == 0) 1621 return DRV_NAME ": shared IRQ"; 1622 1623 return devm_kasprintf(dev, GFP_KERNEL, 1624 DRV_NAME ": queue %d", i + vec); 1625 } 1626 if (i == 0) 1627 return DRV_NAME ": default queue"; 1628 1629 if (i == trans_p->alloc_vecs - 1) 1630 return DRV_NAME ": exception"; 1631 1632 return devm_kasprintf(dev, GFP_KERNEL, 1633 DRV_NAME ": queue %d", i); 1634 } 1635 1636 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1637 struct iwl_trans_pcie *trans_pcie) 1638 { 1639 int i; 1640 1641 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1642 int ret; 1643 struct msix_entry *msix_entry; 1644 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1645 1646 if (!qname) 1647 return -ENOMEM; 1648 1649 msix_entry = &trans_pcie->msix_entries[i]; 1650 ret = devm_request_threaded_irq(&pdev->dev, 1651 msix_entry->vector, 1652 iwl_pcie_msix_isr, 1653 (i == trans_pcie->def_irq) ? 1654 iwl_pcie_irq_msix_handler : 1655 iwl_pcie_irq_rx_msix_handler, 1656 IRQF_SHARED, 1657 qname, 1658 msix_entry); 1659 if (ret) { 1660 IWL_ERR(trans_pcie->trans, 1661 "Error allocating IRQ %d\n", i); 1662 1663 return ret; 1664 } 1665 } 1666 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1667 1668 return 0; 1669 } 1670 1671 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1672 { 1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1674 int err; 1675 1676 lockdep_assert_held(&trans_pcie->mutex); 1677 1678 err = iwl_pcie_prepare_card_hw(trans); 1679 if (err) { 1680 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1681 return err; 1682 } 1683 1684 /* Reset the entire device */ 1685 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1686 usleep_range(1000, 2000); 1687 1688 iwl_pcie_apm_init(trans); 1689 1690 iwl_pcie_init_msix(trans_pcie); 1691 1692 /* From now on, the op_mode will be kept updated about RF kill state */ 1693 iwl_enable_rfkill_int(trans); 1694 1695 /* Set is_down to false here so that...*/ 1696 trans_pcie->is_down = false; 1697 1698 /* ...rfkill can call stop_device and set it false if needed */ 1699 iwl_trans_check_hw_rf_kill(trans); 1700 1701 /* Make sure we sync here, because we'll need full access later */ 1702 if (low_power) 1703 pm_runtime_resume(trans->dev); 1704 1705 return 0; 1706 } 1707 1708 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1709 { 1710 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1711 int ret; 1712 1713 mutex_lock(&trans_pcie->mutex); 1714 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1715 mutex_unlock(&trans_pcie->mutex); 1716 1717 return ret; 1718 } 1719 1720 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1721 { 1722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1723 1724 mutex_lock(&trans_pcie->mutex); 1725 1726 /* disable interrupts - don't enable HW RF kill interrupt */ 1727 iwl_disable_interrupts(trans); 1728 1729 iwl_pcie_apm_stop(trans, true); 1730 1731 iwl_disable_interrupts(trans); 1732 1733 iwl_pcie_disable_ict(trans); 1734 1735 mutex_unlock(&trans_pcie->mutex); 1736 1737 iwl_pcie_synchronize_irqs(trans); 1738 } 1739 1740 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1741 { 1742 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1743 } 1744 1745 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1746 { 1747 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1748 } 1749 1750 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1751 { 1752 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1753 } 1754 1755 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1756 { 1757 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1758 ((reg & 0x000FFFFF) | (3 << 24))); 1759 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1760 } 1761 1762 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1763 u32 val) 1764 { 1765 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1766 ((addr & 0x000FFFFF) | (3 << 24))); 1767 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1768 } 1769 1770 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1771 const struct iwl_trans_config *trans_cfg) 1772 { 1773 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1774 1775 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1776 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1777 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1778 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1779 trans_pcie->n_no_reclaim_cmds = 0; 1780 else 1781 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1782 if (trans_pcie->n_no_reclaim_cmds) 1783 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1784 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1785 1786 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1787 trans_pcie->rx_page_order = 1788 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1789 1790 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1791 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1792 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1793 1794 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1795 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1796 1797 trans->command_groups = trans_cfg->command_groups; 1798 trans->command_groups_size = trans_cfg->command_groups_size; 1799 1800 /* Initialize NAPI here - it should be before registering to mac80211 1801 * in the opmode but after the HW struct is allocated. 1802 * As this function may be called again in some corner cases don't 1803 * do anything if NAPI was already initialized. 1804 */ 1805 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1806 init_dummy_netdev(&trans_pcie->napi_dev); 1807 } 1808 1809 void iwl_trans_pcie_free(struct iwl_trans *trans) 1810 { 1811 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1812 int i; 1813 1814 iwl_pcie_synchronize_irqs(trans); 1815 1816 iwl_pcie_tx_free(trans); 1817 iwl_pcie_rx_free(trans); 1818 1819 if (trans_pcie->msix_enabled) { 1820 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1821 irq_set_affinity_hint( 1822 trans_pcie->msix_entries[i].vector, 1823 NULL); 1824 } 1825 1826 trans_pcie->msix_enabled = false; 1827 } else { 1828 iwl_pcie_free_ict(trans); 1829 } 1830 1831 iwl_pcie_free_fw_monitor(trans); 1832 1833 for_each_possible_cpu(i) { 1834 struct iwl_tso_hdr_page *p = 1835 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1836 1837 if (p->page) 1838 __free_page(p->page); 1839 } 1840 1841 free_percpu(trans_pcie->tso_hdr_page); 1842 mutex_destroy(&trans_pcie->mutex); 1843 iwl_trans_free(trans); 1844 } 1845 1846 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1847 { 1848 if (state) 1849 set_bit(STATUS_TPOWER_PMI, &trans->status); 1850 else 1851 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1852 } 1853 1854 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1855 unsigned long *flags) 1856 { 1857 int ret; 1858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1859 1860 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1861 1862 if (trans_pcie->cmd_hold_nic_awake) 1863 goto out; 1864 1865 /* this bit wakes up the NIC */ 1866 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1867 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1868 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1869 udelay(2); 1870 1871 /* 1872 * These bits say the device is running, and should keep running for 1873 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1874 * but they do not indicate that embedded SRAM is restored yet; 1875 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1876 * to/from host DRAM when sleeping/waking for power-saving. 1877 * Each direction takes approximately 1/4 millisecond; with this 1878 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1879 * series of register accesses are expected (e.g. reading Event Log), 1880 * to keep device from sleeping. 1881 * 1882 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1883 * SRAM is okay/restored. We don't check that here because this call 1884 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1885 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1886 * 1887 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1888 * and do not save/restore SRAM when power cycling. 1889 */ 1890 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1891 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1892 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1893 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1894 if (unlikely(ret < 0)) { 1895 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1896 WARN_ONCE(1, 1897 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1898 iwl_read32(trans, CSR_GP_CNTRL)); 1899 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1900 return false; 1901 } 1902 1903 out: 1904 /* 1905 * Fool sparse by faking we release the lock - sparse will 1906 * track nic_access anyway. 1907 */ 1908 __release(&trans_pcie->reg_lock); 1909 return true; 1910 } 1911 1912 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1913 unsigned long *flags) 1914 { 1915 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1916 1917 lockdep_assert_held(&trans_pcie->reg_lock); 1918 1919 /* 1920 * Fool sparse by faking we acquiring the lock - sparse will 1921 * track nic_access anyway. 1922 */ 1923 __acquire(&trans_pcie->reg_lock); 1924 1925 if (trans_pcie->cmd_hold_nic_awake) 1926 goto out; 1927 1928 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1929 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1930 /* 1931 * Above we read the CSR_GP_CNTRL register, which will flush 1932 * any previous writes, but we need the write that clears the 1933 * MAC_ACCESS_REQ bit to be performed before any other writes 1934 * scheduled on different CPUs (after we drop reg_lock). 1935 */ 1936 mmiowb(); 1937 out: 1938 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1939 } 1940 1941 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1942 void *buf, int dwords) 1943 { 1944 unsigned long flags; 1945 int offs, ret = 0; 1946 u32 *vals = buf; 1947 1948 if (iwl_trans_grab_nic_access(trans, &flags)) { 1949 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1950 for (offs = 0; offs < dwords; offs++) 1951 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1952 iwl_trans_release_nic_access(trans, &flags); 1953 } else { 1954 ret = -EBUSY; 1955 } 1956 return ret; 1957 } 1958 1959 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1960 const void *buf, int dwords) 1961 { 1962 unsigned long flags; 1963 int offs, ret = 0; 1964 const u32 *vals = buf; 1965 1966 if (iwl_trans_grab_nic_access(trans, &flags)) { 1967 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1968 for (offs = 0; offs < dwords; offs++) 1969 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1970 vals ? vals[offs] : 0); 1971 iwl_trans_release_nic_access(trans, &flags); 1972 } else { 1973 ret = -EBUSY; 1974 } 1975 return ret; 1976 } 1977 1978 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1979 unsigned long txqs, 1980 bool freeze) 1981 { 1982 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1983 int queue; 1984 1985 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1986 struct iwl_txq *txq = &trans_pcie->txq[queue]; 1987 unsigned long now; 1988 1989 spin_lock_bh(&txq->lock); 1990 1991 now = jiffies; 1992 1993 if (txq->frozen == freeze) 1994 goto next_queue; 1995 1996 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1997 freeze ? "Freezing" : "Waking", queue); 1998 1999 txq->frozen = freeze; 2000 2001 if (txq->read_ptr == txq->write_ptr) 2002 goto next_queue; 2003 2004 if (freeze) { 2005 if (unlikely(time_after(now, 2006 txq->stuck_timer.expires))) { 2007 /* 2008 * The timer should have fired, maybe it is 2009 * spinning right now on the lock. 2010 */ 2011 goto next_queue; 2012 } 2013 /* remember how long until the timer fires */ 2014 txq->frozen_expiry_remainder = 2015 txq->stuck_timer.expires - now; 2016 del_timer(&txq->stuck_timer); 2017 goto next_queue; 2018 } 2019 2020 /* 2021 * Wake a non-empty queue -> arm timer with the 2022 * remainder before it froze 2023 */ 2024 mod_timer(&txq->stuck_timer, 2025 now + txq->frozen_expiry_remainder); 2026 2027 next_queue: 2028 spin_unlock_bh(&txq->lock); 2029 } 2030 } 2031 2032 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2033 { 2034 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2035 int i; 2036 2037 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2038 struct iwl_txq *txq = &trans_pcie->txq[i]; 2039 2040 if (i == trans_pcie->cmd_queue) 2041 continue; 2042 2043 spin_lock_bh(&txq->lock); 2044 2045 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2046 txq->block--; 2047 if (!txq->block) { 2048 iwl_write32(trans, HBUS_TARG_WRPTR, 2049 txq->write_ptr | (i << 8)); 2050 } 2051 } else if (block) { 2052 txq->block++; 2053 } 2054 2055 spin_unlock_bh(&txq->lock); 2056 } 2057 } 2058 2059 #define IWL_FLUSH_WAIT_MS 2000 2060 2061 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2062 { 2063 u32 txq_id = txq->id; 2064 u32 status; 2065 bool active; 2066 u8 fifo; 2067 2068 if (trans->cfg->use_tfh) { 2069 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2070 txq->read_ptr, txq->write_ptr); 2071 /* TODO: access new SCD registers and dump them */ 2072 return; 2073 } 2074 2075 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2076 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2077 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2078 2079 IWL_ERR(trans, 2080 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2081 txq_id, active ? "" : "in", fifo, 2082 jiffies_to_msecs(txq->wd_timeout), 2083 txq->read_ptr, txq->write_ptr, 2084 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2085 (TFD_QUEUE_SIZE_MAX - 1), 2086 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2087 (TFD_QUEUE_SIZE_MAX - 1), 2088 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2089 } 2090 2091 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 2092 { 2093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2094 struct iwl_txq *txq; 2095 int cnt; 2096 unsigned long now = jiffies; 2097 int ret = 0; 2098 2099 /* waiting for all the tx frames complete might take a while */ 2100 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2101 u8 wr_ptr; 2102 2103 if (cnt == trans_pcie->cmd_queue) 2104 continue; 2105 if (!test_bit(cnt, trans_pcie->queue_used)) 2106 continue; 2107 if (!(BIT(cnt) & txq_bm)) 2108 continue; 2109 2110 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 2111 txq = &trans_pcie->txq[cnt]; 2112 wr_ptr = ACCESS_ONCE(txq->write_ptr); 2113 2114 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) && 2115 !time_after(jiffies, 2116 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2117 u8 write_ptr = ACCESS_ONCE(txq->write_ptr); 2118 2119 if (WARN_ONCE(wr_ptr != write_ptr, 2120 "WR pointer moved while flushing %d -> %d\n", 2121 wr_ptr, write_ptr)) 2122 return -ETIMEDOUT; 2123 usleep_range(1000, 2000); 2124 } 2125 2126 if (txq->read_ptr != txq->write_ptr) { 2127 IWL_ERR(trans, 2128 "fail to flush all tx fifo queues Q %d\n", cnt); 2129 ret = -ETIMEDOUT; 2130 break; 2131 } 2132 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 2133 } 2134 2135 if (ret) 2136 iwl_trans_pcie_log_scd_error(trans, txq); 2137 2138 return ret; 2139 } 2140 2141 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2142 u32 mask, u32 value) 2143 { 2144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2145 unsigned long flags; 2146 2147 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2148 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2149 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2150 } 2151 2152 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2153 { 2154 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2155 2156 if (iwlwifi_mod_params.d0i3_disable) 2157 return; 2158 2159 pm_runtime_get(&trans_pcie->pci_dev->dev); 2160 2161 #ifdef CONFIG_PM 2162 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2163 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2164 #endif /* CONFIG_PM */ 2165 } 2166 2167 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2168 { 2169 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2170 2171 if (iwlwifi_mod_params.d0i3_disable) 2172 return; 2173 2174 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2175 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2176 2177 #ifdef CONFIG_PM 2178 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2179 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2180 #endif /* CONFIG_PM */ 2181 } 2182 2183 static const char *get_csr_string(int cmd) 2184 { 2185 #define IWL_CMD(x) case x: return #x 2186 switch (cmd) { 2187 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2188 IWL_CMD(CSR_INT_COALESCING); 2189 IWL_CMD(CSR_INT); 2190 IWL_CMD(CSR_INT_MASK); 2191 IWL_CMD(CSR_FH_INT_STATUS); 2192 IWL_CMD(CSR_GPIO_IN); 2193 IWL_CMD(CSR_RESET); 2194 IWL_CMD(CSR_GP_CNTRL); 2195 IWL_CMD(CSR_HW_REV); 2196 IWL_CMD(CSR_EEPROM_REG); 2197 IWL_CMD(CSR_EEPROM_GP); 2198 IWL_CMD(CSR_OTP_GP_REG); 2199 IWL_CMD(CSR_GIO_REG); 2200 IWL_CMD(CSR_GP_UCODE_REG); 2201 IWL_CMD(CSR_GP_DRIVER_REG); 2202 IWL_CMD(CSR_UCODE_DRV_GP1); 2203 IWL_CMD(CSR_UCODE_DRV_GP2); 2204 IWL_CMD(CSR_LED_REG); 2205 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2206 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2207 IWL_CMD(CSR_ANA_PLL_CFG); 2208 IWL_CMD(CSR_HW_REV_WA_REG); 2209 IWL_CMD(CSR_MONITOR_STATUS_REG); 2210 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2211 default: 2212 return "UNKNOWN"; 2213 } 2214 #undef IWL_CMD 2215 } 2216 2217 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2218 { 2219 int i; 2220 static const u32 csr_tbl[] = { 2221 CSR_HW_IF_CONFIG_REG, 2222 CSR_INT_COALESCING, 2223 CSR_INT, 2224 CSR_INT_MASK, 2225 CSR_FH_INT_STATUS, 2226 CSR_GPIO_IN, 2227 CSR_RESET, 2228 CSR_GP_CNTRL, 2229 CSR_HW_REV, 2230 CSR_EEPROM_REG, 2231 CSR_EEPROM_GP, 2232 CSR_OTP_GP_REG, 2233 CSR_GIO_REG, 2234 CSR_GP_UCODE_REG, 2235 CSR_GP_DRIVER_REG, 2236 CSR_UCODE_DRV_GP1, 2237 CSR_UCODE_DRV_GP2, 2238 CSR_LED_REG, 2239 CSR_DRAM_INT_TBL_REG, 2240 CSR_GIO_CHICKEN_BITS, 2241 CSR_ANA_PLL_CFG, 2242 CSR_MONITOR_STATUS_REG, 2243 CSR_HW_REV_WA_REG, 2244 CSR_DBG_HPET_MEM_REG 2245 }; 2246 IWL_ERR(trans, "CSR values:\n"); 2247 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2248 "CSR_INT_PERIODIC_REG)\n"); 2249 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2250 IWL_ERR(trans, " %25s: 0X%08x\n", 2251 get_csr_string(csr_tbl[i]), 2252 iwl_read32(trans, csr_tbl[i])); 2253 } 2254 } 2255 2256 #ifdef CONFIG_IWLWIFI_DEBUGFS 2257 /* create and remove of files */ 2258 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2259 if (!debugfs_create_file(#name, mode, parent, trans, \ 2260 &iwl_dbgfs_##name##_ops)) \ 2261 goto err; \ 2262 } while (0) 2263 2264 /* file operation */ 2265 #define DEBUGFS_READ_FILE_OPS(name) \ 2266 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2267 .read = iwl_dbgfs_##name##_read, \ 2268 .open = simple_open, \ 2269 .llseek = generic_file_llseek, \ 2270 }; 2271 2272 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2273 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2274 .write = iwl_dbgfs_##name##_write, \ 2275 .open = simple_open, \ 2276 .llseek = generic_file_llseek, \ 2277 }; 2278 2279 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2280 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2281 .write = iwl_dbgfs_##name##_write, \ 2282 .read = iwl_dbgfs_##name##_read, \ 2283 .open = simple_open, \ 2284 .llseek = generic_file_llseek, \ 2285 }; 2286 2287 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2288 char __user *user_buf, 2289 size_t count, loff_t *ppos) 2290 { 2291 struct iwl_trans *trans = file->private_data; 2292 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2293 struct iwl_txq *txq; 2294 char *buf; 2295 int pos = 0; 2296 int cnt; 2297 int ret; 2298 size_t bufsz; 2299 2300 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2301 2302 if (!trans_pcie->txq) 2303 return -EAGAIN; 2304 2305 buf = kzalloc(bufsz, GFP_KERNEL); 2306 if (!buf) 2307 return -ENOMEM; 2308 2309 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2310 txq = &trans_pcie->txq[cnt]; 2311 pos += scnprintf(buf + pos, bufsz - pos, 2312 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2313 cnt, txq->read_ptr, txq->write_ptr, 2314 !!test_bit(cnt, trans_pcie->queue_used), 2315 !!test_bit(cnt, trans_pcie->queue_stopped), 2316 txq->need_update, txq->frozen, 2317 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2318 } 2319 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2320 kfree(buf); 2321 return ret; 2322 } 2323 2324 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2325 char __user *user_buf, 2326 size_t count, loff_t *ppos) 2327 { 2328 struct iwl_trans *trans = file->private_data; 2329 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2330 char *buf; 2331 int pos = 0, i, ret; 2332 size_t bufsz = sizeof(buf); 2333 2334 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2335 2336 if (!trans_pcie->rxq) 2337 return -EAGAIN; 2338 2339 buf = kzalloc(bufsz, GFP_KERNEL); 2340 if (!buf) 2341 return -ENOMEM; 2342 2343 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2344 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2345 2346 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2347 i); 2348 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2349 rxq->read); 2350 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2351 rxq->write); 2352 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2353 rxq->write_actual); 2354 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2355 rxq->need_update); 2356 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2357 rxq->free_count); 2358 if (rxq->rb_stts) { 2359 pos += scnprintf(buf + pos, bufsz - pos, 2360 "\tclosed_rb_num: %u\n", 2361 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2362 0x0FFF); 2363 } else { 2364 pos += scnprintf(buf + pos, bufsz - pos, 2365 "\tclosed_rb_num: Not Allocated\n"); 2366 } 2367 } 2368 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2369 kfree(buf); 2370 2371 return ret; 2372 } 2373 2374 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2375 char __user *user_buf, 2376 size_t count, loff_t *ppos) 2377 { 2378 struct iwl_trans *trans = file->private_data; 2379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2380 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2381 2382 int pos = 0; 2383 char *buf; 2384 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2385 ssize_t ret; 2386 2387 buf = kzalloc(bufsz, GFP_KERNEL); 2388 if (!buf) 2389 return -ENOMEM; 2390 2391 pos += scnprintf(buf + pos, bufsz - pos, 2392 "Interrupt Statistics Report:\n"); 2393 2394 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2395 isr_stats->hw); 2396 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2397 isr_stats->sw); 2398 if (isr_stats->sw || isr_stats->hw) { 2399 pos += scnprintf(buf + pos, bufsz - pos, 2400 "\tLast Restarting Code: 0x%X\n", 2401 isr_stats->err_code); 2402 } 2403 #ifdef CONFIG_IWLWIFI_DEBUG 2404 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2405 isr_stats->sch); 2406 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2407 isr_stats->alive); 2408 #endif 2409 pos += scnprintf(buf + pos, bufsz - pos, 2410 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2411 2412 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2413 isr_stats->ctkill); 2414 2415 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2416 isr_stats->wakeup); 2417 2418 pos += scnprintf(buf + pos, bufsz - pos, 2419 "Rx command responses:\t\t %u\n", isr_stats->rx); 2420 2421 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2422 isr_stats->tx); 2423 2424 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2425 isr_stats->unhandled); 2426 2427 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2428 kfree(buf); 2429 return ret; 2430 } 2431 2432 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2433 const char __user *user_buf, 2434 size_t count, loff_t *ppos) 2435 { 2436 struct iwl_trans *trans = file->private_data; 2437 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2438 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2439 2440 char buf[8]; 2441 int buf_size; 2442 u32 reset_flag; 2443 2444 memset(buf, 0, sizeof(buf)); 2445 buf_size = min(count, sizeof(buf) - 1); 2446 if (copy_from_user(buf, user_buf, buf_size)) 2447 return -EFAULT; 2448 if (sscanf(buf, "%x", &reset_flag) != 1) 2449 return -EFAULT; 2450 if (reset_flag == 0) 2451 memset(isr_stats, 0, sizeof(*isr_stats)); 2452 2453 return count; 2454 } 2455 2456 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2457 const char __user *user_buf, 2458 size_t count, loff_t *ppos) 2459 { 2460 struct iwl_trans *trans = file->private_data; 2461 char buf[8]; 2462 int buf_size; 2463 int csr; 2464 2465 memset(buf, 0, sizeof(buf)); 2466 buf_size = min(count, sizeof(buf) - 1); 2467 if (copy_from_user(buf, user_buf, buf_size)) 2468 return -EFAULT; 2469 if (sscanf(buf, "%d", &csr) != 1) 2470 return -EFAULT; 2471 2472 iwl_pcie_dump_csr(trans); 2473 2474 return count; 2475 } 2476 2477 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2478 char __user *user_buf, 2479 size_t count, loff_t *ppos) 2480 { 2481 struct iwl_trans *trans = file->private_data; 2482 char *buf = NULL; 2483 ssize_t ret; 2484 2485 ret = iwl_dump_fh(trans, &buf); 2486 if (ret < 0) 2487 return ret; 2488 if (!buf) 2489 return -EINVAL; 2490 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2491 kfree(buf); 2492 return ret; 2493 } 2494 2495 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2496 DEBUGFS_READ_FILE_OPS(fh_reg); 2497 DEBUGFS_READ_FILE_OPS(rx_queue); 2498 DEBUGFS_READ_FILE_OPS(tx_queue); 2499 DEBUGFS_WRITE_FILE_OPS(csr); 2500 2501 /* Create the debugfs files and directories */ 2502 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2503 { 2504 struct dentry *dir = trans->dbgfs_dir; 2505 2506 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2507 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2508 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2509 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2510 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2511 return 0; 2512 2513 err: 2514 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2515 return -ENOMEM; 2516 } 2517 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2518 2519 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2520 { 2521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2522 u32 cmdlen = 0; 2523 int i; 2524 2525 for (i = 0; i < trans_pcie->max_tbs; i++) 2526 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2527 2528 return cmdlen; 2529 } 2530 2531 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2532 struct iwl_fw_error_dump_data **data, 2533 int allocated_rb_nums) 2534 { 2535 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2536 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2537 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2538 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2539 u32 i, r, j, rb_len = 0; 2540 2541 spin_lock(&rxq->lock); 2542 2543 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2544 2545 for (i = rxq->read, j = 0; 2546 i != r && j < allocated_rb_nums; 2547 i = (i + 1) & RX_QUEUE_MASK, j++) { 2548 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2549 struct iwl_fw_error_dump_rb *rb; 2550 2551 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2552 DMA_FROM_DEVICE); 2553 2554 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2555 2556 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2557 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2558 rb = (void *)(*data)->data; 2559 rb->index = cpu_to_le32(i); 2560 memcpy(rb->data, page_address(rxb->page), max_len); 2561 /* remap the page for the free benefit */ 2562 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2563 max_len, 2564 DMA_FROM_DEVICE); 2565 2566 *data = iwl_fw_error_next_data(*data); 2567 } 2568 2569 spin_unlock(&rxq->lock); 2570 2571 return rb_len; 2572 } 2573 #define IWL_CSR_TO_DUMP (0x250) 2574 2575 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2576 struct iwl_fw_error_dump_data **data) 2577 { 2578 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2579 __le32 *val; 2580 int i; 2581 2582 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2583 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2584 val = (void *)(*data)->data; 2585 2586 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2587 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2588 2589 *data = iwl_fw_error_next_data(*data); 2590 2591 return csr_len; 2592 } 2593 2594 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2595 struct iwl_fw_error_dump_data **data) 2596 { 2597 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2598 unsigned long flags; 2599 __le32 *val; 2600 int i; 2601 2602 if (!iwl_trans_grab_nic_access(trans, &flags)) 2603 return 0; 2604 2605 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2606 (*data)->len = cpu_to_le32(fh_regs_len); 2607 val = (void *)(*data)->data; 2608 2609 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2610 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2611 2612 iwl_trans_release_nic_access(trans, &flags); 2613 2614 *data = iwl_fw_error_next_data(*data); 2615 2616 return sizeof(**data) + fh_regs_len; 2617 } 2618 2619 static u32 2620 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2621 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2622 u32 monitor_len) 2623 { 2624 u32 buf_size_in_dwords = (monitor_len >> 2); 2625 u32 *buffer = (u32 *)fw_mon_data->data; 2626 unsigned long flags; 2627 u32 i; 2628 2629 if (!iwl_trans_grab_nic_access(trans, &flags)) 2630 return 0; 2631 2632 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2633 for (i = 0; i < buf_size_in_dwords; i++) 2634 buffer[i] = iwl_read_prph_no_grab(trans, 2635 MON_DMARB_RD_DATA_ADDR); 2636 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2637 2638 iwl_trans_release_nic_access(trans, &flags); 2639 2640 return monitor_len; 2641 } 2642 2643 static u32 2644 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2645 struct iwl_fw_error_dump_data **data, 2646 u32 monitor_len) 2647 { 2648 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2649 u32 len = 0; 2650 2651 if ((trans_pcie->fw_mon_page && 2652 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2653 trans->dbg_dest_tlv) { 2654 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2655 u32 base, write_ptr, wrap_cnt; 2656 2657 /* If there was a dest TLV - use the values from there */ 2658 if (trans->dbg_dest_tlv) { 2659 write_ptr = 2660 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2661 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2662 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2663 } else { 2664 base = MON_BUFF_BASE_ADDR; 2665 write_ptr = MON_BUFF_WRPTR; 2666 wrap_cnt = MON_BUFF_CYCLE_CNT; 2667 } 2668 2669 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2670 fw_mon_data = (void *)(*data)->data; 2671 fw_mon_data->fw_mon_wr_ptr = 2672 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2673 fw_mon_data->fw_mon_cycle_cnt = 2674 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2675 fw_mon_data->fw_mon_base_ptr = 2676 cpu_to_le32(iwl_read_prph(trans, base)); 2677 2678 len += sizeof(**data) + sizeof(*fw_mon_data); 2679 if (trans_pcie->fw_mon_page) { 2680 /* 2681 * The firmware is now asserted, it won't write anything 2682 * to the buffer. CPU can take ownership to fetch the 2683 * data. The buffer will be handed back to the device 2684 * before the firmware will be restarted. 2685 */ 2686 dma_sync_single_for_cpu(trans->dev, 2687 trans_pcie->fw_mon_phys, 2688 trans_pcie->fw_mon_size, 2689 DMA_FROM_DEVICE); 2690 memcpy(fw_mon_data->data, 2691 page_address(trans_pcie->fw_mon_page), 2692 trans_pcie->fw_mon_size); 2693 2694 monitor_len = trans_pcie->fw_mon_size; 2695 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2696 /* 2697 * Update pointers to reflect actual values after 2698 * shifting 2699 */ 2700 base = iwl_read_prph(trans, base) << 2701 trans->dbg_dest_tlv->base_shift; 2702 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2703 monitor_len / sizeof(u32)); 2704 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2705 monitor_len = 2706 iwl_trans_pci_dump_marbh_monitor(trans, 2707 fw_mon_data, 2708 monitor_len); 2709 } else { 2710 /* Didn't match anything - output no monitor data */ 2711 monitor_len = 0; 2712 } 2713 2714 len += monitor_len; 2715 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2716 } 2717 2718 return len; 2719 } 2720 2721 static struct iwl_trans_dump_data 2722 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2723 const struct iwl_fw_dbg_trigger_tlv *trigger) 2724 { 2725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2726 struct iwl_fw_error_dump_data *data; 2727 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2728 struct iwl_fw_error_dump_txcmd *txcmd; 2729 struct iwl_trans_dump_data *dump_data; 2730 u32 len, num_rbs; 2731 u32 monitor_len; 2732 int i, ptr; 2733 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2734 !trans->cfg->mq_rx_supported; 2735 2736 /* transport dump header */ 2737 len = sizeof(*dump_data); 2738 2739 /* host commands */ 2740 len += sizeof(*data) + 2741 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2742 2743 /* FW monitor */ 2744 if (trans_pcie->fw_mon_page) { 2745 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2746 trans_pcie->fw_mon_size; 2747 monitor_len = trans_pcie->fw_mon_size; 2748 } else if (trans->dbg_dest_tlv) { 2749 u32 base, end; 2750 2751 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2752 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2753 2754 base = iwl_read_prph(trans, base) << 2755 trans->dbg_dest_tlv->base_shift; 2756 end = iwl_read_prph(trans, end) << 2757 trans->dbg_dest_tlv->end_shift; 2758 2759 /* Make "end" point to the actual end */ 2760 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2761 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2762 end += (1 << trans->dbg_dest_tlv->end_shift); 2763 monitor_len = end - base; 2764 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2765 monitor_len; 2766 } else { 2767 monitor_len = 0; 2768 } 2769 2770 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2771 dump_data = vzalloc(len); 2772 if (!dump_data) 2773 return NULL; 2774 2775 data = (void *)dump_data->data; 2776 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2777 dump_data->len = len; 2778 2779 return dump_data; 2780 } 2781 2782 /* CSR registers */ 2783 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2784 2785 /* FH registers */ 2786 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2787 2788 if (dump_rbs) { 2789 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2790 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2791 /* RBs */ 2792 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2793 & 0x0FFF; 2794 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2795 len += num_rbs * (sizeof(*data) + 2796 sizeof(struct iwl_fw_error_dump_rb) + 2797 (PAGE_SIZE << trans_pcie->rx_page_order)); 2798 } 2799 2800 dump_data = vzalloc(len); 2801 if (!dump_data) 2802 return NULL; 2803 2804 len = 0; 2805 data = (void *)dump_data->data; 2806 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2807 txcmd = (void *)data->data; 2808 spin_lock_bh(&cmdq->lock); 2809 ptr = cmdq->write_ptr; 2810 for (i = 0; i < cmdq->n_window; i++) { 2811 u8 idx = get_cmd_index(cmdq, ptr); 2812 u32 caplen, cmdlen; 2813 2814 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 2815 trans_pcie->tfd_size * ptr); 2816 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2817 2818 if (cmdlen) { 2819 len += sizeof(*txcmd) + caplen; 2820 txcmd->cmdlen = cpu_to_le32(cmdlen); 2821 txcmd->caplen = cpu_to_le32(caplen); 2822 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2823 txcmd = (void *)((u8 *)txcmd->data + caplen); 2824 } 2825 2826 ptr = iwl_queue_dec_wrap(ptr); 2827 } 2828 spin_unlock_bh(&cmdq->lock); 2829 2830 data->len = cpu_to_le32(len); 2831 len += sizeof(*data); 2832 data = iwl_fw_error_next_data(data); 2833 2834 len += iwl_trans_pcie_dump_csr(trans, &data); 2835 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2836 if (dump_rbs) 2837 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2838 2839 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2840 2841 dump_data->len = len; 2842 2843 return dump_data; 2844 } 2845 2846 #ifdef CONFIG_PM_SLEEP 2847 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2848 { 2849 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2850 return iwl_pci_fw_enter_d0i3(trans); 2851 2852 return 0; 2853 } 2854 2855 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2856 { 2857 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2858 iwl_pci_fw_exit_d0i3(trans); 2859 } 2860 #endif /* CONFIG_PM_SLEEP */ 2861 2862 #define IWL_TRANS_COMMON_OPS \ 2863 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 2864 .write8 = iwl_trans_pcie_write8, \ 2865 .write32 = iwl_trans_pcie_write32, \ 2866 .read32 = iwl_trans_pcie_read32, \ 2867 .read_prph = iwl_trans_pcie_read_prph, \ 2868 .write_prph = iwl_trans_pcie_write_prph, \ 2869 .read_mem = iwl_trans_pcie_read_mem, \ 2870 .write_mem = iwl_trans_pcie_write_mem, \ 2871 .configure = iwl_trans_pcie_configure, \ 2872 .set_pmi = iwl_trans_pcie_set_pmi, \ 2873 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 2874 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 2875 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 2876 .ref = iwl_trans_pcie_ref, \ 2877 .unref = iwl_trans_pcie_unref, \ 2878 .dump_data = iwl_trans_pcie_dump_data, \ 2879 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, \ 2880 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 2881 .d3_resume = iwl_trans_pcie_d3_resume 2882 2883 #ifdef CONFIG_PM_SLEEP 2884 #define IWL_TRANS_PM_OPS \ 2885 .suspend = iwl_trans_pcie_suspend, \ 2886 .resume = iwl_trans_pcie_resume, 2887 #else 2888 #define IWL_TRANS_PM_OPS 2889 #endif /* CONFIG_PM_SLEEP */ 2890 2891 static const struct iwl_trans_ops trans_ops_pcie = { 2892 IWL_TRANS_COMMON_OPS, 2893 IWL_TRANS_PM_OPS 2894 .start_hw = iwl_trans_pcie_start_hw, 2895 .fw_alive = iwl_trans_pcie_fw_alive, 2896 .start_fw = iwl_trans_pcie_start_fw, 2897 .stop_device = iwl_trans_pcie_stop_device, 2898 2899 .send_cmd = iwl_trans_pcie_send_hcmd, 2900 2901 .tx = iwl_trans_pcie_tx, 2902 .reclaim = iwl_trans_pcie_reclaim, 2903 2904 .txq_disable = iwl_trans_pcie_txq_disable, 2905 .txq_enable = iwl_trans_pcie_txq_enable, 2906 2907 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2908 2909 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2910 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2911 }; 2912 2913 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 2914 IWL_TRANS_COMMON_OPS, 2915 IWL_TRANS_PM_OPS 2916 .start_hw = iwl_trans_pcie_start_hw, 2917 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 2918 .start_fw = iwl_trans_pcie_gen2_start_fw, 2919 .stop_device = iwl_trans_pcie_stop_device, 2920 2921 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 2922 2923 .tx = iwl_trans_pcie_gen2_tx, 2924 .reclaim = iwl_trans_pcie_reclaim, 2925 2926 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 2927 .txq_free = iwl_trans_pcie_dyn_txq_free, 2928 2929 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2930 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2931 }; 2932 2933 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2934 const struct pci_device_id *ent, 2935 const struct iwl_cfg *cfg) 2936 { 2937 struct iwl_trans_pcie *trans_pcie; 2938 struct iwl_trans *trans; 2939 int ret, addr_size; 2940 2941 ret = pcim_enable_device(pdev); 2942 if (ret) 2943 return ERR_PTR(ret); 2944 2945 if (cfg->gen2) 2946 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2947 &pdev->dev, cfg, &trans_ops_pcie_gen2); 2948 else 2949 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2950 &pdev->dev, cfg, &trans_ops_pcie); 2951 if (!trans) 2952 return ERR_PTR(-ENOMEM); 2953 2954 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2955 2956 trans_pcie->trans = trans; 2957 spin_lock_init(&trans_pcie->irq_lock); 2958 spin_lock_init(&trans_pcie->reg_lock); 2959 mutex_init(&trans_pcie->mutex); 2960 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 2961 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 2962 if (!trans_pcie->tso_hdr_page) { 2963 ret = -ENOMEM; 2964 goto out_no_pci; 2965 } 2966 2967 2968 if (!cfg->base_params->pcie_l1_allowed) { 2969 /* 2970 * W/A - seems to solve weird behavior. We need to remove this 2971 * if we don't want to stay in L1 all the time. This wastes a 2972 * lot of power. 2973 */ 2974 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2975 PCIE_LINK_STATE_L1 | 2976 PCIE_LINK_STATE_CLKPM); 2977 } 2978 2979 if (cfg->use_tfh) { 2980 addr_size = 64; 2981 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 2982 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 2983 } else { 2984 addr_size = 36; 2985 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 2986 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 2987 } 2988 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 2989 2990 pci_set_master(pdev); 2991 2992 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2993 if (!ret) 2994 ret = pci_set_consistent_dma_mask(pdev, 2995 DMA_BIT_MASK(addr_size)); 2996 if (ret) { 2997 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2998 if (!ret) 2999 ret = pci_set_consistent_dma_mask(pdev, 3000 DMA_BIT_MASK(32)); 3001 /* both attempts failed: */ 3002 if (ret) { 3003 dev_err(&pdev->dev, "No suitable DMA available\n"); 3004 goto out_no_pci; 3005 } 3006 } 3007 3008 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3009 if (ret) { 3010 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3011 goto out_no_pci; 3012 } 3013 3014 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3015 if (!trans_pcie->hw_base) { 3016 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3017 ret = -ENODEV; 3018 goto out_no_pci; 3019 } 3020 3021 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3022 * PCI Tx retries from interfering with C3 CPU state */ 3023 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3024 3025 trans->dev = &pdev->dev; 3026 trans_pcie->pci_dev = pdev; 3027 iwl_disable_interrupts(trans); 3028 3029 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3030 /* 3031 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3032 * changed, and now the revision step also includes bit 0-1 (no more 3033 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3034 * in the old format. 3035 */ 3036 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 3037 unsigned long flags; 3038 3039 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3040 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3041 3042 ret = iwl_pcie_prepare_card_hw(trans); 3043 if (ret) { 3044 IWL_WARN(trans, "Exit HW not ready\n"); 3045 goto out_no_pci; 3046 } 3047 3048 /* 3049 * in-order to recognize C step driver should read chip version 3050 * id located at the AUX bus MISC address space. 3051 */ 3052 iwl_set_bit(trans, CSR_GP_CNTRL, 3053 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3054 udelay(2); 3055 3056 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3057 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3058 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3059 25000); 3060 if (ret < 0) { 3061 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3062 goto out_no_pci; 3063 } 3064 3065 if (iwl_trans_grab_nic_access(trans, &flags)) { 3066 u32 hw_step; 3067 3068 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3069 hw_step |= ENABLE_WFPM; 3070 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3071 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3072 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3073 if (hw_step == 0x3) 3074 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3075 (SILICON_C_STEP << 2); 3076 iwl_trans_release_nic_access(trans, &flags); 3077 } 3078 } 3079 3080 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3081 3082 iwl_pcie_set_interrupt_capa(pdev, trans); 3083 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3084 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3085 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3086 3087 /* Initialize the wait queue for commands */ 3088 init_waitqueue_head(&trans_pcie->wait_command_queue); 3089 3090 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3091 3092 if (trans_pcie->msix_enabled) { 3093 if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 3094 goto out_no_pci; 3095 } else { 3096 ret = iwl_pcie_alloc_ict(trans); 3097 if (ret) 3098 goto out_no_pci; 3099 3100 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3101 iwl_pcie_isr, 3102 iwl_pcie_irq_handler, 3103 IRQF_SHARED, DRV_NAME, trans); 3104 if (ret) { 3105 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3106 goto out_free_ict; 3107 } 3108 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3109 } 3110 3111 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3112 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3113 #else 3114 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3115 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3116 3117 return trans; 3118 3119 out_free_ict: 3120 iwl_pcie_free_ict(trans); 3121 out_no_pci: 3122 free_percpu(trans_pcie->tso_hdr_page); 3123 iwl_trans_free(trans); 3124 return ERR_PTR(ret); 3125 } 3126