1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "iwl-fw-error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92 { 93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94 95 if (!trans_pcie->fw_mon_page) 96 return; 97 98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100 __free_pages(trans_pcie->fw_mon_page, 101 get_order(trans_pcie->fw_mon_size)); 102 trans_pcie->fw_mon_page = NULL; 103 trans_pcie->fw_mon_phys = 0; 104 trans_pcie->fw_mon_size = 0; 105 } 106 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108 { 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110 struct page *page = NULL; 111 dma_addr_t phys; 112 u32 size = 0; 113 u8 power; 114 115 if (!max_power) { 116 /* default max_power is maximum */ 117 max_power = 26; 118 } else { 119 max_power += 11; 120 } 121 122 if (WARN(max_power > 26, 123 "External buffer size for monitor is too big %d, check the FW TLV\n", 124 max_power)) 125 return; 126 127 if (trans_pcie->fw_mon_page) { 128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129 trans_pcie->fw_mon_size, 130 DMA_FROM_DEVICE); 131 return; 132 } 133 134 phys = 0; 135 for (power = max_power; power >= 11; power--) { 136 int order; 137 138 size = BIT(power); 139 order = get_order(size); 140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141 order); 142 if (!page) 143 continue; 144 145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146 DMA_FROM_DEVICE); 147 if (dma_mapping_error(trans->dev, phys)) { 148 __free_pages(page, order); 149 page = NULL; 150 continue; 151 } 152 IWL_INFO(trans, 153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154 size, order); 155 break; 156 } 157 158 if (WARN_ON_ONCE(!page)) 159 return; 160 161 if (power != max_power) 162 IWL_ERR(trans, 163 "Sorry - debug buffer is only %luK while you requested %luK\n", 164 (unsigned long)BIT(power - 10), 165 (unsigned long)BIT(max_power - 10)); 166 167 trans_pcie->fw_mon_page = page; 168 trans_pcie->fw_mon_phys = phys; 169 trans_pcie->fw_mon_size = size; 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->cfg->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 static void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212 * Check if BIOS (or OS) enabled L1-ASPM on this device. 213 * If so (likely), disable L0S, so device moves directly L0->L1; 214 * costs negligible amount of power savings. 215 * If not (unlikely), enable L0S, so there is at least some 216 * power savings, even without L1. 217 */ 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221 else 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224 225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229 trans->ltr_enabled ? "En" : "Dis"); 230 } 231 232 /* 233 * Start up NIC's basic functionality after it has been reset 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235 * NOTE: This does not load uCode nor start the embedded processor 236 */ 237 static int iwl_pcie_apm_init(struct iwl_trans *trans) 238 { 239 int ret = 0; 240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 241 242 /* 243 * Use "set_bit" below rather than "write", to preserve any hardware 244 * bits already set by default after reset. 245 */ 246 247 /* Disable L0S exit timer (platform NMI Work/Around) */ 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 251 252 /* 253 * Disable L0s without affecting L1; 254 * don't wait for ICH L0s (ICH bug W/A) 255 */ 256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 258 259 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 261 262 /* 263 * Enable HAP INTA (interrupt from management bus) to 264 * wake device's PCI Express link L1a -> L0s 265 */ 266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 268 269 iwl_pcie_apm_config(trans); 270 271 /* Configure analog phase-lock-loop before activating to D0A */ 272 if (trans->cfg->base_params->pll_cfg) 273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 274 275 /* 276 * Set "initialization complete" bit to move adapter from 277 * D0U* --> D0A* (powered-up active) state. 278 */ 279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 280 281 /* 282 * Wait for clock stabilization; once stabilized, access to 283 * device-internal resources is supported, e.g. iwl_write_prph() 284 * and accesses to uCode SRAM. 285 */ 286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 289 if (ret < 0) { 290 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 291 goto out; 292 } 293 294 if (trans->cfg->host_interrupt_operation_mode) { 295 /* 296 * This is a bit of an abuse - This is needed for 7260 / 3160 297 * only check host_interrupt_operation_mode even if this is 298 * not related to host_interrupt_operation_mode. 299 * 300 * Enable the oscillator to count wake up time for L1 exit. This 301 * consumes slightly more power (100uA) - but allows to be sure 302 * that we wake up from L1 on time. 303 * 304 * This looks weird: read twice the same register, discard the 305 * value, set a bit, and yet again, read that same register 306 * just to discard the value. But that's the way the hardware 307 * seems to like it. 308 */ 309 iwl_read_prph(trans, OSC_CLK); 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 312 iwl_read_prph(trans, OSC_CLK); 313 iwl_read_prph(trans, OSC_CLK); 314 } 315 316 /* 317 * Enable DMA clock and wait for it to stabilize. 318 * 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 320 * bits do not disable clocks. This preserves any hardware 321 * bits already set by default in "CLK_CTRL_REG" after reset. 322 */ 323 if (!trans->cfg->apmg_not_supported) { 324 iwl_write_prph(trans, APMG_CLK_EN_REG, 325 APMG_CLK_VAL_DMA_CLK_RQT); 326 udelay(20); 327 328 /* Disable L1-Active */ 329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 331 332 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 334 APMG_RTC_INT_STT_RFKILL); 335 } 336 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 338 339 out: 340 return ret; 341 } 342 343 /* 344 * Enable LP XTAL to avoid HW bug where device may consume much power if 345 * FW is not loaded after device reset. LP XTAL is disabled by default 346 * after device HW reset. Do it only if XTAL is fed by internal source. 347 * Configure device's "persistence" mode to avoid resetting XTAL again when 348 * SHRD_HW_RST occurs in S3. 349 */ 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351 { 352 int ret; 353 u32 apmg_gp1_reg; 354 u32 apmg_xtal_cfg_reg; 355 u32 dl_cfg_reg; 356 357 /* Force XTAL ON */ 358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360 361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 363 usleep_range(1000, 2000); 364 365 /* 366 * Set "initialization complete" bit to move adapter from 367 * D0U* --> D0A* (powered-up active) state. 368 */ 369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 370 371 /* 372 * Wait for clock stabilization; once stabilized, access to 373 * device-internal resources is possible. 374 */ 375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378 25000); 379 if (WARN_ON(ret < 0)) { 380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 381 /* Release XTAL ON request */ 382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384 return; 385 } 386 387 /* 388 * Clear "disable persistence" to avoid LP XTAL resetting when 389 * SHRD_HW_RST is applied in S3. 390 */ 391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 392 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 393 394 /* 395 * Force APMG XTAL to be active to prevent its disabling by HW 396 * caused by APMG idle state. 397 */ 398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 399 SHR_APMG_XTAL_CFG_REG); 400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 401 apmg_xtal_cfg_reg | 402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 403 404 /* 405 * Reset entire device again - do controller reset (results in 406 * SHRD_HW_RST). Turn MAC off before proceeding. 407 */ 408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 409 usleep_range(1000, 2000); 410 411 /* Enable LP XTAL by indirect access through CSR */ 412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 414 SHR_APMG_GP1_WF_XTAL_LP_EN | 415 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 416 417 /* Clear delay line clock power up */ 418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 421 422 /* 423 * Enable persistence mode to avoid LP XTAL resetting when 424 * SHRD_HW_RST is applied in S3. 425 */ 426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 428 429 /* 430 * Clear "initialization complete" bit to move adapter from 431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 432 */ 433 iwl_clear_bit(trans, CSR_GP_CNTRL, 434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 435 436 /* Activates XTAL resources monitor */ 437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 438 CSR_MONITOR_XTAL_RESOURCES); 439 440 /* Release XTAL ON request */ 441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 443 udelay(10); 444 445 /* Release APMG XTAL */ 446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 447 apmg_xtal_cfg_reg & 448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 449 } 450 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 452 { 453 int ret = 0; 454 455 /* stop device's busmaster DMA activity */ 456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 457 458 ret = iwl_poll_bit(trans, CSR_RESET, 459 CSR_RESET_REG_FLAG_MASTER_DISABLED, 460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 461 if (ret < 0) 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 463 464 IWL_DEBUG_INFO(trans, "stop master\n"); 465 466 return ret; 467 } 468 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 470 { 471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 472 473 if (op_mode_leave) { 474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 475 iwl_pcie_apm_init(trans); 476 477 /* inform ME that we are leaving */ 478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 480 APMG_PCIDEV_STT_VAL_WAKE_ME); 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 483 CSR_RESET_LINK_PWR_MGMT_DISABLED); 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485 CSR_HW_IF_CONFIG_REG_PREPARE | 486 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 487 mdelay(1); 488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 489 CSR_RESET_LINK_PWR_MGMT_DISABLED); 490 } 491 mdelay(5); 492 } 493 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 495 496 /* Stop device's DMA activity */ 497 iwl_pcie_apm_stop_master(trans); 498 499 if (trans->cfg->lp_xtal_workaround) { 500 iwl_pcie_apm_lp_xtal_enable(trans); 501 return; 502 } 503 504 /* Reset the entire device */ 505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 506 usleep_range(1000, 2000); 507 508 /* 509 * Clear "initialization complete" bit to move adapter from 510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 511 */ 512 iwl_clear_bit(trans, CSR_GP_CNTRL, 513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 514 } 515 516 static int iwl_pcie_nic_init(struct iwl_trans *trans) 517 { 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 519 520 /* nic_init */ 521 spin_lock(&trans_pcie->irq_lock); 522 iwl_pcie_apm_init(trans); 523 524 spin_unlock(&trans_pcie->irq_lock); 525 526 iwl_pcie_set_pwr(trans, false); 527 528 iwl_op_mode_nic_config(trans->op_mode); 529 530 /* Allocate the RX queue, or reset if it is already allocated */ 531 iwl_pcie_rx_init(trans); 532 533 /* Allocate or reset and init all Tx and Command queues */ 534 if (iwl_pcie_tx_init(trans)) 535 return -ENOMEM; 536 537 if (trans->cfg->base_params->shadow_reg_enable) { 538 /* enable shadow regs in HW */ 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 541 } 542 543 return 0; 544 } 545 546 #define HW_READY_TIMEOUT (50) 547 548 /* Note: returns poll_bit return value, which is >= 0 if success */ 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 550 { 551 int ret; 552 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 555 556 /* See if we got it */ 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560 HW_READY_TIMEOUT); 561 562 if (ret >= 0) 563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 564 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 566 return ret; 567 } 568 569 /* Note: returns standard 0/-ERROR code */ 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 571 { 572 int ret; 573 int t = 0; 574 int iter; 575 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 577 578 ret = iwl_pcie_set_hw_ready(trans); 579 /* If the card is ready, exit 0 */ 580 if (ret >= 0) 581 return 0; 582 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 584 CSR_RESET_LINK_PWR_MGMT_DISABLED); 585 usleep_range(1000, 2000); 586 587 for (iter = 0; iter < 10; iter++) { 588 /* If HW is not ready, prepare the conditions to check again */ 589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 590 CSR_HW_IF_CONFIG_REG_PREPARE); 591 592 do { 593 ret = iwl_pcie_set_hw_ready(trans); 594 if (ret >= 0) 595 return 0; 596 597 usleep_range(200, 1000); 598 t += 200; 599 } while (t < 150000); 600 msleep(25); 601 } 602 603 IWL_ERR(trans, "Couldn't prepare the card\n"); 604 605 return ret; 606 } 607 608 /* 609 * ucode 610 */ 611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 612 u32 dst_addr, dma_addr_t phy_addr, 613 u32 byte_cnt) 614 { 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 617 618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 619 dst_addr); 620 621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 623 624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 625 (iwl_get_dma_hi_addr(phy_addr) 626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 627 628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 632 633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 637 } 638 639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans, 640 u32 dst_addr, dma_addr_t phy_addr, 641 u32 byte_cnt) 642 { 643 /* Stop DMA channel */ 644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0); 645 646 /* Configure SRAM address */ 647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR, 648 dst_addr); 649 650 /* Configure DRAM address - 64 bit */ 651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr); 652 653 /* Configure byte count to transfer */ 654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt); 655 656 /* Enable the DRAM2SRAM to start */ 657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP | 658 TFH_SRV_DMA_TO_DRIVER | 659 TFH_SRV_DMA_START); 660 } 661 662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 663 u32 dst_addr, dma_addr_t phy_addr, 664 u32 byte_cnt) 665 { 666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 667 unsigned long flags; 668 int ret; 669 670 trans_pcie->ucode_write_complete = false; 671 672 if (!iwl_trans_grab_nic_access(trans, &flags)) 673 return -EIO; 674 675 if (trans->cfg->use_tfh) 676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr, 677 byte_cnt); 678 else 679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 680 byte_cnt); 681 iwl_trans_release_nic_access(trans, &flags); 682 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 684 trans_pcie->ucode_write_complete, 5 * HZ); 685 if (!ret) { 686 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 687 return -ETIMEDOUT; 688 } 689 690 return 0; 691 } 692 693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 694 const struct fw_desc *section) 695 { 696 u8 *v_addr; 697 dma_addr_t p_addr; 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 699 int ret = 0; 700 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 702 section_num); 703 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 705 GFP_KERNEL | __GFP_NOWARN); 706 if (!v_addr) { 707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 708 chunk_sz = PAGE_SIZE; 709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 710 &p_addr, GFP_KERNEL); 711 if (!v_addr) 712 return -ENOMEM; 713 } 714 715 for (offset = 0; offset < section->len; offset += chunk_sz) { 716 u32 copy_size, dst_addr; 717 bool extended_addr = false; 718 719 copy_size = min_t(u32, chunk_sz, section->len - offset); 720 dst_addr = section->offset + offset; 721 722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 723 dst_addr <= IWL_FW_MEM_EXTENDED_END) 724 extended_addr = true; 725 726 if (extended_addr) 727 iwl_set_bits_prph(trans, LMPM_CHICK, 728 LMPM_CHICK_EXTENDED_ADDR_SPACE); 729 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 732 copy_size); 733 734 if (extended_addr) 735 iwl_clear_bits_prph(trans, LMPM_CHICK, 736 LMPM_CHICK_EXTENDED_ADDR_SPACE); 737 738 if (ret) { 739 IWL_ERR(trans, 740 "Could not load the [%d] uCode section\n", 741 section_num); 742 break; 743 } 744 } 745 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 747 return ret; 748 } 749 750 /* 751 * Driver Takes the ownership on secure machine before FW load 752 * and prevent race with the BT load. 753 * W/A for ROM bug. (should be remove in the next Si step) 754 */ 755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 756 { 757 u32 val, loop = 1000; 758 759 /* 760 * Check the RSA semaphore is accessible. 761 * If the HW isn't locked and the rsa semaphore isn't accessible, 762 * we are in trouble. 763 */ 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 765 if (val & (BIT(1) | BIT(17))) { 766 IWL_DEBUG_INFO(trans, 767 "can't access the RSA semaphore it is write protected\n"); 768 return 0; 769 } 770 771 /* take ownership on the AUX IF */ 772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 774 775 do { 776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 778 if (val == 0x1) { 779 iwl_write_prph(trans, RSA_ENABLE, 0); 780 return 0; 781 } 782 783 udelay(10); 784 loop--; 785 } while (loop > 0); 786 787 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 788 return -EIO; 789 } 790 791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 792 const struct fw_img *image, 793 int cpu, 794 int *first_ucode_section) 795 { 796 int shift_param; 797 int i, ret = 0, sec_num = 0x1; 798 u32 val, last_read_idx = 0; 799 800 if (cpu == 1) { 801 shift_param = 0; 802 *first_ucode_section = 0; 803 } else { 804 shift_param = 16; 805 (*first_ucode_section)++; 806 } 807 808 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 809 last_read_idx = i; 810 811 /* 812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 813 * CPU1 to CPU2. 814 * PAGING_SEPARATOR_SECTION delimiter - separate between 815 * CPU2 non paged to CPU2 paging sec. 816 */ 817 if (!image->sec[i].data || 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 820 IWL_DEBUG_FW(trans, 821 "Break since Data not valid or Empty section, sec = %d\n", 822 i); 823 break; 824 } 825 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 827 if (ret) 828 return ret; 829 830 /* Notify the ucode of the loaded section number and status */ 831 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 832 val = val | (sec_num << shift_param); 833 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 834 sec_num = (sec_num << 1) | 0x1; 835 } 836 837 *first_ucode_section = last_read_idx; 838 839 iwl_enable_interrupts(trans); 840 841 if (cpu == 1) 842 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); 843 else 844 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 845 846 return 0; 847 } 848 849 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 850 const struct fw_img *image, 851 int cpu, 852 int *first_ucode_section) 853 { 854 int shift_param; 855 int i, ret = 0; 856 u32 last_read_idx = 0; 857 858 if (cpu == 1) { 859 shift_param = 0; 860 *first_ucode_section = 0; 861 } else { 862 shift_param = 16; 863 (*first_ucode_section)++; 864 } 865 866 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 867 last_read_idx = i; 868 869 /* 870 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 871 * CPU1 to CPU2. 872 * PAGING_SEPARATOR_SECTION delimiter - separate between 873 * CPU2 non paged to CPU2 paging sec. 874 */ 875 if (!image->sec[i].data || 876 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 877 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 878 IWL_DEBUG_FW(trans, 879 "Break since Data not valid or Empty section, sec = %d\n", 880 i); 881 break; 882 } 883 884 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 885 if (ret) 886 return ret; 887 } 888 889 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 890 iwl_set_bits_prph(trans, 891 CSR_UCODE_LOAD_STATUS_ADDR, 892 (LMPM_CPU_UCODE_LOADING_COMPLETED | 893 LMPM_CPU_HDRS_LOADING_COMPLETED | 894 LMPM_CPU_UCODE_LOADING_STARTED) << 895 shift_param); 896 897 *first_ucode_section = last_read_idx; 898 899 return 0; 900 } 901 902 static void iwl_pcie_apply_destination(struct iwl_trans *trans) 903 { 904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 905 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 906 int i; 907 908 if (dest->version) 909 IWL_ERR(trans, 910 "DBG DEST version is %d - expect issues\n", 911 dest->version); 912 913 IWL_INFO(trans, "Applying debug destination %s\n", 914 get_fw_dbg_mode_string(dest->monitor_mode)); 915 916 if (dest->monitor_mode == EXTERNAL_MODE) 917 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 918 else 919 IWL_WARN(trans, "PCI should have external buffer debug\n"); 920 921 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 922 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 923 u32 val = le32_to_cpu(dest->reg_ops[i].val); 924 925 switch (dest->reg_ops[i].op) { 926 case CSR_ASSIGN: 927 iwl_write32(trans, addr, val); 928 break; 929 case CSR_SETBIT: 930 iwl_set_bit(trans, addr, BIT(val)); 931 break; 932 case CSR_CLEARBIT: 933 iwl_clear_bit(trans, addr, BIT(val)); 934 break; 935 case PRPH_ASSIGN: 936 iwl_write_prph(trans, addr, val); 937 break; 938 case PRPH_SETBIT: 939 iwl_set_bits_prph(trans, addr, BIT(val)); 940 break; 941 case PRPH_CLEARBIT: 942 iwl_clear_bits_prph(trans, addr, BIT(val)); 943 break; 944 case PRPH_BLOCKBIT: 945 if (iwl_read_prph(trans, addr) & BIT(val)) { 946 IWL_ERR(trans, 947 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 948 val, addr); 949 goto monitor; 950 } 951 break; 952 default: 953 IWL_ERR(trans, "FW debug - unknown OP %d\n", 954 dest->reg_ops[i].op); 955 break; 956 } 957 } 958 959 monitor: 960 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 961 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 962 trans_pcie->fw_mon_phys >> dest->base_shift); 963 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 964 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 965 (trans_pcie->fw_mon_phys + 966 trans_pcie->fw_mon_size - 256) >> 967 dest->end_shift); 968 else 969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 970 (trans_pcie->fw_mon_phys + 971 trans_pcie->fw_mon_size) >> 972 dest->end_shift); 973 } 974 } 975 976 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 977 const struct fw_img *image) 978 { 979 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 980 int ret = 0; 981 int first_ucode_section; 982 983 IWL_DEBUG_FW(trans, "working with %s CPU\n", 984 image->is_dual_cpus ? "Dual" : "Single"); 985 986 /* load to FW the binary non secured sections of CPU1 */ 987 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 988 if (ret) 989 return ret; 990 991 if (image->is_dual_cpus) { 992 /* set CPU2 header address */ 993 iwl_write_prph(trans, 994 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 995 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 996 997 /* load to FW the binary sections of CPU2 */ 998 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 999 &first_ucode_section); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 /* supported for 7000 only for the moment */ 1005 if (iwlwifi_mod_params.fw_monitor && 1006 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1007 iwl_pcie_alloc_fw_monitor(trans, 0); 1008 1009 if (trans_pcie->fw_mon_size) { 1010 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1011 trans_pcie->fw_mon_phys >> 4); 1012 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1013 (trans_pcie->fw_mon_phys + 1014 trans_pcie->fw_mon_size) >> 4); 1015 } 1016 } else if (trans->dbg_dest_tlv) { 1017 iwl_pcie_apply_destination(trans); 1018 } 1019 1020 iwl_enable_interrupts(trans); 1021 1022 /* release CPU reset */ 1023 iwl_write32(trans, CSR_RESET, 0); 1024 1025 return 0; 1026 } 1027 1028 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1029 const struct fw_img *image) 1030 { 1031 int ret = 0; 1032 int first_ucode_section; 1033 1034 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1035 image->is_dual_cpus ? "Dual" : "Single"); 1036 1037 if (trans->dbg_dest_tlv) 1038 iwl_pcie_apply_destination(trans); 1039 1040 /* TODO: remove in the next Si step */ 1041 ret = iwl_pcie_rsa_race_bug_wa(trans); 1042 if (ret) 1043 return ret; 1044 1045 /* configure the ucode to be ready to get the secured image */ 1046 /* release CPU reset */ 1047 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1048 1049 /* load to FW the binary Secured sections of CPU1 */ 1050 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1051 &first_ucode_section); 1052 if (ret) 1053 return ret; 1054 1055 /* load to FW the binary sections of CPU2 */ 1056 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1057 &first_ucode_section); 1058 } 1059 1060 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1061 { 1062 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1063 bool hw_rfkill, was_hw_rfkill; 1064 1065 lockdep_assert_held(&trans_pcie->mutex); 1066 1067 if (trans_pcie->is_down) 1068 return; 1069 1070 trans_pcie->is_down = true; 1071 1072 was_hw_rfkill = iwl_is_rfkill_set(trans); 1073 1074 /* tell the device to stop sending interrupts */ 1075 iwl_disable_interrupts(trans); 1076 1077 /* device going down, Stop using ICT table */ 1078 iwl_pcie_disable_ict(trans); 1079 1080 /* 1081 * If a HW restart happens during firmware loading, 1082 * then the firmware loading might call this function 1083 * and later it might be called again due to the 1084 * restart. So don't process again if the device is 1085 * already dead. 1086 */ 1087 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1088 IWL_DEBUG_INFO(trans, 1089 "DEVICE_ENABLED bit was set and is now cleared\n"); 1090 iwl_pcie_tx_stop(trans); 1091 iwl_pcie_rx_stop(trans); 1092 1093 /* Power-down device's busmaster DMA clocks */ 1094 if (!trans->cfg->apmg_not_supported) { 1095 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1096 APMG_CLK_VAL_DMA_CLK_RQT); 1097 udelay(5); 1098 } 1099 } 1100 1101 /* Make sure (redundant) we've released our request to stay awake */ 1102 iwl_clear_bit(trans, CSR_GP_CNTRL, 1103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1104 1105 /* Stop the device, and put it in low power state */ 1106 iwl_pcie_apm_stop(trans, false); 1107 1108 /* stop and reset the on-board processor */ 1109 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1110 usleep_range(1000, 2000); 1111 1112 /* 1113 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1114 * This is a bug in certain verions of the hardware. 1115 * Certain devices also keep sending HW RF kill interrupt all 1116 * the time, unless the interrupt is ACKed even if the interrupt 1117 * should be masked. Re-ACK all the interrupts here. 1118 */ 1119 iwl_disable_interrupts(trans); 1120 1121 /* clear all status bits */ 1122 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1123 clear_bit(STATUS_INT_ENABLED, &trans->status); 1124 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1125 clear_bit(STATUS_RFKILL, &trans->status); 1126 1127 /* 1128 * Even if we stop the HW, we still want the RF kill 1129 * interrupt 1130 */ 1131 iwl_enable_rfkill_int(trans); 1132 1133 /* 1134 * Check again since the RF kill state may have changed while 1135 * all the interrupts were disabled, in this case we couldn't 1136 * receive the RF kill interrupt and update the state in the 1137 * op_mode. 1138 * Don't call the op_mode if the rkfill state hasn't changed. 1139 * This allows the op_mode to call stop_device from the rfkill 1140 * notification without endless recursion. Under very rare 1141 * circumstances, we might have a small recursion if the rfkill 1142 * state changed exactly now while we were called from stop_device. 1143 * This is very unlikely but can happen and is supported. 1144 */ 1145 hw_rfkill = iwl_is_rfkill_set(trans); 1146 if (hw_rfkill) 1147 set_bit(STATUS_RFKILL, &trans->status); 1148 else 1149 clear_bit(STATUS_RFKILL, &trans->status); 1150 if (hw_rfkill != was_hw_rfkill) 1151 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1152 1153 /* re-take ownership to prevent other users from stealing the device */ 1154 iwl_pcie_prepare_card_hw(trans); 1155 } 1156 1157 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1158 { 1159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1160 1161 if (trans_pcie->msix_enabled) { 1162 int i; 1163 1164 for (i = 0; i < trans_pcie->allocated_vector; i++) 1165 synchronize_irq(trans_pcie->msix_entries[i].vector); 1166 } else { 1167 synchronize_irq(trans_pcie->pci_dev->irq); 1168 } 1169 } 1170 1171 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1172 const struct fw_img *fw, bool run_in_rfkill) 1173 { 1174 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1175 bool hw_rfkill; 1176 int ret; 1177 1178 /* This may fail if AMT took ownership of the device */ 1179 if (iwl_pcie_prepare_card_hw(trans)) { 1180 IWL_WARN(trans, "Exit HW not ready\n"); 1181 ret = -EIO; 1182 goto out; 1183 } 1184 1185 iwl_enable_rfkill_int(trans); 1186 1187 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1188 1189 /* 1190 * We enabled the RF-Kill interrupt and the handler may very 1191 * well be running. Disable the interrupts to make sure no other 1192 * interrupt can be fired. 1193 */ 1194 iwl_disable_interrupts(trans); 1195 1196 /* Make sure it finished running */ 1197 iwl_pcie_synchronize_irqs(trans); 1198 1199 mutex_lock(&trans_pcie->mutex); 1200 1201 /* If platform's RF_KILL switch is NOT set to KILL */ 1202 hw_rfkill = iwl_is_rfkill_set(trans); 1203 if (hw_rfkill) 1204 set_bit(STATUS_RFKILL, &trans->status); 1205 else 1206 clear_bit(STATUS_RFKILL, &trans->status); 1207 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1208 if (hw_rfkill && !run_in_rfkill) { 1209 ret = -ERFKILL; 1210 goto out; 1211 } 1212 1213 /* Someone called stop_device, don't try to start_fw */ 1214 if (trans_pcie->is_down) { 1215 IWL_WARN(trans, 1216 "Can't start_fw since the HW hasn't been started\n"); 1217 ret = -EIO; 1218 goto out; 1219 } 1220 1221 /* make sure rfkill handshake bits are cleared */ 1222 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1223 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1224 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1225 1226 /* clear (again), then enable host interrupts */ 1227 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1228 1229 ret = iwl_pcie_nic_init(trans); 1230 if (ret) { 1231 IWL_ERR(trans, "Unable to init nic\n"); 1232 goto out; 1233 } 1234 1235 /* 1236 * Now, we load the firmware and don't want to be interrupted, even 1237 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1238 * FH_TX interrupt which is needed to load the firmware). If the 1239 * RF-Kill switch is toggled, we will find out after having loaded 1240 * the firmware and return the proper value to the caller. 1241 */ 1242 iwl_enable_fw_load_int(trans); 1243 1244 /* really make sure rfkill handshake bits are cleared */ 1245 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1246 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1247 1248 /* Load the given image to the HW */ 1249 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1250 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1251 else 1252 ret = iwl_pcie_load_given_ucode(trans, fw); 1253 1254 /* re-check RF-Kill state since we may have missed the interrupt */ 1255 hw_rfkill = iwl_is_rfkill_set(trans); 1256 if (hw_rfkill) 1257 set_bit(STATUS_RFKILL, &trans->status); 1258 else 1259 clear_bit(STATUS_RFKILL, &trans->status); 1260 1261 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1262 if (hw_rfkill && !run_in_rfkill) 1263 ret = -ERFKILL; 1264 1265 out: 1266 mutex_unlock(&trans_pcie->mutex); 1267 return ret; 1268 } 1269 1270 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1271 { 1272 iwl_pcie_reset_ict(trans); 1273 iwl_pcie_tx_start(trans, scd_addr); 1274 } 1275 1276 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1277 { 1278 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1279 1280 mutex_lock(&trans_pcie->mutex); 1281 _iwl_trans_pcie_stop_device(trans, low_power); 1282 mutex_unlock(&trans_pcie->mutex); 1283 } 1284 1285 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1286 { 1287 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1288 IWL_TRANS_GET_PCIE_TRANS(trans); 1289 1290 lockdep_assert_held(&trans_pcie->mutex); 1291 1292 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1293 _iwl_trans_pcie_stop_device(trans, true); 1294 } 1295 1296 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1297 bool reset) 1298 { 1299 if (!reset) { 1300 /* Enable persistence mode to avoid reset */ 1301 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1302 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1303 } 1304 1305 iwl_disable_interrupts(trans); 1306 1307 /* 1308 * in testing mode, the host stays awake and the 1309 * hardware won't be reset (not even partially) 1310 */ 1311 if (test) 1312 return; 1313 1314 iwl_pcie_disable_ict(trans); 1315 1316 iwl_pcie_synchronize_irqs(trans); 1317 1318 iwl_clear_bit(trans, CSR_GP_CNTRL, 1319 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1320 iwl_clear_bit(trans, CSR_GP_CNTRL, 1321 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1322 1323 iwl_pcie_enable_rx_wake(trans, false); 1324 1325 if (reset) { 1326 /* 1327 * reset TX queues -- some of their registers reset during S3 1328 * so if we don't reset everything here the D3 image would try 1329 * to execute some invalid memory upon resume 1330 */ 1331 iwl_trans_pcie_tx_reset(trans); 1332 } 1333 1334 iwl_pcie_set_pwr(trans, true); 1335 } 1336 1337 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1338 enum iwl_d3_status *status, 1339 bool test, bool reset) 1340 { 1341 u32 val; 1342 int ret; 1343 1344 if (test) { 1345 iwl_enable_interrupts(trans); 1346 *status = IWL_D3_STATUS_ALIVE; 1347 return 0; 1348 } 1349 1350 iwl_pcie_enable_rx_wake(trans, true); 1351 1352 /* 1353 * Also enables interrupts - none will happen as the device doesn't 1354 * know we're waking it up, only when the opmode actually tells it 1355 * after this call. 1356 */ 1357 iwl_pcie_reset_ict(trans); 1358 iwl_enable_interrupts(trans); 1359 1360 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1361 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1362 1363 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1364 udelay(2); 1365 1366 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1367 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1368 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1369 25000); 1370 if (ret < 0) { 1371 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1372 return ret; 1373 } 1374 1375 iwl_pcie_set_pwr(trans, false); 1376 1377 if (!reset) { 1378 iwl_clear_bit(trans, CSR_GP_CNTRL, 1379 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1380 } else { 1381 iwl_trans_pcie_tx_reset(trans); 1382 1383 ret = iwl_pcie_rx_init(trans); 1384 if (ret) { 1385 IWL_ERR(trans, 1386 "Failed to resume the device (RX reset)\n"); 1387 return ret; 1388 } 1389 } 1390 1391 val = iwl_read32(trans, CSR_RESET); 1392 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1393 *status = IWL_D3_STATUS_RESET; 1394 else 1395 *status = IWL_D3_STATUS_ALIVE; 1396 1397 return 0; 1398 } 1399 1400 struct iwl_causes_list { 1401 u32 cause_num; 1402 u32 mask_reg; 1403 u8 addr; 1404 }; 1405 1406 static struct iwl_causes_list causes_list[] = { 1407 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1408 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1409 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1410 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1411 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1412 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1413 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1414 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1415 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1416 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1417 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1418 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1419 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1420 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1421 }; 1422 1423 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1424 { 1425 u32 val, max_rx_vector, i; 1426 struct iwl_trans *trans = trans_pcie->trans; 1427 1428 max_rx_vector = trans_pcie->allocated_vector - 1; 1429 1430 if (!trans_pcie->msix_enabled) { 1431 if (trans->cfg->mq_rx_supported) 1432 iwl_write_prph(trans, UREG_CHICK, 1433 UREG_CHICK_MSI_ENABLE); 1434 return; 1435 } 1436 1437 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1438 1439 /* 1440 * Each cause from the list above and the RX causes is represented as 1441 * a byte in the IVAR table. We access the first (N - 1) bytes and map 1442 * them to the (N - 1) vectors so these vectors will be used as rx 1443 * vectors. Then access all non rx causes and map them to the 1444 * default queue (N'th queue). 1445 */ 1446 for (i = 0; i < max_rx_vector; i++) { 1447 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i)); 1448 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD, 1449 BIT(MSIX_FH_INT_CAUSES_Q(i))); 1450 } 1451 1452 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1453 val = trans_pcie->default_irq_num | 1454 MSIX_NON_AUTO_CLEAR_CAUSE; 1455 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1456 iwl_clear_bit(trans, causes_list[i].mask_reg, 1457 causes_list[i].cause_num); 1458 } 1459 trans_pcie->fh_init_mask = 1460 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1461 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1462 trans_pcie->hw_init_mask = 1463 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1464 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1465 } 1466 1467 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1468 struct iwl_trans *trans) 1469 { 1470 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1471 u16 pci_cmd; 1472 int max_vector; 1473 int ret, i; 1474 1475 if (trans->cfg->mq_rx_supported) { 1476 max_vector = min_t(u32, (num_possible_cpus() + 2), 1477 IWL_MAX_RX_HW_QUEUES); 1478 for (i = 0; i < max_vector; i++) 1479 trans_pcie->msix_entries[i].entry = i; 1480 1481 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1482 MSIX_MIN_INTERRUPT_VECTORS, 1483 max_vector); 1484 if (ret > 1) { 1485 IWL_DEBUG_INFO(trans, 1486 "Enable MSI-X allocate %d interrupt vector\n", 1487 ret); 1488 trans_pcie->allocated_vector = ret; 1489 trans_pcie->default_irq_num = 1490 trans_pcie->allocated_vector - 1; 1491 trans_pcie->trans->num_rx_queues = 1492 trans_pcie->allocated_vector - 1; 1493 trans_pcie->msix_enabled = true; 1494 1495 return; 1496 } 1497 IWL_DEBUG_INFO(trans, 1498 "ret = %d %s move to msi mode\n", ret, 1499 (ret == 1) ? 1500 "can't allocate more than 1 interrupt vector" : 1501 "failed to enable msi-x mode"); 1502 pci_disable_msix(pdev); 1503 } 1504 1505 ret = pci_enable_msi(pdev); 1506 if (ret) { 1507 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1508 /* enable rfkill interrupt: hw bug w/a */ 1509 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1510 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1511 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1512 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1513 } 1514 } 1515 } 1516 1517 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1518 struct iwl_trans_pcie *trans_pcie) 1519 { 1520 int i, last_vector; 1521 1522 last_vector = trans_pcie->trans->num_rx_queues; 1523 1524 for (i = 0; i < trans_pcie->allocated_vector; i++) { 1525 int ret; 1526 1527 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector, 1528 iwl_pcie_msix_isr, 1529 (i == last_vector) ? 1530 iwl_pcie_irq_msix_handler : 1531 iwl_pcie_irq_rx_msix_handler, 1532 IRQF_SHARED, 1533 DRV_NAME, 1534 &trans_pcie->msix_entries[i]); 1535 if (ret) { 1536 int j; 1537 1538 IWL_ERR(trans_pcie->trans, 1539 "Error allocating IRQ %d\n", i); 1540 for (j = 0; j < i; j++) 1541 free_irq(trans_pcie->msix_entries[j].vector, 1542 &trans_pcie->msix_entries[j]); 1543 pci_disable_msix(pdev); 1544 return ret; 1545 } 1546 } 1547 1548 return 0; 1549 } 1550 1551 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1552 { 1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1554 bool hw_rfkill; 1555 int err; 1556 1557 lockdep_assert_held(&trans_pcie->mutex); 1558 1559 err = iwl_pcie_prepare_card_hw(trans); 1560 if (err) { 1561 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1562 return err; 1563 } 1564 1565 /* Reset the entire device */ 1566 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1567 usleep_range(1000, 2000); 1568 1569 iwl_pcie_apm_init(trans); 1570 1571 iwl_pcie_init_msix(trans_pcie); 1572 /* From now on, the op_mode will be kept updated about RF kill state */ 1573 iwl_enable_rfkill_int(trans); 1574 1575 /* Set is_down to false here so that...*/ 1576 trans_pcie->is_down = false; 1577 1578 hw_rfkill = iwl_is_rfkill_set(trans); 1579 if (hw_rfkill) 1580 set_bit(STATUS_RFKILL, &trans->status); 1581 else 1582 clear_bit(STATUS_RFKILL, &trans->status); 1583 /* ... rfkill can call stop_device and set it false if needed */ 1584 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1585 1586 /* Make sure we sync here, because we'll need full access later */ 1587 if (low_power) 1588 pm_runtime_resume(trans->dev); 1589 1590 return 0; 1591 } 1592 1593 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1594 { 1595 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1596 int ret; 1597 1598 mutex_lock(&trans_pcie->mutex); 1599 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1600 mutex_unlock(&trans_pcie->mutex); 1601 1602 return ret; 1603 } 1604 1605 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1606 { 1607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1608 1609 mutex_lock(&trans_pcie->mutex); 1610 1611 /* disable interrupts - don't enable HW RF kill interrupt */ 1612 iwl_disable_interrupts(trans); 1613 1614 iwl_pcie_apm_stop(trans, true); 1615 1616 iwl_disable_interrupts(trans); 1617 1618 iwl_pcie_disable_ict(trans); 1619 1620 mutex_unlock(&trans_pcie->mutex); 1621 1622 iwl_pcie_synchronize_irqs(trans); 1623 } 1624 1625 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1626 { 1627 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1628 } 1629 1630 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1631 { 1632 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1633 } 1634 1635 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1636 { 1637 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1638 } 1639 1640 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1641 { 1642 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1643 ((reg & 0x000FFFFF) | (3 << 24))); 1644 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1645 } 1646 1647 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1648 u32 val) 1649 { 1650 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1651 ((addr & 0x000FFFFF) | (3 << 24))); 1652 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1653 } 1654 1655 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1656 const struct iwl_trans_config *trans_cfg) 1657 { 1658 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1659 1660 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1661 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1662 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1663 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1664 trans_pcie->n_no_reclaim_cmds = 0; 1665 else 1666 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1667 if (trans_pcie->n_no_reclaim_cmds) 1668 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1669 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1670 1671 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1672 trans_pcie->rx_page_order = 1673 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1674 1675 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; 1676 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1677 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1678 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1679 1680 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1681 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1682 1683 trans->command_groups = trans_cfg->command_groups; 1684 trans->command_groups_size = trans_cfg->command_groups_size; 1685 1686 /* Initialize NAPI here - it should be before registering to mac80211 1687 * in the opmode but after the HW struct is allocated. 1688 * As this function may be called again in some corner cases don't 1689 * do anything if NAPI was already initialized. 1690 */ 1691 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1692 init_dummy_netdev(&trans_pcie->napi_dev); 1693 } 1694 1695 void iwl_trans_pcie_free(struct iwl_trans *trans) 1696 { 1697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1698 int i; 1699 1700 iwl_pcie_synchronize_irqs(trans); 1701 1702 iwl_pcie_tx_free(trans); 1703 iwl_pcie_rx_free(trans); 1704 1705 if (trans_pcie->msix_enabled) { 1706 for (i = 0; i < trans_pcie->allocated_vector; i++) 1707 free_irq(trans_pcie->msix_entries[i].vector, 1708 &trans_pcie->msix_entries[i]); 1709 1710 pci_disable_msix(trans_pcie->pci_dev); 1711 trans_pcie->msix_enabled = false; 1712 } else { 1713 free_irq(trans_pcie->pci_dev->irq, trans); 1714 1715 iwl_pcie_free_ict(trans); 1716 1717 pci_disable_msi(trans_pcie->pci_dev); 1718 } 1719 iounmap(trans_pcie->hw_base); 1720 pci_release_regions(trans_pcie->pci_dev); 1721 pci_disable_device(trans_pcie->pci_dev); 1722 1723 iwl_pcie_free_fw_monitor(trans); 1724 1725 for_each_possible_cpu(i) { 1726 struct iwl_tso_hdr_page *p = 1727 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1728 1729 if (p->page) 1730 __free_page(p->page); 1731 } 1732 1733 free_percpu(trans_pcie->tso_hdr_page); 1734 mutex_destroy(&trans_pcie->mutex); 1735 iwl_trans_free(trans); 1736 } 1737 1738 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1739 { 1740 if (state) 1741 set_bit(STATUS_TPOWER_PMI, &trans->status); 1742 else 1743 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1744 } 1745 1746 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1747 unsigned long *flags) 1748 { 1749 int ret; 1750 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1751 1752 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1753 1754 if (trans_pcie->cmd_hold_nic_awake) 1755 goto out; 1756 1757 /* this bit wakes up the NIC */ 1758 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1759 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1760 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1761 udelay(2); 1762 1763 /* 1764 * These bits say the device is running, and should keep running for 1765 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1766 * but they do not indicate that embedded SRAM is restored yet; 1767 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1768 * to/from host DRAM when sleeping/waking for power-saving. 1769 * Each direction takes approximately 1/4 millisecond; with this 1770 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1771 * series of register accesses are expected (e.g. reading Event Log), 1772 * to keep device from sleeping. 1773 * 1774 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1775 * SRAM is okay/restored. We don't check that here because this call 1776 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1777 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1778 * 1779 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1780 * and do not save/restore SRAM when power cycling. 1781 */ 1782 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1783 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1784 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1785 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1786 if (unlikely(ret < 0)) { 1787 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1788 WARN_ONCE(1, 1789 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1790 iwl_read32(trans, CSR_GP_CNTRL)); 1791 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1792 return false; 1793 } 1794 1795 out: 1796 /* 1797 * Fool sparse by faking we release the lock - sparse will 1798 * track nic_access anyway. 1799 */ 1800 __release(&trans_pcie->reg_lock); 1801 return true; 1802 } 1803 1804 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1805 unsigned long *flags) 1806 { 1807 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1808 1809 lockdep_assert_held(&trans_pcie->reg_lock); 1810 1811 /* 1812 * Fool sparse by faking we acquiring the lock - sparse will 1813 * track nic_access anyway. 1814 */ 1815 __acquire(&trans_pcie->reg_lock); 1816 1817 if (trans_pcie->cmd_hold_nic_awake) 1818 goto out; 1819 1820 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1821 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1822 /* 1823 * Above we read the CSR_GP_CNTRL register, which will flush 1824 * any previous writes, but we need the write that clears the 1825 * MAC_ACCESS_REQ bit to be performed before any other writes 1826 * scheduled on different CPUs (after we drop reg_lock). 1827 */ 1828 mmiowb(); 1829 out: 1830 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1831 } 1832 1833 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1834 void *buf, int dwords) 1835 { 1836 unsigned long flags; 1837 int offs, ret = 0; 1838 u32 *vals = buf; 1839 1840 if (iwl_trans_grab_nic_access(trans, &flags)) { 1841 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1842 for (offs = 0; offs < dwords; offs++) 1843 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1844 iwl_trans_release_nic_access(trans, &flags); 1845 } else { 1846 ret = -EBUSY; 1847 } 1848 return ret; 1849 } 1850 1851 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1852 const void *buf, int dwords) 1853 { 1854 unsigned long flags; 1855 int offs, ret = 0; 1856 const u32 *vals = buf; 1857 1858 if (iwl_trans_grab_nic_access(trans, &flags)) { 1859 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1860 for (offs = 0; offs < dwords; offs++) 1861 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1862 vals ? vals[offs] : 0); 1863 iwl_trans_release_nic_access(trans, &flags); 1864 } else { 1865 ret = -EBUSY; 1866 } 1867 return ret; 1868 } 1869 1870 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1871 unsigned long txqs, 1872 bool freeze) 1873 { 1874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1875 int queue; 1876 1877 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1878 struct iwl_txq *txq = &trans_pcie->txq[queue]; 1879 unsigned long now; 1880 1881 spin_lock_bh(&txq->lock); 1882 1883 now = jiffies; 1884 1885 if (txq->frozen == freeze) 1886 goto next_queue; 1887 1888 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1889 freeze ? "Freezing" : "Waking", queue); 1890 1891 txq->frozen = freeze; 1892 1893 if (txq->q.read_ptr == txq->q.write_ptr) 1894 goto next_queue; 1895 1896 if (freeze) { 1897 if (unlikely(time_after(now, 1898 txq->stuck_timer.expires))) { 1899 /* 1900 * The timer should have fired, maybe it is 1901 * spinning right now on the lock. 1902 */ 1903 goto next_queue; 1904 } 1905 /* remember how long until the timer fires */ 1906 txq->frozen_expiry_remainder = 1907 txq->stuck_timer.expires - now; 1908 del_timer(&txq->stuck_timer); 1909 goto next_queue; 1910 } 1911 1912 /* 1913 * Wake a non-empty queue -> arm timer with the 1914 * remainder before it froze 1915 */ 1916 mod_timer(&txq->stuck_timer, 1917 now + txq->frozen_expiry_remainder); 1918 1919 next_queue: 1920 spin_unlock_bh(&txq->lock); 1921 } 1922 } 1923 1924 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 1925 { 1926 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1927 int i; 1928 1929 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 1930 struct iwl_txq *txq = &trans_pcie->txq[i]; 1931 1932 if (i == trans_pcie->cmd_queue) 1933 continue; 1934 1935 spin_lock_bh(&txq->lock); 1936 1937 if (!block && !(WARN_ON_ONCE(!txq->block))) { 1938 txq->block--; 1939 if (!txq->block) { 1940 iwl_write32(trans, HBUS_TARG_WRPTR, 1941 txq->q.write_ptr | (i << 8)); 1942 } 1943 } else if (block) { 1944 txq->block++; 1945 } 1946 1947 spin_unlock_bh(&txq->lock); 1948 } 1949 } 1950 1951 #define IWL_FLUSH_WAIT_MS 2000 1952 1953 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 1954 { 1955 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1956 u32 scd_sram_addr; 1957 u8 buf[16]; 1958 int cnt; 1959 1960 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1961 txq->q.read_ptr, txq->q.write_ptr); 1962 1963 scd_sram_addr = trans_pcie->scd_base_addr + 1964 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 1965 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 1966 1967 iwl_print_hex_error(trans, buf, sizeof(buf)); 1968 1969 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 1970 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 1971 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 1972 1973 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1974 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 1975 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 1976 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 1977 u32 tbl_dw = 1978 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 1979 SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 1980 1981 if (cnt & 0x1) 1982 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 1983 else 1984 tbl_dw = tbl_dw & 0x0000FFFF; 1985 1986 IWL_ERR(trans, 1987 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 1988 cnt, active ? "" : "in", fifo, tbl_dw, 1989 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 1990 (TFD_QUEUE_SIZE_MAX - 1), 1991 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 1992 } 1993 } 1994 1995 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 1996 { 1997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1998 struct iwl_txq *txq; 1999 struct iwl_queue *q; 2000 int cnt; 2001 unsigned long now = jiffies; 2002 int ret = 0; 2003 2004 /* waiting for all the tx frames complete might take a while */ 2005 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2006 u8 wr_ptr; 2007 2008 if (cnt == trans_pcie->cmd_queue) 2009 continue; 2010 if (!test_bit(cnt, trans_pcie->queue_used)) 2011 continue; 2012 if (!(BIT(cnt) & txq_bm)) 2013 continue; 2014 2015 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 2016 txq = &trans_pcie->txq[cnt]; 2017 q = &txq->q; 2018 wr_ptr = ACCESS_ONCE(q->write_ptr); 2019 2020 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && 2021 !time_after(jiffies, 2022 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2023 u8 write_ptr = ACCESS_ONCE(q->write_ptr); 2024 2025 if (WARN_ONCE(wr_ptr != write_ptr, 2026 "WR pointer moved while flushing %d -> %d\n", 2027 wr_ptr, write_ptr)) 2028 return -ETIMEDOUT; 2029 usleep_range(1000, 2000); 2030 } 2031 2032 if (q->read_ptr != q->write_ptr) { 2033 IWL_ERR(trans, 2034 "fail to flush all tx fifo queues Q %d\n", cnt); 2035 ret = -ETIMEDOUT; 2036 break; 2037 } 2038 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 2039 } 2040 2041 if (ret) 2042 iwl_trans_pcie_log_scd_error(trans, txq); 2043 2044 return ret; 2045 } 2046 2047 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2048 u32 mask, u32 value) 2049 { 2050 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2051 unsigned long flags; 2052 2053 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2054 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2055 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2056 } 2057 2058 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2059 { 2060 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2061 2062 if (iwlwifi_mod_params.d0i3_disable) 2063 return; 2064 2065 pm_runtime_get(&trans_pcie->pci_dev->dev); 2066 2067 #ifdef CONFIG_PM 2068 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2069 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2070 #endif /* CONFIG_PM */ 2071 } 2072 2073 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2074 { 2075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2076 2077 if (iwlwifi_mod_params.d0i3_disable) 2078 return; 2079 2080 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2081 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2082 2083 #ifdef CONFIG_PM 2084 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2085 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2086 #endif /* CONFIG_PM */ 2087 } 2088 2089 static const char *get_csr_string(int cmd) 2090 { 2091 #define IWL_CMD(x) case x: return #x 2092 switch (cmd) { 2093 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2094 IWL_CMD(CSR_INT_COALESCING); 2095 IWL_CMD(CSR_INT); 2096 IWL_CMD(CSR_INT_MASK); 2097 IWL_CMD(CSR_FH_INT_STATUS); 2098 IWL_CMD(CSR_GPIO_IN); 2099 IWL_CMD(CSR_RESET); 2100 IWL_CMD(CSR_GP_CNTRL); 2101 IWL_CMD(CSR_HW_REV); 2102 IWL_CMD(CSR_EEPROM_REG); 2103 IWL_CMD(CSR_EEPROM_GP); 2104 IWL_CMD(CSR_OTP_GP_REG); 2105 IWL_CMD(CSR_GIO_REG); 2106 IWL_CMD(CSR_GP_UCODE_REG); 2107 IWL_CMD(CSR_GP_DRIVER_REG); 2108 IWL_CMD(CSR_UCODE_DRV_GP1); 2109 IWL_CMD(CSR_UCODE_DRV_GP2); 2110 IWL_CMD(CSR_LED_REG); 2111 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2112 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2113 IWL_CMD(CSR_ANA_PLL_CFG); 2114 IWL_CMD(CSR_HW_REV_WA_REG); 2115 IWL_CMD(CSR_MONITOR_STATUS_REG); 2116 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2117 default: 2118 return "UNKNOWN"; 2119 } 2120 #undef IWL_CMD 2121 } 2122 2123 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2124 { 2125 int i; 2126 static const u32 csr_tbl[] = { 2127 CSR_HW_IF_CONFIG_REG, 2128 CSR_INT_COALESCING, 2129 CSR_INT, 2130 CSR_INT_MASK, 2131 CSR_FH_INT_STATUS, 2132 CSR_GPIO_IN, 2133 CSR_RESET, 2134 CSR_GP_CNTRL, 2135 CSR_HW_REV, 2136 CSR_EEPROM_REG, 2137 CSR_EEPROM_GP, 2138 CSR_OTP_GP_REG, 2139 CSR_GIO_REG, 2140 CSR_GP_UCODE_REG, 2141 CSR_GP_DRIVER_REG, 2142 CSR_UCODE_DRV_GP1, 2143 CSR_UCODE_DRV_GP2, 2144 CSR_LED_REG, 2145 CSR_DRAM_INT_TBL_REG, 2146 CSR_GIO_CHICKEN_BITS, 2147 CSR_ANA_PLL_CFG, 2148 CSR_MONITOR_STATUS_REG, 2149 CSR_HW_REV_WA_REG, 2150 CSR_DBG_HPET_MEM_REG 2151 }; 2152 IWL_ERR(trans, "CSR values:\n"); 2153 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2154 "CSR_INT_PERIODIC_REG)\n"); 2155 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2156 IWL_ERR(trans, " %25s: 0X%08x\n", 2157 get_csr_string(csr_tbl[i]), 2158 iwl_read32(trans, csr_tbl[i])); 2159 } 2160 } 2161 2162 #ifdef CONFIG_IWLWIFI_DEBUGFS 2163 /* create and remove of files */ 2164 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2165 if (!debugfs_create_file(#name, mode, parent, trans, \ 2166 &iwl_dbgfs_##name##_ops)) \ 2167 goto err; \ 2168 } while (0) 2169 2170 /* file operation */ 2171 #define DEBUGFS_READ_FILE_OPS(name) \ 2172 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2173 .read = iwl_dbgfs_##name##_read, \ 2174 .open = simple_open, \ 2175 .llseek = generic_file_llseek, \ 2176 }; 2177 2178 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2179 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2180 .write = iwl_dbgfs_##name##_write, \ 2181 .open = simple_open, \ 2182 .llseek = generic_file_llseek, \ 2183 }; 2184 2185 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2186 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2187 .write = iwl_dbgfs_##name##_write, \ 2188 .read = iwl_dbgfs_##name##_read, \ 2189 .open = simple_open, \ 2190 .llseek = generic_file_llseek, \ 2191 }; 2192 2193 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2194 char __user *user_buf, 2195 size_t count, loff_t *ppos) 2196 { 2197 struct iwl_trans *trans = file->private_data; 2198 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2199 struct iwl_txq *txq; 2200 struct iwl_queue *q; 2201 char *buf; 2202 int pos = 0; 2203 int cnt; 2204 int ret; 2205 size_t bufsz; 2206 2207 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2208 2209 if (!trans_pcie->txq) 2210 return -EAGAIN; 2211 2212 buf = kzalloc(bufsz, GFP_KERNEL); 2213 if (!buf) 2214 return -ENOMEM; 2215 2216 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2217 txq = &trans_pcie->txq[cnt]; 2218 q = &txq->q; 2219 pos += scnprintf(buf + pos, bufsz - pos, 2220 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2221 cnt, q->read_ptr, q->write_ptr, 2222 !!test_bit(cnt, trans_pcie->queue_used), 2223 !!test_bit(cnt, trans_pcie->queue_stopped), 2224 txq->need_update, txq->frozen, 2225 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2226 } 2227 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2228 kfree(buf); 2229 return ret; 2230 } 2231 2232 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2233 char __user *user_buf, 2234 size_t count, loff_t *ppos) 2235 { 2236 struct iwl_trans *trans = file->private_data; 2237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2238 char *buf; 2239 int pos = 0, i, ret; 2240 size_t bufsz = sizeof(buf); 2241 2242 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2243 2244 if (!trans_pcie->rxq) 2245 return -EAGAIN; 2246 2247 buf = kzalloc(bufsz, GFP_KERNEL); 2248 if (!buf) 2249 return -ENOMEM; 2250 2251 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2252 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2253 2254 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2255 i); 2256 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2257 rxq->read); 2258 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2259 rxq->write); 2260 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2261 rxq->write_actual); 2262 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2263 rxq->need_update); 2264 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2265 rxq->free_count); 2266 if (rxq->rb_stts) { 2267 pos += scnprintf(buf + pos, bufsz - pos, 2268 "\tclosed_rb_num: %u\n", 2269 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2270 0x0FFF); 2271 } else { 2272 pos += scnprintf(buf + pos, bufsz - pos, 2273 "\tclosed_rb_num: Not Allocated\n"); 2274 } 2275 } 2276 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2277 kfree(buf); 2278 2279 return ret; 2280 } 2281 2282 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2283 char __user *user_buf, 2284 size_t count, loff_t *ppos) 2285 { 2286 struct iwl_trans *trans = file->private_data; 2287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2288 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2289 2290 int pos = 0; 2291 char *buf; 2292 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2293 ssize_t ret; 2294 2295 buf = kzalloc(bufsz, GFP_KERNEL); 2296 if (!buf) 2297 return -ENOMEM; 2298 2299 pos += scnprintf(buf + pos, bufsz - pos, 2300 "Interrupt Statistics Report:\n"); 2301 2302 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2303 isr_stats->hw); 2304 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2305 isr_stats->sw); 2306 if (isr_stats->sw || isr_stats->hw) { 2307 pos += scnprintf(buf + pos, bufsz - pos, 2308 "\tLast Restarting Code: 0x%X\n", 2309 isr_stats->err_code); 2310 } 2311 #ifdef CONFIG_IWLWIFI_DEBUG 2312 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2313 isr_stats->sch); 2314 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2315 isr_stats->alive); 2316 #endif 2317 pos += scnprintf(buf + pos, bufsz - pos, 2318 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2319 2320 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2321 isr_stats->ctkill); 2322 2323 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2324 isr_stats->wakeup); 2325 2326 pos += scnprintf(buf + pos, bufsz - pos, 2327 "Rx command responses:\t\t %u\n", isr_stats->rx); 2328 2329 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2330 isr_stats->tx); 2331 2332 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2333 isr_stats->unhandled); 2334 2335 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2336 kfree(buf); 2337 return ret; 2338 } 2339 2340 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2341 const char __user *user_buf, 2342 size_t count, loff_t *ppos) 2343 { 2344 struct iwl_trans *trans = file->private_data; 2345 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2346 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2347 2348 char buf[8]; 2349 int buf_size; 2350 u32 reset_flag; 2351 2352 memset(buf, 0, sizeof(buf)); 2353 buf_size = min(count, sizeof(buf) - 1); 2354 if (copy_from_user(buf, user_buf, buf_size)) 2355 return -EFAULT; 2356 if (sscanf(buf, "%x", &reset_flag) != 1) 2357 return -EFAULT; 2358 if (reset_flag == 0) 2359 memset(isr_stats, 0, sizeof(*isr_stats)); 2360 2361 return count; 2362 } 2363 2364 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2365 const char __user *user_buf, 2366 size_t count, loff_t *ppos) 2367 { 2368 struct iwl_trans *trans = file->private_data; 2369 char buf[8]; 2370 int buf_size; 2371 int csr; 2372 2373 memset(buf, 0, sizeof(buf)); 2374 buf_size = min(count, sizeof(buf) - 1); 2375 if (copy_from_user(buf, user_buf, buf_size)) 2376 return -EFAULT; 2377 if (sscanf(buf, "%d", &csr) != 1) 2378 return -EFAULT; 2379 2380 iwl_pcie_dump_csr(trans); 2381 2382 return count; 2383 } 2384 2385 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2386 char __user *user_buf, 2387 size_t count, loff_t *ppos) 2388 { 2389 struct iwl_trans *trans = file->private_data; 2390 char *buf = NULL; 2391 ssize_t ret; 2392 2393 ret = iwl_dump_fh(trans, &buf); 2394 if (ret < 0) 2395 return ret; 2396 if (!buf) 2397 return -EINVAL; 2398 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2399 kfree(buf); 2400 return ret; 2401 } 2402 2403 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2404 DEBUGFS_READ_FILE_OPS(fh_reg); 2405 DEBUGFS_READ_FILE_OPS(rx_queue); 2406 DEBUGFS_READ_FILE_OPS(tx_queue); 2407 DEBUGFS_WRITE_FILE_OPS(csr); 2408 2409 /* Create the debugfs files and directories */ 2410 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2411 { 2412 struct dentry *dir = trans->dbgfs_dir; 2413 2414 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2415 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2416 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2417 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2418 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2419 return 0; 2420 2421 err: 2422 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2423 return -ENOMEM; 2424 } 2425 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2426 2427 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) 2428 { 2429 u32 cmdlen = 0; 2430 int i; 2431 2432 for (i = 0; i < IWL_NUM_OF_TBS; i++) 2433 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); 2434 2435 return cmdlen; 2436 } 2437 2438 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2439 struct iwl_fw_error_dump_data **data, 2440 int allocated_rb_nums) 2441 { 2442 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2443 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2444 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2445 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2446 u32 i, r, j, rb_len = 0; 2447 2448 spin_lock(&rxq->lock); 2449 2450 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2451 2452 for (i = rxq->read, j = 0; 2453 i != r && j < allocated_rb_nums; 2454 i = (i + 1) & RX_QUEUE_MASK, j++) { 2455 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2456 struct iwl_fw_error_dump_rb *rb; 2457 2458 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2459 DMA_FROM_DEVICE); 2460 2461 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2462 2463 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2464 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2465 rb = (void *)(*data)->data; 2466 rb->index = cpu_to_le32(i); 2467 memcpy(rb->data, page_address(rxb->page), max_len); 2468 /* remap the page for the free benefit */ 2469 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2470 max_len, 2471 DMA_FROM_DEVICE); 2472 2473 *data = iwl_fw_error_next_data(*data); 2474 } 2475 2476 spin_unlock(&rxq->lock); 2477 2478 return rb_len; 2479 } 2480 #define IWL_CSR_TO_DUMP (0x250) 2481 2482 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2483 struct iwl_fw_error_dump_data **data) 2484 { 2485 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2486 __le32 *val; 2487 int i; 2488 2489 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2490 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2491 val = (void *)(*data)->data; 2492 2493 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2494 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2495 2496 *data = iwl_fw_error_next_data(*data); 2497 2498 return csr_len; 2499 } 2500 2501 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2502 struct iwl_fw_error_dump_data **data) 2503 { 2504 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2505 unsigned long flags; 2506 __le32 *val; 2507 int i; 2508 2509 if (!iwl_trans_grab_nic_access(trans, &flags)) 2510 return 0; 2511 2512 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2513 (*data)->len = cpu_to_le32(fh_regs_len); 2514 val = (void *)(*data)->data; 2515 2516 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2517 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2518 2519 iwl_trans_release_nic_access(trans, &flags); 2520 2521 *data = iwl_fw_error_next_data(*data); 2522 2523 return sizeof(**data) + fh_regs_len; 2524 } 2525 2526 static u32 2527 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2528 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2529 u32 monitor_len) 2530 { 2531 u32 buf_size_in_dwords = (monitor_len >> 2); 2532 u32 *buffer = (u32 *)fw_mon_data->data; 2533 unsigned long flags; 2534 u32 i; 2535 2536 if (!iwl_trans_grab_nic_access(trans, &flags)) 2537 return 0; 2538 2539 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2540 for (i = 0; i < buf_size_in_dwords; i++) 2541 buffer[i] = iwl_read_prph_no_grab(trans, 2542 MON_DMARB_RD_DATA_ADDR); 2543 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2544 2545 iwl_trans_release_nic_access(trans, &flags); 2546 2547 return monitor_len; 2548 } 2549 2550 static u32 2551 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2552 struct iwl_fw_error_dump_data **data, 2553 u32 monitor_len) 2554 { 2555 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2556 u32 len = 0; 2557 2558 if ((trans_pcie->fw_mon_page && 2559 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2560 trans->dbg_dest_tlv) { 2561 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2562 u32 base, write_ptr, wrap_cnt; 2563 2564 /* If there was a dest TLV - use the values from there */ 2565 if (trans->dbg_dest_tlv) { 2566 write_ptr = 2567 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2568 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2569 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2570 } else { 2571 base = MON_BUFF_BASE_ADDR; 2572 write_ptr = MON_BUFF_WRPTR; 2573 wrap_cnt = MON_BUFF_CYCLE_CNT; 2574 } 2575 2576 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2577 fw_mon_data = (void *)(*data)->data; 2578 fw_mon_data->fw_mon_wr_ptr = 2579 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2580 fw_mon_data->fw_mon_cycle_cnt = 2581 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2582 fw_mon_data->fw_mon_base_ptr = 2583 cpu_to_le32(iwl_read_prph(trans, base)); 2584 2585 len += sizeof(**data) + sizeof(*fw_mon_data); 2586 if (trans_pcie->fw_mon_page) { 2587 /* 2588 * The firmware is now asserted, it won't write anything 2589 * to the buffer. CPU can take ownership to fetch the 2590 * data. The buffer will be handed back to the device 2591 * before the firmware will be restarted. 2592 */ 2593 dma_sync_single_for_cpu(trans->dev, 2594 trans_pcie->fw_mon_phys, 2595 trans_pcie->fw_mon_size, 2596 DMA_FROM_DEVICE); 2597 memcpy(fw_mon_data->data, 2598 page_address(trans_pcie->fw_mon_page), 2599 trans_pcie->fw_mon_size); 2600 2601 monitor_len = trans_pcie->fw_mon_size; 2602 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2603 /* 2604 * Update pointers to reflect actual values after 2605 * shifting 2606 */ 2607 base = iwl_read_prph(trans, base) << 2608 trans->dbg_dest_tlv->base_shift; 2609 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2610 monitor_len / sizeof(u32)); 2611 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2612 monitor_len = 2613 iwl_trans_pci_dump_marbh_monitor(trans, 2614 fw_mon_data, 2615 monitor_len); 2616 } else { 2617 /* Didn't match anything - output no monitor data */ 2618 monitor_len = 0; 2619 } 2620 2621 len += monitor_len; 2622 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2623 } 2624 2625 return len; 2626 } 2627 2628 static struct iwl_trans_dump_data 2629 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2630 const struct iwl_fw_dbg_trigger_tlv *trigger) 2631 { 2632 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2633 struct iwl_fw_error_dump_data *data; 2634 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2635 struct iwl_fw_error_dump_txcmd *txcmd; 2636 struct iwl_trans_dump_data *dump_data; 2637 u32 len, num_rbs; 2638 u32 monitor_len; 2639 int i, ptr; 2640 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2641 !trans->cfg->mq_rx_supported; 2642 2643 /* transport dump header */ 2644 len = sizeof(*dump_data); 2645 2646 /* host commands */ 2647 len += sizeof(*data) + 2648 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2649 2650 /* FW monitor */ 2651 if (trans_pcie->fw_mon_page) { 2652 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2653 trans_pcie->fw_mon_size; 2654 monitor_len = trans_pcie->fw_mon_size; 2655 } else if (trans->dbg_dest_tlv) { 2656 u32 base, end; 2657 2658 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2659 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2660 2661 base = iwl_read_prph(trans, base) << 2662 trans->dbg_dest_tlv->base_shift; 2663 end = iwl_read_prph(trans, end) << 2664 trans->dbg_dest_tlv->end_shift; 2665 2666 /* Make "end" point to the actual end */ 2667 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2668 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2669 end += (1 << trans->dbg_dest_tlv->end_shift); 2670 monitor_len = end - base; 2671 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2672 monitor_len; 2673 } else { 2674 monitor_len = 0; 2675 } 2676 2677 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2678 dump_data = vzalloc(len); 2679 if (!dump_data) 2680 return NULL; 2681 2682 data = (void *)dump_data->data; 2683 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2684 dump_data->len = len; 2685 2686 return dump_data; 2687 } 2688 2689 /* CSR registers */ 2690 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2691 2692 /* FH registers */ 2693 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2694 2695 if (dump_rbs) { 2696 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2697 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2698 /* RBs */ 2699 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2700 & 0x0FFF; 2701 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2702 len += num_rbs * (sizeof(*data) + 2703 sizeof(struct iwl_fw_error_dump_rb) + 2704 (PAGE_SIZE << trans_pcie->rx_page_order)); 2705 } 2706 2707 dump_data = vzalloc(len); 2708 if (!dump_data) 2709 return NULL; 2710 2711 len = 0; 2712 data = (void *)dump_data->data; 2713 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2714 txcmd = (void *)data->data; 2715 spin_lock_bh(&cmdq->lock); 2716 ptr = cmdq->q.write_ptr; 2717 for (i = 0; i < cmdq->q.n_window; i++) { 2718 u8 idx = get_cmd_index(&cmdq->q, ptr); 2719 u32 caplen, cmdlen; 2720 2721 cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); 2722 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2723 2724 if (cmdlen) { 2725 len += sizeof(*txcmd) + caplen; 2726 txcmd->cmdlen = cpu_to_le32(cmdlen); 2727 txcmd->caplen = cpu_to_le32(caplen); 2728 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2729 txcmd = (void *)((u8 *)txcmd->data + caplen); 2730 } 2731 2732 ptr = iwl_queue_dec_wrap(ptr); 2733 } 2734 spin_unlock_bh(&cmdq->lock); 2735 2736 data->len = cpu_to_le32(len); 2737 len += sizeof(*data); 2738 data = iwl_fw_error_next_data(data); 2739 2740 len += iwl_trans_pcie_dump_csr(trans, &data); 2741 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2742 if (dump_rbs) 2743 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2744 2745 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2746 2747 dump_data->len = len; 2748 2749 return dump_data; 2750 } 2751 2752 #ifdef CONFIG_PM_SLEEP 2753 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2754 { 2755 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2756 return iwl_pci_fw_enter_d0i3(trans); 2757 2758 return 0; 2759 } 2760 2761 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2762 { 2763 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2764 iwl_pci_fw_exit_d0i3(trans); 2765 } 2766 #endif /* CONFIG_PM_SLEEP */ 2767 2768 static const struct iwl_trans_ops trans_ops_pcie = { 2769 .start_hw = iwl_trans_pcie_start_hw, 2770 .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2771 .fw_alive = iwl_trans_pcie_fw_alive, 2772 .start_fw = iwl_trans_pcie_start_fw, 2773 .stop_device = iwl_trans_pcie_stop_device, 2774 2775 .d3_suspend = iwl_trans_pcie_d3_suspend, 2776 .d3_resume = iwl_trans_pcie_d3_resume, 2777 2778 #ifdef CONFIG_PM_SLEEP 2779 .suspend = iwl_trans_pcie_suspend, 2780 .resume = iwl_trans_pcie_resume, 2781 #endif /* CONFIG_PM_SLEEP */ 2782 2783 .send_cmd = iwl_trans_pcie_send_hcmd, 2784 2785 .tx = iwl_trans_pcie_tx, 2786 .reclaim = iwl_trans_pcie_reclaim, 2787 2788 .txq_disable = iwl_trans_pcie_txq_disable, 2789 .txq_enable = iwl_trans_pcie_txq_enable, 2790 2791 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2792 2793 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2794 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2795 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2796 2797 .write8 = iwl_trans_pcie_write8, 2798 .write32 = iwl_trans_pcie_write32, 2799 .read32 = iwl_trans_pcie_read32, 2800 .read_prph = iwl_trans_pcie_read_prph, 2801 .write_prph = iwl_trans_pcie_write_prph, 2802 .read_mem = iwl_trans_pcie_read_mem, 2803 .write_mem = iwl_trans_pcie_write_mem, 2804 .configure = iwl_trans_pcie_configure, 2805 .set_pmi = iwl_trans_pcie_set_pmi, 2806 .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2807 .release_nic_access = iwl_trans_pcie_release_nic_access, 2808 .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2809 2810 .ref = iwl_trans_pcie_ref, 2811 .unref = iwl_trans_pcie_unref, 2812 2813 .dump_data = iwl_trans_pcie_dump_data, 2814 }; 2815 2816 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2817 const struct pci_device_id *ent, 2818 const struct iwl_cfg *cfg) 2819 { 2820 struct iwl_trans_pcie *trans_pcie; 2821 struct iwl_trans *trans; 2822 int ret, addr_size; 2823 2824 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2825 &pdev->dev, cfg, &trans_ops_pcie, 0); 2826 if (!trans) 2827 return ERR_PTR(-ENOMEM); 2828 2829 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; 2830 2831 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2832 2833 trans_pcie->trans = trans; 2834 spin_lock_init(&trans_pcie->irq_lock); 2835 spin_lock_init(&trans_pcie->reg_lock); 2836 mutex_init(&trans_pcie->mutex); 2837 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 2838 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 2839 if (!trans_pcie->tso_hdr_page) { 2840 ret = -ENOMEM; 2841 goto out_no_pci; 2842 } 2843 2844 ret = pci_enable_device(pdev); 2845 if (ret) 2846 goto out_no_pci; 2847 2848 if (!cfg->base_params->pcie_l1_allowed) { 2849 /* 2850 * W/A - seems to solve weird behavior. We need to remove this 2851 * if we don't want to stay in L1 all the time. This wastes a 2852 * lot of power. 2853 */ 2854 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2855 PCIE_LINK_STATE_L1 | 2856 PCIE_LINK_STATE_CLKPM); 2857 } 2858 2859 if (cfg->mq_rx_supported) 2860 addr_size = 64; 2861 else 2862 addr_size = 36; 2863 2864 pci_set_master(pdev); 2865 2866 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2867 if (!ret) 2868 ret = pci_set_consistent_dma_mask(pdev, 2869 DMA_BIT_MASK(addr_size)); 2870 if (ret) { 2871 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2872 if (!ret) 2873 ret = pci_set_consistent_dma_mask(pdev, 2874 DMA_BIT_MASK(32)); 2875 /* both attempts failed: */ 2876 if (ret) { 2877 dev_err(&pdev->dev, "No suitable DMA available\n"); 2878 goto out_pci_disable_device; 2879 } 2880 } 2881 2882 ret = pci_request_regions(pdev, DRV_NAME); 2883 if (ret) { 2884 dev_err(&pdev->dev, "pci_request_regions failed\n"); 2885 goto out_pci_disable_device; 2886 } 2887 2888 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); 2889 if (!trans_pcie->hw_base) { 2890 dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); 2891 ret = -ENODEV; 2892 goto out_pci_release_regions; 2893 } 2894 2895 /* We disable the RETRY_TIMEOUT register (0x41) to keep 2896 * PCI Tx retries from interfering with C3 CPU state */ 2897 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 2898 2899 trans->dev = &pdev->dev; 2900 trans_pcie->pci_dev = pdev; 2901 iwl_disable_interrupts(trans); 2902 2903 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 2904 /* 2905 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 2906 * changed, and now the revision step also includes bit 0-1 (no more 2907 * "dash" value). To keep hw_rev backwards compatible - we'll store it 2908 * in the old format. 2909 */ 2910 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 2911 unsigned long flags; 2912 2913 trans->hw_rev = (trans->hw_rev & 0xfff0) | 2914 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 2915 2916 ret = iwl_pcie_prepare_card_hw(trans); 2917 if (ret) { 2918 IWL_WARN(trans, "Exit HW not ready\n"); 2919 goto out_pci_disable_msi; 2920 } 2921 2922 /* 2923 * in-order to recognize C step driver should read chip version 2924 * id located at the AUX bus MISC address space. 2925 */ 2926 iwl_set_bit(trans, CSR_GP_CNTRL, 2927 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 2928 udelay(2); 2929 2930 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2931 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2932 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2933 25000); 2934 if (ret < 0) { 2935 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 2936 goto out_pci_disable_msi; 2937 } 2938 2939 if (iwl_trans_grab_nic_access(trans, &flags)) { 2940 u32 hw_step; 2941 2942 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 2943 hw_step |= ENABLE_WFPM; 2944 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 2945 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 2946 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 2947 if (hw_step == 0x3) 2948 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 2949 (SILICON_C_STEP << 2); 2950 iwl_trans_release_nic_access(trans, &flags); 2951 } 2952 } 2953 2954 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 2955 2956 iwl_pcie_set_interrupt_capa(pdev, trans); 2957 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 2958 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 2959 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 2960 2961 /* Initialize the wait queue for commands */ 2962 init_waitqueue_head(&trans_pcie->wait_command_queue); 2963 2964 init_waitqueue_head(&trans_pcie->d0i3_waitq); 2965 2966 if (trans_pcie->msix_enabled) { 2967 if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 2968 goto out_pci_release_regions; 2969 } else { 2970 ret = iwl_pcie_alloc_ict(trans); 2971 if (ret) 2972 goto out_pci_disable_msi; 2973 2974 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, 2975 iwl_pcie_irq_handler, 2976 IRQF_SHARED, DRV_NAME, trans); 2977 if (ret) { 2978 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 2979 goto out_free_ict; 2980 } 2981 trans_pcie->inta_mask = CSR_INI_SET_MASK; 2982 } 2983 2984 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 2985 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 2986 #else 2987 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 2988 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 2989 2990 return trans; 2991 2992 out_free_ict: 2993 iwl_pcie_free_ict(trans); 2994 out_pci_disable_msi: 2995 pci_disable_msi(pdev); 2996 out_pci_release_regions: 2997 pci_release_regions(pdev); 2998 out_pci_disable_device: 2999 pci_disable_device(pdev); 3000 out_no_pci: 3001 free_percpu(trans_pcie->tso_hdr_page); 3002 iwl_trans_free(trans); 3003 return ERR_PTR(ret); 3004 } 3005