1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25 * USA 26 * 27 * The full GNU General Public License is included in this distribution 28 * in the file called COPYING. 29 * 30 * Contact Information: 31 * Intel Linux Wireless <linuxwifi@intel.com> 32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33 * 34 * BSD LICENSE 35 * 36 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 37 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 38 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 39 * Copyright(c) 2018 Intel Corporation 40 * All rights reserved. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 46 * * Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * * Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in 50 * the documentation and/or other materials provided with the 51 * distribution. 52 * * Neither the name Intel Corporation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 59 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 60 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 61 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 62 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 * 68 *****************************************************************************/ 69 #include <linux/pci.h> 70 #include <linux/pci-aspm.h> 71 #include <linux/interrupt.h> 72 #include <linux/debugfs.h> 73 #include <linux/sched.h> 74 #include <linux/bitops.h> 75 #include <linux/gfp.h> 76 #include <linux/vmalloc.h> 77 #include <linux/pm_runtime.h> 78 #include <linux/module.h> 79 80 #include "iwl-drv.h" 81 #include "iwl-trans.h" 82 #include "iwl-csr.h" 83 #include "iwl-prph.h" 84 #include "iwl-scd.h" 85 #include "iwl-agn-hw.h" 86 #include "fw/error-dump.h" 87 #include "internal.h" 88 #include "iwl-fh.h" 89 90 /* extended range in FW SRAM */ 91 #define IWL_FW_MEM_EXTENDED_START 0x40000 92 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 93 94 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 95 { 96 #define PCI_DUMP_SIZE 64 97 #define PREFIX_LEN 32 98 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 99 struct pci_dev *pdev = trans_pcie->pci_dev; 100 u32 i, pos, alloc_size, *ptr, *buf; 101 char *prefix; 102 103 if (trans_pcie->pcie_dbg_dumped_once) 104 return; 105 106 /* Should be a multiple of 4 */ 107 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 108 /* Alloc a max size buffer */ 109 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 110 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 111 else 112 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 113 buf = kmalloc(alloc_size, GFP_ATOMIC); 114 if (!buf) 115 return; 116 prefix = (char *)buf + alloc_size - PREFIX_LEN; 117 118 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 119 120 /* Print wifi device registers */ 121 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 122 IWL_ERR(trans, "iwlwifi device config registers:\n"); 123 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 124 if (pci_read_config_dword(pdev, i, ptr)) 125 goto err_read; 126 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 127 128 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 129 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 130 *ptr = iwl_read32(trans, i); 131 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 132 133 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 134 if (pos) { 135 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 136 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 137 if (pci_read_config_dword(pdev, pos + i, ptr)) 138 goto err_read; 139 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 140 32, 4, buf, i, 0); 141 } 142 143 /* Print parent device registers next */ 144 if (!pdev->bus->self) 145 goto out; 146 147 pdev = pdev->bus->self; 148 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 149 150 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 151 pci_name(pdev)); 152 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 153 if (pci_read_config_dword(pdev, i, ptr)) 154 goto err_read; 155 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 156 157 /* Print root port AER registers */ 158 pos = 0; 159 pdev = pcie_find_root_port(pdev); 160 if (pdev) 161 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 162 if (pos) { 163 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 164 pci_name(pdev)); 165 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 166 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 167 if (pci_read_config_dword(pdev, pos + i, ptr)) 168 goto err_read; 169 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 170 4, buf, i, 0); 171 } 172 goto out; 173 174 err_read: 175 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 176 IWL_ERR(trans, "Read failed at 0x%X\n", i); 177 out: 178 trans_pcie->pcie_dbg_dumped_once = 1; 179 kfree(buf); 180 } 181 182 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 183 { 184 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 185 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 186 BIT(trans->cfg->csr->flag_sw_reset)); 187 usleep_range(5000, 6000); 188 } 189 190 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 191 { 192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 193 194 if (!trans_pcie->fw_mon_page) 195 return; 196 197 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 198 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 199 __free_pages(trans_pcie->fw_mon_page, 200 get_order(trans_pcie->fw_mon_size)); 201 trans_pcie->fw_mon_page = NULL; 202 trans_pcie->fw_mon_phys = 0; 203 trans_pcie->fw_mon_size = 0; 204 } 205 206 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 207 { 208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 209 struct page *page = NULL; 210 dma_addr_t phys; 211 u32 size = 0; 212 u8 power; 213 214 if (!max_power) { 215 /* default max_power is maximum */ 216 max_power = 26; 217 } else { 218 max_power += 11; 219 } 220 221 if (WARN(max_power > 26, 222 "External buffer size for monitor is too big %d, check the FW TLV\n", 223 max_power)) 224 return; 225 226 if (trans_pcie->fw_mon_page) { 227 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 228 trans_pcie->fw_mon_size, 229 DMA_FROM_DEVICE); 230 return; 231 } 232 233 phys = 0; 234 for (power = max_power; power >= 11; power--) { 235 int order; 236 237 size = BIT(power); 238 order = get_order(size); 239 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 240 order); 241 if (!page) 242 continue; 243 244 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 245 DMA_FROM_DEVICE); 246 if (dma_mapping_error(trans->dev, phys)) { 247 __free_pages(page, order); 248 page = NULL; 249 continue; 250 } 251 IWL_INFO(trans, 252 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 253 size, order); 254 break; 255 } 256 257 if (WARN_ON_ONCE(!page)) 258 return; 259 260 if (power != max_power) 261 IWL_ERR(trans, 262 "Sorry - debug buffer is only %luK while you requested %luK\n", 263 (unsigned long)BIT(power - 10), 264 (unsigned long)BIT(max_power - 10)); 265 266 trans_pcie->fw_mon_page = page; 267 trans_pcie->fw_mon_phys = phys; 268 trans_pcie->fw_mon_size = size; 269 } 270 271 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 272 { 273 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274 ((reg & 0x0000ffff) | (2 << 28))); 275 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 276 } 277 278 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 279 { 280 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 281 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 282 ((reg & 0x0000ffff) | (3 << 28))); 283 } 284 285 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 286 { 287 if (trans->cfg->apmg_not_supported) 288 return; 289 290 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 291 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 292 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 293 ~APMG_PS_CTRL_MSK_PWR_SRC); 294 else 295 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 296 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 297 ~APMG_PS_CTRL_MSK_PWR_SRC); 298 } 299 300 /* PCI registers */ 301 #define PCI_CFG_RETRY_TIMEOUT 0x041 302 303 void iwl_pcie_apm_config(struct iwl_trans *trans) 304 { 305 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 306 u16 lctl; 307 u16 cap; 308 309 /* 310 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 311 * Check if BIOS (or OS) enabled L1-ASPM on this device. 312 * If so (likely), disable L0S, so device moves directly L0->L1; 313 * costs negligible amount of power savings. 314 * If not (unlikely), enable L0S, so there is at least some 315 * power savings, even without L1. 316 */ 317 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 318 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 319 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 320 else 321 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 322 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 323 324 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 325 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 326 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 327 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 328 trans->ltr_enabled ? "En" : "Dis"); 329 } 330 331 /* 332 * Start up NIC's basic functionality after it has been reset 333 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 334 * NOTE: This does not load uCode nor start the embedded processor 335 */ 336 static int iwl_pcie_apm_init(struct iwl_trans *trans) 337 { 338 int ret; 339 340 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 341 342 /* 343 * Use "set_bit" below rather than "write", to preserve any hardware 344 * bits already set by default after reset. 345 */ 346 347 /* Disable L0S exit timer (platform NMI Work/Around) */ 348 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 349 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 350 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 351 352 /* 353 * Disable L0s without affecting L1; 354 * don't wait for ICH L0s (ICH bug W/A) 355 */ 356 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 357 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 358 359 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 360 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 361 362 /* 363 * Enable HAP INTA (interrupt from management bus) to 364 * wake device's PCI Express link L1a -> L0s 365 */ 366 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 367 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 368 369 iwl_pcie_apm_config(trans); 370 371 /* Configure analog phase-lock-loop before activating to D0A */ 372 if (trans->cfg->base_params->pll_cfg) 373 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 374 375 /* 376 * Set "initialization complete" bit to move adapter from 377 * D0U* --> D0A* (powered-up active) state. 378 */ 379 iwl_set_bit(trans, CSR_GP_CNTRL, 380 BIT(trans->cfg->csr->flag_init_done)); 381 382 /* 383 * Wait for clock stabilization; once stabilized, access to 384 * device-internal resources is supported, e.g. iwl_write_prph() 385 * and accesses to uCode SRAM. 386 */ 387 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 388 BIT(trans->cfg->csr->flag_mac_clock_ready), 389 BIT(trans->cfg->csr->flag_mac_clock_ready), 390 25000); 391 if (ret < 0) { 392 IWL_ERR(trans, "Failed to init the card\n"); 393 return ret; 394 } 395 396 if (trans->cfg->host_interrupt_operation_mode) { 397 /* 398 * This is a bit of an abuse - This is needed for 7260 / 3160 399 * only check host_interrupt_operation_mode even if this is 400 * not related to host_interrupt_operation_mode. 401 * 402 * Enable the oscillator to count wake up time for L1 exit. This 403 * consumes slightly more power (100uA) - but allows to be sure 404 * that we wake up from L1 on time. 405 * 406 * This looks weird: read twice the same register, discard the 407 * value, set a bit, and yet again, read that same register 408 * just to discard the value. But that's the way the hardware 409 * seems to like it. 410 */ 411 iwl_read_prph(trans, OSC_CLK); 412 iwl_read_prph(trans, OSC_CLK); 413 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 414 iwl_read_prph(trans, OSC_CLK); 415 iwl_read_prph(trans, OSC_CLK); 416 } 417 418 /* 419 * Enable DMA clock and wait for it to stabilize. 420 * 421 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 422 * bits do not disable clocks. This preserves any hardware 423 * bits already set by default in "CLK_CTRL_REG" after reset. 424 */ 425 if (!trans->cfg->apmg_not_supported) { 426 iwl_write_prph(trans, APMG_CLK_EN_REG, 427 APMG_CLK_VAL_DMA_CLK_RQT); 428 udelay(20); 429 430 /* Disable L1-Active */ 431 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 432 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 433 434 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 435 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 436 APMG_RTC_INT_STT_RFKILL); 437 } 438 439 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 440 441 return 0; 442 } 443 444 /* 445 * Enable LP XTAL to avoid HW bug where device may consume much power if 446 * FW is not loaded after device reset. LP XTAL is disabled by default 447 * after device HW reset. Do it only if XTAL is fed by internal source. 448 * Configure device's "persistence" mode to avoid resetting XTAL again when 449 * SHRD_HW_RST occurs in S3. 450 */ 451 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 452 { 453 int ret; 454 u32 apmg_gp1_reg; 455 u32 apmg_xtal_cfg_reg; 456 u32 dl_cfg_reg; 457 458 /* Force XTAL ON */ 459 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 460 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 461 462 iwl_trans_pcie_sw_reset(trans); 463 464 /* 465 * Set "initialization complete" bit to move adapter from 466 * D0U* --> D0A* (powered-up active) state. 467 */ 468 iwl_set_bit(trans, CSR_GP_CNTRL, 469 BIT(trans->cfg->csr->flag_init_done)); 470 471 /* 472 * Wait for clock stabilization; once stabilized, access to 473 * device-internal resources is possible. 474 */ 475 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 476 BIT(trans->cfg->csr->flag_mac_clock_ready), 477 BIT(trans->cfg->csr->flag_mac_clock_ready), 478 25000); 479 if (WARN_ON(ret < 0)) { 480 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 481 /* Release XTAL ON request */ 482 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 483 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 484 return; 485 } 486 487 /* 488 * Clear "disable persistence" to avoid LP XTAL resetting when 489 * SHRD_HW_RST is applied in S3. 490 */ 491 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 492 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 493 494 /* 495 * Force APMG XTAL to be active to prevent its disabling by HW 496 * caused by APMG idle state. 497 */ 498 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 499 SHR_APMG_XTAL_CFG_REG); 500 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 501 apmg_xtal_cfg_reg | 502 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 503 504 iwl_trans_pcie_sw_reset(trans); 505 506 /* Enable LP XTAL by indirect access through CSR */ 507 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 508 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 509 SHR_APMG_GP1_WF_XTAL_LP_EN | 510 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 511 512 /* Clear delay line clock power up */ 513 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 514 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 515 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 516 517 /* 518 * Enable persistence mode to avoid LP XTAL resetting when 519 * SHRD_HW_RST is applied in S3. 520 */ 521 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 522 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 523 524 /* 525 * Clear "initialization complete" bit to move adapter from 526 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 527 */ 528 iwl_clear_bit(trans, CSR_GP_CNTRL, 529 BIT(trans->cfg->csr->flag_init_done)); 530 531 /* Activates XTAL resources monitor */ 532 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 533 CSR_MONITOR_XTAL_RESOURCES); 534 535 /* Release XTAL ON request */ 536 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 537 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 538 udelay(10); 539 540 /* Release APMG XTAL */ 541 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 542 apmg_xtal_cfg_reg & 543 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 544 } 545 546 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 547 { 548 int ret; 549 550 /* stop device's busmaster DMA activity */ 551 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 552 BIT(trans->cfg->csr->flag_stop_master)); 553 554 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 555 BIT(trans->cfg->csr->flag_master_dis), 556 BIT(trans->cfg->csr->flag_master_dis), 100); 557 if (ret < 0) 558 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 559 560 IWL_DEBUG_INFO(trans, "stop master\n"); 561 } 562 563 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 564 { 565 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 566 567 if (op_mode_leave) { 568 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 569 iwl_pcie_apm_init(trans); 570 571 /* inform ME that we are leaving */ 572 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 573 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 574 APMG_PCIDEV_STT_VAL_WAKE_ME); 575 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 576 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 577 CSR_RESET_LINK_PWR_MGMT_DISABLED); 578 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 579 CSR_HW_IF_CONFIG_REG_PREPARE | 580 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 581 mdelay(1); 582 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 583 CSR_RESET_LINK_PWR_MGMT_DISABLED); 584 } 585 mdelay(5); 586 } 587 588 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 589 590 /* Stop device's DMA activity */ 591 iwl_pcie_apm_stop_master(trans); 592 593 if (trans->cfg->lp_xtal_workaround) { 594 iwl_pcie_apm_lp_xtal_enable(trans); 595 return; 596 } 597 598 iwl_trans_pcie_sw_reset(trans); 599 600 /* 601 * Clear "initialization complete" bit to move adapter from 602 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 603 */ 604 iwl_clear_bit(trans, CSR_GP_CNTRL, 605 BIT(trans->cfg->csr->flag_init_done)); 606 } 607 608 static int iwl_pcie_nic_init(struct iwl_trans *trans) 609 { 610 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 611 int ret; 612 613 /* nic_init */ 614 spin_lock(&trans_pcie->irq_lock); 615 ret = iwl_pcie_apm_init(trans); 616 spin_unlock(&trans_pcie->irq_lock); 617 618 if (ret) 619 return ret; 620 621 iwl_pcie_set_pwr(trans, false); 622 623 iwl_op_mode_nic_config(trans->op_mode); 624 625 /* Allocate the RX queue, or reset if it is already allocated */ 626 iwl_pcie_rx_init(trans); 627 628 /* Allocate or reset and init all Tx and Command queues */ 629 if (iwl_pcie_tx_init(trans)) 630 return -ENOMEM; 631 632 if (trans->cfg->base_params->shadow_reg_enable) { 633 /* enable shadow regs in HW */ 634 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 635 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 636 } 637 638 return 0; 639 } 640 641 #define HW_READY_TIMEOUT (50) 642 643 /* Note: returns poll_bit return value, which is >= 0 if success */ 644 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 645 { 646 int ret; 647 648 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 649 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 650 651 /* See if we got it */ 652 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 653 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 654 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 655 HW_READY_TIMEOUT); 656 657 if (ret >= 0) 658 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 659 660 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 661 return ret; 662 } 663 664 /* Note: returns standard 0/-ERROR code */ 665 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 666 { 667 int ret; 668 int t = 0; 669 int iter; 670 671 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 672 673 ret = iwl_pcie_set_hw_ready(trans); 674 /* If the card is ready, exit 0 */ 675 if (ret >= 0) 676 return 0; 677 678 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 679 CSR_RESET_LINK_PWR_MGMT_DISABLED); 680 usleep_range(1000, 2000); 681 682 for (iter = 0; iter < 10; iter++) { 683 /* If HW is not ready, prepare the conditions to check again */ 684 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 685 CSR_HW_IF_CONFIG_REG_PREPARE); 686 687 do { 688 ret = iwl_pcie_set_hw_ready(trans); 689 if (ret >= 0) 690 return 0; 691 692 usleep_range(200, 1000); 693 t += 200; 694 } while (t < 150000); 695 msleep(25); 696 } 697 698 IWL_ERR(trans, "Couldn't prepare the card\n"); 699 700 return ret; 701 } 702 703 /* 704 * ucode 705 */ 706 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 707 u32 dst_addr, dma_addr_t phy_addr, 708 u32 byte_cnt) 709 { 710 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 711 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 712 713 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 714 dst_addr); 715 716 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 717 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 718 719 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 720 (iwl_get_dma_hi_addr(phy_addr) 721 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 722 723 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 724 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 725 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 726 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 727 728 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 729 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 730 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 731 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 732 } 733 734 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 735 u32 dst_addr, dma_addr_t phy_addr, 736 u32 byte_cnt) 737 { 738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 739 unsigned long flags; 740 int ret; 741 742 trans_pcie->ucode_write_complete = false; 743 744 if (!iwl_trans_grab_nic_access(trans, &flags)) 745 return -EIO; 746 747 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 748 byte_cnt); 749 iwl_trans_release_nic_access(trans, &flags); 750 751 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 752 trans_pcie->ucode_write_complete, 5 * HZ); 753 if (!ret) { 754 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 755 iwl_trans_pcie_dump_regs(trans); 756 return -ETIMEDOUT; 757 } 758 759 return 0; 760 } 761 762 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 763 const struct fw_desc *section) 764 { 765 u8 *v_addr; 766 dma_addr_t p_addr; 767 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 768 int ret = 0; 769 770 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 771 section_num); 772 773 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 774 GFP_KERNEL | __GFP_NOWARN); 775 if (!v_addr) { 776 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 777 chunk_sz = PAGE_SIZE; 778 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 779 &p_addr, GFP_KERNEL); 780 if (!v_addr) 781 return -ENOMEM; 782 } 783 784 for (offset = 0; offset < section->len; offset += chunk_sz) { 785 u32 copy_size, dst_addr; 786 bool extended_addr = false; 787 788 copy_size = min_t(u32, chunk_sz, section->len - offset); 789 dst_addr = section->offset + offset; 790 791 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 792 dst_addr <= IWL_FW_MEM_EXTENDED_END) 793 extended_addr = true; 794 795 if (extended_addr) 796 iwl_set_bits_prph(trans, LMPM_CHICK, 797 LMPM_CHICK_EXTENDED_ADDR_SPACE); 798 799 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 800 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 801 copy_size); 802 803 if (extended_addr) 804 iwl_clear_bits_prph(trans, LMPM_CHICK, 805 LMPM_CHICK_EXTENDED_ADDR_SPACE); 806 807 if (ret) { 808 IWL_ERR(trans, 809 "Could not load the [%d] uCode section\n", 810 section_num); 811 break; 812 } 813 } 814 815 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 816 return ret; 817 } 818 819 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 820 const struct fw_img *image, 821 int cpu, 822 int *first_ucode_section) 823 { 824 int shift_param; 825 int i, ret = 0, sec_num = 0x1; 826 u32 val, last_read_idx = 0; 827 828 if (cpu == 1) { 829 shift_param = 0; 830 *first_ucode_section = 0; 831 } else { 832 shift_param = 16; 833 (*first_ucode_section)++; 834 } 835 836 for (i = *first_ucode_section; i < image->num_sec; i++) { 837 last_read_idx = i; 838 839 /* 840 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 841 * CPU1 to CPU2. 842 * PAGING_SEPARATOR_SECTION delimiter - separate between 843 * CPU2 non paged to CPU2 paging sec. 844 */ 845 if (!image->sec[i].data || 846 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 847 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 848 IWL_DEBUG_FW(trans, 849 "Break since Data not valid or Empty section, sec = %d\n", 850 i); 851 break; 852 } 853 854 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 855 if (ret) 856 return ret; 857 858 /* Notify ucode of loaded section number and status */ 859 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 860 val = val | (sec_num << shift_param); 861 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 862 863 sec_num = (sec_num << 1) | 0x1; 864 } 865 866 *first_ucode_section = last_read_idx; 867 868 iwl_enable_interrupts(trans); 869 870 if (trans->cfg->use_tfh) { 871 if (cpu == 1) 872 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 873 0xFFFF); 874 else 875 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 876 0xFFFFFFFF); 877 } else { 878 if (cpu == 1) 879 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 880 0xFFFF); 881 else 882 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 883 0xFFFFFFFF); 884 } 885 886 return 0; 887 } 888 889 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 890 const struct fw_img *image, 891 int cpu, 892 int *first_ucode_section) 893 { 894 int i, ret = 0; 895 u32 last_read_idx = 0; 896 897 if (cpu == 1) 898 *first_ucode_section = 0; 899 else 900 (*first_ucode_section)++; 901 902 for (i = *first_ucode_section; i < image->num_sec; i++) { 903 last_read_idx = i; 904 905 /* 906 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 907 * CPU1 to CPU2. 908 * PAGING_SEPARATOR_SECTION delimiter - separate between 909 * CPU2 non paged to CPU2 paging sec. 910 */ 911 if (!image->sec[i].data || 912 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 913 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 914 IWL_DEBUG_FW(trans, 915 "Break since Data not valid or Empty section, sec = %d\n", 916 i); 917 break; 918 } 919 920 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 921 if (ret) 922 return ret; 923 } 924 925 *first_ucode_section = last_read_idx; 926 927 return 0; 928 } 929 930 void iwl_pcie_apply_destination(struct iwl_trans *trans) 931 { 932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 933 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 934 int i; 935 936 IWL_INFO(trans, "Applying debug destination %s\n", 937 get_fw_dbg_mode_string(dest->monitor_mode)); 938 939 if (dest->monitor_mode == EXTERNAL_MODE) 940 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 941 else 942 IWL_WARN(trans, "PCI should have external buffer debug\n"); 943 944 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 945 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 946 u32 val = le32_to_cpu(dest->reg_ops[i].val); 947 948 switch (dest->reg_ops[i].op) { 949 case CSR_ASSIGN: 950 iwl_write32(trans, addr, val); 951 break; 952 case CSR_SETBIT: 953 iwl_set_bit(trans, addr, BIT(val)); 954 break; 955 case CSR_CLEARBIT: 956 iwl_clear_bit(trans, addr, BIT(val)); 957 break; 958 case PRPH_ASSIGN: 959 iwl_write_prph(trans, addr, val); 960 break; 961 case PRPH_SETBIT: 962 iwl_set_bits_prph(trans, addr, BIT(val)); 963 break; 964 case PRPH_CLEARBIT: 965 iwl_clear_bits_prph(trans, addr, BIT(val)); 966 break; 967 case PRPH_BLOCKBIT: 968 if (iwl_read_prph(trans, addr) & BIT(val)) { 969 IWL_ERR(trans, 970 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 971 val, addr); 972 goto monitor; 973 } 974 break; 975 default: 976 IWL_ERR(trans, "FW debug - unknown OP %d\n", 977 dest->reg_ops[i].op); 978 break; 979 } 980 } 981 982 monitor: 983 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 984 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 985 trans_pcie->fw_mon_phys >> dest->base_shift); 986 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 987 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 988 (trans_pcie->fw_mon_phys + 989 trans_pcie->fw_mon_size - 256) >> 990 dest->end_shift); 991 else 992 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 993 (trans_pcie->fw_mon_phys + 994 trans_pcie->fw_mon_size) >> 995 dest->end_shift); 996 } 997 } 998 999 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1000 const struct fw_img *image) 1001 { 1002 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1003 int ret = 0; 1004 int first_ucode_section; 1005 1006 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1007 image->is_dual_cpus ? "Dual" : "Single"); 1008 1009 /* load to FW the binary non secured sections of CPU1 */ 1010 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1011 if (ret) 1012 return ret; 1013 1014 if (image->is_dual_cpus) { 1015 /* set CPU2 header address */ 1016 iwl_write_prph(trans, 1017 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1018 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1019 1020 /* load to FW the binary sections of CPU2 */ 1021 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1022 &first_ucode_section); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 /* supported for 7000 only for the moment */ 1028 if (iwlwifi_mod_params.fw_monitor && 1029 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1030 iwl_pcie_alloc_fw_monitor(trans, 0); 1031 1032 if (trans_pcie->fw_mon_size) { 1033 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1034 trans_pcie->fw_mon_phys >> 4); 1035 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1036 (trans_pcie->fw_mon_phys + 1037 trans_pcie->fw_mon_size) >> 4); 1038 } 1039 } else if (trans->dbg_dest_tlv) { 1040 iwl_pcie_apply_destination(trans); 1041 } 1042 1043 iwl_enable_interrupts(trans); 1044 1045 /* release CPU reset */ 1046 iwl_write32(trans, CSR_RESET, 0); 1047 1048 return 0; 1049 } 1050 1051 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1052 const struct fw_img *image) 1053 { 1054 int ret = 0; 1055 int first_ucode_section; 1056 1057 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1058 image->is_dual_cpus ? "Dual" : "Single"); 1059 1060 if (trans->dbg_dest_tlv) 1061 iwl_pcie_apply_destination(trans); 1062 1063 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1064 iwl_read_prph(trans, WFPM_GP2)); 1065 1066 /* 1067 * Set default value. On resume reading the values that were 1068 * zeored can provide debug data on the resume flow. 1069 * This is for debugging only and has no functional impact. 1070 */ 1071 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1072 1073 /* configure the ucode to be ready to get the secured image */ 1074 /* release CPU reset */ 1075 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1076 1077 /* load to FW the binary Secured sections of CPU1 */ 1078 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1079 &first_ucode_section); 1080 if (ret) 1081 return ret; 1082 1083 /* load to FW the binary sections of CPU2 */ 1084 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1085 &first_ucode_section); 1086 } 1087 1088 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1089 { 1090 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1091 bool hw_rfkill = iwl_is_rfkill_set(trans); 1092 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1093 bool report; 1094 1095 if (hw_rfkill) { 1096 set_bit(STATUS_RFKILL_HW, &trans->status); 1097 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1098 } else { 1099 clear_bit(STATUS_RFKILL_HW, &trans->status); 1100 if (trans_pcie->opmode_down) 1101 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1102 } 1103 1104 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1105 1106 if (prev != report) 1107 iwl_trans_pcie_rf_kill(trans, report); 1108 1109 return hw_rfkill; 1110 } 1111 1112 struct iwl_causes_list { 1113 u32 cause_num; 1114 u32 mask_reg; 1115 u8 addr; 1116 }; 1117 1118 static struct iwl_causes_list causes_list[] = { 1119 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1120 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1121 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1122 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1123 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1124 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1125 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1126 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1127 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1128 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1129 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1130 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1131 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1132 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1133 }; 1134 1135 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1136 { 1137 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1138 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1139 int i; 1140 1141 /* 1142 * Access all non RX causes and map them to the default irq. 1143 * In case we are missing at least one interrupt vector, 1144 * the first interrupt vector will serve non-RX and FBQ causes. 1145 */ 1146 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1147 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1148 iwl_clear_bit(trans, causes_list[i].mask_reg, 1149 causes_list[i].cause_num); 1150 } 1151 } 1152 1153 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1154 { 1155 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1156 u32 offset = 1157 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1158 u32 val, idx; 1159 1160 /* 1161 * The first RX queue - fallback queue, which is designated for 1162 * management frame, command responses etc, is always mapped to the 1163 * first interrupt vector. The other RX queues are mapped to 1164 * the other (N - 2) interrupt vectors. 1165 */ 1166 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1167 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1168 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1169 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1170 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1171 } 1172 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1173 1174 val = MSIX_FH_INT_CAUSES_Q(0); 1175 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1176 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1177 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1178 1179 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1180 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1181 } 1182 1183 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1184 { 1185 struct iwl_trans *trans = trans_pcie->trans; 1186 1187 if (!trans_pcie->msix_enabled) { 1188 if (trans->cfg->mq_rx_supported && 1189 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1190 iwl_write_prph(trans, UREG_CHICK, 1191 UREG_CHICK_MSI_ENABLE); 1192 return; 1193 } 1194 /* 1195 * The IVAR table needs to be configured again after reset, 1196 * but if the device is disabled, we can't write to 1197 * prph. 1198 */ 1199 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1200 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1201 1202 /* 1203 * Each cause from the causes list above and the RX causes is 1204 * represented as a byte in the IVAR table. The first nibble 1205 * represents the bound interrupt vector of the cause, the second 1206 * represents no auto clear for this cause. This will be set if its 1207 * interrupt vector is bound to serve other causes. 1208 */ 1209 iwl_pcie_map_rx_causes(trans); 1210 1211 iwl_pcie_map_non_rx_causes(trans); 1212 } 1213 1214 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1215 { 1216 struct iwl_trans *trans = trans_pcie->trans; 1217 1218 iwl_pcie_conf_msix_hw(trans_pcie); 1219 1220 if (!trans_pcie->msix_enabled) 1221 return; 1222 1223 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1224 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1225 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1226 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1227 } 1228 1229 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1230 { 1231 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1232 1233 lockdep_assert_held(&trans_pcie->mutex); 1234 1235 if (trans_pcie->is_down) 1236 return; 1237 1238 trans_pcie->is_down = true; 1239 1240 /* Stop dbgc before stopping device */ 1241 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1242 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 1243 } else { 1244 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); 1245 udelay(100); 1246 iwl_write_prph(trans, DBGC_OUT_CTRL, 0); 1247 } 1248 1249 /* tell the device to stop sending interrupts */ 1250 iwl_disable_interrupts(trans); 1251 1252 /* device going down, Stop using ICT table */ 1253 iwl_pcie_disable_ict(trans); 1254 1255 /* 1256 * If a HW restart happens during firmware loading, 1257 * then the firmware loading might call this function 1258 * and later it might be called again due to the 1259 * restart. So don't process again if the device is 1260 * already dead. 1261 */ 1262 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1263 IWL_DEBUG_INFO(trans, 1264 "DEVICE_ENABLED bit was set and is now cleared\n"); 1265 iwl_pcie_tx_stop(trans); 1266 iwl_pcie_rx_stop(trans); 1267 1268 /* Power-down device's busmaster DMA clocks */ 1269 if (!trans->cfg->apmg_not_supported) { 1270 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1271 APMG_CLK_VAL_DMA_CLK_RQT); 1272 udelay(5); 1273 } 1274 } 1275 1276 /* Make sure (redundant) we've released our request to stay awake */ 1277 iwl_clear_bit(trans, CSR_GP_CNTRL, 1278 BIT(trans->cfg->csr->flag_mac_access_req)); 1279 1280 /* Stop the device, and put it in low power state */ 1281 iwl_pcie_apm_stop(trans, false); 1282 1283 iwl_trans_pcie_sw_reset(trans); 1284 1285 /* 1286 * Upon stop, the IVAR table gets erased, so msi-x won't 1287 * work. This causes a bug in RF-KILL flows, since the interrupt 1288 * that enables radio won't fire on the correct irq, and the 1289 * driver won't be able to handle the interrupt. 1290 * Configure the IVAR table again after reset. 1291 */ 1292 iwl_pcie_conf_msix_hw(trans_pcie); 1293 1294 /* 1295 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1296 * This is a bug in certain verions of the hardware. 1297 * Certain devices also keep sending HW RF kill interrupt all 1298 * the time, unless the interrupt is ACKed even if the interrupt 1299 * should be masked. Re-ACK all the interrupts here. 1300 */ 1301 iwl_disable_interrupts(trans); 1302 1303 /* clear all status bits */ 1304 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1305 clear_bit(STATUS_INT_ENABLED, &trans->status); 1306 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1307 1308 /* 1309 * Even if we stop the HW, we still want the RF kill 1310 * interrupt 1311 */ 1312 iwl_enable_rfkill_int(trans); 1313 1314 /* re-take ownership to prevent other users from stealing the device */ 1315 iwl_pcie_prepare_card_hw(trans); 1316 } 1317 1318 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1319 { 1320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1321 1322 if (trans_pcie->msix_enabled) { 1323 int i; 1324 1325 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1326 synchronize_irq(trans_pcie->msix_entries[i].vector); 1327 } else { 1328 synchronize_irq(trans_pcie->pci_dev->irq); 1329 } 1330 } 1331 1332 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1333 const struct fw_img *fw, bool run_in_rfkill) 1334 { 1335 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1336 bool hw_rfkill; 1337 int ret; 1338 1339 /* This may fail if AMT took ownership of the device */ 1340 if (iwl_pcie_prepare_card_hw(trans)) { 1341 IWL_WARN(trans, "Exit HW not ready\n"); 1342 ret = -EIO; 1343 goto out; 1344 } 1345 1346 iwl_enable_rfkill_int(trans); 1347 1348 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1349 1350 /* 1351 * We enabled the RF-Kill interrupt and the handler may very 1352 * well be running. Disable the interrupts to make sure no other 1353 * interrupt can be fired. 1354 */ 1355 iwl_disable_interrupts(trans); 1356 1357 /* Make sure it finished running */ 1358 iwl_pcie_synchronize_irqs(trans); 1359 1360 mutex_lock(&trans_pcie->mutex); 1361 1362 /* If platform's RF_KILL switch is NOT set to KILL */ 1363 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1364 if (hw_rfkill && !run_in_rfkill) { 1365 ret = -ERFKILL; 1366 goto out; 1367 } 1368 1369 /* Someone called stop_device, don't try to start_fw */ 1370 if (trans_pcie->is_down) { 1371 IWL_WARN(trans, 1372 "Can't start_fw since the HW hasn't been started\n"); 1373 ret = -EIO; 1374 goto out; 1375 } 1376 1377 /* make sure rfkill handshake bits are cleared */ 1378 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1379 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1380 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1381 1382 /* clear (again), then enable host interrupts */ 1383 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1384 1385 ret = iwl_pcie_nic_init(trans); 1386 if (ret) { 1387 IWL_ERR(trans, "Unable to init nic\n"); 1388 goto out; 1389 } 1390 1391 /* 1392 * Now, we load the firmware and don't want to be interrupted, even 1393 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1394 * FH_TX interrupt which is needed to load the firmware). If the 1395 * RF-Kill switch is toggled, we will find out after having loaded 1396 * the firmware and return the proper value to the caller. 1397 */ 1398 iwl_enable_fw_load_int(trans); 1399 1400 /* really make sure rfkill handshake bits are cleared */ 1401 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1402 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1403 1404 /* Load the given image to the HW */ 1405 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1406 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1407 else 1408 ret = iwl_pcie_load_given_ucode(trans, fw); 1409 1410 /* re-check RF-Kill state since we may have missed the interrupt */ 1411 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1412 if (hw_rfkill && !run_in_rfkill) 1413 ret = -ERFKILL; 1414 1415 out: 1416 mutex_unlock(&trans_pcie->mutex); 1417 return ret; 1418 } 1419 1420 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1421 { 1422 iwl_pcie_reset_ict(trans); 1423 iwl_pcie_tx_start(trans, scd_addr); 1424 } 1425 1426 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1427 bool was_in_rfkill) 1428 { 1429 bool hw_rfkill; 1430 1431 /* 1432 * Check again since the RF kill state may have changed while 1433 * all the interrupts were disabled, in this case we couldn't 1434 * receive the RF kill interrupt and update the state in the 1435 * op_mode. 1436 * Don't call the op_mode if the rkfill state hasn't changed. 1437 * This allows the op_mode to call stop_device from the rfkill 1438 * notification without endless recursion. Under very rare 1439 * circumstances, we might have a small recursion if the rfkill 1440 * state changed exactly now while we were called from stop_device. 1441 * This is very unlikely but can happen and is supported. 1442 */ 1443 hw_rfkill = iwl_is_rfkill_set(trans); 1444 if (hw_rfkill) { 1445 set_bit(STATUS_RFKILL_HW, &trans->status); 1446 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1447 } else { 1448 clear_bit(STATUS_RFKILL_HW, &trans->status); 1449 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1450 } 1451 if (hw_rfkill != was_in_rfkill) 1452 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1453 } 1454 1455 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1456 { 1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1458 bool was_in_rfkill; 1459 1460 mutex_lock(&trans_pcie->mutex); 1461 trans_pcie->opmode_down = true; 1462 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1463 _iwl_trans_pcie_stop_device(trans, low_power); 1464 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1465 mutex_unlock(&trans_pcie->mutex); 1466 } 1467 1468 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1469 { 1470 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1471 IWL_TRANS_GET_PCIE_TRANS(trans); 1472 1473 lockdep_assert_held(&trans_pcie->mutex); 1474 1475 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1476 state ? "disabled" : "enabled"); 1477 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1478 if (trans->cfg->gen2) 1479 _iwl_trans_pcie_gen2_stop_device(trans, true); 1480 else 1481 _iwl_trans_pcie_stop_device(trans, true); 1482 } 1483 } 1484 1485 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1486 bool reset) 1487 { 1488 if (!reset) { 1489 /* Enable persistence mode to avoid reset */ 1490 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1491 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1492 } 1493 1494 iwl_disable_interrupts(trans); 1495 1496 /* 1497 * in testing mode, the host stays awake and the 1498 * hardware won't be reset (not even partially) 1499 */ 1500 if (test) 1501 return; 1502 1503 iwl_pcie_disable_ict(trans); 1504 1505 iwl_pcie_synchronize_irqs(trans); 1506 1507 iwl_clear_bit(trans, CSR_GP_CNTRL, 1508 BIT(trans->cfg->csr->flag_mac_access_req)); 1509 iwl_clear_bit(trans, CSR_GP_CNTRL, 1510 BIT(trans->cfg->csr->flag_init_done)); 1511 1512 iwl_pcie_enable_rx_wake(trans, false); 1513 1514 if (reset) { 1515 /* 1516 * reset TX queues -- some of their registers reset during S3 1517 * so if we don't reset everything here the D3 image would try 1518 * to execute some invalid memory upon resume 1519 */ 1520 iwl_trans_pcie_tx_reset(trans); 1521 } 1522 1523 iwl_pcie_set_pwr(trans, true); 1524 } 1525 1526 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1527 enum iwl_d3_status *status, 1528 bool test, bool reset) 1529 { 1530 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1531 u32 val; 1532 int ret; 1533 1534 if (test) { 1535 iwl_enable_interrupts(trans); 1536 *status = IWL_D3_STATUS_ALIVE; 1537 return 0; 1538 } 1539 1540 iwl_pcie_enable_rx_wake(trans, true); 1541 1542 /* 1543 * Reconfigure IVAR table in case of MSIX or reset ict table in 1544 * MSI mode since HW reset erased it. 1545 * Also enables interrupts - none will happen as 1546 * the device doesn't know we're waking it up, only when 1547 * the opmode actually tells it after this call. 1548 */ 1549 iwl_pcie_conf_msix_hw(trans_pcie); 1550 if (!trans_pcie->msix_enabled) 1551 iwl_pcie_reset_ict(trans); 1552 iwl_enable_interrupts(trans); 1553 1554 iwl_set_bit(trans, CSR_GP_CNTRL, 1555 BIT(trans->cfg->csr->flag_mac_access_req)); 1556 iwl_set_bit(trans, CSR_GP_CNTRL, 1557 BIT(trans->cfg->csr->flag_init_done)); 1558 1559 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1560 udelay(2); 1561 1562 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1563 BIT(trans->cfg->csr->flag_mac_clock_ready), 1564 BIT(trans->cfg->csr->flag_mac_clock_ready), 1565 25000); 1566 if (ret < 0) { 1567 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1568 return ret; 1569 } 1570 1571 iwl_pcie_set_pwr(trans, false); 1572 1573 if (!reset) { 1574 iwl_clear_bit(trans, CSR_GP_CNTRL, 1575 BIT(trans->cfg->csr->flag_mac_access_req)); 1576 } else { 1577 iwl_trans_pcie_tx_reset(trans); 1578 1579 ret = iwl_pcie_rx_init(trans); 1580 if (ret) { 1581 IWL_ERR(trans, 1582 "Failed to resume the device (RX reset)\n"); 1583 return ret; 1584 } 1585 } 1586 1587 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1588 iwl_read_prph(trans, WFPM_GP2)); 1589 1590 val = iwl_read32(trans, CSR_RESET); 1591 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1592 *status = IWL_D3_STATUS_RESET; 1593 else 1594 *status = IWL_D3_STATUS_ALIVE; 1595 1596 return 0; 1597 } 1598 1599 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1600 struct iwl_trans *trans) 1601 { 1602 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1603 int max_irqs, num_irqs, i, ret; 1604 u16 pci_cmd; 1605 1606 if (!trans->cfg->mq_rx_supported) 1607 goto enable_msi; 1608 1609 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 1610 for (i = 0; i < max_irqs; i++) 1611 trans_pcie->msix_entries[i].entry = i; 1612 1613 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1614 MSIX_MIN_INTERRUPT_VECTORS, 1615 max_irqs); 1616 if (num_irqs < 0) { 1617 IWL_DEBUG_INFO(trans, 1618 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1619 num_irqs); 1620 goto enable_msi; 1621 } 1622 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1623 1624 IWL_DEBUG_INFO(trans, 1625 "MSI-X enabled. %d interrupt vectors were allocated\n", 1626 num_irqs); 1627 1628 /* 1629 * In case the OS provides fewer interrupts than requested, different 1630 * causes will share the same interrupt vector as follows: 1631 * One interrupt less: non rx causes shared with FBQ. 1632 * Two interrupts less: non rx causes shared with FBQ and RSS. 1633 * More than two interrupts: we will use fewer RSS queues. 1634 */ 1635 if (num_irqs <= max_irqs - 2) { 1636 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1637 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1638 IWL_SHARED_IRQ_FIRST_RSS; 1639 } else if (num_irqs == max_irqs - 1) { 1640 trans_pcie->trans->num_rx_queues = num_irqs; 1641 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1642 } else { 1643 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1644 } 1645 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1646 1647 trans_pcie->alloc_vecs = num_irqs; 1648 trans_pcie->msix_enabled = true; 1649 return; 1650 1651 enable_msi: 1652 ret = pci_enable_msi(pdev); 1653 if (ret) { 1654 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1655 /* enable rfkill interrupt: hw bug w/a */ 1656 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1657 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1658 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1659 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1660 } 1661 } 1662 } 1663 1664 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1665 { 1666 int iter_rx_q, i, ret, cpu, offset; 1667 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1668 1669 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1670 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1671 offset = 1 + i; 1672 for (; i < iter_rx_q ; i++) { 1673 /* 1674 * Get the cpu prior to the place to search 1675 * (i.e. return will be > i - 1). 1676 */ 1677 cpu = cpumask_next(i - offset, cpu_online_mask); 1678 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1679 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1680 &trans_pcie->affinity_mask[i]); 1681 if (ret) 1682 IWL_ERR(trans_pcie->trans, 1683 "Failed to set affinity mask for IRQ %d\n", 1684 i); 1685 } 1686 } 1687 1688 static const char *queue_name(struct device *dev, 1689 struct iwl_trans_pcie *trans_p, int i) 1690 { 1691 if (trans_p->shared_vec_mask) { 1692 int vec = trans_p->shared_vec_mask & 1693 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1694 1695 if (i == 0) 1696 return DRV_NAME ": shared IRQ"; 1697 1698 return devm_kasprintf(dev, GFP_KERNEL, 1699 DRV_NAME ": queue %d", i + vec); 1700 } 1701 if (i == 0) 1702 return DRV_NAME ": default queue"; 1703 1704 if (i == trans_p->alloc_vecs - 1) 1705 return DRV_NAME ": exception"; 1706 1707 return devm_kasprintf(dev, GFP_KERNEL, 1708 DRV_NAME ": queue %d", i); 1709 } 1710 1711 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1712 struct iwl_trans_pcie *trans_pcie) 1713 { 1714 int i; 1715 1716 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1717 int ret; 1718 struct msix_entry *msix_entry; 1719 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1720 1721 if (!qname) 1722 return -ENOMEM; 1723 1724 msix_entry = &trans_pcie->msix_entries[i]; 1725 ret = devm_request_threaded_irq(&pdev->dev, 1726 msix_entry->vector, 1727 iwl_pcie_msix_isr, 1728 (i == trans_pcie->def_irq) ? 1729 iwl_pcie_irq_msix_handler : 1730 iwl_pcie_irq_rx_msix_handler, 1731 IRQF_SHARED, 1732 qname, 1733 msix_entry); 1734 if (ret) { 1735 IWL_ERR(trans_pcie->trans, 1736 "Error allocating IRQ %d\n", i); 1737 1738 return ret; 1739 } 1740 } 1741 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1742 1743 return 0; 1744 } 1745 1746 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1747 { 1748 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1749 int err; 1750 1751 lockdep_assert_held(&trans_pcie->mutex); 1752 1753 err = iwl_pcie_prepare_card_hw(trans); 1754 if (err) { 1755 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1756 return err; 1757 } 1758 1759 iwl_trans_pcie_sw_reset(trans); 1760 1761 err = iwl_pcie_apm_init(trans); 1762 if (err) 1763 return err; 1764 1765 iwl_pcie_init_msix(trans_pcie); 1766 1767 /* From now on, the op_mode will be kept updated about RF kill state */ 1768 iwl_enable_rfkill_int(trans); 1769 1770 trans_pcie->opmode_down = false; 1771 1772 /* Set is_down to false here so that...*/ 1773 trans_pcie->is_down = false; 1774 1775 /* ...rfkill can call stop_device and set it false if needed */ 1776 iwl_pcie_check_hw_rf_kill(trans); 1777 1778 /* Make sure we sync here, because we'll need full access later */ 1779 if (low_power) 1780 pm_runtime_resume(trans->dev); 1781 1782 return 0; 1783 } 1784 1785 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1786 { 1787 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1788 int ret; 1789 1790 mutex_lock(&trans_pcie->mutex); 1791 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1792 mutex_unlock(&trans_pcie->mutex); 1793 1794 return ret; 1795 } 1796 1797 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1798 { 1799 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1800 1801 mutex_lock(&trans_pcie->mutex); 1802 1803 /* disable interrupts - don't enable HW RF kill interrupt */ 1804 iwl_disable_interrupts(trans); 1805 1806 iwl_pcie_apm_stop(trans, true); 1807 1808 iwl_disable_interrupts(trans); 1809 1810 iwl_pcie_disable_ict(trans); 1811 1812 mutex_unlock(&trans_pcie->mutex); 1813 1814 iwl_pcie_synchronize_irqs(trans); 1815 } 1816 1817 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1818 { 1819 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1820 } 1821 1822 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1823 { 1824 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1825 } 1826 1827 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1828 { 1829 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1830 } 1831 1832 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1833 { 1834 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1835 ((reg & 0x000FFFFF) | (3 << 24))); 1836 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1837 } 1838 1839 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1840 u32 val) 1841 { 1842 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1843 ((addr & 0x000FFFFF) | (3 << 24))); 1844 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1845 } 1846 1847 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1848 const struct iwl_trans_config *trans_cfg) 1849 { 1850 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1851 1852 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1853 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1854 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1855 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1856 trans_pcie->n_no_reclaim_cmds = 0; 1857 else 1858 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1859 if (trans_pcie->n_no_reclaim_cmds) 1860 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1861 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1862 1863 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1864 trans_pcie->rx_page_order = 1865 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1866 1867 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1868 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1869 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1870 1871 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1872 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1873 1874 trans->command_groups = trans_cfg->command_groups; 1875 trans->command_groups_size = trans_cfg->command_groups_size; 1876 1877 /* Initialize NAPI here - it should be before registering to mac80211 1878 * in the opmode but after the HW struct is allocated. 1879 * As this function may be called again in some corner cases don't 1880 * do anything if NAPI was already initialized. 1881 */ 1882 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1883 init_dummy_netdev(&trans_pcie->napi_dev); 1884 } 1885 1886 void iwl_trans_pcie_free(struct iwl_trans *trans) 1887 { 1888 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1889 int i; 1890 1891 iwl_pcie_synchronize_irqs(trans); 1892 1893 if (trans->cfg->gen2) 1894 iwl_pcie_gen2_tx_free(trans); 1895 else 1896 iwl_pcie_tx_free(trans); 1897 iwl_pcie_rx_free(trans); 1898 1899 if (trans_pcie->rba.alloc_wq) { 1900 destroy_workqueue(trans_pcie->rba.alloc_wq); 1901 trans_pcie->rba.alloc_wq = NULL; 1902 } 1903 1904 if (trans_pcie->msix_enabled) { 1905 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1906 irq_set_affinity_hint( 1907 trans_pcie->msix_entries[i].vector, 1908 NULL); 1909 } 1910 1911 trans_pcie->msix_enabled = false; 1912 } else { 1913 iwl_pcie_free_ict(trans); 1914 } 1915 1916 iwl_pcie_free_fw_monitor(trans); 1917 1918 for_each_possible_cpu(i) { 1919 struct iwl_tso_hdr_page *p = 1920 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1921 1922 if (p->page) 1923 __free_page(p->page); 1924 } 1925 1926 free_percpu(trans_pcie->tso_hdr_page); 1927 mutex_destroy(&trans_pcie->mutex); 1928 iwl_trans_free(trans); 1929 } 1930 1931 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1932 { 1933 if (state) 1934 set_bit(STATUS_TPOWER_PMI, &trans->status); 1935 else 1936 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1937 } 1938 1939 struct iwl_trans_pcie_removal { 1940 struct pci_dev *pdev; 1941 struct work_struct work; 1942 }; 1943 1944 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 1945 { 1946 struct iwl_trans_pcie_removal *removal = 1947 container_of(wk, struct iwl_trans_pcie_removal, work); 1948 struct pci_dev *pdev = removal->pdev; 1949 char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 1950 1951 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 1952 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 1953 pci_lock_rescan_remove(); 1954 pci_dev_put(pdev); 1955 pci_stop_and_remove_bus_device(pdev); 1956 pci_unlock_rescan_remove(); 1957 1958 kfree(removal); 1959 module_put(THIS_MODULE); 1960 } 1961 1962 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1963 unsigned long *flags) 1964 { 1965 int ret; 1966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1967 1968 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1969 1970 if (trans_pcie->cmd_hold_nic_awake) 1971 goto out; 1972 1973 /* this bit wakes up the NIC */ 1974 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1975 BIT(trans->cfg->csr->flag_mac_access_req)); 1976 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1977 udelay(2); 1978 1979 /* 1980 * These bits say the device is running, and should keep running for 1981 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1982 * but they do not indicate that embedded SRAM is restored yet; 1983 * HW with volatile SRAM must save/restore contents to/from 1984 * host DRAM when sleeping/waking for power-saving. 1985 * Each direction takes approximately 1/4 millisecond; with this 1986 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1987 * series of register accesses are expected (e.g. reading Event Log), 1988 * to keep device from sleeping. 1989 * 1990 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1991 * SRAM is okay/restored. We don't check that here because this call 1992 * is just for hardware register access; but GP1 MAC_SLEEP 1993 * check is a good idea before accessing the SRAM of HW with 1994 * volatile SRAM (e.g. reading Event Log). 1995 * 1996 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1997 * and do not save/restore SRAM when power cycling. 1998 */ 1999 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2000 BIT(trans->cfg->csr->flag_val_mac_access_en), 2001 (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2002 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2003 if (unlikely(ret < 0)) { 2004 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2005 2006 WARN_ONCE(1, 2007 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2008 cntrl); 2009 2010 iwl_trans_pcie_dump_regs(trans); 2011 2012 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2013 struct iwl_trans_pcie_removal *removal; 2014 2015 if (trans_pcie->scheduled_for_removal) 2016 goto err; 2017 2018 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2019 2020 /* 2021 * get a module reference to avoid doing this 2022 * while unloading anyway and to avoid 2023 * scheduling a work with code that's being 2024 * removed. 2025 */ 2026 if (!try_module_get(THIS_MODULE)) { 2027 IWL_ERR(trans, 2028 "Module is being unloaded - abort\n"); 2029 goto err; 2030 } 2031 2032 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2033 if (!removal) { 2034 module_put(THIS_MODULE); 2035 goto err; 2036 } 2037 /* 2038 * we don't need to clear this flag, because 2039 * the trans will be freed and reallocated. 2040 */ 2041 trans_pcie->scheduled_for_removal = true; 2042 2043 removal->pdev = to_pci_dev(trans->dev); 2044 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2045 pci_dev_get(removal->pdev); 2046 schedule_work(&removal->work); 2047 } else { 2048 iwl_write32(trans, CSR_RESET, 2049 CSR_RESET_REG_FLAG_FORCE_NMI); 2050 } 2051 2052 err: 2053 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2054 return false; 2055 } 2056 2057 out: 2058 /* 2059 * Fool sparse by faking we release the lock - sparse will 2060 * track nic_access anyway. 2061 */ 2062 __release(&trans_pcie->reg_lock); 2063 return true; 2064 } 2065 2066 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2067 unsigned long *flags) 2068 { 2069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2070 2071 lockdep_assert_held(&trans_pcie->reg_lock); 2072 2073 /* 2074 * Fool sparse by faking we acquiring the lock - sparse will 2075 * track nic_access anyway. 2076 */ 2077 __acquire(&trans_pcie->reg_lock); 2078 2079 if (trans_pcie->cmd_hold_nic_awake) 2080 goto out; 2081 2082 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2083 BIT(trans->cfg->csr->flag_mac_access_req)); 2084 /* 2085 * Above we read the CSR_GP_CNTRL register, which will flush 2086 * any previous writes, but we need the write that clears the 2087 * MAC_ACCESS_REQ bit to be performed before any other writes 2088 * scheduled on different CPUs (after we drop reg_lock). 2089 */ 2090 mmiowb(); 2091 out: 2092 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2093 } 2094 2095 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2096 void *buf, int dwords) 2097 { 2098 unsigned long flags; 2099 int offs, ret = 0; 2100 u32 *vals = buf; 2101 2102 if (iwl_trans_grab_nic_access(trans, &flags)) { 2103 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2104 for (offs = 0; offs < dwords; offs++) 2105 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2106 iwl_trans_release_nic_access(trans, &flags); 2107 } else { 2108 ret = -EBUSY; 2109 } 2110 return ret; 2111 } 2112 2113 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2114 const void *buf, int dwords) 2115 { 2116 unsigned long flags; 2117 int offs, ret = 0; 2118 const u32 *vals = buf; 2119 2120 if (iwl_trans_grab_nic_access(trans, &flags)) { 2121 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2122 for (offs = 0; offs < dwords; offs++) 2123 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2124 vals ? vals[offs] : 0); 2125 iwl_trans_release_nic_access(trans, &flags); 2126 } else { 2127 ret = -EBUSY; 2128 } 2129 return ret; 2130 } 2131 2132 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2133 unsigned long txqs, 2134 bool freeze) 2135 { 2136 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2137 int queue; 2138 2139 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2140 struct iwl_txq *txq = trans_pcie->txq[queue]; 2141 unsigned long now; 2142 2143 spin_lock_bh(&txq->lock); 2144 2145 now = jiffies; 2146 2147 if (txq->frozen == freeze) 2148 goto next_queue; 2149 2150 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2151 freeze ? "Freezing" : "Waking", queue); 2152 2153 txq->frozen = freeze; 2154 2155 if (txq->read_ptr == txq->write_ptr) 2156 goto next_queue; 2157 2158 if (freeze) { 2159 if (unlikely(time_after(now, 2160 txq->stuck_timer.expires))) { 2161 /* 2162 * The timer should have fired, maybe it is 2163 * spinning right now on the lock. 2164 */ 2165 goto next_queue; 2166 } 2167 /* remember how long until the timer fires */ 2168 txq->frozen_expiry_remainder = 2169 txq->stuck_timer.expires - now; 2170 del_timer(&txq->stuck_timer); 2171 goto next_queue; 2172 } 2173 2174 /* 2175 * Wake a non-empty queue -> arm timer with the 2176 * remainder before it froze 2177 */ 2178 mod_timer(&txq->stuck_timer, 2179 now + txq->frozen_expiry_remainder); 2180 2181 next_queue: 2182 spin_unlock_bh(&txq->lock); 2183 } 2184 } 2185 2186 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2187 { 2188 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2189 int i; 2190 2191 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2192 struct iwl_txq *txq = trans_pcie->txq[i]; 2193 2194 if (i == trans_pcie->cmd_queue) 2195 continue; 2196 2197 spin_lock_bh(&txq->lock); 2198 2199 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2200 txq->block--; 2201 if (!txq->block) { 2202 iwl_write32(trans, HBUS_TARG_WRPTR, 2203 txq->write_ptr | (i << 8)); 2204 } 2205 } else if (block) { 2206 txq->block++; 2207 } 2208 2209 spin_unlock_bh(&txq->lock); 2210 } 2211 } 2212 2213 #define IWL_FLUSH_WAIT_MS 2000 2214 2215 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2216 { 2217 u32 txq_id = txq->id; 2218 u32 status; 2219 bool active; 2220 u8 fifo; 2221 2222 if (trans->cfg->use_tfh) { 2223 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2224 txq->read_ptr, txq->write_ptr); 2225 /* TODO: access new SCD registers and dump them */ 2226 return; 2227 } 2228 2229 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2230 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2231 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2232 2233 IWL_ERR(trans, 2234 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2235 txq_id, active ? "" : "in", fifo, 2236 jiffies_to_msecs(txq->wd_timeout), 2237 txq->read_ptr, txq->write_ptr, 2238 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2239 (TFD_QUEUE_SIZE_MAX - 1), 2240 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2241 (TFD_QUEUE_SIZE_MAX - 1), 2242 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2243 } 2244 2245 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2246 { 2247 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2248 struct iwl_txq *txq; 2249 unsigned long now = jiffies; 2250 u8 wr_ptr; 2251 2252 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2253 return -EINVAL; 2254 2255 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2256 txq = trans_pcie->txq[txq_idx]; 2257 wr_ptr = READ_ONCE(txq->write_ptr); 2258 2259 while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2260 !time_after(jiffies, 2261 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2262 u8 write_ptr = READ_ONCE(txq->write_ptr); 2263 2264 if (WARN_ONCE(wr_ptr != write_ptr, 2265 "WR pointer moved while flushing %d -> %d\n", 2266 wr_ptr, write_ptr)) 2267 return -ETIMEDOUT; 2268 usleep_range(1000, 2000); 2269 } 2270 2271 if (txq->read_ptr != txq->write_ptr) { 2272 IWL_ERR(trans, 2273 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2274 iwl_trans_pcie_log_scd_error(trans, txq); 2275 return -ETIMEDOUT; 2276 } 2277 2278 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2279 2280 return 0; 2281 } 2282 2283 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2284 { 2285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2286 int cnt; 2287 int ret = 0; 2288 2289 /* waiting for all the tx frames complete might take a while */ 2290 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2291 2292 if (cnt == trans_pcie->cmd_queue) 2293 continue; 2294 if (!test_bit(cnt, trans_pcie->queue_used)) 2295 continue; 2296 if (!(BIT(cnt) & txq_bm)) 2297 continue; 2298 2299 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2300 if (ret) 2301 break; 2302 } 2303 2304 return ret; 2305 } 2306 2307 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2308 u32 mask, u32 value) 2309 { 2310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2311 unsigned long flags; 2312 2313 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2314 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2315 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2316 } 2317 2318 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2319 { 2320 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2321 2322 if (iwlwifi_mod_params.d0i3_disable) 2323 return; 2324 2325 pm_runtime_get(&trans_pcie->pci_dev->dev); 2326 2327 #ifdef CONFIG_PM 2328 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2329 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2330 #endif /* CONFIG_PM */ 2331 } 2332 2333 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2334 { 2335 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2336 2337 if (iwlwifi_mod_params.d0i3_disable) 2338 return; 2339 2340 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2341 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2342 2343 #ifdef CONFIG_PM 2344 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2345 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2346 #endif /* CONFIG_PM */ 2347 } 2348 2349 static const char *get_csr_string(int cmd) 2350 { 2351 #define IWL_CMD(x) case x: return #x 2352 switch (cmd) { 2353 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2354 IWL_CMD(CSR_INT_COALESCING); 2355 IWL_CMD(CSR_INT); 2356 IWL_CMD(CSR_INT_MASK); 2357 IWL_CMD(CSR_FH_INT_STATUS); 2358 IWL_CMD(CSR_GPIO_IN); 2359 IWL_CMD(CSR_RESET); 2360 IWL_CMD(CSR_GP_CNTRL); 2361 IWL_CMD(CSR_HW_REV); 2362 IWL_CMD(CSR_EEPROM_REG); 2363 IWL_CMD(CSR_EEPROM_GP); 2364 IWL_CMD(CSR_OTP_GP_REG); 2365 IWL_CMD(CSR_GIO_REG); 2366 IWL_CMD(CSR_GP_UCODE_REG); 2367 IWL_CMD(CSR_GP_DRIVER_REG); 2368 IWL_CMD(CSR_UCODE_DRV_GP1); 2369 IWL_CMD(CSR_UCODE_DRV_GP2); 2370 IWL_CMD(CSR_LED_REG); 2371 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2372 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2373 IWL_CMD(CSR_ANA_PLL_CFG); 2374 IWL_CMD(CSR_HW_REV_WA_REG); 2375 IWL_CMD(CSR_MONITOR_STATUS_REG); 2376 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2377 default: 2378 return "UNKNOWN"; 2379 } 2380 #undef IWL_CMD 2381 } 2382 2383 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2384 { 2385 int i; 2386 static const u32 csr_tbl[] = { 2387 CSR_HW_IF_CONFIG_REG, 2388 CSR_INT_COALESCING, 2389 CSR_INT, 2390 CSR_INT_MASK, 2391 CSR_FH_INT_STATUS, 2392 CSR_GPIO_IN, 2393 CSR_RESET, 2394 CSR_GP_CNTRL, 2395 CSR_HW_REV, 2396 CSR_EEPROM_REG, 2397 CSR_EEPROM_GP, 2398 CSR_OTP_GP_REG, 2399 CSR_GIO_REG, 2400 CSR_GP_UCODE_REG, 2401 CSR_GP_DRIVER_REG, 2402 CSR_UCODE_DRV_GP1, 2403 CSR_UCODE_DRV_GP2, 2404 CSR_LED_REG, 2405 CSR_DRAM_INT_TBL_REG, 2406 CSR_GIO_CHICKEN_BITS, 2407 CSR_ANA_PLL_CFG, 2408 CSR_MONITOR_STATUS_REG, 2409 CSR_HW_REV_WA_REG, 2410 CSR_DBG_HPET_MEM_REG 2411 }; 2412 IWL_ERR(trans, "CSR values:\n"); 2413 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2414 "CSR_INT_PERIODIC_REG)\n"); 2415 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2416 IWL_ERR(trans, " %25s: 0X%08x\n", 2417 get_csr_string(csr_tbl[i]), 2418 iwl_read32(trans, csr_tbl[i])); 2419 } 2420 } 2421 2422 #ifdef CONFIG_IWLWIFI_DEBUGFS 2423 /* create and remove of files */ 2424 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2425 if (!debugfs_create_file(#name, mode, parent, trans, \ 2426 &iwl_dbgfs_##name##_ops)) \ 2427 goto err; \ 2428 } while (0) 2429 2430 /* file operation */ 2431 #define DEBUGFS_READ_FILE_OPS(name) \ 2432 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2433 .read = iwl_dbgfs_##name##_read, \ 2434 .open = simple_open, \ 2435 .llseek = generic_file_llseek, \ 2436 }; 2437 2438 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2439 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2440 .write = iwl_dbgfs_##name##_write, \ 2441 .open = simple_open, \ 2442 .llseek = generic_file_llseek, \ 2443 }; 2444 2445 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2446 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2447 .write = iwl_dbgfs_##name##_write, \ 2448 .read = iwl_dbgfs_##name##_read, \ 2449 .open = simple_open, \ 2450 .llseek = generic_file_llseek, \ 2451 }; 2452 2453 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2454 char __user *user_buf, 2455 size_t count, loff_t *ppos) 2456 { 2457 struct iwl_trans *trans = file->private_data; 2458 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2459 struct iwl_txq *txq; 2460 char *buf; 2461 int pos = 0; 2462 int cnt; 2463 int ret; 2464 size_t bufsz; 2465 2466 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2467 2468 if (!trans_pcie->txq_memory) 2469 return -EAGAIN; 2470 2471 buf = kzalloc(bufsz, GFP_KERNEL); 2472 if (!buf) 2473 return -ENOMEM; 2474 2475 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2476 txq = trans_pcie->txq[cnt]; 2477 pos += scnprintf(buf + pos, bufsz - pos, 2478 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2479 cnt, txq->read_ptr, txq->write_ptr, 2480 !!test_bit(cnt, trans_pcie->queue_used), 2481 !!test_bit(cnt, trans_pcie->queue_stopped), 2482 txq->need_update, txq->frozen, 2483 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2484 } 2485 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2486 kfree(buf); 2487 return ret; 2488 } 2489 2490 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2491 char __user *user_buf, 2492 size_t count, loff_t *ppos) 2493 { 2494 struct iwl_trans *trans = file->private_data; 2495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2496 char *buf; 2497 int pos = 0, i, ret; 2498 size_t bufsz = sizeof(buf); 2499 2500 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2501 2502 if (!trans_pcie->rxq) 2503 return -EAGAIN; 2504 2505 buf = kzalloc(bufsz, GFP_KERNEL); 2506 if (!buf) 2507 return -ENOMEM; 2508 2509 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2510 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2511 2512 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2513 i); 2514 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2515 rxq->read); 2516 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2517 rxq->write); 2518 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2519 rxq->write_actual); 2520 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2521 rxq->need_update); 2522 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2523 rxq->free_count); 2524 if (rxq->rb_stts) { 2525 pos += scnprintf(buf + pos, bufsz - pos, 2526 "\tclosed_rb_num: %u\n", 2527 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2528 0x0FFF); 2529 } else { 2530 pos += scnprintf(buf + pos, bufsz - pos, 2531 "\tclosed_rb_num: Not Allocated\n"); 2532 } 2533 } 2534 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2535 kfree(buf); 2536 2537 return ret; 2538 } 2539 2540 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2541 char __user *user_buf, 2542 size_t count, loff_t *ppos) 2543 { 2544 struct iwl_trans *trans = file->private_data; 2545 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2546 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2547 2548 int pos = 0; 2549 char *buf; 2550 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2551 ssize_t ret; 2552 2553 buf = kzalloc(bufsz, GFP_KERNEL); 2554 if (!buf) 2555 return -ENOMEM; 2556 2557 pos += scnprintf(buf + pos, bufsz - pos, 2558 "Interrupt Statistics Report:\n"); 2559 2560 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2561 isr_stats->hw); 2562 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2563 isr_stats->sw); 2564 if (isr_stats->sw || isr_stats->hw) { 2565 pos += scnprintf(buf + pos, bufsz - pos, 2566 "\tLast Restarting Code: 0x%X\n", 2567 isr_stats->err_code); 2568 } 2569 #ifdef CONFIG_IWLWIFI_DEBUG 2570 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2571 isr_stats->sch); 2572 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2573 isr_stats->alive); 2574 #endif 2575 pos += scnprintf(buf + pos, bufsz - pos, 2576 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2577 2578 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2579 isr_stats->ctkill); 2580 2581 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2582 isr_stats->wakeup); 2583 2584 pos += scnprintf(buf + pos, bufsz - pos, 2585 "Rx command responses:\t\t %u\n", isr_stats->rx); 2586 2587 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2588 isr_stats->tx); 2589 2590 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2591 isr_stats->unhandled); 2592 2593 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2594 kfree(buf); 2595 return ret; 2596 } 2597 2598 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2599 const char __user *user_buf, 2600 size_t count, loff_t *ppos) 2601 { 2602 struct iwl_trans *trans = file->private_data; 2603 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2604 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2605 u32 reset_flag; 2606 int ret; 2607 2608 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2609 if (ret) 2610 return ret; 2611 if (reset_flag == 0) 2612 memset(isr_stats, 0, sizeof(*isr_stats)); 2613 2614 return count; 2615 } 2616 2617 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2618 const char __user *user_buf, 2619 size_t count, loff_t *ppos) 2620 { 2621 struct iwl_trans *trans = file->private_data; 2622 2623 iwl_pcie_dump_csr(trans); 2624 2625 return count; 2626 } 2627 2628 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2629 char __user *user_buf, 2630 size_t count, loff_t *ppos) 2631 { 2632 struct iwl_trans *trans = file->private_data; 2633 char *buf = NULL; 2634 ssize_t ret; 2635 2636 ret = iwl_dump_fh(trans, &buf); 2637 if (ret < 0) 2638 return ret; 2639 if (!buf) 2640 return -EINVAL; 2641 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2642 kfree(buf); 2643 return ret; 2644 } 2645 2646 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2647 char __user *user_buf, 2648 size_t count, loff_t *ppos) 2649 { 2650 struct iwl_trans *trans = file->private_data; 2651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2652 char buf[100]; 2653 int pos; 2654 2655 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2656 trans_pcie->debug_rfkill, 2657 !(iwl_read32(trans, CSR_GP_CNTRL) & 2658 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2659 2660 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2661 } 2662 2663 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2664 const char __user *user_buf, 2665 size_t count, loff_t *ppos) 2666 { 2667 struct iwl_trans *trans = file->private_data; 2668 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2669 bool old = trans_pcie->debug_rfkill; 2670 int ret; 2671 2672 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2673 if (ret) 2674 return ret; 2675 if (old == trans_pcie->debug_rfkill) 2676 return count; 2677 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2678 old, trans_pcie->debug_rfkill); 2679 iwl_pcie_handle_rfkill_irq(trans); 2680 2681 return count; 2682 } 2683 2684 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2685 DEBUGFS_READ_FILE_OPS(fh_reg); 2686 DEBUGFS_READ_FILE_OPS(rx_queue); 2687 DEBUGFS_READ_FILE_OPS(tx_queue); 2688 DEBUGFS_WRITE_FILE_OPS(csr); 2689 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2690 2691 /* Create the debugfs files and directories */ 2692 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2693 { 2694 struct dentry *dir = trans->dbgfs_dir; 2695 2696 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2697 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2698 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2699 DEBUGFS_ADD_FILE(csr, dir, 0200); 2700 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2701 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2702 return 0; 2703 2704 err: 2705 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2706 return -ENOMEM; 2707 } 2708 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2709 2710 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2711 { 2712 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2713 u32 cmdlen = 0; 2714 int i; 2715 2716 for (i = 0; i < trans_pcie->max_tbs; i++) 2717 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2718 2719 return cmdlen; 2720 } 2721 2722 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2723 struct iwl_fw_error_dump_data **data, 2724 int allocated_rb_nums) 2725 { 2726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2727 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2728 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2729 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2730 u32 i, r, j, rb_len = 0; 2731 2732 spin_lock(&rxq->lock); 2733 2734 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2735 2736 for (i = rxq->read, j = 0; 2737 i != r && j < allocated_rb_nums; 2738 i = (i + 1) & RX_QUEUE_MASK, j++) { 2739 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2740 struct iwl_fw_error_dump_rb *rb; 2741 2742 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2743 DMA_FROM_DEVICE); 2744 2745 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2746 2747 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2748 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2749 rb = (void *)(*data)->data; 2750 rb->index = cpu_to_le32(i); 2751 memcpy(rb->data, page_address(rxb->page), max_len); 2752 /* remap the page for the free benefit */ 2753 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2754 max_len, 2755 DMA_FROM_DEVICE); 2756 2757 *data = iwl_fw_error_next_data(*data); 2758 } 2759 2760 spin_unlock(&rxq->lock); 2761 2762 return rb_len; 2763 } 2764 #define IWL_CSR_TO_DUMP (0x250) 2765 2766 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2767 struct iwl_fw_error_dump_data **data) 2768 { 2769 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2770 __le32 *val; 2771 int i; 2772 2773 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2774 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2775 val = (void *)(*data)->data; 2776 2777 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2778 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2779 2780 *data = iwl_fw_error_next_data(*data); 2781 2782 return csr_len; 2783 } 2784 2785 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2786 struct iwl_fw_error_dump_data **data) 2787 { 2788 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2789 unsigned long flags; 2790 __le32 *val; 2791 int i; 2792 2793 if (!iwl_trans_grab_nic_access(trans, &flags)) 2794 return 0; 2795 2796 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2797 (*data)->len = cpu_to_le32(fh_regs_len); 2798 val = (void *)(*data)->data; 2799 2800 if (!trans->cfg->gen2) 2801 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2802 i += sizeof(u32)) 2803 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2804 else 2805 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2806 i += sizeof(u32)) 2807 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2808 i)); 2809 2810 iwl_trans_release_nic_access(trans, &flags); 2811 2812 *data = iwl_fw_error_next_data(*data); 2813 2814 return sizeof(**data) + fh_regs_len; 2815 } 2816 2817 static u32 2818 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2819 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2820 u32 monitor_len) 2821 { 2822 u32 buf_size_in_dwords = (monitor_len >> 2); 2823 u32 *buffer = (u32 *)fw_mon_data->data; 2824 unsigned long flags; 2825 u32 i; 2826 2827 if (!iwl_trans_grab_nic_access(trans, &flags)) 2828 return 0; 2829 2830 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2831 for (i = 0; i < buf_size_in_dwords; i++) 2832 buffer[i] = iwl_read_prph_no_grab(trans, 2833 MON_DMARB_RD_DATA_ADDR); 2834 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2835 2836 iwl_trans_release_nic_access(trans, &flags); 2837 2838 return monitor_len; 2839 } 2840 2841 static u32 2842 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2843 struct iwl_fw_error_dump_data **data, 2844 u32 monitor_len) 2845 { 2846 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2847 u32 len = 0; 2848 2849 if ((trans_pcie->fw_mon_page && 2850 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2851 trans->dbg_dest_tlv) { 2852 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2853 u32 base, write_ptr, wrap_cnt; 2854 2855 /* If there was a dest TLV - use the values from there */ 2856 if (trans->dbg_dest_tlv) { 2857 write_ptr = 2858 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2859 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2860 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2861 } else { 2862 base = MON_BUFF_BASE_ADDR; 2863 write_ptr = MON_BUFF_WRPTR; 2864 wrap_cnt = MON_BUFF_CYCLE_CNT; 2865 } 2866 2867 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2868 fw_mon_data = (void *)(*data)->data; 2869 fw_mon_data->fw_mon_wr_ptr = 2870 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2871 fw_mon_data->fw_mon_cycle_cnt = 2872 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2873 fw_mon_data->fw_mon_base_ptr = 2874 cpu_to_le32(iwl_read_prph(trans, base)); 2875 2876 len += sizeof(**data) + sizeof(*fw_mon_data); 2877 if (trans_pcie->fw_mon_page) { 2878 /* 2879 * The firmware is now asserted, it won't write anything 2880 * to the buffer. CPU can take ownership to fetch the 2881 * data. The buffer will be handed back to the device 2882 * before the firmware will be restarted. 2883 */ 2884 dma_sync_single_for_cpu(trans->dev, 2885 trans_pcie->fw_mon_phys, 2886 trans_pcie->fw_mon_size, 2887 DMA_FROM_DEVICE); 2888 memcpy(fw_mon_data->data, 2889 page_address(trans_pcie->fw_mon_page), 2890 trans_pcie->fw_mon_size); 2891 2892 monitor_len = trans_pcie->fw_mon_size; 2893 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2894 /* 2895 * Update pointers to reflect actual values after 2896 * shifting 2897 */ 2898 if (trans->dbg_dest_tlv->version) { 2899 base = (iwl_read_prph(trans, base) & 2900 IWL_LDBG_M2S_BUF_BA_MSK) << 2901 trans->dbg_dest_tlv->base_shift; 2902 base *= IWL_M2S_UNIT_SIZE; 2903 base += trans->cfg->smem_offset; 2904 } else { 2905 base = iwl_read_prph(trans, base) << 2906 trans->dbg_dest_tlv->base_shift; 2907 } 2908 2909 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2910 monitor_len / sizeof(u32)); 2911 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2912 monitor_len = 2913 iwl_trans_pci_dump_marbh_monitor(trans, 2914 fw_mon_data, 2915 monitor_len); 2916 } else { 2917 /* Didn't match anything - output no monitor data */ 2918 monitor_len = 0; 2919 } 2920 2921 len += monitor_len; 2922 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2923 } 2924 2925 return len; 2926 } 2927 2928 static struct iwl_trans_dump_data 2929 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2930 const struct iwl_fw_dbg_trigger_tlv *trigger) 2931 { 2932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2933 struct iwl_fw_error_dump_data *data; 2934 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2935 struct iwl_fw_error_dump_txcmd *txcmd; 2936 struct iwl_trans_dump_data *dump_data; 2937 u32 len, num_rbs; 2938 u32 monitor_len; 2939 int i, ptr; 2940 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2941 !trans->cfg->mq_rx_supported; 2942 2943 /* transport dump header */ 2944 len = sizeof(*dump_data); 2945 2946 /* host commands */ 2947 len += sizeof(*data) + 2948 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2949 2950 /* FW monitor */ 2951 if (trans_pcie->fw_mon_page) { 2952 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2953 trans_pcie->fw_mon_size; 2954 monitor_len = trans_pcie->fw_mon_size; 2955 } else if (trans->dbg_dest_tlv) { 2956 u32 base, end, cfg_reg; 2957 2958 if (trans->dbg_dest_tlv->version == 1) { 2959 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2960 cfg_reg = iwl_read_prph(trans, cfg_reg); 2961 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 2962 trans->dbg_dest_tlv->base_shift; 2963 base *= IWL_M2S_UNIT_SIZE; 2964 base += trans->cfg->smem_offset; 2965 2966 monitor_len = 2967 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 2968 trans->dbg_dest_tlv->end_shift; 2969 monitor_len *= IWL_M2S_UNIT_SIZE; 2970 } else { 2971 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2972 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2973 2974 base = iwl_read_prph(trans, base) << 2975 trans->dbg_dest_tlv->base_shift; 2976 end = iwl_read_prph(trans, end) << 2977 trans->dbg_dest_tlv->end_shift; 2978 2979 /* Make "end" point to the actual end */ 2980 if (trans->cfg->device_family >= 2981 IWL_DEVICE_FAMILY_8000 || 2982 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2983 end += (1 << trans->dbg_dest_tlv->end_shift); 2984 monitor_len = end - base; 2985 } 2986 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2987 monitor_len; 2988 } else { 2989 monitor_len = 0; 2990 } 2991 2992 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2993 dump_data = vzalloc(len); 2994 if (!dump_data) 2995 return NULL; 2996 2997 data = (void *)dump_data->data; 2998 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2999 dump_data->len = len; 3000 3001 return dump_data; 3002 } 3003 3004 /* CSR registers */ 3005 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3006 3007 /* FH registers */ 3008 if (trans->cfg->gen2) 3009 len += sizeof(*data) + 3010 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2); 3011 else 3012 len += sizeof(*data) + 3013 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 3014 3015 if (dump_rbs) { 3016 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3017 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3018 /* RBs */ 3019 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) 3020 & 0x0FFF; 3021 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3022 len += num_rbs * (sizeof(*data) + 3023 sizeof(struct iwl_fw_error_dump_rb) + 3024 (PAGE_SIZE << trans_pcie->rx_page_order)); 3025 } 3026 3027 /* Paged memory for gen2 HW */ 3028 if (trans->cfg->gen2) 3029 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 3030 len += sizeof(*data) + 3031 sizeof(struct iwl_fw_error_dump_paging) + 3032 trans_pcie->init_dram.paging[i].size; 3033 3034 dump_data = vzalloc(len); 3035 if (!dump_data) 3036 return NULL; 3037 3038 len = 0; 3039 data = (void *)dump_data->data; 3040 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3041 txcmd = (void *)data->data; 3042 spin_lock_bh(&cmdq->lock); 3043 ptr = cmdq->write_ptr; 3044 for (i = 0; i < cmdq->n_window; i++) { 3045 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3046 u32 caplen, cmdlen; 3047 3048 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 3049 trans_pcie->tfd_size * ptr); 3050 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3051 3052 if (cmdlen) { 3053 len += sizeof(*txcmd) + caplen; 3054 txcmd->cmdlen = cpu_to_le32(cmdlen); 3055 txcmd->caplen = cpu_to_le32(caplen); 3056 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 3057 txcmd = (void *)((u8 *)txcmd->data + caplen); 3058 } 3059 3060 ptr = iwl_queue_dec_wrap(ptr); 3061 } 3062 spin_unlock_bh(&cmdq->lock); 3063 3064 data->len = cpu_to_le32(len); 3065 len += sizeof(*data); 3066 data = iwl_fw_error_next_data(data); 3067 3068 len += iwl_trans_pcie_dump_csr(trans, &data); 3069 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3070 if (dump_rbs) 3071 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3072 3073 /* Paged memory for gen2 HW */ 3074 if (trans->cfg->gen2) { 3075 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 3076 struct iwl_fw_error_dump_paging *paging; 3077 dma_addr_t addr = 3078 trans_pcie->init_dram.paging[i].physical; 3079 u32 page_len = trans_pcie->init_dram.paging[i].size; 3080 3081 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3082 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3083 paging = (void *)data->data; 3084 paging->index = cpu_to_le32(i); 3085 dma_sync_single_for_cpu(trans->dev, addr, page_len, 3086 DMA_BIDIRECTIONAL); 3087 memcpy(paging->data, 3088 trans_pcie->init_dram.paging[i].block, page_len); 3089 data = iwl_fw_error_next_data(data); 3090 3091 len += sizeof(*data) + sizeof(*paging) + page_len; 3092 } 3093 } 3094 3095 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3096 3097 dump_data->len = len; 3098 3099 return dump_data; 3100 } 3101 3102 #ifdef CONFIG_PM_SLEEP 3103 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3104 { 3105 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3106 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3107 return iwl_pci_fw_enter_d0i3(trans); 3108 3109 return 0; 3110 } 3111 3112 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3113 { 3114 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3115 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3116 iwl_pci_fw_exit_d0i3(trans); 3117 } 3118 #endif /* CONFIG_PM_SLEEP */ 3119 3120 #define IWL_TRANS_COMMON_OPS \ 3121 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3122 .write8 = iwl_trans_pcie_write8, \ 3123 .write32 = iwl_trans_pcie_write32, \ 3124 .read32 = iwl_trans_pcie_read32, \ 3125 .read_prph = iwl_trans_pcie_read_prph, \ 3126 .write_prph = iwl_trans_pcie_write_prph, \ 3127 .read_mem = iwl_trans_pcie_read_mem, \ 3128 .write_mem = iwl_trans_pcie_write_mem, \ 3129 .configure = iwl_trans_pcie_configure, \ 3130 .set_pmi = iwl_trans_pcie_set_pmi, \ 3131 .sw_reset = iwl_trans_pcie_sw_reset, \ 3132 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3133 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3134 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3135 .ref = iwl_trans_pcie_ref, \ 3136 .unref = iwl_trans_pcie_unref, \ 3137 .dump_data = iwl_trans_pcie_dump_data, \ 3138 .dump_regs = iwl_trans_pcie_dump_regs, \ 3139 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3140 .d3_resume = iwl_trans_pcie_d3_resume 3141 3142 #ifdef CONFIG_PM_SLEEP 3143 #define IWL_TRANS_PM_OPS \ 3144 .suspend = iwl_trans_pcie_suspend, \ 3145 .resume = iwl_trans_pcie_resume, 3146 #else 3147 #define IWL_TRANS_PM_OPS 3148 #endif /* CONFIG_PM_SLEEP */ 3149 3150 static const struct iwl_trans_ops trans_ops_pcie = { 3151 IWL_TRANS_COMMON_OPS, 3152 IWL_TRANS_PM_OPS 3153 .start_hw = iwl_trans_pcie_start_hw, 3154 .fw_alive = iwl_trans_pcie_fw_alive, 3155 .start_fw = iwl_trans_pcie_start_fw, 3156 .stop_device = iwl_trans_pcie_stop_device, 3157 3158 .send_cmd = iwl_trans_pcie_send_hcmd, 3159 3160 .tx = iwl_trans_pcie_tx, 3161 .reclaim = iwl_trans_pcie_reclaim, 3162 3163 .txq_disable = iwl_trans_pcie_txq_disable, 3164 .txq_enable = iwl_trans_pcie_txq_enable, 3165 3166 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3167 3168 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3169 3170 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3171 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3172 }; 3173 3174 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3175 IWL_TRANS_COMMON_OPS, 3176 IWL_TRANS_PM_OPS 3177 .start_hw = iwl_trans_pcie_start_hw, 3178 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3179 .start_fw = iwl_trans_pcie_gen2_start_fw, 3180 .stop_device = iwl_trans_pcie_gen2_stop_device, 3181 3182 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3183 3184 .tx = iwl_trans_pcie_gen2_tx, 3185 .reclaim = iwl_trans_pcie_reclaim, 3186 3187 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3188 .txq_free = iwl_trans_pcie_dyn_txq_free, 3189 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3190 }; 3191 3192 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3193 const struct pci_device_id *ent, 3194 const struct iwl_cfg *cfg) 3195 { 3196 struct iwl_trans_pcie *trans_pcie; 3197 struct iwl_trans *trans; 3198 int ret, addr_size; 3199 3200 ret = pcim_enable_device(pdev); 3201 if (ret) 3202 return ERR_PTR(ret); 3203 3204 if (cfg->gen2) 3205 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3206 &pdev->dev, cfg, &trans_ops_pcie_gen2); 3207 else 3208 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3209 &pdev->dev, cfg, &trans_ops_pcie); 3210 if (!trans) 3211 return ERR_PTR(-ENOMEM); 3212 3213 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3214 3215 trans_pcie->trans = trans; 3216 trans_pcie->opmode_down = true; 3217 spin_lock_init(&trans_pcie->irq_lock); 3218 spin_lock_init(&trans_pcie->reg_lock); 3219 mutex_init(&trans_pcie->mutex); 3220 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3221 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3222 if (!trans_pcie->tso_hdr_page) { 3223 ret = -ENOMEM; 3224 goto out_no_pci; 3225 } 3226 3227 3228 if (!cfg->base_params->pcie_l1_allowed) { 3229 /* 3230 * W/A - seems to solve weird behavior. We need to remove this 3231 * if we don't want to stay in L1 all the time. This wastes a 3232 * lot of power. 3233 */ 3234 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3235 PCIE_LINK_STATE_L1 | 3236 PCIE_LINK_STATE_CLKPM); 3237 } 3238 3239 if (cfg->use_tfh) { 3240 addr_size = 64; 3241 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3242 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3243 } else { 3244 addr_size = 36; 3245 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3246 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3247 } 3248 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3249 3250 pci_set_master(pdev); 3251 3252 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3253 if (!ret) 3254 ret = pci_set_consistent_dma_mask(pdev, 3255 DMA_BIT_MASK(addr_size)); 3256 if (ret) { 3257 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3258 if (!ret) 3259 ret = pci_set_consistent_dma_mask(pdev, 3260 DMA_BIT_MASK(32)); 3261 /* both attempts failed: */ 3262 if (ret) { 3263 dev_err(&pdev->dev, "No suitable DMA available\n"); 3264 goto out_no_pci; 3265 } 3266 } 3267 3268 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3269 if (ret) { 3270 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3271 goto out_no_pci; 3272 } 3273 3274 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3275 if (!trans_pcie->hw_base) { 3276 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3277 ret = -ENODEV; 3278 goto out_no_pci; 3279 } 3280 3281 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3282 * PCI Tx retries from interfering with C3 CPU state */ 3283 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3284 3285 trans_pcie->pci_dev = pdev; 3286 iwl_disable_interrupts(trans); 3287 3288 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3289 /* 3290 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3291 * changed, and now the revision step also includes bit 0-1 (no more 3292 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3293 * in the old format. 3294 */ 3295 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3296 unsigned long flags; 3297 3298 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3299 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3300 3301 ret = iwl_pcie_prepare_card_hw(trans); 3302 if (ret) { 3303 IWL_WARN(trans, "Exit HW not ready\n"); 3304 goto out_no_pci; 3305 } 3306 3307 /* 3308 * in-order to recognize C step driver should read chip version 3309 * id located at the AUX bus MISC address space. 3310 */ 3311 iwl_set_bit(trans, CSR_GP_CNTRL, 3312 BIT(trans->cfg->csr->flag_init_done)); 3313 udelay(2); 3314 3315 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3316 BIT(trans->cfg->csr->flag_mac_clock_ready), 3317 BIT(trans->cfg->csr->flag_mac_clock_ready), 3318 25000); 3319 if (ret < 0) { 3320 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3321 goto out_no_pci; 3322 } 3323 3324 if (iwl_trans_grab_nic_access(trans, &flags)) { 3325 u32 hw_step; 3326 3327 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3328 hw_step |= ENABLE_WFPM; 3329 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3330 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3331 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3332 if (hw_step == 0x3) 3333 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3334 (SILICON_C_STEP << 2); 3335 iwl_trans_release_nic_access(trans, &flags); 3336 } 3337 } 3338 3339 /* 3340 * 9000-series integrated A-step has a problem with suspend/resume 3341 * and sometimes even causes the whole platform to get stuck. This 3342 * workaround makes the hardware not go into the problematic state. 3343 */ 3344 if (trans->cfg->integrated && 3345 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3346 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3347 iwl_set_bit(trans, CSR_HOST_CHICKEN, 3348 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3349 3350 #if IS_ENABLED(CONFIG_IWLMVM) 3351 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3352 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) { 3353 u32 hw_status; 3354 3355 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3356 if (hw_status & UMAG_GEN_HW_IS_FPGA) 3357 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_f0; 3358 else 3359 trans->cfg = &iwl22000_2ac_cfg_hr; 3360 } 3361 #endif 3362 3363 iwl_pcie_set_interrupt_capa(pdev, trans); 3364 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3365 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3366 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3367 3368 /* Initialize the wait queue for commands */ 3369 init_waitqueue_head(&trans_pcie->wait_command_queue); 3370 3371 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3372 3373 if (trans_pcie->msix_enabled) { 3374 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3375 if (ret) 3376 goto out_no_pci; 3377 } else { 3378 ret = iwl_pcie_alloc_ict(trans); 3379 if (ret) 3380 goto out_no_pci; 3381 3382 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3383 iwl_pcie_isr, 3384 iwl_pcie_irq_handler, 3385 IRQF_SHARED, DRV_NAME, trans); 3386 if (ret) { 3387 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3388 goto out_free_ict; 3389 } 3390 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3391 } 3392 3393 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3394 WQ_HIGHPRI | WQ_UNBOUND, 1); 3395 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3396 3397 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3398 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3399 #else 3400 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3401 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3402 3403 return trans; 3404 3405 out_free_ict: 3406 iwl_pcie_free_ict(trans); 3407 out_no_pci: 3408 free_percpu(trans_pcie->tso_hdr_page); 3409 iwl_trans_free(trans); 3410 return ERR_PTR(ret); 3411 } 3412