1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "fw/error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92 { 93 #define PCI_DUMP_SIZE 64 94 #define PREFIX_LEN 32 95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96 struct pci_dev *pdev = trans_pcie->pci_dev; 97 u32 i, pos, alloc_size, *ptr, *buf; 98 char *prefix; 99 100 if (trans_pcie->pcie_dbg_dumped_once) 101 return; 102 103 /* Should be a multiple of 4 */ 104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105 /* Alloc a max size buffer */ 106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108 else 109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110 buf = kmalloc(alloc_size, GFP_ATOMIC); 111 if (!buf) 112 return; 113 prefix = (char *)buf + alloc_size - PREFIX_LEN; 114 115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116 117 /* Print wifi device registers */ 118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119 IWL_ERR(trans, "iwlwifi device config registers:\n"); 120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121 if (pci_read_config_dword(pdev, i, ptr)) 122 goto err_read; 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127 *ptr = iwl_read32(trans, i); 128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129 130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131 if (pos) { 132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134 if (pci_read_config_dword(pdev, pos + i, ptr)) 135 goto err_read; 136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137 32, 4, buf, i, 0); 138 } 139 140 /* Print parent device registers next */ 141 if (!pdev->bus->self) 142 goto out; 143 144 pdev = pdev->bus->self; 145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146 147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148 pci_name(pdev)); 149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150 if (pci_read_config_dword(pdev, i, ptr)) 151 goto err_read; 152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153 154 /* Print root port AER registers */ 155 pos = 0; 156 pdev = pcie_find_root_port(pdev); 157 if (pdev) 158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159 if (pos) { 160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161 pci_name(pdev)); 162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164 if (pci_read_config_dword(pdev, pos + i, ptr)) 165 goto err_read; 166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167 4, buf, i, 0); 168 } 169 goto out; 170 171 err_read: 172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173 IWL_ERR(trans, "Read failed at 0x%X\n", i); 174 out: 175 trans_pcie->pcie_dbg_dumped_once = 1; 176 kfree(buf); 177 } 178 179 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 180 { 181 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 182 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 183 usleep_range(5000, 6000); 184 } 185 186 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 187 { 188 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 189 190 if (!trans_pcie->fw_mon_page) 191 return; 192 193 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 194 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 195 __free_pages(trans_pcie->fw_mon_page, 196 get_order(trans_pcie->fw_mon_size)); 197 trans_pcie->fw_mon_page = NULL; 198 trans_pcie->fw_mon_phys = 0; 199 trans_pcie->fw_mon_size = 0; 200 } 201 202 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 203 { 204 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 205 struct page *page = NULL; 206 dma_addr_t phys; 207 u32 size = 0; 208 u8 power; 209 210 if (!max_power) { 211 /* default max_power is maximum */ 212 max_power = 26; 213 } else { 214 max_power += 11; 215 } 216 217 if (WARN(max_power > 26, 218 "External buffer size for monitor is too big %d, check the FW TLV\n", 219 max_power)) 220 return; 221 222 if (trans_pcie->fw_mon_page) { 223 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 224 trans_pcie->fw_mon_size, 225 DMA_FROM_DEVICE); 226 return; 227 } 228 229 phys = 0; 230 for (power = max_power; power >= 11; power--) { 231 int order; 232 233 size = BIT(power); 234 order = get_order(size); 235 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 236 order); 237 if (!page) 238 continue; 239 240 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 241 DMA_FROM_DEVICE); 242 if (dma_mapping_error(trans->dev, phys)) { 243 __free_pages(page, order); 244 page = NULL; 245 continue; 246 } 247 IWL_INFO(trans, 248 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 249 size, order); 250 break; 251 } 252 253 if (WARN_ON_ONCE(!page)) 254 return; 255 256 if (power != max_power) 257 IWL_ERR(trans, 258 "Sorry - debug buffer is only %luK while you requested %luK\n", 259 (unsigned long)BIT(power - 10), 260 (unsigned long)BIT(max_power - 10)); 261 262 trans_pcie->fw_mon_page = page; 263 trans_pcie->fw_mon_phys = phys; 264 trans_pcie->fw_mon_size = size; 265 } 266 267 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 268 { 269 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 270 ((reg & 0x0000ffff) | (2 << 28))); 271 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 272 } 273 274 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 275 { 276 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 277 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 278 ((reg & 0x0000ffff) | (3 << 28))); 279 } 280 281 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 282 { 283 if (trans->cfg->apmg_not_supported) 284 return; 285 286 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 287 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 288 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 289 ~APMG_PS_CTRL_MSK_PWR_SRC); 290 else 291 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 292 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 293 ~APMG_PS_CTRL_MSK_PWR_SRC); 294 } 295 296 /* PCI registers */ 297 #define PCI_CFG_RETRY_TIMEOUT 0x041 298 299 void iwl_pcie_apm_config(struct iwl_trans *trans) 300 { 301 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 302 u16 lctl; 303 u16 cap; 304 305 /* 306 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 307 * Check if BIOS (or OS) enabled L1-ASPM on this device. 308 * If so (likely), disable L0S, so device moves directly L0->L1; 309 * costs negligible amount of power savings. 310 * If not (unlikely), enable L0S, so there is at least some 311 * power savings, even without L1. 312 */ 313 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 314 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 315 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 316 else 317 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 318 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 319 320 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 321 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 322 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 323 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 324 trans->ltr_enabled ? "En" : "Dis"); 325 } 326 327 /* 328 * Start up NIC's basic functionality after it has been reset 329 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 330 * NOTE: This does not load uCode nor start the embedded processor 331 */ 332 static int iwl_pcie_apm_init(struct iwl_trans *trans) 333 { 334 int ret; 335 336 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 337 338 /* 339 * Use "set_bit" below rather than "write", to preserve any hardware 340 * bits already set by default after reset. 341 */ 342 343 /* Disable L0S exit timer (platform NMI Work/Around) */ 344 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 345 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 346 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 347 348 /* 349 * Disable L0s without affecting L1; 350 * don't wait for ICH L0s (ICH bug W/A) 351 */ 352 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 353 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 354 355 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 356 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 357 358 /* 359 * Enable HAP INTA (interrupt from management bus) to 360 * wake device's PCI Express link L1a -> L0s 361 */ 362 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 363 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 364 365 iwl_pcie_apm_config(trans); 366 367 /* Configure analog phase-lock-loop before activating to D0A */ 368 if (trans->cfg->base_params->pll_cfg) 369 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 370 371 /* 372 * Set "initialization complete" bit to move adapter from 373 * D0U* --> D0A* (powered-up active) state. 374 */ 375 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 376 377 /* 378 * Wait for clock stabilization; once stabilized, access to 379 * device-internal resources is supported, e.g. iwl_write_prph() 380 * and accesses to uCode SRAM. 381 */ 382 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 384 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 385 if (ret < 0) { 386 IWL_ERR(trans, "Failed to init the card\n"); 387 return ret; 388 } 389 390 if (trans->cfg->host_interrupt_operation_mode) { 391 /* 392 * This is a bit of an abuse - This is needed for 7260 / 3160 393 * only check host_interrupt_operation_mode even if this is 394 * not related to host_interrupt_operation_mode. 395 * 396 * Enable the oscillator to count wake up time for L1 exit. This 397 * consumes slightly more power (100uA) - but allows to be sure 398 * that we wake up from L1 on time. 399 * 400 * This looks weird: read twice the same register, discard the 401 * value, set a bit, and yet again, read that same register 402 * just to discard the value. But that's the way the hardware 403 * seems to like it. 404 */ 405 iwl_read_prph(trans, OSC_CLK); 406 iwl_read_prph(trans, OSC_CLK); 407 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 408 iwl_read_prph(trans, OSC_CLK); 409 iwl_read_prph(trans, OSC_CLK); 410 } 411 412 /* 413 * Enable DMA clock and wait for it to stabilize. 414 * 415 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 416 * bits do not disable clocks. This preserves any hardware 417 * bits already set by default in "CLK_CTRL_REG" after reset. 418 */ 419 if (!trans->cfg->apmg_not_supported) { 420 iwl_write_prph(trans, APMG_CLK_EN_REG, 421 APMG_CLK_VAL_DMA_CLK_RQT); 422 udelay(20); 423 424 /* Disable L1-Active */ 425 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 426 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 427 428 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 429 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 430 APMG_RTC_INT_STT_RFKILL); 431 } 432 433 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 434 435 return 0; 436 } 437 438 /* 439 * Enable LP XTAL to avoid HW bug where device may consume much power if 440 * FW is not loaded after device reset. LP XTAL is disabled by default 441 * after device HW reset. Do it only if XTAL is fed by internal source. 442 * Configure device's "persistence" mode to avoid resetting XTAL again when 443 * SHRD_HW_RST occurs in S3. 444 */ 445 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 446 { 447 int ret; 448 u32 apmg_gp1_reg; 449 u32 apmg_xtal_cfg_reg; 450 u32 dl_cfg_reg; 451 452 /* Force XTAL ON */ 453 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 454 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 455 456 iwl_trans_pcie_sw_reset(trans); 457 458 /* 459 * Set "initialization complete" bit to move adapter from 460 * D0U* --> D0A* (powered-up active) state. 461 */ 462 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 463 464 /* 465 * Wait for clock stabilization; once stabilized, access to 466 * device-internal resources is possible. 467 */ 468 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 469 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 470 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 471 25000); 472 if (WARN_ON(ret < 0)) { 473 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 474 /* Release XTAL ON request */ 475 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 476 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 477 return; 478 } 479 480 /* 481 * Clear "disable persistence" to avoid LP XTAL resetting when 482 * SHRD_HW_RST is applied in S3. 483 */ 484 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 485 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 486 487 /* 488 * Force APMG XTAL to be active to prevent its disabling by HW 489 * caused by APMG idle state. 490 */ 491 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 492 SHR_APMG_XTAL_CFG_REG); 493 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 494 apmg_xtal_cfg_reg | 495 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 496 497 iwl_trans_pcie_sw_reset(trans); 498 499 /* Enable LP XTAL by indirect access through CSR */ 500 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 501 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 502 SHR_APMG_GP1_WF_XTAL_LP_EN | 503 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 504 505 /* Clear delay line clock power up */ 506 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 507 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 508 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 509 510 /* 511 * Enable persistence mode to avoid LP XTAL resetting when 512 * SHRD_HW_RST is applied in S3. 513 */ 514 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 515 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 516 517 /* 518 * Clear "initialization complete" bit to move adapter from 519 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 520 */ 521 iwl_clear_bit(trans, CSR_GP_CNTRL, 522 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 523 524 /* Activates XTAL resources monitor */ 525 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 526 CSR_MONITOR_XTAL_RESOURCES); 527 528 /* Release XTAL ON request */ 529 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 530 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 531 udelay(10); 532 533 /* Release APMG XTAL */ 534 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 535 apmg_xtal_cfg_reg & 536 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 537 } 538 539 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 540 { 541 int ret; 542 543 /* stop device's busmaster DMA activity */ 544 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 545 546 ret = iwl_poll_bit(trans, CSR_RESET, 547 CSR_RESET_REG_FLAG_MASTER_DISABLED, 548 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 549 if (ret < 0) 550 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 551 552 IWL_DEBUG_INFO(trans, "stop master\n"); 553 } 554 555 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 556 { 557 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 558 559 if (op_mode_leave) { 560 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 561 iwl_pcie_apm_init(trans); 562 563 /* inform ME that we are leaving */ 564 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 565 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 566 APMG_PCIDEV_STT_VAL_WAKE_ME); 567 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 568 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 569 CSR_RESET_LINK_PWR_MGMT_DISABLED); 570 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 571 CSR_HW_IF_CONFIG_REG_PREPARE | 572 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 573 mdelay(1); 574 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 575 CSR_RESET_LINK_PWR_MGMT_DISABLED); 576 } 577 mdelay(5); 578 } 579 580 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 581 582 /* Stop device's DMA activity */ 583 iwl_pcie_apm_stop_master(trans); 584 585 if (trans->cfg->lp_xtal_workaround) { 586 iwl_pcie_apm_lp_xtal_enable(trans); 587 return; 588 } 589 590 iwl_trans_pcie_sw_reset(trans); 591 592 /* 593 * Clear "initialization complete" bit to move adapter from 594 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 595 */ 596 iwl_clear_bit(trans, CSR_GP_CNTRL, 597 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 598 } 599 600 static int iwl_pcie_nic_init(struct iwl_trans *trans) 601 { 602 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 603 int ret; 604 605 /* nic_init */ 606 spin_lock(&trans_pcie->irq_lock); 607 ret = iwl_pcie_apm_init(trans); 608 spin_unlock(&trans_pcie->irq_lock); 609 610 if (ret) 611 return ret; 612 613 iwl_pcie_set_pwr(trans, false); 614 615 iwl_op_mode_nic_config(trans->op_mode); 616 617 /* Allocate the RX queue, or reset if it is already allocated */ 618 iwl_pcie_rx_init(trans); 619 620 /* Allocate or reset and init all Tx and Command queues */ 621 if (iwl_pcie_tx_init(trans)) 622 return -ENOMEM; 623 624 if (trans->cfg->base_params->shadow_reg_enable) { 625 /* enable shadow regs in HW */ 626 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 627 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 628 } 629 630 return 0; 631 } 632 633 #define HW_READY_TIMEOUT (50) 634 635 /* Note: returns poll_bit return value, which is >= 0 if success */ 636 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 637 { 638 int ret; 639 640 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 641 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 642 643 /* See if we got it */ 644 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 645 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 646 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 647 HW_READY_TIMEOUT); 648 649 if (ret >= 0) 650 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 651 652 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 653 return ret; 654 } 655 656 /* Note: returns standard 0/-ERROR code */ 657 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 658 { 659 int ret; 660 int t = 0; 661 int iter; 662 663 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 664 665 ret = iwl_pcie_set_hw_ready(trans); 666 /* If the card is ready, exit 0 */ 667 if (ret >= 0) 668 return 0; 669 670 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 671 CSR_RESET_LINK_PWR_MGMT_DISABLED); 672 usleep_range(1000, 2000); 673 674 for (iter = 0; iter < 10; iter++) { 675 /* If HW is not ready, prepare the conditions to check again */ 676 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 677 CSR_HW_IF_CONFIG_REG_PREPARE); 678 679 do { 680 ret = iwl_pcie_set_hw_ready(trans); 681 if (ret >= 0) 682 return 0; 683 684 usleep_range(200, 1000); 685 t += 200; 686 } while (t < 150000); 687 msleep(25); 688 } 689 690 IWL_ERR(trans, "Couldn't prepare the card\n"); 691 692 return ret; 693 } 694 695 /* 696 * ucode 697 */ 698 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 699 u32 dst_addr, dma_addr_t phy_addr, 700 u32 byte_cnt) 701 { 702 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 703 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 704 705 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 706 dst_addr); 707 708 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 709 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 710 711 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 712 (iwl_get_dma_hi_addr(phy_addr) 713 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 714 715 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 716 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 717 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 718 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 719 720 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 721 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 722 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 723 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 724 } 725 726 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 727 u32 dst_addr, dma_addr_t phy_addr, 728 u32 byte_cnt) 729 { 730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 731 unsigned long flags; 732 int ret; 733 734 trans_pcie->ucode_write_complete = false; 735 736 if (!iwl_trans_grab_nic_access(trans, &flags)) 737 return -EIO; 738 739 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 740 byte_cnt); 741 iwl_trans_release_nic_access(trans, &flags); 742 743 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 744 trans_pcie->ucode_write_complete, 5 * HZ); 745 if (!ret) { 746 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 747 iwl_trans_pcie_dump_regs(trans); 748 return -ETIMEDOUT; 749 } 750 751 return 0; 752 } 753 754 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 755 const struct fw_desc *section) 756 { 757 u8 *v_addr; 758 dma_addr_t p_addr; 759 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 760 int ret = 0; 761 762 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 763 section_num); 764 765 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 766 GFP_KERNEL | __GFP_NOWARN); 767 if (!v_addr) { 768 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 769 chunk_sz = PAGE_SIZE; 770 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 771 &p_addr, GFP_KERNEL); 772 if (!v_addr) 773 return -ENOMEM; 774 } 775 776 for (offset = 0; offset < section->len; offset += chunk_sz) { 777 u32 copy_size, dst_addr; 778 bool extended_addr = false; 779 780 copy_size = min_t(u32, chunk_sz, section->len - offset); 781 dst_addr = section->offset + offset; 782 783 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 784 dst_addr <= IWL_FW_MEM_EXTENDED_END) 785 extended_addr = true; 786 787 if (extended_addr) 788 iwl_set_bits_prph(trans, LMPM_CHICK, 789 LMPM_CHICK_EXTENDED_ADDR_SPACE); 790 791 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 792 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 793 copy_size); 794 795 if (extended_addr) 796 iwl_clear_bits_prph(trans, LMPM_CHICK, 797 LMPM_CHICK_EXTENDED_ADDR_SPACE); 798 799 if (ret) { 800 IWL_ERR(trans, 801 "Could not load the [%d] uCode section\n", 802 section_num); 803 break; 804 } 805 } 806 807 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 808 return ret; 809 } 810 811 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 812 const struct fw_img *image, 813 int cpu, 814 int *first_ucode_section) 815 { 816 int shift_param; 817 int i, ret = 0, sec_num = 0x1; 818 u32 val, last_read_idx = 0; 819 820 if (cpu == 1) { 821 shift_param = 0; 822 *first_ucode_section = 0; 823 } else { 824 shift_param = 16; 825 (*first_ucode_section)++; 826 } 827 828 for (i = *first_ucode_section; i < image->num_sec; i++) { 829 last_read_idx = i; 830 831 /* 832 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 833 * CPU1 to CPU2. 834 * PAGING_SEPARATOR_SECTION delimiter - separate between 835 * CPU2 non paged to CPU2 paging sec. 836 */ 837 if (!image->sec[i].data || 838 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 839 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 840 IWL_DEBUG_FW(trans, 841 "Break since Data not valid or Empty section, sec = %d\n", 842 i); 843 break; 844 } 845 846 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 847 if (ret) 848 return ret; 849 850 /* Notify ucode of loaded section number and status */ 851 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 852 val = val | (sec_num << shift_param); 853 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 854 855 sec_num = (sec_num << 1) | 0x1; 856 } 857 858 *first_ucode_section = last_read_idx; 859 860 iwl_enable_interrupts(trans); 861 862 if (trans->cfg->use_tfh) { 863 if (cpu == 1) 864 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 865 0xFFFF); 866 else 867 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 868 0xFFFFFFFF); 869 } else { 870 if (cpu == 1) 871 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 872 0xFFFF); 873 else 874 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 875 0xFFFFFFFF); 876 } 877 878 return 0; 879 } 880 881 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 882 const struct fw_img *image, 883 int cpu, 884 int *first_ucode_section) 885 { 886 int i, ret = 0; 887 u32 last_read_idx = 0; 888 889 if (cpu == 1) 890 *first_ucode_section = 0; 891 else 892 (*first_ucode_section)++; 893 894 for (i = *first_ucode_section; i < image->num_sec; i++) { 895 last_read_idx = i; 896 897 /* 898 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 899 * CPU1 to CPU2. 900 * PAGING_SEPARATOR_SECTION delimiter - separate between 901 * CPU2 non paged to CPU2 paging sec. 902 */ 903 if (!image->sec[i].data || 904 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 905 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 906 IWL_DEBUG_FW(trans, 907 "Break since Data not valid or Empty section, sec = %d\n", 908 i); 909 break; 910 } 911 912 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 913 if (ret) 914 return ret; 915 } 916 917 *first_ucode_section = last_read_idx; 918 919 return 0; 920 } 921 922 void iwl_pcie_apply_destination(struct iwl_trans *trans) 923 { 924 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 925 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 926 int i; 927 928 IWL_INFO(trans, "Applying debug destination %s\n", 929 get_fw_dbg_mode_string(dest->monitor_mode)); 930 931 if (dest->monitor_mode == EXTERNAL_MODE) 932 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 933 else 934 IWL_WARN(trans, "PCI should have external buffer debug\n"); 935 936 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 937 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 938 u32 val = le32_to_cpu(dest->reg_ops[i].val); 939 940 switch (dest->reg_ops[i].op) { 941 case CSR_ASSIGN: 942 iwl_write32(trans, addr, val); 943 break; 944 case CSR_SETBIT: 945 iwl_set_bit(trans, addr, BIT(val)); 946 break; 947 case CSR_CLEARBIT: 948 iwl_clear_bit(trans, addr, BIT(val)); 949 break; 950 case PRPH_ASSIGN: 951 iwl_write_prph(trans, addr, val); 952 break; 953 case PRPH_SETBIT: 954 iwl_set_bits_prph(trans, addr, BIT(val)); 955 break; 956 case PRPH_CLEARBIT: 957 iwl_clear_bits_prph(trans, addr, BIT(val)); 958 break; 959 case PRPH_BLOCKBIT: 960 if (iwl_read_prph(trans, addr) & BIT(val)) { 961 IWL_ERR(trans, 962 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 963 val, addr); 964 goto monitor; 965 } 966 break; 967 default: 968 IWL_ERR(trans, "FW debug - unknown OP %d\n", 969 dest->reg_ops[i].op); 970 break; 971 } 972 } 973 974 monitor: 975 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 976 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 977 trans_pcie->fw_mon_phys >> dest->base_shift); 978 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 979 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 980 (trans_pcie->fw_mon_phys + 981 trans_pcie->fw_mon_size - 256) >> 982 dest->end_shift); 983 else 984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 985 (trans_pcie->fw_mon_phys + 986 trans_pcie->fw_mon_size) >> 987 dest->end_shift); 988 } 989 } 990 991 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 992 const struct fw_img *image) 993 { 994 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 995 int ret = 0; 996 int first_ucode_section; 997 998 IWL_DEBUG_FW(trans, "working with %s CPU\n", 999 image->is_dual_cpus ? "Dual" : "Single"); 1000 1001 /* load to FW the binary non secured sections of CPU1 */ 1002 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1003 if (ret) 1004 return ret; 1005 1006 if (image->is_dual_cpus) { 1007 /* set CPU2 header address */ 1008 iwl_write_prph(trans, 1009 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1010 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1011 1012 /* load to FW the binary sections of CPU2 */ 1013 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1014 &first_ucode_section); 1015 if (ret) 1016 return ret; 1017 } 1018 1019 /* supported for 7000 only for the moment */ 1020 if (iwlwifi_mod_params.fw_monitor && 1021 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1022 iwl_pcie_alloc_fw_monitor(trans, 0); 1023 1024 if (trans_pcie->fw_mon_size) { 1025 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1026 trans_pcie->fw_mon_phys >> 4); 1027 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1028 (trans_pcie->fw_mon_phys + 1029 trans_pcie->fw_mon_size) >> 4); 1030 } 1031 } else if (trans->dbg_dest_tlv) { 1032 iwl_pcie_apply_destination(trans); 1033 } 1034 1035 iwl_enable_interrupts(trans); 1036 1037 /* release CPU reset */ 1038 iwl_write32(trans, CSR_RESET, 0); 1039 1040 return 0; 1041 } 1042 1043 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1044 const struct fw_img *image) 1045 { 1046 int ret = 0; 1047 int first_ucode_section; 1048 1049 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1050 image->is_dual_cpus ? "Dual" : "Single"); 1051 1052 if (trans->dbg_dest_tlv) 1053 iwl_pcie_apply_destination(trans); 1054 1055 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1056 iwl_read_prph(trans, WFPM_GP2)); 1057 1058 /* 1059 * Set default value. On resume reading the values that were 1060 * zeored can provide debug data on the resume flow. 1061 * This is for debugging only and has no functional impact. 1062 */ 1063 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1064 1065 /* configure the ucode to be ready to get the secured image */ 1066 /* release CPU reset */ 1067 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1068 1069 /* load to FW the binary Secured sections of CPU1 */ 1070 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1071 &first_ucode_section); 1072 if (ret) 1073 return ret; 1074 1075 /* load to FW the binary sections of CPU2 */ 1076 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1077 &first_ucode_section); 1078 } 1079 1080 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1081 { 1082 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1083 bool hw_rfkill = iwl_is_rfkill_set(trans); 1084 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1085 bool report; 1086 1087 if (hw_rfkill) { 1088 set_bit(STATUS_RFKILL_HW, &trans->status); 1089 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1090 } else { 1091 clear_bit(STATUS_RFKILL_HW, &trans->status); 1092 if (trans_pcie->opmode_down) 1093 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1094 } 1095 1096 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1097 1098 if (prev != report) 1099 iwl_trans_pcie_rf_kill(trans, report); 1100 1101 return hw_rfkill; 1102 } 1103 1104 struct iwl_causes_list { 1105 u32 cause_num; 1106 u32 mask_reg; 1107 u8 addr; 1108 }; 1109 1110 static struct iwl_causes_list causes_list[] = { 1111 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1112 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1113 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1114 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1115 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1116 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1117 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1118 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1119 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1120 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1121 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1122 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1123 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1124 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1125 }; 1126 1127 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1128 { 1129 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1130 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1131 int i; 1132 1133 /* 1134 * Access all non RX causes and map them to the default irq. 1135 * In case we are missing at least one interrupt vector, 1136 * the first interrupt vector will serve non-RX and FBQ causes. 1137 */ 1138 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1139 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1140 iwl_clear_bit(trans, causes_list[i].mask_reg, 1141 causes_list[i].cause_num); 1142 } 1143 } 1144 1145 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1146 { 1147 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1148 u32 offset = 1149 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1150 u32 val, idx; 1151 1152 /* 1153 * The first RX queue - fallback queue, which is designated for 1154 * management frame, command responses etc, is always mapped to the 1155 * first interrupt vector. The other RX queues are mapped to 1156 * the other (N - 2) interrupt vectors. 1157 */ 1158 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1159 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1160 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1161 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1162 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1163 } 1164 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1165 1166 val = MSIX_FH_INT_CAUSES_Q(0); 1167 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1168 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1169 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1170 1171 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1172 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1173 } 1174 1175 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1176 { 1177 struct iwl_trans *trans = trans_pcie->trans; 1178 1179 if (!trans_pcie->msix_enabled) { 1180 if (trans->cfg->mq_rx_supported && 1181 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1182 iwl_write_prph(trans, UREG_CHICK, 1183 UREG_CHICK_MSI_ENABLE); 1184 return; 1185 } 1186 /* 1187 * The IVAR table needs to be configured again after reset, 1188 * but if the device is disabled, we can't write to 1189 * prph. 1190 */ 1191 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1192 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1193 1194 /* 1195 * Each cause from the causes list above and the RX causes is 1196 * represented as a byte in the IVAR table. The first nibble 1197 * represents the bound interrupt vector of the cause, the second 1198 * represents no auto clear for this cause. This will be set if its 1199 * interrupt vector is bound to serve other causes. 1200 */ 1201 iwl_pcie_map_rx_causes(trans); 1202 1203 iwl_pcie_map_non_rx_causes(trans); 1204 } 1205 1206 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1207 { 1208 struct iwl_trans *trans = trans_pcie->trans; 1209 1210 iwl_pcie_conf_msix_hw(trans_pcie); 1211 1212 if (!trans_pcie->msix_enabled) 1213 return; 1214 1215 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1216 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1217 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1218 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1219 } 1220 1221 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1222 { 1223 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1224 1225 lockdep_assert_held(&trans_pcie->mutex); 1226 1227 if (trans_pcie->is_down) 1228 return; 1229 1230 trans_pcie->is_down = true; 1231 1232 /* Stop dbgc before stopping device */ 1233 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1234 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 1235 } else { 1236 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); 1237 udelay(100); 1238 iwl_write_prph(trans, DBGC_OUT_CTRL, 0); 1239 } 1240 1241 /* tell the device to stop sending interrupts */ 1242 iwl_disable_interrupts(trans); 1243 1244 /* device going down, Stop using ICT table */ 1245 iwl_pcie_disable_ict(trans); 1246 1247 /* 1248 * If a HW restart happens during firmware loading, 1249 * then the firmware loading might call this function 1250 * and later it might be called again due to the 1251 * restart. So don't process again if the device is 1252 * already dead. 1253 */ 1254 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1255 IWL_DEBUG_INFO(trans, 1256 "DEVICE_ENABLED bit was set and is now cleared\n"); 1257 iwl_pcie_tx_stop(trans); 1258 iwl_pcie_rx_stop(trans); 1259 1260 /* Power-down device's busmaster DMA clocks */ 1261 if (!trans->cfg->apmg_not_supported) { 1262 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1263 APMG_CLK_VAL_DMA_CLK_RQT); 1264 udelay(5); 1265 } 1266 } 1267 1268 /* Make sure (redundant) we've released our request to stay awake */ 1269 iwl_clear_bit(trans, CSR_GP_CNTRL, 1270 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1271 1272 /* Stop the device, and put it in low power state */ 1273 iwl_pcie_apm_stop(trans, false); 1274 1275 iwl_trans_pcie_sw_reset(trans); 1276 1277 /* 1278 * Upon stop, the IVAR table gets erased, so msi-x won't 1279 * work. This causes a bug in RF-KILL flows, since the interrupt 1280 * that enables radio won't fire on the correct irq, and the 1281 * driver won't be able to handle the interrupt. 1282 * Configure the IVAR table again after reset. 1283 */ 1284 iwl_pcie_conf_msix_hw(trans_pcie); 1285 1286 /* 1287 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1288 * This is a bug in certain verions of the hardware. 1289 * Certain devices also keep sending HW RF kill interrupt all 1290 * the time, unless the interrupt is ACKed even if the interrupt 1291 * should be masked. Re-ACK all the interrupts here. 1292 */ 1293 iwl_disable_interrupts(trans); 1294 1295 /* clear all status bits */ 1296 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1297 clear_bit(STATUS_INT_ENABLED, &trans->status); 1298 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1299 1300 /* 1301 * Even if we stop the HW, we still want the RF kill 1302 * interrupt 1303 */ 1304 iwl_enable_rfkill_int(trans); 1305 1306 /* re-take ownership to prevent other users from stealing the device */ 1307 iwl_pcie_prepare_card_hw(trans); 1308 } 1309 1310 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1311 { 1312 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1313 1314 if (trans_pcie->msix_enabled) { 1315 int i; 1316 1317 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1318 synchronize_irq(trans_pcie->msix_entries[i].vector); 1319 } else { 1320 synchronize_irq(trans_pcie->pci_dev->irq); 1321 } 1322 } 1323 1324 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1325 const struct fw_img *fw, bool run_in_rfkill) 1326 { 1327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1328 bool hw_rfkill; 1329 int ret; 1330 1331 /* This may fail if AMT took ownership of the device */ 1332 if (iwl_pcie_prepare_card_hw(trans)) { 1333 IWL_WARN(trans, "Exit HW not ready\n"); 1334 ret = -EIO; 1335 goto out; 1336 } 1337 1338 iwl_enable_rfkill_int(trans); 1339 1340 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1341 1342 /* 1343 * We enabled the RF-Kill interrupt and the handler may very 1344 * well be running. Disable the interrupts to make sure no other 1345 * interrupt can be fired. 1346 */ 1347 iwl_disable_interrupts(trans); 1348 1349 /* Make sure it finished running */ 1350 iwl_pcie_synchronize_irqs(trans); 1351 1352 mutex_lock(&trans_pcie->mutex); 1353 1354 /* If platform's RF_KILL switch is NOT set to KILL */ 1355 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1356 if (hw_rfkill && !run_in_rfkill) { 1357 ret = -ERFKILL; 1358 goto out; 1359 } 1360 1361 /* Someone called stop_device, don't try to start_fw */ 1362 if (trans_pcie->is_down) { 1363 IWL_WARN(trans, 1364 "Can't start_fw since the HW hasn't been started\n"); 1365 ret = -EIO; 1366 goto out; 1367 } 1368 1369 /* make sure rfkill handshake bits are cleared */ 1370 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1371 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1372 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1373 1374 /* clear (again), then enable host interrupts */ 1375 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1376 1377 ret = iwl_pcie_nic_init(trans); 1378 if (ret) { 1379 IWL_ERR(trans, "Unable to init nic\n"); 1380 goto out; 1381 } 1382 1383 /* 1384 * Now, we load the firmware and don't want to be interrupted, even 1385 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1386 * FH_TX interrupt which is needed to load the firmware). If the 1387 * RF-Kill switch is toggled, we will find out after having loaded 1388 * the firmware and return the proper value to the caller. 1389 */ 1390 iwl_enable_fw_load_int(trans); 1391 1392 /* really make sure rfkill handshake bits are cleared */ 1393 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1394 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1395 1396 /* Load the given image to the HW */ 1397 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1398 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1399 else 1400 ret = iwl_pcie_load_given_ucode(trans, fw); 1401 1402 /* re-check RF-Kill state since we may have missed the interrupt */ 1403 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1404 if (hw_rfkill && !run_in_rfkill) 1405 ret = -ERFKILL; 1406 1407 out: 1408 mutex_unlock(&trans_pcie->mutex); 1409 return ret; 1410 } 1411 1412 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1413 { 1414 iwl_pcie_reset_ict(trans); 1415 iwl_pcie_tx_start(trans, scd_addr); 1416 } 1417 1418 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1419 bool was_in_rfkill) 1420 { 1421 bool hw_rfkill; 1422 1423 /* 1424 * Check again since the RF kill state may have changed while 1425 * all the interrupts were disabled, in this case we couldn't 1426 * receive the RF kill interrupt and update the state in the 1427 * op_mode. 1428 * Don't call the op_mode if the rkfill state hasn't changed. 1429 * This allows the op_mode to call stop_device from the rfkill 1430 * notification without endless recursion. Under very rare 1431 * circumstances, we might have a small recursion if the rfkill 1432 * state changed exactly now while we were called from stop_device. 1433 * This is very unlikely but can happen and is supported. 1434 */ 1435 hw_rfkill = iwl_is_rfkill_set(trans); 1436 if (hw_rfkill) { 1437 set_bit(STATUS_RFKILL_HW, &trans->status); 1438 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1439 } else { 1440 clear_bit(STATUS_RFKILL_HW, &trans->status); 1441 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1442 } 1443 if (hw_rfkill != was_in_rfkill) 1444 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1445 } 1446 1447 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1448 { 1449 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1450 bool was_in_rfkill; 1451 1452 mutex_lock(&trans_pcie->mutex); 1453 trans_pcie->opmode_down = true; 1454 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1455 _iwl_trans_pcie_stop_device(trans, low_power); 1456 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1457 mutex_unlock(&trans_pcie->mutex); 1458 } 1459 1460 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1461 { 1462 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1463 IWL_TRANS_GET_PCIE_TRANS(trans); 1464 1465 lockdep_assert_held(&trans_pcie->mutex); 1466 1467 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1468 state ? "disabled" : "enabled"); 1469 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1470 if (trans->cfg->gen2) 1471 _iwl_trans_pcie_gen2_stop_device(trans, true); 1472 else 1473 _iwl_trans_pcie_stop_device(trans, true); 1474 } 1475 } 1476 1477 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1478 bool reset) 1479 { 1480 if (!reset) { 1481 /* Enable persistence mode to avoid reset */ 1482 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1483 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1484 } 1485 1486 iwl_disable_interrupts(trans); 1487 1488 /* 1489 * in testing mode, the host stays awake and the 1490 * hardware won't be reset (not even partially) 1491 */ 1492 if (test) 1493 return; 1494 1495 iwl_pcie_disable_ict(trans); 1496 1497 iwl_pcie_synchronize_irqs(trans); 1498 1499 iwl_clear_bit(trans, CSR_GP_CNTRL, 1500 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1501 iwl_clear_bit(trans, CSR_GP_CNTRL, 1502 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1503 1504 iwl_pcie_enable_rx_wake(trans, false); 1505 1506 if (reset) { 1507 /* 1508 * reset TX queues -- some of their registers reset during S3 1509 * so if we don't reset everything here the D3 image would try 1510 * to execute some invalid memory upon resume 1511 */ 1512 iwl_trans_pcie_tx_reset(trans); 1513 } 1514 1515 iwl_pcie_set_pwr(trans, true); 1516 } 1517 1518 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1519 enum iwl_d3_status *status, 1520 bool test, bool reset) 1521 { 1522 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1523 u32 val; 1524 int ret; 1525 1526 if (test) { 1527 iwl_enable_interrupts(trans); 1528 *status = IWL_D3_STATUS_ALIVE; 1529 return 0; 1530 } 1531 1532 iwl_pcie_enable_rx_wake(trans, true); 1533 1534 /* 1535 * Reconfigure IVAR table in case of MSIX or reset ict table in 1536 * MSI mode since HW reset erased it. 1537 * Also enables interrupts - none will happen as 1538 * the device doesn't know we're waking it up, only when 1539 * the opmode actually tells it after this call. 1540 */ 1541 iwl_pcie_conf_msix_hw(trans_pcie); 1542 if (!trans_pcie->msix_enabled) 1543 iwl_pcie_reset_ict(trans); 1544 iwl_enable_interrupts(trans); 1545 1546 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1547 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1548 1549 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1550 udelay(2); 1551 1552 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1553 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1554 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1555 25000); 1556 if (ret < 0) { 1557 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1558 return ret; 1559 } 1560 1561 iwl_pcie_set_pwr(trans, false); 1562 1563 if (!reset) { 1564 iwl_clear_bit(trans, CSR_GP_CNTRL, 1565 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1566 } else { 1567 iwl_trans_pcie_tx_reset(trans); 1568 1569 ret = iwl_pcie_rx_init(trans); 1570 if (ret) { 1571 IWL_ERR(trans, 1572 "Failed to resume the device (RX reset)\n"); 1573 return ret; 1574 } 1575 } 1576 1577 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1578 iwl_read_prph(trans, WFPM_GP2)); 1579 1580 val = iwl_read32(trans, CSR_RESET); 1581 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1582 *status = IWL_D3_STATUS_RESET; 1583 else 1584 *status = IWL_D3_STATUS_ALIVE; 1585 1586 return 0; 1587 } 1588 1589 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1590 struct iwl_trans *trans) 1591 { 1592 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1593 int max_irqs, num_irqs, i, ret, nr_online_cpus; 1594 u16 pci_cmd; 1595 1596 if (!trans->cfg->mq_rx_supported) 1597 goto enable_msi; 1598 1599 nr_online_cpus = num_online_cpus(); 1600 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 1601 for (i = 0; i < max_irqs; i++) 1602 trans_pcie->msix_entries[i].entry = i; 1603 1604 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1605 MSIX_MIN_INTERRUPT_VECTORS, 1606 max_irqs); 1607 if (num_irqs < 0) { 1608 IWL_DEBUG_INFO(trans, 1609 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1610 num_irqs); 1611 goto enable_msi; 1612 } 1613 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1614 1615 IWL_DEBUG_INFO(trans, 1616 "MSI-X enabled. %d interrupt vectors were allocated\n", 1617 num_irqs); 1618 1619 /* 1620 * In case the OS provides fewer interrupts than requested, different 1621 * causes will share the same interrupt vector as follows: 1622 * One interrupt less: non rx causes shared with FBQ. 1623 * Two interrupts less: non rx causes shared with FBQ and RSS. 1624 * More than two interrupts: we will use fewer RSS queues. 1625 */ 1626 if (num_irqs <= nr_online_cpus) { 1627 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1628 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1629 IWL_SHARED_IRQ_FIRST_RSS; 1630 } else if (num_irqs == nr_online_cpus + 1) { 1631 trans_pcie->trans->num_rx_queues = num_irqs; 1632 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1633 } else { 1634 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1635 } 1636 1637 trans_pcie->alloc_vecs = num_irqs; 1638 trans_pcie->msix_enabled = true; 1639 return; 1640 1641 enable_msi: 1642 ret = pci_enable_msi(pdev); 1643 if (ret) { 1644 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1645 /* enable rfkill interrupt: hw bug w/a */ 1646 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1647 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1648 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1649 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1650 } 1651 } 1652 } 1653 1654 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1655 { 1656 int iter_rx_q, i, ret, cpu, offset; 1657 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1658 1659 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1660 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1661 offset = 1 + i; 1662 for (; i < iter_rx_q ; i++) { 1663 /* 1664 * Get the cpu prior to the place to search 1665 * (i.e. return will be > i - 1). 1666 */ 1667 cpu = cpumask_next(i - offset, cpu_online_mask); 1668 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1669 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1670 &trans_pcie->affinity_mask[i]); 1671 if (ret) 1672 IWL_ERR(trans_pcie->trans, 1673 "Failed to set affinity mask for IRQ %d\n", 1674 i); 1675 } 1676 } 1677 1678 static const char *queue_name(struct device *dev, 1679 struct iwl_trans_pcie *trans_p, int i) 1680 { 1681 if (trans_p->shared_vec_mask) { 1682 int vec = trans_p->shared_vec_mask & 1683 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1684 1685 if (i == 0) 1686 return DRV_NAME ": shared IRQ"; 1687 1688 return devm_kasprintf(dev, GFP_KERNEL, 1689 DRV_NAME ": queue %d", i + vec); 1690 } 1691 if (i == 0) 1692 return DRV_NAME ": default queue"; 1693 1694 if (i == trans_p->alloc_vecs - 1) 1695 return DRV_NAME ": exception"; 1696 1697 return devm_kasprintf(dev, GFP_KERNEL, 1698 DRV_NAME ": queue %d", i); 1699 } 1700 1701 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1702 struct iwl_trans_pcie *trans_pcie) 1703 { 1704 int i; 1705 1706 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1707 int ret; 1708 struct msix_entry *msix_entry; 1709 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1710 1711 if (!qname) 1712 return -ENOMEM; 1713 1714 msix_entry = &trans_pcie->msix_entries[i]; 1715 ret = devm_request_threaded_irq(&pdev->dev, 1716 msix_entry->vector, 1717 iwl_pcie_msix_isr, 1718 (i == trans_pcie->def_irq) ? 1719 iwl_pcie_irq_msix_handler : 1720 iwl_pcie_irq_rx_msix_handler, 1721 IRQF_SHARED, 1722 qname, 1723 msix_entry); 1724 if (ret) { 1725 IWL_ERR(trans_pcie->trans, 1726 "Error allocating IRQ %d\n", i); 1727 1728 return ret; 1729 } 1730 } 1731 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1732 1733 return 0; 1734 } 1735 1736 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1737 { 1738 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1739 int err; 1740 1741 lockdep_assert_held(&trans_pcie->mutex); 1742 1743 err = iwl_pcie_prepare_card_hw(trans); 1744 if (err) { 1745 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1746 return err; 1747 } 1748 1749 iwl_trans_pcie_sw_reset(trans); 1750 1751 err = iwl_pcie_apm_init(trans); 1752 if (err) 1753 return err; 1754 1755 iwl_pcie_init_msix(trans_pcie); 1756 1757 /* From now on, the op_mode will be kept updated about RF kill state */ 1758 iwl_enable_rfkill_int(trans); 1759 1760 trans_pcie->opmode_down = false; 1761 1762 /* Set is_down to false here so that...*/ 1763 trans_pcie->is_down = false; 1764 1765 /* ...rfkill can call stop_device and set it false if needed */ 1766 iwl_pcie_check_hw_rf_kill(trans); 1767 1768 /* Make sure we sync here, because we'll need full access later */ 1769 if (low_power) 1770 pm_runtime_resume(trans->dev); 1771 1772 return 0; 1773 } 1774 1775 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1776 { 1777 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1778 int ret; 1779 1780 mutex_lock(&trans_pcie->mutex); 1781 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1782 mutex_unlock(&trans_pcie->mutex); 1783 1784 return ret; 1785 } 1786 1787 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1788 { 1789 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1790 1791 mutex_lock(&trans_pcie->mutex); 1792 1793 /* disable interrupts - don't enable HW RF kill interrupt */ 1794 iwl_disable_interrupts(trans); 1795 1796 iwl_pcie_apm_stop(trans, true); 1797 1798 iwl_disable_interrupts(trans); 1799 1800 iwl_pcie_disable_ict(trans); 1801 1802 mutex_unlock(&trans_pcie->mutex); 1803 1804 iwl_pcie_synchronize_irqs(trans); 1805 } 1806 1807 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1808 { 1809 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1810 } 1811 1812 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1813 { 1814 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1815 } 1816 1817 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1818 { 1819 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1820 } 1821 1822 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1823 { 1824 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1825 ((reg & 0x000FFFFF) | (3 << 24))); 1826 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1827 } 1828 1829 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1830 u32 val) 1831 { 1832 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1833 ((addr & 0x000FFFFF) | (3 << 24))); 1834 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1835 } 1836 1837 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1838 const struct iwl_trans_config *trans_cfg) 1839 { 1840 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1841 1842 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1843 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1844 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1845 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1846 trans_pcie->n_no_reclaim_cmds = 0; 1847 else 1848 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1849 if (trans_pcie->n_no_reclaim_cmds) 1850 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1851 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1852 1853 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1854 trans_pcie->rx_page_order = 1855 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1856 1857 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1858 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1859 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1860 1861 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1862 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1863 1864 trans->command_groups = trans_cfg->command_groups; 1865 trans->command_groups_size = trans_cfg->command_groups_size; 1866 1867 /* Initialize NAPI here - it should be before registering to mac80211 1868 * in the opmode but after the HW struct is allocated. 1869 * As this function may be called again in some corner cases don't 1870 * do anything if NAPI was already initialized. 1871 */ 1872 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1873 init_dummy_netdev(&trans_pcie->napi_dev); 1874 } 1875 1876 void iwl_trans_pcie_free(struct iwl_trans *trans) 1877 { 1878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1879 int i; 1880 1881 iwl_pcie_synchronize_irqs(trans); 1882 1883 if (trans->cfg->gen2) 1884 iwl_pcie_gen2_tx_free(trans); 1885 else 1886 iwl_pcie_tx_free(trans); 1887 iwl_pcie_rx_free(trans); 1888 1889 if (trans_pcie->rba.alloc_wq) { 1890 destroy_workqueue(trans_pcie->rba.alloc_wq); 1891 trans_pcie->rba.alloc_wq = NULL; 1892 } 1893 1894 if (trans_pcie->msix_enabled) { 1895 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1896 irq_set_affinity_hint( 1897 trans_pcie->msix_entries[i].vector, 1898 NULL); 1899 } 1900 1901 trans_pcie->msix_enabled = false; 1902 } else { 1903 iwl_pcie_free_ict(trans); 1904 } 1905 1906 iwl_pcie_free_fw_monitor(trans); 1907 1908 for_each_possible_cpu(i) { 1909 struct iwl_tso_hdr_page *p = 1910 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1911 1912 if (p->page) 1913 __free_page(p->page); 1914 } 1915 1916 free_percpu(trans_pcie->tso_hdr_page); 1917 mutex_destroy(&trans_pcie->mutex); 1918 iwl_trans_free(trans); 1919 } 1920 1921 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1922 { 1923 if (state) 1924 set_bit(STATUS_TPOWER_PMI, &trans->status); 1925 else 1926 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1927 } 1928 1929 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1930 unsigned long *flags) 1931 { 1932 int ret; 1933 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1934 1935 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1936 1937 if (trans_pcie->cmd_hold_nic_awake) 1938 goto out; 1939 1940 /* this bit wakes up the NIC */ 1941 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1942 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1943 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1944 udelay(2); 1945 1946 /* 1947 * These bits say the device is running, and should keep running for 1948 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1949 * but they do not indicate that embedded SRAM is restored yet; 1950 * HW with volatile SRAM must save/restore contents to/from 1951 * host DRAM when sleeping/waking for power-saving. 1952 * Each direction takes approximately 1/4 millisecond; with this 1953 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1954 * series of register accesses are expected (e.g. reading Event Log), 1955 * to keep device from sleeping. 1956 * 1957 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1958 * SRAM is okay/restored. We don't check that here because this call 1959 * is just for hardware register access; but GP1 MAC_SLEEP 1960 * check is a good idea before accessing the SRAM of HW with 1961 * volatile SRAM (e.g. reading Event Log). 1962 * 1963 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1964 * and do not save/restore SRAM when power cycling. 1965 */ 1966 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1967 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1968 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1969 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1970 if (unlikely(ret < 0)) { 1971 iwl_trans_pcie_dump_regs(trans); 1972 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1973 WARN_ONCE(1, 1974 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1975 iwl_read32(trans, CSR_GP_CNTRL)); 1976 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1977 return false; 1978 } 1979 1980 out: 1981 /* 1982 * Fool sparse by faking we release the lock - sparse will 1983 * track nic_access anyway. 1984 */ 1985 __release(&trans_pcie->reg_lock); 1986 return true; 1987 } 1988 1989 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1990 unsigned long *flags) 1991 { 1992 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1993 1994 lockdep_assert_held(&trans_pcie->reg_lock); 1995 1996 /* 1997 * Fool sparse by faking we acquiring the lock - sparse will 1998 * track nic_access anyway. 1999 */ 2000 __acquire(&trans_pcie->reg_lock); 2001 2002 if (trans_pcie->cmd_hold_nic_awake) 2003 goto out; 2004 2005 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2006 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2007 /* 2008 * Above we read the CSR_GP_CNTRL register, which will flush 2009 * any previous writes, but we need the write that clears the 2010 * MAC_ACCESS_REQ bit to be performed before any other writes 2011 * scheduled on different CPUs (after we drop reg_lock). 2012 */ 2013 mmiowb(); 2014 out: 2015 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2016 } 2017 2018 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2019 void *buf, int dwords) 2020 { 2021 unsigned long flags; 2022 int offs, ret = 0; 2023 u32 *vals = buf; 2024 2025 if (iwl_trans_grab_nic_access(trans, &flags)) { 2026 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2027 for (offs = 0; offs < dwords; offs++) 2028 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2029 iwl_trans_release_nic_access(trans, &flags); 2030 } else { 2031 ret = -EBUSY; 2032 } 2033 return ret; 2034 } 2035 2036 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2037 const void *buf, int dwords) 2038 { 2039 unsigned long flags; 2040 int offs, ret = 0; 2041 const u32 *vals = buf; 2042 2043 if (iwl_trans_grab_nic_access(trans, &flags)) { 2044 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2045 for (offs = 0; offs < dwords; offs++) 2046 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2047 vals ? vals[offs] : 0); 2048 iwl_trans_release_nic_access(trans, &flags); 2049 } else { 2050 ret = -EBUSY; 2051 } 2052 return ret; 2053 } 2054 2055 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2056 unsigned long txqs, 2057 bool freeze) 2058 { 2059 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2060 int queue; 2061 2062 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2063 struct iwl_txq *txq = trans_pcie->txq[queue]; 2064 unsigned long now; 2065 2066 spin_lock_bh(&txq->lock); 2067 2068 now = jiffies; 2069 2070 if (txq->frozen == freeze) 2071 goto next_queue; 2072 2073 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2074 freeze ? "Freezing" : "Waking", queue); 2075 2076 txq->frozen = freeze; 2077 2078 if (txq->read_ptr == txq->write_ptr) 2079 goto next_queue; 2080 2081 if (freeze) { 2082 if (unlikely(time_after(now, 2083 txq->stuck_timer.expires))) { 2084 /* 2085 * The timer should have fired, maybe it is 2086 * spinning right now on the lock. 2087 */ 2088 goto next_queue; 2089 } 2090 /* remember how long until the timer fires */ 2091 txq->frozen_expiry_remainder = 2092 txq->stuck_timer.expires - now; 2093 del_timer(&txq->stuck_timer); 2094 goto next_queue; 2095 } 2096 2097 /* 2098 * Wake a non-empty queue -> arm timer with the 2099 * remainder before it froze 2100 */ 2101 mod_timer(&txq->stuck_timer, 2102 now + txq->frozen_expiry_remainder); 2103 2104 next_queue: 2105 spin_unlock_bh(&txq->lock); 2106 } 2107 } 2108 2109 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2110 { 2111 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2112 int i; 2113 2114 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2115 struct iwl_txq *txq = trans_pcie->txq[i]; 2116 2117 if (i == trans_pcie->cmd_queue) 2118 continue; 2119 2120 spin_lock_bh(&txq->lock); 2121 2122 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2123 txq->block--; 2124 if (!txq->block) { 2125 iwl_write32(trans, HBUS_TARG_WRPTR, 2126 txq->write_ptr | (i << 8)); 2127 } 2128 } else if (block) { 2129 txq->block++; 2130 } 2131 2132 spin_unlock_bh(&txq->lock); 2133 } 2134 } 2135 2136 #define IWL_FLUSH_WAIT_MS 2000 2137 2138 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2139 { 2140 u32 txq_id = txq->id; 2141 u32 status; 2142 bool active; 2143 u8 fifo; 2144 2145 if (trans->cfg->use_tfh) { 2146 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2147 txq->read_ptr, txq->write_ptr); 2148 /* TODO: access new SCD registers and dump them */ 2149 return; 2150 } 2151 2152 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2153 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2154 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2155 2156 IWL_ERR(trans, 2157 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2158 txq_id, active ? "" : "in", fifo, 2159 jiffies_to_msecs(txq->wd_timeout), 2160 txq->read_ptr, txq->write_ptr, 2161 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2162 (TFD_QUEUE_SIZE_MAX - 1), 2163 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2164 (TFD_QUEUE_SIZE_MAX - 1), 2165 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2166 } 2167 2168 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2169 { 2170 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2171 struct iwl_txq *txq; 2172 unsigned long now = jiffies; 2173 u8 wr_ptr; 2174 2175 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2176 return -EINVAL; 2177 2178 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2179 txq = trans_pcie->txq[txq_idx]; 2180 wr_ptr = READ_ONCE(txq->write_ptr); 2181 2182 while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2183 !time_after(jiffies, 2184 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2185 u8 write_ptr = READ_ONCE(txq->write_ptr); 2186 2187 if (WARN_ONCE(wr_ptr != write_ptr, 2188 "WR pointer moved while flushing %d -> %d\n", 2189 wr_ptr, write_ptr)) 2190 return -ETIMEDOUT; 2191 usleep_range(1000, 2000); 2192 } 2193 2194 if (txq->read_ptr != txq->write_ptr) { 2195 IWL_ERR(trans, 2196 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2197 iwl_trans_pcie_log_scd_error(trans, txq); 2198 return -ETIMEDOUT; 2199 } 2200 2201 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2202 2203 return 0; 2204 } 2205 2206 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2207 { 2208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2209 int cnt; 2210 int ret = 0; 2211 2212 /* waiting for all the tx frames complete might take a while */ 2213 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2214 2215 if (cnt == trans_pcie->cmd_queue) 2216 continue; 2217 if (!test_bit(cnt, trans_pcie->queue_used)) 2218 continue; 2219 if (!(BIT(cnt) & txq_bm)) 2220 continue; 2221 2222 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2223 if (ret) 2224 break; 2225 } 2226 2227 return ret; 2228 } 2229 2230 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2231 u32 mask, u32 value) 2232 { 2233 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2234 unsigned long flags; 2235 2236 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2237 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2238 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2239 } 2240 2241 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2242 { 2243 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2244 2245 if (iwlwifi_mod_params.d0i3_disable) 2246 return; 2247 2248 pm_runtime_get(&trans_pcie->pci_dev->dev); 2249 2250 #ifdef CONFIG_PM 2251 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2252 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2253 #endif /* CONFIG_PM */ 2254 } 2255 2256 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2257 { 2258 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2259 2260 if (iwlwifi_mod_params.d0i3_disable) 2261 return; 2262 2263 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2264 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2265 2266 #ifdef CONFIG_PM 2267 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2268 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2269 #endif /* CONFIG_PM */ 2270 } 2271 2272 static const char *get_csr_string(int cmd) 2273 { 2274 #define IWL_CMD(x) case x: return #x 2275 switch (cmd) { 2276 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2277 IWL_CMD(CSR_INT_COALESCING); 2278 IWL_CMD(CSR_INT); 2279 IWL_CMD(CSR_INT_MASK); 2280 IWL_CMD(CSR_FH_INT_STATUS); 2281 IWL_CMD(CSR_GPIO_IN); 2282 IWL_CMD(CSR_RESET); 2283 IWL_CMD(CSR_GP_CNTRL); 2284 IWL_CMD(CSR_HW_REV); 2285 IWL_CMD(CSR_EEPROM_REG); 2286 IWL_CMD(CSR_EEPROM_GP); 2287 IWL_CMD(CSR_OTP_GP_REG); 2288 IWL_CMD(CSR_GIO_REG); 2289 IWL_CMD(CSR_GP_UCODE_REG); 2290 IWL_CMD(CSR_GP_DRIVER_REG); 2291 IWL_CMD(CSR_UCODE_DRV_GP1); 2292 IWL_CMD(CSR_UCODE_DRV_GP2); 2293 IWL_CMD(CSR_LED_REG); 2294 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2295 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2296 IWL_CMD(CSR_ANA_PLL_CFG); 2297 IWL_CMD(CSR_HW_REV_WA_REG); 2298 IWL_CMD(CSR_MONITOR_STATUS_REG); 2299 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2300 default: 2301 return "UNKNOWN"; 2302 } 2303 #undef IWL_CMD 2304 } 2305 2306 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2307 { 2308 int i; 2309 static const u32 csr_tbl[] = { 2310 CSR_HW_IF_CONFIG_REG, 2311 CSR_INT_COALESCING, 2312 CSR_INT, 2313 CSR_INT_MASK, 2314 CSR_FH_INT_STATUS, 2315 CSR_GPIO_IN, 2316 CSR_RESET, 2317 CSR_GP_CNTRL, 2318 CSR_HW_REV, 2319 CSR_EEPROM_REG, 2320 CSR_EEPROM_GP, 2321 CSR_OTP_GP_REG, 2322 CSR_GIO_REG, 2323 CSR_GP_UCODE_REG, 2324 CSR_GP_DRIVER_REG, 2325 CSR_UCODE_DRV_GP1, 2326 CSR_UCODE_DRV_GP2, 2327 CSR_LED_REG, 2328 CSR_DRAM_INT_TBL_REG, 2329 CSR_GIO_CHICKEN_BITS, 2330 CSR_ANA_PLL_CFG, 2331 CSR_MONITOR_STATUS_REG, 2332 CSR_HW_REV_WA_REG, 2333 CSR_DBG_HPET_MEM_REG 2334 }; 2335 IWL_ERR(trans, "CSR values:\n"); 2336 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2337 "CSR_INT_PERIODIC_REG)\n"); 2338 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2339 IWL_ERR(trans, " %25s: 0X%08x\n", 2340 get_csr_string(csr_tbl[i]), 2341 iwl_read32(trans, csr_tbl[i])); 2342 } 2343 } 2344 2345 #ifdef CONFIG_IWLWIFI_DEBUGFS 2346 /* create and remove of files */ 2347 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2348 if (!debugfs_create_file(#name, mode, parent, trans, \ 2349 &iwl_dbgfs_##name##_ops)) \ 2350 goto err; \ 2351 } while (0) 2352 2353 /* file operation */ 2354 #define DEBUGFS_READ_FILE_OPS(name) \ 2355 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2356 .read = iwl_dbgfs_##name##_read, \ 2357 .open = simple_open, \ 2358 .llseek = generic_file_llseek, \ 2359 }; 2360 2361 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2362 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2363 .write = iwl_dbgfs_##name##_write, \ 2364 .open = simple_open, \ 2365 .llseek = generic_file_llseek, \ 2366 }; 2367 2368 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2369 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2370 .write = iwl_dbgfs_##name##_write, \ 2371 .read = iwl_dbgfs_##name##_read, \ 2372 .open = simple_open, \ 2373 .llseek = generic_file_llseek, \ 2374 }; 2375 2376 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2377 char __user *user_buf, 2378 size_t count, loff_t *ppos) 2379 { 2380 struct iwl_trans *trans = file->private_data; 2381 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2382 struct iwl_txq *txq; 2383 char *buf; 2384 int pos = 0; 2385 int cnt; 2386 int ret; 2387 size_t bufsz; 2388 2389 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2390 2391 if (!trans_pcie->txq_memory) 2392 return -EAGAIN; 2393 2394 buf = kzalloc(bufsz, GFP_KERNEL); 2395 if (!buf) 2396 return -ENOMEM; 2397 2398 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2399 txq = trans_pcie->txq[cnt]; 2400 pos += scnprintf(buf + pos, bufsz - pos, 2401 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2402 cnt, txq->read_ptr, txq->write_ptr, 2403 !!test_bit(cnt, trans_pcie->queue_used), 2404 !!test_bit(cnt, trans_pcie->queue_stopped), 2405 txq->need_update, txq->frozen, 2406 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2407 } 2408 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2409 kfree(buf); 2410 return ret; 2411 } 2412 2413 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2414 char __user *user_buf, 2415 size_t count, loff_t *ppos) 2416 { 2417 struct iwl_trans *trans = file->private_data; 2418 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2419 char *buf; 2420 int pos = 0, i, ret; 2421 size_t bufsz = sizeof(buf); 2422 2423 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2424 2425 if (!trans_pcie->rxq) 2426 return -EAGAIN; 2427 2428 buf = kzalloc(bufsz, GFP_KERNEL); 2429 if (!buf) 2430 return -ENOMEM; 2431 2432 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2433 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2434 2435 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2436 i); 2437 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2438 rxq->read); 2439 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2440 rxq->write); 2441 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2442 rxq->write_actual); 2443 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2444 rxq->need_update); 2445 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2446 rxq->free_count); 2447 if (rxq->rb_stts) { 2448 pos += scnprintf(buf + pos, bufsz - pos, 2449 "\tclosed_rb_num: %u\n", 2450 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2451 0x0FFF); 2452 } else { 2453 pos += scnprintf(buf + pos, bufsz - pos, 2454 "\tclosed_rb_num: Not Allocated\n"); 2455 } 2456 } 2457 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2458 kfree(buf); 2459 2460 return ret; 2461 } 2462 2463 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2464 char __user *user_buf, 2465 size_t count, loff_t *ppos) 2466 { 2467 struct iwl_trans *trans = file->private_data; 2468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2469 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2470 2471 int pos = 0; 2472 char *buf; 2473 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2474 ssize_t ret; 2475 2476 buf = kzalloc(bufsz, GFP_KERNEL); 2477 if (!buf) 2478 return -ENOMEM; 2479 2480 pos += scnprintf(buf + pos, bufsz - pos, 2481 "Interrupt Statistics Report:\n"); 2482 2483 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2484 isr_stats->hw); 2485 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2486 isr_stats->sw); 2487 if (isr_stats->sw || isr_stats->hw) { 2488 pos += scnprintf(buf + pos, bufsz - pos, 2489 "\tLast Restarting Code: 0x%X\n", 2490 isr_stats->err_code); 2491 } 2492 #ifdef CONFIG_IWLWIFI_DEBUG 2493 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2494 isr_stats->sch); 2495 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2496 isr_stats->alive); 2497 #endif 2498 pos += scnprintf(buf + pos, bufsz - pos, 2499 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2500 2501 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2502 isr_stats->ctkill); 2503 2504 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2505 isr_stats->wakeup); 2506 2507 pos += scnprintf(buf + pos, bufsz - pos, 2508 "Rx command responses:\t\t %u\n", isr_stats->rx); 2509 2510 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2511 isr_stats->tx); 2512 2513 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2514 isr_stats->unhandled); 2515 2516 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2517 kfree(buf); 2518 return ret; 2519 } 2520 2521 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2522 const char __user *user_buf, 2523 size_t count, loff_t *ppos) 2524 { 2525 struct iwl_trans *trans = file->private_data; 2526 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2527 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2528 u32 reset_flag; 2529 int ret; 2530 2531 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2532 if (ret) 2533 return ret; 2534 if (reset_flag == 0) 2535 memset(isr_stats, 0, sizeof(*isr_stats)); 2536 2537 return count; 2538 } 2539 2540 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2541 const char __user *user_buf, 2542 size_t count, loff_t *ppos) 2543 { 2544 struct iwl_trans *trans = file->private_data; 2545 2546 iwl_pcie_dump_csr(trans); 2547 2548 return count; 2549 } 2550 2551 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2552 char __user *user_buf, 2553 size_t count, loff_t *ppos) 2554 { 2555 struct iwl_trans *trans = file->private_data; 2556 char *buf = NULL; 2557 ssize_t ret; 2558 2559 ret = iwl_dump_fh(trans, &buf); 2560 if (ret < 0) 2561 return ret; 2562 if (!buf) 2563 return -EINVAL; 2564 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2565 kfree(buf); 2566 return ret; 2567 } 2568 2569 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2570 char __user *user_buf, 2571 size_t count, loff_t *ppos) 2572 { 2573 struct iwl_trans *trans = file->private_data; 2574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2575 char buf[100]; 2576 int pos; 2577 2578 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2579 trans_pcie->debug_rfkill, 2580 !(iwl_read32(trans, CSR_GP_CNTRL) & 2581 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2582 2583 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2584 } 2585 2586 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2587 const char __user *user_buf, 2588 size_t count, loff_t *ppos) 2589 { 2590 struct iwl_trans *trans = file->private_data; 2591 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2592 bool old = trans_pcie->debug_rfkill; 2593 int ret; 2594 2595 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2596 if (ret) 2597 return ret; 2598 if (old == trans_pcie->debug_rfkill) 2599 return count; 2600 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2601 old, trans_pcie->debug_rfkill); 2602 iwl_pcie_handle_rfkill_irq(trans); 2603 2604 return count; 2605 } 2606 2607 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2608 DEBUGFS_READ_FILE_OPS(fh_reg); 2609 DEBUGFS_READ_FILE_OPS(rx_queue); 2610 DEBUGFS_READ_FILE_OPS(tx_queue); 2611 DEBUGFS_WRITE_FILE_OPS(csr); 2612 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2613 2614 /* Create the debugfs files and directories */ 2615 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2616 { 2617 struct dentry *dir = trans->dbgfs_dir; 2618 2619 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2620 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2621 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2622 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2623 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2624 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR); 2625 return 0; 2626 2627 err: 2628 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2629 return -ENOMEM; 2630 } 2631 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2632 2633 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2634 { 2635 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2636 u32 cmdlen = 0; 2637 int i; 2638 2639 for (i = 0; i < trans_pcie->max_tbs; i++) 2640 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2641 2642 return cmdlen; 2643 } 2644 2645 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2646 struct iwl_fw_error_dump_data **data, 2647 int allocated_rb_nums) 2648 { 2649 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2650 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2651 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2652 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2653 u32 i, r, j, rb_len = 0; 2654 2655 spin_lock(&rxq->lock); 2656 2657 r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2658 2659 for (i = rxq->read, j = 0; 2660 i != r && j < allocated_rb_nums; 2661 i = (i + 1) & RX_QUEUE_MASK, j++) { 2662 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2663 struct iwl_fw_error_dump_rb *rb; 2664 2665 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2666 DMA_FROM_DEVICE); 2667 2668 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2669 2670 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2671 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2672 rb = (void *)(*data)->data; 2673 rb->index = cpu_to_le32(i); 2674 memcpy(rb->data, page_address(rxb->page), max_len); 2675 /* remap the page for the free benefit */ 2676 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2677 max_len, 2678 DMA_FROM_DEVICE); 2679 2680 *data = iwl_fw_error_next_data(*data); 2681 } 2682 2683 spin_unlock(&rxq->lock); 2684 2685 return rb_len; 2686 } 2687 #define IWL_CSR_TO_DUMP (0x250) 2688 2689 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2690 struct iwl_fw_error_dump_data **data) 2691 { 2692 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2693 __le32 *val; 2694 int i; 2695 2696 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2697 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2698 val = (void *)(*data)->data; 2699 2700 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2701 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2702 2703 *data = iwl_fw_error_next_data(*data); 2704 2705 return csr_len; 2706 } 2707 2708 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2709 struct iwl_fw_error_dump_data **data) 2710 { 2711 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2712 unsigned long flags; 2713 __le32 *val; 2714 int i; 2715 2716 if (!iwl_trans_grab_nic_access(trans, &flags)) 2717 return 0; 2718 2719 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2720 (*data)->len = cpu_to_le32(fh_regs_len); 2721 val = (void *)(*data)->data; 2722 2723 if (!trans->cfg->gen2) 2724 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2725 i += sizeof(u32)) 2726 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2727 else 2728 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2729 i += sizeof(u32)) 2730 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2731 i)); 2732 2733 iwl_trans_release_nic_access(trans, &flags); 2734 2735 *data = iwl_fw_error_next_data(*data); 2736 2737 return sizeof(**data) + fh_regs_len; 2738 } 2739 2740 static u32 2741 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2742 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2743 u32 monitor_len) 2744 { 2745 u32 buf_size_in_dwords = (monitor_len >> 2); 2746 u32 *buffer = (u32 *)fw_mon_data->data; 2747 unsigned long flags; 2748 u32 i; 2749 2750 if (!iwl_trans_grab_nic_access(trans, &flags)) 2751 return 0; 2752 2753 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2754 for (i = 0; i < buf_size_in_dwords; i++) 2755 buffer[i] = iwl_read_prph_no_grab(trans, 2756 MON_DMARB_RD_DATA_ADDR); 2757 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2758 2759 iwl_trans_release_nic_access(trans, &flags); 2760 2761 return monitor_len; 2762 } 2763 2764 static u32 2765 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2766 struct iwl_fw_error_dump_data **data, 2767 u32 monitor_len) 2768 { 2769 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2770 u32 len = 0; 2771 2772 if ((trans_pcie->fw_mon_page && 2773 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2774 trans->dbg_dest_tlv) { 2775 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2776 u32 base, write_ptr, wrap_cnt; 2777 2778 /* If there was a dest TLV - use the values from there */ 2779 if (trans->dbg_dest_tlv) { 2780 write_ptr = 2781 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2782 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2783 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2784 } else { 2785 base = MON_BUFF_BASE_ADDR; 2786 write_ptr = MON_BUFF_WRPTR; 2787 wrap_cnt = MON_BUFF_CYCLE_CNT; 2788 } 2789 2790 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2791 fw_mon_data = (void *)(*data)->data; 2792 fw_mon_data->fw_mon_wr_ptr = 2793 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2794 fw_mon_data->fw_mon_cycle_cnt = 2795 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2796 fw_mon_data->fw_mon_base_ptr = 2797 cpu_to_le32(iwl_read_prph(trans, base)); 2798 2799 len += sizeof(**data) + sizeof(*fw_mon_data); 2800 if (trans_pcie->fw_mon_page) { 2801 /* 2802 * The firmware is now asserted, it won't write anything 2803 * to the buffer. CPU can take ownership to fetch the 2804 * data. The buffer will be handed back to the device 2805 * before the firmware will be restarted. 2806 */ 2807 dma_sync_single_for_cpu(trans->dev, 2808 trans_pcie->fw_mon_phys, 2809 trans_pcie->fw_mon_size, 2810 DMA_FROM_DEVICE); 2811 memcpy(fw_mon_data->data, 2812 page_address(trans_pcie->fw_mon_page), 2813 trans_pcie->fw_mon_size); 2814 2815 monitor_len = trans_pcie->fw_mon_size; 2816 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2817 /* 2818 * Update pointers to reflect actual values after 2819 * shifting 2820 */ 2821 if (trans->dbg_dest_tlv->version) { 2822 base = (iwl_read_prph(trans, base) & 2823 IWL_LDBG_M2S_BUF_BA_MSK) << 2824 trans->dbg_dest_tlv->base_shift; 2825 base *= IWL_M2S_UNIT_SIZE; 2826 base += trans->cfg->smem_offset; 2827 } else { 2828 base = iwl_read_prph(trans, base) << 2829 trans->dbg_dest_tlv->base_shift; 2830 } 2831 2832 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2833 monitor_len / sizeof(u32)); 2834 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2835 monitor_len = 2836 iwl_trans_pci_dump_marbh_monitor(trans, 2837 fw_mon_data, 2838 monitor_len); 2839 } else { 2840 /* Didn't match anything - output no monitor data */ 2841 monitor_len = 0; 2842 } 2843 2844 len += monitor_len; 2845 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2846 } 2847 2848 return len; 2849 } 2850 2851 static struct iwl_trans_dump_data 2852 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2853 const struct iwl_fw_dbg_trigger_tlv *trigger) 2854 { 2855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2856 struct iwl_fw_error_dump_data *data; 2857 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2858 struct iwl_fw_error_dump_txcmd *txcmd; 2859 struct iwl_trans_dump_data *dump_data; 2860 u32 len, num_rbs; 2861 u32 monitor_len; 2862 int i, ptr; 2863 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2864 !trans->cfg->mq_rx_supported; 2865 2866 /* transport dump header */ 2867 len = sizeof(*dump_data); 2868 2869 /* host commands */ 2870 len += sizeof(*data) + 2871 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2872 2873 /* FW monitor */ 2874 if (trans_pcie->fw_mon_page) { 2875 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2876 trans_pcie->fw_mon_size; 2877 monitor_len = trans_pcie->fw_mon_size; 2878 } else if (trans->dbg_dest_tlv) { 2879 u32 base, end, cfg_reg; 2880 2881 if (trans->dbg_dest_tlv->version == 1) { 2882 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2883 cfg_reg = iwl_read_prph(trans, cfg_reg); 2884 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 2885 trans->dbg_dest_tlv->base_shift; 2886 base *= IWL_M2S_UNIT_SIZE; 2887 base += trans->cfg->smem_offset; 2888 2889 monitor_len = 2890 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 2891 trans->dbg_dest_tlv->end_shift; 2892 monitor_len *= IWL_M2S_UNIT_SIZE; 2893 } else { 2894 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2895 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2896 2897 base = iwl_read_prph(trans, base) << 2898 trans->dbg_dest_tlv->base_shift; 2899 end = iwl_read_prph(trans, end) << 2900 trans->dbg_dest_tlv->end_shift; 2901 2902 /* Make "end" point to the actual end */ 2903 if (trans->cfg->device_family >= 2904 IWL_DEVICE_FAMILY_8000 || 2905 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2906 end += (1 << trans->dbg_dest_tlv->end_shift); 2907 monitor_len = end - base; 2908 } 2909 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2910 monitor_len; 2911 } else { 2912 monitor_len = 0; 2913 } 2914 2915 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2916 dump_data = vzalloc(len); 2917 if (!dump_data) 2918 return NULL; 2919 2920 data = (void *)dump_data->data; 2921 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2922 dump_data->len = len; 2923 2924 return dump_data; 2925 } 2926 2927 /* CSR registers */ 2928 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2929 2930 /* FH registers */ 2931 if (trans->cfg->gen2) 2932 len += sizeof(*data) + 2933 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2); 2934 else 2935 len += sizeof(*data) + 2936 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2937 2938 if (dump_rbs) { 2939 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2940 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2941 /* RBs */ 2942 num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) 2943 & 0x0FFF; 2944 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2945 len += num_rbs * (sizeof(*data) + 2946 sizeof(struct iwl_fw_error_dump_rb) + 2947 (PAGE_SIZE << trans_pcie->rx_page_order)); 2948 } 2949 2950 /* Paged memory for gen2 HW */ 2951 if (trans->cfg->gen2) 2952 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 2953 len += sizeof(*data) + 2954 sizeof(struct iwl_fw_error_dump_paging) + 2955 trans_pcie->init_dram.paging[i].size; 2956 2957 dump_data = vzalloc(len); 2958 if (!dump_data) 2959 return NULL; 2960 2961 len = 0; 2962 data = (void *)dump_data->data; 2963 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2964 txcmd = (void *)data->data; 2965 spin_lock_bh(&cmdq->lock); 2966 ptr = cmdq->write_ptr; 2967 for (i = 0; i < cmdq->n_window; i++) { 2968 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 2969 u32 caplen, cmdlen; 2970 2971 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 2972 trans_pcie->tfd_size * ptr); 2973 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2974 2975 if (cmdlen) { 2976 len += sizeof(*txcmd) + caplen; 2977 txcmd->cmdlen = cpu_to_le32(cmdlen); 2978 txcmd->caplen = cpu_to_le32(caplen); 2979 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2980 txcmd = (void *)((u8 *)txcmd->data + caplen); 2981 } 2982 2983 ptr = iwl_queue_dec_wrap(ptr); 2984 } 2985 spin_unlock_bh(&cmdq->lock); 2986 2987 data->len = cpu_to_le32(len); 2988 len += sizeof(*data); 2989 data = iwl_fw_error_next_data(data); 2990 2991 len += iwl_trans_pcie_dump_csr(trans, &data); 2992 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2993 if (dump_rbs) 2994 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2995 2996 /* Paged memory for gen2 HW */ 2997 if (trans->cfg->gen2) { 2998 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 2999 struct iwl_fw_error_dump_paging *paging; 3000 dma_addr_t addr = 3001 trans_pcie->init_dram.paging[i].physical; 3002 u32 page_len = trans_pcie->init_dram.paging[i].size; 3003 3004 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3005 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3006 paging = (void *)data->data; 3007 paging->index = cpu_to_le32(i); 3008 dma_sync_single_for_cpu(trans->dev, addr, page_len, 3009 DMA_BIDIRECTIONAL); 3010 memcpy(paging->data, 3011 trans_pcie->init_dram.paging[i].block, page_len); 3012 data = iwl_fw_error_next_data(data); 3013 3014 len += sizeof(*data) + sizeof(*paging) + page_len; 3015 } 3016 } 3017 3018 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3019 3020 dump_data->len = len; 3021 3022 return dump_data; 3023 } 3024 3025 #ifdef CONFIG_PM_SLEEP 3026 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3027 { 3028 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3029 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3030 return iwl_pci_fw_enter_d0i3(trans); 3031 3032 return 0; 3033 } 3034 3035 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3036 { 3037 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3038 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3039 iwl_pci_fw_exit_d0i3(trans); 3040 } 3041 #endif /* CONFIG_PM_SLEEP */ 3042 3043 #define IWL_TRANS_COMMON_OPS \ 3044 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3045 .write8 = iwl_trans_pcie_write8, \ 3046 .write32 = iwl_trans_pcie_write32, \ 3047 .read32 = iwl_trans_pcie_read32, \ 3048 .read_prph = iwl_trans_pcie_read_prph, \ 3049 .write_prph = iwl_trans_pcie_write_prph, \ 3050 .read_mem = iwl_trans_pcie_read_mem, \ 3051 .write_mem = iwl_trans_pcie_write_mem, \ 3052 .configure = iwl_trans_pcie_configure, \ 3053 .set_pmi = iwl_trans_pcie_set_pmi, \ 3054 .sw_reset = iwl_trans_pcie_sw_reset, \ 3055 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3056 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3057 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3058 .ref = iwl_trans_pcie_ref, \ 3059 .unref = iwl_trans_pcie_unref, \ 3060 .dump_data = iwl_trans_pcie_dump_data, \ 3061 .dump_regs = iwl_trans_pcie_dump_regs, \ 3062 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3063 .d3_resume = iwl_trans_pcie_d3_resume 3064 3065 #ifdef CONFIG_PM_SLEEP 3066 #define IWL_TRANS_PM_OPS \ 3067 .suspend = iwl_trans_pcie_suspend, \ 3068 .resume = iwl_trans_pcie_resume, 3069 #else 3070 #define IWL_TRANS_PM_OPS 3071 #endif /* CONFIG_PM_SLEEP */ 3072 3073 static const struct iwl_trans_ops trans_ops_pcie = { 3074 IWL_TRANS_COMMON_OPS, 3075 IWL_TRANS_PM_OPS 3076 .start_hw = iwl_trans_pcie_start_hw, 3077 .fw_alive = iwl_trans_pcie_fw_alive, 3078 .start_fw = iwl_trans_pcie_start_fw, 3079 .stop_device = iwl_trans_pcie_stop_device, 3080 3081 .send_cmd = iwl_trans_pcie_send_hcmd, 3082 3083 .tx = iwl_trans_pcie_tx, 3084 .reclaim = iwl_trans_pcie_reclaim, 3085 3086 .txq_disable = iwl_trans_pcie_txq_disable, 3087 .txq_enable = iwl_trans_pcie_txq_enable, 3088 3089 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3090 3091 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3092 3093 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3094 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3095 }; 3096 3097 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3098 IWL_TRANS_COMMON_OPS, 3099 IWL_TRANS_PM_OPS 3100 .start_hw = iwl_trans_pcie_start_hw, 3101 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3102 .start_fw = iwl_trans_pcie_gen2_start_fw, 3103 .stop_device = iwl_trans_pcie_gen2_stop_device, 3104 3105 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3106 3107 .tx = iwl_trans_pcie_gen2_tx, 3108 .reclaim = iwl_trans_pcie_reclaim, 3109 3110 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3111 .txq_free = iwl_trans_pcie_dyn_txq_free, 3112 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3113 }; 3114 3115 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3116 const struct pci_device_id *ent, 3117 const struct iwl_cfg *cfg) 3118 { 3119 struct iwl_trans_pcie *trans_pcie; 3120 struct iwl_trans *trans; 3121 int ret, addr_size; 3122 3123 ret = pcim_enable_device(pdev); 3124 if (ret) 3125 return ERR_PTR(ret); 3126 3127 if (cfg->gen2) 3128 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3129 &pdev->dev, cfg, &trans_ops_pcie_gen2); 3130 else 3131 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3132 &pdev->dev, cfg, &trans_ops_pcie); 3133 if (!trans) 3134 return ERR_PTR(-ENOMEM); 3135 3136 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3137 3138 trans_pcie->trans = trans; 3139 trans_pcie->opmode_down = true; 3140 spin_lock_init(&trans_pcie->irq_lock); 3141 spin_lock_init(&trans_pcie->reg_lock); 3142 mutex_init(&trans_pcie->mutex); 3143 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3144 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3145 if (!trans_pcie->tso_hdr_page) { 3146 ret = -ENOMEM; 3147 goto out_no_pci; 3148 } 3149 3150 3151 if (!cfg->base_params->pcie_l1_allowed) { 3152 /* 3153 * W/A - seems to solve weird behavior. We need to remove this 3154 * if we don't want to stay in L1 all the time. This wastes a 3155 * lot of power. 3156 */ 3157 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3158 PCIE_LINK_STATE_L1 | 3159 PCIE_LINK_STATE_CLKPM); 3160 } 3161 3162 if (cfg->use_tfh) { 3163 addr_size = 64; 3164 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3165 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3166 } else { 3167 addr_size = 36; 3168 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3169 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3170 } 3171 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3172 3173 pci_set_master(pdev); 3174 3175 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3176 if (!ret) 3177 ret = pci_set_consistent_dma_mask(pdev, 3178 DMA_BIT_MASK(addr_size)); 3179 if (ret) { 3180 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3181 if (!ret) 3182 ret = pci_set_consistent_dma_mask(pdev, 3183 DMA_BIT_MASK(32)); 3184 /* both attempts failed: */ 3185 if (ret) { 3186 dev_err(&pdev->dev, "No suitable DMA available\n"); 3187 goto out_no_pci; 3188 } 3189 } 3190 3191 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3192 if (ret) { 3193 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3194 goto out_no_pci; 3195 } 3196 3197 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3198 if (!trans_pcie->hw_base) { 3199 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3200 ret = -ENODEV; 3201 goto out_no_pci; 3202 } 3203 3204 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3205 * PCI Tx retries from interfering with C3 CPU state */ 3206 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3207 3208 trans_pcie->pci_dev = pdev; 3209 iwl_disable_interrupts(trans); 3210 3211 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3212 /* 3213 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3214 * changed, and now the revision step also includes bit 0-1 (no more 3215 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3216 * in the old format. 3217 */ 3218 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3219 unsigned long flags; 3220 3221 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3222 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3223 3224 ret = iwl_pcie_prepare_card_hw(trans); 3225 if (ret) { 3226 IWL_WARN(trans, "Exit HW not ready\n"); 3227 goto out_no_pci; 3228 } 3229 3230 /* 3231 * in-order to recognize C step driver should read chip version 3232 * id located at the AUX bus MISC address space. 3233 */ 3234 iwl_set_bit(trans, CSR_GP_CNTRL, 3235 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3236 udelay(2); 3237 3238 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3239 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3240 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3241 25000); 3242 if (ret < 0) { 3243 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3244 goto out_no_pci; 3245 } 3246 3247 if (iwl_trans_grab_nic_access(trans, &flags)) { 3248 u32 hw_step; 3249 3250 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3251 hw_step |= ENABLE_WFPM; 3252 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3253 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3254 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3255 if (hw_step == 0x3) 3256 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3257 (SILICON_C_STEP << 2); 3258 iwl_trans_release_nic_access(trans, &flags); 3259 } 3260 } 3261 3262 /* 3263 * 9000-series integrated A-step has a problem with suspend/resume 3264 * and sometimes even causes the whole platform to get stuck. This 3265 * workaround makes the hardware not go into the problematic state. 3266 */ 3267 if (trans->cfg->integrated && 3268 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3269 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3270 iwl_set_bit(trans, CSR_HOST_CHICKEN, 3271 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3272 3273 #if IS_ENABLED(CONFIG_IWLMVM) 3274 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3275 if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) { 3276 u32 hw_status; 3277 3278 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3279 if (hw_status & UMAG_GEN_HW_IS_FPGA) 3280 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_f0; 3281 else 3282 trans->cfg = &iwl22000_2ac_cfg_hr; 3283 } 3284 #endif 3285 3286 iwl_pcie_set_interrupt_capa(pdev, trans); 3287 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3288 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3289 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3290 3291 /* Initialize the wait queue for commands */ 3292 init_waitqueue_head(&trans_pcie->wait_command_queue); 3293 3294 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3295 3296 if (trans_pcie->msix_enabled) { 3297 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3298 if (ret) 3299 goto out_no_pci; 3300 } else { 3301 ret = iwl_pcie_alloc_ict(trans); 3302 if (ret) 3303 goto out_no_pci; 3304 3305 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3306 iwl_pcie_isr, 3307 iwl_pcie_irq_handler, 3308 IRQF_SHARED, DRV_NAME, trans); 3309 if (ret) { 3310 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3311 goto out_free_ict; 3312 } 3313 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3314 } 3315 3316 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3317 WQ_HIGHPRI | WQ_UNBOUND, 1); 3318 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3319 3320 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3321 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3322 #else 3323 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3324 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3325 3326 return trans; 3327 3328 out_free_ict: 3329 iwl_pcie_free_ict(trans); 3330 out_no_pci: 3331 free_percpu(trans_pcie->tso_hdr_page); 3332 iwl_trans_free(trans); 3333 return ERR_PTR(ret); 3334 } 3335