1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "iwl-fw-error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92 { 93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94 95 if (!trans_pcie->fw_mon_page) 96 return; 97 98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100 __free_pages(trans_pcie->fw_mon_page, 101 get_order(trans_pcie->fw_mon_size)); 102 trans_pcie->fw_mon_page = NULL; 103 trans_pcie->fw_mon_phys = 0; 104 trans_pcie->fw_mon_size = 0; 105 } 106 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108 { 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110 struct page *page = NULL; 111 dma_addr_t phys; 112 u32 size = 0; 113 u8 power; 114 115 if (!max_power) { 116 /* default max_power is maximum */ 117 max_power = 26; 118 } else { 119 max_power += 11; 120 } 121 122 if (WARN(max_power > 26, 123 "External buffer size for monitor is too big %d, check the FW TLV\n", 124 max_power)) 125 return; 126 127 if (trans_pcie->fw_mon_page) { 128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129 trans_pcie->fw_mon_size, 130 DMA_FROM_DEVICE); 131 return; 132 } 133 134 phys = 0; 135 for (power = max_power; power >= 11; power--) { 136 int order; 137 138 size = BIT(power); 139 order = get_order(size); 140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141 order); 142 if (!page) 143 continue; 144 145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146 DMA_FROM_DEVICE); 147 if (dma_mapping_error(trans->dev, phys)) { 148 __free_pages(page, order); 149 page = NULL; 150 continue; 151 } 152 IWL_INFO(trans, 153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154 size, order); 155 break; 156 } 157 158 if (WARN_ON_ONCE(!page)) 159 return; 160 161 if (power != max_power) 162 IWL_ERR(trans, 163 "Sorry - debug buffer is only %luK while you requested %luK\n", 164 (unsigned long)BIT(power - 10), 165 (unsigned long)BIT(max_power - 10)); 166 167 trans_pcie->fw_mon_page = page; 168 trans_pcie->fw_mon_phys = phys; 169 trans_pcie->fw_mon_size = size; 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->cfg->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 static void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212 * Check if BIOS (or OS) enabled L1-ASPM on this device. 213 * If so (likely), disable L0S, so device moves directly L0->L1; 214 * costs negligible amount of power savings. 215 * If not (unlikely), enable L0S, so there is at least some 216 * power savings, even without L1. 217 */ 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221 else 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224 225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229 trans->ltr_enabled ? "En" : "Dis"); 230 } 231 232 /* 233 * Start up NIC's basic functionality after it has been reset 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235 * NOTE: This does not load uCode nor start the embedded processor 236 */ 237 static int iwl_pcie_apm_init(struct iwl_trans *trans) 238 { 239 int ret = 0; 240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 241 242 /* 243 * Use "set_bit" below rather than "write", to preserve any hardware 244 * bits already set by default after reset. 245 */ 246 247 /* Disable L0S exit timer (platform NMI Work/Around) */ 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 251 252 /* 253 * Disable L0s without affecting L1; 254 * don't wait for ICH L0s (ICH bug W/A) 255 */ 256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 258 259 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 261 262 /* 263 * Enable HAP INTA (interrupt from management bus) to 264 * wake device's PCI Express link L1a -> L0s 265 */ 266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 268 269 iwl_pcie_apm_config(trans); 270 271 /* Configure analog phase-lock-loop before activating to D0A */ 272 if (trans->cfg->base_params->pll_cfg) 273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 274 275 /* 276 * Set "initialization complete" bit to move adapter from 277 * D0U* --> D0A* (powered-up active) state. 278 */ 279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 280 281 /* 282 * Wait for clock stabilization; once stabilized, access to 283 * device-internal resources is supported, e.g. iwl_write_prph() 284 * and accesses to uCode SRAM. 285 */ 286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 289 if (ret < 0) { 290 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 291 goto out; 292 } 293 294 if (trans->cfg->host_interrupt_operation_mode) { 295 /* 296 * This is a bit of an abuse - This is needed for 7260 / 3160 297 * only check host_interrupt_operation_mode even if this is 298 * not related to host_interrupt_operation_mode. 299 * 300 * Enable the oscillator to count wake up time for L1 exit. This 301 * consumes slightly more power (100uA) - but allows to be sure 302 * that we wake up from L1 on time. 303 * 304 * This looks weird: read twice the same register, discard the 305 * value, set a bit, and yet again, read that same register 306 * just to discard the value. But that's the way the hardware 307 * seems to like it. 308 */ 309 iwl_read_prph(trans, OSC_CLK); 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 312 iwl_read_prph(trans, OSC_CLK); 313 iwl_read_prph(trans, OSC_CLK); 314 } 315 316 /* 317 * Enable DMA clock and wait for it to stabilize. 318 * 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 320 * bits do not disable clocks. This preserves any hardware 321 * bits already set by default in "CLK_CTRL_REG" after reset. 322 */ 323 if (!trans->cfg->apmg_not_supported) { 324 iwl_write_prph(trans, APMG_CLK_EN_REG, 325 APMG_CLK_VAL_DMA_CLK_RQT); 326 udelay(20); 327 328 /* Disable L1-Active */ 329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 331 332 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 334 APMG_RTC_INT_STT_RFKILL); 335 } 336 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 338 339 out: 340 return ret; 341 } 342 343 /* 344 * Enable LP XTAL to avoid HW bug where device may consume much power if 345 * FW is not loaded after device reset. LP XTAL is disabled by default 346 * after device HW reset. Do it only if XTAL is fed by internal source. 347 * Configure device's "persistence" mode to avoid resetting XTAL again when 348 * SHRD_HW_RST occurs in S3. 349 */ 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351 { 352 int ret; 353 u32 apmg_gp1_reg; 354 u32 apmg_xtal_cfg_reg; 355 u32 dl_cfg_reg; 356 357 /* Force XTAL ON */ 358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360 361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 363 usleep_range(1000, 2000); 364 365 /* 366 * Set "initialization complete" bit to move adapter from 367 * D0U* --> D0A* (powered-up active) state. 368 */ 369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 370 371 /* 372 * Wait for clock stabilization; once stabilized, access to 373 * device-internal resources is possible. 374 */ 375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378 25000); 379 if (WARN_ON(ret < 0)) { 380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 381 /* Release XTAL ON request */ 382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384 return; 385 } 386 387 /* 388 * Clear "disable persistence" to avoid LP XTAL resetting when 389 * SHRD_HW_RST is applied in S3. 390 */ 391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 392 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 393 394 /* 395 * Force APMG XTAL to be active to prevent its disabling by HW 396 * caused by APMG idle state. 397 */ 398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 399 SHR_APMG_XTAL_CFG_REG); 400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 401 apmg_xtal_cfg_reg | 402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 403 404 /* 405 * Reset entire device again - do controller reset (results in 406 * SHRD_HW_RST). Turn MAC off before proceeding. 407 */ 408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 409 usleep_range(1000, 2000); 410 411 /* Enable LP XTAL by indirect access through CSR */ 412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 414 SHR_APMG_GP1_WF_XTAL_LP_EN | 415 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 416 417 /* Clear delay line clock power up */ 418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 421 422 /* 423 * Enable persistence mode to avoid LP XTAL resetting when 424 * SHRD_HW_RST is applied in S3. 425 */ 426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 428 429 /* 430 * Clear "initialization complete" bit to move adapter from 431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 432 */ 433 iwl_clear_bit(trans, CSR_GP_CNTRL, 434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 435 436 /* Activates XTAL resources monitor */ 437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 438 CSR_MONITOR_XTAL_RESOURCES); 439 440 /* Release XTAL ON request */ 441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 443 udelay(10); 444 445 /* Release APMG XTAL */ 446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 447 apmg_xtal_cfg_reg & 448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 449 } 450 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 452 { 453 int ret = 0; 454 455 /* stop device's busmaster DMA activity */ 456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 457 458 ret = iwl_poll_bit(trans, CSR_RESET, 459 CSR_RESET_REG_FLAG_MASTER_DISABLED, 460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 461 if (ret < 0) 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 463 464 IWL_DEBUG_INFO(trans, "stop master\n"); 465 466 return ret; 467 } 468 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 470 { 471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 472 473 if (op_mode_leave) { 474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 475 iwl_pcie_apm_init(trans); 476 477 /* inform ME that we are leaving */ 478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 480 APMG_PCIDEV_STT_VAL_WAKE_ME); 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 483 CSR_RESET_LINK_PWR_MGMT_DISABLED); 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485 CSR_HW_IF_CONFIG_REG_PREPARE | 486 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 487 mdelay(1); 488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 489 CSR_RESET_LINK_PWR_MGMT_DISABLED); 490 } 491 mdelay(5); 492 } 493 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 495 496 /* Stop device's DMA activity */ 497 iwl_pcie_apm_stop_master(trans); 498 499 if (trans->cfg->lp_xtal_workaround) { 500 iwl_pcie_apm_lp_xtal_enable(trans); 501 return; 502 } 503 504 /* Reset the entire device */ 505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 506 usleep_range(1000, 2000); 507 508 /* 509 * Clear "initialization complete" bit to move adapter from 510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 511 */ 512 iwl_clear_bit(trans, CSR_GP_CNTRL, 513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 514 } 515 516 static int iwl_pcie_nic_init(struct iwl_trans *trans) 517 { 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 519 520 /* nic_init */ 521 spin_lock(&trans_pcie->irq_lock); 522 iwl_pcie_apm_init(trans); 523 524 spin_unlock(&trans_pcie->irq_lock); 525 526 iwl_pcie_set_pwr(trans, false); 527 528 iwl_op_mode_nic_config(trans->op_mode); 529 530 /* Allocate the RX queue, or reset if it is already allocated */ 531 iwl_pcie_rx_init(trans); 532 533 /* Allocate or reset and init all Tx and Command queues */ 534 if (iwl_pcie_tx_init(trans)) 535 return -ENOMEM; 536 537 if (trans->cfg->base_params->shadow_reg_enable) { 538 /* enable shadow regs in HW */ 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 541 } 542 543 return 0; 544 } 545 546 #define HW_READY_TIMEOUT (50) 547 548 /* Note: returns poll_bit return value, which is >= 0 if success */ 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 550 { 551 int ret; 552 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 555 556 /* See if we got it */ 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560 HW_READY_TIMEOUT); 561 562 if (ret >= 0) 563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 564 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 566 return ret; 567 } 568 569 /* Note: returns standard 0/-ERROR code */ 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 571 { 572 int ret; 573 int t = 0; 574 int iter; 575 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 577 578 ret = iwl_pcie_set_hw_ready(trans); 579 /* If the card is ready, exit 0 */ 580 if (ret >= 0) 581 return 0; 582 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 584 CSR_RESET_LINK_PWR_MGMT_DISABLED); 585 usleep_range(1000, 2000); 586 587 for (iter = 0; iter < 10; iter++) { 588 /* If HW is not ready, prepare the conditions to check again */ 589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 590 CSR_HW_IF_CONFIG_REG_PREPARE); 591 592 do { 593 ret = iwl_pcie_set_hw_ready(trans); 594 if (ret >= 0) 595 return 0; 596 597 usleep_range(200, 1000); 598 t += 200; 599 } while (t < 150000); 600 msleep(25); 601 } 602 603 IWL_ERR(trans, "Couldn't prepare the card\n"); 604 605 return ret; 606 } 607 608 /* 609 * ucode 610 */ 611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 612 u32 dst_addr, dma_addr_t phy_addr, 613 u32 byte_cnt) 614 { 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 617 618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 619 dst_addr); 620 621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 623 624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 625 (iwl_get_dma_hi_addr(phy_addr) 626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 627 628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 632 633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 637 } 638 639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans, 640 u32 dst_addr, dma_addr_t phy_addr, 641 u32 byte_cnt) 642 { 643 /* Stop DMA channel */ 644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0); 645 646 /* Configure SRAM address */ 647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR, 648 dst_addr); 649 650 /* Configure DRAM address - 64 bit */ 651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr); 652 653 /* Configure byte count to transfer */ 654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt); 655 656 /* Enable the DRAM2SRAM to start */ 657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP | 658 TFH_SRV_DMA_TO_DRIVER | 659 TFH_SRV_DMA_START); 660 } 661 662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 663 u32 dst_addr, dma_addr_t phy_addr, 664 u32 byte_cnt) 665 { 666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 667 unsigned long flags; 668 int ret; 669 670 trans_pcie->ucode_write_complete = false; 671 672 if (!iwl_trans_grab_nic_access(trans, &flags)) 673 return -EIO; 674 675 if (trans->cfg->use_tfh) 676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr, 677 byte_cnt); 678 else 679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 680 byte_cnt); 681 iwl_trans_release_nic_access(trans, &flags); 682 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 684 trans_pcie->ucode_write_complete, 5 * HZ); 685 if (!ret) { 686 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 687 return -ETIMEDOUT; 688 } 689 690 return 0; 691 } 692 693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 694 const struct fw_desc *section) 695 { 696 u8 *v_addr; 697 dma_addr_t p_addr; 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 699 int ret = 0; 700 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 702 section_num); 703 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 705 GFP_KERNEL | __GFP_NOWARN); 706 if (!v_addr) { 707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 708 chunk_sz = PAGE_SIZE; 709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 710 &p_addr, GFP_KERNEL); 711 if (!v_addr) 712 return -ENOMEM; 713 } 714 715 for (offset = 0; offset < section->len; offset += chunk_sz) { 716 u32 copy_size, dst_addr; 717 bool extended_addr = false; 718 719 copy_size = min_t(u32, chunk_sz, section->len - offset); 720 dst_addr = section->offset + offset; 721 722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 723 dst_addr <= IWL_FW_MEM_EXTENDED_END) 724 extended_addr = true; 725 726 if (extended_addr) 727 iwl_set_bits_prph(trans, LMPM_CHICK, 728 LMPM_CHICK_EXTENDED_ADDR_SPACE); 729 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 732 copy_size); 733 734 if (extended_addr) 735 iwl_clear_bits_prph(trans, LMPM_CHICK, 736 LMPM_CHICK_EXTENDED_ADDR_SPACE); 737 738 if (ret) { 739 IWL_ERR(trans, 740 "Could not load the [%d] uCode section\n", 741 section_num); 742 break; 743 } 744 } 745 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 747 return ret; 748 } 749 750 /* 751 * Driver Takes the ownership on secure machine before FW load 752 * and prevent race with the BT load. 753 * W/A for ROM bug. (should be remove in the next Si step) 754 */ 755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 756 { 757 u32 val, loop = 1000; 758 759 /* 760 * Check the RSA semaphore is accessible. 761 * If the HW isn't locked and the rsa semaphore isn't accessible, 762 * we are in trouble. 763 */ 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 765 if (val & (BIT(1) | BIT(17))) { 766 IWL_DEBUG_INFO(trans, 767 "can't access the RSA semaphore it is write protected\n"); 768 return 0; 769 } 770 771 /* take ownership on the AUX IF */ 772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 774 775 do { 776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 778 if (val == 0x1) { 779 iwl_write_prph(trans, RSA_ENABLE, 0); 780 return 0; 781 } 782 783 udelay(10); 784 loop--; 785 } while (loop > 0); 786 787 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 788 return -EIO; 789 } 790 791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 792 const struct fw_img *image, 793 int cpu, 794 int *first_ucode_section) 795 { 796 int shift_param; 797 int i, ret = 0, sec_num = 0x1; 798 u32 val, last_read_idx = 0; 799 800 if (cpu == 1) { 801 shift_param = 0; 802 *first_ucode_section = 0; 803 } else { 804 shift_param = 16; 805 (*first_ucode_section)++; 806 } 807 808 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 809 last_read_idx = i; 810 811 /* 812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 813 * CPU1 to CPU2. 814 * PAGING_SEPARATOR_SECTION delimiter - separate between 815 * CPU2 non paged to CPU2 paging sec. 816 */ 817 if (!image->sec[i].data || 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 820 IWL_DEBUG_FW(trans, 821 "Break since Data not valid or Empty section, sec = %d\n", 822 i); 823 break; 824 } 825 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 827 if (ret) 828 return ret; 829 830 /* Notify ucode of loaded section number and status */ 831 if (trans->cfg->use_tfh) { 832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS); 833 val = val | (sec_num << shift_param); 834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val); 835 } else { 836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 837 val = val | (sec_num << shift_param); 838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 839 } 840 sec_num = (sec_num << 1) | 0x1; 841 } 842 843 *first_ucode_section = last_read_idx; 844 845 iwl_enable_interrupts(trans); 846 847 if (trans->cfg->use_tfh) { 848 if (cpu == 1) 849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 850 0xFFFF); 851 else 852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 853 0xFFFFFFFF); 854 } else { 855 if (cpu == 1) 856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 857 0xFFFF); 858 else 859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 860 0xFFFFFFFF); 861 } 862 863 return 0; 864 } 865 866 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 867 const struct fw_img *image, 868 int cpu, 869 int *first_ucode_section) 870 { 871 int shift_param; 872 int i, ret = 0; 873 u32 last_read_idx = 0; 874 875 if (cpu == 1) { 876 shift_param = 0; 877 *first_ucode_section = 0; 878 } else { 879 shift_param = 16; 880 (*first_ucode_section)++; 881 } 882 883 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 884 last_read_idx = i; 885 886 /* 887 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 888 * CPU1 to CPU2. 889 * PAGING_SEPARATOR_SECTION delimiter - separate between 890 * CPU2 non paged to CPU2 paging sec. 891 */ 892 if (!image->sec[i].data || 893 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 894 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 895 IWL_DEBUG_FW(trans, 896 "Break since Data not valid or Empty section, sec = %d\n", 897 i); 898 break; 899 } 900 901 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 902 if (ret) 903 return ret; 904 } 905 906 *first_ucode_section = last_read_idx; 907 908 return 0; 909 } 910 911 static void iwl_pcie_apply_destination(struct iwl_trans *trans) 912 { 913 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 914 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 915 int i; 916 917 if (dest->version) 918 IWL_ERR(trans, 919 "DBG DEST version is %d - expect issues\n", 920 dest->version); 921 922 IWL_INFO(trans, "Applying debug destination %s\n", 923 get_fw_dbg_mode_string(dest->monitor_mode)); 924 925 if (dest->monitor_mode == EXTERNAL_MODE) 926 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 927 else 928 IWL_WARN(trans, "PCI should have external buffer debug\n"); 929 930 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 931 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 932 u32 val = le32_to_cpu(dest->reg_ops[i].val); 933 934 switch (dest->reg_ops[i].op) { 935 case CSR_ASSIGN: 936 iwl_write32(trans, addr, val); 937 break; 938 case CSR_SETBIT: 939 iwl_set_bit(trans, addr, BIT(val)); 940 break; 941 case CSR_CLEARBIT: 942 iwl_clear_bit(trans, addr, BIT(val)); 943 break; 944 case PRPH_ASSIGN: 945 iwl_write_prph(trans, addr, val); 946 break; 947 case PRPH_SETBIT: 948 iwl_set_bits_prph(trans, addr, BIT(val)); 949 break; 950 case PRPH_CLEARBIT: 951 iwl_clear_bits_prph(trans, addr, BIT(val)); 952 break; 953 case PRPH_BLOCKBIT: 954 if (iwl_read_prph(trans, addr) & BIT(val)) { 955 IWL_ERR(trans, 956 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 957 val, addr); 958 goto monitor; 959 } 960 break; 961 default: 962 IWL_ERR(trans, "FW debug - unknown OP %d\n", 963 dest->reg_ops[i].op); 964 break; 965 } 966 } 967 968 monitor: 969 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 970 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 971 trans_pcie->fw_mon_phys >> dest->base_shift); 972 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 973 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 974 (trans_pcie->fw_mon_phys + 975 trans_pcie->fw_mon_size - 256) >> 976 dest->end_shift); 977 else 978 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 979 (trans_pcie->fw_mon_phys + 980 trans_pcie->fw_mon_size) >> 981 dest->end_shift); 982 } 983 } 984 985 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 986 const struct fw_img *image) 987 { 988 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 989 int ret = 0; 990 int first_ucode_section; 991 992 IWL_DEBUG_FW(trans, "working with %s CPU\n", 993 image->is_dual_cpus ? "Dual" : "Single"); 994 995 /* load to FW the binary non secured sections of CPU1 */ 996 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 997 if (ret) 998 return ret; 999 1000 if (image->is_dual_cpus) { 1001 /* set CPU2 header address */ 1002 iwl_write_prph(trans, 1003 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1004 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1005 1006 /* load to FW the binary sections of CPU2 */ 1007 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1008 &first_ucode_section); 1009 if (ret) 1010 return ret; 1011 } 1012 1013 /* supported for 7000 only for the moment */ 1014 if (iwlwifi_mod_params.fw_monitor && 1015 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1016 iwl_pcie_alloc_fw_monitor(trans, 0); 1017 1018 if (trans_pcie->fw_mon_size) { 1019 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1020 trans_pcie->fw_mon_phys >> 4); 1021 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1022 (trans_pcie->fw_mon_phys + 1023 trans_pcie->fw_mon_size) >> 4); 1024 } 1025 } else if (trans->dbg_dest_tlv) { 1026 iwl_pcie_apply_destination(trans); 1027 } 1028 1029 iwl_enable_interrupts(trans); 1030 1031 /* release CPU reset */ 1032 iwl_write32(trans, CSR_RESET, 0); 1033 1034 return 0; 1035 } 1036 1037 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1038 const struct fw_img *image) 1039 { 1040 int ret = 0; 1041 int first_ucode_section; 1042 1043 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1044 image->is_dual_cpus ? "Dual" : "Single"); 1045 1046 if (trans->dbg_dest_tlv) 1047 iwl_pcie_apply_destination(trans); 1048 1049 /* TODO: remove in the next Si step */ 1050 ret = iwl_pcie_rsa_race_bug_wa(trans); 1051 if (ret) 1052 return ret; 1053 1054 /* configure the ucode to be ready to get the secured image */ 1055 /* release CPU reset */ 1056 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1057 1058 /* load to FW the binary Secured sections of CPU1 */ 1059 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1060 &first_ucode_section); 1061 if (ret) 1062 return ret; 1063 1064 /* load to FW the binary sections of CPU2 */ 1065 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1066 &first_ucode_section); 1067 } 1068 1069 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1070 { 1071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1072 bool hw_rfkill, was_hw_rfkill; 1073 1074 lockdep_assert_held(&trans_pcie->mutex); 1075 1076 if (trans_pcie->is_down) 1077 return; 1078 1079 trans_pcie->is_down = true; 1080 1081 was_hw_rfkill = iwl_is_rfkill_set(trans); 1082 1083 /* tell the device to stop sending interrupts */ 1084 iwl_disable_interrupts(trans); 1085 1086 /* device going down, Stop using ICT table */ 1087 iwl_pcie_disable_ict(trans); 1088 1089 /* 1090 * If a HW restart happens during firmware loading, 1091 * then the firmware loading might call this function 1092 * and later it might be called again due to the 1093 * restart. So don't process again if the device is 1094 * already dead. 1095 */ 1096 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1097 IWL_DEBUG_INFO(trans, 1098 "DEVICE_ENABLED bit was set and is now cleared\n"); 1099 iwl_pcie_tx_stop(trans); 1100 iwl_pcie_rx_stop(trans); 1101 1102 /* Power-down device's busmaster DMA clocks */ 1103 if (!trans->cfg->apmg_not_supported) { 1104 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1105 APMG_CLK_VAL_DMA_CLK_RQT); 1106 udelay(5); 1107 } 1108 } 1109 1110 /* Make sure (redundant) we've released our request to stay awake */ 1111 iwl_clear_bit(trans, CSR_GP_CNTRL, 1112 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1113 1114 /* Stop the device, and put it in low power state */ 1115 iwl_pcie_apm_stop(trans, false); 1116 1117 /* stop and reset the on-board processor */ 1118 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1119 usleep_range(1000, 2000); 1120 1121 /* 1122 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1123 * This is a bug in certain verions of the hardware. 1124 * Certain devices also keep sending HW RF kill interrupt all 1125 * the time, unless the interrupt is ACKed even if the interrupt 1126 * should be masked. Re-ACK all the interrupts here. 1127 */ 1128 iwl_disable_interrupts(trans); 1129 1130 /* clear all status bits */ 1131 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1132 clear_bit(STATUS_INT_ENABLED, &trans->status); 1133 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1134 clear_bit(STATUS_RFKILL, &trans->status); 1135 1136 /* 1137 * Even if we stop the HW, we still want the RF kill 1138 * interrupt 1139 */ 1140 iwl_enable_rfkill_int(trans); 1141 1142 /* 1143 * Check again since the RF kill state may have changed while 1144 * all the interrupts were disabled, in this case we couldn't 1145 * receive the RF kill interrupt and update the state in the 1146 * op_mode. 1147 * Don't call the op_mode if the rkfill state hasn't changed. 1148 * This allows the op_mode to call stop_device from the rfkill 1149 * notification without endless recursion. Under very rare 1150 * circumstances, we might have a small recursion if the rfkill 1151 * state changed exactly now while we were called from stop_device. 1152 * This is very unlikely but can happen and is supported. 1153 */ 1154 hw_rfkill = iwl_is_rfkill_set(trans); 1155 if (hw_rfkill) 1156 set_bit(STATUS_RFKILL, &trans->status); 1157 else 1158 clear_bit(STATUS_RFKILL, &trans->status); 1159 if (hw_rfkill != was_hw_rfkill) 1160 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1161 1162 /* re-take ownership to prevent other users from stealing the device */ 1163 iwl_pcie_prepare_card_hw(trans); 1164 } 1165 1166 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1167 { 1168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1169 1170 if (trans_pcie->msix_enabled) { 1171 int i; 1172 1173 for (i = 0; i < trans_pcie->allocated_vector; i++) 1174 synchronize_irq(trans_pcie->msix_entries[i].vector); 1175 } else { 1176 synchronize_irq(trans_pcie->pci_dev->irq); 1177 } 1178 } 1179 1180 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1181 const struct fw_img *fw, bool run_in_rfkill) 1182 { 1183 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1184 bool hw_rfkill; 1185 int ret; 1186 1187 /* This may fail if AMT took ownership of the device */ 1188 if (iwl_pcie_prepare_card_hw(trans)) { 1189 IWL_WARN(trans, "Exit HW not ready\n"); 1190 ret = -EIO; 1191 goto out; 1192 } 1193 1194 iwl_enable_rfkill_int(trans); 1195 1196 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1197 1198 /* 1199 * We enabled the RF-Kill interrupt and the handler may very 1200 * well be running. Disable the interrupts to make sure no other 1201 * interrupt can be fired. 1202 */ 1203 iwl_disable_interrupts(trans); 1204 1205 /* Make sure it finished running */ 1206 iwl_pcie_synchronize_irqs(trans); 1207 1208 mutex_lock(&trans_pcie->mutex); 1209 1210 /* If platform's RF_KILL switch is NOT set to KILL */ 1211 hw_rfkill = iwl_is_rfkill_set(trans); 1212 if (hw_rfkill) 1213 set_bit(STATUS_RFKILL, &trans->status); 1214 else 1215 clear_bit(STATUS_RFKILL, &trans->status); 1216 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1217 if (hw_rfkill && !run_in_rfkill) { 1218 ret = -ERFKILL; 1219 goto out; 1220 } 1221 1222 /* Someone called stop_device, don't try to start_fw */ 1223 if (trans_pcie->is_down) { 1224 IWL_WARN(trans, 1225 "Can't start_fw since the HW hasn't been started\n"); 1226 ret = -EIO; 1227 goto out; 1228 } 1229 1230 /* make sure rfkill handshake bits are cleared */ 1231 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1232 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1233 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1234 1235 /* clear (again), then enable host interrupts */ 1236 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1237 1238 ret = iwl_pcie_nic_init(trans); 1239 if (ret) { 1240 IWL_ERR(trans, "Unable to init nic\n"); 1241 goto out; 1242 } 1243 1244 /* 1245 * Now, we load the firmware and don't want to be interrupted, even 1246 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1247 * FH_TX interrupt which is needed to load the firmware). If the 1248 * RF-Kill switch is toggled, we will find out after having loaded 1249 * the firmware and return the proper value to the caller. 1250 */ 1251 iwl_enable_fw_load_int(trans); 1252 1253 /* really make sure rfkill handshake bits are cleared */ 1254 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1255 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1256 1257 /* Load the given image to the HW */ 1258 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1259 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1260 else 1261 ret = iwl_pcie_load_given_ucode(trans, fw); 1262 1263 /* re-check RF-Kill state since we may have missed the interrupt */ 1264 hw_rfkill = iwl_is_rfkill_set(trans); 1265 if (hw_rfkill) 1266 set_bit(STATUS_RFKILL, &trans->status); 1267 else 1268 clear_bit(STATUS_RFKILL, &trans->status); 1269 1270 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1271 if (hw_rfkill && !run_in_rfkill) 1272 ret = -ERFKILL; 1273 1274 out: 1275 mutex_unlock(&trans_pcie->mutex); 1276 return ret; 1277 } 1278 1279 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1280 { 1281 iwl_pcie_reset_ict(trans); 1282 iwl_pcie_tx_start(trans, scd_addr); 1283 } 1284 1285 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1286 { 1287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1288 1289 mutex_lock(&trans_pcie->mutex); 1290 _iwl_trans_pcie_stop_device(trans, low_power); 1291 mutex_unlock(&trans_pcie->mutex); 1292 } 1293 1294 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1295 { 1296 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1297 IWL_TRANS_GET_PCIE_TRANS(trans); 1298 1299 lockdep_assert_held(&trans_pcie->mutex); 1300 1301 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1302 _iwl_trans_pcie_stop_device(trans, true); 1303 } 1304 1305 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1306 bool reset) 1307 { 1308 if (!reset) { 1309 /* Enable persistence mode to avoid reset */ 1310 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1311 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1312 } 1313 1314 iwl_disable_interrupts(trans); 1315 1316 /* 1317 * in testing mode, the host stays awake and the 1318 * hardware won't be reset (not even partially) 1319 */ 1320 if (test) 1321 return; 1322 1323 iwl_pcie_disable_ict(trans); 1324 1325 iwl_pcie_synchronize_irqs(trans); 1326 1327 iwl_clear_bit(trans, CSR_GP_CNTRL, 1328 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1329 iwl_clear_bit(trans, CSR_GP_CNTRL, 1330 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1331 1332 iwl_pcie_enable_rx_wake(trans, false); 1333 1334 if (reset) { 1335 /* 1336 * reset TX queues -- some of their registers reset during S3 1337 * so if we don't reset everything here the D3 image would try 1338 * to execute some invalid memory upon resume 1339 */ 1340 iwl_trans_pcie_tx_reset(trans); 1341 } 1342 1343 iwl_pcie_set_pwr(trans, true); 1344 } 1345 1346 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1347 enum iwl_d3_status *status, 1348 bool test, bool reset) 1349 { 1350 u32 val; 1351 int ret; 1352 1353 if (test) { 1354 iwl_enable_interrupts(trans); 1355 *status = IWL_D3_STATUS_ALIVE; 1356 return 0; 1357 } 1358 1359 iwl_pcie_enable_rx_wake(trans, true); 1360 1361 /* 1362 * Also enables interrupts - none will happen as the device doesn't 1363 * know we're waking it up, only when the opmode actually tells it 1364 * after this call. 1365 */ 1366 iwl_pcie_reset_ict(trans); 1367 iwl_enable_interrupts(trans); 1368 1369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1370 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1371 1372 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1373 udelay(2); 1374 1375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1378 25000); 1379 if (ret < 0) { 1380 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1381 return ret; 1382 } 1383 1384 iwl_pcie_set_pwr(trans, false); 1385 1386 if (!reset) { 1387 iwl_clear_bit(trans, CSR_GP_CNTRL, 1388 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1389 } else { 1390 iwl_trans_pcie_tx_reset(trans); 1391 1392 ret = iwl_pcie_rx_init(trans); 1393 if (ret) { 1394 IWL_ERR(trans, 1395 "Failed to resume the device (RX reset)\n"); 1396 return ret; 1397 } 1398 } 1399 1400 val = iwl_read32(trans, CSR_RESET); 1401 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1402 *status = IWL_D3_STATUS_RESET; 1403 else 1404 *status = IWL_D3_STATUS_ALIVE; 1405 1406 return 0; 1407 } 1408 1409 struct iwl_causes_list { 1410 u32 cause_num; 1411 u32 mask_reg; 1412 u8 addr; 1413 }; 1414 1415 static struct iwl_causes_list causes_list[] = { 1416 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1417 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1418 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1419 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1420 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1421 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1422 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1423 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1424 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1425 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1426 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1427 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1428 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1429 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1430 }; 1431 1432 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1433 { 1434 u32 val, max_rx_vector, i; 1435 struct iwl_trans *trans = trans_pcie->trans; 1436 1437 max_rx_vector = trans_pcie->allocated_vector - 1; 1438 1439 if (!trans_pcie->msix_enabled) { 1440 if (trans->cfg->mq_rx_supported) 1441 iwl_write_prph(trans, UREG_CHICK, 1442 UREG_CHICK_MSI_ENABLE); 1443 return; 1444 } 1445 1446 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1447 1448 /* 1449 * Each cause from the list above and the RX causes is represented as 1450 * a byte in the IVAR table. We access the first (N - 1) bytes and map 1451 * them to the (N - 1) vectors so these vectors will be used as rx 1452 * vectors. Then access all non rx causes and map them to the 1453 * default queue (N'th queue). 1454 */ 1455 for (i = 0; i < max_rx_vector; i++) { 1456 iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i)); 1457 iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD, 1458 BIT(MSIX_FH_INT_CAUSES_Q(i))); 1459 } 1460 1461 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1462 val = trans_pcie->default_irq_num | 1463 MSIX_NON_AUTO_CLEAR_CAUSE; 1464 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1465 iwl_clear_bit(trans, causes_list[i].mask_reg, 1466 causes_list[i].cause_num); 1467 } 1468 trans_pcie->fh_init_mask = 1469 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1470 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1471 trans_pcie->hw_init_mask = 1472 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1473 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1474 } 1475 1476 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1477 struct iwl_trans *trans) 1478 { 1479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1480 u16 pci_cmd; 1481 int max_vector; 1482 int ret, i; 1483 1484 if (trans->cfg->mq_rx_supported) { 1485 max_vector = min_t(u32, (num_possible_cpus() + 2), 1486 IWL_MAX_RX_HW_QUEUES); 1487 for (i = 0; i < max_vector; i++) 1488 trans_pcie->msix_entries[i].entry = i; 1489 1490 ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1491 MSIX_MIN_INTERRUPT_VECTORS, 1492 max_vector); 1493 if (ret > 1) { 1494 IWL_DEBUG_INFO(trans, 1495 "Enable MSI-X allocate %d interrupt vector\n", 1496 ret); 1497 trans_pcie->allocated_vector = ret; 1498 trans_pcie->default_irq_num = 1499 trans_pcie->allocated_vector - 1; 1500 trans_pcie->trans->num_rx_queues = 1501 trans_pcie->allocated_vector - 1; 1502 trans_pcie->msix_enabled = true; 1503 1504 return; 1505 } 1506 IWL_DEBUG_INFO(trans, 1507 "ret = %d %s move to msi mode\n", ret, 1508 (ret == 1) ? 1509 "can't allocate more than 1 interrupt vector" : 1510 "failed to enable msi-x mode"); 1511 pci_disable_msix(pdev); 1512 } 1513 1514 ret = pci_enable_msi(pdev); 1515 if (ret) { 1516 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1517 /* enable rfkill interrupt: hw bug w/a */ 1518 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1519 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1520 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1521 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1522 } 1523 } 1524 } 1525 1526 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1527 struct iwl_trans_pcie *trans_pcie) 1528 { 1529 int i, last_vector; 1530 1531 last_vector = trans_pcie->trans->num_rx_queues; 1532 1533 for (i = 0; i < trans_pcie->allocated_vector; i++) { 1534 int ret; 1535 1536 ret = request_threaded_irq(trans_pcie->msix_entries[i].vector, 1537 iwl_pcie_msix_isr, 1538 (i == last_vector) ? 1539 iwl_pcie_irq_msix_handler : 1540 iwl_pcie_irq_rx_msix_handler, 1541 IRQF_SHARED, 1542 DRV_NAME, 1543 &trans_pcie->msix_entries[i]); 1544 if (ret) { 1545 int j; 1546 1547 IWL_ERR(trans_pcie->trans, 1548 "Error allocating IRQ %d\n", i); 1549 for (j = 0; j < i; j++) 1550 free_irq(trans_pcie->msix_entries[j].vector, 1551 &trans_pcie->msix_entries[j]); 1552 pci_disable_msix(pdev); 1553 return ret; 1554 } 1555 } 1556 1557 return 0; 1558 } 1559 1560 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1561 { 1562 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1563 bool hw_rfkill; 1564 int err; 1565 1566 lockdep_assert_held(&trans_pcie->mutex); 1567 1568 err = iwl_pcie_prepare_card_hw(trans); 1569 if (err) { 1570 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1571 return err; 1572 } 1573 1574 /* Reset the entire device */ 1575 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1576 usleep_range(1000, 2000); 1577 1578 iwl_pcie_apm_init(trans); 1579 1580 iwl_pcie_init_msix(trans_pcie); 1581 /* From now on, the op_mode will be kept updated about RF kill state */ 1582 iwl_enable_rfkill_int(trans); 1583 1584 /* Set is_down to false here so that...*/ 1585 trans_pcie->is_down = false; 1586 1587 hw_rfkill = iwl_is_rfkill_set(trans); 1588 if (hw_rfkill) 1589 set_bit(STATUS_RFKILL, &trans->status); 1590 else 1591 clear_bit(STATUS_RFKILL, &trans->status); 1592 /* ... rfkill can call stop_device and set it false if needed */ 1593 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1594 1595 /* Make sure we sync here, because we'll need full access later */ 1596 if (low_power) 1597 pm_runtime_resume(trans->dev); 1598 1599 return 0; 1600 } 1601 1602 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1603 { 1604 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1605 int ret; 1606 1607 mutex_lock(&trans_pcie->mutex); 1608 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1609 mutex_unlock(&trans_pcie->mutex); 1610 1611 return ret; 1612 } 1613 1614 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1615 { 1616 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1617 1618 mutex_lock(&trans_pcie->mutex); 1619 1620 /* disable interrupts - don't enable HW RF kill interrupt */ 1621 iwl_disable_interrupts(trans); 1622 1623 iwl_pcie_apm_stop(trans, true); 1624 1625 iwl_disable_interrupts(trans); 1626 1627 iwl_pcie_disable_ict(trans); 1628 1629 mutex_unlock(&trans_pcie->mutex); 1630 1631 iwl_pcie_synchronize_irqs(trans); 1632 } 1633 1634 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1635 { 1636 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1637 } 1638 1639 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1640 { 1641 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1642 } 1643 1644 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1645 { 1646 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1647 } 1648 1649 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1650 { 1651 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1652 ((reg & 0x000FFFFF) | (3 << 24))); 1653 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1654 } 1655 1656 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1657 u32 val) 1658 { 1659 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1660 ((addr & 0x000FFFFF) | (3 << 24))); 1661 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1662 } 1663 1664 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1665 const struct iwl_trans_config *trans_cfg) 1666 { 1667 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1668 1669 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1670 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1671 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1672 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1673 trans_pcie->n_no_reclaim_cmds = 0; 1674 else 1675 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1676 if (trans_pcie->n_no_reclaim_cmds) 1677 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1678 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1679 1680 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1681 trans_pcie->rx_page_order = 1682 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1683 1684 trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; 1685 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1686 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1687 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1688 1689 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1690 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1691 1692 trans->command_groups = trans_cfg->command_groups; 1693 trans->command_groups_size = trans_cfg->command_groups_size; 1694 1695 /* Initialize NAPI here - it should be before registering to mac80211 1696 * in the opmode but after the HW struct is allocated. 1697 * As this function may be called again in some corner cases don't 1698 * do anything if NAPI was already initialized. 1699 */ 1700 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1701 init_dummy_netdev(&trans_pcie->napi_dev); 1702 } 1703 1704 void iwl_trans_pcie_free(struct iwl_trans *trans) 1705 { 1706 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1707 int i; 1708 1709 iwl_pcie_synchronize_irqs(trans); 1710 1711 iwl_pcie_tx_free(trans); 1712 iwl_pcie_rx_free(trans); 1713 1714 if (trans_pcie->msix_enabled) { 1715 for (i = 0; i < trans_pcie->allocated_vector; i++) 1716 free_irq(trans_pcie->msix_entries[i].vector, 1717 &trans_pcie->msix_entries[i]); 1718 1719 pci_disable_msix(trans_pcie->pci_dev); 1720 trans_pcie->msix_enabled = false; 1721 } else { 1722 free_irq(trans_pcie->pci_dev->irq, trans); 1723 1724 iwl_pcie_free_ict(trans); 1725 1726 pci_disable_msi(trans_pcie->pci_dev); 1727 } 1728 iounmap(trans_pcie->hw_base); 1729 pci_release_regions(trans_pcie->pci_dev); 1730 pci_disable_device(trans_pcie->pci_dev); 1731 1732 iwl_pcie_free_fw_monitor(trans); 1733 1734 for_each_possible_cpu(i) { 1735 struct iwl_tso_hdr_page *p = 1736 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1737 1738 if (p->page) 1739 __free_page(p->page); 1740 } 1741 1742 free_percpu(trans_pcie->tso_hdr_page); 1743 mutex_destroy(&trans_pcie->mutex); 1744 iwl_trans_free(trans); 1745 } 1746 1747 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1748 { 1749 if (state) 1750 set_bit(STATUS_TPOWER_PMI, &trans->status); 1751 else 1752 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1753 } 1754 1755 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1756 unsigned long *flags) 1757 { 1758 int ret; 1759 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1760 1761 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1762 1763 if (trans_pcie->cmd_hold_nic_awake) 1764 goto out; 1765 1766 /* this bit wakes up the NIC */ 1767 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1768 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1769 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1770 udelay(2); 1771 1772 /* 1773 * These bits say the device is running, and should keep running for 1774 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1775 * but they do not indicate that embedded SRAM is restored yet; 1776 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1777 * to/from host DRAM when sleeping/waking for power-saving. 1778 * Each direction takes approximately 1/4 millisecond; with this 1779 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1780 * series of register accesses are expected (e.g. reading Event Log), 1781 * to keep device from sleeping. 1782 * 1783 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1784 * SRAM is okay/restored. We don't check that here because this call 1785 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1786 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1787 * 1788 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1789 * and do not save/restore SRAM when power cycling. 1790 */ 1791 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1792 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1793 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1794 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1795 if (unlikely(ret < 0)) { 1796 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1797 WARN_ONCE(1, 1798 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1799 iwl_read32(trans, CSR_GP_CNTRL)); 1800 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1801 return false; 1802 } 1803 1804 out: 1805 /* 1806 * Fool sparse by faking we release the lock - sparse will 1807 * track nic_access anyway. 1808 */ 1809 __release(&trans_pcie->reg_lock); 1810 return true; 1811 } 1812 1813 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1814 unsigned long *flags) 1815 { 1816 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1817 1818 lockdep_assert_held(&trans_pcie->reg_lock); 1819 1820 /* 1821 * Fool sparse by faking we acquiring the lock - sparse will 1822 * track nic_access anyway. 1823 */ 1824 __acquire(&trans_pcie->reg_lock); 1825 1826 if (trans_pcie->cmd_hold_nic_awake) 1827 goto out; 1828 1829 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1830 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1831 /* 1832 * Above we read the CSR_GP_CNTRL register, which will flush 1833 * any previous writes, but we need the write that clears the 1834 * MAC_ACCESS_REQ bit to be performed before any other writes 1835 * scheduled on different CPUs (after we drop reg_lock). 1836 */ 1837 mmiowb(); 1838 out: 1839 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1840 } 1841 1842 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1843 void *buf, int dwords) 1844 { 1845 unsigned long flags; 1846 int offs, ret = 0; 1847 u32 *vals = buf; 1848 1849 if (iwl_trans_grab_nic_access(trans, &flags)) { 1850 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1851 for (offs = 0; offs < dwords; offs++) 1852 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1853 iwl_trans_release_nic_access(trans, &flags); 1854 } else { 1855 ret = -EBUSY; 1856 } 1857 return ret; 1858 } 1859 1860 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1861 const void *buf, int dwords) 1862 { 1863 unsigned long flags; 1864 int offs, ret = 0; 1865 const u32 *vals = buf; 1866 1867 if (iwl_trans_grab_nic_access(trans, &flags)) { 1868 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1869 for (offs = 0; offs < dwords; offs++) 1870 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1871 vals ? vals[offs] : 0); 1872 iwl_trans_release_nic_access(trans, &flags); 1873 } else { 1874 ret = -EBUSY; 1875 } 1876 return ret; 1877 } 1878 1879 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1880 unsigned long txqs, 1881 bool freeze) 1882 { 1883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1884 int queue; 1885 1886 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1887 struct iwl_txq *txq = &trans_pcie->txq[queue]; 1888 unsigned long now; 1889 1890 spin_lock_bh(&txq->lock); 1891 1892 now = jiffies; 1893 1894 if (txq->frozen == freeze) 1895 goto next_queue; 1896 1897 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1898 freeze ? "Freezing" : "Waking", queue); 1899 1900 txq->frozen = freeze; 1901 1902 if (txq->q.read_ptr == txq->q.write_ptr) 1903 goto next_queue; 1904 1905 if (freeze) { 1906 if (unlikely(time_after(now, 1907 txq->stuck_timer.expires))) { 1908 /* 1909 * The timer should have fired, maybe it is 1910 * spinning right now on the lock. 1911 */ 1912 goto next_queue; 1913 } 1914 /* remember how long until the timer fires */ 1915 txq->frozen_expiry_remainder = 1916 txq->stuck_timer.expires - now; 1917 del_timer(&txq->stuck_timer); 1918 goto next_queue; 1919 } 1920 1921 /* 1922 * Wake a non-empty queue -> arm timer with the 1923 * remainder before it froze 1924 */ 1925 mod_timer(&txq->stuck_timer, 1926 now + txq->frozen_expiry_remainder); 1927 1928 next_queue: 1929 spin_unlock_bh(&txq->lock); 1930 } 1931 } 1932 1933 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 1934 { 1935 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1936 int i; 1937 1938 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 1939 struct iwl_txq *txq = &trans_pcie->txq[i]; 1940 1941 if (i == trans_pcie->cmd_queue) 1942 continue; 1943 1944 spin_lock_bh(&txq->lock); 1945 1946 if (!block && !(WARN_ON_ONCE(!txq->block))) { 1947 txq->block--; 1948 if (!txq->block) { 1949 iwl_write32(trans, HBUS_TARG_WRPTR, 1950 txq->q.write_ptr | (i << 8)); 1951 } 1952 } else if (block) { 1953 txq->block++; 1954 } 1955 1956 spin_unlock_bh(&txq->lock); 1957 } 1958 } 1959 1960 #define IWL_FLUSH_WAIT_MS 2000 1961 1962 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 1963 { 1964 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1965 u32 scd_sram_addr; 1966 u8 buf[16]; 1967 int cnt; 1968 1969 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1970 txq->q.read_ptr, txq->q.write_ptr); 1971 1972 if (trans->cfg->use_tfh) 1973 /* TODO: access new SCD registers and dump them */ 1974 return; 1975 1976 scd_sram_addr = trans_pcie->scd_base_addr + 1977 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 1978 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 1979 1980 iwl_print_hex_error(trans, buf, sizeof(buf)); 1981 1982 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 1983 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 1984 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 1985 1986 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1987 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 1988 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 1989 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 1990 u32 tbl_dw = 1991 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 1992 SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 1993 1994 if (cnt & 0x1) 1995 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 1996 else 1997 tbl_dw = tbl_dw & 0x0000FFFF; 1998 1999 IWL_ERR(trans, 2000 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 2001 cnt, active ? "" : "in", fifo, tbl_dw, 2002 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 2003 (TFD_QUEUE_SIZE_MAX - 1), 2004 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 2005 } 2006 } 2007 2008 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 2009 { 2010 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2011 struct iwl_txq *txq; 2012 struct iwl_queue *q; 2013 int cnt; 2014 unsigned long now = jiffies; 2015 int ret = 0; 2016 2017 /* waiting for all the tx frames complete might take a while */ 2018 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2019 u8 wr_ptr; 2020 2021 if (cnt == trans_pcie->cmd_queue) 2022 continue; 2023 if (!test_bit(cnt, trans_pcie->queue_used)) 2024 continue; 2025 if (!(BIT(cnt) & txq_bm)) 2026 continue; 2027 2028 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 2029 txq = &trans_pcie->txq[cnt]; 2030 q = &txq->q; 2031 wr_ptr = ACCESS_ONCE(q->write_ptr); 2032 2033 while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && 2034 !time_after(jiffies, 2035 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2036 u8 write_ptr = ACCESS_ONCE(q->write_ptr); 2037 2038 if (WARN_ONCE(wr_ptr != write_ptr, 2039 "WR pointer moved while flushing %d -> %d\n", 2040 wr_ptr, write_ptr)) 2041 return -ETIMEDOUT; 2042 usleep_range(1000, 2000); 2043 } 2044 2045 if (q->read_ptr != q->write_ptr) { 2046 IWL_ERR(trans, 2047 "fail to flush all tx fifo queues Q %d\n", cnt); 2048 ret = -ETIMEDOUT; 2049 break; 2050 } 2051 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 2052 } 2053 2054 if (ret) 2055 iwl_trans_pcie_log_scd_error(trans, txq); 2056 2057 return ret; 2058 } 2059 2060 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2061 u32 mask, u32 value) 2062 { 2063 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2064 unsigned long flags; 2065 2066 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2067 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2068 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2069 } 2070 2071 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2072 { 2073 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2074 2075 if (iwlwifi_mod_params.d0i3_disable) 2076 return; 2077 2078 pm_runtime_get(&trans_pcie->pci_dev->dev); 2079 2080 #ifdef CONFIG_PM 2081 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2082 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2083 #endif /* CONFIG_PM */ 2084 } 2085 2086 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2087 { 2088 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2089 2090 if (iwlwifi_mod_params.d0i3_disable) 2091 return; 2092 2093 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2094 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2095 2096 #ifdef CONFIG_PM 2097 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2098 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2099 #endif /* CONFIG_PM */ 2100 } 2101 2102 static const char *get_csr_string(int cmd) 2103 { 2104 #define IWL_CMD(x) case x: return #x 2105 switch (cmd) { 2106 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2107 IWL_CMD(CSR_INT_COALESCING); 2108 IWL_CMD(CSR_INT); 2109 IWL_CMD(CSR_INT_MASK); 2110 IWL_CMD(CSR_FH_INT_STATUS); 2111 IWL_CMD(CSR_GPIO_IN); 2112 IWL_CMD(CSR_RESET); 2113 IWL_CMD(CSR_GP_CNTRL); 2114 IWL_CMD(CSR_HW_REV); 2115 IWL_CMD(CSR_EEPROM_REG); 2116 IWL_CMD(CSR_EEPROM_GP); 2117 IWL_CMD(CSR_OTP_GP_REG); 2118 IWL_CMD(CSR_GIO_REG); 2119 IWL_CMD(CSR_GP_UCODE_REG); 2120 IWL_CMD(CSR_GP_DRIVER_REG); 2121 IWL_CMD(CSR_UCODE_DRV_GP1); 2122 IWL_CMD(CSR_UCODE_DRV_GP2); 2123 IWL_CMD(CSR_LED_REG); 2124 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2125 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2126 IWL_CMD(CSR_ANA_PLL_CFG); 2127 IWL_CMD(CSR_HW_REV_WA_REG); 2128 IWL_CMD(CSR_MONITOR_STATUS_REG); 2129 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2130 default: 2131 return "UNKNOWN"; 2132 } 2133 #undef IWL_CMD 2134 } 2135 2136 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2137 { 2138 int i; 2139 static const u32 csr_tbl[] = { 2140 CSR_HW_IF_CONFIG_REG, 2141 CSR_INT_COALESCING, 2142 CSR_INT, 2143 CSR_INT_MASK, 2144 CSR_FH_INT_STATUS, 2145 CSR_GPIO_IN, 2146 CSR_RESET, 2147 CSR_GP_CNTRL, 2148 CSR_HW_REV, 2149 CSR_EEPROM_REG, 2150 CSR_EEPROM_GP, 2151 CSR_OTP_GP_REG, 2152 CSR_GIO_REG, 2153 CSR_GP_UCODE_REG, 2154 CSR_GP_DRIVER_REG, 2155 CSR_UCODE_DRV_GP1, 2156 CSR_UCODE_DRV_GP2, 2157 CSR_LED_REG, 2158 CSR_DRAM_INT_TBL_REG, 2159 CSR_GIO_CHICKEN_BITS, 2160 CSR_ANA_PLL_CFG, 2161 CSR_MONITOR_STATUS_REG, 2162 CSR_HW_REV_WA_REG, 2163 CSR_DBG_HPET_MEM_REG 2164 }; 2165 IWL_ERR(trans, "CSR values:\n"); 2166 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2167 "CSR_INT_PERIODIC_REG)\n"); 2168 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2169 IWL_ERR(trans, " %25s: 0X%08x\n", 2170 get_csr_string(csr_tbl[i]), 2171 iwl_read32(trans, csr_tbl[i])); 2172 } 2173 } 2174 2175 #ifdef CONFIG_IWLWIFI_DEBUGFS 2176 /* create and remove of files */ 2177 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2178 if (!debugfs_create_file(#name, mode, parent, trans, \ 2179 &iwl_dbgfs_##name##_ops)) \ 2180 goto err; \ 2181 } while (0) 2182 2183 /* file operation */ 2184 #define DEBUGFS_READ_FILE_OPS(name) \ 2185 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2186 .read = iwl_dbgfs_##name##_read, \ 2187 .open = simple_open, \ 2188 .llseek = generic_file_llseek, \ 2189 }; 2190 2191 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2192 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2193 .write = iwl_dbgfs_##name##_write, \ 2194 .open = simple_open, \ 2195 .llseek = generic_file_llseek, \ 2196 }; 2197 2198 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2199 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2200 .write = iwl_dbgfs_##name##_write, \ 2201 .read = iwl_dbgfs_##name##_read, \ 2202 .open = simple_open, \ 2203 .llseek = generic_file_llseek, \ 2204 }; 2205 2206 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2207 char __user *user_buf, 2208 size_t count, loff_t *ppos) 2209 { 2210 struct iwl_trans *trans = file->private_data; 2211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2212 struct iwl_txq *txq; 2213 struct iwl_queue *q; 2214 char *buf; 2215 int pos = 0; 2216 int cnt; 2217 int ret; 2218 size_t bufsz; 2219 2220 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2221 2222 if (!trans_pcie->txq) 2223 return -EAGAIN; 2224 2225 buf = kzalloc(bufsz, GFP_KERNEL); 2226 if (!buf) 2227 return -ENOMEM; 2228 2229 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2230 txq = &trans_pcie->txq[cnt]; 2231 q = &txq->q; 2232 pos += scnprintf(buf + pos, bufsz - pos, 2233 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2234 cnt, q->read_ptr, q->write_ptr, 2235 !!test_bit(cnt, trans_pcie->queue_used), 2236 !!test_bit(cnt, trans_pcie->queue_stopped), 2237 txq->need_update, txq->frozen, 2238 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2239 } 2240 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2241 kfree(buf); 2242 return ret; 2243 } 2244 2245 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2246 char __user *user_buf, 2247 size_t count, loff_t *ppos) 2248 { 2249 struct iwl_trans *trans = file->private_data; 2250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2251 char *buf; 2252 int pos = 0, i, ret; 2253 size_t bufsz = sizeof(buf); 2254 2255 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2256 2257 if (!trans_pcie->rxq) 2258 return -EAGAIN; 2259 2260 buf = kzalloc(bufsz, GFP_KERNEL); 2261 if (!buf) 2262 return -ENOMEM; 2263 2264 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2265 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2266 2267 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2268 i); 2269 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2270 rxq->read); 2271 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2272 rxq->write); 2273 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2274 rxq->write_actual); 2275 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2276 rxq->need_update); 2277 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2278 rxq->free_count); 2279 if (rxq->rb_stts) { 2280 pos += scnprintf(buf + pos, bufsz - pos, 2281 "\tclosed_rb_num: %u\n", 2282 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2283 0x0FFF); 2284 } else { 2285 pos += scnprintf(buf + pos, bufsz - pos, 2286 "\tclosed_rb_num: Not Allocated\n"); 2287 } 2288 } 2289 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2290 kfree(buf); 2291 2292 return ret; 2293 } 2294 2295 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2296 char __user *user_buf, 2297 size_t count, loff_t *ppos) 2298 { 2299 struct iwl_trans *trans = file->private_data; 2300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2301 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2302 2303 int pos = 0; 2304 char *buf; 2305 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2306 ssize_t ret; 2307 2308 buf = kzalloc(bufsz, GFP_KERNEL); 2309 if (!buf) 2310 return -ENOMEM; 2311 2312 pos += scnprintf(buf + pos, bufsz - pos, 2313 "Interrupt Statistics Report:\n"); 2314 2315 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2316 isr_stats->hw); 2317 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2318 isr_stats->sw); 2319 if (isr_stats->sw || isr_stats->hw) { 2320 pos += scnprintf(buf + pos, bufsz - pos, 2321 "\tLast Restarting Code: 0x%X\n", 2322 isr_stats->err_code); 2323 } 2324 #ifdef CONFIG_IWLWIFI_DEBUG 2325 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2326 isr_stats->sch); 2327 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2328 isr_stats->alive); 2329 #endif 2330 pos += scnprintf(buf + pos, bufsz - pos, 2331 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2332 2333 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2334 isr_stats->ctkill); 2335 2336 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2337 isr_stats->wakeup); 2338 2339 pos += scnprintf(buf + pos, bufsz - pos, 2340 "Rx command responses:\t\t %u\n", isr_stats->rx); 2341 2342 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2343 isr_stats->tx); 2344 2345 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2346 isr_stats->unhandled); 2347 2348 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2349 kfree(buf); 2350 return ret; 2351 } 2352 2353 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2354 const char __user *user_buf, 2355 size_t count, loff_t *ppos) 2356 { 2357 struct iwl_trans *trans = file->private_data; 2358 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2359 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2360 2361 char buf[8]; 2362 int buf_size; 2363 u32 reset_flag; 2364 2365 memset(buf, 0, sizeof(buf)); 2366 buf_size = min(count, sizeof(buf) - 1); 2367 if (copy_from_user(buf, user_buf, buf_size)) 2368 return -EFAULT; 2369 if (sscanf(buf, "%x", &reset_flag) != 1) 2370 return -EFAULT; 2371 if (reset_flag == 0) 2372 memset(isr_stats, 0, sizeof(*isr_stats)); 2373 2374 return count; 2375 } 2376 2377 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2378 const char __user *user_buf, 2379 size_t count, loff_t *ppos) 2380 { 2381 struct iwl_trans *trans = file->private_data; 2382 char buf[8]; 2383 int buf_size; 2384 int csr; 2385 2386 memset(buf, 0, sizeof(buf)); 2387 buf_size = min(count, sizeof(buf) - 1); 2388 if (copy_from_user(buf, user_buf, buf_size)) 2389 return -EFAULT; 2390 if (sscanf(buf, "%d", &csr) != 1) 2391 return -EFAULT; 2392 2393 iwl_pcie_dump_csr(trans); 2394 2395 return count; 2396 } 2397 2398 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2399 char __user *user_buf, 2400 size_t count, loff_t *ppos) 2401 { 2402 struct iwl_trans *trans = file->private_data; 2403 char *buf = NULL; 2404 ssize_t ret; 2405 2406 ret = iwl_dump_fh(trans, &buf); 2407 if (ret < 0) 2408 return ret; 2409 if (!buf) 2410 return -EINVAL; 2411 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2412 kfree(buf); 2413 return ret; 2414 } 2415 2416 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2417 DEBUGFS_READ_FILE_OPS(fh_reg); 2418 DEBUGFS_READ_FILE_OPS(rx_queue); 2419 DEBUGFS_READ_FILE_OPS(tx_queue); 2420 DEBUGFS_WRITE_FILE_OPS(csr); 2421 2422 /* Create the debugfs files and directories */ 2423 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2424 { 2425 struct dentry *dir = trans->dbgfs_dir; 2426 2427 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2428 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2429 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2430 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2431 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2432 return 0; 2433 2434 err: 2435 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2436 return -ENOMEM; 2437 } 2438 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2439 2440 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, 2441 struct iwl_tfd *tfd) 2442 { 2443 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2444 u32 cmdlen = 0; 2445 int i; 2446 2447 for (i = 0; i < trans_pcie->max_tbs; i++) 2448 cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); 2449 2450 return cmdlen; 2451 } 2452 2453 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2454 struct iwl_fw_error_dump_data **data, 2455 int allocated_rb_nums) 2456 { 2457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2458 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2459 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2460 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2461 u32 i, r, j, rb_len = 0; 2462 2463 spin_lock(&rxq->lock); 2464 2465 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2466 2467 for (i = rxq->read, j = 0; 2468 i != r && j < allocated_rb_nums; 2469 i = (i + 1) & RX_QUEUE_MASK, j++) { 2470 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2471 struct iwl_fw_error_dump_rb *rb; 2472 2473 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2474 DMA_FROM_DEVICE); 2475 2476 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2477 2478 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2479 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2480 rb = (void *)(*data)->data; 2481 rb->index = cpu_to_le32(i); 2482 memcpy(rb->data, page_address(rxb->page), max_len); 2483 /* remap the page for the free benefit */ 2484 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2485 max_len, 2486 DMA_FROM_DEVICE); 2487 2488 *data = iwl_fw_error_next_data(*data); 2489 } 2490 2491 spin_unlock(&rxq->lock); 2492 2493 return rb_len; 2494 } 2495 #define IWL_CSR_TO_DUMP (0x250) 2496 2497 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2498 struct iwl_fw_error_dump_data **data) 2499 { 2500 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2501 __le32 *val; 2502 int i; 2503 2504 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2505 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2506 val = (void *)(*data)->data; 2507 2508 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2509 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2510 2511 *data = iwl_fw_error_next_data(*data); 2512 2513 return csr_len; 2514 } 2515 2516 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2517 struct iwl_fw_error_dump_data **data) 2518 { 2519 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2520 unsigned long flags; 2521 __le32 *val; 2522 int i; 2523 2524 if (!iwl_trans_grab_nic_access(trans, &flags)) 2525 return 0; 2526 2527 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2528 (*data)->len = cpu_to_le32(fh_regs_len); 2529 val = (void *)(*data)->data; 2530 2531 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2532 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2533 2534 iwl_trans_release_nic_access(trans, &flags); 2535 2536 *data = iwl_fw_error_next_data(*data); 2537 2538 return sizeof(**data) + fh_regs_len; 2539 } 2540 2541 static u32 2542 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2543 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2544 u32 monitor_len) 2545 { 2546 u32 buf_size_in_dwords = (monitor_len >> 2); 2547 u32 *buffer = (u32 *)fw_mon_data->data; 2548 unsigned long flags; 2549 u32 i; 2550 2551 if (!iwl_trans_grab_nic_access(trans, &flags)) 2552 return 0; 2553 2554 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2555 for (i = 0; i < buf_size_in_dwords; i++) 2556 buffer[i] = iwl_read_prph_no_grab(trans, 2557 MON_DMARB_RD_DATA_ADDR); 2558 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2559 2560 iwl_trans_release_nic_access(trans, &flags); 2561 2562 return monitor_len; 2563 } 2564 2565 static u32 2566 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2567 struct iwl_fw_error_dump_data **data, 2568 u32 monitor_len) 2569 { 2570 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2571 u32 len = 0; 2572 2573 if ((trans_pcie->fw_mon_page && 2574 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2575 trans->dbg_dest_tlv) { 2576 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2577 u32 base, write_ptr, wrap_cnt; 2578 2579 /* If there was a dest TLV - use the values from there */ 2580 if (trans->dbg_dest_tlv) { 2581 write_ptr = 2582 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2583 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2584 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2585 } else { 2586 base = MON_BUFF_BASE_ADDR; 2587 write_ptr = MON_BUFF_WRPTR; 2588 wrap_cnt = MON_BUFF_CYCLE_CNT; 2589 } 2590 2591 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2592 fw_mon_data = (void *)(*data)->data; 2593 fw_mon_data->fw_mon_wr_ptr = 2594 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2595 fw_mon_data->fw_mon_cycle_cnt = 2596 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2597 fw_mon_data->fw_mon_base_ptr = 2598 cpu_to_le32(iwl_read_prph(trans, base)); 2599 2600 len += sizeof(**data) + sizeof(*fw_mon_data); 2601 if (trans_pcie->fw_mon_page) { 2602 /* 2603 * The firmware is now asserted, it won't write anything 2604 * to the buffer. CPU can take ownership to fetch the 2605 * data. The buffer will be handed back to the device 2606 * before the firmware will be restarted. 2607 */ 2608 dma_sync_single_for_cpu(trans->dev, 2609 trans_pcie->fw_mon_phys, 2610 trans_pcie->fw_mon_size, 2611 DMA_FROM_DEVICE); 2612 memcpy(fw_mon_data->data, 2613 page_address(trans_pcie->fw_mon_page), 2614 trans_pcie->fw_mon_size); 2615 2616 monitor_len = trans_pcie->fw_mon_size; 2617 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2618 /* 2619 * Update pointers to reflect actual values after 2620 * shifting 2621 */ 2622 base = iwl_read_prph(trans, base) << 2623 trans->dbg_dest_tlv->base_shift; 2624 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2625 monitor_len / sizeof(u32)); 2626 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2627 monitor_len = 2628 iwl_trans_pci_dump_marbh_monitor(trans, 2629 fw_mon_data, 2630 monitor_len); 2631 } else { 2632 /* Didn't match anything - output no monitor data */ 2633 monitor_len = 0; 2634 } 2635 2636 len += monitor_len; 2637 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2638 } 2639 2640 return len; 2641 } 2642 2643 static struct iwl_trans_dump_data 2644 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2645 const struct iwl_fw_dbg_trigger_tlv *trigger) 2646 { 2647 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2648 struct iwl_fw_error_dump_data *data; 2649 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2650 struct iwl_fw_error_dump_txcmd *txcmd; 2651 struct iwl_trans_dump_data *dump_data; 2652 u32 len, num_rbs; 2653 u32 monitor_len; 2654 int i, ptr; 2655 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2656 !trans->cfg->mq_rx_supported; 2657 2658 /* transport dump header */ 2659 len = sizeof(*dump_data); 2660 2661 /* host commands */ 2662 len += sizeof(*data) + 2663 cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2664 2665 /* FW monitor */ 2666 if (trans_pcie->fw_mon_page) { 2667 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2668 trans_pcie->fw_mon_size; 2669 monitor_len = trans_pcie->fw_mon_size; 2670 } else if (trans->dbg_dest_tlv) { 2671 u32 base, end; 2672 2673 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2674 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2675 2676 base = iwl_read_prph(trans, base) << 2677 trans->dbg_dest_tlv->base_shift; 2678 end = iwl_read_prph(trans, end) << 2679 trans->dbg_dest_tlv->end_shift; 2680 2681 /* Make "end" point to the actual end */ 2682 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2683 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2684 end += (1 << trans->dbg_dest_tlv->end_shift); 2685 monitor_len = end - base; 2686 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2687 monitor_len; 2688 } else { 2689 monitor_len = 0; 2690 } 2691 2692 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2693 dump_data = vzalloc(len); 2694 if (!dump_data) 2695 return NULL; 2696 2697 data = (void *)dump_data->data; 2698 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2699 dump_data->len = len; 2700 2701 return dump_data; 2702 } 2703 2704 /* CSR registers */ 2705 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2706 2707 /* FH registers */ 2708 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2709 2710 if (dump_rbs) { 2711 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2712 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2713 /* RBs */ 2714 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2715 & 0x0FFF; 2716 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2717 len += num_rbs * (sizeof(*data) + 2718 sizeof(struct iwl_fw_error_dump_rb) + 2719 (PAGE_SIZE << trans_pcie->rx_page_order)); 2720 } 2721 2722 dump_data = vzalloc(len); 2723 if (!dump_data) 2724 return NULL; 2725 2726 len = 0; 2727 data = (void *)dump_data->data; 2728 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2729 txcmd = (void *)data->data; 2730 spin_lock_bh(&cmdq->lock); 2731 ptr = cmdq->q.write_ptr; 2732 for (i = 0; i < cmdq->q.n_window; i++) { 2733 u8 idx = get_cmd_index(&cmdq->q, ptr); 2734 u32 caplen, cmdlen; 2735 2736 cmdlen = iwl_trans_pcie_get_cmdlen(trans, &cmdq->tfds[ptr]); 2737 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2738 2739 if (cmdlen) { 2740 len += sizeof(*txcmd) + caplen; 2741 txcmd->cmdlen = cpu_to_le32(cmdlen); 2742 txcmd->caplen = cpu_to_le32(caplen); 2743 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2744 txcmd = (void *)((u8 *)txcmd->data + caplen); 2745 } 2746 2747 ptr = iwl_queue_dec_wrap(ptr); 2748 } 2749 spin_unlock_bh(&cmdq->lock); 2750 2751 data->len = cpu_to_le32(len); 2752 len += sizeof(*data); 2753 data = iwl_fw_error_next_data(data); 2754 2755 len += iwl_trans_pcie_dump_csr(trans, &data); 2756 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2757 if (dump_rbs) 2758 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2759 2760 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2761 2762 dump_data->len = len; 2763 2764 return dump_data; 2765 } 2766 2767 #ifdef CONFIG_PM_SLEEP 2768 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2769 { 2770 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2771 return iwl_pci_fw_enter_d0i3(trans); 2772 2773 return 0; 2774 } 2775 2776 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2777 { 2778 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2779 iwl_pci_fw_exit_d0i3(trans); 2780 } 2781 #endif /* CONFIG_PM_SLEEP */ 2782 2783 static const struct iwl_trans_ops trans_ops_pcie = { 2784 .start_hw = iwl_trans_pcie_start_hw, 2785 .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2786 .fw_alive = iwl_trans_pcie_fw_alive, 2787 .start_fw = iwl_trans_pcie_start_fw, 2788 .stop_device = iwl_trans_pcie_stop_device, 2789 2790 .d3_suspend = iwl_trans_pcie_d3_suspend, 2791 .d3_resume = iwl_trans_pcie_d3_resume, 2792 2793 #ifdef CONFIG_PM_SLEEP 2794 .suspend = iwl_trans_pcie_suspend, 2795 .resume = iwl_trans_pcie_resume, 2796 #endif /* CONFIG_PM_SLEEP */ 2797 2798 .send_cmd = iwl_trans_pcie_send_hcmd, 2799 2800 .tx = iwl_trans_pcie_tx, 2801 .reclaim = iwl_trans_pcie_reclaim, 2802 2803 .txq_disable = iwl_trans_pcie_txq_disable, 2804 .txq_enable = iwl_trans_pcie_txq_enable, 2805 2806 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table, 2807 2808 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2809 2810 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2811 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2812 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2813 2814 .write8 = iwl_trans_pcie_write8, 2815 .write32 = iwl_trans_pcie_write32, 2816 .read32 = iwl_trans_pcie_read32, 2817 .read_prph = iwl_trans_pcie_read_prph, 2818 .write_prph = iwl_trans_pcie_write_prph, 2819 .read_mem = iwl_trans_pcie_read_mem, 2820 .write_mem = iwl_trans_pcie_write_mem, 2821 .configure = iwl_trans_pcie_configure, 2822 .set_pmi = iwl_trans_pcie_set_pmi, 2823 .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2824 .release_nic_access = iwl_trans_pcie_release_nic_access, 2825 .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2826 2827 .ref = iwl_trans_pcie_ref, 2828 .unref = iwl_trans_pcie_unref, 2829 2830 .dump_data = iwl_trans_pcie_dump_data, 2831 }; 2832 2833 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2834 const struct pci_device_id *ent, 2835 const struct iwl_cfg *cfg) 2836 { 2837 struct iwl_trans_pcie *trans_pcie; 2838 struct iwl_trans *trans; 2839 int ret, addr_size; 2840 2841 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2842 &pdev->dev, cfg, &trans_ops_pcie, 0); 2843 if (!trans) 2844 return ERR_PTR(-ENOMEM); 2845 2846 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2847 2848 trans_pcie->trans = trans; 2849 spin_lock_init(&trans_pcie->irq_lock); 2850 spin_lock_init(&trans_pcie->reg_lock); 2851 mutex_init(&trans_pcie->mutex); 2852 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 2853 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 2854 if (!trans_pcie->tso_hdr_page) { 2855 ret = -ENOMEM; 2856 goto out_no_pci; 2857 } 2858 2859 ret = pci_enable_device(pdev); 2860 if (ret) 2861 goto out_no_pci; 2862 2863 if (!cfg->base_params->pcie_l1_allowed) { 2864 /* 2865 * W/A - seems to solve weird behavior. We need to remove this 2866 * if we don't want to stay in L1 all the time. This wastes a 2867 * lot of power. 2868 */ 2869 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2870 PCIE_LINK_STATE_L1 | 2871 PCIE_LINK_STATE_CLKPM); 2872 } 2873 2874 if (cfg->mq_rx_supported) 2875 addr_size = 64; 2876 else 2877 addr_size = 36; 2878 2879 if (cfg->use_tfh) 2880 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 2881 else 2882 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 2883 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 2884 2885 pci_set_master(pdev); 2886 2887 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2888 if (!ret) 2889 ret = pci_set_consistent_dma_mask(pdev, 2890 DMA_BIT_MASK(addr_size)); 2891 if (ret) { 2892 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2893 if (!ret) 2894 ret = pci_set_consistent_dma_mask(pdev, 2895 DMA_BIT_MASK(32)); 2896 /* both attempts failed: */ 2897 if (ret) { 2898 dev_err(&pdev->dev, "No suitable DMA available\n"); 2899 goto out_pci_disable_device; 2900 } 2901 } 2902 2903 ret = pci_request_regions(pdev, DRV_NAME); 2904 if (ret) { 2905 dev_err(&pdev->dev, "pci_request_regions failed\n"); 2906 goto out_pci_disable_device; 2907 } 2908 2909 trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); 2910 if (!trans_pcie->hw_base) { 2911 dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); 2912 ret = -ENODEV; 2913 goto out_pci_release_regions; 2914 } 2915 2916 /* We disable the RETRY_TIMEOUT register (0x41) to keep 2917 * PCI Tx retries from interfering with C3 CPU state */ 2918 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 2919 2920 trans->dev = &pdev->dev; 2921 trans_pcie->pci_dev = pdev; 2922 iwl_disable_interrupts(trans); 2923 2924 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 2925 /* 2926 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 2927 * changed, and now the revision step also includes bit 0-1 (no more 2928 * "dash" value). To keep hw_rev backwards compatible - we'll store it 2929 * in the old format. 2930 */ 2931 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 2932 unsigned long flags; 2933 2934 trans->hw_rev = (trans->hw_rev & 0xfff0) | 2935 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 2936 2937 ret = iwl_pcie_prepare_card_hw(trans); 2938 if (ret) { 2939 IWL_WARN(trans, "Exit HW not ready\n"); 2940 goto out_pci_disable_msi; 2941 } 2942 2943 /* 2944 * in-order to recognize C step driver should read chip version 2945 * id located at the AUX bus MISC address space. 2946 */ 2947 iwl_set_bit(trans, CSR_GP_CNTRL, 2948 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 2949 udelay(2); 2950 2951 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2952 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2953 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2954 25000); 2955 if (ret < 0) { 2956 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 2957 goto out_pci_disable_msi; 2958 } 2959 2960 if (iwl_trans_grab_nic_access(trans, &flags)) { 2961 u32 hw_step; 2962 2963 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 2964 hw_step |= ENABLE_WFPM; 2965 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 2966 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 2967 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 2968 if (hw_step == 0x3) 2969 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 2970 (SILICON_C_STEP << 2); 2971 iwl_trans_release_nic_access(trans, &flags); 2972 } 2973 } 2974 2975 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 2976 2977 iwl_pcie_set_interrupt_capa(pdev, trans); 2978 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 2979 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 2980 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 2981 2982 /* Initialize the wait queue for commands */ 2983 init_waitqueue_head(&trans_pcie->wait_command_queue); 2984 2985 init_waitqueue_head(&trans_pcie->d0i3_waitq); 2986 2987 if (trans_pcie->msix_enabled) { 2988 if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 2989 goto out_pci_release_regions; 2990 } else { 2991 ret = iwl_pcie_alloc_ict(trans); 2992 if (ret) 2993 goto out_pci_disable_msi; 2994 2995 ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, 2996 iwl_pcie_irq_handler, 2997 IRQF_SHARED, DRV_NAME, trans); 2998 if (ret) { 2999 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3000 goto out_free_ict; 3001 } 3002 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3003 } 3004 3005 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3006 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3007 #else 3008 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3009 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3010 3011 return trans; 3012 3013 out_free_ict: 3014 iwl_pcie_free_ict(trans); 3015 out_pci_disable_msi: 3016 pci_disable_msi(pdev); 3017 out_pci_release_regions: 3018 pci_release_regions(pdev); 3019 out_pci_disable_device: 3020 pci_disable_device(pdev); 3021 out_no_pci: 3022 free_percpu(trans_pcie->tso_hdr_page); 3023 iwl_trans_free(trans); 3024 return ERR_PTR(ret); 3025 } 3026