1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "fw/error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92 { 93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94 95 if (!trans_pcie->fw_mon_page) 96 return; 97 98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100 __free_pages(trans_pcie->fw_mon_page, 101 get_order(trans_pcie->fw_mon_size)); 102 trans_pcie->fw_mon_page = NULL; 103 trans_pcie->fw_mon_phys = 0; 104 trans_pcie->fw_mon_size = 0; 105 } 106 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108 { 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110 struct page *page = NULL; 111 dma_addr_t phys; 112 u32 size = 0; 113 u8 power; 114 115 if (!max_power) { 116 /* default max_power is maximum */ 117 max_power = 26; 118 } else { 119 max_power += 11; 120 } 121 122 if (WARN(max_power > 26, 123 "External buffer size for monitor is too big %d, check the FW TLV\n", 124 max_power)) 125 return; 126 127 if (trans_pcie->fw_mon_page) { 128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129 trans_pcie->fw_mon_size, 130 DMA_FROM_DEVICE); 131 return; 132 } 133 134 phys = 0; 135 for (power = max_power; power >= 11; power--) { 136 int order; 137 138 size = BIT(power); 139 order = get_order(size); 140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141 order); 142 if (!page) 143 continue; 144 145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146 DMA_FROM_DEVICE); 147 if (dma_mapping_error(trans->dev, phys)) { 148 __free_pages(page, order); 149 page = NULL; 150 continue; 151 } 152 IWL_INFO(trans, 153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154 size, order); 155 break; 156 } 157 158 if (WARN_ON_ONCE(!page)) 159 return; 160 161 if (power != max_power) 162 IWL_ERR(trans, 163 "Sorry - debug buffer is only %luK while you requested %luK\n", 164 (unsigned long)BIT(power - 10), 165 (unsigned long)BIT(max_power - 10)); 166 167 trans_pcie->fw_mon_page = page; 168 trans_pcie->fw_mon_phys = phys; 169 trans_pcie->fw_mon_size = size; 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->cfg->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212 * Check if BIOS (or OS) enabled L1-ASPM on this device. 213 * If so (likely), disable L0S, so device moves directly L0->L1; 214 * costs negligible amount of power savings. 215 * If not (unlikely), enable L0S, so there is at least some 216 * power savings, even without L1. 217 */ 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221 else 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224 225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229 trans->ltr_enabled ? "En" : "Dis"); 230 } 231 232 /* 233 * Start up NIC's basic functionality after it has been reset 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235 * NOTE: This does not load uCode nor start the embedded processor 236 */ 237 static int iwl_pcie_apm_init(struct iwl_trans *trans) 238 { 239 int ret; 240 241 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 242 243 /* 244 * Use "set_bit" below rather than "write", to preserve any hardware 245 * bits already set by default after reset. 246 */ 247 248 /* Disable L0S exit timer (platform NMI Work/Around) */ 249 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 250 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 251 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 252 253 /* 254 * Disable L0s without affecting L1; 255 * don't wait for ICH L0s (ICH bug W/A) 256 */ 257 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 258 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 259 260 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 261 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 262 263 /* 264 * Enable HAP INTA (interrupt from management bus) to 265 * wake device's PCI Express link L1a -> L0s 266 */ 267 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 268 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 269 270 iwl_pcie_apm_config(trans); 271 272 /* Configure analog phase-lock-loop before activating to D0A */ 273 if (trans->cfg->base_params->pll_cfg) 274 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 275 276 /* 277 * Set "initialization complete" bit to move adapter from 278 * D0U* --> D0A* (powered-up active) state. 279 */ 280 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 281 282 /* 283 * Wait for clock stabilization; once stabilized, access to 284 * device-internal resources is supported, e.g. iwl_write_prph() 285 * and accesses to uCode SRAM. 286 */ 287 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 289 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 290 if (ret < 0) { 291 IWL_ERR(trans, "Failed to init the card\n"); 292 return ret; 293 } 294 295 if (trans->cfg->host_interrupt_operation_mode) { 296 /* 297 * This is a bit of an abuse - This is needed for 7260 / 3160 298 * only check host_interrupt_operation_mode even if this is 299 * not related to host_interrupt_operation_mode. 300 * 301 * Enable the oscillator to count wake up time for L1 exit. This 302 * consumes slightly more power (100uA) - but allows to be sure 303 * that we wake up from L1 on time. 304 * 305 * This looks weird: read twice the same register, discard the 306 * value, set a bit, and yet again, read that same register 307 * just to discard the value. But that's the way the hardware 308 * seems to like it. 309 */ 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_read_prph(trans, OSC_CLK); 312 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 313 iwl_read_prph(trans, OSC_CLK); 314 iwl_read_prph(trans, OSC_CLK); 315 } 316 317 /* 318 * Enable DMA clock and wait for it to stabilize. 319 * 320 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 321 * bits do not disable clocks. This preserves any hardware 322 * bits already set by default in "CLK_CTRL_REG" after reset. 323 */ 324 if (!trans->cfg->apmg_not_supported) { 325 iwl_write_prph(trans, APMG_CLK_EN_REG, 326 APMG_CLK_VAL_DMA_CLK_RQT); 327 udelay(20); 328 329 /* Disable L1-Active */ 330 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 331 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 332 333 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 334 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 335 APMG_RTC_INT_STT_RFKILL); 336 } 337 338 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 339 340 return 0; 341 } 342 343 /* 344 * Enable LP XTAL to avoid HW bug where device may consume much power if 345 * FW is not loaded after device reset. LP XTAL is disabled by default 346 * after device HW reset. Do it only if XTAL is fed by internal source. 347 * Configure device's "persistence" mode to avoid resetting XTAL again when 348 * SHRD_HW_RST occurs in S3. 349 */ 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351 { 352 int ret; 353 u32 apmg_gp1_reg; 354 u32 apmg_xtal_cfg_reg; 355 u32 dl_cfg_reg; 356 357 /* Force XTAL ON */ 358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360 361 iwl_pcie_sw_reset(trans); 362 363 /* 364 * Set "initialization complete" bit to move adapter from 365 * D0U* --> D0A* (powered-up active) state. 366 */ 367 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 368 369 /* 370 * Wait for clock stabilization; once stabilized, access to 371 * device-internal resources is possible. 372 */ 373 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 374 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 375 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 376 25000); 377 if (WARN_ON(ret < 0)) { 378 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 379 /* Release XTAL ON request */ 380 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 381 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 382 return; 383 } 384 385 /* 386 * Clear "disable persistence" to avoid LP XTAL resetting when 387 * SHRD_HW_RST is applied in S3. 388 */ 389 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 390 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 391 392 /* 393 * Force APMG XTAL to be active to prevent its disabling by HW 394 * caused by APMG idle state. 395 */ 396 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 397 SHR_APMG_XTAL_CFG_REG); 398 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 399 apmg_xtal_cfg_reg | 400 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 401 402 iwl_pcie_sw_reset(trans); 403 404 /* Enable LP XTAL by indirect access through CSR */ 405 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 406 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 407 SHR_APMG_GP1_WF_XTAL_LP_EN | 408 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 409 410 /* Clear delay line clock power up */ 411 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 412 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 413 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 414 415 /* 416 * Enable persistence mode to avoid LP XTAL resetting when 417 * SHRD_HW_RST is applied in S3. 418 */ 419 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 420 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 421 422 /* 423 * Clear "initialization complete" bit to move adapter from 424 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 425 */ 426 iwl_clear_bit(trans, CSR_GP_CNTRL, 427 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 428 429 /* Activates XTAL resources monitor */ 430 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 431 CSR_MONITOR_XTAL_RESOURCES); 432 433 /* Release XTAL ON request */ 434 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 435 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 436 udelay(10); 437 438 /* Release APMG XTAL */ 439 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 440 apmg_xtal_cfg_reg & 441 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 442 } 443 444 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 445 { 446 int ret; 447 448 /* stop device's busmaster DMA activity */ 449 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 450 451 ret = iwl_poll_bit(trans, CSR_RESET, 452 CSR_RESET_REG_FLAG_MASTER_DISABLED, 453 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 454 if (ret < 0) 455 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 456 457 IWL_DEBUG_INFO(trans, "stop master\n"); 458 } 459 460 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 461 { 462 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 463 464 if (op_mode_leave) { 465 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 466 iwl_pcie_apm_init(trans); 467 468 /* inform ME that we are leaving */ 469 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 470 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 471 APMG_PCIDEV_STT_VAL_WAKE_ME); 472 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 473 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 474 CSR_RESET_LINK_PWR_MGMT_DISABLED); 475 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 476 CSR_HW_IF_CONFIG_REG_PREPARE | 477 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 478 mdelay(1); 479 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 480 CSR_RESET_LINK_PWR_MGMT_DISABLED); 481 } 482 mdelay(5); 483 } 484 485 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 486 487 /* Stop device's DMA activity */ 488 iwl_pcie_apm_stop_master(trans); 489 490 if (trans->cfg->lp_xtal_workaround) { 491 iwl_pcie_apm_lp_xtal_enable(trans); 492 return; 493 } 494 495 iwl_pcie_sw_reset(trans); 496 497 /* 498 * Clear "initialization complete" bit to move adapter from 499 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 500 */ 501 iwl_clear_bit(trans, CSR_GP_CNTRL, 502 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 503 } 504 505 static int iwl_pcie_nic_init(struct iwl_trans *trans) 506 { 507 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 508 int ret; 509 510 /* nic_init */ 511 spin_lock(&trans_pcie->irq_lock); 512 ret = iwl_pcie_apm_init(trans); 513 spin_unlock(&trans_pcie->irq_lock); 514 515 if (ret) 516 return ret; 517 518 iwl_pcie_set_pwr(trans, false); 519 520 iwl_op_mode_nic_config(trans->op_mode); 521 522 /* Allocate the RX queue, or reset if it is already allocated */ 523 iwl_pcie_rx_init(trans); 524 525 /* Allocate or reset and init all Tx and Command queues */ 526 if (iwl_pcie_tx_init(trans)) 527 return -ENOMEM; 528 529 if (trans->cfg->base_params->shadow_reg_enable) { 530 /* enable shadow regs in HW */ 531 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 532 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 533 } 534 535 return 0; 536 } 537 538 #define HW_READY_TIMEOUT (50) 539 540 /* Note: returns poll_bit return value, which is >= 0 if success */ 541 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 542 { 543 int ret; 544 545 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 546 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 547 548 /* See if we got it */ 549 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 550 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 551 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 552 HW_READY_TIMEOUT); 553 554 if (ret >= 0) 555 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 556 557 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 558 return ret; 559 } 560 561 /* Note: returns standard 0/-ERROR code */ 562 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 563 { 564 int ret; 565 int t = 0; 566 int iter; 567 568 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 569 570 ret = iwl_pcie_set_hw_ready(trans); 571 /* If the card is ready, exit 0 */ 572 if (ret >= 0) 573 return 0; 574 575 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 576 CSR_RESET_LINK_PWR_MGMT_DISABLED); 577 usleep_range(1000, 2000); 578 579 for (iter = 0; iter < 10; iter++) { 580 /* If HW is not ready, prepare the conditions to check again */ 581 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 582 CSR_HW_IF_CONFIG_REG_PREPARE); 583 584 do { 585 ret = iwl_pcie_set_hw_ready(trans); 586 if (ret >= 0) 587 return 0; 588 589 usleep_range(200, 1000); 590 t += 200; 591 } while (t < 150000); 592 msleep(25); 593 } 594 595 IWL_ERR(trans, "Couldn't prepare the card\n"); 596 597 return ret; 598 } 599 600 /* 601 * ucode 602 */ 603 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 604 u32 dst_addr, dma_addr_t phy_addr, 605 u32 byte_cnt) 606 { 607 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 608 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 609 610 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 611 dst_addr); 612 613 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 614 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 615 616 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 617 (iwl_get_dma_hi_addr(phy_addr) 618 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 619 620 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 621 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 622 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 623 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 624 625 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 626 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 627 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 628 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 629 } 630 631 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 632 u32 dst_addr, dma_addr_t phy_addr, 633 u32 byte_cnt) 634 { 635 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 636 unsigned long flags; 637 int ret; 638 639 trans_pcie->ucode_write_complete = false; 640 641 if (!iwl_trans_grab_nic_access(trans, &flags)) 642 return -EIO; 643 644 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 645 byte_cnt); 646 iwl_trans_release_nic_access(trans, &flags); 647 648 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 649 trans_pcie->ucode_write_complete, 5 * HZ); 650 if (!ret) { 651 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 652 return -ETIMEDOUT; 653 } 654 655 return 0; 656 } 657 658 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 659 const struct fw_desc *section) 660 { 661 u8 *v_addr; 662 dma_addr_t p_addr; 663 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 664 int ret = 0; 665 666 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 667 section_num); 668 669 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 670 GFP_KERNEL | __GFP_NOWARN); 671 if (!v_addr) { 672 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 673 chunk_sz = PAGE_SIZE; 674 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 675 &p_addr, GFP_KERNEL); 676 if (!v_addr) 677 return -ENOMEM; 678 } 679 680 for (offset = 0; offset < section->len; offset += chunk_sz) { 681 u32 copy_size, dst_addr; 682 bool extended_addr = false; 683 684 copy_size = min_t(u32, chunk_sz, section->len - offset); 685 dst_addr = section->offset + offset; 686 687 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 688 dst_addr <= IWL_FW_MEM_EXTENDED_END) 689 extended_addr = true; 690 691 if (extended_addr) 692 iwl_set_bits_prph(trans, LMPM_CHICK, 693 LMPM_CHICK_EXTENDED_ADDR_SPACE); 694 695 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 696 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 697 copy_size); 698 699 if (extended_addr) 700 iwl_clear_bits_prph(trans, LMPM_CHICK, 701 LMPM_CHICK_EXTENDED_ADDR_SPACE); 702 703 if (ret) { 704 IWL_ERR(trans, 705 "Could not load the [%d] uCode section\n", 706 section_num); 707 break; 708 } 709 } 710 711 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 712 return ret; 713 } 714 715 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 716 const struct fw_img *image, 717 int cpu, 718 int *first_ucode_section) 719 { 720 int shift_param; 721 int i, ret = 0, sec_num = 0x1; 722 u32 val, last_read_idx = 0; 723 724 if (cpu == 1) { 725 shift_param = 0; 726 *first_ucode_section = 0; 727 } else { 728 shift_param = 16; 729 (*first_ucode_section)++; 730 } 731 732 for (i = *first_ucode_section; i < image->num_sec; i++) { 733 last_read_idx = i; 734 735 /* 736 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 737 * CPU1 to CPU2. 738 * PAGING_SEPARATOR_SECTION delimiter - separate between 739 * CPU2 non paged to CPU2 paging sec. 740 */ 741 if (!image->sec[i].data || 742 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 743 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 744 IWL_DEBUG_FW(trans, 745 "Break since Data not valid or Empty section, sec = %d\n", 746 i); 747 break; 748 } 749 750 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 751 if (ret) 752 return ret; 753 754 /* Notify ucode of loaded section number and status */ 755 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 756 val = val | (sec_num << shift_param); 757 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 758 759 sec_num = (sec_num << 1) | 0x1; 760 } 761 762 *first_ucode_section = last_read_idx; 763 764 iwl_enable_interrupts(trans); 765 766 if (trans->cfg->use_tfh) { 767 if (cpu == 1) 768 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 769 0xFFFF); 770 else 771 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 772 0xFFFFFFFF); 773 } else { 774 if (cpu == 1) 775 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 776 0xFFFF); 777 else 778 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 779 0xFFFFFFFF); 780 } 781 782 return 0; 783 } 784 785 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 786 const struct fw_img *image, 787 int cpu, 788 int *first_ucode_section) 789 { 790 int i, ret = 0; 791 u32 last_read_idx = 0; 792 793 if (cpu == 1) 794 *first_ucode_section = 0; 795 else 796 (*first_ucode_section)++; 797 798 for (i = *first_ucode_section; i < image->num_sec; i++) { 799 last_read_idx = i; 800 801 /* 802 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 803 * CPU1 to CPU2. 804 * PAGING_SEPARATOR_SECTION delimiter - separate between 805 * CPU2 non paged to CPU2 paging sec. 806 */ 807 if (!image->sec[i].data || 808 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 809 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 810 IWL_DEBUG_FW(trans, 811 "Break since Data not valid or Empty section, sec = %d\n", 812 i); 813 break; 814 } 815 816 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 817 if (ret) 818 return ret; 819 } 820 821 *first_ucode_section = last_read_idx; 822 823 return 0; 824 } 825 826 void iwl_pcie_apply_destination(struct iwl_trans *trans) 827 { 828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 829 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 830 int i; 831 832 if (dest->version) 833 IWL_ERR(trans, 834 "DBG DEST version is %d - expect issues\n", 835 dest->version); 836 837 IWL_INFO(trans, "Applying debug destination %s\n", 838 get_fw_dbg_mode_string(dest->monitor_mode)); 839 840 if (dest->monitor_mode == EXTERNAL_MODE) 841 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 842 else 843 IWL_WARN(trans, "PCI should have external buffer debug\n"); 844 845 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 846 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 847 u32 val = le32_to_cpu(dest->reg_ops[i].val); 848 849 switch (dest->reg_ops[i].op) { 850 case CSR_ASSIGN: 851 iwl_write32(trans, addr, val); 852 break; 853 case CSR_SETBIT: 854 iwl_set_bit(trans, addr, BIT(val)); 855 break; 856 case CSR_CLEARBIT: 857 iwl_clear_bit(trans, addr, BIT(val)); 858 break; 859 case PRPH_ASSIGN: 860 iwl_write_prph(trans, addr, val); 861 break; 862 case PRPH_SETBIT: 863 iwl_set_bits_prph(trans, addr, BIT(val)); 864 break; 865 case PRPH_CLEARBIT: 866 iwl_clear_bits_prph(trans, addr, BIT(val)); 867 break; 868 case PRPH_BLOCKBIT: 869 if (iwl_read_prph(trans, addr) & BIT(val)) { 870 IWL_ERR(trans, 871 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 872 val, addr); 873 goto monitor; 874 } 875 break; 876 default: 877 IWL_ERR(trans, "FW debug - unknown OP %d\n", 878 dest->reg_ops[i].op); 879 break; 880 } 881 } 882 883 monitor: 884 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 885 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 886 trans_pcie->fw_mon_phys >> dest->base_shift); 887 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 888 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 889 (trans_pcie->fw_mon_phys + 890 trans_pcie->fw_mon_size - 256) >> 891 dest->end_shift); 892 else 893 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 894 (trans_pcie->fw_mon_phys + 895 trans_pcie->fw_mon_size) >> 896 dest->end_shift); 897 } 898 } 899 900 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 901 const struct fw_img *image) 902 { 903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 904 int ret = 0; 905 int first_ucode_section; 906 907 IWL_DEBUG_FW(trans, "working with %s CPU\n", 908 image->is_dual_cpus ? "Dual" : "Single"); 909 910 /* load to FW the binary non secured sections of CPU1 */ 911 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 912 if (ret) 913 return ret; 914 915 if (image->is_dual_cpus) { 916 /* set CPU2 header address */ 917 iwl_write_prph(trans, 918 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 919 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 920 921 /* load to FW the binary sections of CPU2 */ 922 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 923 &first_ucode_section); 924 if (ret) 925 return ret; 926 } 927 928 /* supported for 7000 only for the moment */ 929 if (iwlwifi_mod_params.fw_monitor && 930 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 931 iwl_pcie_alloc_fw_monitor(trans, 0); 932 933 if (trans_pcie->fw_mon_size) { 934 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 935 trans_pcie->fw_mon_phys >> 4); 936 iwl_write_prph(trans, MON_BUFF_END_ADDR, 937 (trans_pcie->fw_mon_phys + 938 trans_pcie->fw_mon_size) >> 4); 939 } 940 } else if (trans->dbg_dest_tlv) { 941 iwl_pcie_apply_destination(trans); 942 } 943 944 iwl_enable_interrupts(trans); 945 946 /* release CPU reset */ 947 iwl_write32(trans, CSR_RESET, 0); 948 949 return 0; 950 } 951 952 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 953 const struct fw_img *image) 954 { 955 int ret = 0; 956 int first_ucode_section; 957 958 IWL_DEBUG_FW(trans, "working with %s CPU\n", 959 image->is_dual_cpus ? "Dual" : "Single"); 960 961 if (trans->dbg_dest_tlv) 962 iwl_pcie_apply_destination(trans); 963 964 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 965 iwl_read_prph(trans, WFPM_GP2)); 966 967 /* 968 * Set default value. On resume reading the values that were 969 * zeored can provide debug data on the resume flow. 970 * This is for debugging only and has no functional impact. 971 */ 972 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 973 974 /* configure the ucode to be ready to get the secured image */ 975 /* release CPU reset */ 976 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 977 978 /* load to FW the binary Secured sections of CPU1 */ 979 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 980 &first_ucode_section); 981 if (ret) 982 return ret; 983 984 /* load to FW the binary sections of CPU2 */ 985 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 986 &first_ucode_section); 987 } 988 989 bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans) 990 { 991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 992 bool hw_rfkill = iwl_is_rfkill_set(trans); 993 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 994 bool report; 995 996 if (hw_rfkill) { 997 set_bit(STATUS_RFKILL_HW, &trans->status); 998 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 999 } else { 1000 clear_bit(STATUS_RFKILL_HW, &trans->status); 1001 if (trans_pcie->opmode_down) 1002 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1003 } 1004 1005 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1006 1007 if (prev != report) 1008 iwl_trans_pcie_rf_kill(trans, report); 1009 1010 return hw_rfkill; 1011 } 1012 1013 struct iwl_causes_list { 1014 u32 cause_num; 1015 u32 mask_reg; 1016 u8 addr; 1017 }; 1018 1019 static struct iwl_causes_list causes_list[] = { 1020 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1021 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1022 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1023 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1024 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1025 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1026 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1027 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1028 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1029 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1030 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1031 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1032 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1033 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1034 }; 1035 1036 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1037 { 1038 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1039 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1040 int i; 1041 1042 /* 1043 * Access all non RX causes and map them to the default irq. 1044 * In case we are missing at least one interrupt vector, 1045 * the first interrupt vector will serve non-RX and FBQ causes. 1046 */ 1047 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1048 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1049 iwl_clear_bit(trans, causes_list[i].mask_reg, 1050 causes_list[i].cause_num); 1051 } 1052 } 1053 1054 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1055 { 1056 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1057 u32 offset = 1058 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1059 u32 val, idx; 1060 1061 /* 1062 * The first RX queue - fallback queue, which is designated for 1063 * management frame, command responses etc, is always mapped to the 1064 * first interrupt vector. The other RX queues are mapped to 1065 * the other (N - 2) interrupt vectors. 1066 */ 1067 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1068 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1069 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1070 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1071 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1072 } 1073 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1074 1075 val = MSIX_FH_INT_CAUSES_Q(0); 1076 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1077 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1078 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1079 1080 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1081 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1082 } 1083 1084 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1085 { 1086 struct iwl_trans *trans = trans_pcie->trans; 1087 1088 if (!trans_pcie->msix_enabled) { 1089 if (trans->cfg->mq_rx_supported && 1090 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1091 iwl_write_prph(trans, UREG_CHICK, 1092 UREG_CHICK_MSI_ENABLE); 1093 return; 1094 } 1095 /* 1096 * The IVAR table needs to be configured again after reset, 1097 * but if the device is disabled, we can't write to 1098 * prph. 1099 */ 1100 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1101 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1102 1103 /* 1104 * Each cause from the causes list above and the RX causes is 1105 * represented as a byte in the IVAR table. The first nibble 1106 * represents the bound interrupt vector of the cause, the second 1107 * represents no auto clear for this cause. This will be set if its 1108 * interrupt vector is bound to serve other causes. 1109 */ 1110 iwl_pcie_map_rx_causes(trans); 1111 1112 iwl_pcie_map_non_rx_causes(trans); 1113 } 1114 1115 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1116 { 1117 struct iwl_trans *trans = trans_pcie->trans; 1118 1119 iwl_pcie_conf_msix_hw(trans_pcie); 1120 1121 if (!trans_pcie->msix_enabled) 1122 return; 1123 1124 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1125 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1126 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1127 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1128 } 1129 1130 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1131 { 1132 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1133 1134 lockdep_assert_held(&trans_pcie->mutex); 1135 1136 if (trans_pcie->is_down) 1137 return; 1138 1139 trans_pcie->is_down = true; 1140 1141 /* tell the device to stop sending interrupts */ 1142 iwl_disable_interrupts(trans); 1143 1144 /* device going down, Stop using ICT table */ 1145 iwl_pcie_disable_ict(trans); 1146 1147 /* 1148 * If a HW restart happens during firmware loading, 1149 * then the firmware loading might call this function 1150 * and later it might be called again due to the 1151 * restart. So don't process again if the device is 1152 * already dead. 1153 */ 1154 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1155 IWL_DEBUG_INFO(trans, 1156 "DEVICE_ENABLED bit was set and is now cleared\n"); 1157 iwl_pcie_tx_stop(trans); 1158 iwl_pcie_rx_stop(trans); 1159 1160 /* Power-down device's busmaster DMA clocks */ 1161 if (!trans->cfg->apmg_not_supported) { 1162 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1163 APMG_CLK_VAL_DMA_CLK_RQT); 1164 udelay(5); 1165 } 1166 } 1167 1168 /* Make sure (redundant) we've released our request to stay awake */ 1169 iwl_clear_bit(trans, CSR_GP_CNTRL, 1170 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1171 1172 /* Stop the device, and put it in low power state */ 1173 iwl_pcie_apm_stop(trans, false); 1174 1175 iwl_pcie_sw_reset(trans); 1176 1177 /* 1178 * Upon stop, the IVAR table gets erased, so msi-x won't 1179 * work. This causes a bug in RF-KILL flows, since the interrupt 1180 * that enables radio won't fire on the correct irq, and the 1181 * driver won't be able to handle the interrupt. 1182 * Configure the IVAR table again after reset. 1183 */ 1184 iwl_pcie_conf_msix_hw(trans_pcie); 1185 1186 /* 1187 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1188 * This is a bug in certain verions of the hardware. 1189 * Certain devices also keep sending HW RF kill interrupt all 1190 * the time, unless the interrupt is ACKed even if the interrupt 1191 * should be masked. Re-ACK all the interrupts here. 1192 */ 1193 iwl_disable_interrupts(trans); 1194 1195 /* clear all status bits */ 1196 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1197 clear_bit(STATUS_INT_ENABLED, &trans->status); 1198 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1199 1200 /* 1201 * Even if we stop the HW, we still want the RF kill 1202 * interrupt 1203 */ 1204 iwl_enable_rfkill_int(trans); 1205 1206 /* re-take ownership to prevent other users from stealing the device */ 1207 iwl_pcie_prepare_card_hw(trans); 1208 } 1209 1210 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1211 { 1212 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1213 1214 if (trans_pcie->msix_enabled) { 1215 int i; 1216 1217 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1218 synchronize_irq(trans_pcie->msix_entries[i].vector); 1219 } else { 1220 synchronize_irq(trans_pcie->pci_dev->irq); 1221 } 1222 } 1223 1224 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1225 const struct fw_img *fw, bool run_in_rfkill) 1226 { 1227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1228 bool hw_rfkill; 1229 int ret; 1230 1231 /* This may fail if AMT took ownership of the device */ 1232 if (iwl_pcie_prepare_card_hw(trans)) { 1233 IWL_WARN(trans, "Exit HW not ready\n"); 1234 ret = -EIO; 1235 goto out; 1236 } 1237 1238 iwl_enable_rfkill_int(trans); 1239 1240 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1241 1242 /* 1243 * We enabled the RF-Kill interrupt and the handler may very 1244 * well be running. Disable the interrupts to make sure no other 1245 * interrupt can be fired. 1246 */ 1247 iwl_disable_interrupts(trans); 1248 1249 /* Make sure it finished running */ 1250 iwl_pcie_synchronize_irqs(trans); 1251 1252 mutex_lock(&trans_pcie->mutex); 1253 1254 /* If platform's RF_KILL switch is NOT set to KILL */ 1255 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1256 if (hw_rfkill && !run_in_rfkill) { 1257 ret = -ERFKILL; 1258 goto out; 1259 } 1260 1261 /* Someone called stop_device, don't try to start_fw */ 1262 if (trans_pcie->is_down) { 1263 IWL_WARN(trans, 1264 "Can't start_fw since the HW hasn't been started\n"); 1265 ret = -EIO; 1266 goto out; 1267 } 1268 1269 /* make sure rfkill handshake bits are cleared */ 1270 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1271 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1272 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1273 1274 /* clear (again), then enable host interrupts */ 1275 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1276 1277 ret = iwl_pcie_nic_init(trans); 1278 if (ret) { 1279 IWL_ERR(trans, "Unable to init nic\n"); 1280 goto out; 1281 } 1282 1283 /* 1284 * Now, we load the firmware and don't want to be interrupted, even 1285 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1286 * FH_TX interrupt which is needed to load the firmware). If the 1287 * RF-Kill switch is toggled, we will find out after having loaded 1288 * the firmware and return the proper value to the caller. 1289 */ 1290 iwl_enable_fw_load_int(trans); 1291 1292 /* really make sure rfkill handshake bits are cleared */ 1293 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1294 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1295 1296 /* Load the given image to the HW */ 1297 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1298 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1299 else 1300 ret = iwl_pcie_load_given_ucode(trans, fw); 1301 1302 /* re-check RF-Kill state since we may have missed the interrupt */ 1303 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1304 if (hw_rfkill && !run_in_rfkill) 1305 ret = -ERFKILL; 1306 1307 out: 1308 mutex_unlock(&trans_pcie->mutex); 1309 return ret; 1310 } 1311 1312 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1313 { 1314 iwl_pcie_reset_ict(trans); 1315 iwl_pcie_tx_start(trans, scd_addr); 1316 } 1317 1318 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1319 bool was_in_rfkill) 1320 { 1321 bool hw_rfkill; 1322 1323 /* 1324 * Check again since the RF kill state may have changed while 1325 * all the interrupts were disabled, in this case we couldn't 1326 * receive the RF kill interrupt and update the state in the 1327 * op_mode. 1328 * Don't call the op_mode if the rkfill state hasn't changed. 1329 * This allows the op_mode to call stop_device from the rfkill 1330 * notification without endless recursion. Under very rare 1331 * circumstances, we might have a small recursion if the rfkill 1332 * state changed exactly now while we were called from stop_device. 1333 * This is very unlikely but can happen and is supported. 1334 */ 1335 hw_rfkill = iwl_is_rfkill_set(trans); 1336 if (hw_rfkill) { 1337 set_bit(STATUS_RFKILL_HW, &trans->status); 1338 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1339 } else { 1340 clear_bit(STATUS_RFKILL_HW, &trans->status); 1341 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1342 } 1343 if (hw_rfkill != was_in_rfkill) 1344 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1345 } 1346 1347 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1348 { 1349 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1350 bool was_in_rfkill; 1351 1352 mutex_lock(&trans_pcie->mutex); 1353 trans_pcie->opmode_down = true; 1354 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1355 _iwl_trans_pcie_stop_device(trans, low_power); 1356 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1357 mutex_unlock(&trans_pcie->mutex); 1358 } 1359 1360 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1361 { 1362 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1363 IWL_TRANS_GET_PCIE_TRANS(trans); 1364 1365 lockdep_assert_held(&trans_pcie->mutex); 1366 1367 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1368 state ? "disabled" : "enabled"); 1369 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1370 if (trans->cfg->gen2) 1371 _iwl_trans_pcie_gen2_stop_device(trans, true); 1372 else 1373 _iwl_trans_pcie_stop_device(trans, true); 1374 } 1375 } 1376 1377 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1378 bool reset) 1379 { 1380 if (!reset) { 1381 /* Enable persistence mode to avoid reset */ 1382 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1383 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1384 } 1385 1386 iwl_disable_interrupts(trans); 1387 1388 /* 1389 * in testing mode, the host stays awake and the 1390 * hardware won't be reset (not even partially) 1391 */ 1392 if (test) 1393 return; 1394 1395 iwl_pcie_disable_ict(trans); 1396 1397 iwl_pcie_synchronize_irqs(trans); 1398 1399 iwl_clear_bit(trans, CSR_GP_CNTRL, 1400 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1401 iwl_clear_bit(trans, CSR_GP_CNTRL, 1402 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1403 1404 iwl_pcie_enable_rx_wake(trans, false); 1405 1406 if (reset) { 1407 /* 1408 * reset TX queues -- some of their registers reset during S3 1409 * so if we don't reset everything here the D3 image would try 1410 * to execute some invalid memory upon resume 1411 */ 1412 iwl_trans_pcie_tx_reset(trans); 1413 } 1414 1415 iwl_pcie_set_pwr(trans, true); 1416 } 1417 1418 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1419 enum iwl_d3_status *status, 1420 bool test, bool reset) 1421 { 1422 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1423 u32 val; 1424 int ret; 1425 1426 if (test) { 1427 iwl_enable_interrupts(trans); 1428 *status = IWL_D3_STATUS_ALIVE; 1429 return 0; 1430 } 1431 1432 iwl_pcie_enable_rx_wake(trans, true); 1433 1434 /* 1435 * Reconfigure IVAR table in case of MSIX or reset ict table in 1436 * MSI mode since HW reset erased it. 1437 * Also enables interrupts - none will happen as 1438 * the device doesn't know we're waking it up, only when 1439 * the opmode actually tells it after this call. 1440 */ 1441 iwl_pcie_conf_msix_hw(trans_pcie); 1442 if (!trans_pcie->msix_enabled) 1443 iwl_pcie_reset_ict(trans); 1444 iwl_enable_interrupts(trans); 1445 1446 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1447 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1448 1449 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1450 udelay(2); 1451 1452 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1453 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1454 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1455 25000); 1456 if (ret < 0) { 1457 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1458 return ret; 1459 } 1460 1461 iwl_pcie_set_pwr(trans, false); 1462 1463 if (!reset) { 1464 iwl_clear_bit(trans, CSR_GP_CNTRL, 1465 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1466 } else { 1467 iwl_trans_pcie_tx_reset(trans); 1468 1469 ret = iwl_pcie_rx_init(trans); 1470 if (ret) { 1471 IWL_ERR(trans, 1472 "Failed to resume the device (RX reset)\n"); 1473 return ret; 1474 } 1475 } 1476 1477 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1478 iwl_read_prph(trans, WFPM_GP2)); 1479 1480 val = iwl_read32(trans, CSR_RESET); 1481 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1482 *status = IWL_D3_STATUS_RESET; 1483 else 1484 *status = IWL_D3_STATUS_ALIVE; 1485 1486 return 0; 1487 } 1488 1489 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1490 struct iwl_trans *trans) 1491 { 1492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1493 int max_irqs, num_irqs, i, ret, nr_online_cpus; 1494 u16 pci_cmd; 1495 1496 if (!trans->cfg->mq_rx_supported) 1497 goto enable_msi; 1498 1499 nr_online_cpus = num_online_cpus(); 1500 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 1501 for (i = 0; i < max_irqs; i++) 1502 trans_pcie->msix_entries[i].entry = i; 1503 1504 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1505 MSIX_MIN_INTERRUPT_VECTORS, 1506 max_irqs); 1507 if (num_irqs < 0) { 1508 IWL_DEBUG_INFO(trans, 1509 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1510 num_irqs); 1511 goto enable_msi; 1512 } 1513 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1514 1515 IWL_DEBUG_INFO(trans, 1516 "MSI-X enabled. %d interrupt vectors were allocated\n", 1517 num_irqs); 1518 1519 /* 1520 * In case the OS provides fewer interrupts than requested, different 1521 * causes will share the same interrupt vector as follows: 1522 * One interrupt less: non rx causes shared with FBQ. 1523 * Two interrupts less: non rx causes shared with FBQ and RSS. 1524 * More than two interrupts: we will use fewer RSS queues. 1525 */ 1526 if (num_irqs <= nr_online_cpus) { 1527 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1528 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1529 IWL_SHARED_IRQ_FIRST_RSS; 1530 } else if (num_irqs == nr_online_cpus + 1) { 1531 trans_pcie->trans->num_rx_queues = num_irqs; 1532 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1533 } else { 1534 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1535 } 1536 1537 trans_pcie->alloc_vecs = num_irqs; 1538 trans_pcie->msix_enabled = true; 1539 return; 1540 1541 enable_msi: 1542 ret = pci_enable_msi(pdev); 1543 if (ret) { 1544 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1545 /* enable rfkill interrupt: hw bug w/a */ 1546 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1547 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1548 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1549 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1550 } 1551 } 1552 } 1553 1554 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1555 { 1556 int iter_rx_q, i, ret, cpu, offset; 1557 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1558 1559 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1560 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1561 offset = 1 + i; 1562 for (; i < iter_rx_q ; i++) { 1563 /* 1564 * Get the cpu prior to the place to search 1565 * (i.e. return will be > i - 1). 1566 */ 1567 cpu = cpumask_next(i - offset, cpu_online_mask); 1568 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1569 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1570 &trans_pcie->affinity_mask[i]); 1571 if (ret) 1572 IWL_ERR(trans_pcie->trans, 1573 "Failed to set affinity mask for IRQ %d\n", 1574 i); 1575 } 1576 } 1577 1578 static const char *queue_name(struct device *dev, 1579 struct iwl_trans_pcie *trans_p, int i) 1580 { 1581 if (trans_p->shared_vec_mask) { 1582 int vec = trans_p->shared_vec_mask & 1583 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1584 1585 if (i == 0) 1586 return DRV_NAME ": shared IRQ"; 1587 1588 return devm_kasprintf(dev, GFP_KERNEL, 1589 DRV_NAME ": queue %d", i + vec); 1590 } 1591 if (i == 0) 1592 return DRV_NAME ": default queue"; 1593 1594 if (i == trans_p->alloc_vecs - 1) 1595 return DRV_NAME ": exception"; 1596 1597 return devm_kasprintf(dev, GFP_KERNEL, 1598 DRV_NAME ": queue %d", i); 1599 } 1600 1601 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1602 struct iwl_trans_pcie *trans_pcie) 1603 { 1604 int i; 1605 1606 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1607 int ret; 1608 struct msix_entry *msix_entry; 1609 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1610 1611 if (!qname) 1612 return -ENOMEM; 1613 1614 msix_entry = &trans_pcie->msix_entries[i]; 1615 ret = devm_request_threaded_irq(&pdev->dev, 1616 msix_entry->vector, 1617 iwl_pcie_msix_isr, 1618 (i == trans_pcie->def_irq) ? 1619 iwl_pcie_irq_msix_handler : 1620 iwl_pcie_irq_rx_msix_handler, 1621 IRQF_SHARED, 1622 qname, 1623 msix_entry); 1624 if (ret) { 1625 IWL_ERR(trans_pcie->trans, 1626 "Error allocating IRQ %d\n", i); 1627 1628 return ret; 1629 } 1630 } 1631 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1632 1633 return 0; 1634 } 1635 1636 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1637 { 1638 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1639 int err; 1640 1641 lockdep_assert_held(&trans_pcie->mutex); 1642 1643 err = iwl_pcie_prepare_card_hw(trans); 1644 if (err) { 1645 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1646 return err; 1647 } 1648 1649 iwl_pcie_sw_reset(trans); 1650 1651 err = iwl_pcie_apm_init(trans); 1652 if (err) 1653 return err; 1654 1655 iwl_pcie_init_msix(trans_pcie); 1656 1657 /* From now on, the op_mode will be kept updated about RF kill state */ 1658 iwl_enable_rfkill_int(trans); 1659 1660 trans_pcie->opmode_down = false; 1661 1662 /* Set is_down to false here so that...*/ 1663 trans_pcie->is_down = false; 1664 1665 /* ...rfkill can call stop_device and set it false if needed */ 1666 iwl_trans_check_hw_rf_kill(trans); 1667 1668 /* Make sure we sync here, because we'll need full access later */ 1669 if (low_power) 1670 pm_runtime_resume(trans->dev); 1671 1672 return 0; 1673 } 1674 1675 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1676 { 1677 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1678 int ret; 1679 1680 mutex_lock(&trans_pcie->mutex); 1681 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1682 mutex_unlock(&trans_pcie->mutex); 1683 1684 return ret; 1685 } 1686 1687 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1688 { 1689 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1690 1691 mutex_lock(&trans_pcie->mutex); 1692 1693 /* disable interrupts - don't enable HW RF kill interrupt */ 1694 iwl_disable_interrupts(trans); 1695 1696 iwl_pcie_apm_stop(trans, true); 1697 1698 iwl_disable_interrupts(trans); 1699 1700 iwl_pcie_disable_ict(trans); 1701 1702 mutex_unlock(&trans_pcie->mutex); 1703 1704 iwl_pcie_synchronize_irqs(trans); 1705 } 1706 1707 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1708 { 1709 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1710 } 1711 1712 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1713 { 1714 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1715 } 1716 1717 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1718 { 1719 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1720 } 1721 1722 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1723 { 1724 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1725 ((reg & 0x000FFFFF) | (3 << 24))); 1726 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1727 } 1728 1729 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1730 u32 val) 1731 { 1732 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1733 ((addr & 0x000FFFFF) | (3 << 24))); 1734 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1735 } 1736 1737 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1738 const struct iwl_trans_config *trans_cfg) 1739 { 1740 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1741 1742 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1743 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1744 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1745 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1746 trans_pcie->n_no_reclaim_cmds = 0; 1747 else 1748 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1749 if (trans_pcie->n_no_reclaim_cmds) 1750 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1751 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1752 1753 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1754 trans_pcie->rx_page_order = 1755 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1756 1757 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1758 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1759 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1760 1761 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1762 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1763 1764 trans->command_groups = trans_cfg->command_groups; 1765 trans->command_groups_size = trans_cfg->command_groups_size; 1766 1767 /* Initialize NAPI here - it should be before registering to mac80211 1768 * in the opmode but after the HW struct is allocated. 1769 * As this function may be called again in some corner cases don't 1770 * do anything if NAPI was already initialized. 1771 */ 1772 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1773 init_dummy_netdev(&trans_pcie->napi_dev); 1774 } 1775 1776 void iwl_trans_pcie_free(struct iwl_trans *trans) 1777 { 1778 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1779 int i; 1780 1781 iwl_pcie_synchronize_irqs(trans); 1782 1783 if (trans->cfg->gen2) 1784 iwl_pcie_gen2_tx_free(trans); 1785 else 1786 iwl_pcie_tx_free(trans); 1787 iwl_pcie_rx_free(trans); 1788 1789 if (trans_pcie->msix_enabled) { 1790 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1791 irq_set_affinity_hint( 1792 trans_pcie->msix_entries[i].vector, 1793 NULL); 1794 } 1795 1796 trans_pcie->msix_enabled = false; 1797 } else { 1798 iwl_pcie_free_ict(trans); 1799 } 1800 1801 iwl_pcie_free_fw_monitor(trans); 1802 1803 for_each_possible_cpu(i) { 1804 struct iwl_tso_hdr_page *p = 1805 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1806 1807 if (p->page) 1808 __free_page(p->page); 1809 } 1810 1811 free_percpu(trans_pcie->tso_hdr_page); 1812 mutex_destroy(&trans_pcie->mutex); 1813 iwl_trans_free(trans); 1814 } 1815 1816 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1817 { 1818 if (state) 1819 set_bit(STATUS_TPOWER_PMI, &trans->status); 1820 else 1821 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1822 } 1823 1824 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1825 unsigned long *flags) 1826 { 1827 int ret; 1828 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1829 1830 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1831 1832 if (trans_pcie->cmd_hold_nic_awake) 1833 goto out; 1834 1835 /* this bit wakes up the NIC */ 1836 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1837 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1838 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1839 udelay(2); 1840 1841 /* 1842 * These bits say the device is running, and should keep running for 1843 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1844 * but they do not indicate that embedded SRAM is restored yet; 1845 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1846 * to/from host DRAM when sleeping/waking for power-saving. 1847 * Each direction takes approximately 1/4 millisecond; with this 1848 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1849 * series of register accesses are expected (e.g. reading Event Log), 1850 * to keep device from sleeping. 1851 * 1852 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1853 * SRAM is okay/restored. We don't check that here because this call 1854 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1855 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1856 * 1857 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1858 * and do not save/restore SRAM when power cycling. 1859 */ 1860 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1861 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1862 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1863 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1864 if (unlikely(ret < 0)) { 1865 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1866 WARN_ONCE(1, 1867 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1868 iwl_read32(trans, CSR_GP_CNTRL)); 1869 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1870 return false; 1871 } 1872 1873 out: 1874 /* 1875 * Fool sparse by faking we release the lock - sparse will 1876 * track nic_access anyway. 1877 */ 1878 __release(&trans_pcie->reg_lock); 1879 return true; 1880 } 1881 1882 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1883 unsigned long *flags) 1884 { 1885 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1886 1887 lockdep_assert_held(&trans_pcie->reg_lock); 1888 1889 /* 1890 * Fool sparse by faking we acquiring the lock - sparse will 1891 * track nic_access anyway. 1892 */ 1893 __acquire(&trans_pcie->reg_lock); 1894 1895 if (trans_pcie->cmd_hold_nic_awake) 1896 goto out; 1897 1898 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1899 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1900 /* 1901 * Above we read the CSR_GP_CNTRL register, which will flush 1902 * any previous writes, but we need the write that clears the 1903 * MAC_ACCESS_REQ bit to be performed before any other writes 1904 * scheduled on different CPUs (after we drop reg_lock). 1905 */ 1906 mmiowb(); 1907 out: 1908 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1909 } 1910 1911 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1912 void *buf, int dwords) 1913 { 1914 unsigned long flags; 1915 int offs, ret = 0; 1916 u32 *vals = buf; 1917 1918 if (iwl_trans_grab_nic_access(trans, &flags)) { 1919 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1920 for (offs = 0; offs < dwords; offs++) 1921 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1922 iwl_trans_release_nic_access(trans, &flags); 1923 } else { 1924 ret = -EBUSY; 1925 } 1926 return ret; 1927 } 1928 1929 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1930 const void *buf, int dwords) 1931 { 1932 unsigned long flags; 1933 int offs, ret = 0; 1934 const u32 *vals = buf; 1935 1936 if (iwl_trans_grab_nic_access(trans, &flags)) { 1937 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1938 for (offs = 0; offs < dwords; offs++) 1939 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1940 vals ? vals[offs] : 0); 1941 iwl_trans_release_nic_access(trans, &flags); 1942 } else { 1943 ret = -EBUSY; 1944 } 1945 return ret; 1946 } 1947 1948 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1949 unsigned long txqs, 1950 bool freeze) 1951 { 1952 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1953 int queue; 1954 1955 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1956 struct iwl_txq *txq = trans_pcie->txq[queue]; 1957 unsigned long now; 1958 1959 spin_lock_bh(&txq->lock); 1960 1961 now = jiffies; 1962 1963 if (txq->frozen == freeze) 1964 goto next_queue; 1965 1966 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1967 freeze ? "Freezing" : "Waking", queue); 1968 1969 txq->frozen = freeze; 1970 1971 if (txq->read_ptr == txq->write_ptr) 1972 goto next_queue; 1973 1974 if (freeze) { 1975 if (unlikely(time_after(now, 1976 txq->stuck_timer.expires))) { 1977 /* 1978 * The timer should have fired, maybe it is 1979 * spinning right now on the lock. 1980 */ 1981 goto next_queue; 1982 } 1983 /* remember how long until the timer fires */ 1984 txq->frozen_expiry_remainder = 1985 txq->stuck_timer.expires - now; 1986 del_timer(&txq->stuck_timer); 1987 goto next_queue; 1988 } 1989 1990 /* 1991 * Wake a non-empty queue -> arm timer with the 1992 * remainder before it froze 1993 */ 1994 mod_timer(&txq->stuck_timer, 1995 now + txq->frozen_expiry_remainder); 1996 1997 next_queue: 1998 spin_unlock_bh(&txq->lock); 1999 } 2000 } 2001 2002 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2003 { 2004 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2005 int i; 2006 2007 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2008 struct iwl_txq *txq = trans_pcie->txq[i]; 2009 2010 if (i == trans_pcie->cmd_queue) 2011 continue; 2012 2013 spin_lock_bh(&txq->lock); 2014 2015 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2016 txq->block--; 2017 if (!txq->block) { 2018 iwl_write32(trans, HBUS_TARG_WRPTR, 2019 txq->write_ptr | (i << 8)); 2020 } 2021 } else if (block) { 2022 txq->block++; 2023 } 2024 2025 spin_unlock_bh(&txq->lock); 2026 } 2027 } 2028 2029 #define IWL_FLUSH_WAIT_MS 2000 2030 2031 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2032 { 2033 u32 txq_id = txq->id; 2034 u32 status; 2035 bool active; 2036 u8 fifo; 2037 2038 if (trans->cfg->use_tfh) { 2039 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2040 txq->read_ptr, txq->write_ptr); 2041 /* TODO: access new SCD registers and dump them */ 2042 return; 2043 } 2044 2045 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2046 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2047 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2048 2049 IWL_ERR(trans, 2050 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2051 txq_id, active ? "" : "in", fifo, 2052 jiffies_to_msecs(txq->wd_timeout), 2053 txq->read_ptr, txq->write_ptr, 2054 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2055 (TFD_QUEUE_SIZE_MAX - 1), 2056 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2057 (TFD_QUEUE_SIZE_MAX - 1), 2058 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2059 } 2060 2061 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2062 { 2063 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2064 struct iwl_txq *txq; 2065 unsigned long now = jiffies; 2066 u8 wr_ptr; 2067 2068 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2069 return -EINVAL; 2070 2071 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2072 txq = trans_pcie->txq[txq_idx]; 2073 wr_ptr = ACCESS_ONCE(txq->write_ptr); 2074 2075 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) && 2076 !time_after(jiffies, 2077 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2078 u8 write_ptr = ACCESS_ONCE(txq->write_ptr); 2079 2080 if (WARN_ONCE(wr_ptr != write_ptr, 2081 "WR pointer moved while flushing %d -> %d\n", 2082 wr_ptr, write_ptr)) 2083 return -ETIMEDOUT; 2084 usleep_range(1000, 2000); 2085 } 2086 2087 if (txq->read_ptr != txq->write_ptr) { 2088 IWL_ERR(trans, 2089 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2090 iwl_trans_pcie_log_scd_error(trans, txq); 2091 return -ETIMEDOUT; 2092 } 2093 2094 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2095 2096 return 0; 2097 } 2098 2099 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2100 { 2101 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2102 int cnt; 2103 int ret = 0; 2104 2105 /* waiting for all the tx frames complete might take a while */ 2106 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2107 2108 if (cnt == trans_pcie->cmd_queue) 2109 continue; 2110 if (!test_bit(cnt, trans_pcie->queue_used)) 2111 continue; 2112 if (!(BIT(cnt) & txq_bm)) 2113 continue; 2114 2115 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2116 if (ret) 2117 break; 2118 } 2119 2120 return ret; 2121 } 2122 2123 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2124 u32 mask, u32 value) 2125 { 2126 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2127 unsigned long flags; 2128 2129 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2130 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2131 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2132 } 2133 2134 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2135 { 2136 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2137 2138 if (iwlwifi_mod_params.d0i3_disable) 2139 return; 2140 2141 pm_runtime_get(&trans_pcie->pci_dev->dev); 2142 2143 #ifdef CONFIG_PM 2144 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2145 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2146 #endif /* CONFIG_PM */ 2147 } 2148 2149 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2150 { 2151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2152 2153 if (iwlwifi_mod_params.d0i3_disable) 2154 return; 2155 2156 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2157 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2158 2159 #ifdef CONFIG_PM 2160 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2161 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2162 #endif /* CONFIG_PM */ 2163 } 2164 2165 static const char *get_csr_string(int cmd) 2166 { 2167 #define IWL_CMD(x) case x: return #x 2168 switch (cmd) { 2169 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2170 IWL_CMD(CSR_INT_COALESCING); 2171 IWL_CMD(CSR_INT); 2172 IWL_CMD(CSR_INT_MASK); 2173 IWL_CMD(CSR_FH_INT_STATUS); 2174 IWL_CMD(CSR_GPIO_IN); 2175 IWL_CMD(CSR_RESET); 2176 IWL_CMD(CSR_GP_CNTRL); 2177 IWL_CMD(CSR_HW_REV); 2178 IWL_CMD(CSR_EEPROM_REG); 2179 IWL_CMD(CSR_EEPROM_GP); 2180 IWL_CMD(CSR_OTP_GP_REG); 2181 IWL_CMD(CSR_GIO_REG); 2182 IWL_CMD(CSR_GP_UCODE_REG); 2183 IWL_CMD(CSR_GP_DRIVER_REG); 2184 IWL_CMD(CSR_UCODE_DRV_GP1); 2185 IWL_CMD(CSR_UCODE_DRV_GP2); 2186 IWL_CMD(CSR_LED_REG); 2187 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2188 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2189 IWL_CMD(CSR_ANA_PLL_CFG); 2190 IWL_CMD(CSR_HW_REV_WA_REG); 2191 IWL_CMD(CSR_MONITOR_STATUS_REG); 2192 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2193 default: 2194 return "UNKNOWN"; 2195 } 2196 #undef IWL_CMD 2197 } 2198 2199 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2200 { 2201 int i; 2202 static const u32 csr_tbl[] = { 2203 CSR_HW_IF_CONFIG_REG, 2204 CSR_INT_COALESCING, 2205 CSR_INT, 2206 CSR_INT_MASK, 2207 CSR_FH_INT_STATUS, 2208 CSR_GPIO_IN, 2209 CSR_RESET, 2210 CSR_GP_CNTRL, 2211 CSR_HW_REV, 2212 CSR_EEPROM_REG, 2213 CSR_EEPROM_GP, 2214 CSR_OTP_GP_REG, 2215 CSR_GIO_REG, 2216 CSR_GP_UCODE_REG, 2217 CSR_GP_DRIVER_REG, 2218 CSR_UCODE_DRV_GP1, 2219 CSR_UCODE_DRV_GP2, 2220 CSR_LED_REG, 2221 CSR_DRAM_INT_TBL_REG, 2222 CSR_GIO_CHICKEN_BITS, 2223 CSR_ANA_PLL_CFG, 2224 CSR_MONITOR_STATUS_REG, 2225 CSR_HW_REV_WA_REG, 2226 CSR_DBG_HPET_MEM_REG 2227 }; 2228 IWL_ERR(trans, "CSR values:\n"); 2229 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2230 "CSR_INT_PERIODIC_REG)\n"); 2231 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2232 IWL_ERR(trans, " %25s: 0X%08x\n", 2233 get_csr_string(csr_tbl[i]), 2234 iwl_read32(trans, csr_tbl[i])); 2235 } 2236 } 2237 2238 #ifdef CONFIG_IWLWIFI_DEBUGFS 2239 /* create and remove of files */ 2240 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2241 if (!debugfs_create_file(#name, mode, parent, trans, \ 2242 &iwl_dbgfs_##name##_ops)) \ 2243 goto err; \ 2244 } while (0) 2245 2246 /* file operation */ 2247 #define DEBUGFS_READ_FILE_OPS(name) \ 2248 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2249 .read = iwl_dbgfs_##name##_read, \ 2250 .open = simple_open, \ 2251 .llseek = generic_file_llseek, \ 2252 }; 2253 2254 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2255 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2256 .write = iwl_dbgfs_##name##_write, \ 2257 .open = simple_open, \ 2258 .llseek = generic_file_llseek, \ 2259 }; 2260 2261 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2262 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2263 .write = iwl_dbgfs_##name##_write, \ 2264 .read = iwl_dbgfs_##name##_read, \ 2265 .open = simple_open, \ 2266 .llseek = generic_file_llseek, \ 2267 }; 2268 2269 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2270 char __user *user_buf, 2271 size_t count, loff_t *ppos) 2272 { 2273 struct iwl_trans *trans = file->private_data; 2274 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2275 struct iwl_txq *txq; 2276 char *buf; 2277 int pos = 0; 2278 int cnt; 2279 int ret; 2280 size_t bufsz; 2281 2282 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2283 2284 if (!trans_pcie->txq_memory) 2285 return -EAGAIN; 2286 2287 buf = kzalloc(bufsz, GFP_KERNEL); 2288 if (!buf) 2289 return -ENOMEM; 2290 2291 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2292 txq = trans_pcie->txq[cnt]; 2293 pos += scnprintf(buf + pos, bufsz - pos, 2294 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2295 cnt, txq->read_ptr, txq->write_ptr, 2296 !!test_bit(cnt, trans_pcie->queue_used), 2297 !!test_bit(cnt, trans_pcie->queue_stopped), 2298 txq->need_update, txq->frozen, 2299 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2300 } 2301 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2302 kfree(buf); 2303 return ret; 2304 } 2305 2306 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2307 char __user *user_buf, 2308 size_t count, loff_t *ppos) 2309 { 2310 struct iwl_trans *trans = file->private_data; 2311 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2312 char *buf; 2313 int pos = 0, i, ret; 2314 size_t bufsz = sizeof(buf); 2315 2316 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2317 2318 if (!trans_pcie->rxq) 2319 return -EAGAIN; 2320 2321 buf = kzalloc(bufsz, GFP_KERNEL); 2322 if (!buf) 2323 return -ENOMEM; 2324 2325 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2326 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2327 2328 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2329 i); 2330 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2331 rxq->read); 2332 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2333 rxq->write); 2334 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2335 rxq->write_actual); 2336 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2337 rxq->need_update); 2338 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2339 rxq->free_count); 2340 if (rxq->rb_stts) { 2341 pos += scnprintf(buf + pos, bufsz - pos, 2342 "\tclosed_rb_num: %u\n", 2343 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2344 0x0FFF); 2345 } else { 2346 pos += scnprintf(buf + pos, bufsz - pos, 2347 "\tclosed_rb_num: Not Allocated\n"); 2348 } 2349 } 2350 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2351 kfree(buf); 2352 2353 return ret; 2354 } 2355 2356 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2357 char __user *user_buf, 2358 size_t count, loff_t *ppos) 2359 { 2360 struct iwl_trans *trans = file->private_data; 2361 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2362 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2363 2364 int pos = 0; 2365 char *buf; 2366 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2367 ssize_t ret; 2368 2369 buf = kzalloc(bufsz, GFP_KERNEL); 2370 if (!buf) 2371 return -ENOMEM; 2372 2373 pos += scnprintf(buf + pos, bufsz - pos, 2374 "Interrupt Statistics Report:\n"); 2375 2376 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2377 isr_stats->hw); 2378 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2379 isr_stats->sw); 2380 if (isr_stats->sw || isr_stats->hw) { 2381 pos += scnprintf(buf + pos, bufsz - pos, 2382 "\tLast Restarting Code: 0x%X\n", 2383 isr_stats->err_code); 2384 } 2385 #ifdef CONFIG_IWLWIFI_DEBUG 2386 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2387 isr_stats->sch); 2388 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2389 isr_stats->alive); 2390 #endif 2391 pos += scnprintf(buf + pos, bufsz - pos, 2392 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2393 2394 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2395 isr_stats->ctkill); 2396 2397 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2398 isr_stats->wakeup); 2399 2400 pos += scnprintf(buf + pos, bufsz - pos, 2401 "Rx command responses:\t\t %u\n", isr_stats->rx); 2402 2403 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2404 isr_stats->tx); 2405 2406 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2407 isr_stats->unhandled); 2408 2409 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2410 kfree(buf); 2411 return ret; 2412 } 2413 2414 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2415 const char __user *user_buf, 2416 size_t count, loff_t *ppos) 2417 { 2418 struct iwl_trans *trans = file->private_data; 2419 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2420 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2421 u32 reset_flag; 2422 int ret; 2423 2424 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2425 if (ret) 2426 return ret; 2427 if (reset_flag == 0) 2428 memset(isr_stats, 0, sizeof(*isr_stats)); 2429 2430 return count; 2431 } 2432 2433 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2434 const char __user *user_buf, 2435 size_t count, loff_t *ppos) 2436 { 2437 struct iwl_trans *trans = file->private_data; 2438 2439 iwl_pcie_dump_csr(trans); 2440 2441 return count; 2442 } 2443 2444 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2445 char __user *user_buf, 2446 size_t count, loff_t *ppos) 2447 { 2448 struct iwl_trans *trans = file->private_data; 2449 char *buf = NULL; 2450 ssize_t ret; 2451 2452 ret = iwl_dump_fh(trans, &buf); 2453 if (ret < 0) 2454 return ret; 2455 if (!buf) 2456 return -EINVAL; 2457 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2458 kfree(buf); 2459 return ret; 2460 } 2461 2462 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2463 char __user *user_buf, 2464 size_t count, loff_t *ppos) 2465 { 2466 struct iwl_trans *trans = file->private_data; 2467 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2468 char buf[100]; 2469 int pos; 2470 2471 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2472 trans_pcie->debug_rfkill, 2473 !(iwl_read32(trans, CSR_GP_CNTRL) & 2474 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2475 2476 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2477 } 2478 2479 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2480 const char __user *user_buf, 2481 size_t count, loff_t *ppos) 2482 { 2483 struct iwl_trans *trans = file->private_data; 2484 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2485 bool old = trans_pcie->debug_rfkill; 2486 int ret; 2487 2488 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2489 if (ret) 2490 return ret; 2491 if (old == trans_pcie->debug_rfkill) 2492 return count; 2493 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2494 old, trans_pcie->debug_rfkill); 2495 iwl_pcie_handle_rfkill_irq(trans); 2496 2497 return count; 2498 } 2499 2500 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2501 DEBUGFS_READ_FILE_OPS(fh_reg); 2502 DEBUGFS_READ_FILE_OPS(rx_queue); 2503 DEBUGFS_READ_FILE_OPS(tx_queue); 2504 DEBUGFS_WRITE_FILE_OPS(csr); 2505 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2506 2507 /* Create the debugfs files and directories */ 2508 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2509 { 2510 struct dentry *dir = trans->dbgfs_dir; 2511 2512 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2513 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2514 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2515 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2516 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2517 DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR); 2518 return 0; 2519 2520 err: 2521 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2522 return -ENOMEM; 2523 } 2524 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2525 2526 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2527 { 2528 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2529 u32 cmdlen = 0; 2530 int i; 2531 2532 for (i = 0; i < trans_pcie->max_tbs; i++) 2533 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2534 2535 return cmdlen; 2536 } 2537 2538 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2539 struct iwl_fw_error_dump_data **data, 2540 int allocated_rb_nums) 2541 { 2542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2543 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2544 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2545 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2546 u32 i, r, j, rb_len = 0; 2547 2548 spin_lock(&rxq->lock); 2549 2550 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2551 2552 for (i = rxq->read, j = 0; 2553 i != r && j < allocated_rb_nums; 2554 i = (i + 1) & RX_QUEUE_MASK, j++) { 2555 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2556 struct iwl_fw_error_dump_rb *rb; 2557 2558 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2559 DMA_FROM_DEVICE); 2560 2561 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2562 2563 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2564 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2565 rb = (void *)(*data)->data; 2566 rb->index = cpu_to_le32(i); 2567 memcpy(rb->data, page_address(rxb->page), max_len); 2568 /* remap the page for the free benefit */ 2569 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2570 max_len, 2571 DMA_FROM_DEVICE); 2572 2573 *data = iwl_fw_error_next_data(*data); 2574 } 2575 2576 spin_unlock(&rxq->lock); 2577 2578 return rb_len; 2579 } 2580 #define IWL_CSR_TO_DUMP (0x250) 2581 2582 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2583 struct iwl_fw_error_dump_data **data) 2584 { 2585 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2586 __le32 *val; 2587 int i; 2588 2589 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2590 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2591 val = (void *)(*data)->data; 2592 2593 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2594 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2595 2596 *data = iwl_fw_error_next_data(*data); 2597 2598 return csr_len; 2599 } 2600 2601 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2602 struct iwl_fw_error_dump_data **data) 2603 { 2604 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2605 unsigned long flags; 2606 __le32 *val; 2607 int i; 2608 2609 if (!iwl_trans_grab_nic_access(trans, &flags)) 2610 return 0; 2611 2612 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2613 (*data)->len = cpu_to_le32(fh_regs_len); 2614 val = (void *)(*data)->data; 2615 2616 if (!trans->cfg->gen2) 2617 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2618 i += sizeof(u32)) 2619 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2620 else 2621 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2622 i += sizeof(u32)) 2623 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2624 i)); 2625 2626 iwl_trans_release_nic_access(trans, &flags); 2627 2628 *data = iwl_fw_error_next_data(*data); 2629 2630 return sizeof(**data) + fh_regs_len; 2631 } 2632 2633 static u32 2634 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2635 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2636 u32 monitor_len) 2637 { 2638 u32 buf_size_in_dwords = (monitor_len >> 2); 2639 u32 *buffer = (u32 *)fw_mon_data->data; 2640 unsigned long flags; 2641 u32 i; 2642 2643 if (!iwl_trans_grab_nic_access(trans, &flags)) 2644 return 0; 2645 2646 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2647 for (i = 0; i < buf_size_in_dwords; i++) 2648 buffer[i] = iwl_read_prph_no_grab(trans, 2649 MON_DMARB_RD_DATA_ADDR); 2650 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2651 2652 iwl_trans_release_nic_access(trans, &flags); 2653 2654 return monitor_len; 2655 } 2656 2657 static u32 2658 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2659 struct iwl_fw_error_dump_data **data, 2660 u32 monitor_len) 2661 { 2662 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2663 u32 len = 0; 2664 2665 if ((trans_pcie->fw_mon_page && 2666 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2667 trans->dbg_dest_tlv) { 2668 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2669 u32 base, write_ptr, wrap_cnt; 2670 2671 /* If there was a dest TLV - use the values from there */ 2672 if (trans->dbg_dest_tlv) { 2673 write_ptr = 2674 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2675 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2676 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2677 } else { 2678 base = MON_BUFF_BASE_ADDR; 2679 write_ptr = MON_BUFF_WRPTR; 2680 wrap_cnt = MON_BUFF_CYCLE_CNT; 2681 } 2682 2683 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2684 fw_mon_data = (void *)(*data)->data; 2685 fw_mon_data->fw_mon_wr_ptr = 2686 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2687 fw_mon_data->fw_mon_cycle_cnt = 2688 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2689 fw_mon_data->fw_mon_base_ptr = 2690 cpu_to_le32(iwl_read_prph(trans, base)); 2691 2692 len += sizeof(**data) + sizeof(*fw_mon_data); 2693 if (trans_pcie->fw_mon_page) { 2694 /* 2695 * The firmware is now asserted, it won't write anything 2696 * to the buffer. CPU can take ownership to fetch the 2697 * data. The buffer will be handed back to the device 2698 * before the firmware will be restarted. 2699 */ 2700 dma_sync_single_for_cpu(trans->dev, 2701 trans_pcie->fw_mon_phys, 2702 trans_pcie->fw_mon_size, 2703 DMA_FROM_DEVICE); 2704 memcpy(fw_mon_data->data, 2705 page_address(trans_pcie->fw_mon_page), 2706 trans_pcie->fw_mon_size); 2707 2708 monitor_len = trans_pcie->fw_mon_size; 2709 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2710 /* 2711 * Update pointers to reflect actual values after 2712 * shifting 2713 */ 2714 base = iwl_read_prph(trans, base) << 2715 trans->dbg_dest_tlv->base_shift; 2716 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2717 monitor_len / sizeof(u32)); 2718 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2719 monitor_len = 2720 iwl_trans_pci_dump_marbh_monitor(trans, 2721 fw_mon_data, 2722 monitor_len); 2723 } else { 2724 /* Didn't match anything - output no monitor data */ 2725 monitor_len = 0; 2726 } 2727 2728 len += monitor_len; 2729 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2730 } 2731 2732 return len; 2733 } 2734 2735 static struct iwl_trans_dump_data 2736 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2737 const struct iwl_fw_dbg_trigger_tlv *trigger) 2738 { 2739 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2740 struct iwl_fw_error_dump_data *data; 2741 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2742 struct iwl_fw_error_dump_txcmd *txcmd; 2743 struct iwl_trans_dump_data *dump_data; 2744 u32 len, num_rbs; 2745 u32 monitor_len; 2746 int i, ptr; 2747 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2748 !trans->cfg->mq_rx_supported; 2749 2750 /* transport dump header */ 2751 len = sizeof(*dump_data); 2752 2753 /* host commands */ 2754 len += sizeof(*data) + 2755 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2756 2757 /* FW monitor */ 2758 if (trans_pcie->fw_mon_page) { 2759 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2760 trans_pcie->fw_mon_size; 2761 monitor_len = trans_pcie->fw_mon_size; 2762 } else if (trans->dbg_dest_tlv) { 2763 u32 base, end; 2764 2765 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2766 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2767 2768 base = iwl_read_prph(trans, base) << 2769 trans->dbg_dest_tlv->base_shift; 2770 end = iwl_read_prph(trans, end) << 2771 trans->dbg_dest_tlv->end_shift; 2772 2773 /* Make "end" point to the actual end */ 2774 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 || 2775 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2776 end += (1 << trans->dbg_dest_tlv->end_shift); 2777 monitor_len = end - base; 2778 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2779 monitor_len; 2780 } else { 2781 monitor_len = 0; 2782 } 2783 2784 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2785 dump_data = vzalloc(len); 2786 if (!dump_data) 2787 return NULL; 2788 2789 data = (void *)dump_data->data; 2790 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2791 dump_data->len = len; 2792 2793 return dump_data; 2794 } 2795 2796 /* CSR registers */ 2797 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2798 2799 /* FH registers */ 2800 if (trans->cfg->gen2) 2801 len += sizeof(*data) + 2802 (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2); 2803 else 2804 len += sizeof(*data) + 2805 (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2806 2807 if (dump_rbs) { 2808 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2809 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2810 /* RBs */ 2811 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2812 & 0x0FFF; 2813 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2814 len += num_rbs * (sizeof(*data) + 2815 sizeof(struct iwl_fw_error_dump_rb) + 2816 (PAGE_SIZE << trans_pcie->rx_page_order)); 2817 } 2818 2819 /* Paged memory for gen2 HW */ 2820 if (trans->cfg->gen2) 2821 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 2822 len += sizeof(*data) + 2823 sizeof(struct iwl_fw_error_dump_paging) + 2824 trans_pcie->init_dram.paging[i].size; 2825 2826 dump_data = vzalloc(len); 2827 if (!dump_data) 2828 return NULL; 2829 2830 len = 0; 2831 data = (void *)dump_data->data; 2832 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2833 txcmd = (void *)data->data; 2834 spin_lock_bh(&cmdq->lock); 2835 ptr = cmdq->write_ptr; 2836 for (i = 0; i < cmdq->n_window; i++) { 2837 u8 idx = get_cmd_index(cmdq, ptr); 2838 u32 caplen, cmdlen; 2839 2840 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 2841 trans_pcie->tfd_size * ptr); 2842 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2843 2844 if (cmdlen) { 2845 len += sizeof(*txcmd) + caplen; 2846 txcmd->cmdlen = cpu_to_le32(cmdlen); 2847 txcmd->caplen = cpu_to_le32(caplen); 2848 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2849 txcmd = (void *)((u8 *)txcmd->data + caplen); 2850 } 2851 2852 ptr = iwl_queue_dec_wrap(ptr); 2853 } 2854 spin_unlock_bh(&cmdq->lock); 2855 2856 data->len = cpu_to_le32(len); 2857 len += sizeof(*data); 2858 data = iwl_fw_error_next_data(data); 2859 2860 len += iwl_trans_pcie_dump_csr(trans, &data); 2861 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2862 if (dump_rbs) 2863 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2864 2865 /* Paged memory for gen2 HW */ 2866 if (trans->cfg->gen2) { 2867 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 2868 struct iwl_fw_error_dump_paging *paging; 2869 dma_addr_t addr = 2870 trans_pcie->init_dram.paging[i].physical; 2871 u32 page_len = trans_pcie->init_dram.paging[i].size; 2872 2873 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 2874 data->len = cpu_to_le32(sizeof(*paging) + page_len); 2875 paging = (void *)data->data; 2876 paging->index = cpu_to_le32(i); 2877 dma_sync_single_for_cpu(trans->dev, addr, page_len, 2878 DMA_BIDIRECTIONAL); 2879 memcpy(paging->data, 2880 trans_pcie->init_dram.paging[i].block, page_len); 2881 data = iwl_fw_error_next_data(data); 2882 2883 len += sizeof(*data) + sizeof(*paging) + page_len; 2884 } 2885 } 2886 2887 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2888 2889 dump_data->len = len; 2890 2891 return dump_data; 2892 } 2893 2894 #ifdef CONFIG_PM_SLEEP 2895 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2896 { 2897 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 2898 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 2899 return iwl_pci_fw_enter_d0i3(trans); 2900 2901 return 0; 2902 } 2903 2904 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2905 { 2906 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 2907 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 2908 iwl_pci_fw_exit_d0i3(trans); 2909 } 2910 #endif /* CONFIG_PM_SLEEP */ 2911 2912 #define IWL_TRANS_COMMON_OPS \ 2913 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 2914 .write8 = iwl_trans_pcie_write8, \ 2915 .write32 = iwl_trans_pcie_write32, \ 2916 .read32 = iwl_trans_pcie_read32, \ 2917 .read_prph = iwl_trans_pcie_read_prph, \ 2918 .write_prph = iwl_trans_pcie_write_prph, \ 2919 .read_mem = iwl_trans_pcie_read_mem, \ 2920 .write_mem = iwl_trans_pcie_write_mem, \ 2921 .configure = iwl_trans_pcie_configure, \ 2922 .set_pmi = iwl_trans_pcie_set_pmi, \ 2923 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 2924 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 2925 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 2926 .ref = iwl_trans_pcie_ref, \ 2927 .unref = iwl_trans_pcie_unref, \ 2928 .dump_data = iwl_trans_pcie_dump_data, \ 2929 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 2930 .d3_resume = iwl_trans_pcie_d3_resume 2931 2932 #ifdef CONFIG_PM_SLEEP 2933 #define IWL_TRANS_PM_OPS \ 2934 .suspend = iwl_trans_pcie_suspend, \ 2935 .resume = iwl_trans_pcie_resume, 2936 #else 2937 #define IWL_TRANS_PM_OPS 2938 #endif /* CONFIG_PM_SLEEP */ 2939 2940 static const struct iwl_trans_ops trans_ops_pcie = { 2941 IWL_TRANS_COMMON_OPS, 2942 IWL_TRANS_PM_OPS 2943 .start_hw = iwl_trans_pcie_start_hw, 2944 .fw_alive = iwl_trans_pcie_fw_alive, 2945 .start_fw = iwl_trans_pcie_start_fw, 2946 .stop_device = iwl_trans_pcie_stop_device, 2947 2948 .send_cmd = iwl_trans_pcie_send_hcmd, 2949 2950 .tx = iwl_trans_pcie_tx, 2951 .reclaim = iwl_trans_pcie_reclaim, 2952 2953 .txq_disable = iwl_trans_pcie_txq_disable, 2954 .txq_enable = iwl_trans_pcie_txq_enable, 2955 2956 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2957 2958 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 2959 2960 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2961 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2962 }; 2963 2964 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 2965 IWL_TRANS_COMMON_OPS, 2966 IWL_TRANS_PM_OPS 2967 .start_hw = iwl_trans_pcie_start_hw, 2968 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 2969 .start_fw = iwl_trans_pcie_gen2_start_fw, 2970 .stop_device = iwl_trans_pcie_gen2_stop_device, 2971 2972 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 2973 2974 .tx = iwl_trans_pcie_gen2_tx, 2975 .reclaim = iwl_trans_pcie_reclaim, 2976 2977 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 2978 .txq_free = iwl_trans_pcie_dyn_txq_free, 2979 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 2980 }; 2981 2982 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2983 const struct pci_device_id *ent, 2984 const struct iwl_cfg *cfg) 2985 { 2986 struct iwl_trans_pcie *trans_pcie; 2987 struct iwl_trans *trans; 2988 int ret, addr_size; 2989 2990 ret = pcim_enable_device(pdev); 2991 if (ret) 2992 return ERR_PTR(ret); 2993 2994 if (cfg->gen2) 2995 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2996 &pdev->dev, cfg, &trans_ops_pcie_gen2); 2997 else 2998 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2999 &pdev->dev, cfg, &trans_ops_pcie); 3000 if (!trans) 3001 return ERR_PTR(-ENOMEM); 3002 3003 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3004 3005 trans_pcie->trans = trans; 3006 trans_pcie->opmode_down = true; 3007 spin_lock_init(&trans_pcie->irq_lock); 3008 spin_lock_init(&trans_pcie->reg_lock); 3009 mutex_init(&trans_pcie->mutex); 3010 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3011 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3012 if (!trans_pcie->tso_hdr_page) { 3013 ret = -ENOMEM; 3014 goto out_no_pci; 3015 } 3016 3017 3018 if (!cfg->base_params->pcie_l1_allowed) { 3019 /* 3020 * W/A - seems to solve weird behavior. We need to remove this 3021 * if we don't want to stay in L1 all the time. This wastes a 3022 * lot of power. 3023 */ 3024 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3025 PCIE_LINK_STATE_L1 | 3026 PCIE_LINK_STATE_CLKPM); 3027 } 3028 3029 if (cfg->use_tfh) { 3030 addr_size = 64; 3031 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3032 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3033 } else { 3034 addr_size = 36; 3035 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3036 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3037 } 3038 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3039 3040 pci_set_master(pdev); 3041 3042 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3043 if (!ret) 3044 ret = pci_set_consistent_dma_mask(pdev, 3045 DMA_BIT_MASK(addr_size)); 3046 if (ret) { 3047 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3048 if (!ret) 3049 ret = pci_set_consistent_dma_mask(pdev, 3050 DMA_BIT_MASK(32)); 3051 /* both attempts failed: */ 3052 if (ret) { 3053 dev_err(&pdev->dev, "No suitable DMA available\n"); 3054 goto out_no_pci; 3055 } 3056 } 3057 3058 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3059 if (ret) { 3060 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3061 goto out_no_pci; 3062 } 3063 3064 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3065 if (!trans_pcie->hw_base) { 3066 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3067 ret = -ENODEV; 3068 goto out_no_pci; 3069 } 3070 3071 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3072 * PCI Tx retries from interfering with C3 CPU state */ 3073 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3074 3075 trans_pcie->pci_dev = pdev; 3076 iwl_disable_interrupts(trans); 3077 3078 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3079 /* 3080 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3081 * changed, and now the revision step also includes bit 0-1 (no more 3082 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3083 * in the old format. 3084 */ 3085 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3086 unsigned long flags; 3087 3088 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3089 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3090 3091 ret = iwl_pcie_prepare_card_hw(trans); 3092 if (ret) { 3093 IWL_WARN(trans, "Exit HW not ready\n"); 3094 goto out_no_pci; 3095 } 3096 3097 /* 3098 * in-order to recognize C step driver should read chip version 3099 * id located at the AUX bus MISC address space. 3100 */ 3101 iwl_set_bit(trans, CSR_GP_CNTRL, 3102 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3103 udelay(2); 3104 3105 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3106 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3107 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3108 25000); 3109 if (ret < 0) { 3110 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3111 goto out_no_pci; 3112 } 3113 3114 if (iwl_trans_grab_nic_access(trans, &flags)) { 3115 u32 hw_step; 3116 3117 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3118 hw_step |= ENABLE_WFPM; 3119 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3120 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3121 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3122 if (hw_step == 0x3) 3123 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3124 (SILICON_C_STEP << 2); 3125 iwl_trans_release_nic_access(trans, &flags); 3126 } 3127 } 3128 3129 /* 3130 * 9000-series integrated A-step has a problem with suspend/resume 3131 * and sometimes even causes the whole platform to get stuck. This 3132 * workaround makes the hardware not go into the problematic state. 3133 */ 3134 if (trans->cfg->integrated && 3135 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3136 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3137 iwl_set_bit(trans, CSR_HOST_CHICKEN, 3138 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3139 3140 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3141 3142 iwl_pcie_set_interrupt_capa(pdev, trans); 3143 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3144 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3145 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3146 3147 /* Initialize the wait queue for commands */ 3148 init_waitqueue_head(&trans_pcie->wait_command_queue); 3149 3150 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3151 3152 if (trans_pcie->msix_enabled) { 3153 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3154 if (ret) 3155 goto out_no_pci; 3156 } else { 3157 ret = iwl_pcie_alloc_ict(trans); 3158 if (ret) 3159 goto out_no_pci; 3160 3161 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3162 iwl_pcie_isr, 3163 iwl_pcie_irq_handler, 3164 IRQF_SHARED, DRV_NAME, trans); 3165 if (ret) { 3166 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3167 goto out_free_ict; 3168 } 3169 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3170 } 3171 3172 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3173 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3174 #else 3175 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3176 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3177 3178 return trans; 3179 3180 out_free_ict: 3181 iwl_pcie_free_ict(trans); 3182 out_no_pci: 3183 free_percpu(trans_pcie->tso_hdr_page); 3184 iwl_trans_free(trans); 3185 return ERR_PTR(ret); 3186 } 3187