1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2007-2015, 2018-2022 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5  * Copyright (C) 2016-2017 Intel Deutschland GmbH
6  */
7 #include <linux/pci.h>
8 #include <linux/interrupt.h>
9 #include <linux/debugfs.h>
10 #include <linux/sched.h>
11 #include <linux/bitops.h>
12 #include <linux/gfp.h>
13 #include <linux/vmalloc.h>
14 #include <linux/module.h>
15 #include <linux/wait.h>
16 #include <linux/seq_file.h>
17 
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
25 #include "fw/dbg.h"
26 #include "fw/api/tx.h"
27 #include "mei/iwl-mei.h"
28 #include "internal.h"
29 #include "iwl-fh.h"
30 #include "iwl-context-info-gen3.h"
31 
32 /* extended range in FW SRAM */
33 #define IWL_FW_MEM_EXTENDED_START	0x40000
34 #define IWL_FW_MEM_EXTENDED_END		0x57FFF
35 
36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
37 {
38 #define PCI_DUMP_SIZE		352
39 #define PCI_MEM_DUMP_SIZE	64
40 #define PCI_PARENT_DUMP_SIZE	524
41 #define PREFIX_LEN		32
42 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
43 	struct pci_dev *pdev = trans_pcie->pci_dev;
44 	u32 i, pos, alloc_size, *ptr, *buf;
45 	char *prefix;
46 
47 	if (trans_pcie->pcie_dbg_dumped_once)
48 		return;
49 
50 	/* Should be a multiple of 4 */
51 	BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
52 	BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3);
53 	BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3);
54 
55 	/* Alloc a max size buffer */
56 	alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
57 	alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN);
58 	alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN);
59 	alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN);
60 
61 	buf = kmalloc(alloc_size, GFP_ATOMIC);
62 	if (!buf)
63 		return;
64 	prefix = (char *)buf + alloc_size - PREFIX_LEN;
65 
66 	IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
67 
68 	/* Print wifi device registers */
69 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
70 	IWL_ERR(trans, "iwlwifi device config registers:\n");
71 	for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
72 		if (pci_read_config_dword(pdev, i, ptr))
73 			goto err_read;
74 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
75 
76 	IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
77 	for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++)
78 		*ptr = iwl_read32(trans, i);
79 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
80 
81 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
82 	if (pos) {
83 		IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
84 		for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
85 			if (pci_read_config_dword(pdev, pos + i, ptr))
86 				goto err_read;
87 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
88 			       32, 4, buf, i, 0);
89 	}
90 
91 	/* Print parent device registers next */
92 	if (!pdev->bus->self)
93 		goto out;
94 
95 	pdev = pdev->bus->self;
96 	sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
97 
98 	IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
99 		pci_name(pdev));
100 	for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++)
101 		if (pci_read_config_dword(pdev, i, ptr))
102 			goto err_read;
103 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
104 
105 	/* Print root port AER registers */
106 	pos = 0;
107 	pdev = pcie_find_root_port(pdev);
108 	if (pdev)
109 		pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
110 	if (pos) {
111 		IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
112 			pci_name(pdev));
113 		sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
114 		for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
115 			if (pci_read_config_dword(pdev, pos + i, ptr))
116 				goto err_read;
117 		print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
118 			       4, buf, i, 0);
119 	}
120 	goto out;
121 
122 err_read:
123 	print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
124 	IWL_ERR(trans, "Read failed at 0x%X\n", i);
125 out:
126 	trans_pcie->pcie_dbg_dumped_once = 1;
127 	kfree(buf);
128 }
129 
130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
131 				   bool retake_ownership)
132 {
133 	/* Reset entire device - do controller reset (results in SHRD_HW_RST) */
134 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
135 		iwl_set_bit(trans, CSR_GP_CNTRL,
136 			    CSR_GP_CNTRL_REG_FLAG_SW_RESET);
137 	else
138 		iwl_set_bit(trans, CSR_RESET,
139 			    CSR_RESET_REG_FLAG_SW_RESET);
140 	usleep_range(5000, 6000);
141 
142 	if (retake_ownership)
143 		return iwl_pcie_prepare_card_hw(trans);
144 
145 	return 0;
146 }
147 
148 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
149 {
150 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
151 
152 	if (!fw_mon->size)
153 		return;
154 
155 	dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block,
156 			  fw_mon->physical);
157 
158 	fw_mon->block = NULL;
159 	fw_mon->physical = 0;
160 	fw_mon->size = 0;
161 }
162 
163 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans,
164 					    u8 max_power, u8 min_power)
165 {
166 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
167 	void *block = NULL;
168 	dma_addr_t physical = 0;
169 	u32 size = 0;
170 	u8 power;
171 
172 	if (fw_mon->size)
173 		return;
174 
175 	for (power = max_power; power >= min_power; power--) {
176 		size = BIT(power);
177 		block = dma_alloc_coherent(trans->dev, size, &physical,
178 					   GFP_KERNEL | __GFP_NOWARN);
179 		if (!block)
180 			continue;
181 
182 		IWL_INFO(trans,
183 			 "Allocated 0x%08x bytes for firmware monitor.\n",
184 			 size);
185 		break;
186 	}
187 
188 	if (WARN_ON_ONCE(!block))
189 		return;
190 
191 	if (power != max_power)
192 		IWL_ERR(trans,
193 			"Sorry - debug buffer is only %luK while you requested %luK\n",
194 			(unsigned long)BIT(power - 10),
195 			(unsigned long)BIT(max_power - 10));
196 
197 	fw_mon->block = block;
198 	fw_mon->physical = physical;
199 	fw_mon->size = size;
200 }
201 
202 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
203 {
204 	if (!max_power) {
205 		/* default max_power is maximum */
206 		max_power = 26;
207 	} else {
208 		max_power += 11;
209 	}
210 
211 	if (WARN(max_power > 26,
212 		 "External buffer size for monitor is too big %d, check the FW TLV\n",
213 		 max_power))
214 		return;
215 
216 	if (trans->dbg.fw_mon.size)
217 		return;
218 
219 	iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11);
220 }
221 
222 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
223 {
224 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
225 		    ((reg & 0x0000ffff) | (2 << 28)));
226 	return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
227 }
228 
229 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
230 {
231 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
232 	iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
233 		    ((reg & 0x0000ffff) | (3 << 28)));
234 }
235 
236 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
237 {
238 	if (trans->cfg->apmg_not_supported)
239 		return;
240 
241 	if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
242 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
243 				       APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
244 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
245 	else
246 		iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
247 				       APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
248 				       ~APMG_PS_CTRL_MSK_PWR_SRC);
249 }
250 
251 /* PCI registers */
252 #define PCI_CFG_RETRY_TIMEOUT	0x041
253 
254 void iwl_pcie_apm_config(struct iwl_trans *trans)
255 {
256 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
257 	u16 lctl;
258 	u16 cap;
259 
260 	/*
261 	 * L0S states have been found to be unstable with our devices
262 	 * and in newer hardware they are not officially supported at
263 	 * all, so we must always set the L0S_DISABLED bit.
264 	 */
265 	iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED);
266 
267 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
268 	trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
269 
270 	pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
271 	trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
272 	IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
273 			(lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
274 			trans->ltr_enabled ? "En" : "Dis");
275 }
276 
277 /*
278  * Start up NIC's basic functionality after it has been reset
279  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
280  * NOTE:  This does not load uCode nor start the embedded processor
281  */
282 static int iwl_pcie_apm_init(struct iwl_trans *trans)
283 {
284 	int ret;
285 
286 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
287 
288 	/*
289 	 * Use "set_bit" below rather than "write", to preserve any hardware
290 	 * bits already set by default after reset.
291 	 */
292 
293 	/* Disable L0S exit timer (platform NMI Work/Around) */
294 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000)
295 		iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
296 			    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
297 
298 	/*
299 	 * Disable L0s without affecting L1;
300 	 *  don't wait for ICH L0s (ICH bug W/A)
301 	 */
302 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
303 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
304 
305 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
306 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
307 
308 	/*
309 	 * Enable HAP INTA (interrupt from management bus) to
310 	 * wake device's PCI Express link L1a -> L0s
311 	 */
312 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
313 		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
314 
315 	iwl_pcie_apm_config(trans);
316 
317 	/* Configure analog phase-lock-loop before activating to D0A */
318 	if (trans->trans_cfg->base_params->pll_cfg)
319 		iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
320 
321 	ret = iwl_finish_nic_init(trans);
322 	if (ret)
323 		return ret;
324 
325 	if (trans->cfg->host_interrupt_operation_mode) {
326 		/*
327 		 * This is a bit of an abuse - This is needed for 7260 / 3160
328 		 * only check host_interrupt_operation_mode even if this is
329 		 * not related to host_interrupt_operation_mode.
330 		 *
331 		 * Enable the oscillator to count wake up time for L1 exit. This
332 		 * consumes slightly more power (100uA) - but allows to be sure
333 		 * that we wake up from L1 on time.
334 		 *
335 		 * This looks weird: read twice the same register, discard the
336 		 * value, set a bit, and yet again, read that same register
337 		 * just to discard the value. But that's the way the hardware
338 		 * seems to like it.
339 		 */
340 		iwl_read_prph(trans, OSC_CLK);
341 		iwl_read_prph(trans, OSC_CLK);
342 		iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
343 		iwl_read_prph(trans, OSC_CLK);
344 		iwl_read_prph(trans, OSC_CLK);
345 	}
346 
347 	/*
348 	 * Enable DMA clock and wait for it to stabilize.
349 	 *
350 	 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
351 	 * bits do not disable clocks.  This preserves any hardware
352 	 * bits already set by default in "CLK_CTRL_REG" after reset.
353 	 */
354 	if (!trans->cfg->apmg_not_supported) {
355 		iwl_write_prph(trans, APMG_CLK_EN_REG,
356 			       APMG_CLK_VAL_DMA_CLK_RQT);
357 		udelay(20);
358 
359 		/* Disable L1-Active */
360 		iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
361 				  APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
362 
363 		/* Clear the interrupt in APMG if the NIC is in RFKILL */
364 		iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
365 			       APMG_RTC_INT_STT_RFKILL);
366 	}
367 
368 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
369 
370 	return 0;
371 }
372 
373 /*
374  * Enable LP XTAL to avoid HW bug where device may consume much power if
375  * FW is not loaded after device reset. LP XTAL is disabled by default
376  * after device HW reset. Do it only if XTAL is fed by internal source.
377  * Configure device's "persistence" mode to avoid resetting XTAL again when
378  * SHRD_HW_RST occurs in S3.
379  */
380 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
381 {
382 	int ret;
383 	u32 apmg_gp1_reg;
384 	u32 apmg_xtal_cfg_reg;
385 	u32 dl_cfg_reg;
386 
387 	/* Force XTAL ON */
388 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
389 				 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
390 
391 	ret = iwl_trans_pcie_sw_reset(trans, true);
392 
393 	if (!ret)
394 		ret = iwl_finish_nic_init(trans);
395 
396 	if (WARN_ON(ret)) {
397 		/* Release XTAL ON request */
398 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
399 					   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
400 		return;
401 	}
402 
403 	/*
404 	 * Clear "disable persistence" to avoid LP XTAL resetting when
405 	 * SHRD_HW_RST is applied in S3.
406 	 */
407 	iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
408 				    APMG_PCIDEV_STT_VAL_PERSIST_DIS);
409 
410 	/*
411 	 * Force APMG XTAL to be active to prevent its disabling by HW
412 	 * caused by APMG idle state.
413 	 */
414 	apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
415 						    SHR_APMG_XTAL_CFG_REG);
416 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
417 				 apmg_xtal_cfg_reg |
418 				 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
419 
420 	ret = iwl_trans_pcie_sw_reset(trans, true);
421 	if (ret)
422 		IWL_ERR(trans,
423 			"iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n");
424 
425 	/* Enable LP XTAL by indirect access through CSR */
426 	apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
427 	iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
428 				 SHR_APMG_GP1_WF_XTAL_LP_EN |
429 				 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
430 
431 	/* Clear delay line clock power up */
432 	dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
433 	iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
434 				 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
435 
436 	/*
437 	 * Enable persistence mode to avoid LP XTAL resetting when
438 	 * SHRD_HW_RST is applied in S3.
439 	 */
440 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
441 		    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
442 
443 	/*
444 	 * Clear "initialization complete" bit to move adapter from
445 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
446 	 */
447 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
448 
449 	/* Activates XTAL resources monitor */
450 	__iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
451 				 CSR_MONITOR_XTAL_RESOURCES);
452 
453 	/* Release XTAL ON request */
454 	__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
455 				   CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
456 	udelay(10);
457 
458 	/* Release APMG XTAL */
459 	iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
460 				 apmg_xtal_cfg_reg &
461 				 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
462 }
463 
464 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
465 {
466 	int ret;
467 
468 	/* stop device's busmaster DMA activity */
469 
470 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
471 		iwl_set_bit(trans, CSR_GP_CNTRL,
472 			    CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
473 
474 		ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
475 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
476 				   CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
477 				   100);
478 		msleep(100);
479 	} else {
480 		iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
481 
482 		ret = iwl_poll_bit(trans, CSR_RESET,
483 				   CSR_RESET_REG_FLAG_MASTER_DISABLED,
484 				   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
485 	}
486 
487 	if (ret < 0)
488 		IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
489 
490 	IWL_DEBUG_INFO(trans, "stop master\n");
491 }
492 
493 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
494 {
495 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
496 
497 	if (op_mode_leave) {
498 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
499 			iwl_pcie_apm_init(trans);
500 
501 		/* inform ME that we are leaving */
502 		if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000)
503 			iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
504 					  APMG_PCIDEV_STT_VAL_WAKE_ME);
505 		else if (trans->trans_cfg->device_family >=
506 			 IWL_DEVICE_FAMILY_8000) {
507 			iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
508 				    CSR_RESET_LINK_PWR_MGMT_DISABLED);
509 			iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
510 				    CSR_HW_IF_CONFIG_REG_PREPARE |
511 				    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
512 			mdelay(1);
513 			iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
514 				      CSR_RESET_LINK_PWR_MGMT_DISABLED);
515 		}
516 		mdelay(5);
517 	}
518 
519 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
520 
521 	/* Stop device's DMA activity */
522 	iwl_pcie_apm_stop_master(trans);
523 
524 	if (trans->cfg->lp_xtal_workaround) {
525 		iwl_pcie_apm_lp_xtal_enable(trans);
526 		return;
527 	}
528 
529 	iwl_trans_pcie_sw_reset(trans, false);
530 
531 	/*
532 	 * Clear "initialization complete" bit to move adapter from
533 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
534 	 */
535 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
536 }
537 
538 static int iwl_pcie_nic_init(struct iwl_trans *trans)
539 {
540 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
541 	int ret;
542 
543 	/* nic_init */
544 	spin_lock_bh(&trans_pcie->irq_lock);
545 	ret = iwl_pcie_apm_init(trans);
546 	spin_unlock_bh(&trans_pcie->irq_lock);
547 
548 	if (ret)
549 		return ret;
550 
551 	iwl_pcie_set_pwr(trans, false);
552 
553 	iwl_op_mode_nic_config(trans->op_mode);
554 
555 	/* Allocate the RX queue, or reset if it is already allocated */
556 	ret = iwl_pcie_rx_init(trans);
557 	if (ret)
558 		return ret;
559 
560 	/* Allocate or reset and init all Tx and Command queues */
561 	if (iwl_pcie_tx_init(trans)) {
562 		iwl_pcie_rx_free(trans);
563 		return -ENOMEM;
564 	}
565 
566 	if (trans->trans_cfg->base_params->shadow_reg_enable) {
567 		/* enable shadow regs in HW */
568 		iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
569 		IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
570 	}
571 
572 	return 0;
573 }
574 
575 #define HW_READY_TIMEOUT (50)
576 
577 /* Note: returns poll_bit return value, which is >= 0 if success */
578 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
579 {
580 	int ret;
581 
582 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
583 		    CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
584 
585 	/* See if we got it */
586 	ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
587 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
588 			   CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
589 			   HW_READY_TIMEOUT);
590 
591 	if (ret >= 0)
592 		iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
593 
594 	IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
595 	return ret;
596 }
597 
598 /* Note: returns standard 0/-ERROR code */
599 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
600 {
601 	int ret;
602 	int t = 0;
603 	int iter;
604 
605 	IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
606 
607 	ret = iwl_pcie_set_hw_ready(trans);
608 	/* If the card is ready, exit 0 */
609 	if (ret >= 0) {
610 		trans->csme_own = false;
611 		return 0;
612 	}
613 
614 	iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
615 		    CSR_RESET_LINK_PWR_MGMT_DISABLED);
616 	usleep_range(1000, 2000);
617 
618 	for (iter = 0; iter < 10; iter++) {
619 		/* If HW is not ready, prepare the conditions to check again */
620 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
621 			    CSR_HW_IF_CONFIG_REG_PREPARE);
622 
623 		do {
624 			ret = iwl_pcie_set_hw_ready(trans);
625 			if (ret >= 0) {
626 				trans->csme_own = false;
627 				return 0;
628 			}
629 
630 			if (iwl_mei_is_connected()) {
631 				IWL_DEBUG_INFO(trans,
632 					       "Couldn't prepare the card but SAP is connected\n");
633 				trans->csme_own = true;
634 				if (trans->trans_cfg->device_family !=
635 				    IWL_DEVICE_FAMILY_9000)
636 					IWL_ERR(trans,
637 						"SAP not supported for this NIC family\n");
638 
639 				return -EBUSY;
640 			}
641 
642 			usleep_range(200, 1000);
643 			t += 200;
644 		} while (t < 150000);
645 		msleep(25);
646 	}
647 
648 	IWL_ERR(trans, "Couldn't prepare the card\n");
649 
650 	return ret;
651 }
652 
653 /*
654  * ucode
655  */
656 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
657 					    u32 dst_addr, dma_addr_t phy_addr,
658 					    u32 byte_cnt)
659 {
660 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
661 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
662 
663 	iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
664 		    dst_addr);
665 
666 	iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
667 		    phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
668 
669 	iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
670 		    (iwl_get_dma_hi_addr(phy_addr)
671 			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
672 
673 	iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
674 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
675 		    BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
676 		    FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
677 
678 	iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
679 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
680 		    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
681 		    FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
682 }
683 
684 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
685 					u32 dst_addr, dma_addr_t phy_addr,
686 					u32 byte_cnt)
687 {
688 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
689 	int ret;
690 
691 	trans_pcie->ucode_write_complete = false;
692 
693 	if (!iwl_trans_grab_nic_access(trans))
694 		return -EIO;
695 
696 	iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
697 					byte_cnt);
698 	iwl_trans_release_nic_access(trans);
699 
700 	ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
701 				 trans_pcie->ucode_write_complete, 5 * HZ);
702 	if (!ret) {
703 		IWL_ERR(trans, "Failed to load firmware chunk!\n");
704 		iwl_trans_pcie_dump_regs(trans);
705 		return -ETIMEDOUT;
706 	}
707 
708 	return 0;
709 }
710 
711 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
712 			    const struct fw_desc *section)
713 {
714 	u8 *v_addr;
715 	dma_addr_t p_addr;
716 	u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
717 	int ret = 0;
718 
719 	IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
720 		     section_num);
721 
722 	v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
723 				    GFP_KERNEL | __GFP_NOWARN);
724 	if (!v_addr) {
725 		IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
726 		chunk_sz = PAGE_SIZE;
727 		v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
728 					    &p_addr, GFP_KERNEL);
729 		if (!v_addr)
730 			return -ENOMEM;
731 	}
732 
733 	for (offset = 0; offset < section->len; offset += chunk_sz) {
734 		u32 copy_size, dst_addr;
735 		bool extended_addr = false;
736 
737 		copy_size = min_t(u32, chunk_sz, section->len - offset);
738 		dst_addr = section->offset + offset;
739 
740 		if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
741 		    dst_addr <= IWL_FW_MEM_EXTENDED_END)
742 			extended_addr = true;
743 
744 		if (extended_addr)
745 			iwl_set_bits_prph(trans, LMPM_CHICK,
746 					  LMPM_CHICK_EXTENDED_ADDR_SPACE);
747 
748 		memcpy(v_addr, (const u8 *)section->data + offset, copy_size);
749 		ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
750 						   copy_size);
751 
752 		if (extended_addr)
753 			iwl_clear_bits_prph(trans, LMPM_CHICK,
754 					    LMPM_CHICK_EXTENDED_ADDR_SPACE);
755 
756 		if (ret) {
757 			IWL_ERR(trans,
758 				"Could not load the [%d] uCode section\n",
759 				section_num);
760 			break;
761 		}
762 	}
763 
764 	dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
765 	return ret;
766 }
767 
768 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
769 					   const struct fw_img *image,
770 					   int cpu,
771 					   int *first_ucode_section)
772 {
773 	int shift_param;
774 	int i, ret = 0, sec_num = 0x1;
775 	u32 val, last_read_idx = 0;
776 
777 	if (cpu == 1) {
778 		shift_param = 0;
779 		*first_ucode_section = 0;
780 	} else {
781 		shift_param = 16;
782 		(*first_ucode_section)++;
783 	}
784 
785 	for (i = *first_ucode_section; i < image->num_sec; i++) {
786 		last_read_idx = i;
787 
788 		/*
789 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
790 		 * CPU1 to CPU2.
791 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
792 		 * CPU2 non paged to CPU2 paging sec.
793 		 */
794 		if (!image->sec[i].data ||
795 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
796 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
797 			IWL_DEBUG_FW(trans,
798 				     "Break since Data not valid or Empty section, sec = %d\n",
799 				     i);
800 			break;
801 		}
802 
803 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
804 		if (ret)
805 			return ret;
806 
807 		/* Notify ucode of loaded section number and status */
808 		val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
809 		val = val | (sec_num << shift_param);
810 		iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
811 
812 		sec_num = (sec_num << 1) | 0x1;
813 	}
814 
815 	*first_ucode_section = last_read_idx;
816 
817 	iwl_enable_interrupts(trans);
818 
819 	if (trans->trans_cfg->use_tfh) {
820 		if (cpu == 1)
821 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
822 				       0xFFFF);
823 		else
824 			iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
825 				       0xFFFFFFFF);
826 	} else {
827 		if (cpu == 1)
828 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
829 					   0xFFFF);
830 		else
831 			iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
832 					   0xFFFFFFFF);
833 	}
834 
835 	return 0;
836 }
837 
838 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
839 				      const struct fw_img *image,
840 				      int cpu,
841 				      int *first_ucode_section)
842 {
843 	int i, ret = 0;
844 	u32 last_read_idx = 0;
845 
846 	if (cpu == 1)
847 		*first_ucode_section = 0;
848 	else
849 		(*first_ucode_section)++;
850 
851 	for (i = *first_ucode_section; i < image->num_sec; i++) {
852 		last_read_idx = i;
853 
854 		/*
855 		 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
856 		 * CPU1 to CPU2.
857 		 * PAGING_SEPARATOR_SECTION delimiter - separate between
858 		 * CPU2 non paged to CPU2 paging sec.
859 		 */
860 		if (!image->sec[i].data ||
861 		    image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
862 		    image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
863 			IWL_DEBUG_FW(trans,
864 				     "Break since Data not valid or Empty section, sec = %d\n",
865 				     i);
866 			break;
867 		}
868 
869 		ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
870 		if (ret)
871 			return ret;
872 	}
873 
874 	*first_ucode_section = last_read_idx;
875 
876 	return 0;
877 }
878 
879 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans)
880 {
881 	enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
882 	struct iwl_fw_ini_allocation_tlv *fw_mon_cfg =
883 		&trans->dbg.fw_mon_cfg[alloc_id];
884 	struct iwl_dram_data *frag;
885 
886 	if (!iwl_trans_dbg_ini_valid(trans))
887 		return;
888 
889 	if (le32_to_cpu(fw_mon_cfg->buf_location) ==
890 	    IWL_FW_INI_LOCATION_SRAM_PATH) {
891 		IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n");
892 		/* set sram monitor by enabling bit 7 */
893 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
894 			    CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM);
895 
896 		return;
897 	}
898 
899 	if (le32_to_cpu(fw_mon_cfg->buf_location) !=
900 	    IWL_FW_INI_LOCATION_DRAM_PATH ||
901 	    !trans->dbg.fw_mon_ini[alloc_id].num_frags)
902 		return;
903 
904 	frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0];
905 
906 	IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n",
907 		     alloc_id);
908 
909 	iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2,
910 			    frag->physical >> MON_BUFF_SHIFT_VER2);
911 	iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2,
912 			    (frag->physical + frag->size - 256) >>
913 			    MON_BUFF_SHIFT_VER2);
914 }
915 
916 void iwl_pcie_apply_destination(struct iwl_trans *trans)
917 {
918 	const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv;
919 	const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
920 	int i;
921 
922 	if (iwl_trans_dbg_ini_valid(trans)) {
923 		iwl_pcie_apply_destination_ini(trans);
924 		return;
925 	}
926 
927 	IWL_INFO(trans, "Applying debug destination %s\n",
928 		 get_fw_dbg_mode_string(dest->monitor_mode));
929 
930 	if (dest->monitor_mode == EXTERNAL_MODE)
931 		iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
932 	else
933 		IWL_WARN(trans, "PCI should have external buffer debug\n");
934 
935 	for (i = 0; i < trans->dbg.n_dest_reg; i++) {
936 		u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
937 		u32 val = le32_to_cpu(dest->reg_ops[i].val);
938 
939 		switch (dest->reg_ops[i].op) {
940 		case CSR_ASSIGN:
941 			iwl_write32(trans, addr, val);
942 			break;
943 		case CSR_SETBIT:
944 			iwl_set_bit(trans, addr, BIT(val));
945 			break;
946 		case CSR_CLEARBIT:
947 			iwl_clear_bit(trans, addr, BIT(val));
948 			break;
949 		case PRPH_ASSIGN:
950 			iwl_write_prph(trans, addr, val);
951 			break;
952 		case PRPH_SETBIT:
953 			iwl_set_bits_prph(trans, addr, BIT(val));
954 			break;
955 		case PRPH_CLEARBIT:
956 			iwl_clear_bits_prph(trans, addr, BIT(val));
957 			break;
958 		case PRPH_BLOCKBIT:
959 			if (iwl_read_prph(trans, addr) & BIT(val)) {
960 				IWL_ERR(trans,
961 					"BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
962 					val, addr);
963 				goto monitor;
964 			}
965 			break;
966 		default:
967 			IWL_ERR(trans, "FW debug - unknown OP %d\n",
968 				dest->reg_ops[i].op);
969 			break;
970 		}
971 	}
972 
973 monitor:
974 	if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) {
975 		iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
976 			       fw_mon->physical >> dest->base_shift);
977 		if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
978 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
979 				       (fw_mon->physical + fw_mon->size -
980 					256) >> dest->end_shift);
981 		else
982 			iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
983 				       (fw_mon->physical + fw_mon->size) >>
984 				       dest->end_shift);
985 	}
986 }
987 
988 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
989 				const struct fw_img *image)
990 {
991 	int ret = 0;
992 	int first_ucode_section;
993 
994 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
995 		     image->is_dual_cpus ? "Dual" : "Single");
996 
997 	/* load to FW the binary non secured sections of CPU1 */
998 	ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
999 	if (ret)
1000 		return ret;
1001 
1002 	if (image->is_dual_cpus) {
1003 		/* set CPU2 header address */
1004 		iwl_write_prph(trans,
1005 			       LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1006 			       LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1007 
1008 		/* load to FW the binary sections of CPU2 */
1009 		ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1010 						 &first_ucode_section);
1011 		if (ret)
1012 			return ret;
1013 	}
1014 
1015 	if (iwl_pcie_dbg_on(trans))
1016 		iwl_pcie_apply_destination(trans);
1017 
1018 	iwl_enable_interrupts(trans);
1019 
1020 	/* release CPU reset */
1021 	iwl_write32(trans, CSR_RESET, 0);
1022 
1023 	return 0;
1024 }
1025 
1026 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1027 					  const struct fw_img *image)
1028 {
1029 	int ret = 0;
1030 	int first_ucode_section;
1031 
1032 	IWL_DEBUG_FW(trans, "working with %s CPU\n",
1033 		     image->is_dual_cpus ? "Dual" : "Single");
1034 
1035 	if (iwl_pcie_dbg_on(trans))
1036 		iwl_pcie_apply_destination(trans);
1037 
1038 	IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1039 			iwl_read_prph(trans, WFPM_GP2));
1040 
1041 	/*
1042 	 * Set default value. On resume reading the values that were
1043 	 * zeored can provide debug data on the resume flow.
1044 	 * This is for debugging only and has no functional impact.
1045 	 */
1046 	iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1047 
1048 	/* configure the ucode to be ready to get the secured image */
1049 	/* release CPU reset */
1050 	iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1051 
1052 	/* load to FW the binary Secured sections of CPU1 */
1053 	ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1054 					      &first_ucode_section);
1055 	if (ret)
1056 		return ret;
1057 
1058 	/* load to FW the binary sections of CPU2 */
1059 	return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1060 					       &first_ucode_section);
1061 }
1062 
1063 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1064 {
1065 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1066 	bool hw_rfkill = iwl_is_rfkill_set(trans);
1067 	bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1068 	bool report;
1069 
1070 	if (hw_rfkill) {
1071 		set_bit(STATUS_RFKILL_HW, &trans->status);
1072 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1073 	} else {
1074 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1075 		if (trans_pcie->opmode_down)
1076 			clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1077 	}
1078 
1079 	report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1080 
1081 	if (prev != report)
1082 		iwl_trans_pcie_rf_kill(trans, report);
1083 
1084 	return hw_rfkill;
1085 }
1086 
1087 struct iwl_causes_list {
1088 	u32 cause_num;
1089 	u32 mask_reg;
1090 	u8 addr;
1091 };
1092 
1093 static const struct iwl_causes_list causes_list_common[] = {
1094 	{MSIX_FH_INT_CAUSES_D2S_CH0_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0},
1095 	{MSIX_FH_INT_CAUSES_D2S_CH1_NUM,	CSR_MSIX_FH_INT_MASK_AD, 0x1},
1096 	{MSIX_FH_INT_CAUSES_S2D,		CSR_MSIX_FH_INT_MASK_AD, 0x3},
1097 	{MSIX_FH_INT_CAUSES_FH_ERR,		CSR_MSIX_FH_INT_MASK_AD, 0x5},
1098 	{MSIX_HW_INT_CAUSES_REG_ALIVE,		CSR_MSIX_HW_INT_MASK_AD, 0x10},
1099 	{MSIX_HW_INT_CAUSES_REG_WAKEUP,		CSR_MSIX_HW_INT_MASK_AD, 0x11},
1100 	{MSIX_HW_INT_CAUSES_REG_RESET_DONE,	CSR_MSIX_HW_INT_MASK_AD, 0x12},
1101 	{MSIX_HW_INT_CAUSES_REG_CT_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x16},
1102 	{MSIX_HW_INT_CAUSES_REG_RF_KILL,	CSR_MSIX_HW_INT_MASK_AD, 0x17},
1103 	{MSIX_HW_INT_CAUSES_REG_PERIODIC,	CSR_MSIX_HW_INT_MASK_AD, 0x18},
1104 	{MSIX_HW_INT_CAUSES_REG_SCD,		CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1105 	{MSIX_HW_INT_CAUSES_REG_FH_TX,		CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1106 	{MSIX_HW_INT_CAUSES_REG_HW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1107 	{MSIX_HW_INT_CAUSES_REG_HAP,		CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1108 };
1109 
1110 static const struct iwl_causes_list causes_list_pre_bz[] = {
1111 	{MSIX_HW_INT_CAUSES_REG_SW_ERR,		CSR_MSIX_HW_INT_MASK_AD, 0x29},
1112 };
1113 
1114 static const struct iwl_causes_list causes_list_bz[] = {
1115 	{MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ,	CSR_MSIX_HW_INT_MASK_AD, 0x15},
1116 };
1117 
1118 static void iwl_pcie_map_list(struct iwl_trans *trans,
1119 			      const struct iwl_causes_list *causes,
1120 			      int arr_size, int val)
1121 {
1122 	int i;
1123 
1124 	for (i = 0; i < arr_size; i++) {
1125 		iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1126 		iwl_clear_bit(trans, causes[i].mask_reg,
1127 			      causes[i].cause_num);
1128 	}
1129 }
1130 
1131 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1132 {
1133 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1134 	int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1135 	/*
1136 	 * Access all non RX causes and map them to the default irq.
1137 	 * In case we are missing at least one interrupt vector,
1138 	 * the first interrupt vector will serve non-RX and FBQ causes.
1139 	 */
1140 	iwl_pcie_map_list(trans, causes_list_common,
1141 			  ARRAY_SIZE(causes_list_common), val);
1142 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1143 		iwl_pcie_map_list(trans, causes_list_bz,
1144 				  ARRAY_SIZE(causes_list_bz), val);
1145 	else
1146 		iwl_pcie_map_list(trans, causes_list_pre_bz,
1147 				  ARRAY_SIZE(causes_list_pre_bz), val);
1148 }
1149 
1150 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1151 {
1152 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1153 	u32 offset =
1154 		trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1155 	u32 val, idx;
1156 
1157 	/*
1158 	 * The first RX queue - fallback queue, which is designated for
1159 	 * management frame, command responses etc, is always mapped to the
1160 	 * first interrupt vector. The other RX queues are mapped to
1161 	 * the other (N - 2) interrupt vectors.
1162 	 */
1163 	val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1164 	for (idx = 1; idx < trans->num_rx_queues; idx++) {
1165 		iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1166 			   MSIX_FH_INT_CAUSES_Q(idx - offset));
1167 		val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1168 	}
1169 	iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1170 
1171 	val = MSIX_FH_INT_CAUSES_Q(0);
1172 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1173 		val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1174 	iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1175 
1176 	if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1177 		iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1178 }
1179 
1180 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1181 {
1182 	struct iwl_trans *trans = trans_pcie->trans;
1183 
1184 	if (!trans_pcie->msix_enabled) {
1185 		if (trans->trans_cfg->mq_rx_supported &&
1186 		    test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1187 			iwl_write_umac_prph(trans, UREG_CHICK,
1188 					    UREG_CHICK_MSI_ENABLE);
1189 		return;
1190 	}
1191 	/*
1192 	 * The IVAR table needs to be configured again after reset,
1193 	 * but if the device is disabled, we can't write to
1194 	 * prph.
1195 	 */
1196 	if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1197 		iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1198 
1199 	/*
1200 	 * Each cause from the causes list above and the RX causes is
1201 	 * represented as a byte in the IVAR table. The first nibble
1202 	 * represents the bound interrupt vector of the cause, the second
1203 	 * represents no auto clear for this cause. This will be set if its
1204 	 * interrupt vector is bound to serve other causes.
1205 	 */
1206 	iwl_pcie_map_rx_causes(trans);
1207 
1208 	iwl_pcie_map_non_rx_causes(trans);
1209 }
1210 
1211 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1212 {
1213 	struct iwl_trans *trans = trans_pcie->trans;
1214 
1215 	iwl_pcie_conf_msix_hw(trans_pcie);
1216 
1217 	if (!trans_pcie->msix_enabled)
1218 		return;
1219 
1220 	trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1221 	trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1222 	trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1223 	trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1224 }
1225 
1226 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1227 {
1228 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1229 
1230 	lockdep_assert_held(&trans_pcie->mutex);
1231 
1232 	if (trans_pcie->is_down)
1233 		return;
1234 
1235 	trans_pcie->is_down = true;
1236 
1237 	/* tell the device to stop sending interrupts */
1238 	iwl_disable_interrupts(trans);
1239 
1240 	/* device going down, Stop using ICT table */
1241 	iwl_pcie_disable_ict(trans);
1242 
1243 	/*
1244 	 * If a HW restart happens during firmware loading,
1245 	 * then the firmware loading might call this function
1246 	 * and later it might be called again due to the
1247 	 * restart. So don't process again if the device is
1248 	 * already dead.
1249 	 */
1250 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1251 		IWL_DEBUG_INFO(trans,
1252 			       "DEVICE_ENABLED bit was set and is now cleared\n");
1253 		iwl_pcie_tx_stop(trans);
1254 		iwl_pcie_rx_stop(trans);
1255 
1256 		/* Power-down device's busmaster DMA clocks */
1257 		if (!trans->cfg->apmg_not_supported) {
1258 			iwl_write_prph(trans, APMG_CLK_DIS_REG,
1259 				       APMG_CLK_VAL_DMA_CLK_RQT);
1260 			udelay(5);
1261 		}
1262 	}
1263 
1264 	/* Make sure (redundant) we've released our request to stay awake */
1265 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
1266 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1267 			      CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
1268 	else
1269 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1270 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1271 
1272 	/* Stop the device, and put it in low power state */
1273 	iwl_pcie_apm_stop(trans, false);
1274 
1275 	/* re-take ownership to prevent other users from stealing the device */
1276 	iwl_trans_pcie_sw_reset(trans, true);
1277 
1278 	/*
1279 	 * Upon stop, the IVAR table gets erased, so msi-x won't
1280 	 * work. This causes a bug in RF-KILL flows, since the interrupt
1281 	 * that enables radio won't fire on the correct irq, and the
1282 	 * driver won't be able to handle the interrupt.
1283 	 * Configure the IVAR table again after reset.
1284 	 */
1285 	iwl_pcie_conf_msix_hw(trans_pcie);
1286 
1287 	/*
1288 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1289 	 * This is a bug in certain verions of the hardware.
1290 	 * Certain devices also keep sending HW RF kill interrupt all
1291 	 * the time, unless the interrupt is ACKed even if the interrupt
1292 	 * should be masked. Re-ACK all the interrupts here.
1293 	 */
1294 	iwl_disable_interrupts(trans);
1295 
1296 	/* clear all status bits */
1297 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1298 	clear_bit(STATUS_INT_ENABLED, &trans->status);
1299 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
1300 
1301 	/*
1302 	 * Even if we stop the HW, we still want the RF kill
1303 	 * interrupt
1304 	 */
1305 	iwl_enable_rfkill_int(trans);
1306 }
1307 
1308 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1309 {
1310 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1311 
1312 	if (trans_pcie->msix_enabled) {
1313 		int i;
1314 
1315 		for (i = 0; i < trans_pcie->alloc_vecs; i++)
1316 			synchronize_irq(trans_pcie->msix_entries[i].vector);
1317 	} else {
1318 		synchronize_irq(trans_pcie->pci_dev->irq);
1319 	}
1320 }
1321 
1322 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1323 				   const struct fw_img *fw, bool run_in_rfkill)
1324 {
1325 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1326 	bool hw_rfkill;
1327 	int ret;
1328 
1329 	/* This may fail if AMT took ownership of the device */
1330 	if (iwl_pcie_prepare_card_hw(trans)) {
1331 		IWL_WARN(trans, "Exit HW not ready\n");
1332 		return -EIO;
1333 	}
1334 
1335 	iwl_enable_rfkill_int(trans);
1336 
1337 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1338 
1339 	/*
1340 	 * We enabled the RF-Kill interrupt and the handler may very
1341 	 * well be running. Disable the interrupts to make sure no other
1342 	 * interrupt can be fired.
1343 	 */
1344 	iwl_disable_interrupts(trans);
1345 
1346 	/* Make sure it finished running */
1347 	iwl_pcie_synchronize_irqs(trans);
1348 
1349 	mutex_lock(&trans_pcie->mutex);
1350 
1351 	/* If platform's RF_KILL switch is NOT set to KILL */
1352 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1353 	if (hw_rfkill && !run_in_rfkill) {
1354 		ret = -ERFKILL;
1355 		goto out;
1356 	}
1357 
1358 	/* Someone called stop_device, don't try to start_fw */
1359 	if (trans_pcie->is_down) {
1360 		IWL_WARN(trans,
1361 			 "Can't start_fw since the HW hasn't been started\n");
1362 		ret = -EIO;
1363 		goto out;
1364 	}
1365 
1366 	/* make sure rfkill handshake bits are cleared */
1367 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1368 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1369 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1370 
1371 	/* clear (again), then enable host interrupts */
1372 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1373 
1374 	ret = iwl_pcie_nic_init(trans);
1375 	if (ret) {
1376 		IWL_ERR(trans, "Unable to init nic\n");
1377 		goto out;
1378 	}
1379 
1380 	/*
1381 	 * Now, we load the firmware and don't want to be interrupted, even
1382 	 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1383 	 * FH_TX interrupt which is needed to load the firmware). If the
1384 	 * RF-Kill switch is toggled, we will find out after having loaded
1385 	 * the firmware and return the proper value to the caller.
1386 	 */
1387 	iwl_enable_fw_load_int(trans);
1388 
1389 	/* really make sure rfkill handshake bits are cleared */
1390 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1391 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1392 
1393 	/* Load the given image to the HW */
1394 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1395 		ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1396 	else
1397 		ret = iwl_pcie_load_given_ucode(trans, fw);
1398 
1399 	/* re-check RF-Kill state since we may have missed the interrupt */
1400 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1401 	if (hw_rfkill && !run_in_rfkill)
1402 		ret = -ERFKILL;
1403 
1404 out:
1405 	mutex_unlock(&trans_pcie->mutex);
1406 	return ret;
1407 }
1408 
1409 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1410 {
1411 	iwl_pcie_reset_ict(trans);
1412 	iwl_pcie_tx_start(trans, scd_addr);
1413 }
1414 
1415 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1416 				       bool was_in_rfkill)
1417 {
1418 	bool hw_rfkill;
1419 
1420 	/*
1421 	 * Check again since the RF kill state may have changed while
1422 	 * all the interrupts were disabled, in this case we couldn't
1423 	 * receive the RF kill interrupt and update the state in the
1424 	 * op_mode.
1425 	 * Don't call the op_mode if the rkfill state hasn't changed.
1426 	 * This allows the op_mode to call stop_device from the rfkill
1427 	 * notification without endless recursion. Under very rare
1428 	 * circumstances, we might have a small recursion if the rfkill
1429 	 * state changed exactly now while we were called from stop_device.
1430 	 * This is very unlikely but can happen and is supported.
1431 	 */
1432 	hw_rfkill = iwl_is_rfkill_set(trans);
1433 	if (hw_rfkill) {
1434 		set_bit(STATUS_RFKILL_HW, &trans->status);
1435 		set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1436 	} else {
1437 		clear_bit(STATUS_RFKILL_HW, &trans->status);
1438 		clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1439 	}
1440 	if (hw_rfkill != was_in_rfkill)
1441 		iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1442 }
1443 
1444 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1445 {
1446 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1447 	bool was_in_rfkill;
1448 
1449 	iwl_op_mode_time_point(trans->op_mode,
1450 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
1451 			       NULL);
1452 
1453 	mutex_lock(&trans_pcie->mutex);
1454 	trans_pcie->opmode_down = true;
1455 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1456 	_iwl_trans_pcie_stop_device(trans);
1457 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1458 	mutex_unlock(&trans_pcie->mutex);
1459 }
1460 
1461 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1462 {
1463 	struct iwl_trans_pcie __maybe_unused *trans_pcie =
1464 		IWL_TRANS_GET_PCIE_TRANS(trans);
1465 
1466 	lockdep_assert_held(&trans_pcie->mutex);
1467 
1468 	IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1469 		 state ? "disabled" : "enabled");
1470 	if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1471 		if (trans->trans_cfg->gen2)
1472 			_iwl_trans_pcie_gen2_stop_device(trans);
1473 		else
1474 			_iwl_trans_pcie_stop_device(trans);
1475 	}
1476 }
1477 
1478 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans,
1479 				  bool test, bool reset)
1480 {
1481 	iwl_disable_interrupts(trans);
1482 
1483 	/*
1484 	 * in testing mode, the host stays awake and the
1485 	 * hardware won't be reset (not even partially)
1486 	 */
1487 	if (test)
1488 		return;
1489 
1490 	iwl_pcie_disable_ict(trans);
1491 
1492 	iwl_pcie_synchronize_irqs(trans);
1493 
1494 	iwl_clear_bit(trans, CSR_GP_CNTRL,
1495 		      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1496 	iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1497 
1498 	if (reset) {
1499 		/*
1500 		 * reset TX queues -- some of their registers reset during S3
1501 		 * so if we don't reset everything here the D3 image would try
1502 		 * to execute some invalid memory upon resume
1503 		 */
1504 		iwl_trans_pcie_tx_reset(trans);
1505 	}
1506 
1507 	iwl_pcie_set_pwr(trans, true);
1508 }
1509 
1510 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend)
1511 {
1512 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1513 	int ret;
1514 
1515 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
1516 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1517 				    suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND :
1518 					      UREG_DOORBELL_TO_ISR6_RESUME);
1519 	} else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
1520 		iwl_write32(trans, CSR_IPC_SLEEP_CONTROL,
1521 			    suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND :
1522 				      CSR_IPC_SLEEP_CONTROL_RESUME);
1523 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
1524 				    UREG_DOORBELL_TO_ISR6_SLEEP_CTRL);
1525 	} else {
1526 		return 0;
1527 	}
1528 
1529 	ret = wait_event_timeout(trans_pcie->sx_waitq,
1530 				 trans_pcie->sx_complete, 2 * HZ);
1531 
1532 	/* Invalidate it toward next suspend or resume */
1533 	trans_pcie->sx_complete = false;
1534 
1535 	if (!ret) {
1536 		IWL_ERR(trans, "Timeout %s D3\n",
1537 			suspend ? "entering" : "exiting");
1538 		return -ETIMEDOUT;
1539 	}
1540 
1541 	return 0;
1542 }
1543 
1544 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1545 				     bool reset)
1546 {
1547 	int ret;
1548 
1549 	if (!reset)
1550 		/* Enable persistence mode to avoid reset */
1551 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1552 			    CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1553 
1554 	ret = iwl_pcie_d3_handshake(trans, true);
1555 	if (ret)
1556 		return ret;
1557 
1558 	iwl_pcie_d3_complete_suspend(trans, test, reset);
1559 
1560 	return 0;
1561 }
1562 
1563 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1564 				    enum iwl_d3_status *status,
1565 				    bool test,  bool reset)
1566 {
1567 	struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1568 	u32 val;
1569 	int ret;
1570 
1571 	if (test) {
1572 		iwl_enable_interrupts(trans);
1573 		*status = IWL_D3_STATUS_ALIVE;
1574 		ret = 0;
1575 		goto out;
1576 	}
1577 
1578 	iwl_set_bit(trans, CSR_GP_CNTRL,
1579 		    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1580 
1581 	ret = iwl_finish_nic_init(trans);
1582 	if (ret)
1583 		return ret;
1584 
1585 	/*
1586 	 * Reconfigure IVAR table in case of MSIX or reset ict table in
1587 	 * MSI mode since HW reset erased it.
1588 	 * Also enables interrupts - none will happen as
1589 	 * the device doesn't know we're waking it up, only when
1590 	 * the opmode actually tells it after this call.
1591 	 */
1592 	iwl_pcie_conf_msix_hw(trans_pcie);
1593 	if (!trans_pcie->msix_enabled)
1594 		iwl_pcie_reset_ict(trans);
1595 	iwl_enable_interrupts(trans);
1596 
1597 	iwl_pcie_set_pwr(trans, false);
1598 
1599 	if (!reset) {
1600 		iwl_clear_bit(trans, CSR_GP_CNTRL,
1601 			      CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1602 	} else {
1603 		iwl_trans_pcie_tx_reset(trans);
1604 
1605 		ret = iwl_pcie_rx_init(trans);
1606 		if (ret) {
1607 			IWL_ERR(trans,
1608 				"Failed to resume the device (RX reset)\n");
1609 			return ret;
1610 		}
1611 	}
1612 
1613 	IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1614 			iwl_read_umac_prph(trans, WFPM_GP2));
1615 
1616 	val = iwl_read32(trans, CSR_RESET);
1617 	if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1618 		*status = IWL_D3_STATUS_RESET;
1619 	else
1620 		*status = IWL_D3_STATUS_ALIVE;
1621 
1622 out:
1623 	if (*status == IWL_D3_STATUS_ALIVE)
1624 		ret = iwl_pcie_d3_handshake(trans, false);
1625 
1626 	return ret;
1627 }
1628 
1629 static void
1630 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1631 			    struct iwl_trans *trans,
1632 			    const struct iwl_cfg_trans_params *cfg_trans)
1633 {
1634 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1635 	int max_irqs, num_irqs, i, ret;
1636 	u16 pci_cmd;
1637 	u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES;
1638 
1639 	if (!cfg_trans->mq_rx_supported)
1640 		goto enable_msi;
1641 
1642 	if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000)
1643 		max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES;
1644 
1645 	max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues);
1646 	for (i = 0; i < max_irqs; i++)
1647 		trans_pcie->msix_entries[i].entry = i;
1648 
1649 	num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1650 					 MSIX_MIN_INTERRUPT_VECTORS,
1651 					 max_irqs);
1652 	if (num_irqs < 0) {
1653 		IWL_DEBUG_INFO(trans,
1654 			       "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1655 			       num_irqs);
1656 		goto enable_msi;
1657 	}
1658 	trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1659 
1660 	IWL_DEBUG_INFO(trans,
1661 		       "MSI-X enabled. %d interrupt vectors were allocated\n",
1662 		       num_irqs);
1663 
1664 	/*
1665 	 * In case the OS provides fewer interrupts than requested, different
1666 	 * causes will share the same interrupt vector as follows:
1667 	 * One interrupt less: non rx causes shared with FBQ.
1668 	 * Two interrupts less: non rx causes shared with FBQ and RSS.
1669 	 * More than two interrupts: we will use fewer RSS queues.
1670 	 */
1671 	if (num_irqs <= max_irqs - 2) {
1672 		trans_pcie->trans->num_rx_queues = num_irqs + 1;
1673 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1674 			IWL_SHARED_IRQ_FIRST_RSS;
1675 	} else if (num_irqs == max_irqs - 1) {
1676 		trans_pcie->trans->num_rx_queues = num_irqs;
1677 		trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1678 	} else {
1679 		trans_pcie->trans->num_rx_queues = num_irqs - 1;
1680 	}
1681 
1682 	IWL_DEBUG_INFO(trans,
1683 		       "MSI-X enabled with rx queues %d, vec mask 0x%x\n",
1684 		       trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask);
1685 
1686 	WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1687 
1688 	trans_pcie->alloc_vecs = num_irqs;
1689 	trans_pcie->msix_enabled = true;
1690 	return;
1691 
1692 enable_msi:
1693 	ret = pci_enable_msi(pdev);
1694 	if (ret) {
1695 		dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1696 		/* enable rfkill interrupt: hw bug w/a */
1697 		pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1698 		if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1699 			pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1700 			pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1701 		}
1702 	}
1703 }
1704 
1705 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1706 {
1707 	int iter_rx_q, i, ret, cpu, offset;
1708 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1709 
1710 	i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1711 	iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1712 	offset = 1 + i;
1713 	for (; i < iter_rx_q ; i++) {
1714 		/*
1715 		 * Get the cpu prior to the place to search
1716 		 * (i.e. return will be > i - 1).
1717 		 */
1718 		cpu = cpumask_next(i - offset, cpu_online_mask);
1719 		cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1720 		ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1721 					    &trans_pcie->affinity_mask[i]);
1722 		if (ret)
1723 			IWL_ERR(trans_pcie->trans,
1724 				"Failed to set affinity mask for IRQ %d\n",
1725 				trans_pcie->msix_entries[i].vector);
1726 	}
1727 }
1728 
1729 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1730 				      struct iwl_trans_pcie *trans_pcie)
1731 {
1732 	int i;
1733 
1734 	for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1735 		int ret;
1736 		struct msix_entry *msix_entry;
1737 		const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1738 
1739 		if (!qname)
1740 			return -ENOMEM;
1741 
1742 		msix_entry = &trans_pcie->msix_entries[i];
1743 		ret = devm_request_threaded_irq(&pdev->dev,
1744 						msix_entry->vector,
1745 						iwl_pcie_msix_isr,
1746 						(i == trans_pcie->def_irq) ?
1747 						iwl_pcie_irq_msix_handler :
1748 						iwl_pcie_irq_rx_msix_handler,
1749 						IRQF_SHARED,
1750 						qname,
1751 						msix_entry);
1752 		if (ret) {
1753 			IWL_ERR(trans_pcie->trans,
1754 				"Error allocating IRQ %d\n", i);
1755 
1756 			return ret;
1757 		}
1758 	}
1759 	iwl_pcie_irq_set_affinity(trans_pcie->trans);
1760 
1761 	return 0;
1762 }
1763 
1764 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans)
1765 {
1766 	u32 hpm, wprot;
1767 
1768 	switch (trans->trans_cfg->device_family) {
1769 	case IWL_DEVICE_FAMILY_9000:
1770 		wprot = PREG_PRPH_WPROT_9000;
1771 		break;
1772 	case IWL_DEVICE_FAMILY_22000:
1773 		wprot = PREG_PRPH_WPROT_22000;
1774 		break;
1775 	default:
1776 		return 0;
1777 	}
1778 
1779 	hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1780 	if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1781 		u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1782 
1783 		if (wprot_val & PREG_WFPM_ACCESS) {
1784 			IWL_ERR(trans,
1785 				"Error, can not clear persistence bit\n");
1786 			return -EPERM;
1787 		}
1788 		iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,
1789 					    hpm & ~PERSISTENCE_BIT);
1790 	}
1791 
1792 	return 0;
1793 }
1794 
1795 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1796 {
1797 	int ret;
1798 
1799 	ret = iwl_finish_nic_init(trans);
1800 	if (ret < 0)
1801 		return ret;
1802 
1803 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1804 			  HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1805 	udelay(20);
1806 	iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1807 			  HPM_HIPM_GEN_CFG_CR_PG_EN |
1808 			  HPM_HIPM_GEN_CFG_CR_SLP_EN);
1809 	udelay(20);
1810 	iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG,
1811 			    HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1812 
1813 	return iwl_trans_pcie_sw_reset(trans, true);
1814 }
1815 
1816 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1817 {
1818 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1819 	int err;
1820 
1821 	lockdep_assert_held(&trans_pcie->mutex);
1822 
1823 	err = iwl_pcie_prepare_card_hw(trans);
1824 	if (err) {
1825 		IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1826 		return err;
1827 	}
1828 
1829 	err = iwl_trans_pcie_clear_persistence_bit(trans);
1830 	if (err)
1831 		return err;
1832 
1833 	err = iwl_trans_pcie_sw_reset(trans, true);
1834 	if (err)
1835 		return err;
1836 
1837 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1838 	    trans->trans_cfg->integrated) {
1839 		err = iwl_pcie_gen2_force_power_gating(trans);
1840 		if (err)
1841 			return err;
1842 	}
1843 
1844 	err = iwl_pcie_apm_init(trans);
1845 	if (err)
1846 		return err;
1847 
1848 	iwl_pcie_init_msix(trans_pcie);
1849 
1850 	/* From now on, the op_mode will be kept updated about RF kill state */
1851 	iwl_enable_rfkill_int(trans);
1852 
1853 	trans_pcie->opmode_down = false;
1854 
1855 	/* Set is_down to false here so that...*/
1856 	trans_pcie->is_down = false;
1857 
1858 	/* ...rfkill can call stop_device and set it false if needed */
1859 	iwl_pcie_check_hw_rf_kill(trans);
1860 
1861 	return 0;
1862 }
1863 
1864 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1865 {
1866 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1867 	int ret;
1868 
1869 	mutex_lock(&trans_pcie->mutex);
1870 	ret = _iwl_trans_pcie_start_hw(trans);
1871 	mutex_unlock(&trans_pcie->mutex);
1872 
1873 	return ret;
1874 }
1875 
1876 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1877 {
1878 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1879 
1880 	mutex_lock(&trans_pcie->mutex);
1881 
1882 	/* disable interrupts - don't enable HW RF kill interrupt */
1883 	iwl_disable_interrupts(trans);
1884 
1885 	iwl_pcie_apm_stop(trans, true);
1886 
1887 	iwl_disable_interrupts(trans);
1888 
1889 	iwl_pcie_disable_ict(trans);
1890 
1891 	mutex_unlock(&trans_pcie->mutex);
1892 
1893 	iwl_pcie_synchronize_irqs(trans);
1894 }
1895 
1896 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1897 {
1898 	writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1899 }
1900 
1901 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1902 {
1903 	writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1904 }
1905 
1906 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1907 {
1908 	return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1909 }
1910 
1911 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1912 {
1913 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1914 		return 0x00FFFFFF;
1915 	else
1916 		return 0x000FFFFF;
1917 }
1918 
1919 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1920 {
1921 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1922 
1923 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1924 			       ((reg & mask) | (3 << 24)));
1925 	return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1926 }
1927 
1928 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1929 				      u32 val)
1930 {
1931 	u32 mask = iwl_trans_pcie_prph_msk(trans);
1932 
1933 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1934 			       ((addr & mask) | (3 << 24)));
1935 	iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1936 }
1937 
1938 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1939 				     const struct iwl_trans_config *trans_cfg)
1940 {
1941 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1942 
1943 	/* free all first - we might be reconfigured for a different size */
1944 	iwl_pcie_free_rbs_pool(trans);
1945 
1946 	trans->txqs.cmd.q_id = trans_cfg->cmd_queue;
1947 	trans->txqs.cmd.fifo = trans_cfg->cmd_fifo;
1948 	trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1949 	trans->txqs.page_offs = trans_cfg->cb_data_offs;
1950 	trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1951 	trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver;
1952 
1953 	if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1954 		trans_pcie->n_no_reclaim_cmds = 0;
1955 	else
1956 		trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1957 	if (trans_pcie->n_no_reclaim_cmds)
1958 		memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1959 		       trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1960 
1961 	trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1962 	trans_pcie->rx_page_order =
1963 		iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1964 	trans_pcie->rx_buf_bytes =
1965 		iwl_trans_get_rb_size(trans_pcie->rx_buf_size);
1966 	trans_pcie->supported_dma_mask = DMA_BIT_MASK(12);
1967 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
1968 		trans_pcie->supported_dma_mask = DMA_BIT_MASK(11);
1969 
1970 	trans->txqs.bc_table_dword = trans_cfg->bc_table_dword;
1971 	trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1972 
1973 	trans->command_groups = trans_cfg->command_groups;
1974 	trans->command_groups_size = trans_cfg->command_groups_size;
1975 
1976 	/* Initialize NAPI here - it should be before registering to mac80211
1977 	 * in the opmode but after the HW struct is allocated.
1978 	 * As this function may be called again in some corner cases don't
1979 	 * do anything if NAPI was already initialized.
1980 	 */
1981 	if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1982 		init_dummy_netdev(&trans_pcie->napi_dev);
1983 
1984 	trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1985 }
1986 
1987 void iwl_trans_pcie_free(struct iwl_trans *trans)
1988 {
1989 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1990 	int i;
1991 
1992 	iwl_pcie_synchronize_irqs(trans);
1993 
1994 	if (trans->trans_cfg->gen2)
1995 		iwl_txq_gen2_tx_free(trans);
1996 	else
1997 		iwl_pcie_tx_free(trans);
1998 	iwl_pcie_rx_free(trans);
1999 
2000 	if (trans_pcie->rba.alloc_wq) {
2001 		destroy_workqueue(trans_pcie->rba.alloc_wq);
2002 		trans_pcie->rba.alloc_wq = NULL;
2003 	}
2004 
2005 	if (trans_pcie->msix_enabled) {
2006 		for (i = 0; i < trans_pcie->alloc_vecs; i++) {
2007 			irq_set_affinity_hint(
2008 				trans_pcie->msix_entries[i].vector,
2009 				NULL);
2010 		}
2011 
2012 		trans_pcie->msix_enabled = false;
2013 	} else {
2014 		iwl_pcie_free_ict(trans);
2015 	}
2016 
2017 	iwl_pcie_free_fw_monitor(trans);
2018 
2019 	if (trans_pcie->pnvm_dram.size)
2020 		dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
2021 				  trans_pcie->pnvm_dram.block,
2022 				  trans_pcie->pnvm_dram.physical);
2023 
2024 	if (trans_pcie->reduce_power_dram.size)
2025 		dma_free_coherent(trans->dev,
2026 				  trans_pcie->reduce_power_dram.size,
2027 				  trans_pcie->reduce_power_dram.block,
2028 				  trans_pcie->reduce_power_dram.physical);
2029 
2030 	mutex_destroy(&trans_pcie->mutex);
2031 	iwl_trans_free(trans);
2032 }
2033 
2034 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2035 {
2036 	if (state)
2037 		set_bit(STATUS_TPOWER_PMI, &trans->status);
2038 	else
2039 		clear_bit(STATUS_TPOWER_PMI, &trans->status);
2040 }
2041 
2042 struct iwl_trans_pcie_removal {
2043 	struct pci_dev *pdev;
2044 	struct work_struct work;
2045 };
2046 
2047 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
2048 {
2049 	struct iwl_trans_pcie_removal *removal =
2050 		container_of(wk, struct iwl_trans_pcie_removal, work);
2051 	struct pci_dev *pdev = removal->pdev;
2052 	static char *prop[] = {"EVENT=INACCESSIBLE", NULL};
2053 
2054 	dev_err(&pdev->dev, "Device gone - attempting removal\n");
2055 	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
2056 	pci_lock_rescan_remove();
2057 	pci_dev_put(pdev);
2058 	pci_stop_and_remove_bus_device(pdev);
2059 	pci_unlock_rescan_remove();
2060 
2061 	kfree(removal);
2062 	module_put(THIS_MODULE);
2063 }
2064 
2065 /*
2066  * This version doesn't disable BHs but rather assumes they're
2067  * already disabled.
2068  */
2069 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2070 {
2071 	int ret;
2072 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2073 	u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ;
2074 	u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
2075 		   CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP;
2076 	u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN;
2077 
2078 	spin_lock(&trans_pcie->reg_lock);
2079 
2080 	if (trans_pcie->cmd_hold_nic_awake)
2081 		goto out;
2082 
2083 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
2084 		write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ;
2085 		mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2086 		poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS;
2087 	}
2088 
2089 	/* this bit wakes up the NIC */
2090 	__iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write);
2091 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2092 		udelay(2);
2093 
2094 	/*
2095 	 * These bits say the device is running, and should keep running for
2096 	 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2097 	 * but they do not indicate that embedded SRAM is restored yet;
2098 	 * HW with volatile SRAM must save/restore contents to/from
2099 	 * host DRAM when sleeping/waking for power-saving.
2100 	 * Each direction takes approximately 1/4 millisecond; with this
2101 	 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2102 	 * series of register accesses are expected (e.g. reading Event Log),
2103 	 * to keep device from sleeping.
2104 	 *
2105 	 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2106 	 * SRAM is okay/restored.  We don't check that here because this call
2107 	 * is just for hardware register access; but GP1 MAC_SLEEP
2108 	 * check is a good idea before accessing the SRAM of HW with
2109 	 * volatile SRAM (e.g. reading Event Log).
2110 	 *
2111 	 * 5000 series and later (including 1000 series) have non-volatile SRAM,
2112 	 * and do not save/restore SRAM when power cycling.
2113 	 */
2114 	ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000);
2115 	if (unlikely(ret < 0)) {
2116 		u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2117 
2118 		WARN_ONCE(1,
2119 			  "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2120 			  cntrl);
2121 
2122 		iwl_trans_pcie_dump_regs(trans);
2123 
2124 		if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2125 			struct iwl_trans_pcie_removal *removal;
2126 
2127 			if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2128 				goto err;
2129 
2130 			IWL_ERR(trans, "Device gone - scheduling removal!\n");
2131 
2132 			/*
2133 			 * get a module reference to avoid doing this
2134 			 * while unloading anyway and to avoid
2135 			 * scheduling a work with code that's being
2136 			 * removed.
2137 			 */
2138 			if (!try_module_get(THIS_MODULE)) {
2139 				IWL_ERR(trans,
2140 					"Module is being unloaded - abort\n");
2141 				goto err;
2142 			}
2143 
2144 			removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2145 			if (!removal) {
2146 				module_put(THIS_MODULE);
2147 				goto err;
2148 			}
2149 			/*
2150 			 * we don't need to clear this flag, because
2151 			 * the trans will be freed and reallocated.
2152 			*/
2153 			set_bit(STATUS_TRANS_DEAD, &trans->status);
2154 
2155 			removal->pdev = to_pci_dev(trans->dev);
2156 			INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2157 			pci_dev_get(removal->pdev);
2158 			schedule_work(&removal->work);
2159 		} else {
2160 			iwl_write32(trans, CSR_RESET,
2161 				    CSR_RESET_REG_FLAG_FORCE_NMI);
2162 		}
2163 
2164 err:
2165 		spin_unlock(&trans_pcie->reg_lock);
2166 		return false;
2167 	}
2168 
2169 out:
2170 	/*
2171 	 * Fool sparse by faking we release the lock - sparse will
2172 	 * track nic_access anyway.
2173 	 */
2174 	__release(&trans_pcie->reg_lock);
2175 	return true;
2176 }
2177 
2178 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans)
2179 {
2180 	bool ret;
2181 
2182 	local_bh_disable();
2183 	ret = __iwl_trans_pcie_grab_nic_access(trans);
2184 	if (ret) {
2185 		/* keep BHs disabled until iwl_trans_pcie_release_nic_access */
2186 		return ret;
2187 	}
2188 	local_bh_enable();
2189 	return false;
2190 }
2191 
2192 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
2193 {
2194 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2195 
2196 	lockdep_assert_held(&trans_pcie->reg_lock);
2197 
2198 	/*
2199 	 * Fool sparse by faking we acquiring the lock - sparse will
2200 	 * track nic_access anyway.
2201 	 */
2202 	__acquire(&trans_pcie->reg_lock);
2203 
2204 	if (trans_pcie->cmd_hold_nic_awake)
2205 		goto out;
2206 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
2207 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2208 					   CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ);
2209 	else
2210 		__iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2211 					   CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2212 	/*
2213 	 * Above we read the CSR_GP_CNTRL register, which will flush
2214 	 * any previous writes, but we need the write that clears the
2215 	 * MAC_ACCESS_REQ bit to be performed before any other writes
2216 	 * scheduled on different CPUs (after we drop reg_lock).
2217 	 */
2218 out:
2219 	spin_unlock_bh(&trans_pcie->reg_lock);
2220 }
2221 
2222 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2223 				   void *buf, int dwords)
2224 {
2225 	int offs = 0;
2226 	u32 *vals = buf;
2227 
2228 	while (offs < dwords) {
2229 		/* limit the time we spin here under lock to 1/2s */
2230 		unsigned long end = jiffies + HZ / 2;
2231 		bool resched = false;
2232 
2233 		if (iwl_trans_grab_nic_access(trans)) {
2234 			iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2235 				    addr + 4 * offs);
2236 
2237 			while (offs < dwords) {
2238 				vals[offs] = iwl_read32(trans,
2239 							HBUS_TARG_MEM_RDAT);
2240 				offs++;
2241 
2242 				if (time_after(jiffies, end)) {
2243 					resched = true;
2244 					break;
2245 				}
2246 			}
2247 			iwl_trans_release_nic_access(trans);
2248 
2249 			if (resched)
2250 				cond_resched();
2251 		} else {
2252 			return -EBUSY;
2253 		}
2254 	}
2255 
2256 	return 0;
2257 }
2258 
2259 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2260 				    const void *buf, int dwords)
2261 {
2262 	int offs, ret = 0;
2263 	const u32 *vals = buf;
2264 
2265 	if (iwl_trans_grab_nic_access(trans)) {
2266 		iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2267 		for (offs = 0; offs < dwords; offs++)
2268 			iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2269 				    vals ? vals[offs] : 0);
2270 		iwl_trans_release_nic_access(trans);
2271 	} else {
2272 		ret = -EBUSY;
2273 	}
2274 	return ret;
2275 }
2276 
2277 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
2278 					u32 *val)
2279 {
2280 	return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev,
2281 				     ofs, val);
2282 }
2283 
2284 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2285 {
2286 	int i;
2287 
2288 	for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) {
2289 		struct iwl_txq *txq = trans->txqs.txq[i];
2290 
2291 		if (i == trans->txqs.cmd.q_id)
2292 			continue;
2293 
2294 		spin_lock_bh(&txq->lock);
2295 
2296 		if (!block && !(WARN_ON_ONCE(!txq->block))) {
2297 			txq->block--;
2298 			if (!txq->block) {
2299 				iwl_write32(trans, HBUS_TARG_WRPTR,
2300 					    txq->write_ptr | (i << 8));
2301 			}
2302 		} else if (block) {
2303 			txq->block++;
2304 		}
2305 
2306 		spin_unlock_bh(&txq->lock);
2307 	}
2308 }
2309 
2310 #define IWL_FLUSH_WAIT_MS	2000
2311 
2312 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2313 				       struct iwl_trans_rxq_dma_data *data)
2314 {
2315 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2316 
2317 	if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2318 		return -EINVAL;
2319 
2320 	data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2321 	data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2322 	data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2323 	data->fr_bd_wid = 0;
2324 
2325 	return 0;
2326 }
2327 
2328 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2329 {
2330 	struct iwl_txq *txq;
2331 	unsigned long now = jiffies;
2332 	bool overflow_tx;
2333 	u8 wr_ptr;
2334 
2335 	/* Make sure the NIC is still alive in the bus */
2336 	if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2337 		return -ENODEV;
2338 
2339 	if (!test_bit(txq_idx, trans->txqs.queue_used))
2340 		return -EINVAL;
2341 
2342 	IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2343 	txq = trans->txqs.txq[txq_idx];
2344 
2345 	spin_lock_bh(&txq->lock);
2346 	overflow_tx = txq->overflow_tx ||
2347 		      !skb_queue_empty(&txq->overflow_q);
2348 	spin_unlock_bh(&txq->lock);
2349 
2350 	wr_ptr = READ_ONCE(txq->write_ptr);
2351 
2352 	while ((txq->read_ptr != READ_ONCE(txq->write_ptr) ||
2353 		overflow_tx) &&
2354 	       !time_after(jiffies,
2355 			   now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2356 		u8 write_ptr = READ_ONCE(txq->write_ptr);
2357 
2358 		/*
2359 		 * If write pointer moved during the wait, warn only
2360 		 * if the TX came from op mode. In case TX came from
2361 		 * trans layer (overflow TX) don't warn.
2362 		 */
2363 		if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx,
2364 			      "WR pointer moved while flushing %d -> %d\n",
2365 			      wr_ptr, write_ptr))
2366 			return -ETIMEDOUT;
2367 		wr_ptr = write_ptr;
2368 
2369 		usleep_range(1000, 2000);
2370 
2371 		spin_lock_bh(&txq->lock);
2372 		overflow_tx = txq->overflow_tx ||
2373 			      !skb_queue_empty(&txq->overflow_q);
2374 		spin_unlock_bh(&txq->lock);
2375 	}
2376 
2377 	if (txq->read_ptr != txq->write_ptr) {
2378 		IWL_ERR(trans,
2379 			"fail to flush all tx fifo queues Q %d\n", txq_idx);
2380 		iwl_txq_log_scd_error(trans, txq);
2381 		return -ETIMEDOUT;
2382 	}
2383 
2384 	IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2385 
2386 	return 0;
2387 }
2388 
2389 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2390 {
2391 	int cnt;
2392 	int ret = 0;
2393 
2394 	/* waiting for all the tx frames complete might take a while */
2395 	for (cnt = 0;
2396 	     cnt < trans->trans_cfg->base_params->num_of_queues;
2397 	     cnt++) {
2398 
2399 		if (cnt == trans->txqs.cmd.q_id)
2400 			continue;
2401 		if (!test_bit(cnt, trans->txqs.queue_used))
2402 			continue;
2403 		if (!(BIT(cnt) & txq_bm))
2404 			continue;
2405 
2406 		ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2407 		if (ret)
2408 			break;
2409 	}
2410 
2411 	return ret;
2412 }
2413 
2414 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2415 					 u32 mask, u32 value)
2416 {
2417 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2418 
2419 	spin_lock_bh(&trans_pcie->reg_lock);
2420 	__iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2421 	spin_unlock_bh(&trans_pcie->reg_lock);
2422 }
2423 
2424 static const char *get_csr_string(int cmd)
2425 {
2426 #define IWL_CMD(x) case x: return #x
2427 	switch (cmd) {
2428 	IWL_CMD(CSR_HW_IF_CONFIG_REG);
2429 	IWL_CMD(CSR_INT_COALESCING);
2430 	IWL_CMD(CSR_INT);
2431 	IWL_CMD(CSR_INT_MASK);
2432 	IWL_CMD(CSR_FH_INT_STATUS);
2433 	IWL_CMD(CSR_GPIO_IN);
2434 	IWL_CMD(CSR_RESET);
2435 	IWL_CMD(CSR_GP_CNTRL);
2436 	IWL_CMD(CSR_HW_REV);
2437 	IWL_CMD(CSR_EEPROM_REG);
2438 	IWL_CMD(CSR_EEPROM_GP);
2439 	IWL_CMD(CSR_OTP_GP_REG);
2440 	IWL_CMD(CSR_GIO_REG);
2441 	IWL_CMD(CSR_GP_UCODE_REG);
2442 	IWL_CMD(CSR_GP_DRIVER_REG);
2443 	IWL_CMD(CSR_UCODE_DRV_GP1);
2444 	IWL_CMD(CSR_UCODE_DRV_GP2);
2445 	IWL_CMD(CSR_LED_REG);
2446 	IWL_CMD(CSR_DRAM_INT_TBL_REG);
2447 	IWL_CMD(CSR_GIO_CHICKEN_BITS);
2448 	IWL_CMD(CSR_ANA_PLL_CFG);
2449 	IWL_CMD(CSR_HW_REV_WA_REG);
2450 	IWL_CMD(CSR_MONITOR_STATUS_REG);
2451 	IWL_CMD(CSR_DBG_HPET_MEM_REG);
2452 	default:
2453 		return "UNKNOWN";
2454 	}
2455 #undef IWL_CMD
2456 }
2457 
2458 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2459 {
2460 	int i;
2461 	static const u32 csr_tbl[] = {
2462 		CSR_HW_IF_CONFIG_REG,
2463 		CSR_INT_COALESCING,
2464 		CSR_INT,
2465 		CSR_INT_MASK,
2466 		CSR_FH_INT_STATUS,
2467 		CSR_GPIO_IN,
2468 		CSR_RESET,
2469 		CSR_GP_CNTRL,
2470 		CSR_HW_REV,
2471 		CSR_EEPROM_REG,
2472 		CSR_EEPROM_GP,
2473 		CSR_OTP_GP_REG,
2474 		CSR_GIO_REG,
2475 		CSR_GP_UCODE_REG,
2476 		CSR_GP_DRIVER_REG,
2477 		CSR_UCODE_DRV_GP1,
2478 		CSR_UCODE_DRV_GP2,
2479 		CSR_LED_REG,
2480 		CSR_DRAM_INT_TBL_REG,
2481 		CSR_GIO_CHICKEN_BITS,
2482 		CSR_ANA_PLL_CFG,
2483 		CSR_MONITOR_STATUS_REG,
2484 		CSR_HW_REV_WA_REG,
2485 		CSR_DBG_HPET_MEM_REG
2486 	};
2487 	IWL_ERR(trans, "CSR values:\n");
2488 	IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2489 		"CSR_INT_PERIODIC_REG)\n");
2490 	for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2491 		IWL_ERR(trans, "  %25s: 0X%08x\n",
2492 			get_csr_string(csr_tbl[i]),
2493 			iwl_read32(trans, csr_tbl[i]));
2494 	}
2495 }
2496 
2497 #ifdef CONFIG_IWLWIFI_DEBUGFS
2498 /* create and remove of files */
2499 #define DEBUGFS_ADD_FILE(name, parent, mode) do {			\
2500 	debugfs_create_file(#name, mode, parent, trans,			\
2501 			    &iwl_dbgfs_##name##_ops);			\
2502 } while (0)
2503 
2504 /* file operation */
2505 #define DEBUGFS_READ_FILE_OPS(name)					\
2506 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2507 	.read = iwl_dbgfs_##name##_read,				\
2508 	.open = simple_open,						\
2509 	.llseek = generic_file_llseek,					\
2510 };
2511 
2512 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2513 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2514 	.write = iwl_dbgfs_##name##_write,                              \
2515 	.open = simple_open,						\
2516 	.llseek = generic_file_llseek,					\
2517 };
2518 
2519 #define DEBUGFS_READ_WRITE_FILE_OPS(name)				\
2520 static const struct file_operations iwl_dbgfs_##name##_ops = {		\
2521 	.write = iwl_dbgfs_##name##_write,				\
2522 	.read = iwl_dbgfs_##name##_read,				\
2523 	.open = simple_open,						\
2524 	.llseek = generic_file_llseek,					\
2525 };
2526 
2527 struct iwl_dbgfs_tx_queue_priv {
2528 	struct iwl_trans *trans;
2529 };
2530 
2531 struct iwl_dbgfs_tx_queue_state {
2532 	loff_t pos;
2533 };
2534 
2535 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos)
2536 {
2537 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2538 	struct iwl_dbgfs_tx_queue_state *state;
2539 
2540 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2541 		return NULL;
2542 
2543 	state = kmalloc(sizeof(*state), GFP_KERNEL);
2544 	if (!state)
2545 		return NULL;
2546 	state->pos = *pos;
2547 	return state;
2548 }
2549 
2550 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq,
2551 					 void *v, loff_t *pos)
2552 {
2553 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2554 	struct iwl_dbgfs_tx_queue_state *state = v;
2555 
2556 	*pos = ++state->pos;
2557 
2558 	if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues)
2559 		return NULL;
2560 
2561 	return state;
2562 }
2563 
2564 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v)
2565 {
2566 	kfree(v);
2567 }
2568 
2569 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v)
2570 {
2571 	struct iwl_dbgfs_tx_queue_priv *priv = seq->private;
2572 	struct iwl_dbgfs_tx_queue_state *state = v;
2573 	struct iwl_trans *trans = priv->trans;
2574 	struct iwl_txq *txq = trans->txqs.txq[state->pos];
2575 
2576 	seq_printf(seq, "hwq %.3u: used=%d stopped=%d ",
2577 		   (unsigned int)state->pos,
2578 		   !!test_bit(state->pos, trans->txqs.queue_used),
2579 		   !!test_bit(state->pos, trans->txqs.queue_stopped));
2580 	if (txq)
2581 		seq_printf(seq,
2582 			   "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d",
2583 			   txq->read_ptr, txq->write_ptr,
2584 			   txq->need_update, txq->frozen,
2585 			   txq->n_window, txq->ampdu);
2586 	else
2587 		seq_puts(seq, "(unallocated)");
2588 
2589 	if (state->pos == trans->txqs.cmd.q_id)
2590 		seq_puts(seq, " (HCMD)");
2591 	seq_puts(seq, "\n");
2592 
2593 	return 0;
2594 }
2595 
2596 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = {
2597 	.start = iwl_dbgfs_tx_queue_seq_start,
2598 	.next = iwl_dbgfs_tx_queue_seq_next,
2599 	.stop = iwl_dbgfs_tx_queue_seq_stop,
2600 	.show = iwl_dbgfs_tx_queue_seq_show,
2601 };
2602 
2603 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp)
2604 {
2605 	struct iwl_dbgfs_tx_queue_priv *priv;
2606 
2607 	priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops,
2608 				  sizeof(*priv));
2609 
2610 	if (!priv)
2611 		return -ENOMEM;
2612 
2613 	priv->trans = inode->i_private;
2614 	return 0;
2615 }
2616 
2617 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2618 				       char __user *user_buf,
2619 				       size_t count, loff_t *ppos)
2620 {
2621 	struct iwl_trans *trans = file->private_data;
2622 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2623 	char *buf;
2624 	int pos = 0, i, ret;
2625 	size_t bufsz;
2626 
2627 	bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2628 
2629 	if (!trans_pcie->rxq)
2630 		return -EAGAIN;
2631 
2632 	buf = kzalloc(bufsz, GFP_KERNEL);
2633 	if (!buf)
2634 		return -ENOMEM;
2635 
2636 	for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2637 		struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2638 
2639 		pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2640 				 i);
2641 		pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2642 				 rxq->read);
2643 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2644 				 rxq->write);
2645 		pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2646 				 rxq->write_actual);
2647 		pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2648 				 rxq->need_update);
2649 		pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2650 				 rxq->free_count);
2651 		if (rxq->rb_stts) {
2652 			u32 r =	__le16_to_cpu(iwl_get_closed_rb_stts(trans,
2653 								     rxq));
2654 			pos += scnprintf(buf + pos, bufsz - pos,
2655 					 "\tclosed_rb_num: %u\n",
2656 					 r & 0x0FFF);
2657 		} else {
2658 			pos += scnprintf(buf + pos, bufsz - pos,
2659 					 "\tclosed_rb_num: Not Allocated\n");
2660 		}
2661 	}
2662 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2663 	kfree(buf);
2664 
2665 	return ret;
2666 }
2667 
2668 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2669 					char __user *user_buf,
2670 					size_t count, loff_t *ppos)
2671 {
2672 	struct iwl_trans *trans = file->private_data;
2673 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2674 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2675 
2676 	int pos = 0;
2677 	char *buf;
2678 	int bufsz = 24 * 64; /* 24 items * 64 char per item */
2679 	ssize_t ret;
2680 
2681 	buf = kzalloc(bufsz, GFP_KERNEL);
2682 	if (!buf)
2683 		return -ENOMEM;
2684 
2685 	pos += scnprintf(buf + pos, bufsz - pos,
2686 			"Interrupt Statistics Report:\n");
2687 
2688 	pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2689 		isr_stats->hw);
2690 	pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2691 		isr_stats->sw);
2692 	if (isr_stats->sw || isr_stats->hw) {
2693 		pos += scnprintf(buf + pos, bufsz - pos,
2694 			"\tLast Restarting Code:  0x%X\n",
2695 			isr_stats->err_code);
2696 	}
2697 #ifdef CONFIG_IWLWIFI_DEBUG
2698 	pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2699 		isr_stats->sch);
2700 	pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2701 		isr_stats->alive);
2702 #endif
2703 	pos += scnprintf(buf + pos, bufsz - pos,
2704 		"HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2705 
2706 	pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2707 		isr_stats->ctkill);
2708 
2709 	pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2710 		isr_stats->wakeup);
2711 
2712 	pos += scnprintf(buf + pos, bufsz - pos,
2713 		"Rx command responses:\t\t %u\n", isr_stats->rx);
2714 
2715 	pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2716 		isr_stats->tx);
2717 
2718 	pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2719 		isr_stats->unhandled);
2720 
2721 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2722 	kfree(buf);
2723 	return ret;
2724 }
2725 
2726 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2727 					 const char __user *user_buf,
2728 					 size_t count, loff_t *ppos)
2729 {
2730 	struct iwl_trans *trans = file->private_data;
2731 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2732 	struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2733 	u32 reset_flag;
2734 	int ret;
2735 
2736 	ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2737 	if (ret)
2738 		return ret;
2739 	if (reset_flag == 0)
2740 		memset(isr_stats, 0, sizeof(*isr_stats));
2741 
2742 	return count;
2743 }
2744 
2745 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2746 				   const char __user *user_buf,
2747 				   size_t count, loff_t *ppos)
2748 {
2749 	struct iwl_trans *trans = file->private_data;
2750 
2751 	iwl_pcie_dump_csr(trans);
2752 
2753 	return count;
2754 }
2755 
2756 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2757 				     char __user *user_buf,
2758 				     size_t count, loff_t *ppos)
2759 {
2760 	struct iwl_trans *trans = file->private_data;
2761 	char *buf = NULL;
2762 	ssize_t ret;
2763 
2764 	ret = iwl_dump_fh(trans, &buf);
2765 	if (ret < 0)
2766 		return ret;
2767 	if (!buf)
2768 		return -EINVAL;
2769 	ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2770 	kfree(buf);
2771 	return ret;
2772 }
2773 
2774 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2775 				     char __user *user_buf,
2776 				     size_t count, loff_t *ppos)
2777 {
2778 	struct iwl_trans *trans = file->private_data;
2779 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2780 	char buf[100];
2781 	int pos;
2782 
2783 	pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2784 			trans_pcie->debug_rfkill,
2785 			!(iwl_read32(trans, CSR_GP_CNTRL) &
2786 				CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2787 
2788 	return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2789 }
2790 
2791 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2792 				      const char __user *user_buf,
2793 				      size_t count, loff_t *ppos)
2794 {
2795 	struct iwl_trans *trans = file->private_data;
2796 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2797 	bool new_value;
2798 	int ret;
2799 
2800 	ret = kstrtobool_from_user(user_buf, count, &new_value);
2801 	if (ret)
2802 		return ret;
2803 	if (new_value == trans_pcie->debug_rfkill)
2804 		return count;
2805 	IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2806 		 trans_pcie->debug_rfkill, new_value);
2807 	trans_pcie->debug_rfkill = new_value;
2808 	iwl_pcie_handle_rfkill_irq(trans);
2809 
2810 	return count;
2811 }
2812 
2813 static int iwl_dbgfs_monitor_data_open(struct inode *inode,
2814 				       struct file *file)
2815 {
2816 	struct iwl_trans *trans = inode->i_private;
2817 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2818 
2819 	if (!trans->dbg.dest_tlv ||
2820 	    trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) {
2821 		IWL_ERR(trans, "Debug destination is not set to DRAM\n");
2822 		return -ENOENT;
2823 	}
2824 
2825 	if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED)
2826 		return -EBUSY;
2827 
2828 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN;
2829 	return simple_open(inode, file);
2830 }
2831 
2832 static int iwl_dbgfs_monitor_data_release(struct inode *inode,
2833 					  struct file *file)
2834 {
2835 	struct iwl_trans_pcie *trans_pcie =
2836 		IWL_TRANS_GET_PCIE_TRANS(inode->i_private);
2837 
2838 	if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN)
2839 		trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
2840 	return 0;
2841 }
2842 
2843 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count,
2844 				  void *buf, ssize_t *size,
2845 				  ssize_t *bytes_copied)
2846 {
2847 	int buf_size_left = count - *bytes_copied;
2848 
2849 	buf_size_left = buf_size_left - (buf_size_left % sizeof(u32));
2850 	if (*size > buf_size_left)
2851 		*size = buf_size_left;
2852 
2853 	*size -= copy_to_user(user_buf, buf, *size);
2854 	*bytes_copied += *size;
2855 
2856 	if (buf_size_left == *size)
2857 		return true;
2858 	return false;
2859 }
2860 
2861 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file,
2862 					   char __user *user_buf,
2863 					   size_t count, loff_t *ppos)
2864 {
2865 	struct iwl_trans *trans = file->private_data;
2866 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2867 	u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf;
2868 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2869 	u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt;
2870 	ssize_t size, bytes_copied = 0;
2871 	bool b_full;
2872 
2873 	if (trans->dbg.dest_tlv) {
2874 		write_ptr_addr =
2875 			le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
2876 		wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
2877 	} else {
2878 		write_ptr_addr = MON_BUFF_WRPTR;
2879 		wrap_cnt_addr = MON_BUFF_CYCLE_CNT;
2880 	}
2881 
2882 	if (unlikely(!trans->dbg.rec_on))
2883 		return 0;
2884 
2885 	mutex_lock(&data->mutex);
2886 	if (data->state ==
2887 	    IWL_FW_MON_DBGFS_STATE_DISABLED) {
2888 		mutex_unlock(&data->mutex);
2889 		return 0;
2890 	}
2891 
2892 	/* write_ptr position in bytes rather then DW */
2893 	write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32);
2894 	wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr);
2895 
2896 	if (data->prev_wrap_cnt == wrap_cnt) {
2897 		size = write_ptr - data->prev_wr_ptr;
2898 		curr_buf = cpu_addr + data->prev_wr_ptr;
2899 		b_full = iwl_write_to_user_buf(user_buf, count,
2900 					       curr_buf, &size,
2901 					       &bytes_copied);
2902 		data->prev_wr_ptr += size;
2903 
2904 	} else if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2905 		   write_ptr < data->prev_wr_ptr) {
2906 		size = trans->dbg.fw_mon.size - data->prev_wr_ptr;
2907 		curr_buf = cpu_addr + data->prev_wr_ptr;
2908 		b_full = iwl_write_to_user_buf(user_buf, count,
2909 					       curr_buf, &size,
2910 					       &bytes_copied);
2911 		data->prev_wr_ptr += size;
2912 
2913 		if (!b_full) {
2914 			size = write_ptr;
2915 			b_full = iwl_write_to_user_buf(user_buf, count,
2916 						       cpu_addr, &size,
2917 						       &bytes_copied);
2918 			data->prev_wr_ptr = size;
2919 			data->prev_wrap_cnt++;
2920 		}
2921 	} else {
2922 		if (data->prev_wrap_cnt == wrap_cnt - 1 &&
2923 		    write_ptr > data->prev_wr_ptr)
2924 			IWL_WARN(trans,
2925 				 "write pointer passed previous write pointer, start copying from the beginning\n");
2926 		else if (!unlikely(data->prev_wrap_cnt == 0 &&
2927 				   data->prev_wr_ptr == 0))
2928 			IWL_WARN(trans,
2929 				 "monitor data is out of sync, start copying from the beginning\n");
2930 
2931 		size = write_ptr;
2932 		b_full = iwl_write_to_user_buf(user_buf, count,
2933 					       cpu_addr, &size,
2934 					       &bytes_copied);
2935 		data->prev_wr_ptr = size;
2936 		data->prev_wrap_cnt = wrap_cnt;
2937 	}
2938 
2939 	mutex_unlock(&data->mutex);
2940 
2941 	return bytes_copied;
2942 }
2943 
2944 static ssize_t iwl_dbgfs_rf_read(struct file *file,
2945 				 char __user *user_buf,
2946 				 size_t count, loff_t *ppos)
2947 {
2948 	struct iwl_trans *trans = file->private_data;
2949 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2950 
2951 	if (!trans_pcie->rf_name[0])
2952 		return -ENODEV;
2953 
2954 	return simple_read_from_buffer(user_buf, count, ppos,
2955 				       trans_pcie->rf_name,
2956 				       strlen(trans_pcie->rf_name));
2957 }
2958 
2959 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2960 DEBUGFS_READ_FILE_OPS(fh_reg);
2961 DEBUGFS_READ_FILE_OPS(rx_queue);
2962 DEBUGFS_WRITE_FILE_OPS(csr);
2963 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2964 DEBUGFS_READ_FILE_OPS(rf);
2965 
2966 static const struct file_operations iwl_dbgfs_tx_queue_ops = {
2967 	.owner = THIS_MODULE,
2968 	.open = iwl_dbgfs_tx_queue_open,
2969 	.read = seq_read,
2970 	.llseek = seq_lseek,
2971 	.release = seq_release_private,
2972 };
2973 
2974 static const struct file_operations iwl_dbgfs_monitor_data_ops = {
2975 	.read = iwl_dbgfs_monitor_data_read,
2976 	.open = iwl_dbgfs_monitor_data_open,
2977 	.release = iwl_dbgfs_monitor_data_release,
2978 };
2979 
2980 /* Create the debugfs files and directories */
2981 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2982 {
2983 	struct dentry *dir = trans->dbgfs_dir;
2984 
2985 	DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2986 	DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2987 	DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2988 	DEBUGFS_ADD_FILE(csr, dir, 0200);
2989 	DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2990 	DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2991 	DEBUGFS_ADD_FILE(monitor_data, dir, 0400);
2992 	DEBUGFS_ADD_FILE(rf, dir, 0400);
2993 }
2994 
2995 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans)
2996 {
2997 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2998 	struct cont_rec *data = &trans_pcie->fw_mon_data;
2999 
3000 	mutex_lock(&data->mutex);
3001 	data->state = IWL_FW_MON_DBGFS_STATE_DISABLED;
3002 	mutex_unlock(&data->mutex);
3003 }
3004 #endif /*CONFIG_IWLWIFI_DEBUGFS */
3005 
3006 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
3007 {
3008 	u32 cmdlen = 0;
3009 	int i;
3010 
3011 	for (i = 0; i < trans->txqs.tfd.max_tbs; i++)
3012 		cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i);
3013 
3014 	return cmdlen;
3015 }
3016 
3017 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
3018 				   struct iwl_fw_error_dump_data **data,
3019 				   int allocated_rb_nums)
3020 {
3021 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3022 	int max_len = trans_pcie->rx_buf_bytes;
3023 	/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3024 	struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3025 	u32 i, r, j, rb_len = 0;
3026 
3027 	spin_lock(&rxq->lock);
3028 
3029 	r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
3030 
3031 	for (i = rxq->read, j = 0;
3032 	     i != r && j < allocated_rb_nums;
3033 	     i = (i + 1) & RX_QUEUE_MASK, j++) {
3034 		struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
3035 		struct iwl_fw_error_dump_rb *rb;
3036 
3037 		dma_sync_single_for_cpu(trans->dev, rxb->page_dma,
3038 					max_len, DMA_FROM_DEVICE);
3039 
3040 		rb_len += sizeof(**data) + sizeof(*rb) + max_len;
3041 
3042 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
3043 		(*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
3044 		rb = (void *)(*data)->data;
3045 		rb->index = cpu_to_le32(i);
3046 		memcpy(rb->data, page_address(rxb->page), max_len);
3047 
3048 		*data = iwl_fw_error_next_data(*data);
3049 	}
3050 
3051 	spin_unlock(&rxq->lock);
3052 
3053 	return rb_len;
3054 }
3055 #define IWL_CSR_TO_DUMP (0x250)
3056 
3057 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
3058 				   struct iwl_fw_error_dump_data **data)
3059 {
3060 	u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
3061 	__le32 *val;
3062 	int i;
3063 
3064 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
3065 	(*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
3066 	val = (void *)(*data)->data;
3067 
3068 	for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
3069 		*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3070 
3071 	*data = iwl_fw_error_next_data(*data);
3072 
3073 	return csr_len;
3074 }
3075 
3076 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
3077 				       struct iwl_fw_error_dump_data **data)
3078 {
3079 	u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
3080 	__le32 *val;
3081 	int i;
3082 
3083 	if (!iwl_trans_grab_nic_access(trans))
3084 		return 0;
3085 
3086 	(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
3087 	(*data)->len = cpu_to_le32(fh_regs_len);
3088 	val = (void *)(*data)->data;
3089 
3090 	if (!trans->trans_cfg->gen2)
3091 		for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
3092 		     i += sizeof(u32))
3093 			*val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
3094 	else
3095 		for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2);
3096 		     i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2);
3097 		     i += sizeof(u32))
3098 			*val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
3099 								      i));
3100 
3101 	iwl_trans_release_nic_access(trans);
3102 
3103 	*data = iwl_fw_error_next_data(*data);
3104 
3105 	return sizeof(**data) + fh_regs_len;
3106 }
3107 
3108 static u32
3109 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
3110 				 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
3111 				 u32 monitor_len)
3112 {
3113 	u32 buf_size_in_dwords = (monitor_len >> 2);
3114 	u32 *buffer = (u32 *)fw_mon_data->data;
3115 	u32 i;
3116 
3117 	if (!iwl_trans_grab_nic_access(trans))
3118 		return 0;
3119 
3120 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
3121 	for (i = 0; i < buf_size_in_dwords; i++)
3122 		buffer[i] = iwl_read_umac_prph_no_grab(trans,
3123 						       MON_DMARB_RD_DATA_ADDR);
3124 	iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
3125 
3126 	iwl_trans_release_nic_access(trans);
3127 
3128 	return monitor_len;
3129 }
3130 
3131 static void
3132 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans,
3133 			     struct iwl_fw_error_dump_fw_mon *fw_mon_data)
3134 {
3135 	u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt;
3136 
3137 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3138 		base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB;
3139 		base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB;
3140 		write_ptr = DBGC_CUR_DBGBUF_STATUS;
3141 		wrap_cnt = DBGC_DBGBUF_WRAP_AROUND;
3142 	} else if (trans->dbg.dest_tlv) {
3143 		write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg);
3144 		wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count);
3145 		base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3146 	} else {
3147 		base = MON_BUFF_BASE_ADDR;
3148 		write_ptr = MON_BUFF_WRPTR;
3149 		wrap_cnt = MON_BUFF_CYCLE_CNT;
3150 	}
3151 
3152 	write_ptr_val = iwl_read_prph(trans, write_ptr);
3153 	fw_mon_data->fw_mon_cycle_cnt =
3154 		cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
3155 	fw_mon_data->fw_mon_base_ptr =
3156 		cpu_to_le32(iwl_read_prph(trans, base));
3157 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
3158 		fw_mon_data->fw_mon_base_high_ptr =
3159 			cpu_to_le32(iwl_read_prph(trans, base_high));
3160 		write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK;
3161 		/* convert wrtPtr to DWs, to align with all HWs */
3162 		write_ptr_val >>= 2;
3163 	}
3164 	fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val);
3165 }
3166 
3167 static u32
3168 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
3169 			    struct iwl_fw_error_dump_data **data,
3170 			    u32 monitor_len)
3171 {
3172 	struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
3173 	u32 len = 0;
3174 
3175 	if (trans->dbg.dest_tlv ||
3176 	    (fw_mon->size &&
3177 	     (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 ||
3178 	      trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) {
3179 		struct iwl_fw_error_dump_fw_mon *fw_mon_data;
3180 
3181 		(*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
3182 		fw_mon_data = (void *)(*data)->data;
3183 
3184 		iwl_trans_pcie_dump_pointers(trans, fw_mon_data);
3185 
3186 		len += sizeof(**data) + sizeof(*fw_mon_data);
3187 		if (fw_mon->size) {
3188 			memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size);
3189 			monitor_len = fw_mon->size;
3190 		} else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) {
3191 			u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr);
3192 			/*
3193 			 * Update pointers to reflect actual values after
3194 			 * shifting
3195 			 */
3196 			if (trans->dbg.dest_tlv->version) {
3197 				base = (iwl_read_prph(trans, base) &
3198 					IWL_LDBG_M2S_BUF_BA_MSK) <<
3199 				       trans->dbg.dest_tlv->base_shift;
3200 				base *= IWL_M2S_UNIT_SIZE;
3201 				base += trans->cfg->smem_offset;
3202 			} else {
3203 				base = iwl_read_prph(trans, base) <<
3204 				       trans->dbg.dest_tlv->base_shift;
3205 			}
3206 
3207 			iwl_trans_read_mem(trans, base, fw_mon_data->data,
3208 					   monitor_len / sizeof(u32));
3209 		} else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) {
3210 			monitor_len =
3211 				iwl_trans_pci_dump_marbh_monitor(trans,
3212 								 fw_mon_data,
3213 								 monitor_len);
3214 		} else {
3215 			/* Didn't match anything - output no monitor data */
3216 			monitor_len = 0;
3217 		}
3218 
3219 		len += monitor_len;
3220 		(*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
3221 	}
3222 
3223 	return len;
3224 }
3225 
3226 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len)
3227 {
3228 	if (trans->dbg.fw_mon.size) {
3229 		*len += sizeof(struct iwl_fw_error_dump_data) +
3230 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3231 			trans->dbg.fw_mon.size;
3232 		return trans->dbg.fw_mon.size;
3233 	} else if (trans->dbg.dest_tlv) {
3234 		u32 base, end, cfg_reg, monitor_len;
3235 
3236 		if (trans->dbg.dest_tlv->version == 1) {
3237 			cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3238 			cfg_reg = iwl_read_prph(trans, cfg_reg);
3239 			base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3240 				trans->dbg.dest_tlv->base_shift;
3241 			base *= IWL_M2S_UNIT_SIZE;
3242 			base += trans->cfg->smem_offset;
3243 
3244 			monitor_len =
3245 				(cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3246 				trans->dbg.dest_tlv->end_shift;
3247 			monitor_len *= IWL_M2S_UNIT_SIZE;
3248 		} else {
3249 			base = le32_to_cpu(trans->dbg.dest_tlv->base_reg);
3250 			end = le32_to_cpu(trans->dbg.dest_tlv->end_reg);
3251 
3252 			base = iwl_read_prph(trans, base) <<
3253 			       trans->dbg.dest_tlv->base_shift;
3254 			end = iwl_read_prph(trans, end) <<
3255 			      trans->dbg.dest_tlv->end_shift;
3256 
3257 			/* Make "end" point to the actual end */
3258 			if (trans->trans_cfg->device_family >=
3259 			    IWL_DEVICE_FAMILY_8000 ||
3260 			    trans->dbg.dest_tlv->monitor_mode == MARBH_MODE)
3261 				end += (1 << trans->dbg.dest_tlv->end_shift);
3262 			monitor_len = end - base;
3263 		}
3264 		*len += sizeof(struct iwl_fw_error_dump_data) +
3265 			sizeof(struct iwl_fw_error_dump_fw_mon) +
3266 			monitor_len;
3267 		return monitor_len;
3268 	}
3269 	return 0;
3270 }
3271 
3272 static struct iwl_trans_dump_data *
3273 iwl_trans_pcie_dump_data(struct iwl_trans *trans,
3274 			 u32 dump_mask,
3275 			 const struct iwl_dump_sanitize_ops *sanitize_ops,
3276 			 void *sanitize_ctx)
3277 {
3278 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3279 	struct iwl_fw_error_dump_data *data;
3280 	struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id];
3281 	struct iwl_fw_error_dump_txcmd *txcmd;
3282 	struct iwl_trans_dump_data *dump_data;
3283 	u32 len, num_rbs = 0, monitor_len = 0;
3284 	int i, ptr;
3285 	bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3286 			!trans->trans_cfg->mq_rx_supported &&
3287 			dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3288 
3289 	if (!dump_mask)
3290 		return NULL;
3291 
3292 	/* transport dump header */
3293 	len = sizeof(*dump_data);
3294 
3295 	/* host commands */
3296 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq)
3297 		len += sizeof(*data) +
3298 			cmdq->n_window * (sizeof(*txcmd) +
3299 					  TFD_MAX_PAYLOAD_SIZE);
3300 
3301 	/* FW monitor */
3302 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3303 		monitor_len = iwl_trans_get_fw_monitor_len(trans, &len);
3304 
3305 	/* CSR registers */
3306 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3307 		len += sizeof(*data) + IWL_CSR_TO_DUMP;
3308 
3309 	/* FH registers */
3310 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3311 		if (trans->trans_cfg->gen2)
3312 			len += sizeof(*data) +
3313 			       (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) -
3314 				iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2));
3315 		else
3316 			len += sizeof(*data) +
3317 			       (FH_MEM_UPPER_BOUND -
3318 				FH_MEM_LOWER_BOUND);
3319 	}
3320 
3321 	if (dump_rbs) {
3322 		/* Dump RBs is supported only for pre-9000 devices (1 queue) */
3323 		struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3324 		/* RBs */
3325 		num_rbs =
3326 			le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3327 			& 0x0FFF;
3328 		num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3329 		len += num_rbs * (sizeof(*data) +
3330 				  sizeof(struct iwl_fw_error_dump_rb) +
3331 				  (PAGE_SIZE << trans_pcie->rx_page_order));
3332 	}
3333 
3334 	/* Paged memory for gen2 HW */
3335 	if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3336 		for (i = 0; i < trans->init_dram.paging_cnt; i++)
3337 			len += sizeof(*data) +
3338 			       sizeof(struct iwl_fw_error_dump_paging) +
3339 			       trans->init_dram.paging[i].size;
3340 
3341 	dump_data = vzalloc(len);
3342 	if (!dump_data)
3343 		return NULL;
3344 
3345 	len = 0;
3346 	data = (void *)dump_data->data;
3347 
3348 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) {
3349 		u16 tfd_size = trans->txqs.tfd.size;
3350 
3351 		data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3352 		txcmd = (void *)data->data;
3353 		spin_lock_bh(&cmdq->lock);
3354 		ptr = cmdq->write_ptr;
3355 		for (i = 0; i < cmdq->n_window; i++) {
3356 			u8 idx = iwl_txq_get_cmd_index(cmdq, ptr);
3357 			u8 tfdidx;
3358 			u32 caplen, cmdlen;
3359 
3360 			if (trans->trans_cfg->use_tfh)
3361 				tfdidx = idx;
3362 			else
3363 				tfdidx = ptr;
3364 
3365 			cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3366 							   (u8 *)cmdq->tfds +
3367 							   tfd_size * tfdidx);
3368 			caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3369 
3370 			if (cmdlen) {
3371 				len += sizeof(*txcmd) + caplen;
3372 				txcmd->cmdlen = cpu_to_le32(cmdlen);
3373 				txcmd->caplen = cpu_to_le32(caplen);
3374 				memcpy(txcmd->data, cmdq->entries[idx].cmd,
3375 				       caplen);
3376 				if (sanitize_ops && sanitize_ops->frob_hcmd)
3377 					sanitize_ops->frob_hcmd(sanitize_ctx,
3378 								txcmd->data,
3379 								caplen);
3380 				txcmd = (void *)((u8 *)txcmd->data + caplen);
3381 			}
3382 
3383 			ptr = iwl_txq_dec_wrap(trans, ptr);
3384 		}
3385 		spin_unlock_bh(&cmdq->lock);
3386 
3387 		data->len = cpu_to_le32(len);
3388 		len += sizeof(*data);
3389 		data = iwl_fw_error_next_data(data);
3390 	}
3391 
3392 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3393 		len += iwl_trans_pcie_dump_csr(trans, &data);
3394 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3395 		len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3396 	if (dump_rbs)
3397 		len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3398 
3399 	/* Paged memory for gen2 HW */
3400 	if (trans->trans_cfg->gen2 &&
3401 	    dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3402 		for (i = 0; i < trans->init_dram.paging_cnt; i++) {
3403 			struct iwl_fw_error_dump_paging *paging;
3404 			u32 page_len = trans->init_dram.paging[i].size;
3405 
3406 			data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3407 			data->len = cpu_to_le32(sizeof(*paging) + page_len);
3408 			paging = (void *)data->data;
3409 			paging->index = cpu_to_le32(i);
3410 			memcpy(paging->data,
3411 			       trans->init_dram.paging[i].block, page_len);
3412 			data = iwl_fw_error_next_data(data);
3413 
3414 			len += sizeof(*data) + sizeof(*paging) + page_len;
3415 		}
3416 	}
3417 	if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3418 		len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3419 
3420 	dump_data->len = len;
3421 
3422 	return dump_data;
3423 }
3424 
3425 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable)
3426 {
3427 	if (enable)
3428 		iwl_enable_interrupts(trans);
3429 	else
3430 		iwl_disable_interrupts(trans);
3431 }
3432 
3433 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans)
3434 {
3435 	u32 inta_addr, sw_err_bit;
3436 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3437 
3438 	if (trans_pcie->msix_enabled) {
3439 		inta_addr = CSR_MSIX_HW_INT_CAUSES_AD;
3440 		if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
3441 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ;
3442 		else
3443 			sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR;
3444 	} else {
3445 		inta_addr = CSR_INT;
3446 		sw_err_bit = CSR_INT_BIT_SW_ERR;
3447 	}
3448 
3449 	iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit);
3450 }
3451 
3452 #define IWL_TRANS_COMMON_OPS						\
3453 	.op_mode_leave = iwl_trans_pcie_op_mode_leave,			\
3454 	.write8 = iwl_trans_pcie_write8,				\
3455 	.write32 = iwl_trans_pcie_write32,				\
3456 	.read32 = iwl_trans_pcie_read32,				\
3457 	.read_prph = iwl_trans_pcie_read_prph,				\
3458 	.write_prph = iwl_trans_pcie_write_prph,			\
3459 	.read_mem = iwl_trans_pcie_read_mem,				\
3460 	.write_mem = iwl_trans_pcie_write_mem,				\
3461 	.read_config32 = iwl_trans_pcie_read_config32,			\
3462 	.configure = iwl_trans_pcie_configure,				\
3463 	.set_pmi = iwl_trans_pcie_set_pmi,				\
3464 	.sw_reset = iwl_trans_pcie_sw_reset,				\
3465 	.grab_nic_access = iwl_trans_pcie_grab_nic_access,		\
3466 	.release_nic_access = iwl_trans_pcie_release_nic_access,	\
3467 	.set_bits_mask = iwl_trans_pcie_set_bits_mask,			\
3468 	.dump_data = iwl_trans_pcie_dump_data,				\
3469 	.d3_suspend = iwl_trans_pcie_d3_suspend,			\
3470 	.d3_resume = iwl_trans_pcie_d3_resume,				\
3471 	.interrupts = iwl_trans_pci_interrupts,				\
3472 	.sync_nmi = iwl_trans_pcie_sync_nmi,				\
3473 	.imr_dma_data = iwl_trans_pcie_copy_imr				\
3474 
3475 static const struct iwl_trans_ops trans_ops_pcie = {
3476 	IWL_TRANS_COMMON_OPS,
3477 	.start_hw = iwl_trans_pcie_start_hw,
3478 	.fw_alive = iwl_trans_pcie_fw_alive,
3479 	.start_fw = iwl_trans_pcie_start_fw,
3480 	.stop_device = iwl_trans_pcie_stop_device,
3481 
3482 	.send_cmd = iwl_pcie_enqueue_hcmd,
3483 
3484 	.tx = iwl_trans_pcie_tx,
3485 	.reclaim = iwl_txq_reclaim,
3486 
3487 	.txq_disable = iwl_trans_pcie_txq_disable,
3488 	.txq_enable = iwl_trans_pcie_txq_enable,
3489 
3490 	.txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3491 
3492 	.wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3493 
3494 	.freeze_txq_timer = iwl_trans_txq_freeze_timer,
3495 	.block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3496 #ifdef CONFIG_IWLWIFI_DEBUGFS
3497 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3498 #endif
3499 };
3500 
3501 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3502 	IWL_TRANS_COMMON_OPS,
3503 	.start_hw = iwl_trans_pcie_start_hw,
3504 	.fw_alive = iwl_trans_pcie_gen2_fw_alive,
3505 	.start_fw = iwl_trans_pcie_gen2_start_fw,
3506 	.stop_device = iwl_trans_pcie_gen2_stop_device,
3507 
3508 	.send_cmd = iwl_pcie_gen2_enqueue_hcmd,
3509 
3510 	.tx = iwl_txq_gen2_tx,
3511 	.reclaim = iwl_txq_reclaim,
3512 
3513 	.set_q_ptrs = iwl_txq_set_q_ptrs,
3514 
3515 	.txq_alloc = iwl_txq_dyn_alloc,
3516 	.txq_free = iwl_txq_dyn_free,
3517 	.wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3518 	.rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3519 	.set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3520 	.set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3521 #ifdef CONFIG_IWLWIFI_DEBUGFS
3522 	.debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3523 #endif
3524 };
3525 
3526 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3527 			       const struct pci_device_id *ent,
3528 			       const struct iwl_cfg_trans_params *cfg_trans)
3529 {
3530 	struct iwl_trans_pcie *trans_pcie;
3531 	struct iwl_trans *trans;
3532 	int ret, addr_size;
3533 	const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2;
3534 	void __iomem * const *table;
3535 
3536 	if (!cfg_trans->gen2)
3537 		ops = &trans_ops_pcie;
3538 
3539 	ret = pcim_enable_device(pdev);
3540 	if (ret)
3541 		return ERR_PTR(ret);
3542 
3543 	trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops,
3544 				cfg_trans);
3545 	if (!trans)
3546 		return ERR_PTR(-ENOMEM);
3547 
3548 	trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3549 
3550 	trans_pcie->trans = trans;
3551 	trans_pcie->opmode_down = true;
3552 	spin_lock_init(&trans_pcie->irq_lock);
3553 	spin_lock_init(&trans_pcie->reg_lock);
3554 	spin_lock_init(&trans_pcie->alloc_page_lock);
3555 	mutex_init(&trans_pcie->mutex);
3556 	init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3557 	init_waitqueue_head(&trans_pcie->fw_reset_waitq);
3558 	init_waitqueue_head(&trans_pcie->imr_waitq);
3559 
3560 	trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3561 						   WQ_HIGHPRI | WQ_UNBOUND, 1);
3562 	if (!trans_pcie->rba.alloc_wq) {
3563 		ret = -ENOMEM;
3564 		goto out_free_trans;
3565 	}
3566 	INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3567 
3568 	trans_pcie->debug_rfkill = -1;
3569 
3570 	if (!cfg_trans->base_params->pcie_l1_allowed) {
3571 		/*
3572 		 * W/A - seems to solve weird behavior. We need to remove this
3573 		 * if we don't want to stay in L1 all the time. This wastes a
3574 		 * lot of power.
3575 		 */
3576 		pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3577 				       PCIE_LINK_STATE_L1 |
3578 				       PCIE_LINK_STATE_CLKPM);
3579 	}
3580 
3581 	trans_pcie->def_rx_queue = 0;
3582 
3583 	pci_set_master(pdev);
3584 
3585 	addr_size = trans->txqs.tfd.addr_size;
3586 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size));
3587 	if (ret) {
3588 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3589 		/* both attempts failed: */
3590 		if (ret) {
3591 			dev_err(&pdev->dev, "No suitable DMA available\n");
3592 			goto out_no_pci;
3593 		}
3594 	}
3595 
3596 	ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3597 	if (ret) {
3598 		dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3599 		goto out_no_pci;
3600 	}
3601 
3602 	table = pcim_iomap_table(pdev);
3603 	if (!table) {
3604 		dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3605 		ret = -ENOMEM;
3606 		goto out_no_pci;
3607 	}
3608 
3609 	trans_pcie->hw_base = table[0];
3610 	if (!trans_pcie->hw_base) {
3611 		dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n");
3612 		ret = -ENODEV;
3613 		goto out_no_pci;
3614 	}
3615 
3616 	/* We disable the RETRY_TIMEOUT register (0x41) to keep
3617 	 * PCI Tx retries from interfering with C3 CPU state */
3618 	pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3619 
3620 	trans_pcie->pci_dev = pdev;
3621 	iwl_disable_interrupts(trans);
3622 
3623 	trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3624 	if (trans->hw_rev == 0xffffffff) {
3625 		dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n");
3626 		ret = -EIO;
3627 		goto out_no_pci;
3628 	}
3629 
3630 	/*
3631 	 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3632 	 * changed, and now the revision step also includes bit 0-1 (no more
3633 	 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3634 	 * in the old format.
3635 	 */
3636 	if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000)
3637 		trans->hw_rev_step = trans->hw_rev & 0xF;
3638 	else
3639 		trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2;
3640 
3641 	IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev);
3642 
3643 	iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans);
3644 	trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3645 	snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3646 		 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3647 
3648 	init_waitqueue_head(&trans_pcie->sx_waitq);
3649 
3650 
3651 	if (trans_pcie->msix_enabled) {
3652 		ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3653 		if (ret)
3654 			goto out_no_pci;
3655 	 } else {
3656 		ret = iwl_pcie_alloc_ict(trans);
3657 		if (ret)
3658 			goto out_no_pci;
3659 
3660 		ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3661 						iwl_pcie_isr,
3662 						iwl_pcie_irq_handler,
3663 						IRQF_SHARED, DRV_NAME, trans);
3664 		if (ret) {
3665 			IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3666 			goto out_free_ict;
3667 		}
3668 	 }
3669 
3670 #ifdef CONFIG_IWLWIFI_DEBUGFS
3671 	trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED;
3672 	mutex_init(&trans_pcie->fw_mon_data.mutex);
3673 #endif
3674 
3675 	iwl_dbg_tlv_init(trans);
3676 
3677 	return trans;
3678 
3679 out_free_ict:
3680 	iwl_pcie_free_ict(trans);
3681 out_no_pci:
3682 	destroy_workqueue(trans_pcie->rba.alloc_wq);
3683 out_free_trans:
3684 	iwl_trans_free(trans);
3685 	return ERR_PTR(ret);
3686 }
3687 
3688 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
3689 				u32 dst_addr, u64 src_addr, u32 byte_cnt)
3690 {
3691 	iwl_write_prph(trans, IMR_UREG_CHICK,
3692 		       iwl_read_prph(trans, IMR_UREG_CHICK) |
3693 		       IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK);
3694 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr);
3695 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB,
3696 		       (u32)(src_addr & 0xFFFFFFFF));
3697 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB,
3698 		       iwl_get_dma_hi_addr(src_addr));
3699 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt);
3700 	iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL,
3701 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS |
3702 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS |
3703 		       IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK);
3704 }
3705 
3706 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
3707 			    u32 dst_addr, u64 src_addr, u32 byte_cnt)
3708 {
3709 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3710 	int ret = -1;
3711 
3712 	trans_pcie->imr_status = IMR_D2S_REQUESTED;
3713 	iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt);
3714 	ret = wait_event_timeout(trans_pcie->imr_waitq,
3715 				 trans_pcie->imr_status !=
3716 				 IMR_D2S_REQUESTED, 5 * HZ);
3717 	if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) {
3718 		IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n");
3719 		iwl_trans_pcie_dump_regs(trans);
3720 		return -ETIMEDOUT;
3721 	}
3722 	trans_pcie->imr_status = IMR_D2S_IDLE;
3723 	return 0;
3724 }
3725