1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2022 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "mei/iwl-mei.h" 28 #include "internal.h" 29 #include "iwl-fh.h" 30 #include "iwl-context-info-gen3.h" 31 32 /* extended range in FW SRAM */ 33 #define IWL_FW_MEM_EXTENDED_START 0x40000 34 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35 36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37 { 38 #define PCI_DUMP_SIZE 352 39 #define PCI_MEM_DUMP_SIZE 64 40 #define PCI_PARENT_DUMP_SIZE 524 41 #define PREFIX_LEN 32 42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43 struct pci_dev *pdev = trans_pcie->pci_dev; 44 u32 i, pos, alloc_size, *ptr, *buf; 45 char *prefix; 46 47 if (trans_pcie->pcie_dbg_dumped_once) 48 return; 49 50 /* Should be a multiple of 4 */ 51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54 55 /* Alloc a max size buffer */ 56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60 61 buf = kmalloc(alloc_size, GFP_ATOMIC); 62 if (!buf) 63 return; 64 prefix = (char *)buf + alloc_size - PREFIX_LEN; 65 66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67 68 /* Print wifi device registers */ 69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70 IWL_ERR(trans, "iwlwifi device config registers:\n"); 71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72 if (pci_read_config_dword(pdev, i, ptr)) 73 goto err_read; 74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75 76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78 *ptr = iwl_read32(trans, i); 79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80 81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82 if (pos) { 83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85 if (pci_read_config_dword(pdev, pos + i, ptr)) 86 goto err_read; 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88 32, 4, buf, i, 0); 89 } 90 91 /* Print parent device registers next */ 92 if (!pdev->bus->self) 93 goto out; 94 95 pdev = pdev->bus->self; 96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97 98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99 pci_name(pdev)); 100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101 if (pci_read_config_dword(pdev, i, ptr)) 102 goto err_read; 103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104 105 /* Print root port AER registers */ 106 pos = 0; 107 pdev = pcie_find_root_port(pdev); 108 if (pdev) 109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110 if (pos) { 111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112 pci_name(pdev)); 113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115 if (pci_read_config_dword(pdev, pos + i, ptr)) 116 goto err_read; 117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118 4, buf, i, 0); 119 } 120 goto out; 121 122 err_read: 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 IWL_ERR(trans, "Read failed at 0x%X\n", i); 125 out: 126 trans_pcie->pcie_dbg_dumped_once = 1; 127 kfree(buf); 128 } 129 130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 131 bool retake_ownership) 132 { 133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 135 iwl_set_bit(trans, CSR_GP_CNTRL, 136 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 137 else 138 iwl_set_bit(trans, CSR_RESET, 139 CSR_RESET_REG_FLAG_SW_RESET); 140 usleep_range(5000, 6000); 141 142 if (retake_ownership) 143 return iwl_pcie_prepare_card_hw(trans); 144 145 return 0; 146 } 147 148 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 149 { 150 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 151 152 if (!fw_mon->size) 153 return; 154 155 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 156 fw_mon->physical); 157 158 fw_mon->block = NULL; 159 fw_mon->physical = 0; 160 fw_mon->size = 0; 161 } 162 163 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 164 u8 max_power, u8 min_power) 165 { 166 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 167 void *block = NULL; 168 dma_addr_t physical = 0; 169 u32 size = 0; 170 u8 power; 171 172 if (fw_mon->size) 173 return; 174 175 for (power = max_power; power >= min_power; power--) { 176 size = BIT(power); 177 block = dma_alloc_coherent(trans->dev, size, &physical, 178 GFP_KERNEL | __GFP_NOWARN); 179 if (!block) 180 continue; 181 182 IWL_INFO(trans, 183 "Allocated 0x%08x bytes for firmware monitor.\n", 184 size); 185 break; 186 } 187 188 if (WARN_ON_ONCE(!block)) 189 return; 190 191 if (power != max_power) 192 IWL_ERR(trans, 193 "Sorry - debug buffer is only %luK while you requested %luK\n", 194 (unsigned long)BIT(power - 10), 195 (unsigned long)BIT(max_power - 10)); 196 197 fw_mon->block = block; 198 fw_mon->physical = physical; 199 fw_mon->size = size; 200 } 201 202 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 203 { 204 if (!max_power) { 205 /* default max_power is maximum */ 206 max_power = 26; 207 } else { 208 max_power += 11; 209 } 210 211 if (WARN(max_power > 26, 212 "External buffer size for monitor is too big %d, check the FW TLV\n", 213 max_power)) 214 return; 215 216 if (trans->dbg.fw_mon.size) 217 return; 218 219 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 220 } 221 222 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 223 { 224 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 225 ((reg & 0x0000ffff) | (2 << 28))); 226 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 227 } 228 229 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 230 { 231 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 232 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 233 ((reg & 0x0000ffff) | (3 << 28))); 234 } 235 236 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 237 { 238 if (trans->cfg->apmg_not_supported) 239 return; 240 241 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 242 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 243 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 244 ~APMG_PS_CTRL_MSK_PWR_SRC); 245 else 246 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 247 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 248 ~APMG_PS_CTRL_MSK_PWR_SRC); 249 } 250 251 /* PCI registers */ 252 #define PCI_CFG_RETRY_TIMEOUT 0x041 253 254 void iwl_pcie_apm_config(struct iwl_trans *trans) 255 { 256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 257 u16 lctl; 258 u16 cap; 259 260 /* 261 * L0S states have been found to be unstable with our devices 262 * and in newer hardware they are not officially supported at 263 * all, so we must always set the L0S_DISABLED bit. 264 */ 265 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 266 267 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 268 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 269 270 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 271 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 272 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 273 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 274 trans->ltr_enabled ? "En" : "Dis"); 275 } 276 277 /* 278 * Start up NIC's basic functionality after it has been reset 279 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 280 * NOTE: This does not load uCode nor start the embedded processor 281 */ 282 static int iwl_pcie_apm_init(struct iwl_trans *trans) 283 { 284 int ret; 285 286 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 287 288 /* 289 * Use "set_bit" below rather than "write", to preserve any hardware 290 * bits already set by default after reset. 291 */ 292 293 /* Disable L0S exit timer (platform NMI Work/Around) */ 294 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 295 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 296 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 297 298 /* 299 * Disable L0s without affecting L1; 300 * don't wait for ICH L0s (ICH bug W/A) 301 */ 302 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 303 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 304 305 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 306 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 307 308 /* 309 * Enable HAP INTA (interrupt from management bus) to 310 * wake device's PCI Express link L1a -> L0s 311 */ 312 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 313 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 314 315 iwl_pcie_apm_config(trans); 316 317 /* Configure analog phase-lock-loop before activating to D0A */ 318 if (trans->trans_cfg->base_params->pll_cfg) 319 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 320 321 ret = iwl_finish_nic_init(trans); 322 if (ret) 323 return ret; 324 325 if (trans->cfg->host_interrupt_operation_mode) { 326 /* 327 * This is a bit of an abuse - This is needed for 7260 / 3160 328 * only check host_interrupt_operation_mode even if this is 329 * not related to host_interrupt_operation_mode. 330 * 331 * Enable the oscillator to count wake up time for L1 exit. This 332 * consumes slightly more power (100uA) - but allows to be sure 333 * that we wake up from L1 on time. 334 * 335 * This looks weird: read twice the same register, discard the 336 * value, set a bit, and yet again, read that same register 337 * just to discard the value. But that's the way the hardware 338 * seems to like it. 339 */ 340 iwl_read_prph(trans, OSC_CLK); 341 iwl_read_prph(trans, OSC_CLK); 342 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 343 iwl_read_prph(trans, OSC_CLK); 344 iwl_read_prph(trans, OSC_CLK); 345 } 346 347 /* 348 * Enable DMA clock and wait for it to stabilize. 349 * 350 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 351 * bits do not disable clocks. This preserves any hardware 352 * bits already set by default in "CLK_CTRL_REG" after reset. 353 */ 354 if (!trans->cfg->apmg_not_supported) { 355 iwl_write_prph(trans, APMG_CLK_EN_REG, 356 APMG_CLK_VAL_DMA_CLK_RQT); 357 udelay(20); 358 359 /* Disable L1-Active */ 360 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 361 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 362 363 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 364 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 365 APMG_RTC_INT_STT_RFKILL); 366 } 367 368 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 369 370 return 0; 371 } 372 373 /* 374 * Enable LP XTAL to avoid HW bug where device may consume much power if 375 * FW is not loaded after device reset. LP XTAL is disabled by default 376 * after device HW reset. Do it only if XTAL is fed by internal source. 377 * Configure device's "persistence" mode to avoid resetting XTAL again when 378 * SHRD_HW_RST occurs in S3. 379 */ 380 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 381 { 382 int ret; 383 u32 apmg_gp1_reg; 384 u32 apmg_xtal_cfg_reg; 385 u32 dl_cfg_reg; 386 387 /* Force XTAL ON */ 388 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 389 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 390 391 ret = iwl_trans_pcie_sw_reset(trans, true); 392 393 if (!ret) 394 ret = iwl_finish_nic_init(trans); 395 396 if (WARN_ON(ret)) { 397 /* Release XTAL ON request */ 398 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 399 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 400 return; 401 } 402 403 /* 404 * Clear "disable persistence" to avoid LP XTAL resetting when 405 * SHRD_HW_RST is applied in S3. 406 */ 407 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 408 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 409 410 /* 411 * Force APMG XTAL to be active to prevent its disabling by HW 412 * caused by APMG idle state. 413 */ 414 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 415 SHR_APMG_XTAL_CFG_REG); 416 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 417 apmg_xtal_cfg_reg | 418 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 419 420 ret = iwl_trans_pcie_sw_reset(trans, true); 421 if (ret) 422 IWL_ERR(trans, 423 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 424 425 /* Enable LP XTAL by indirect access through CSR */ 426 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 427 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 428 SHR_APMG_GP1_WF_XTAL_LP_EN | 429 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 430 431 /* Clear delay line clock power up */ 432 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 433 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 434 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 435 436 /* 437 * Enable persistence mode to avoid LP XTAL resetting when 438 * SHRD_HW_RST is applied in S3. 439 */ 440 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 441 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 442 443 /* 444 * Clear "initialization complete" bit to move adapter from 445 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 446 */ 447 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 448 449 /* Activates XTAL resources monitor */ 450 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 451 CSR_MONITOR_XTAL_RESOURCES); 452 453 /* Release XTAL ON request */ 454 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 455 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 456 udelay(10); 457 458 /* Release APMG XTAL */ 459 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 460 apmg_xtal_cfg_reg & 461 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 462 } 463 464 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 465 { 466 int ret; 467 468 /* stop device's busmaster DMA activity */ 469 470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 471 iwl_set_bit(trans, CSR_GP_CNTRL, 472 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 473 474 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 475 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 476 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 477 100); 478 msleep(100); 479 } else { 480 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 481 482 ret = iwl_poll_bit(trans, CSR_RESET, 483 CSR_RESET_REG_FLAG_MASTER_DISABLED, 484 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 485 } 486 487 if (ret < 0) 488 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 489 490 IWL_DEBUG_INFO(trans, "stop master\n"); 491 } 492 493 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 494 { 495 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 496 497 if (op_mode_leave) { 498 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 499 iwl_pcie_apm_init(trans); 500 501 /* inform ME that we are leaving */ 502 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 503 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 504 APMG_PCIDEV_STT_VAL_WAKE_ME); 505 else if (trans->trans_cfg->device_family >= 506 IWL_DEVICE_FAMILY_8000) { 507 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 508 CSR_RESET_LINK_PWR_MGMT_DISABLED); 509 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 510 CSR_HW_IF_CONFIG_REG_PREPARE | 511 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 512 mdelay(1); 513 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 514 CSR_RESET_LINK_PWR_MGMT_DISABLED); 515 } 516 mdelay(5); 517 } 518 519 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 520 521 /* Stop device's DMA activity */ 522 iwl_pcie_apm_stop_master(trans); 523 524 if (trans->cfg->lp_xtal_workaround) { 525 iwl_pcie_apm_lp_xtal_enable(trans); 526 return; 527 } 528 529 iwl_trans_pcie_sw_reset(trans, false); 530 531 /* 532 * Clear "initialization complete" bit to move adapter from 533 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 534 */ 535 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 536 } 537 538 static int iwl_pcie_nic_init(struct iwl_trans *trans) 539 { 540 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 541 int ret; 542 543 /* nic_init */ 544 spin_lock_bh(&trans_pcie->irq_lock); 545 ret = iwl_pcie_apm_init(trans); 546 spin_unlock_bh(&trans_pcie->irq_lock); 547 548 if (ret) 549 return ret; 550 551 iwl_pcie_set_pwr(trans, false); 552 553 iwl_op_mode_nic_config(trans->op_mode); 554 555 /* Allocate the RX queue, or reset if it is already allocated */ 556 ret = iwl_pcie_rx_init(trans); 557 if (ret) 558 return ret; 559 560 /* Allocate or reset and init all Tx and Command queues */ 561 if (iwl_pcie_tx_init(trans)) { 562 iwl_pcie_rx_free(trans); 563 return -ENOMEM; 564 } 565 566 if (trans->trans_cfg->base_params->shadow_reg_enable) { 567 /* enable shadow regs in HW */ 568 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 569 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 570 } 571 572 return 0; 573 } 574 575 #define HW_READY_TIMEOUT (50) 576 577 /* Note: returns poll_bit return value, which is >= 0 if success */ 578 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 579 { 580 int ret; 581 582 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 583 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 584 585 /* See if we got it */ 586 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 587 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 588 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 589 HW_READY_TIMEOUT); 590 591 if (ret >= 0) 592 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 593 594 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 595 return ret; 596 } 597 598 /* Note: returns standard 0/-ERROR code */ 599 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 600 { 601 int ret; 602 int t = 0; 603 int iter; 604 605 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 606 607 ret = iwl_pcie_set_hw_ready(trans); 608 /* If the card is ready, exit 0 */ 609 if (ret >= 0) { 610 trans->csme_own = false; 611 return 0; 612 } 613 614 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 615 CSR_RESET_LINK_PWR_MGMT_DISABLED); 616 usleep_range(1000, 2000); 617 618 for (iter = 0; iter < 10; iter++) { 619 /* If HW is not ready, prepare the conditions to check again */ 620 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 621 CSR_HW_IF_CONFIG_REG_PREPARE); 622 623 do { 624 ret = iwl_pcie_set_hw_ready(trans); 625 if (ret >= 0) { 626 trans->csme_own = false; 627 return 0; 628 } 629 630 if (iwl_mei_is_connected()) { 631 IWL_DEBUG_INFO(trans, 632 "Couldn't prepare the card but SAP is connected\n"); 633 trans->csme_own = true; 634 if (trans->trans_cfg->device_family != 635 IWL_DEVICE_FAMILY_9000) 636 IWL_ERR(trans, 637 "SAP not supported for this NIC family\n"); 638 639 return -EBUSY; 640 } 641 642 usleep_range(200, 1000); 643 t += 200; 644 } while (t < 150000); 645 msleep(25); 646 } 647 648 IWL_ERR(trans, "Couldn't prepare the card\n"); 649 650 return ret; 651 } 652 653 /* 654 * ucode 655 */ 656 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 657 u32 dst_addr, dma_addr_t phy_addr, 658 u32 byte_cnt) 659 { 660 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 661 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 662 663 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 664 dst_addr); 665 666 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 667 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 668 669 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 670 (iwl_get_dma_hi_addr(phy_addr) 671 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 672 673 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 674 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 675 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 676 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 677 678 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 679 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 680 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 681 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 682 } 683 684 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 685 u32 dst_addr, dma_addr_t phy_addr, 686 u32 byte_cnt) 687 { 688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 689 int ret; 690 691 trans_pcie->ucode_write_complete = false; 692 693 if (!iwl_trans_grab_nic_access(trans)) 694 return -EIO; 695 696 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 697 byte_cnt); 698 iwl_trans_release_nic_access(trans); 699 700 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 701 trans_pcie->ucode_write_complete, 5 * HZ); 702 if (!ret) { 703 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 704 iwl_trans_pcie_dump_regs(trans); 705 return -ETIMEDOUT; 706 } 707 708 return 0; 709 } 710 711 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 712 const struct fw_desc *section) 713 { 714 u8 *v_addr; 715 dma_addr_t p_addr; 716 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 717 int ret = 0; 718 719 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 720 section_num); 721 722 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 723 GFP_KERNEL | __GFP_NOWARN); 724 if (!v_addr) { 725 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 726 chunk_sz = PAGE_SIZE; 727 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 728 &p_addr, GFP_KERNEL); 729 if (!v_addr) 730 return -ENOMEM; 731 } 732 733 for (offset = 0; offset < section->len; offset += chunk_sz) { 734 u32 copy_size, dst_addr; 735 bool extended_addr = false; 736 737 copy_size = min_t(u32, chunk_sz, section->len - offset); 738 dst_addr = section->offset + offset; 739 740 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 741 dst_addr <= IWL_FW_MEM_EXTENDED_END) 742 extended_addr = true; 743 744 if (extended_addr) 745 iwl_set_bits_prph(trans, LMPM_CHICK, 746 LMPM_CHICK_EXTENDED_ADDR_SPACE); 747 748 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 749 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 750 copy_size); 751 752 if (extended_addr) 753 iwl_clear_bits_prph(trans, LMPM_CHICK, 754 LMPM_CHICK_EXTENDED_ADDR_SPACE); 755 756 if (ret) { 757 IWL_ERR(trans, 758 "Could not load the [%d] uCode section\n", 759 section_num); 760 break; 761 } 762 } 763 764 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 765 return ret; 766 } 767 768 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 769 const struct fw_img *image, 770 int cpu, 771 int *first_ucode_section) 772 { 773 int shift_param; 774 int i, ret = 0, sec_num = 0x1; 775 u32 val, last_read_idx = 0; 776 777 if (cpu == 1) { 778 shift_param = 0; 779 *first_ucode_section = 0; 780 } else { 781 shift_param = 16; 782 (*first_ucode_section)++; 783 } 784 785 for (i = *first_ucode_section; i < image->num_sec; i++) { 786 last_read_idx = i; 787 788 /* 789 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 790 * CPU1 to CPU2. 791 * PAGING_SEPARATOR_SECTION delimiter - separate between 792 * CPU2 non paged to CPU2 paging sec. 793 */ 794 if (!image->sec[i].data || 795 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 796 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 797 IWL_DEBUG_FW(trans, 798 "Break since Data not valid or Empty section, sec = %d\n", 799 i); 800 break; 801 } 802 803 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 804 if (ret) 805 return ret; 806 807 /* Notify ucode of loaded section number and status */ 808 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 809 val = val | (sec_num << shift_param); 810 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 811 812 sec_num = (sec_num << 1) | 0x1; 813 } 814 815 *first_ucode_section = last_read_idx; 816 817 iwl_enable_interrupts(trans); 818 819 if (trans->trans_cfg->use_tfh) { 820 if (cpu == 1) 821 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 822 0xFFFF); 823 else 824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825 0xFFFFFFFF); 826 } else { 827 if (cpu == 1) 828 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 829 0xFFFF); 830 else 831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832 0xFFFFFFFF); 833 } 834 835 return 0; 836 } 837 838 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 839 const struct fw_img *image, 840 int cpu, 841 int *first_ucode_section) 842 { 843 int i, ret = 0; 844 u32 last_read_idx = 0; 845 846 if (cpu == 1) 847 *first_ucode_section = 0; 848 else 849 (*first_ucode_section)++; 850 851 for (i = *first_ucode_section; i < image->num_sec; i++) { 852 last_read_idx = i; 853 854 /* 855 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 856 * CPU1 to CPU2. 857 * PAGING_SEPARATOR_SECTION delimiter - separate between 858 * CPU2 non paged to CPU2 paging sec. 859 */ 860 if (!image->sec[i].data || 861 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 862 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 863 IWL_DEBUG_FW(trans, 864 "Break since Data not valid or Empty section, sec = %d\n", 865 i); 866 break; 867 } 868 869 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 870 if (ret) 871 return ret; 872 } 873 874 *first_ucode_section = last_read_idx; 875 876 return 0; 877 } 878 879 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 880 { 881 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 882 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 883 &trans->dbg.fw_mon_cfg[alloc_id]; 884 struct iwl_dram_data *frag; 885 886 if (!iwl_trans_dbg_ini_valid(trans)) 887 return; 888 889 if (le32_to_cpu(fw_mon_cfg->buf_location) == 890 IWL_FW_INI_LOCATION_SRAM_PATH) { 891 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 892 /* set sram monitor by enabling bit 7 */ 893 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 894 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 895 896 return; 897 } 898 899 if (le32_to_cpu(fw_mon_cfg->buf_location) != 900 IWL_FW_INI_LOCATION_DRAM_PATH || 901 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 902 return; 903 904 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 905 906 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 907 alloc_id); 908 909 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 910 frag->physical >> MON_BUFF_SHIFT_VER2); 911 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 912 (frag->physical + frag->size - 256) >> 913 MON_BUFF_SHIFT_VER2); 914 } 915 916 void iwl_pcie_apply_destination(struct iwl_trans *trans) 917 { 918 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 919 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 920 int i; 921 922 if (iwl_trans_dbg_ini_valid(trans)) { 923 iwl_pcie_apply_destination_ini(trans); 924 return; 925 } 926 927 IWL_INFO(trans, "Applying debug destination %s\n", 928 get_fw_dbg_mode_string(dest->monitor_mode)); 929 930 if (dest->monitor_mode == EXTERNAL_MODE) 931 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 932 else 933 IWL_WARN(trans, "PCI should have external buffer debug\n"); 934 935 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 936 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 937 u32 val = le32_to_cpu(dest->reg_ops[i].val); 938 939 switch (dest->reg_ops[i].op) { 940 case CSR_ASSIGN: 941 iwl_write32(trans, addr, val); 942 break; 943 case CSR_SETBIT: 944 iwl_set_bit(trans, addr, BIT(val)); 945 break; 946 case CSR_CLEARBIT: 947 iwl_clear_bit(trans, addr, BIT(val)); 948 break; 949 case PRPH_ASSIGN: 950 iwl_write_prph(trans, addr, val); 951 break; 952 case PRPH_SETBIT: 953 iwl_set_bits_prph(trans, addr, BIT(val)); 954 break; 955 case PRPH_CLEARBIT: 956 iwl_clear_bits_prph(trans, addr, BIT(val)); 957 break; 958 case PRPH_BLOCKBIT: 959 if (iwl_read_prph(trans, addr) & BIT(val)) { 960 IWL_ERR(trans, 961 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 962 val, addr); 963 goto monitor; 964 } 965 break; 966 default: 967 IWL_ERR(trans, "FW debug - unknown OP %d\n", 968 dest->reg_ops[i].op); 969 break; 970 } 971 } 972 973 monitor: 974 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 975 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 976 fw_mon->physical >> dest->base_shift); 977 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 978 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 979 (fw_mon->physical + fw_mon->size - 980 256) >> dest->end_shift); 981 else 982 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 983 (fw_mon->physical + fw_mon->size) >> 984 dest->end_shift); 985 } 986 } 987 988 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 989 const struct fw_img *image) 990 { 991 int ret = 0; 992 int first_ucode_section; 993 994 IWL_DEBUG_FW(trans, "working with %s CPU\n", 995 image->is_dual_cpus ? "Dual" : "Single"); 996 997 /* load to FW the binary non secured sections of CPU1 */ 998 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 999 if (ret) 1000 return ret; 1001 1002 if (image->is_dual_cpus) { 1003 /* set CPU2 header address */ 1004 iwl_write_prph(trans, 1005 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1006 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1007 1008 /* load to FW the binary sections of CPU2 */ 1009 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1010 &first_ucode_section); 1011 if (ret) 1012 return ret; 1013 } 1014 1015 if (iwl_pcie_dbg_on(trans)) 1016 iwl_pcie_apply_destination(trans); 1017 1018 iwl_enable_interrupts(trans); 1019 1020 /* release CPU reset */ 1021 iwl_write32(trans, CSR_RESET, 0); 1022 1023 return 0; 1024 } 1025 1026 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1027 const struct fw_img *image) 1028 { 1029 int ret = 0; 1030 int first_ucode_section; 1031 1032 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1033 image->is_dual_cpus ? "Dual" : "Single"); 1034 1035 if (iwl_pcie_dbg_on(trans)) 1036 iwl_pcie_apply_destination(trans); 1037 1038 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1039 iwl_read_prph(trans, WFPM_GP2)); 1040 1041 /* 1042 * Set default value. On resume reading the values that were 1043 * zeored can provide debug data on the resume flow. 1044 * This is for debugging only and has no functional impact. 1045 */ 1046 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1047 1048 /* configure the ucode to be ready to get the secured image */ 1049 /* release CPU reset */ 1050 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1051 1052 /* load to FW the binary Secured sections of CPU1 */ 1053 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1054 &first_ucode_section); 1055 if (ret) 1056 return ret; 1057 1058 /* load to FW the binary sections of CPU2 */ 1059 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1060 &first_ucode_section); 1061 } 1062 1063 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1064 { 1065 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1066 bool hw_rfkill = iwl_is_rfkill_set(trans); 1067 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1068 bool report; 1069 1070 if (hw_rfkill) { 1071 set_bit(STATUS_RFKILL_HW, &trans->status); 1072 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1073 } else { 1074 clear_bit(STATUS_RFKILL_HW, &trans->status); 1075 if (trans_pcie->opmode_down) 1076 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1077 } 1078 1079 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080 1081 if (prev != report) 1082 iwl_trans_pcie_rf_kill(trans, report); 1083 1084 return hw_rfkill; 1085 } 1086 1087 struct iwl_causes_list { 1088 u16 mask_reg; 1089 u8 bit; 1090 u8 addr; 1091 }; 1092 1093 #define IWL_CAUSE(reg, mask) \ 1094 { \ 1095 .mask_reg = reg, \ 1096 .bit = ilog2(mask), \ 1097 .addr = ilog2(mask) + \ 1098 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1099 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1100 0xffff), /* causes overflow warning */ \ 1101 } 1102 1103 static const struct iwl_causes_list causes_list_common[] = { 1104 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1105 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1106 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1107 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1108 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1109 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1110 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1111 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1112 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1113 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1114 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1115 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1116 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1117 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1118 }; 1119 1120 static const struct iwl_causes_list causes_list_pre_bz[] = { 1121 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1122 }; 1123 1124 static const struct iwl_causes_list causes_list_bz[] = { 1125 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1126 }; 1127 1128 static void iwl_pcie_map_list(struct iwl_trans *trans, 1129 const struct iwl_causes_list *causes, 1130 int arr_size, int val) 1131 { 1132 int i; 1133 1134 for (i = 0; i < arr_size; i++) { 1135 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1136 iwl_clear_bit(trans, causes[i].mask_reg, 1137 BIT(causes[i].bit)); 1138 } 1139 } 1140 1141 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1142 { 1143 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1144 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1145 /* 1146 * Access all non RX causes and map them to the default irq. 1147 * In case we are missing at least one interrupt vector, 1148 * the first interrupt vector will serve non-RX and FBQ causes. 1149 */ 1150 iwl_pcie_map_list(trans, causes_list_common, 1151 ARRAY_SIZE(causes_list_common), val); 1152 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1153 iwl_pcie_map_list(trans, causes_list_bz, 1154 ARRAY_SIZE(causes_list_bz), val); 1155 else 1156 iwl_pcie_map_list(trans, causes_list_pre_bz, 1157 ARRAY_SIZE(causes_list_pre_bz), val); 1158 } 1159 1160 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1161 { 1162 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1163 u32 offset = 1164 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1165 u32 val, idx; 1166 1167 /* 1168 * The first RX queue - fallback queue, which is designated for 1169 * management frame, command responses etc, is always mapped to the 1170 * first interrupt vector. The other RX queues are mapped to 1171 * the other (N - 2) interrupt vectors. 1172 */ 1173 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1174 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1175 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1176 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1177 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1178 } 1179 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1180 1181 val = MSIX_FH_INT_CAUSES_Q(0); 1182 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1183 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1184 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1185 1186 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1187 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1188 } 1189 1190 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1191 { 1192 struct iwl_trans *trans = trans_pcie->trans; 1193 1194 if (!trans_pcie->msix_enabled) { 1195 if (trans->trans_cfg->mq_rx_supported && 1196 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1197 iwl_write_umac_prph(trans, UREG_CHICK, 1198 UREG_CHICK_MSI_ENABLE); 1199 return; 1200 } 1201 /* 1202 * The IVAR table needs to be configured again after reset, 1203 * but if the device is disabled, we can't write to 1204 * prph. 1205 */ 1206 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1207 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1208 1209 /* 1210 * Each cause from the causes list above and the RX causes is 1211 * represented as a byte in the IVAR table. The first nibble 1212 * represents the bound interrupt vector of the cause, the second 1213 * represents no auto clear for this cause. This will be set if its 1214 * interrupt vector is bound to serve other causes. 1215 */ 1216 iwl_pcie_map_rx_causes(trans); 1217 1218 iwl_pcie_map_non_rx_causes(trans); 1219 } 1220 1221 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1222 { 1223 struct iwl_trans *trans = trans_pcie->trans; 1224 1225 iwl_pcie_conf_msix_hw(trans_pcie); 1226 1227 if (!trans_pcie->msix_enabled) 1228 return; 1229 1230 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1231 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1232 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1233 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1234 } 1235 1236 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1237 { 1238 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1239 1240 lockdep_assert_held(&trans_pcie->mutex); 1241 1242 if (trans_pcie->is_down) 1243 return; 1244 1245 trans_pcie->is_down = true; 1246 1247 /* tell the device to stop sending interrupts */ 1248 iwl_disable_interrupts(trans); 1249 1250 /* device going down, Stop using ICT table */ 1251 iwl_pcie_disable_ict(trans); 1252 1253 /* 1254 * If a HW restart happens during firmware loading, 1255 * then the firmware loading might call this function 1256 * and later it might be called again due to the 1257 * restart. So don't process again if the device is 1258 * already dead. 1259 */ 1260 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1261 IWL_DEBUG_INFO(trans, 1262 "DEVICE_ENABLED bit was set and is now cleared\n"); 1263 iwl_pcie_rx_napi_sync(trans); 1264 iwl_pcie_tx_stop(trans); 1265 iwl_pcie_rx_stop(trans); 1266 1267 /* Power-down device's busmaster DMA clocks */ 1268 if (!trans->cfg->apmg_not_supported) { 1269 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1270 APMG_CLK_VAL_DMA_CLK_RQT); 1271 udelay(5); 1272 } 1273 } 1274 1275 /* Make sure (redundant) we've released our request to stay awake */ 1276 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1277 iwl_clear_bit(trans, CSR_GP_CNTRL, 1278 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1279 else 1280 iwl_clear_bit(trans, CSR_GP_CNTRL, 1281 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1282 1283 /* Stop the device, and put it in low power state */ 1284 iwl_pcie_apm_stop(trans, false); 1285 1286 /* re-take ownership to prevent other users from stealing the device */ 1287 iwl_trans_pcie_sw_reset(trans, true); 1288 1289 /* 1290 * Upon stop, the IVAR table gets erased, so msi-x won't 1291 * work. This causes a bug in RF-KILL flows, since the interrupt 1292 * that enables radio won't fire on the correct irq, and the 1293 * driver won't be able to handle the interrupt. 1294 * Configure the IVAR table again after reset. 1295 */ 1296 iwl_pcie_conf_msix_hw(trans_pcie); 1297 1298 /* 1299 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1300 * This is a bug in certain verions of the hardware. 1301 * Certain devices also keep sending HW RF kill interrupt all 1302 * the time, unless the interrupt is ACKed even if the interrupt 1303 * should be masked. Re-ACK all the interrupts here. 1304 */ 1305 iwl_disable_interrupts(trans); 1306 1307 /* clear all status bits */ 1308 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1309 clear_bit(STATUS_INT_ENABLED, &trans->status); 1310 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1311 1312 /* 1313 * Even if we stop the HW, we still want the RF kill 1314 * interrupt 1315 */ 1316 iwl_enable_rfkill_int(trans); 1317 } 1318 1319 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1320 { 1321 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1322 1323 if (trans_pcie->msix_enabled) { 1324 int i; 1325 1326 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1327 synchronize_irq(trans_pcie->msix_entries[i].vector); 1328 } else { 1329 synchronize_irq(trans_pcie->pci_dev->irq); 1330 } 1331 } 1332 1333 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1334 const struct fw_img *fw, bool run_in_rfkill) 1335 { 1336 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1337 bool hw_rfkill; 1338 int ret; 1339 1340 /* This may fail if AMT took ownership of the device */ 1341 if (iwl_pcie_prepare_card_hw(trans)) { 1342 IWL_WARN(trans, "Exit HW not ready\n"); 1343 return -EIO; 1344 } 1345 1346 iwl_enable_rfkill_int(trans); 1347 1348 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1349 1350 /* 1351 * We enabled the RF-Kill interrupt and the handler may very 1352 * well be running. Disable the interrupts to make sure no other 1353 * interrupt can be fired. 1354 */ 1355 iwl_disable_interrupts(trans); 1356 1357 /* Make sure it finished running */ 1358 iwl_pcie_synchronize_irqs(trans); 1359 1360 mutex_lock(&trans_pcie->mutex); 1361 1362 /* If platform's RF_KILL switch is NOT set to KILL */ 1363 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1364 if (hw_rfkill && !run_in_rfkill) { 1365 ret = -ERFKILL; 1366 goto out; 1367 } 1368 1369 /* Someone called stop_device, don't try to start_fw */ 1370 if (trans_pcie->is_down) { 1371 IWL_WARN(trans, 1372 "Can't start_fw since the HW hasn't been started\n"); 1373 ret = -EIO; 1374 goto out; 1375 } 1376 1377 /* make sure rfkill handshake bits are cleared */ 1378 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1379 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1380 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1381 1382 /* clear (again), then enable host interrupts */ 1383 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1384 1385 ret = iwl_pcie_nic_init(trans); 1386 if (ret) { 1387 IWL_ERR(trans, "Unable to init nic\n"); 1388 goto out; 1389 } 1390 1391 /* 1392 * Now, we load the firmware and don't want to be interrupted, even 1393 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1394 * FH_TX interrupt which is needed to load the firmware). If the 1395 * RF-Kill switch is toggled, we will find out after having loaded 1396 * the firmware and return the proper value to the caller. 1397 */ 1398 iwl_enable_fw_load_int(trans); 1399 1400 /* really make sure rfkill handshake bits are cleared */ 1401 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1402 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1403 1404 /* Load the given image to the HW */ 1405 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1406 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1407 else 1408 ret = iwl_pcie_load_given_ucode(trans, fw); 1409 1410 /* re-check RF-Kill state since we may have missed the interrupt */ 1411 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1412 if (hw_rfkill && !run_in_rfkill) 1413 ret = -ERFKILL; 1414 1415 out: 1416 mutex_unlock(&trans_pcie->mutex); 1417 return ret; 1418 } 1419 1420 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1421 { 1422 iwl_pcie_reset_ict(trans); 1423 iwl_pcie_tx_start(trans, scd_addr); 1424 } 1425 1426 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1427 bool was_in_rfkill) 1428 { 1429 bool hw_rfkill; 1430 1431 /* 1432 * Check again since the RF kill state may have changed while 1433 * all the interrupts were disabled, in this case we couldn't 1434 * receive the RF kill interrupt and update the state in the 1435 * op_mode. 1436 * Don't call the op_mode if the rkfill state hasn't changed. 1437 * This allows the op_mode to call stop_device from the rfkill 1438 * notification without endless recursion. Under very rare 1439 * circumstances, we might have a small recursion if the rfkill 1440 * state changed exactly now while we were called from stop_device. 1441 * This is very unlikely but can happen and is supported. 1442 */ 1443 hw_rfkill = iwl_is_rfkill_set(trans); 1444 if (hw_rfkill) { 1445 set_bit(STATUS_RFKILL_HW, &trans->status); 1446 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1447 } else { 1448 clear_bit(STATUS_RFKILL_HW, &trans->status); 1449 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1450 } 1451 if (hw_rfkill != was_in_rfkill) 1452 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1453 } 1454 1455 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1456 { 1457 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1458 bool was_in_rfkill; 1459 1460 iwl_op_mode_time_point(trans->op_mode, 1461 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1462 NULL); 1463 1464 mutex_lock(&trans_pcie->mutex); 1465 trans_pcie->opmode_down = true; 1466 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1467 _iwl_trans_pcie_stop_device(trans); 1468 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1469 mutex_unlock(&trans_pcie->mutex); 1470 } 1471 1472 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1473 { 1474 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1475 IWL_TRANS_GET_PCIE_TRANS(trans); 1476 1477 lockdep_assert_held(&trans_pcie->mutex); 1478 1479 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1480 state ? "disabled" : "enabled"); 1481 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1482 if (trans->trans_cfg->gen2) 1483 _iwl_trans_pcie_gen2_stop_device(trans); 1484 else 1485 _iwl_trans_pcie_stop_device(trans); 1486 } 1487 } 1488 1489 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1490 bool test, bool reset) 1491 { 1492 iwl_disable_interrupts(trans); 1493 1494 /* 1495 * in testing mode, the host stays awake and the 1496 * hardware won't be reset (not even partially) 1497 */ 1498 if (test) 1499 return; 1500 1501 iwl_pcie_disable_ict(trans); 1502 1503 iwl_pcie_synchronize_irqs(trans); 1504 1505 iwl_clear_bit(trans, CSR_GP_CNTRL, 1506 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1507 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1508 1509 if (reset) { 1510 /* 1511 * reset TX queues -- some of their registers reset during S3 1512 * so if we don't reset everything here the D3 image would try 1513 * to execute some invalid memory upon resume 1514 */ 1515 iwl_trans_pcie_tx_reset(trans); 1516 } 1517 1518 iwl_pcie_set_pwr(trans, true); 1519 } 1520 1521 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1522 { 1523 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1524 int ret; 1525 1526 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1527 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1528 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1529 UREG_DOORBELL_TO_ISR6_RESUME); 1530 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1531 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1532 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1533 CSR_IPC_SLEEP_CONTROL_RESUME); 1534 else 1535 return 0; 1536 1537 ret = wait_event_timeout(trans_pcie->sx_waitq, 1538 trans_pcie->sx_complete, 2 * HZ); 1539 1540 /* Invalidate it toward next suspend or resume */ 1541 trans_pcie->sx_complete = false; 1542 1543 if (!ret) { 1544 IWL_ERR(trans, "Timeout %s D3\n", 1545 suspend ? "entering" : "exiting"); 1546 return -ETIMEDOUT; 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1553 bool reset) 1554 { 1555 int ret; 1556 1557 if (!reset) 1558 /* Enable persistence mode to avoid reset */ 1559 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1560 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1561 1562 ret = iwl_pcie_d3_handshake(trans, true); 1563 if (ret) 1564 return ret; 1565 1566 iwl_pcie_d3_complete_suspend(trans, test, reset); 1567 1568 return 0; 1569 } 1570 1571 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1572 enum iwl_d3_status *status, 1573 bool test, bool reset) 1574 { 1575 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1576 u32 val; 1577 int ret; 1578 1579 if (test) { 1580 iwl_enable_interrupts(trans); 1581 *status = IWL_D3_STATUS_ALIVE; 1582 ret = 0; 1583 goto out; 1584 } 1585 1586 iwl_set_bit(trans, CSR_GP_CNTRL, 1587 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1588 1589 ret = iwl_finish_nic_init(trans); 1590 if (ret) 1591 return ret; 1592 1593 /* 1594 * Reconfigure IVAR table in case of MSIX or reset ict table in 1595 * MSI mode since HW reset erased it. 1596 * Also enables interrupts - none will happen as 1597 * the device doesn't know we're waking it up, only when 1598 * the opmode actually tells it after this call. 1599 */ 1600 iwl_pcie_conf_msix_hw(trans_pcie); 1601 if (!trans_pcie->msix_enabled) 1602 iwl_pcie_reset_ict(trans); 1603 iwl_enable_interrupts(trans); 1604 1605 iwl_pcie_set_pwr(trans, false); 1606 1607 if (!reset) { 1608 iwl_clear_bit(trans, CSR_GP_CNTRL, 1609 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1610 } else { 1611 iwl_trans_pcie_tx_reset(trans); 1612 1613 ret = iwl_pcie_rx_init(trans); 1614 if (ret) { 1615 IWL_ERR(trans, 1616 "Failed to resume the device (RX reset)\n"); 1617 return ret; 1618 } 1619 } 1620 1621 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1622 iwl_read_umac_prph(trans, WFPM_GP2)); 1623 1624 val = iwl_read32(trans, CSR_RESET); 1625 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1626 *status = IWL_D3_STATUS_RESET; 1627 else 1628 *status = IWL_D3_STATUS_ALIVE; 1629 1630 out: 1631 if (*status == IWL_D3_STATUS_ALIVE) 1632 ret = iwl_pcie_d3_handshake(trans, false); 1633 1634 return ret; 1635 } 1636 1637 static void 1638 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1639 struct iwl_trans *trans, 1640 const struct iwl_cfg_trans_params *cfg_trans) 1641 { 1642 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1643 int max_irqs, num_irqs, i, ret; 1644 u16 pci_cmd; 1645 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1646 1647 if (!cfg_trans->mq_rx_supported) 1648 goto enable_msi; 1649 1650 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1651 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1652 1653 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1654 for (i = 0; i < max_irqs; i++) 1655 trans_pcie->msix_entries[i].entry = i; 1656 1657 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1658 MSIX_MIN_INTERRUPT_VECTORS, 1659 max_irqs); 1660 if (num_irqs < 0) { 1661 IWL_DEBUG_INFO(trans, 1662 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1663 num_irqs); 1664 goto enable_msi; 1665 } 1666 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1667 1668 IWL_DEBUG_INFO(trans, 1669 "MSI-X enabled. %d interrupt vectors were allocated\n", 1670 num_irqs); 1671 1672 /* 1673 * In case the OS provides fewer interrupts than requested, different 1674 * causes will share the same interrupt vector as follows: 1675 * One interrupt less: non rx causes shared with FBQ. 1676 * Two interrupts less: non rx causes shared with FBQ and RSS. 1677 * More than two interrupts: we will use fewer RSS queues. 1678 */ 1679 if (num_irqs <= max_irqs - 2) { 1680 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1681 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1682 IWL_SHARED_IRQ_FIRST_RSS; 1683 } else if (num_irqs == max_irqs - 1) { 1684 trans_pcie->trans->num_rx_queues = num_irqs; 1685 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1686 } else { 1687 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1688 } 1689 1690 IWL_DEBUG_INFO(trans, 1691 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1692 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1693 1694 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1695 1696 trans_pcie->alloc_vecs = num_irqs; 1697 trans_pcie->msix_enabled = true; 1698 return; 1699 1700 enable_msi: 1701 ret = pci_enable_msi(pdev); 1702 if (ret) { 1703 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1704 /* enable rfkill interrupt: hw bug w/a */ 1705 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1706 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1707 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1708 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1709 } 1710 } 1711 } 1712 1713 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1714 { 1715 int iter_rx_q, i, ret, cpu, offset; 1716 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1717 1718 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1719 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1720 offset = 1 + i; 1721 for (; i < iter_rx_q ; i++) { 1722 /* 1723 * Get the cpu prior to the place to search 1724 * (i.e. return will be > i - 1). 1725 */ 1726 cpu = cpumask_next(i - offset, cpu_online_mask); 1727 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1728 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1729 &trans_pcie->affinity_mask[i]); 1730 if (ret) 1731 IWL_ERR(trans_pcie->trans, 1732 "Failed to set affinity mask for IRQ %d\n", 1733 trans_pcie->msix_entries[i].vector); 1734 } 1735 } 1736 1737 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1738 struct iwl_trans_pcie *trans_pcie) 1739 { 1740 int i; 1741 1742 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1743 int ret; 1744 struct msix_entry *msix_entry; 1745 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1746 1747 if (!qname) 1748 return -ENOMEM; 1749 1750 msix_entry = &trans_pcie->msix_entries[i]; 1751 ret = devm_request_threaded_irq(&pdev->dev, 1752 msix_entry->vector, 1753 iwl_pcie_msix_isr, 1754 (i == trans_pcie->def_irq) ? 1755 iwl_pcie_irq_msix_handler : 1756 iwl_pcie_irq_rx_msix_handler, 1757 IRQF_SHARED, 1758 qname, 1759 msix_entry); 1760 if (ret) { 1761 IWL_ERR(trans_pcie->trans, 1762 "Error allocating IRQ %d\n", i); 1763 1764 return ret; 1765 } 1766 } 1767 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1768 1769 return 0; 1770 } 1771 1772 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1773 { 1774 u32 hpm, wprot; 1775 1776 switch (trans->trans_cfg->device_family) { 1777 case IWL_DEVICE_FAMILY_9000: 1778 wprot = PREG_PRPH_WPROT_9000; 1779 break; 1780 case IWL_DEVICE_FAMILY_22000: 1781 wprot = PREG_PRPH_WPROT_22000; 1782 break; 1783 default: 1784 return 0; 1785 } 1786 1787 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1788 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1789 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1790 1791 if (wprot_val & PREG_WFPM_ACCESS) { 1792 IWL_ERR(trans, 1793 "Error, can not clear persistence bit\n"); 1794 return -EPERM; 1795 } 1796 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1797 hpm & ~PERSISTENCE_BIT); 1798 } 1799 1800 return 0; 1801 } 1802 1803 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1804 { 1805 int ret; 1806 1807 ret = iwl_finish_nic_init(trans); 1808 if (ret < 0) 1809 return ret; 1810 1811 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1812 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1813 udelay(20); 1814 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1815 HPM_HIPM_GEN_CFG_CR_PG_EN | 1816 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1817 udelay(20); 1818 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1819 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1820 1821 return iwl_trans_pcie_sw_reset(trans, true); 1822 } 1823 1824 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1825 { 1826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1827 int err; 1828 1829 lockdep_assert_held(&trans_pcie->mutex); 1830 1831 err = iwl_pcie_prepare_card_hw(trans); 1832 if (err) { 1833 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1834 return err; 1835 } 1836 1837 err = iwl_trans_pcie_clear_persistence_bit(trans); 1838 if (err) 1839 return err; 1840 1841 err = iwl_trans_pcie_sw_reset(trans, true); 1842 if (err) 1843 return err; 1844 1845 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1846 trans->trans_cfg->integrated) { 1847 err = iwl_pcie_gen2_force_power_gating(trans); 1848 if (err) 1849 return err; 1850 } 1851 1852 err = iwl_pcie_apm_init(trans); 1853 if (err) 1854 return err; 1855 1856 iwl_pcie_init_msix(trans_pcie); 1857 1858 /* From now on, the op_mode will be kept updated about RF kill state */ 1859 iwl_enable_rfkill_int(trans); 1860 1861 trans_pcie->opmode_down = false; 1862 1863 /* Set is_down to false here so that...*/ 1864 trans_pcie->is_down = false; 1865 1866 /* ...rfkill can call stop_device and set it false if needed */ 1867 iwl_pcie_check_hw_rf_kill(trans); 1868 1869 return 0; 1870 } 1871 1872 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1873 { 1874 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1875 int ret; 1876 1877 mutex_lock(&trans_pcie->mutex); 1878 ret = _iwl_trans_pcie_start_hw(trans); 1879 mutex_unlock(&trans_pcie->mutex); 1880 1881 return ret; 1882 } 1883 1884 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1885 { 1886 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1887 1888 mutex_lock(&trans_pcie->mutex); 1889 1890 /* disable interrupts - don't enable HW RF kill interrupt */ 1891 iwl_disable_interrupts(trans); 1892 1893 iwl_pcie_apm_stop(trans, true); 1894 1895 iwl_disable_interrupts(trans); 1896 1897 iwl_pcie_disable_ict(trans); 1898 1899 mutex_unlock(&trans_pcie->mutex); 1900 1901 iwl_pcie_synchronize_irqs(trans); 1902 } 1903 1904 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1905 { 1906 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1907 } 1908 1909 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1910 { 1911 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1912 } 1913 1914 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1915 { 1916 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1917 } 1918 1919 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1920 { 1921 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1922 return 0x00FFFFFF; 1923 else 1924 return 0x000FFFFF; 1925 } 1926 1927 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1928 { 1929 u32 mask = iwl_trans_pcie_prph_msk(trans); 1930 1931 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1932 ((reg & mask) | (3 << 24))); 1933 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1934 } 1935 1936 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1937 u32 val) 1938 { 1939 u32 mask = iwl_trans_pcie_prph_msk(trans); 1940 1941 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1942 ((addr & mask) | (3 << 24))); 1943 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1944 } 1945 1946 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1947 const struct iwl_trans_config *trans_cfg) 1948 { 1949 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1950 1951 /* free all first - we might be reconfigured for a different size */ 1952 iwl_pcie_free_rbs_pool(trans); 1953 1954 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 1955 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 1956 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1957 trans->txqs.page_offs = trans_cfg->cb_data_offs; 1958 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1959 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 1960 1961 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1962 trans_pcie->n_no_reclaim_cmds = 0; 1963 else 1964 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1965 if (trans_pcie->n_no_reclaim_cmds) 1966 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1967 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1968 1969 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1970 trans_pcie->rx_page_order = 1971 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1972 trans_pcie->rx_buf_bytes = 1973 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1974 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1975 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1976 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1977 1978 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1979 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1980 1981 trans->command_groups = trans_cfg->command_groups; 1982 trans->command_groups_size = trans_cfg->command_groups_size; 1983 1984 /* Initialize NAPI here - it should be before registering to mac80211 1985 * in the opmode but after the HW struct is allocated. 1986 * As this function may be called again in some corner cases don't 1987 * do anything if NAPI was already initialized. 1988 */ 1989 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1990 init_dummy_netdev(&trans_pcie->napi_dev); 1991 1992 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1993 } 1994 1995 void iwl_trans_pcie_free(struct iwl_trans *trans) 1996 { 1997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1998 int i; 1999 2000 iwl_pcie_synchronize_irqs(trans); 2001 2002 if (trans->trans_cfg->gen2) 2003 iwl_txq_gen2_tx_free(trans); 2004 else 2005 iwl_pcie_tx_free(trans); 2006 iwl_pcie_rx_free(trans); 2007 2008 if (trans_pcie->rba.alloc_wq) { 2009 destroy_workqueue(trans_pcie->rba.alloc_wq); 2010 trans_pcie->rba.alloc_wq = NULL; 2011 } 2012 2013 if (trans_pcie->msix_enabled) { 2014 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2015 irq_set_affinity_hint( 2016 trans_pcie->msix_entries[i].vector, 2017 NULL); 2018 } 2019 2020 trans_pcie->msix_enabled = false; 2021 } else { 2022 iwl_pcie_free_ict(trans); 2023 } 2024 2025 iwl_pcie_free_fw_monitor(trans); 2026 2027 if (trans_pcie->pnvm_dram.size) 2028 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 2029 trans_pcie->pnvm_dram.block, 2030 trans_pcie->pnvm_dram.physical); 2031 2032 if (trans_pcie->reduce_power_dram.size) 2033 dma_free_coherent(trans->dev, 2034 trans_pcie->reduce_power_dram.size, 2035 trans_pcie->reduce_power_dram.block, 2036 trans_pcie->reduce_power_dram.physical); 2037 2038 mutex_destroy(&trans_pcie->mutex); 2039 iwl_trans_free(trans); 2040 } 2041 2042 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2043 { 2044 if (state) 2045 set_bit(STATUS_TPOWER_PMI, &trans->status); 2046 else 2047 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2048 } 2049 2050 struct iwl_trans_pcie_removal { 2051 struct pci_dev *pdev; 2052 struct work_struct work; 2053 bool rescan; 2054 }; 2055 2056 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2057 { 2058 struct iwl_trans_pcie_removal *removal = 2059 container_of(wk, struct iwl_trans_pcie_removal, work); 2060 struct pci_dev *pdev = removal->pdev; 2061 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2062 struct pci_bus *bus = pdev->bus; 2063 2064 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2065 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2066 pci_lock_rescan_remove(); 2067 pci_dev_put(pdev); 2068 pci_stop_and_remove_bus_device(pdev); 2069 if (removal->rescan) 2070 pci_rescan_bus(bus->parent); 2071 pci_unlock_rescan_remove(); 2072 2073 kfree(removal); 2074 module_put(THIS_MODULE); 2075 } 2076 2077 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2078 { 2079 struct iwl_trans_pcie_removal *removal; 2080 2081 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2082 return; 2083 2084 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2085 2086 /* 2087 * get a module reference to avoid doing this 2088 * while unloading anyway and to avoid 2089 * scheduling a work with code that's being 2090 * removed. 2091 */ 2092 if (!try_module_get(THIS_MODULE)) { 2093 IWL_ERR(trans, 2094 "Module is being unloaded - abort\n"); 2095 return; 2096 } 2097 2098 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2099 if (!removal) { 2100 module_put(THIS_MODULE); 2101 return; 2102 } 2103 /* 2104 * we don't need to clear this flag, because 2105 * the trans will be freed and reallocated. 2106 */ 2107 set_bit(STATUS_TRANS_DEAD, &trans->status); 2108 2109 removal->pdev = to_pci_dev(trans->dev); 2110 removal->rescan = rescan; 2111 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2112 pci_dev_get(removal->pdev); 2113 schedule_work(&removal->work); 2114 } 2115 EXPORT_SYMBOL(iwl_trans_pcie_remove); 2116 2117 /* 2118 * This version doesn't disable BHs but rather assumes they're 2119 * already disabled. 2120 */ 2121 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2122 { 2123 int ret; 2124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2125 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2126 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2127 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2128 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2129 2130 spin_lock(&trans_pcie->reg_lock); 2131 2132 if (trans_pcie->cmd_hold_nic_awake) 2133 goto out; 2134 2135 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2136 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2137 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2138 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2139 } 2140 2141 /* this bit wakes up the NIC */ 2142 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2143 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2144 udelay(2); 2145 2146 /* 2147 * These bits say the device is running, and should keep running for 2148 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2149 * but they do not indicate that embedded SRAM is restored yet; 2150 * HW with volatile SRAM must save/restore contents to/from 2151 * host DRAM when sleeping/waking for power-saving. 2152 * Each direction takes approximately 1/4 millisecond; with this 2153 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2154 * series of register accesses are expected (e.g. reading Event Log), 2155 * to keep device from sleeping. 2156 * 2157 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2158 * SRAM is okay/restored. We don't check that here because this call 2159 * is just for hardware register access; but GP1 MAC_SLEEP 2160 * check is a good idea before accessing the SRAM of HW with 2161 * volatile SRAM (e.g. reading Event Log). 2162 * 2163 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2164 * and do not save/restore SRAM when power cycling. 2165 */ 2166 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2167 if (unlikely(ret < 0)) { 2168 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2169 2170 WARN_ONCE(1, 2171 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2172 cntrl); 2173 2174 iwl_trans_pcie_dump_regs(trans); 2175 2176 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2177 iwl_trans_pcie_remove(trans, false); 2178 else 2179 iwl_write32(trans, CSR_RESET, 2180 CSR_RESET_REG_FLAG_FORCE_NMI); 2181 2182 spin_unlock(&trans_pcie->reg_lock); 2183 return false; 2184 } 2185 2186 out: 2187 /* 2188 * Fool sparse by faking we release the lock - sparse will 2189 * track nic_access anyway. 2190 */ 2191 __release(&trans_pcie->reg_lock); 2192 return true; 2193 } 2194 2195 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2196 { 2197 bool ret; 2198 2199 local_bh_disable(); 2200 ret = __iwl_trans_pcie_grab_nic_access(trans); 2201 if (ret) { 2202 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2203 return ret; 2204 } 2205 local_bh_enable(); 2206 return false; 2207 } 2208 2209 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2210 { 2211 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2212 2213 lockdep_assert_held(&trans_pcie->reg_lock); 2214 2215 /* 2216 * Fool sparse by faking we acquiring the lock - sparse will 2217 * track nic_access anyway. 2218 */ 2219 __acquire(&trans_pcie->reg_lock); 2220 2221 if (trans_pcie->cmd_hold_nic_awake) 2222 goto out; 2223 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2224 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2225 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2226 else 2227 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2228 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2229 /* 2230 * Above we read the CSR_GP_CNTRL register, which will flush 2231 * any previous writes, but we need the write that clears the 2232 * MAC_ACCESS_REQ bit to be performed before any other writes 2233 * scheduled on different CPUs (after we drop reg_lock). 2234 */ 2235 out: 2236 spin_unlock_bh(&trans_pcie->reg_lock); 2237 } 2238 2239 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2240 void *buf, int dwords) 2241 { 2242 int offs = 0; 2243 u32 *vals = buf; 2244 2245 while (offs < dwords) { 2246 /* limit the time we spin here under lock to 1/2s */ 2247 unsigned long end = jiffies + HZ / 2; 2248 bool resched = false; 2249 2250 if (iwl_trans_grab_nic_access(trans)) { 2251 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2252 addr + 4 * offs); 2253 2254 while (offs < dwords) { 2255 vals[offs] = iwl_read32(trans, 2256 HBUS_TARG_MEM_RDAT); 2257 offs++; 2258 2259 if (time_after(jiffies, end)) { 2260 resched = true; 2261 break; 2262 } 2263 } 2264 iwl_trans_release_nic_access(trans); 2265 2266 if (resched) 2267 cond_resched(); 2268 } else { 2269 return -EBUSY; 2270 } 2271 } 2272 2273 return 0; 2274 } 2275 2276 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2277 const void *buf, int dwords) 2278 { 2279 int offs, ret = 0; 2280 const u32 *vals = buf; 2281 2282 if (iwl_trans_grab_nic_access(trans)) { 2283 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2284 for (offs = 0; offs < dwords; offs++) 2285 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2286 vals ? vals[offs] : 0); 2287 iwl_trans_release_nic_access(trans); 2288 } else { 2289 ret = -EBUSY; 2290 } 2291 return ret; 2292 } 2293 2294 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2295 u32 *val) 2296 { 2297 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2298 ofs, val); 2299 } 2300 2301 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2302 { 2303 int i; 2304 2305 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2306 struct iwl_txq *txq = trans->txqs.txq[i]; 2307 2308 if (i == trans->txqs.cmd.q_id) 2309 continue; 2310 2311 spin_lock_bh(&txq->lock); 2312 2313 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2314 txq->block--; 2315 if (!txq->block) { 2316 iwl_write32(trans, HBUS_TARG_WRPTR, 2317 txq->write_ptr | (i << 8)); 2318 } 2319 } else if (block) { 2320 txq->block++; 2321 } 2322 2323 spin_unlock_bh(&txq->lock); 2324 } 2325 } 2326 2327 #define IWL_FLUSH_WAIT_MS 2000 2328 2329 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2330 struct iwl_trans_rxq_dma_data *data) 2331 { 2332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2333 2334 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2335 return -EINVAL; 2336 2337 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2338 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2339 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2340 data->fr_bd_wid = 0; 2341 2342 return 0; 2343 } 2344 2345 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2346 { 2347 struct iwl_txq *txq; 2348 unsigned long now = jiffies; 2349 bool overflow_tx; 2350 u8 wr_ptr; 2351 2352 /* Make sure the NIC is still alive in the bus */ 2353 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2354 return -ENODEV; 2355 2356 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2357 return -EINVAL; 2358 2359 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2360 txq = trans->txqs.txq[txq_idx]; 2361 2362 spin_lock_bh(&txq->lock); 2363 overflow_tx = txq->overflow_tx || 2364 !skb_queue_empty(&txq->overflow_q); 2365 spin_unlock_bh(&txq->lock); 2366 2367 wr_ptr = READ_ONCE(txq->write_ptr); 2368 2369 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2370 overflow_tx) && 2371 !time_after(jiffies, 2372 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2373 u8 write_ptr = READ_ONCE(txq->write_ptr); 2374 2375 /* 2376 * If write pointer moved during the wait, warn only 2377 * if the TX came from op mode. In case TX came from 2378 * trans layer (overflow TX) don't warn. 2379 */ 2380 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2381 "WR pointer moved while flushing %d -> %d\n", 2382 wr_ptr, write_ptr)) 2383 return -ETIMEDOUT; 2384 wr_ptr = write_ptr; 2385 2386 usleep_range(1000, 2000); 2387 2388 spin_lock_bh(&txq->lock); 2389 overflow_tx = txq->overflow_tx || 2390 !skb_queue_empty(&txq->overflow_q); 2391 spin_unlock_bh(&txq->lock); 2392 } 2393 2394 if (txq->read_ptr != txq->write_ptr) { 2395 IWL_ERR(trans, 2396 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2397 iwl_txq_log_scd_error(trans, txq); 2398 return -ETIMEDOUT; 2399 } 2400 2401 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2402 2403 return 0; 2404 } 2405 2406 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2407 { 2408 int cnt; 2409 int ret = 0; 2410 2411 /* waiting for all the tx frames complete might take a while */ 2412 for (cnt = 0; 2413 cnt < trans->trans_cfg->base_params->num_of_queues; 2414 cnt++) { 2415 2416 if (cnt == trans->txqs.cmd.q_id) 2417 continue; 2418 if (!test_bit(cnt, trans->txqs.queue_used)) 2419 continue; 2420 if (!(BIT(cnt) & txq_bm)) 2421 continue; 2422 2423 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2424 if (ret) 2425 break; 2426 } 2427 2428 return ret; 2429 } 2430 2431 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2432 u32 mask, u32 value) 2433 { 2434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2435 2436 spin_lock_bh(&trans_pcie->reg_lock); 2437 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2438 spin_unlock_bh(&trans_pcie->reg_lock); 2439 } 2440 2441 static const char *get_csr_string(int cmd) 2442 { 2443 #define IWL_CMD(x) case x: return #x 2444 switch (cmd) { 2445 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2446 IWL_CMD(CSR_INT_COALESCING); 2447 IWL_CMD(CSR_INT); 2448 IWL_CMD(CSR_INT_MASK); 2449 IWL_CMD(CSR_FH_INT_STATUS); 2450 IWL_CMD(CSR_GPIO_IN); 2451 IWL_CMD(CSR_RESET); 2452 IWL_CMD(CSR_GP_CNTRL); 2453 IWL_CMD(CSR_HW_REV); 2454 IWL_CMD(CSR_EEPROM_REG); 2455 IWL_CMD(CSR_EEPROM_GP); 2456 IWL_CMD(CSR_OTP_GP_REG); 2457 IWL_CMD(CSR_GIO_REG); 2458 IWL_CMD(CSR_GP_UCODE_REG); 2459 IWL_CMD(CSR_GP_DRIVER_REG); 2460 IWL_CMD(CSR_UCODE_DRV_GP1); 2461 IWL_CMD(CSR_UCODE_DRV_GP2); 2462 IWL_CMD(CSR_LED_REG); 2463 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2464 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2465 IWL_CMD(CSR_ANA_PLL_CFG); 2466 IWL_CMD(CSR_HW_REV_WA_REG); 2467 IWL_CMD(CSR_MONITOR_STATUS_REG); 2468 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2469 default: 2470 return "UNKNOWN"; 2471 } 2472 #undef IWL_CMD 2473 } 2474 2475 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2476 { 2477 int i; 2478 static const u32 csr_tbl[] = { 2479 CSR_HW_IF_CONFIG_REG, 2480 CSR_INT_COALESCING, 2481 CSR_INT, 2482 CSR_INT_MASK, 2483 CSR_FH_INT_STATUS, 2484 CSR_GPIO_IN, 2485 CSR_RESET, 2486 CSR_GP_CNTRL, 2487 CSR_HW_REV, 2488 CSR_EEPROM_REG, 2489 CSR_EEPROM_GP, 2490 CSR_OTP_GP_REG, 2491 CSR_GIO_REG, 2492 CSR_GP_UCODE_REG, 2493 CSR_GP_DRIVER_REG, 2494 CSR_UCODE_DRV_GP1, 2495 CSR_UCODE_DRV_GP2, 2496 CSR_LED_REG, 2497 CSR_DRAM_INT_TBL_REG, 2498 CSR_GIO_CHICKEN_BITS, 2499 CSR_ANA_PLL_CFG, 2500 CSR_MONITOR_STATUS_REG, 2501 CSR_HW_REV_WA_REG, 2502 CSR_DBG_HPET_MEM_REG 2503 }; 2504 IWL_ERR(trans, "CSR values:\n"); 2505 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2506 "CSR_INT_PERIODIC_REG)\n"); 2507 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2508 IWL_ERR(trans, " %25s: 0X%08x\n", 2509 get_csr_string(csr_tbl[i]), 2510 iwl_read32(trans, csr_tbl[i])); 2511 } 2512 } 2513 2514 #ifdef CONFIG_IWLWIFI_DEBUGFS 2515 /* create and remove of files */ 2516 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2517 debugfs_create_file(#name, mode, parent, trans, \ 2518 &iwl_dbgfs_##name##_ops); \ 2519 } while (0) 2520 2521 /* file operation */ 2522 #define DEBUGFS_READ_FILE_OPS(name) \ 2523 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2524 .read = iwl_dbgfs_##name##_read, \ 2525 .open = simple_open, \ 2526 .llseek = generic_file_llseek, \ 2527 }; 2528 2529 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2530 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2531 .write = iwl_dbgfs_##name##_write, \ 2532 .open = simple_open, \ 2533 .llseek = generic_file_llseek, \ 2534 }; 2535 2536 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2537 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2538 .write = iwl_dbgfs_##name##_write, \ 2539 .read = iwl_dbgfs_##name##_read, \ 2540 .open = simple_open, \ 2541 .llseek = generic_file_llseek, \ 2542 }; 2543 2544 struct iwl_dbgfs_tx_queue_priv { 2545 struct iwl_trans *trans; 2546 }; 2547 2548 struct iwl_dbgfs_tx_queue_state { 2549 loff_t pos; 2550 }; 2551 2552 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2553 { 2554 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2555 struct iwl_dbgfs_tx_queue_state *state; 2556 2557 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2558 return NULL; 2559 2560 state = kmalloc(sizeof(*state), GFP_KERNEL); 2561 if (!state) 2562 return NULL; 2563 state->pos = *pos; 2564 return state; 2565 } 2566 2567 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2568 void *v, loff_t *pos) 2569 { 2570 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2571 struct iwl_dbgfs_tx_queue_state *state = v; 2572 2573 *pos = ++state->pos; 2574 2575 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2576 return NULL; 2577 2578 return state; 2579 } 2580 2581 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2582 { 2583 kfree(v); 2584 } 2585 2586 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2587 { 2588 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2589 struct iwl_dbgfs_tx_queue_state *state = v; 2590 struct iwl_trans *trans = priv->trans; 2591 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2592 2593 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2594 (unsigned int)state->pos, 2595 !!test_bit(state->pos, trans->txqs.queue_used), 2596 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2597 if (txq) 2598 seq_printf(seq, 2599 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2600 txq->read_ptr, txq->write_ptr, 2601 txq->need_update, txq->frozen, 2602 txq->n_window, txq->ampdu); 2603 else 2604 seq_puts(seq, "(unallocated)"); 2605 2606 if (state->pos == trans->txqs.cmd.q_id) 2607 seq_puts(seq, " (HCMD)"); 2608 seq_puts(seq, "\n"); 2609 2610 return 0; 2611 } 2612 2613 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2614 .start = iwl_dbgfs_tx_queue_seq_start, 2615 .next = iwl_dbgfs_tx_queue_seq_next, 2616 .stop = iwl_dbgfs_tx_queue_seq_stop, 2617 .show = iwl_dbgfs_tx_queue_seq_show, 2618 }; 2619 2620 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2621 { 2622 struct iwl_dbgfs_tx_queue_priv *priv; 2623 2624 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2625 sizeof(*priv)); 2626 2627 if (!priv) 2628 return -ENOMEM; 2629 2630 priv->trans = inode->i_private; 2631 return 0; 2632 } 2633 2634 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2635 char __user *user_buf, 2636 size_t count, loff_t *ppos) 2637 { 2638 struct iwl_trans *trans = file->private_data; 2639 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2640 char *buf; 2641 int pos = 0, i, ret; 2642 size_t bufsz; 2643 2644 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2645 2646 if (!trans_pcie->rxq) 2647 return -EAGAIN; 2648 2649 buf = kzalloc(bufsz, GFP_KERNEL); 2650 if (!buf) 2651 return -ENOMEM; 2652 2653 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2654 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2655 2656 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2657 i); 2658 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2659 rxq->read); 2660 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2661 rxq->write); 2662 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2663 rxq->write_actual); 2664 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2665 rxq->need_update); 2666 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2667 rxq->free_count); 2668 if (rxq->rb_stts) { 2669 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2670 rxq)); 2671 pos += scnprintf(buf + pos, bufsz - pos, 2672 "\tclosed_rb_num: %u\n", 2673 r & 0x0FFF); 2674 } else { 2675 pos += scnprintf(buf + pos, bufsz - pos, 2676 "\tclosed_rb_num: Not Allocated\n"); 2677 } 2678 } 2679 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2680 kfree(buf); 2681 2682 return ret; 2683 } 2684 2685 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2686 char __user *user_buf, 2687 size_t count, loff_t *ppos) 2688 { 2689 struct iwl_trans *trans = file->private_data; 2690 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2691 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2692 2693 int pos = 0; 2694 char *buf; 2695 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2696 ssize_t ret; 2697 2698 buf = kzalloc(bufsz, GFP_KERNEL); 2699 if (!buf) 2700 return -ENOMEM; 2701 2702 pos += scnprintf(buf + pos, bufsz - pos, 2703 "Interrupt Statistics Report:\n"); 2704 2705 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2706 isr_stats->hw); 2707 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2708 isr_stats->sw); 2709 if (isr_stats->sw || isr_stats->hw) { 2710 pos += scnprintf(buf + pos, bufsz - pos, 2711 "\tLast Restarting Code: 0x%X\n", 2712 isr_stats->err_code); 2713 } 2714 #ifdef CONFIG_IWLWIFI_DEBUG 2715 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2716 isr_stats->sch); 2717 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2718 isr_stats->alive); 2719 #endif 2720 pos += scnprintf(buf + pos, bufsz - pos, 2721 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2722 2723 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2724 isr_stats->ctkill); 2725 2726 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2727 isr_stats->wakeup); 2728 2729 pos += scnprintf(buf + pos, bufsz - pos, 2730 "Rx command responses:\t\t %u\n", isr_stats->rx); 2731 2732 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2733 isr_stats->tx); 2734 2735 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2736 isr_stats->unhandled); 2737 2738 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2739 kfree(buf); 2740 return ret; 2741 } 2742 2743 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2744 const char __user *user_buf, 2745 size_t count, loff_t *ppos) 2746 { 2747 struct iwl_trans *trans = file->private_data; 2748 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2749 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2750 u32 reset_flag; 2751 int ret; 2752 2753 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2754 if (ret) 2755 return ret; 2756 if (reset_flag == 0) 2757 memset(isr_stats, 0, sizeof(*isr_stats)); 2758 2759 return count; 2760 } 2761 2762 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2763 const char __user *user_buf, 2764 size_t count, loff_t *ppos) 2765 { 2766 struct iwl_trans *trans = file->private_data; 2767 2768 iwl_pcie_dump_csr(trans); 2769 2770 return count; 2771 } 2772 2773 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2774 char __user *user_buf, 2775 size_t count, loff_t *ppos) 2776 { 2777 struct iwl_trans *trans = file->private_data; 2778 char *buf = NULL; 2779 ssize_t ret; 2780 2781 ret = iwl_dump_fh(trans, &buf); 2782 if (ret < 0) 2783 return ret; 2784 if (!buf) 2785 return -EINVAL; 2786 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2787 kfree(buf); 2788 return ret; 2789 } 2790 2791 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2792 char __user *user_buf, 2793 size_t count, loff_t *ppos) 2794 { 2795 struct iwl_trans *trans = file->private_data; 2796 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2797 char buf[100]; 2798 int pos; 2799 2800 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2801 trans_pcie->debug_rfkill, 2802 !(iwl_read32(trans, CSR_GP_CNTRL) & 2803 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2804 2805 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2806 } 2807 2808 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2809 const char __user *user_buf, 2810 size_t count, loff_t *ppos) 2811 { 2812 struct iwl_trans *trans = file->private_data; 2813 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2814 bool new_value; 2815 int ret; 2816 2817 ret = kstrtobool_from_user(user_buf, count, &new_value); 2818 if (ret) 2819 return ret; 2820 if (new_value == trans_pcie->debug_rfkill) 2821 return count; 2822 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2823 trans_pcie->debug_rfkill, new_value); 2824 trans_pcie->debug_rfkill = new_value; 2825 iwl_pcie_handle_rfkill_irq(trans); 2826 2827 return count; 2828 } 2829 2830 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2831 struct file *file) 2832 { 2833 struct iwl_trans *trans = inode->i_private; 2834 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2835 2836 if (!trans->dbg.dest_tlv || 2837 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2838 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2839 return -ENOENT; 2840 } 2841 2842 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2843 return -EBUSY; 2844 2845 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2846 return simple_open(inode, file); 2847 } 2848 2849 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2850 struct file *file) 2851 { 2852 struct iwl_trans_pcie *trans_pcie = 2853 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2854 2855 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2856 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2857 return 0; 2858 } 2859 2860 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2861 void *buf, ssize_t *size, 2862 ssize_t *bytes_copied) 2863 { 2864 ssize_t buf_size_left = count - *bytes_copied; 2865 2866 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2867 if (*size > buf_size_left) 2868 *size = buf_size_left; 2869 2870 *size -= copy_to_user(user_buf, buf, *size); 2871 *bytes_copied += *size; 2872 2873 if (buf_size_left == *size) 2874 return true; 2875 return false; 2876 } 2877 2878 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2879 char __user *user_buf, 2880 size_t count, loff_t *ppos) 2881 { 2882 struct iwl_trans *trans = file->private_data; 2883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2884 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2885 struct cont_rec *data = &trans_pcie->fw_mon_data; 2886 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2887 ssize_t size, bytes_copied = 0; 2888 bool b_full; 2889 2890 if (trans->dbg.dest_tlv) { 2891 write_ptr_addr = 2892 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2893 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2894 } else { 2895 write_ptr_addr = MON_BUFF_WRPTR; 2896 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2897 } 2898 2899 if (unlikely(!trans->dbg.rec_on)) 2900 return 0; 2901 2902 mutex_lock(&data->mutex); 2903 if (data->state == 2904 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2905 mutex_unlock(&data->mutex); 2906 return 0; 2907 } 2908 2909 /* write_ptr position in bytes rather then DW */ 2910 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2911 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2912 2913 if (data->prev_wrap_cnt == wrap_cnt) { 2914 size = write_ptr - data->prev_wr_ptr; 2915 curr_buf = cpu_addr + data->prev_wr_ptr; 2916 b_full = iwl_write_to_user_buf(user_buf, count, 2917 curr_buf, &size, 2918 &bytes_copied); 2919 data->prev_wr_ptr += size; 2920 2921 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2922 write_ptr < data->prev_wr_ptr) { 2923 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2924 curr_buf = cpu_addr + data->prev_wr_ptr; 2925 b_full = iwl_write_to_user_buf(user_buf, count, 2926 curr_buf, &size, 2927 &bytes_copied); 2928 data->prev_wr_ptr += size; 2929 2930 if (!b_full) { 2931 size = write_ptr; 2932 b_full = iwl_write_to_user_buf(user_buf, count, 2933 cpu_addr, &size, 2934 &bytes_copied); 2935 data->prev_wr_ptr = size; 2936 data->prev_wrap_cnt++; 2937 } 2938 } else { 2939 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2940 write_ptr > data->prev_wr_ptr) 2941 IWL_WARN(trans, 2942 "write pointer passed previous write pointer, start copying from the beginning\n"); 2943 else if (!unlikely(data->prev_wrap_cnt == 0 && 2944 data->prev_wr_ptr == 0)) 2945 IWL_WARN(trans, 2946 "monitor data is out of sync, start copying from the beginning\n"); 2947 2948 size = write_ptr; 2949 b_full = iwl_write_to_user_buf(user_buf, count, 2950 cpu_addr, &size, 2951 &bytes_copied); 2952 data->prev_wr_ptr = size; 2953 data->prev_wrap_cnt = wrap_cnt; 2954 } 2955 2956 mutex_unlock(&data->mutex); 2957 2958 return bytes_copied; 2959 } 2960 2961 static ssize_t iwl_dbgfs_rf_read(struct file *file, 2962 char __user *user_buf, 2963 size_t count, loff_t *ppos) 2964 { 2965 struct iwl_trans *trans = file->private_data; 2966 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2967 2968 if (!trans_pcie->rf_name[0]) 2969 return -ENODEV; 2970 2971 return simple_read_from_buffer(user_buf, count, ppos, 2972 trans_pcie->rf_name, 2973 strlen(trans_pcie->rf_name)); 2974 } 2975 2976 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2977 DEBUGFS_READ_FILE_OPS(fh_reg); 2978 DEBUGFS_READ_FILE_OPS(rx_queue); 2979 DEBUGFS_WRITE_FILE_OPS(csr); 2980 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2981 DEBUGFS_READ_FILE_OPS(rf); 2982 2983 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2984 .owner = THIS_MODULE, 2985 .open = iwl_dbgfs_tx_queue_open, 2986 .read = seq_read, 2987 .llseek = seq_lseek, 2988 .release = seq_release_private, 2989 }; 2990 2991 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2992 .read = iwl_dbgfs_monitor_data_read, 2993 .open = iwl_dbgfs_monitor_data_open, 2994 .release = iwl_dbgfs_monitor_data_release, 2995 }; 2996 2997 /* Create the debugfs files and directories */ 2998 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2999 { 3000 struct dentry *dir = trans->dbgfs_dir; 3001 3002 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3003 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3004 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3005 DEBUGFS_ADD_FILE(csr, dir, 0200); 3006 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3007 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3008 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3009 DEBUGFS_ADD_FILE(rf, dir, 0400); 3010 } 3011 3012 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3013 { 3014 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3015 struct cont_rec *data = &trans_pcie->fw_mon_data; 3016 3017 mutex_lock(&data->mutex); 3018 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3019 mutex_unlock(&data->mutex); 3020 } 3021 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3022 3023 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3024 { 3025 u32 cmdlen = 0; 3026 int i; 3027 3028 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 3029 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3030 3031 return cmdlen; 3032 } 3033 3034 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3035 struct iwl_fw_error_dump_data **data, 3036 int allocated_rb_nums) 3037 { 3038 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3039 int max_len = trans_pcie->rx_buf_bytes; 3040 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3041 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3042 u32 i, r, j, rb_len = 0; 3043 3044 spin_lock(&rxq->lock); 3045 3046 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3047 3048 for (i = rxq->read, j = 0; 3049 i != r && j < allocated_rb_nums; 3050 i = (i + 1) & RX_QUEUE_MASK, j++) { 3051 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3052 struct iwl_fw_error_dump_rb *rb; 3053 3054 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3055 max_len, DMA_FROM_DEVICE); 3056 3057 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3058 3059 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3060 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3061 rb = (void *)(*data)->data; 3062 rb->index = cpu_to_le32(i); 3063 memcpy(rb->data, page_address(rxb->page), max_len); 3064 3065 *data = iwl_fw_error_next_data(*data); 3066 } 3067 3068 spin_unlock(&rxq->lock); 3069 3070 return rb_len; 3071 } 3072 #define IWL_CSR_TO_DUMP (0x250) 3073 3074 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3075 struct iwl_fw_error_dump_data **data) 3076 { 3077 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3078 __le32 *val; 3079 int i; 3080 3081 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3082 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3083 val = (void *)(*data)->data; 3084 3085 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3086 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3087 3088 *data = iwl_fw_error_next_data(*data); 3089 3090 return csr_len; 3091 } 3092 3093 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3094 struct iwl_fw_error_dump_data **data) 3095 { 3096 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3097 __le32 *val; 3098 int i; 3099 3100 if (!iwl_trans_grab_nic_access(trans)) 3101 return 0; 3102 3103 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3104 (*data)->len = cpu_to_le32(fh_regs_len); 3105 val = (void *)(*data)->data; 3106 3107 if (!trans->trans_cfg->gen2) 3108 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3109 i += sizeof(u32)) 3110 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3111 else 3112 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3113 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3114 i += sizeof(u32)) 3115 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3116 i)); 3117 3118 iwl_trans_release_nic_access(trans); 3119 3120 *data = iwl_fw_error_next_data(*data); 3121 3122 return sizeof(**data) + fh_regs_len; 3123 } 3124 3125 static u32 3126 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3127 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3128 u32 monitor_len) 3129 { 3130 u32 buf_size_in_dwords = (monitor_len >> 2); 3131 u32 *buffer = (u32 *)fw_mon_data->data; 3132 u32 i; 3133 3134 if (!iwl_trans_grab_nic_access(trans)) 3135 return 0; 3136 3137 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3138 for (i = 0; i < buf_size_in_dwords; i++) 3139 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3140 MON_DMARB_RD_DATA_ADDR); 3141 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3142 3143 iwl_trans_release_nic_access(trans); 3144 3145 return monitor_len; 3146 } 3147 3148 static void 3149 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3150 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3151 { 3152 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3153 3154 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3155 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3156 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3157 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3158 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3159 } else if (trans->dbg.dest_tlv) { 3160 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3161 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3162 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3163 } else { 3164 base = MON_BUFF_BASE_ADDR; 3165 write_ptr = MON_BUFF_WRPTR; 3166 wrap_cnt = MON_BUFF_CYCLE_CNT; 3167 } 3168 3169 write_ptr_val = iwl_read_prph(trans, write_ptr); 3170 fw_mon_data->fw_mon_cycle_cnt = 3171 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3172 fw_mon_data->fw_mon_base_ptr = 3173 cpu_to_le32(iwl_read_prph(trans, base)); 3174 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3175 fw_mon_data->fw_mon_base_high_ptr = 3176 cpu_to_le32(iwl_read_prph(trans, base_high)); 3177 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3178 /* convert wrtPtr to DWs, to align with all HWs */ 3179 write_ptr_val >>= 2; 3180 } 3181 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3182 } 3183 3184 static u32 3185 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3186 struct iwl_fw_error_dump_data **data, 3187 u32 monitor_len) 3188 { 3189 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3190 u32 len = 0; 3191 3192 if (trans->dbg.dest_tlv || 3193 (fw_mon->size && 3194 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3195 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3196 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3197 3198 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3199 fw_mon_data = (void *)(*data)->data; 3200 3201 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3202 3203 len += sizeof(**data) + sizeof(*fw_mon_data); 3204 if (fw_mon->size) { 3205 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3206 monitor_len = fw_mon->size; 3207 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3208 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3209 /* 3210 * Update pointers to reflect actual values after 3211 * shifting 3212 */ 3213 if (trans->dbg.dest_tlv->version) { 3214 base = (iwl_read_prph(trans, base) & 3215 IWL_LDBG_M2S_BUF_BA_MSK) << 3216 trans->dbg.dest_tlv->base_shift; 3217 base *= IWL_M2S_UNIT_SIZE; 3218 base += trans->cfg->smem_offset; 3219 } else { 3220 base = iwl_read_prph(trans, base) << 3221 trans->dbg.dest_tlv->base_shift; 3222 } 3223 3224 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3225 monitor_len / sizeof(u32)); 3226 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3227 monitor_len = 3228 iwl_trans_pci_dump_marbh_monitor(trans, 3229 fw_mon_data, 3230 monitor_len); 3231 } else { 3232 /* Didn't match anything - output no monitor data */ 3233 monitor_len = 0; 3234 } 3235 3236 len += monitor_len; 3237 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3238 } 3239 3240 return len; 3241 } 3242 3243 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3244 { 3245 if (trans->dbg.fw_mon.size) { 3246 *len += sizeof(struct iwl_fw_error_dump_data) + 3247 sizeof(struct iwl_fw_error_dump_fw_mon) + 3248 trans->dbg.fw_mon.size; 3249 return trans->dbg.fw_mon.size; 3250 } else if (trans->dbg.dest_tlv) { 3251 u32 base, end, cfg_reg, monitor_len; 3252 3253 if (trans->dbg.dest_tlv->version == 1) { 3254 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3255 cfg_reg = iwl_read_prph(trans, cfg_reg); 3256 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3257 trans->dbg.dest_tlv->base_shift; 3258 base *= IWL_M2S_UNIT_SIZE; 3259 base += trans->cfg->smem_offset; 3260 3261 monitor_len = 3262 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3263 trans->dbg.dest_tlv->end_shift; 3264 monitor_len *= IWL_M2S_UNIT_SIZE; 3265 } else { 3266 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3267 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3268 3269 base = iwl_read_prph(trans, base) << 3270 trans->dbg.dest_tlv->base_shift; 3271 end = iwl_read_prph(trans, end) << 3272 trans->dbg.dest_tlv->end_shift; 3273 3274 /* Make "end" point to the actual end */ 3275 if (trans->trans_cfg->device_family >= 3276 IWL_DEVICE_FAMILY_8000 || 3277 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3278 end += (1 << trans->dbg.dest_tlv->end_shift); 3279 monitor_len = end - base; 3280 } 3281 *len += sizeof(struct iwl_fw_error_dump_data) + 3282 sizeof(struct iwl_fw_error_dump_fw_mon) + 3283 monitor_len; 3284 return monitor_len; 3285 } 3286 return 0; 3287 } 3288 3289 static struct iwl_trans_dump_data * 3290 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3291 u32 dump_mask, 3292 const struct iwl_dump_sanitize_ops *sanitize_ops, 3293 void *sanitize_ctx) 3294 { 3295 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3296 struct iwl_fw_error_dump_data *data; 3297 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3298 struct iwl_fw_error_dump_txcmd *txcmd; 3299 struct iwl_trans_dump_data *dump_data; 3300 u32 len, num_rbs = 0, monitor_len = 0; 3301 int i, ptr; 3302 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3303 !trans->trans_cfg->mq_rx_supported && 3304 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3305 3306 if (!dump_mask) 3307 return NULL; 3308 3309 /* transport dump header */ 3310 len = sizeof(*dump_data); 3311 3312 /* host commands */ 3313 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3314 len += sizeof(*data) + 3315 cmdq->n_window * (sizeof(*txcmd) + 3316 TFD_MAX_PAYLOAD_SIZE); 3317 3318 /* FW monitor */ 3319 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3320 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3321 3322 /* CSR registers */ 3323 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3324 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3325 3326 /* FH registers */ 3327 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3328 if (trans->trans_cfg->gen2) 3329 len += sizeof(*data) + 3330 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3331 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3332 else 3333 len += sizeof(*data) + 3334 (FH_MEM_UPPER_BOUND - 3335 FH_MEM_LOWER_BOUND); 3336 } 3337 3338 if (dump_rbs) { 3339 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3340 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3341 /* RBs */ 3342 num_rbs = 3343 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3344 & 0x0FFF; 3345 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3346 len += num_rbs * (sizeof(*data) + 3347 sizeof(struct iwl_fw_error_dump_rb) + 3348 (PAGE_SIZE << trans_pcie->rx_page_order)); 3349 } 3350 3351 /* Paged memory for gen2 HW */ 3352 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3353 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3354 len += sizeof(*data) + 3355 sizeof(struct iwl_fw_error_dump_paging) + 3356 trans->init_dram.paging[i].size; 3357 3358 dump_data = vzalloc(len); 3359 if (!dump_data) 3360 return NULL; 3361 3362 len = 0; 3363 data = (void *)dump_data->data; 3364 3365 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3366 u16 tfd_size = trans->txqs.tfd.size; 3367 3368 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3369 txcmd = (void *)data->data; 3370 spin_lock_bh(&cmdq->lock); 3371 ptr = cmdq->write_ptr; 3372 for (i = 0; i < cmdq->n_window; i++) { 3373 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3374 u8 tfdidx; 3375 u32 caplen, cmdlen; 3376 3377 if (trans->trans_cfg->use_tfh) 3378 tfdidx = idx; 3379 else 3380 tfdidx = ptr; 3381 3382 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3383 (u8 *)cmdq->tfds + 3384 tfd_size * tfdidx); 3385 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3386 3387 if (cmdlen) { 3388 len += sizeof(*txcmd) + caplen; 3389 txcmd->cmdlen = cpu_to_le32(cmdlen); 3390 txcmd->caplen = cpu_to_le32(caplen); 3391 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3392 caplen); 3393 if (sanitize_ops && sanitize_ops->frob_hcmd) 3394 sanitize_ops->frob_hcmd(sanitize_ctx, 3395 txcmd->data, 3396 caplen); 3397 txcmd = (void *)((u8 *)txcmd->data + caplen); 3398 } 3399 3400 ptr = iwl_txq_dec_wrap(trans, ptr); 3401 } 3402 spin_unlock_bh(&cmdq->lock); 3403 3404 data->len = cpu_to_le32(len); 3405 len += sizeof(*data); 3406 data = iwl_fw_error_next_data(data); 3407 } 3408 3409 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3410 len += iwl_trans_pcie_dump_csr(trans, &data); 3411 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3412 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3413 if (dump_rbs) 3414 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3415 3416 /* Paged memory for gen2 HW */ 3417 if (trans->trans_cfg->gen2 && 3418 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3419 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3420 struct iwl_fw_error_dump_paging *paging; 3421 u32 page_len = trans->init_dram.paging[i].size; 3422 3423 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3424 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3425 paging = (void *)data->data; 3426 paging->index = cpu_to_le32(i); 3427 memcpy(paging->data, 3428 trans->init_dram.paging[i].block, page_len); 3429 data = iwl_fw_error_next_data(data); 3430 3431 len += sizeof(*data) + sizeof(*paging) + page_len; 3432 } 3433 } 3434 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3435 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3436 3437 dump_data->len = len; 3438 3439 return dump_data; 3440 } 3441 3442 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3443 { 3444 if (enable) 3445 iwl_enable_interrupts(trans); 3446 else 3447 iwl_disable_interrupts(trans); 3448 } 3449 3450 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3451 { 3452 u32 inta_addr, sw_err_bit; 3453 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3454 3455 if (trans_pcie->msix_enabled) { 3456 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3457 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3458 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3459 else 3460 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3461 } else { 3462 inta_addr = CSR_INT; 3463 sw_err_bit = CSR_INT_BIT_SW_ERR; 3464 } 3465 3466 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3467 } 3468 3469 #define IWL_TRANS_COMMON_OPS \ 3470 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3471 .write8 = iwl_trans_pcie_write8, \ 3472 .write32 = iwl_trans_pcie_write32, \ 3473 .read32 = iwl_trans_pcie_read32, \ 3474 .read_prph = iwl_trans_pcie_read_prph, \ 3475 .write_prph = iwl_trans_pcie_write_prph, \ 3476 .read_mem = iwl_trans_pcie_read_mem, \ 3477 .write_mem = iwl_trans_pcie_write_mem, \ 3478 .read_config32 = iwl_trans_pcie_read_config32, \ 3479 .configure = iwl_trans_pcie_configure, \ 3480 .set_pmi = iwl_trans_pcie_set_pmi, \ 3481 .sw_reset = iwl_trans_pcie_sw_reset, \ 3482 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3483 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3484 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3485 .dump_data = iwl_trans_pcie_dump_data, \ 3486 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3487 .d3_resume = iwl_trans_pcie_d3_resume, \ 3488 .interrupts = iwl_trans_pci_interrupts, \ 3489 .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3490 .imr_dma_data = iwl_trans_pcie_copy_imr \ 3491 3492 static const struct iwl_trans_ops trans_ops_pcie = { 3493 IWL_TRANS_COMMON_OPS, 3494 .start_hw = iwl_trans_pcie_start_hw, 3495 .fw_alive = iwl_trans_pcie_fw_alive, 3496 .start_fw = iwl_trans_pcie_start_fw, 3497 .stop_device = iwl_trans_pcie_stop_device, 3498 3499 .send_cmd = iwl_pcie_enqueue_hcmd, 3500 3501 .tx = iwl_trans_pcie_tx, 3502 .reclaim = iwl_txq_reclaim, 3503 3504 .txq_disable = iwl_trans_pcie_txq_disable, 3505 .txq_enable = iwl_trans_pcie_txq_enable, 3506 3507 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3508 3509 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3510 3511 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3512 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3513 #ifdef CONFIG_IWLWIFI_DEBUGFS 3514 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3515 #endif 3516 }; 3517 3518 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3519 IWL_TRANS_COMMON_OPS, 3520 .start_hw = iwl_trans_pcie_start_hw, 3521 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3522 .start_fw = iwl_trans_pcie_gen2_start_fw, 3523 .stop_device = iwl_trans_pcie_gen2_stop_device, 3524 3525 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3526 3527 .tx = iwl_txq_gen2_tx, 3528 .reclaim = iwl_txq_reclaim, 3529 3530 .set_q_ptrs = iwl_txq_set_q_ptrs, 3531 3532 .txq_alloc = iwl_txq_dyn_alloc, 3533 .txq_free = iwl_txq_dyn_free, 3534 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3535 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3536 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3537 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3538 #ifdef CONFIG_IWLWIFI_DEBUGFS 3539 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3540 #endif 3541 }; 3542 3543 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3544 const struct pci_device_id *ent, 3545 const struct iwl_cfg_trans_params *cfg_trans) 3546 { 3547 struct iwl_trans_pcie *trans_pcie; 3548 struct iwl_trans *trans; 3549 int ret, addr_size; 3550 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3551 void __iomem * const *table; 3552 3553 if (!cfg_trans->gen2) 3554 ops = &trans_ops_pcie; 3555 3556 ret = pcim_enable_device(pdev); 3557 if (ret) 3558 return ERR_PTR(ret); 3559 3560 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3561 cfg_trans); 3562 if (!trans) 3563 return ERR_PTR(-ENOMEM); 3564 3565 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3566 3567 trans_pcie->trans = trans; 3568 trans_pcie->opmode_down = true; 3569 spin_lock_init(&trans_pcie->irq_lock); 3570 spin_lock_init(&trans_pcie->reg_lock); 3571 spin_lock_init(&trans_pcie->alloc_page_lock); 3572 mutex_init(&trans_pcie->mutex); 3573 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3574 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3575 init_waitqueue_head(&trans_pcie->imr_waitq); 3576 3577 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3578 WQ_HIGHPRI | WQ_UNBOUND, 1); 3579 if (!trans_pcie->rba.alloc_wq) { 3580 ret = -ENOMEM; 3581 goto out_free_trans; 3582 } 3583 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3584 3585 trans_pcie->debug_rfkill = -1; 3586 3587 if (!cfg_trans->base_params->pcie_l1_allowed) { 3588 /* 3589 * W/A - seems to solve weird behavior. We need to remove this 3590 * if we don't want to stay in L1 all the time. This wastes a 3591 * lot of power. 3592 */ 3593 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3594 PCIE_LINK_STATE_L1 | 3595 PCIE_LINK_STATE_CLKPM); 3596 } 3597 3598 trans_pcie->def_rx_queue = 0; 3599 3600 pci_set_master(pdev); 3601 3602 addr_size = trans->txqs.tfd.addr_size; 3603 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3604 if (ret) { 3605 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3606 /* both attempts failed: */ 3607 if (ret) { 3608 dev_err(&pdev->dev, "No suitable DMA available\n"); 3609 goto out_no_pci; 3610 } 3611 } 3612 3613 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3614 if (ret) { 3615 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3616 goto out_no_pci; 3617 } 3618 3619 table = pcim_iomap_table(pdev); 3620 if (!table) { 3621 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3622 ret = -ENOMEM; 3623 goto out_no_pci; 3624 } 3625 3626 trans_pcie->hw_base = table[0]; 3627 if (!trans_pcie->hw_base) { 3628 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3629 ret = -ENODEV; 3630 goto out_no_pci; 3631 } 3632 3633 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3634 * PCI Tx retries from interfering with C3 CPU state */ 3635 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3636 3637 trans_pcie->pci_dev = pdev; 3638 iwl_disable_interrupts(trans); 3639 3640 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3641 if (trans->hw_rev == 0xffffffff) { 3642 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3643 ret = -EIO; 3644 goto out_no_pci; 3645 } 3646 3647 /* 3648 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3649 * changed, and now the revision step also includes bit 0-1 (no more 3650 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3651 * in the old format. 3652 */ 3653 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3654 trans->hw_rev_step = trans->hw_rev & 0xF; 3655 else 3656 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3657 3658 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3659 3660 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3661 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3662 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3663 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3664 3665 init_waitqueue_head(&trans_pcie->sx_waitq); 3666 3667 3668 if (trans_pcie->msix_enabled) { 3669 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3670 if (ret) 3671 goto out_no_pci; 3672 } else { 3673 ret = iwl_pcie_alloc_ict(trans); 3674 if (ret) 3675 goto out_no_pci; 3676 3677 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3678 iwl_pcie_isr, 3679 iwl_pcie_irq_handler, 3680 IRQF_SHARED, DRV_NAME, trans); 3681 if (ret) { 3682 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3683 goto out_free_ict; 3684 } 3685 } 3686 3687 #ifdef CONFIG_IWLWIFI_DEBUGFS 3688 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3689 mutex_init(&trans_pcie->fw_mon_data.mutex); 3690 #endif 3691 3692 iwl_dbg_tlv_init(trans); 3693 3694 return trans; 3695 3696 out_free_ict: 3697 iwl_pcie_free_ict(trans); 3698 out_no_pci: 3699 destroy_workqueue(trans_pcie->rba.alloc_wq); 3700 out_free_trans: 3701 iwl_trans_free(trans); 3702 return ERR_PTR(ret); 3703 } 3704 3705 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3706 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3707 { 3708 iwl_write_prph(trans, IMR_UREG_CHICK, 3709 iwl_read_prph(trans, IMR_UREG_CHICK) | 3710 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3711 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3712 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3713 (u32)(src_addr & 0xFFFFFFFF)); 3714 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3715 iwl_get_dma_hi_addr(src_addr)); 3716 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3717 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3718 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3719 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3720 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3721 } 3722 3723 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3724 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3725 { 3726 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3727 int ret = -1; 3728 3729 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3730 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3731 ret = wait_event_timeout(trans_pcie->imr_waitq, 3732 trans_pcie->imr_status != 3733 IMR_D2S_REQUESTED, 5 * HZ); 3734 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3735 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3736 iwl_trans_pcie_dump_regs(trans); 3737 return -ETIMEDOUT; 3738 } 3739 trans_pcie->imr_status = IMR_D2S_IDLE; 3740 return 0; 3741 } 3742