1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 18 #include "iwl-drv.h" 19 #include "iwl-trans.h" 20 #include "iwl-csr.h" 21 #include "iwl-prph.h" 22 #include "iwl-scd.h" 23 #include "iwl-agn-hw.h" 24 #include "fw/error-dump.h" 25 #include "fw/dbg.h" 26 #include "fw/api/tx.h" 27 #include "mei/iwl-mei.h" 28 #include "internal.h" 29 #include "iwl-fh.h" 30 #include "iwl-context-info-gen3.h" 31 32 /* extended range in FW SRAM */ 33 #define IWL_FW_MEM_EXTENDED_START 0x40000 34 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35 36 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37 { 38 #define PCI_DUMP_SIZE 352 39 #define PCI_MEM_DUMP_SIZE 64 40 #define PCI_PARENT_DUMP_SIZE 524 41 #define PREFIX_LEN 32 42 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43 struct pci_dev *pdev = trans_pcie->pci_dev; 44 u32 i, pos, alloc_size, *ptr, *buf; 45 char *prefix; 46 47 if (trans_pcie->pcie_dbg_dumped_once) 48 return; 49 50 /* Should be a multiple of 4 */ 51 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54 55 /* Alloc a max size buffer */ 56 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60 61 buf = kmalloc(alloc_size, GFP_ATOMIC); 62 if (!buf) 63 return; 64 prefix = (char *)buf + alloc_size - PREFIX_LEN; 65 66 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67 68 /* Print wifi device registers */ 69 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70 IWL_ERR(trans, "iwlwifi device config registers:\n"); 71 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72 if (pci_read_config_dword(pdev, i, ptr)) 73 goto err_read; 74 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75 76 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78 *ptr = iwl_read32(trans, i); 79 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80 81 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82 if (pos) { 83 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85 if (pci_read_config_dword(pdev, pos + i, ptr)) 86 goto err_read; 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88 32, 4, buf, i, 0); 89 } 90 91 /* Print parent device registers next */ 92 if (!pdev->bus->self) 93 goto out; 94 95 pdev = pdev->bus->self; 96 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97 98 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99 pci_name(pdev)); 100 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101 if (pci_read_config_dword(pdev, i, ptr)) 102 goto err_read; 103 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104 105 /* Print root port AER registers */ 106 pos = 0; 107 pdev = pcie_find_root_port(pdev); 108 if (pdev) 109 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110 if (pos) { 111 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112 pci_name(pdev)); 113 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115 if (pci_read_config_dword(pdev, pos + i, ptr)) 116 goto err_read; 117 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118 4, buf, i, 0); 119 } 120 goto out; 121 122 err_read: 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 IWL_ERR(trans, "Read failed at 0x%X\n", i); 125 out: 126 trans_pcie->pcie_dbg_dumped_once = 1; 127 kfree(buf); 128 } 129 130 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 131 bool retake_ownership) 132 { 133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 135 iwl_set_bit(trans, CSR_GP_CNTRL, 136 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 137 else 138 iwl_set_bit(trans, CSR_RESET, 139 CSR_RESET_REG_FLAG_SW_RESET); 140 usleep_range(5000, 6000); 141 142 if (retake_ownership) 143 return iwl_pcie_prepare_card_hw(trans); 144 145 return 0; 146 } 147 148 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 149 { 150 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 151 152 if (!fw_mon->size) 153 return; 154 155 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 156 fw_mon->physical); 157 158 fw_mon->block = NULL; 159 fw_mon->physical = 0; 160 fw_mon->size = 0; 161 } 162 163 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 164 u8 max_power, u8 min_power) 165 { 166 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 167 void *block = NULL; 168 dma_addr_t physical = 0; 169 u32 size = 0; 170 u8 power; 171 172 if (fw_mon->size) 173 return; 174 175 for (power = max_power; power >= min_power; power--) { 176 size = BIT(power); 177 block = dma_alloc_coherent(trans->dev, size, &physical, 178 GFP_KERNEL | __GFP_NOWARN); 179 if (!block) 180 continue; 181 182 IWL_INFO(trans, 183 "Allocated 0x%08x bytes for firmware monitor.\n", 184 size); 185 break; 186 } 187 188 if (WARN_ON_ONCE(!block)) 189 return; 190 191 if (power != max_power) 192 IWL_ERR(trans, 193 "Sorry - debug buffer is only %luK while you requested %luK\n", 194 (unsigned long)BIT(power - 10), 195 (unsigned long)BIT(max_power - 10)); 196 197 fw_mon->block = block; 198 fw_mon->physical = physical; 199 fw_mon->size = size; 200 } 201 202 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 203 { 204 if (!max_power) { 205 /* default max_power is maximum */ 206 max_power = 26; 207 } else { 208 max_power += 11; 209 } 210 211 if (WARN(max_power > 26, 212 "External buffer size for monitor is too big %d, check the FW TLV\n", 213 max_power)) 214 return; 215 216 if (trans->dbg.fw_mon.size) 217 return; 218 219 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 220 } 221 222 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 223 { 224 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 225 ((reg & 0x0000ffff) | (2 << 28))); 226 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 227 } 228 229 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 230 { 231 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 232 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 233 ((reg & 0x0000ffff) | (3 << 28))); 234 } 235 236 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 237 { 238 if (trans->cfg->apmg_not_supported) 239 return; 240 241 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 242 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 243 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 244 ~APMG_PS_CTRL_MSK_PWR_SRC); 245 else 246 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 247 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 248 ~APMG_PS_CTRL_MSK_PWR_SRC); 249 } 250 251 /* PCI registers */ 252 #define PCI_CFG_RETRY_TIMEOUT 0x041 253 254 void iwl_pcie_apm_config(struct iwl_trans *trans) 255 { 256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 257 u16 lctl; 258 u16 cap; 259 260 /* 261 * L0S states have been found to be unstable with our devices 262 * and in newer hardware they are not officially supported at 263 * all, so we must always set the L0S_DISABLED bit. 264 */ 265 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 266 267 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 268 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 269 270 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 271 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 272 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 273 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 274 trans->ltr_enabled ? "En" : "Dis"); 275 } 276 277 /* 278 * Start up NIC's basic functionality after it has been reset 279 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 280 * NOTE: This does not load uCode nor start the embedded processor 281 */ 282 static int iwl_pcie_apm_init(struct iwl_trans *trans) 283 { 284 int ret; 285 286 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 287 288 /* 289 * Use "set_bit" below rather than "write", to preserve any hardware 290 * bits already set by default after reset. 291 */ 292 293 /* Disable L0S exit timer (platform NMI Work/Around) */ 294 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 295 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 296 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 297 298 /* 299 * Disable L0s without affecting L1; 300 * don't wait for ICH L0s (ICH bug W/A) 301 */ 302 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 303 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 304 305 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 306 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 307 308 /* 309 * Enable HAP INTA (interrupt from management bus) to 310 * wake device's PCI Express link L1a -> L0s 311 */ 312 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 313 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 314 315 iwl_pcie_apm_config(trans); 316 317 /* Configure analog phase-lock-loop before activating to D0A */ 318 if (trans->trans_cfg->base_params->pll_cfg) 319 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 320 321 ret = iwl_finish_nic_init(trans); 322 if (ret) 323 return ret; 324 325 if (trans->cfg->host_interrupt_operation_mode) { 326 /* 327 * This is a bit of an abuse - This is needed for 7260 / 3160 328 * only check host_interrupt_operation_mode even if this is 329 * not related to host_interrupt_operation_mode. 330 * 331 * Enable the oscillator to count wake up time for L1 exit. This 332 * consumes slightly more power (100uA) - but allows to be sure 333 * that we wake up from L1 on time. 334 * 335 * This looks weird: read twice the same register, discard the 336 * value, set a bit, and yet again, read that same register 337 * just to discard the value. But that's the way the hardware 338 * seems to like it. 339 */ 340 iwl_read_prph(trans, OSC_CLK); 341 iwl_read_prph(trans, OSC_CLK); 342 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 343 iwl_read_prph(trans, OSC_CLK); 344 iwl_read_prph(trans, OSC_CLK); 345 } 346 347 /* 348 * Enable DMA clock and wait for it to stabilize. 349 * 350 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 351 * bits do not disable clocks. This preserves any hardware 352 * bits already set by default in "CLK_CTRL_REG" after reset. 353 */ 354 if (!trans->cfg->apmg_not_supported) { 355 iwl_write_prph(trans, APMG_CLK_EN_REG, 356 APMG_CLK_VAL_DMA_CLK_RQT); 357 udelay(20); 358 359 /* Disable L1-Active */ 360 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 361 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 362 363 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 364 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 365 APMG_RTC_INT_STT_RFKILL); 366 } 367 368 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 369 370 return 0; 371 } 372 373 /* 374 * Enable LP XTAL to avoid HW bug where device may consume much power if 375 * FW is not loaded after device reset. LP XTAL is disabled by default 376 * after device HW reset. Do it only if XTAL is fed by internal source. 377 * Configure device's "persistence" mode to avoid resetting XTAL again when 378 * SHRD_HW_RST occurs in S3. 379 */ 380 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 381 { 382 int ret; 383 u32 apmg_gp1_reg; 384 u32 apmg_xtal_cfg_reg; 385 u32 dl_cfg_reg; 386 387 /* Force XTAL ON */ 388 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 389 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 390 391 ret = iwl_trans_pcie_sw_reset(trans, true); 392 393 if (!ret) 394 ret = iwl_finish_nic_init(trans); 395 396 if (WARN_ON(ret)) { 397 /* Release XTAL ON request */ 398 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 399 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 400 return; 401 } 402 403 /* 404 * Clear "disable persistence" to avoid LP XTAL resetting when 405 * SHRD_HW_RST is applied in S3. 406 */ 407 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 408 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 409 410 /* 411 * Force APMG XTAL to be active to prevent its disabling by HW 412 * caused by APMG idle state. 413 */ 414 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 415 SHR_APMG_XTAL_CFG_REG); 416 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 417 apmg_xtal_cfg_reg | 418 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 419 420 ret = iwl_trans_pcie_sw_reset(trans, true); 421 if (ret) 422 IWL_ERR(trans, 423 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 424 425 /* Enable LP XTAL by indirect access through CSR */ 426 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 427 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 428 SHR_APMG_GP1_WF_XTAL_LP_EN | 429 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 430 431 /* Clear delay line clock power up */ 432 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 433 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 434 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 435 436 /* 437 * Enable persistence mode to avoid LP XTAL resetting when 438 * SHRD_HW_RST is applied in S3. 439 */ 440 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 441 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 442 443 /* 444 * Clear "initialization complete" bit to move adapter from 445 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 446 */ 447 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 448 449 /* Activates XTAL resources monitor */ 450 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 451 CSR_MONITOR_XTAL_RESOURCES); 452 453 /* Release XTAL ON request */ 454 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 455 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 456 udelay(10); 457 458 /* Release APMG XTAL */ 459 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 460 apmg_xtal_cfg_reg & 461 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 462 } 463 464 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 465 { 466 int ret; 467 468 /* stop device's busmaster DMA activity */ 469 470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 471 iwl_set_bit(trans, CSR_GP_CNTRL, 472 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 473 474 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 475 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 476 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 477 100); 478 msleep(100); 479 } else { 480 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 481 482 ret = iwl_poll_bit(trans, CSR_RESET, 483 CSR_RESET_REG_FLAG_MASTER_DISABLED, 484 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 485 } 486 487 if (ret < 0) 488 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 489 490 IWL_DEBUG_INFO(trans, "stop master\n"); 491 } 492 493 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 494 { 495 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 496 497 if (op_mode_leave) { 498 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 499 iwl_pcie_apm_init(trans); 500 501 /* inform ME that we are leaving */ 502 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 503 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 504 APMG_PCIDEV_STT_VAL_WAKE_ME); 505 else if (trans->trans_cfg->device_family >= 506 IWL_DEVICE_FAMILY_8000) { 507 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 508 CSR_RESET_LINK_PWR_MGMT_DISABLED); 509 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 510 CSR_HW_IF_CONFIG_REG_PREPARE | 511 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 512 mdelay(1); 513 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 514 CSR_RESET_LINK_PWR_MGMT_DISABLED); 515 } 516 mdelay(5); 517 } 518 519 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 520 521 /* Stop device's DMA activity */ 522 iwl_pcie_apm_stop_master(trans); 523 524 if (trans->cfg->lp_xtal_workaround) { 525 iwl_pcie_apm_lp_xtal_enable(trans); 526 return; 527 } 528 529 iwl_trans_pcie_sw_reset(trans, false); 530 531 /* 532 * Clear "initialization complete" bit to move adapter from 533 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 534 */ 535 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 536 } 537 538 static int iwl_pcie_nic_init(struct iwl_trans *trans) 539 { 540 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 541 int ret; 542 543 /* nic_init */ 544 spin_lock_bh(&trans_pcie->irq_lock); 545 ret = iwl_pcie_apm_init(trans); 546 spin_unlock_bh(&trans_pcie->irq_lock); 547 548 if (ret) 549 return ret; 550 551 iwl_pcie_set_pwr(trans, false); 552 553 iwl_op_mode_nic_config(trans->op_mode); 554 555 /* Allocate the RX queue, or reset if it is already allocated */ 556 ret = iwl_pcie_rx_init(trans); 557 if (ret) 558 return ret; 559 560 /* Allocate or reset and init all Tx and Command queues */ 561 if (iwl_pcie_tx_init(trans)) { 562 iwl_pcie_rx_free(trans); 563 return -ENOMEM; 564 } 565 566 if (trans->trans_cfg->base_params->shadow_reg_enable) { 567 /* enable shadow regs in HW */ 568 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 569 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 570 } 571 572 return 0; 573 } 574 575 #define HW_READY_TIMEOUT (50) 576 577 /* Note: returns poll_bit return value, which is >= 0 if success */ 578 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 579 { 580 int ret; 581 582 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 583 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 584 585 /* See if we got it */ 586 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 587 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 588 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 589 HW_READY_TIMEOUT); 590 591 if (ret >= 0) 592 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 593 594 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 595 return ret; 596 } 597 598 /* Note: returns standard 0/-ERROR code */ 599 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 600 { 601 int ret; 602 int t = 0; 603 int iter; 604 605 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 606 607 ret = iwl_pcie_set_hw_ready(trans); 608 /* If the card is ready, exit 0 */ 609 if (ret >= 0) { 610 trans->csme_own = false; 611 return 0; 612 } 613 614 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 615 CSR_RESET_LINK_PWR_MGMT_DISABLED); 616 usleep_range(1000, 2000); 617 618 for (iter = 0; iter < 10; iter++) { 619 /* If HW is not ready, prepare the conditions to check again */ 620 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 621 CSR_HW_IF_CONFIG_REG_PREPARE); 622 623 do { 624 ret = iwl_pcie_set_hw_ready(trans); 625 if (ret >= 0) { 626 trans->csme_own = false; 627 return 0; 628 } 629 630 if (iwl_mei_is_connected()) { 631 IWL_DEBUG_INFO(trans, 632 "Couldn't prepare the card but SAP is connected\n"); 633 trans->csme_own = true; 634 if (trans->trans_cfg->device_family != 635 IWL_DEVICE_FAMILY_9000) 636 IWL_ERR(trans, 637 "SAP not supported for this NIC family\n"); 638 639 return -EBUSY; 640 } 641 642 usleep_range(200, 1000); 643 t += 200; 644 } while (t < 150000); 645 msleep(25); 646 } 647 648 IWL_ERR(trans, "Couldn't prepare the card\n"); 649 650 return ret; 651 } 652 653 /* 654 * ucode 655 */ 656 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 657 u32 dst_addr, dma_addr_t phy_addr, 658 u32 byte_cnt) 659 { 660 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 661 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 662 663 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 664 dst_addr); 665 666 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 667 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 668 669 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 670 (iwl_get_dma_hi_addr(phy_addr) 671 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 672 673 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 674 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 675 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 676 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 677 678 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 679 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 680 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 681 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 682 } 683 684 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 685 u32 dst_addr, dma_addr_t phy_addr, 686 u32 byte_cnt) 687 { 688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 689 int ret; 690 691 trans_pcie->ucode_write_complete = false; 692 693 if (!iwl_trans_grab_nic_access(trans)) 694 return -EIO; 695 696 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 697 byte_cnt); 698 iwl_trans_release_nic_access(trans); 699 700 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 701 trans_pcie->ucode_write_complete, 5 * HZ); 702 if (!ret) { 703 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 704 iwl_trans_pcie_dump_regs(trans); 705 return -ETIMEDOUT; 706 } 707 708 return 0; 709 } 710 711 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 712 const struct fw_desc *section) 713 { 714 u8 *v_addr; 715 dma_addr_t p_addr; 716 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 717 int ret = 0; 718 719 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 720 section_num); 721 722 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 723 GFP_KERNEL | __GFP_NOWARN); 724 if (!v_addr) { 725 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 726 chunk_sz = PAGE_SIZE; 727 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 728 &p_addr, GFP_KERNEL); 729 if (!v_addr) 730 return -ENOMEM; 731 } 732 733 for (offset = 0; offset < section->len; offset += chunk_sz) { 734 u32 copy_size, dst_addr; 735 bool extended_addr = false; 736 737 copy_size = min_t(u32, chunk_sz, section->len - offset); 738 dst_addr = section->offset + offset; 739 740 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 741 dst_addr <= IWL_FW_MEM_EXTENDED_END) 742 extended_addr = true; 743 744 if (extended_addr) 745 iwl_set_bits_prph(trans, LMPM_CHICK, 746 LMPM_CHICK_EXTENDED_ADDR_SPACE); 747 748 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 749 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 750 copy_size); 751 752 if (extended_addr) 753 iwl_clear_bits_prph(trans, LMPM_CHICK, 754 LMPM_CHICK_EXTENDED_ADDR_SPACE); 755 756 if (ret) { 757 IWL_ERR(trans, 758 "Could not load the [%d] uCode section\n", 759 section_num); 760 break; 761 } 762 } 763 764 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 765 return ret; 766 } 767 768 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 769 const struct fw_img *image, 770 int cpu, 771 int *first_ucode_section) 772 { 773 int shift_param; 774 int i, ret = 0, sec_num = 0x1; 775 u32 val, last_read_idx = 0; 776 777 if (cpu == 1) { 778 shift_param = 0; 779 *first_ucode_section = 0; 780 } else { 781 shift_param = 16; 782 (*first_ucode_section)++; 783 } 784 785 for (i = *first_ucode_section; i < image->num_sec; i++) { 786 last_read_idx = i; 787 788 /* 789 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 790 * CPU1 to CPU2. 791 * PAGING_SEPARATOR_SECTION delimiter - separate between 792 * CPU2 non paged to CPU2 paging sec. 793 */ 794 if (!image->sec[i].data || 795 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 796 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 797 IWL_DEBUG_FW(trans, 798 "Break since Data not valid or Empty section, sec = %d\n", 799 i); 800 break; 801 } 802 803 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 804 if (ret) 805 return ret; 806 807 /* Notify ucode of loaded section number and status */ 808 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 809 val = val | (sec_num << shift_param); 810 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 811 812 sec_num = (sec_num << 1) | 0x1; 813 } 814 815 *first_ucode_section = last_read_idx; 816 817 iwl_enable_interrupts(trans); 818 819 if (trans->trans_cfg->use_tfh) { 820 if (cpu == 1) 821 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 822 0xFFFF); 823 else 824 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825 0xFFFFFFFF); 826 } else { 827 if (cpu == 1) 828 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 829 0xFFFF); 830 else 831 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832 0xFFFFFFFF); 833 } 834 835 return 0; 836 } 837 838 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 839 const struct fw_img *image, 840 int cpu, 841 int *first_ucode_section) 842 { 843 int i, ret = 0; 844 u32 last_read_idx = 0; 845 846 if (cpu == 1) 847 *first_ucode_section = 0; 848 else 849 (*first_ucode_section)++; 850 851 for (i = *first_ucode_section; i < image->num_sec; i++) { 852 last_read_idx = i; 853 854 /* 855 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 856 * CPU1 to CPU2. 857 * PAGING_SEPARATOR_SECTION delimiter - separate between 858 * CPU2 non paged to CPU2 paging sec. 859 */ 860 if (!image->sec[i].data || 861 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 862 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 863 IWL_DEBUG_FW(trans, 864 "Break since Data not valid or Empty section, sec = %d\n", 865 i); 866 break; 867 } 868 869 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 870 if (ret) 871 return ret; 872 } 873 874 *first_ucode_section = last_read_idx; 875 876 return 0; 877 } 878 879 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 880 { 881 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 882 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 883 &trans->dbg.fw_mon_cfg[alloc_id]; 884 struct iwl_dram_data *frag; 885 886 if (!iwl_trans_dbg_ini_valid(trans)) 887 return; 888 889 if (le32_to_cpu(fw_mon_cfg->buf_location) == 890 IWL_FW_INI_LOCATION_SRAM_PATH) { 891 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 892 /* set sram monitor by enabling bit 7 */ 893 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 894 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 895 896 return; 897 } 898 899 if (le32_to_cpu(fw_mon_cfg->buf_location) != 900 IWL_FW_INI_LOCATION_DRAM_PATH || 901 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 902 return; 903 904 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 905 906 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 907 alloc_id); 908 909 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 910 frag->physical >> MON_BUFF_SHIFT_VER2); 911 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 912 (frag->physical + frag->size - 256) >> 913 MON_BUFF_SHIFT_VER2); 914 } 915 916 void iwl_pcie_apply_destination(struct iwl_trans *trans) 917 { 918 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 919 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 920 int i; 921 922 if (iwl_trans_dbg_ini_valid(trans)) { 923 iwl_pcie_apply_destination_ini(trans); 924 return; 925 } 926 927 IWL_INFO(trans, "Applying debug destination %s\n", 928 get_fw_dbg_mode_string(dest->monitor_mode)); 929 930 if (dest->monitor_mode == EXTERNAL_MODE) 931 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 932 else 933 IWL_WARN(trans, "PCI should have external buffer debug\n"); 934 935 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 936 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 937 u32 val = le32_to_cpu(dest->reg_ops[i].val); 938 939 switch (dest->reg_ops[i].op) { 940 case CSR_ASSIGN: 941 iwl_write32(trans, addr, val); 942 break; 943 case CSR_SETBIT: 944 iwl_set_bit(trans, addr, BIT(val)); 945 break; 946 case CSR_CLEARBIT: 947 iwl_clear_bit(trans, addr, BIT(val)); 948 break; 949 case PRPH_ASSIGN: 950 iwl_write_prph(trans, addr, val); 951 break; 952 case PRPH_SETBIT: 953 iwl_set_bits_prph(trans, addr, BIT(val)); 954 break; 955 case PRPH_CLEARBIT: 956 iwl_clear_bits_prph(trans, addr, BIT(val)); 957 break; 958 case PRPH_BLOCKBIT: 959 if (iwl_read_prph(trans, addr) & BIT(val)) { 960 IWL_ERR(trans, 961 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 962 val, addr); 963 goto monitor; 964 } 965 break; 966 default: 967 IWL_ERR(trans, "FW debug - unknown OP %d\n", 968 dest->reg_ops[i].op); 969 break; 970 } 971 } 972 973 monitor: 974 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 975 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 976 fw_mon->physical >> dest->base_shift); 977 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 978 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 979 (fw_mon->physical + fw_mon->size - 980 256) >> dest->end_shift); 981 else 982 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 983 (fw_mon->physical + fw_mon->size) >> 984 dest->end_shift); 985 } 986 } 987 988 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 989 const struct fw_img *image) 990 { 991 int ret = 0; 992 int first_ucode_section; 993 994 IWL_DEBUG_FW(trans, "working with %s CPU\n", 995 image->is_dual_cpus ? "Dual" : "Single"); 996 997 /* load to FW the binary non secured sections of CPU1 */ 998 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 999 if (ret) 1000 return ret; 1001 1002 if (image->is_dual_cpus) { 1003 /* set CPU2 header address */ 1004 iwl_write_prph(trans, 1005 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1006 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1007 1008 /* load to FW the binary sections of CPU2 */ 1009 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1010 &first_ucode_section); 1011 if (ret) 1012 return ret; 1013 } 1014 1015 if (iwl_pcie_dbg_on(trans)) 1016 iwl_pcie_apply_destination(trans); 1017 1018 iwl_enable_interrupts(trans); 1019 1020 /* release CPU reset */ 1021 iwl_write32(trans, CSR_RESET, 0); 1022 1023 return 0; 1024 } 1025 1026 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1027 const struct fw_img *image) 1028 { 1029 int ret = 0; 1030 int first_ucode_section; 1031 1032 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1033 image->is_dual_cpus ? "Dual" : "Single"); 1034 1035 if (iwl_pcie_dbg_on(trans)) 1036 iwl_pcie_apply_destination(trans); 1037 1038 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1039 iwl_read_prph(trans, WFPM_GP2)); 1040 1041 /* 1042 * Set default value. On resume reading the values that were 1043 * zeored can provide debug data on the resume flow. 1044 * This is for debugging only and has no functional impact. 1045 */ 1046 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1047 1048 /* configure the ucode to be ready to get the secured image */ 1049 /* release CPU reset */ 1050 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1051 1052 /* load to FW the binary Secured sections of CPU1 */ 1053 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1054 &first_ucode_section); 1055 if (ret) 1056 return ret; 1057 1058 /* load to FW the binary sections of CPU2 */ 1059 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1060 &first_ucode_section); 1061 } 1062 1063 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1064 { 1065 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1066 bool hw_rfkill = iwl_is_rfkill_set(trans); 1067 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1068 bool report; 1069 1070 if (hw_rfkill) { 1071 set_bit(STATUS_RFKILL_HW, &trans->status); 1072 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1073 } else { 1074 clear_bit(STATUS_RFKILL_HW, &trans->status); 1075 if (trans_pcie->opmode_down) 1076 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1077 } 1078 1079 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080 1081 if (prev != report) 1082 iwl_trans_pcie_rf_kill(trans, report); 1083 1084 return hw_rfkill; 1085 } 1086 1087 struct iwl_causes_list { 1088 u32 cause_num; 1089 u32 mask_reg; 1090 u8 addr; 1091 }; 1092 1093 static const struct iwl_causes_list causes_list_common[] = { 1094 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1095 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1096 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1097 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1098 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1099 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1100 {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 1101 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1102 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1103 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1104 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1105 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1106 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1107 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1108 }; 1109 1110 static const struct iwl_causes_list causes_list_pre_bz[] = { 1111 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1112 }; 1113 1114 static const struct iwl_causes_list causes_list_bz[] = { 1115 {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1116 }; 1117 1118 static void iwl_pcie_map_list(struct iwl_trans *trans, 1119 const struct iwl_causes_list *causes, 1120 int arr_size, int val) 1121 { 1122 int i; 1123 1124 for (i = 0; i < arr_size; i++) { 1125 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1126 iwl_clear_bit(trans, causes[i].mask_reg, 1127 causes[i].cause_num); 1128 } 1129 } 1130 1131 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1132 { 1133 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1134 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1135 /* 1136 * Access all non RX causes and map them to the default irq. 1137 * In case we are missing at least one interrupt vector, 1138 * the first interrupt vector will serve non-RX and FBQ causes. 1139 */ 1140 iwl_pcie_map_list(trans, causes_list_common, 1141 ARRAY_SIZE(causes_list_common), val); 1142 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1143 iwl_pcie_map_list(trans, causes_list_bz, 1144 ARRAY_SIZE(causes_list_bz), val); 1145 else 1146 iwl_pcie_map_list(trans, causes_list_pre_bz, 1147 ARRAY_SIZE(causes_list_pre_bz), val); 1148 } 1149 1150 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1151 { 1152 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1153 u32 offset = 1154 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1155 u32 val, idx; 1156 1157 /* 1158 * The first RX queue - fallback queue, which is designated for 1159 * management frame, command responses etc, is always mapped to the 1160 * first interrupt vector. The other RX queues are mapped to 1161 * the other (N - 2) interrupt vectors. 1162 */ 1163 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1164 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1165 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1166 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1167 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1168 } 1169 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1170 1171 val = MSIX_FH_INT_CAUSES_Q(0); 1172 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1173 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1174 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1175 1176 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1177 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1178 } 1179 1180 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1181 { 1182 struct iwl_trans *trans = trans_pcie->trans; 1183 1184 if (!trans_pcie->msix_enabled) { 1185 if (trans->trans_cfg->mq_rx_supported && 1186 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1187 iwl_write_umac_prph(trans, UREG_CHICK, 1188 UREG_CHICK_MSI_ENABLE); 1189 return; 1190 } 1191 /* 1192 * The IVAR table needs to be configured again after reset, 1193 * but if the device is disabled, we can't write to 1194 * prph. 1195 */ 1196 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1197 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1198 1199 /* 1200 * Each cause from the causes list above and the RX causes is 1201 * represented as a byte in the IVAR table. The first nibble 1202 * represents the bound interrupt vector of the cause, the second 1203 * represents no auto clear for this cause. This will be set if its 1204 * interrupt vector is bound to serve other causes. 1205 */ 1206 iwl_pcie_map_rx_causes(trans); 1207 1208 iwl_pcie_map_non_rx_causes(trans); 1209 } 1210 1211 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1212 { 1213 struct iwl_trans *trans = trans_pcie->trans; 1214 1215 iwl_pcie_conf_msix_hw(trans_pcie); 1216 1217 if (!trans_pcie->msix_enabled) 1218 return; 1219 1220 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1221 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1222 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1223 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1224 } 1225 1226 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1227 { 1228 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1229 1230 lockdep_assert_held(&trans_pcie->mutex); 1231 1232 if (trans_pcie->is_down) 1233 return; 1234 1235 trans_pcie->is_down = true; 1236 1237 /* tell the device to stop sending interrupts */ 1238 iwl_disable_interrupts(trans); 1239 1240 /* device going down, Stop using ICT table */ 1241 iwl_pcie_disable_ict(trans); 1242 1243 /* 1244 * If a HW restart happens during firmware loading, 1245 * then the firmware loading might call this function 1246 * and later it might be called again due to the 1247 * restart. So don't process again if the device is 1248 * already dead. 1249 */ 1250 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1251 IWL_DEBUG_INFO(trans, 1252 "DEVICE_ENABLED bit was set and is now cleared\n"); 1253 iwl_pcie_tx_stop(trans); 1254 iwl_pcie_rx_stop(trans); 1255 1256 /* Power-down device's busmaster DMA clocks */ 1257 if (!trans->cfg->apmg_not_supported) { 1258 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1259 APMG_CLK_VAL_DMA_CLK_RQT); 1260 udelay(5); 1261 } 1262 } 1263 1264 /* Make sure (redundant) we've released our request to stay awake */ 1265 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1266 iwl_clear_bit(trans, CSR_GP_CNTRL, 1267 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1268 else 1269 iwl_clear_bit(trans, CSR_GP_CNTRL, 1270 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1271 1272 /* Stop the device, and put it in low power state */ 1273 iwl_pcie_apm_stop(trans, false); 1274 1275 /* re-take ownership to prevent other users from stealing the device */ 1276 iwl_trans_pcie_sw_reset(trans, true); 1277 1278 /* 1279 * Upon stop, the IVAR table gets erased, so msi-x won't 1280 * work. This causes a bug in RF-KILL flows, since the interrupt 1281 * that enables radio won't fire on the correct irq, and the 1282 * driver won't be able to handle the interrupt. 1283 * Configure the IVAR table again after reset. 1284 */ 1285 iwl_pcie_conf_msix_hw(trans_pcie); 1286 1287 /* 1288 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1289 * This is a bug in certain verions of the hardware. 1290 * Certain devices also keep sending HW RF kill interrupt all 1291 * the time, unless the interrupt is ACKed even if the interrupt 1292 * should be masked. Re-ACK all the interrupts here. 1293 */ 1294 iwl_disable_interrupts(trans); 1295 1296 /* clear all status bits */ 1297 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1298 clear_bit(STATUS_INT_ENABLED, &trans->status); 1299 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1300 1301 /* 1302 * Even if we stop the HW, we still want the RF kill 1303 * interrupt 1304 */ 1305 iwl_enable_rfkill_int(trans); 1306 } 1307 1308 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1309 { 1310 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1311 1312 if (trans_pcie->msix_enabled) { 1313 int i; 1314 1315 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1316 synchronize_irq(trans_pcie->msix_entries[i].vector); 1317 } else { 1318 synchronize_irq(trans_pcie->pci_dev->irq); 1319 } 1320 } 1321 1322 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1323 const struct fw_img *fw, bool run_in_rfkill) 1324 { 1325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1326 bool hw_rfkill; 1327 int ret; 1328 1329 /* This may fail if AMT took ownership of the device */ 1330 if (iwl_pcie_prepare_card_hw(trans)) { 1331 IWL_WARN(trans, "Exit HW not ready\n"); 1332 return -EIO; 1333 } 1334 1335 iwl_enable_rfkill_int(trans); 1336 1337 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1338 1339 /* 1340 * We enabled the RF-Kill interrupt and the handler may very 1341 * well be running. Disable the interrupts to make sure no other 1342 * interrupt can be fired. 1343 */ 1344 iwl_disable_interrupts(trans); 1345 1346 /* Make sure it finished running */ 1347 iwl_pcie_synchronize_irqs(trans); 1348 1349 mutex_lock(&trans_pcie->mutex); 1350 1351 /* If platform's RF_KILL switch is NOT set to KILL */ 1352 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1353 if (hw_rfkill && !run_in_rfkill) { 1354 ret = -ERFKILL; 1355 goto out; 1356 } 1357 1358 /* Someone called stop_device, don't try to start_fw */ 1359 if (trans_pcie->is_down) { 1360 IWL_WARN(trans, 1361 "Can't start_fw since the HW hasn't been started\n"); 1362 ret = -EIO; 1363 goto out; 1364 } 1365 1366 /* make sure rfkill handshake bits are cleared */ 1367 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1368 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1369 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1370 1371 /* clear (again), then enable host interrupts */ 1372 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1373 1374 ret = iwl_pcie_nic_init(trans); 1375 if (ret) { 1376 IWL_ERR(trans, "Unable to init nic\n"); 1377 goto out; 1378 } 1379 1380 /* 1381 * Now, we load the firmware and don't want to be interrupted, even 1382 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1383 * FH_TX interrupt which is needed to load the firmware). If the 1384 * RF-Kill switch is toggled, we will find out after having loaded 1385 * the firmware and return the proper value to the caller. 1386 */ 1387 iwl_enable_fw_load_int(trans); 1388 1389 /* really make sure rfkill handshake bits are cleared */ 1390 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1391 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1392 1393 /* Load the given image to the HW */ 1394 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1395 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1396 else 1397 ret = iwl_pcie_load_given_ucode(trans, fw); 1398 1399 /* re-check RF-Kill state since we may have missed the interrupt */ 1400 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1401 if (hw_rfkill && !run_in_rfkill) 1402 ret = -ERFKILL; 1403 1404 out: 1405 mutex_unlock(&trans_pcie->mutex); 1406 return ret; 1407 } 1408 1409 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1410 { 1411 iwl_pcie_reset_ict(trans); 1412 iwl_pcie_tx_start(trans, scd_addr); 1413 } 1414 1415 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1416 bool was_in_rfkill) 1417 { 1418 bool hw_rfkill; 1419 1420 /* 1421 * Check again since the RF kill state may have changed while 1422 * all the interrupts were disabled, in this case we couldn't 1423 * receive the RF kill interrupt and update the state in the 1424 * op_mode. 1425 * Don't call the op_mode if the rkfill state hasn't changed. 1426 * This allows the op_mode to call stop_device from the rfkill 1427 * notification without endless recursion. Under very rare 1428 * circumstances, we might have a small recursion if the rfkill 1429 * state changed exactly now while we were called from stop_device. 1430 * This is very unlikely but can happen and is supported. 1431 */ 1432 hw_rfkill = iwl_is_rfkill_set(trans); 1433 if (hw_rfkill) { 1434 set_bit(STATUS_RFKILL_HW, &trans->status); 1435 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1436 } else { 1437 clear_bit(STATUS_RFKILL_HW, &trans->status); 1438 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1439 } 1440 if (hw_rfkill != was_in_rfkill) 1441 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1442 } 1443 1444 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1445 { 1446 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1447 bool was_in_rfkill; 1448 1449 iwl_op_mode_time_point(trans->op_mode, 1450 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1451 NULL); 1452 1453 mutex_lock(&trans_pcie->mutex); 1454 trans_pcie->opmode_down = true; 1455 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1456 _iwl_trans_pcie_stop_device(trans); 1457 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1458 mutex_unlock(&trans_pcie->mutex); 1459 } 1460 1461 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1462 { 1463 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1464 IWL_TRANS_GET_PCIE_TRANS(trans); 1465 1466 lockdep_assert_held(&trans_pcie->mutex); 1467 1468 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1469 state ? "disabled" : "enabled"); 1470 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1471 if (trans->trans_cfg->gen2) 1472 _iwl_trans_pcie_gen2_stop_device(trans); 1473 else 1474 _iwl_trans_pcie_stop_device(trans); 1475 } 1476 } 1477 1478 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1479 bool test, bool reset) 1480 { 1481 iwl_disable_interrupts(trans); 1482 1483 /* 1484 * in testing mode, the host stays awake and the 1485 * hardware won't be reset (not even partially) 1486 */ 1487 if (test) 1488 return; 1489 1490 iwl_pcie_disable_ict(trans); 1491 1492 iwl_pcie_synchronize_irqs(trans); 1493 1494 iwl_clear_bit(trans, CSR_GP_CNTRL, 1495 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1496 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1497 1498 if (reset) { 1499 /* 1500 * reset TX queues -- some of their registers reset during S3 1501 * so if we don't reset everything here the D3 image would try 1502 * to execute some invalid memory upon resume 1503 */ 1504 iwl_trans_pcie_tx_reset(trans); 1505 } 1506 1507 iwl_pcie_set_pwr(trans, true); 1508 } 1509 1510 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1511 { 1512 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1513 int ret; 1514 1515 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 1516 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1517 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1518 UREG_DOORBELL_TO_ISR6_RESUME); 1519 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1520 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1521 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1522 CSR_IPC_SLEEP_CONTROL_RESUME); 1523 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1524 UREG_DOORBELL_TO_ISR6_SLEEP_CTRL); 1525 } else { 1526 return 0; 1527 } 1528 1529 ret = wait_event_timeout(trans_pcie->sx_waitq, 1530 trans_pcie->sx_complete, 2 * HZ); 1531 1532 /* Invalidate it toward next suspend or resume */ 1533 trans_pcie->sx_complete = false; 1534 1535 if (!ret) { 1536 IWL_ERR(trans, "Timeout %s D3\n", 1537 suspend ? "entering" : "exiting"); 1538 return -ETIMEDOUT; 1539 } 1540 1541 return 0; 1542 } 1543 1544 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1545 bool reset) 1546 { 1547 int ret; 1548 1549 if (!reset) 1550 /* Enable persistence mode to avoid reset */ 1551 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1552 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1553 1554 ret = iwl_pcie_d3_handshake(trans, true); 1555 if (ret) 1556 return ret; 1557 1558 iwl_pcie_d3_complete_suspend(trans, test, reset); 1559 1560 return 0; 1561 } 1562 1563 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1564 enum iwl_d3_status *status, 1565 bool test, bool reset) 1566 { 1567 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1568 u32 val; 1569 int ret; 1570 1571 if (test) { 1572 iwl_enable_interrupts(trans); 1573 *status = IWL_D3_STATUS_ALIVE; 1574 ret = 0; 1575 goto out; 1576 } 1577 1578 iwl_set_bit(trans, CSR_GP_CNTRL, 1579 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1580 1581 ret = iwl_finish_nic_init(trans); 1582 if (ret) 1583 return ret; 1584 1585 /* 1586 * Reconfigure IVAR table in case of MSIX or reset ict table in 1587 * MSI mode since HW reset erased it. 1588 * Also enables interrupts - none will happen as 1589 * the device doesn't know we're waking it up, only when 1590 * the opmode actually tells it after this call. 1591 */ 1592 iwl_pcie_conf_msix_hw(trans_pcie); 1593 if (!trans_pcie->msix_enabled) 1594 iwl_pcie_reset_ict(trans); 1595 iwl_enable_interrupts(trans); 1596 1597 iwl_pcie_set_pwr(trans, false); 1598 1599 if (!reset) { 1600 iwl_clear_bit(trans, CSR_GP_CNTRL, 1601 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1602 } else { 1603 iwl_trans_pcie_tx_reset(trans); 1604 1605 ret = iwl_pcie_rx_init(trans); 1606 if (ret) { 1607 IWL_ERR(trans, 1608 "Failed to resume the device (RX reset)\n"); 1609 return ret; 1610 } 1611 } 1612 1613 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1614 iwl_read_umac_prph(trans, WFPM_GP2)); 1615 1616 val = iwl_read32(trans, CSR_RESET); 1617 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1618 *status = IWL_D3_STATUS_RESET; 1619 else 1620 *status = IWL_D3_STATUS_ALIVE; 1621 1622 out: 1623 if (*status == IWL_D3_STATUS_ALIVE) 1624 ret = iwl_pcie_d3_handshake(trans, false); 1625 1626 return ret; 1627 } 1628 1629 static void 1630 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1631 struct iwl_trans *trans, 1632 const struct iwl_cfg_trans_params *cfg_trans) 1633 { 1634 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1635 int max_irqs, num_irqs, i, ret; 1636 u16 pci_cmd; 1637 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1638 1639 if (!cfg_trans->mq_rx_supported) 1640 goto enable_msi; 1641 1642 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1643 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1644 1645 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1646 for (i = 0; i < max_irqs; i++) 1647 trans_pcie->msix_entries[i].entry = i; 1648 1649 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1650 MSIX_MIN_INTERRUPT_VECTORS, 1651 max_irqs); 1652 if (num_irqs < 0) { 1653 IWL_DEBUG_INFO(trans, 1654 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1655 num_irqs); 1656 goto enable_msi; 1657 } 1658 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1659 1660 IWL_DEBUG_INFO(trans, 1661 "MSI-X enabled. %d interrupt vectors were allocated\n", 1662 num_irqs); 1663 1664 /* 1665 * In case the OS provides fewer interrupts than requested, different 1666 * causes will share the same interrupt vector as follows: 1667 * One interrupt less: non rx causes shared with FBQ. 1668 * Two interrupts less: non rx causes shared with FBQ and RSS. 1669 * More than two interrupts: we will use fewer RSS queues. 1670 */ 1671 if (num_irqs <= max_irqs - 2) { 1672 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1673 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1674 IWL_SHARED_IRQ_FIRST_RSS; 1675 } else if (num_irqs == max_irqs - 1) { 1676 trans_pcie->trans->num_rx_queues = num_irqs; 1677 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1678 } else { 1679 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1680 } 1681 1682 IWL_DEBUG_INFO(trans, 1683 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1684 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1685 1686 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1687 1688 trans_pcie->alloc_vecs = num_irqs; 1689 trans_pcie->msix_enabled = true; 1690 return; 1691 1692 enable_msi: 1693 ret = pci_enable_msi(pdev); 1694 if (ret) { 1695 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1696 /* enable rfkill interrupt: hw bug w/a */ 1697 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1698 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1699 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1700 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1701 } 1702 } 1703 } 1704 1705 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1706 { 1707 int iter_rx_q, i, ret, cpu, offset; 1708 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1709 1710 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1711 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1712 offset = 1 + i; 1713 for (; i < iter_rx_q ; i++) { 1714 /* 1715 * Get the cpu prior to the place to search 1716 * (i.e. return will be > i - 1). 1717 */ 1718 cpu = cpumask_next(i - offset, cpu_online_mask); 1719 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1720 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1721 &trans_pcie->affinity_mask[i]); 1722 if (ret) 1723 IWL_ERR(trans_pcie->trans, 1724 "Failed to set affinity mask for IRQ %d\n", 1725 trans_pcie->msix_entries[i].vector); 1726 } 1727 } 1728 1729 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1730 struct iwl_trans_pcie *trans_pcie) 1731 { 1732 int i; 1733 1734 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1735 int ret; 1736 struct msix_entry *msix_entry; 1737 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1738 1739 if (!qname) 1740 return -ENOMEM; 1741 1742 msix_entry = &trans_pcie->msix_entries[i]; 1743 ret = devm_request_threaded_irq(&pdev->dev, 1744 msix_entry->vector, 1745 iwl_pcie_msix_isr, 1746 (i == trans_pcie->def_irq) ? 1747 iwl_pcie_irq_msix_handler : 1748 iwl_pcie_irq_rx_msix_handler, 1749 IRQF_SHARED, 1750 qname, 1751 msix_entry); 1752 if (ret) { 1753 IWL_ERR(trans_pcie->trans, 1754 "Error allocating IRQ %d\n", i); 1755 1756 return ret; 1757 } 1758 } 1759 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1760 1761 return 0; 1762 } 1763 1764 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1765 { 1766 u32 hpm, wprot; 1767 1768 switch (trans->trans_cfg->device_family) { 1769 case IWL_DEVICE_FAMILY_9000: 1770 wprot = PREG_PRPH_WPROT_9000; 1771 break; 1772 case IWL_DEVICE_FAMILY_22000: 1773 wprot = PREG_PRPH_WPROT_22000; 1774 break; 1775 default: 1776 return 0; 1777 } 1778 1779 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1780 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1781 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1782 1783 if (wprot_val & PREG_WFPM_ACCESS) { 1784 IWL_ERR(trans, 1785 "Error, can not clear persistence bit\n"); 1786 return -EPERM; 1787 } 1788 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1789 hpm & ~PERSISTENCE_BIT); 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1796 { 1797 int ret; 1798 1799 ret = iwl_finish_nic_init(trans); 1800 if (ret < 0) 1801 return ret; 1802 1803 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1804 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1805 udelay(20); 1806 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1807 HPM_HIPM_GEN_CFG_CR_PG_EN | 1808 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1809 udelay(20); 1810 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1811 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1812 1813 return iwl_trans_pcie_sw_reset(trans, true); 1814 } 1815 1816 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1817 { 1818 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1819 int err; 1820 1821 lockdep_assert_held(&trans_pcie->mutex); 1822 1823 err = iwl_pcie_prepare_card_hw(trans); 1824 if (err) { 1825 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1826 return err; 1827 } 1828 1829 err = iwl_trans_pcie_clear_persistence_bit(trans); 1830 if (err) 1831 return err; 1832 1833 err = iwl_trans_pcie_sw_reset(trans, true); 1834 if (err) 1835 return err; 1836 1837 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1838 trans->trans_cfg->integrated) { 1839 err = iwl_pcie_gen2_force_power_gating(trans); 1840 if (err) 1841 return err; 1842 } 1843 1844 err = iwl_pcie_apm_init(trans); 1845 if (err) 1846 return err; 1847 1848 iwl_pcie_init_msix(trans_pcie); 1849 1850 /* From now on, the op_mode will be kept updated about RF kill state */ 1851 iwl_enable_rfkill_int(trans); 1852 1853 trans_pcie->opmode_down = false; 1854 1855 /* Set is_down to false here so that...*/ 1856 trans_pcie->is_down = false; 1857 1858 /* ...rfkill can call stop_device and set it false if needed */ 1859 iwl_pcie_check_hw_rf_kill(trans); 1860 1861 return 0; 1862 } 1863 1864 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1865 { 1866 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1867 int ret; 1868 1869 mutex_lock(&trans_pcie->mutex); 1870 ret = _iwl_trans_pcie_start_hw(trans); 1871 mutex_unlock(&trans_pcie->mutex); 1872 1873 return ret; 1874 } 1875 1876 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1877 { 1878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1879 1880 mutex_lock(&trans_pcie->mutex); 1881 1882 /* disable interrupts - don't enable HW RF kill interrupt */ 1883 iwl_disable_interrupts(trans); 1884 1885 iwl_pcie_apm_stop(trans, true); 1886 1887 iwl_disable_interrupts(trans); 1888 1889 iwl_pcie_disable_ict(trans); 1890 1891 mutex_unlock(&trans_pcie->mutex); 1892 1893 iwl_pcie_synchronize_irqs(trans); 1894 } 1895 1896 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1897 { 1898 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1899 } 1900 1901 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1902 { 1903 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1904 } 1905 1906 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1907 { 1908 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1909 } 1910 1911 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1912 { 1913 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1914 return 0x00FFFFFF; 1915 else 1916 return 0x000FFFFF; 1917 } 1918 1919 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1920 { 1921 u32 mask = iwl_trans_pcie_prph_msk(trans); 1922 1923 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1924 ((reg & mask) | (3 << 24))); 1925 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1926 } 1927 1928 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1929 u32 val) 1930 { 1931 u32 mask = iwl_trans_pcie_prph_msk(trans); 1932 1933 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1934 ((addr & mask) | (3 << 24))); 1935 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1936 } 1937 1938 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1939 const struct iwl_trans_config *trans_cfg) 1940 { 1941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1942 1943 /* free all first - we might be reconfigured for a different size */ 1944 iwl_pcie_free_rbs_pool(trans); 1945 1946 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 1947 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 1948 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1949 trans->txqs.page_offs = trans_cfg->cb_data_offs; 1950 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1951 1952 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1953 trans_pcie->n_no_reclaim_cmds = 0; 1954 else 1955 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1956 if (trans_pcie->n_no_reclaim_cmds) 1957 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1958 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1959 1960 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1961 trans_pcie->rx_page_order = 1962 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1963 trans_pcie->rx_buf_bytes = 1964 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1965 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1966 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1967 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1968 1969 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1970 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1971 1972 trans->command_groups = trans_cfg->command_groups; 1973 trans->command_groups_size = trans_cfg->command_groups_size; 1974 1975 /* Initialize NAPI here - it should be before registering to mac80211 1976 * in the opmode but after the HW struct is allocated. 1977 * As this function may be called again in some corner cases don't 1978 * do anything if NAPI was already initialized. 1979 */ 1980 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1981 init_dummy_netdev(&trans_pcie->napi_dev); 1982 1983 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1984 } 1985 1986 void iwl_trans_pcie_free(struct iwl_trans *trans) 1987 { 1988 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1989 int i; 1990 1991 iwl_pcie_synchronize_irqs(trans); 1992 1993 if (trans->trans_cfg->gen2) 1994 iwl_txq_gen2_tx_free(trans); 1995 else 1996 iwl_pcie_tx_free(trans); 1997 iwl_pcie_rx_free(trans); 1998 1999 if (trans_pcie->rba.alloc_wq) { 2000 destroy_workqueue(trans_pcie->rba.alloc_wq); 2001 trans_pcie->rba.alloc_wq = NULL; 2002 } 2003 2004 if (trans_pcie->msix_enabled) { 2005 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2006 irq_set_affinity_hint( 2007 trans_pcie->msix_entries[i].vector, 2008 NULL); 2009 } 2010 2011 trans_pcie->msix_enabled = false; 2012 } else { 2013 iwl_pcie_free_ict(trans); 2014 } 2015 2016 iwl_pcie_free_fw_monitor(trans); 2017 2018 if (trans_pcie->pnvm_dram.size) 2019 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 2020 trans_pcie->pnvm_dram.block, 2021 trans_pcie->pnvm_dram.physical); 2022 2023 if (trans_pcie->reduce_power_dram.size) 2024 dma_free_coherent(trans->dev, 2025 trans_pcie->reduce_power_dram.size, 2026 trans_pcie->reduce_power_dram.block, 2027 trans_pcie->reduce_power_dram.physical); 2028 2029 mutex_destroy(&trans_pcie->mutex); 2030 iwl_trans_free(trans); 2031 } 2032 2033 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2034 { 2035 if (state) 2036 set_bit(STATUS_TPOWER_PMI, &trans->status); 2037 else 2038 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2039 } 2040 2041 struct iwl_trans_pcie_removal { 2042 struct pci_dev *pdev; 2043 struct work_struct work; 2044 }; 2045 2046 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2047 { 2048 struct iwl_trans_pcie_removal *removal = 2049 container_of(wk, struct iwl_trans_pcie_removal, work); 2050 struct pci_dev *pdev = removal->pdev; 2051 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2052 2053 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2054 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2055 pci_lock_rescan_remove(); 2056 pci_dev_put(pdev); 2057 pci_stop_and_remove_bus_device(pdev); 2058 pci_unlock_rescan_remove(); 2059 2060 kfree(removal); 2061 module_put(THIS_MODULE); 2062 } 2063 2064 /* 2065 * This version doesn't disable BHs but rather assumes they're 2066 * already disabled. 2067 */ 2068 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2069 { 2070 int ret; 2071 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2072 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2073 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2074 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2075 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2076 2077 spin_lock(&trans_pcie->reg_lock); 2078 2079 if (trans_pcie->cmd_hold_nic_awake) 2080 goto out; 2081 2082 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2083 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2084 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2085 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2086 } 2087 2088 /* this bit wakes up the NIC */ 2089 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2090 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2091 udelay(2); 2092 2093 /* 2094 * These bits say the device is running, and should keep running for 2095 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2096 * but they do not indicate that embedded SRAM is restored yet; 2097 * HW with volatile SRAM must save/restore contents to/from 2098 * host DRAM when sleeping/waking for power-saving. 2099 * Each direction takes approximately 1/4 millisecond; with this 2100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2101 * series of register accesses are expected (e.g. reading Event Log), 2102 * to keep device from sleeping. 2103 * 2104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2105 * SRAM is okay/restored. We don't check that here because this call 2106 * is just for hardware register access; but GP1 MAC_SLEEP 2107 * check is a good idea before accessing the SRAM of HW with 2108 * volatile SRAM (e.g. reading Event Log). 2109 * 2110 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2111 * and do not save/restore SRAM when power cycling. 2112 */ 2113 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2114 if (unlikely(ret < 0)) { 2115 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2116 2117 WARN_ONCE(1, 2118 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2119 cntrl); 2120 2121 iwl_trans_pcie_dump_regs(trans); 2122 2123 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2124 struct iwl_trans_pcie_removal *removal; 2125 2126 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2127 goto err; 2128 2129 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2130 2131 /* 2132 * get a module reference to avoid doing this 2133 * while unloading anyway and to avoid 2134 * scheduling a work with code that's being 2135 * removed. 2136 */ 2137 if (!try_module_get(THIS_MODULE)) { 2138 IWL_ERR(trans, 2139 "Module is being unloaded - abort\n"); 2140 goto err; 2141 } 2142 2143 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2144 if (!removal) { 2145 module_put(THIS_MODULE); 2146 goto err; 2147 } 2148 /* 2149 * we don't need to clear this flag, because 2150 * the trans will be freed and reallocated. 2151 */ 2152 set_bit(STATUS_TRANS_DEAD, &trans->status); 2153 2154 removal->pdev = to_pci_dev(trans->dev); 2155 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2156 pci_dev_get(removal->pdev); 2157 schedule_work(&removal->work); 2158 } else { 2159 iwl_write32(trans, CSR_RESET, 2160 CSR_RESET_REG_FLAG_FORCE_NMI); 2161 } 2162 2163 err: 2164 spin_unlock(&trans_pcie->reg_lock); 2165 return false; 2166 } 2167 2168 out: 2169 /* 2170 * Fool sparse by faking we release the lock - sparse will 2171 * track nic_access anyway. 2172 */ 2173 __release(&trans_pcie->reg_lock); 2174 return true; 2175 } 2176 2177 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2178 { 2179 bool ret; 2180 2181 local_bh_disable(); 2182 ret = __iwl_trans_pcie_grab_nic_access(trans); 2183 if (ret) { 2184 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2185 return ret; 2186 } 2187 local_bh_enable(); 2188 return false; 2189 } 2190 2191 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2192 { 2193 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2194 2195 lockdep_assert_held(&trans_pcie->reg_lock); 2196 2197 /* 2198 * Fool sparse by faking we acquiring the lock - sparse will 2199 * track nic_access anyway. 2200 */ 2201 __acquire(&trans_pcie->reg_lock); 2202 2203 if (trans_pcie->cmd_hold_nic_awake) 2204 goto out; 2205 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2206 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2207 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2208 else 2209 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2210 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2211 /* 2212 * Above we read the CSR_GP_CNTRL register, which will flush 2213 * any previous writes, but we need the write that clears the 2214 * MAC_ACCESS_REQ bit to be performed before any other writes 2215 * scheduled on different CPUs (after we drop reg_lock). 2216 */ 2217 out: 2218 spin_unlock_bh(&trans_pcie->reg_lock); 2219 } 2220 2221 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2222 void *buf, int dwords) 2223 { 2224 int offs = 0; 2225 u32 *vals = buf; 2226 2227 while (offs < dwords) { 2228 /* limit the time we spin here under lock to 1/2s */ 2229 unsigned long end = jiffies + HZ / 2; 2230 bool resched = false; 2231 2232 if (iwl_trans_grab_nic_access(trans)) { 2233 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2234 addr + 4 * offs); 2235 2236 while (offs < dwords) { 2237 vals[offs] = iwl_read32(trans, 2238 HBUS_TARG_MEM_RDAT); 2239 offs++; 2240 2241 if (time_after(jiffies, end)) { 2242 resched = true; 2243 break; 2244 } 2245 } 2246 iwl_trans_release_nic_access(trans); 2247 2248 if (resched) 2249 cond_resched(); 2250 } else { 2251 return -EBUSY; 2252 } 2253 } 2254 2255 return 0; 2256 } 2257 2258 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2259 const void *buf, int dwords) 2260 { 2261 int offs, ret = 0; 2262 const u32 *vals = buf; 2263 2264 if (iwl_trans_grab_nic_access(trans)) { 2265 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2266 for (offs = 0; offs < dwords; offs++) 2267 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2268 vals ? vals[offs] : 0); 2269 iwl_trans_release_nic_access(trans); 2270 } else { 2271 ret = -EBUSY; 2272 } 2273 return ret; 2274 } 2275 2276 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2277 u32 *val) 2278 { 2279 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2280 ofs, val); 2281 } 2282 2283 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2284 { 2285 int i; 2286 2287 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2288 struct iwl_txq *txq = trans->txqs.txq[i]; 2289 2290 if (i == trans->txqs.cmd.q_id) 2291 continue; 2292 2293 spin_lock_bh(&txq->lock); 2294 2295 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2296 txq->block--; 2297 if (!txq->block) { 2298 iwl_write32(trans, HBUS_TARG_WRPTR, 2299 txq->write_ptr | (i << 8)); 2300 } 2301 } else if (block) { 2302 txq->block++; 2303 } 2304 2305 spin_unlock_bh(&txq->lock); 2306 } 2307 } 2308 2309 #define IWL_FLUSH_WAIT_MS 2000 2310 2311 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2312 struct iwl_trans_rxq_dma_data *data) 2313 { 2314 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2315 2316 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2317 return -EINVAL; 2318 2319 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2320 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2321 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2322 data->fr_bd_wid = 0; 2323 2324 return 0; 2325 } 2326 2327 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2328 { 2329 struct iwl_txq *txq; 2330 unsigned long now = jiffies; 2331 bool overflow_tx; 2332 u8 wr_ptr; 2333 2334 /* Make sure the NIC is still alive in the bus */ 2335 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2336 return -ENODEV; 2337 2338 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2339 return -EINVAL; 2340 2341 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2342 txq = trans->txqs.txq[txq_idx]; 2343 2344 spin_lock_bh(&txq->lock); 2345 overflow_tx = txq->overflow_tx || 2346 !skb_queue_empty(&txq->overflow_q); 2347 spin_unlock_bh(&txq->lock); 2348 2349 wr_ptr = READ_ONCE(txq->write_ptr); 2350 2351 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2352 overflow_tx) && 2353 !time_after(jiffies, 2354 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2355 u8 write_ptr = READ_ONCE(txq->write_ptr); 2356 2357 /* 2358 * If write pointer moved during the wait, warn only 2359 * if the TX came from op mode. In case TX came from 2360 * trans layer (overflow TX) don't warn. 2361 */ 2362 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2363 "WR pointer moved while flushing %d -> %d\n", 2364 wr_ptr, write_ptr)) 2365 return -ETIMEDOUT; 2366 wr_ptr = write_ptr; 2367 2368 usleep_range(1000, 2000); 2369 2370 spin_lock_bh(&txq->lock); 2371 overflow_tx = txq->overflow_tx || 2372 !skb_queue_empty(&txq->overflow_q); 2373 spin_unlock_bh(&txq->lock); 2374 } 2375 2376 if (txq->read_ptr != txq->write_ptr) { 2377 IWL_ERR(trans, 2378 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2379 iwl_txq_log_scd_error(trans, txq); 2380 return -ETIMEDOUT; 2381 } 2382 2383 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2384 2385 return 0; 2386 } 2387 2388 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2389 { 2390 int cnt; 2391 int ret = 0; 2392 2393 /* waiting for all the tx frames complete might take a while */ 2394 for (cnt = 0; 2395 cnt < trans->trans_cfg->base_params->num_of_queues; 2396 cnt++) { 2397 2398 if (cnt == trans->txqs.cmd.q_id) 2399 continue; 2400 if (!test_bit(cnt, trans->txqs.queue_used)) 2401 continue; 2402 if (!(BIT(cnt) & txq_bm)) 2403 continue; 2404 2405 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2406 if (ret) 2407 break; 2408 } 2409 2410 return ret; 2411 } 2412 2413 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2414 u32 mask, u32 value) 2415 { 2416 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2417 2418 spin_lock_bh(&trans_pcie->reg_lock); 2419 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2420 spin_unlock_bh(&trans_pcie->reg_lock); 2421 } 2422 2423 static const char *get_csr_string(int cmd) 2424 { 2425 #define IWL_CMD(x) case x: return #x 2426 switch (cmd) { 2427 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2428 IWL_CMD(CSR_INT_COALESCING); 2429 IWL_CMD(CSR_INT); 2430 IWL_CMD(CSR_INT_MASK); 2431 IWL_CMD(CSR_FH_INT_STATUS); 2432 IWL_CMD(CSR_GPIO_IN); 2433 IWL_CMD(CSR_RESET); 2434 IWL_CMD(CSR_GP_CNTRL); 2435 IWL_CMD(CSR_HW_REV); 2436 IWL_CMD(CSR_EEPROM_REG); 2437 IWL_CMD(CSR_EEPROM_GP); 2438 IWL_CMD(CSR_OTP_GP_REG); 2439 IWL_CMD(CSR_GIO_REG); 2440 IWL_CMD(CSR_GP_UCODE_REG); 2441 IWL_CMD(CSR_GP_DRIVER_REG); 2442 IWL_CMD(CSR_UCODE_DRV_GP1); 2443 IWL_CMD(CSR_UCODE_DRV_GP2); 2444 IWL_CMD(CSR_LED_REG); 2445 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2446 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2447 IWL_CMD(CSR_ANA_PLL_CFG); 2448 IWL_CMD(CSR_HW_REV_WA_REG); 2449 IWL_CMD(CSR_MONITOR_STATUS_REG); 2450 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2451 default: 2452 return "UNKNOWN"; 2453 } 2454 #undef IWL_CMD 2455 } 2456 2457 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2458 { 2459 int i; 2460 static const u32 csr_tbl[] = { 2461 CSR_HW_IF_CONFIG_REG, 2462 CSR_INT_COALESCING, 2463 CSR_INT, 2464 CSR_INT_MASK, 2465 CSR_FH_INT_STATUS, 2466 CSR_GPIO_IN, 2467 CSR_RESET, 2468 CSR_GP_CNTRL, 2469 CSR_HW_REV, 2470 CSR_EEPROM_REG, 2471 CSR_EEPROM_GP, 2472 CSR_OTP_GP_REG, 2473 CSR_GIO_REG, 2474 CSR_GP_UCODE_REG, 2475 CSR_GP_DRIVER_REG, 2476 CSR_UCODE_DRV_GP1, 2477 CSR_UCODE_DRV_GP2, 2478 CSR_LED_REG, 2479 CSR_DRAM_INT_TBL_REG, 2480 CSR_GIO_CHICKEN_BITS, 2481 CSR_ANA_PLL_CFG, 2482 CSR_MONITOR_STATUS_REG, 2483 CSR_HW_REV_WA_REG, 2484 CSR_DBG_HPET_MEM_REG 2485 }; 2486 IWL_ERR(trans, "CSR values:\n"); 2487 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2488 "CSR_INT_PERIODIC_REG)\n"); 2489 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2490 IWL_ERR(trans, " %25s: 0X%08x\n", 2491 get_csr_string(csr_tbl[i]), 2492 iwl_read32(trans, csr_tbl[i])); 2493 } 2494 } 2495 2496 #ifdef CONFIG_IWLWIFI_DEBUGFS 2497 /* create and remove of files */ 2498 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2499 debugfs_create_file(#name, mode, parent, trans, \ 2500 &iwl_dbgfs_##name##_ops); \ 2501 } while (0) 2502 2503 /* file operation */ 2504 #define DEBUGFS_READ_FILE_OPS(name) \ 2505 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2506 .read = iwl_dbgfs_##name##_read, \ 2507 .open = simple_open, \ 2508 .llseek = generic_file_llseek, \ 2509 }; 2510 2511 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2512 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2513 .write = iwl_dbgfs_##name##_write, \ 2514 .open = simple_open, \ 2515 .llseek = generic_file_llseek, \ 2516 }; 2517 2518 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2519 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2520 .write = iwl_dbgfs_##name##_write, \ 2521 .read = iwl_dbgfs_##name##_read, \ 2522 .open = simple_open, \ 2523 .llseek = generic_file_llseek, \ 2524 }; 2525 2526 struct iwl_dbgfs_tx_queue_priv { 2527 struct iwl_trans *trans; 2528 }; 2529 2530 struct iwl_dbgfs_tx_queue_state { 2531 loff_t pos; 2532 }; 2533 2534 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2535 { 2536 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2537 struct iwl_dbgfs_tx_queue_state *state; 2538 2539 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2540 return NULL; 2541 2542 state = kmalloc(sizeof(*state), GFP_KERNEL); 2543 if (!state) 2544 return NULL; 2545 state->pos = *pos; 2546 return state; 2547 } 2548 2549 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2550 void *v, loff_t *pos) 2551 { 2552 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2553 struct iwl_dbgfs_tx_queue_state *state = v; 2554 2555 *pos = ++state->pos; 2556 2557 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2558 return NULL; 2559 2560 return state; 2561 } 2562 2563 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2564 { 2565 kfree(v); 2566 } 2567 2568 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2569 { 2570 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2571 struct iwl_dbgfs_tx_queue_state *state = v; 2572 struct iwl_trans *trans = priv->trans; 2573 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2574 2575 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2576 (unsigned int)state->pos, 2577 !!test_bit(state->pos, trans->txqs.queue_used), 2578 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2579 if (txq) 2580 seq_printf(seq, 2581 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2582 txq->read_ptr, txq->write_ptr, 2583 txq->need_update, txq->frozen, 2584 txq->n_window, txq->ampdu); 2585 else 2586 seq_puts(seq, "(unallocated)"); 2587 2588 if (state->pos == trans->txqs.cmd.q_id) 2589 seq_puts(seq, " (HCMD)"); 2590 seq_puts(seq, "\n"); 2591 2592 return 0; 2593 } 2594 2595 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2596 .start = iwl_dbgfs_tx_queue_seq_start, 2597 .next = iwl_dbgfs_tx_queue_seq_next, 2598 .stop = iwl_dbgfs_tx_queue_seq_stop, 2599 .show = iwl_dbgfs_tx_queue_seq_show, 2600 }; 2601 2602 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2603 { 2604 struct iwl_dbgfs_tx_queue_priv *priv; 2605 2606 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2607 sizeof(*priv)); 2608 2609 if (!priv) 2610 return -ENOMEM; 2611 2612 priv->trans = inode->i_private; 2613 return 0; 2614 } 2615 2616 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2617 char __user *user_buf, 2618 size_t count, loff_t *ppos) 2619 { 2620 struct iwl_trans *trans = file->private_data; 2621 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2622 char *buf; 2623 int pos = 0, i, ret; 2624 size_t bufsz; 2625 2626 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2627 2628 if (!trans_pcie->rxq) 2629 return -EAGAIN; 2630 2631 buf = kzalloc(bufsz, GFP_KERNEL); 2632 if (!buf) 2633 return -ENOMEM; 2634 2635 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2636 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2637 2638 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2639 i); 2640 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2641 rxq->read); 2642 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2643 rxq->write); 2644 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2645 rxq->write_actual); 2646 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2647 rxq->need_update); 2648 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2649 rxq->free_count); 2650 if (rxq->rb_stts) { 2651 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2652 rxq)); 2653 pos += scnprintf(buf + pos, bufsz - pos, 2654 "\tclosed_rb_num: %u\n", 2655 r & 0x0FFF); 2656 } else { 2657 pos += scnprintf(buf + pos, bufsz - pos, 2658 "\tclosed_rb_num: Not Allocated\n"); 2659 } 2660 } 2661 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2662 kfree(buf); 2663 2664 return ret; 2665 } 2666 2667 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2668 char __user *user_buf, 2669 size_t count, loff_t *ppos) 2670 { 2671 struct iwl_trans *trans = file->private_data; 2672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2673 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2674 2675 int pos = 0; 2676 char *buf; 2677 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2678 ssize_t ret; 2679 2680 buf = kzalloc(bufsz, GFP_KERNEL); 2681 if (!buf) 2682 return -ENOMEM; 2683 2684 pos += scnprintf(buf + pos, bufsz - pos, 2685 "Interrupt Statistics Report:\n"); 2686 2687 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2688 isr_stats->hw); 2689 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2690 isr_stats->sw); 2691 if (isr_stats->sw || isr_stats->hw) { 2692 pos += scnprintf(buf + pos, bufsz - pos, 2693 "\tLast Restarting Code: 0x%X\n", 2694 isr_stats->err_code); 2695 } 2696 #ifdef CONFIG_IWLWIFI_DEBUG 2697 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2698 isr_stats->sch); 2699 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2700 isr_stats->alive); 2701 #endif 2702 pos += scnprintf(buf + pos, bufsz - pos, 2703 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2704 2705 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2706 isr_stats->ctkill); 2707 2708 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2709 isr_stats->wakeup); 2710 2711 pos += scnprintf(buf + pos, bufsz - pos, 2712 "Rx command responses:\t\t %u\n", isr_stats->rx); 2713 2714 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2715 isr_stats->tx); 2716 2717 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2718 isr_stats->unhandled); 2719 2720 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2721 kfree(buf); 2722 return ret; 2723 } 2724 2725 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2726 const char __user *user_buf, 2727 size_t count, loff_t *ppos) 2728 { 2729 struct iwl_trans *trans = file->private_data; 2730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2731 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2732 u32 reset_flag; 2733 int ret; 2734 2735 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2736 if (ret) 2737 return ret; 2738 if (reset_flag == 0) 2739 memset(isr_stats, 0, sizeof(*isr_stats)); 2740 2741 return count; 2742 } 2743 2744 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2745 const char __user *user_buf, 2746 size_t count, loff_t *ppos) 2747 { 2748 struct iwl_trans *trans = file->private_data; 2749 2750 iwl_pcie_dump_csr(trans); 2751 2752 return count; 2753 } 2754 2755 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2756 char __user *user_buf, 2757 size_t count, loff_t *ppos) 2758 { 2759 struct iwl_trans *trans = file->private_data; 2760 char *buf = NULL; 2761 ssize_t ret; 2762 2763 ret = iwl_dump_fh(trans, &buf); 2764 if (ret < 0) 2765 return ret; 2766 if (!buf) 2767 return -EINVAL; 2768 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2769 kfree(buf); 2770 return ret; 2771 } 2772 2773 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2774 char __user *user_buf, 2775 size_t count, loff_t *ppos) 2776 { 2777 struct iwl_trans *trans = file->private_data; 2778 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2779 char buf[100]; 2780 int pos; 2781 2782 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2783 trans_pcie->debug_rfkill, 2784 !(iwl_read32(trans, CSR_GP_CNTRL) & 2785 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2786 2787 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2788 } 2789 2790 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2791 const char __user *user_buf, 2792 size_t count, loff_t *ppos) 2793 { 2794 struct iwl_trans *trans = file->private_data; 2795 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2796 bool new_value; 2797 int ret; 2798 2799 ret = kstrtobool_from_user(user_buf, count, &new_value); 2800 if (ret) 2801 return ret; 2802 if (new_value == trans_pcie->debug_rfkill) 2803 return count; 2804 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2805 trans_pcie->debug_rfkill, new_value); 2806 trans_pcie->debug_rfkill = new_value; 2807 iwl_pcie_handle_rfkill_irq(trans); 2808 2809 return count; 2810 } 2811 2812 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2813 struct file *file) 2814 { 2815 struct iwl_trans *trans = inode->i_private; 2816 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2817 2818 if (!trans->dbg.dest_tlv || 2819 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2820 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2821 return -ENOENT; 2822 } 2823 2824 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2825 return -EBUSY; 2826 2827 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2828 return simple_open(inode, file); 2829 } 2830 2831 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2832 struct file *file) 2833 { 2834 struct iwl_trans_pcie *trans_pcie = 2835 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2836 2837 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2838 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2839 return 0; 2840 } 2841 2842 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2843 void *buf, ssize_t *size, 2844 ssize_t *bytes_copied) 2845 { 2846 int buf_size_left = count - *bytes_copied; 2847 2848 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2849 if (*size > buf_size_left) 2850 *size = buf_size_left; 2851 2852 *size -= copy_to_user(user_buf, buf, *size); 2853 *bytes_copied += *size; 2854 2855 if (buf_size_left == *size) 2856 return true; 2857 return false; 2858 } 2859 2860 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2861 char __user *user_buf, 2862 size_t count, loff_t *ppos) 2863 { 2864 struct iwl_trans *trans = file->private_data; 2865 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2866 void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2867 struct cont_rec *data = &trans_pcie->fw_mon_data; 2868 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2869 ssize_t size, bytes_copied = 0; 2870 bool b_full; 2871 2872 if (trans->dbg.dest_tlv) { 2873 write_ptr_addr = 2874 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2875 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2876 } else { 2877 write_ptr_addr = MON_BUFF_WRPTR; 2878 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2879 } 2880 2881 if (unlikely(!trans->dbg.rec_on)) 2882 return 0; 2883 2884 mutex_lock(&data->mutex); 2885 if (data->state == 2886 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2887 mutex_unlock(&data->mutex); 2888 return 0; 2889 } 2890 2891 /* write_ptr position in bytes rather then DW */ 2892 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2893 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2894 2895 if (data->prev_wrap_cnt == wrap_cnt) { 2896 size = write_ptr - data->prev_wr_ptr; 2897 curr_buf = cpu_addr + data->prev_wr_ptr; 2898 b_full = iwl_write_to_user_buf(user_buf, count, 2899 curr_buf, &size, 2900 &bytes_copied); 2901 data->prev_wr_ptr += size; 2902 2903 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2904 write_ptr < data->prev_wr_ptr) { 2905 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2906 curr_buf = cpu_addr + data->prev_wr_ptr; 2907 b_full = iwl_write_to_user_buf(user_buf, count, 2908 curr_buf, &size, 2909 &bytes_copied); 2910 data->prev_wr_ptr += size; 2911 2912 if (!b_full) { 2913 size = write_ptr; 2914 b_full = iwl_write_to_user_buf(user_buf, count, 2915 cpu_addr, &size, 2916 &bytes_copied); 2917 data->prev_wr_ptr = size; 2918 data->prev_wrap_cnt++; 2919 } 2920 } else { 2921 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2922 write_ptr > data->prev_wr_ptr) 2923 IWL_WARN(trans, 2924 "write pointer passed previous write pointer, start copying from the beginning\n"); 2925 else if (!unlikely(data->prev_wrap_cnt == 0 && 2926 data->prev_wr_ptr == 0)) 2927 IWL_WARN(trans, 2928 "monitor data is out of sync, start copying from the beginning\n"); 2929 2930 size = write_ptr; 2931 b_full = iwl_write_to_user_buf(user_buf, count, 2932 cpu_addr, &size, 2933 &bytes_copied); 2934 data->prev_wr_ptr = size; 2935 data->prev_wrap_cnt = wrap_cnt; 2936 } 2937 2938 mutex_unlock(&data->mutex); 2939 2940 return bytes_copied; 2941 } 2942 2943 static ssize_t iwl_dbgfs_rf_read(struct file *file, 2944 char __user *user_buf, 2945 size_t count, loff_t *ppos) 2946 { 2947 struct iwl_trans *trans = file->private_data; 2948 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2949 2950 if (!trans_pcie->rf_name[0]) 2951 return -ENODEV; 2952 2953 return simple_read_from_buffer(user_buf, count, ppos, 2954 trans_pcie->rf_name, 2955 strlen(trans_pcie->rf_name)); 2956 } 2957 2958 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2959 DEBUGFS_READ_FILE_OPS(fh_reg); 2960 DEBUGFS_READ_FILE_OPS(rx_queue); 2961 DEBUGFS_WRITE_FILE_OPS(csr); 2962 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2963 DEBUGFS_READ_FILE_OPS(rf); 2964 2965 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2966 .owner = THIS_MODULE, 2967 .open = iwl_dbgfs_tx_queue_open, 2968 .read = seq_read, 2969 .llseek = seq_lseek, 2970 .release = seq_release_private, 2971 }; 2972 2973 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2974 .read = iwl_dbgfs_monitor_data_read, 2975 .open = iwl_dbgfs_monitor_data_open, 2976 .release = iwl_dbgfs_monitor_data_release, 2977 }; 2978 2979 /* Create the debugfs files and directories */ 2980 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2981 { 2982 struct dentry *dir = trans->dbgfs_dir; 2983 2984 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2985 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2986 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2987 DEBUGFS_ADD_FILE(csr, dir, 0200); 2988 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2989 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2990 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2991 DEBUGFS_ADD_FILE(rf, dir, 0400); 2992 } 2993 2994 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2995 { 2996 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2997 struct cont_rec *data = &trans_pcie->fw_mon_data; 2998 2999 mutex_lock(&data->mutex); 3000 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3001 mutex_unlock(&data->mutex); 3002 } 3003 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3004 3005 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3006 { 3007 u32 cmdlen = 0; 3008 int i; 3009 3010 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 3011 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3012 3013 return cmdlen; 3014 } 3015 3016 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3017 struct iwl_fw_error_dump_data **data, 3018 int allocated_rb_nums) 3019 { 3020 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3021 int max_len = trans_pcie->rx_buf_bytes; 3022 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3023 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3024 u32 i, r, j, rb_len = 0; 3025 3026 spin_lock(&rxq->lock); 3027 3028 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3029 3030 for (i = rxq->read, j = 0; 3031 i != r && j < allocated_rb_nums; 3032 i = (i + 1) & RX_QUEUE_MASK, j++) { 3033 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3034 struct iwl_fw_error_dump_rb *rb; 3035 3036 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3037 max_len, DMA_FROM_DEVICE); 3038 3039 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3040 3041 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3042 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3043 rb = (void *)(*data)->data; 3044 rb->index = cpu_to_le32(i); 3045 memcpy(rb->data, page_address(rxb->page), max_len); 3046 3047 *data = iwl_fw_error_next_data(*data); 3048 } 3049 3050 spin_unlock(&rxq->lock); 3051 3052 return rb_len; 3053 } 3054 #define IWL_CSR_TO_DUMP (0x250) 3055 3056 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3057 struct iwl_fw_error_dump_data **data) 3058 { 3059 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3060 __le32 *val; 3061 int i; 3062 3063 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3064 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3065 val = (void *)(*data)->data; 3066 3067 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3068 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3069 3070 *data = iwl_fw_error_next_data(*data); 3071 3072 return csr_len; 3073 } 3074 3075 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3076 struct iwl_fw_error_dump_data **data) 3077 { 3078 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3079 __le32 *val; 3080 int i; 3081 3082 if (!iwl_trans_grab_nic_access(trans)) 3083 return 0; 3084 3085 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3086 (*data)->len = cpu_to_le32(fh_regs_len); 3087 val = (void *)(*data)->data; 3088 3089 if (!trans->trans_cfg->gen2) 3090 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3091 i += sizeof(u32)) 3092 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3093 else 3094 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3095 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3096 i += sizeof(u32)) 3097 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3098 i)); 3099 3100 iwl_trans_release_nic_access(trans); 3101 3102 *data = iwl_fw_error_next_data(*data); 3103 3104 return sizeof(**data) + fh_regs_len; 3105 } 3106 3107 static u32 3108 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3109 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3110 u32 monitor_len) 3111 { 3112 u32 buf_size_in_dwords = (monitor_len >> 2); 3113 u32 *buffer = (u32 *)fw_mon_data->data; 3114 u32 i; 3115 3116 if (!iwl_trans_grab_nic_access(trans)) 3117 return 0; 3118 3119 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3120 for (i = 0; i < buf_size_in_dwords; i++) 3121 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3122 MON_DMARB_RD_DATA_ADDR); 3123 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3124 3125 iwl_trans_release_nic_access(trans); 3126 3127 return monitor_len; 3128 } 3129 3130 static void 3131 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3132 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3133 { 3134 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3135 3136 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3137 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3138 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3139 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3140 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3141 } else if (trans->dbg.dest_tlv) { 3142 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3143 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3144 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3145 } else { 3146 base = MON_BUFF_BASE_ADDR; 3147 write_ptr = MON_BUFF_WRPTR; 3148 wrap_cnt = MON_BUFF_CYCLE_CNT; 3149 } 3150 3151 write_ptr_val = iwl_read_prph(trans, write_ptr); 3152 fw_mon_data->fw_mon_cycle_cnt = 3153 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3154 fw_mon_data->fw_mon_base_ptr = 3155 cpu_to_le32(iwl_read_prph(trans, base)); 3156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3157 fw_mon_data->fw_mon_base_high_ptr = 3158 cpu_to_le32(iwl_read_prph(trans, base_high)); 3159 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3160 /* convert wrtPtr to DWs, to align with all HWs */ 3161 write_ptr_val >>= 2; 3162 } 3163 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3164 } 3165 3166 static u32 3167 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3168 struct iwl_fw_error_dump_data **data, 3169 u32 monitor_len) 3170 { 3171 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3172 u32 len = 0; 3173 3174 if (trans->dbg.dest_tlv || 3175 (fw_mon->size && 3176 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3177 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3178 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3179 3180 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3181 fw_mon_data = (void *)(*data)->data; 3182 3183 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3184 3185 len += sizeof(**data) + sizeof(*fw_mon_data); 3186 if (fw_mon->size) { 3187 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3188 monitor_len = fw_mon->size; 3189 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3190 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3191 /* 3192 * Update pointers to reflect actual values after 3193 * shifting 3194 */ 3195 if (trans->dbg.dest_tlv->version) { 3196 base = (iwl_read_prph(trans, base) & 3197 IWL_LDBG_M2S_BUF_BA_MSK) << 3198 trans->dbg.dest_tlv->base_shift; 3199 base *= IWL_M2S_UNIT_SIZE; 3200 base += trans->cfg->smem_offset; 3201 } else { 3202 base = iwl_read_prph(trans, base) << 3203 trans->dbg.dest_tlv->base_shift; 3204 } 3205 3206 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3207 monitor_len / sizeof(u32)); 3208 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3209 monitor_len = 3210 iwl_trans_pci_dump_marbh_monitor(trans, 3211 fw_mon_data, 3212 monitor_len); 3213 } else { 3214 /* Didn't match anything - output no monitor data */ 3215 monitor_len = 0; 3216 } 3217 3218 len += monitor_len; 3219 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3220 } 3221 3222 return len; 3223 } 3224 3225 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3226 { 3227 if (trans->dbg.fw_mon.size) { 3228 *len += sizeof(struct iwl_fw_error_dump_data) + 3229 sizeof(struct iwl_fw_error_dump_fw_mon) + 3230 trans->dbg.fw_mon.size; 3231 return trans->dbg.fw_mon.size; 3232 } else if (trans->dbg.dest_tlv) { 3233 u32 base, end, cfg_reg, monitor_len; 3234 3235 if (trans->dbg.dest_tlv->version == 1) { 3236 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3237 cfg_reg = iwl_read_prph(trans, cfg_reg); 3238 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3239 trans->dbg.dest_tlv->base_shift; 3240 base *= IWL_M2S_UNIT_SIZE; 3241 base += trans->cfg->smem_offset; 3242 3243 monitor_len = 3244 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3245 trans->dbg.dest_tlv->end_shift; 3246 monitor_len *= IWL_M2S_UNIT_SIZE; 3247 } else { 3248 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3249 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3250 3251 base = iwl_read_prph(trans, base) << 3252 trans->dbg.dest_tlv->base_shift; 3253 end = iwl_read_prph(trans, end) << 3254 trans->dbg.dest_tlv->end_shift; 3255 3256 /* Make "end" point to the actual end */ 3257 if (trans->trans_cfg->device_family >= 3258 IWL_DEVICE_FAMILY_8000 || 3259 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3260 end += (1 << trans->dbg.dest_tlv->end_shift); 3261 monitor_len = end - base; 3262 } 3263 *len += sizeof(struct iwl_fw_error_dump_data) + 3264 sizeof(struct iwl_fw_error_dump_fw_mon) + 3265 monitor_len; 3266 return monitor_len; 3267 } 3268 return 0; 3269 } 3270 3271 static struct iwl_trans_dump_data * 3272 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3273 u32 dump_mask, 3274 const struct iwl_dump_sanitize_ops *sanitize_ops, 3275 void *sanitize_ctx) 3276 { 3277 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3278 struct iwl_fw_error_dump_data *data; 3279 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3280 struct iwl_fw_error_dump_txcmd *txcmd; 3281 struct iwl_trans_dump_data *dump_data; 3282 u32 len, num_rbs = 0, monitor_len = 0; 3283 int i, ptr; 3284 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3285 !trans->trans_cfg->mq_rx_supported && 3286 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3287 3288 if (!dump_mask) 3289 return NULL; 3290 3291 /* transport dump header */ 3292 len = sizeof(*dump_data); 3293 3294 /* host commands */ 3295 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3296 len += sizeof(*data) + 3297 cmdq->n_window * (sizeof(*txcmd) + 3298 TFD_MAX_PAYLOAD_SIZE); 3299 3300 /* FW monitor */ 3301 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3302 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3303 3304 /* CSR registers */ 3305 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3306 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3307 3308 /* FH registers */ 3309 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3310 if (trans->trans_cfg->gen2) 3311 len += sizeof(*data) + 3312 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3313 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3314 else 3315 len += sizeof(*data) + 3316 (FH_MEM_UPPER_BOUND - 3317 FH_MEM_LOWER_BOUND); 3318 } 3319 3320 if (dump_rbs) { 3321 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3322 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3323 /* RBs */ 3324 num_rbs = 3325 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3326 & 0x0FFF; 3327 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3328 len += num_rbs * (sizeof(*data) + 3329 sizeof(struct iwl_fw_error_dump_rb) + 3330 (PAGE_SIZE << trans_pcie->rx_page_order)); 3331 } 3332 3333 /* Paged memory for gen2 HW */ 3334 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3335 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3336 len += sizeof(*data) + 3337 sizeof(struct iwl_fw_error_dump_paging) + 3338 trans->init_dram.paging[i].size; 3339 3340 dump_data = vzalloc(len); 3341 if (!dump_data) 3342 return NULL; 3343 3344 len = 0; 3345 data = (void *)dump_data->data; 3346 3347 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3348 u16 tfd_size = trans->txqs.tfd.size; 3349 3350 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3351 txcmd = (void *)data->data; 3352 spin_lock_bh(&cmdq->lock); 3353 ptr = cmdq->write_ptr; 3354 for (i = 0; i < cmdq->n_window; i++) { 3355 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3356 u8 tfdidx; 3357 u32 caplen, cmdlen; 3358 3359 if (trans->trans_cfg->use_tfh) 3360 tfdidx = idx; 3361 else 3362 tfdidx = ptr; 3363 3364 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3365 (u8 *)cmdq->tfds + 3366 tfd_size * tfdidx); 3367 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3368 3369 if (cmdlen) { 3370 len += sizeof(*txcmd) + caplen; 3371 txcmd->cmdlen = cpu_to_le32(cmdlen); 3372 txcmd->caplen = cpu_to_le32(caplen); 3373 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3374 caplen); 3375 if (sanitize_ops && sanitize_ops->frob_hcmd) 3376 sanitize_ops->frob_hcmd(sanitize_ctx, 3377 txcmd->data, 3378 caplen); 3379 txcmd = (void *)((u8 *)txcmd->data + caplen); 3380 } 3381 3382 ptr = iwl_txq_dec_wrap(trans, ptr); 3383 } 3384 spin_unlock_bh(&cmdq->lock); 3385 3386 data->len = cpu_to_le32(len); 3387 len += sizeof(*data); 3388 data = iwl_fw_error_next_data(data); 3389 } 3390 3391 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3392 len += iwl_trans_pcie_dump_csr(trans, &data); 3393 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3394 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3395 if (dump_rbs) 3396 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3397 3398 /* Paged memory for gen2 HW */ 3399 if (trans->trans_cfg->gen2 && 3400 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3401 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3402 struct iwl_fw_error_dump_paging *paging; 3403 u32 page_len = trans->init_dram.paging[i].size; 3404 3405 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3406 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3407 paging = (void *)data->data; 3408 paging->index = cpu_to_le32(i); 3409 memcpy(paging->data, 3410 trans->init_dram.paging[i].block, page_len); 3411 data = iwl_fw_error_next_data(data); 3412 3413 len += sizeof(*data) + sizeof(*paging) + page_len; 3414 } 3415 } 3416 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3417 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3418 3419 dump_data->len = len; 3420 3421 return dump_data; 3422 } 3423 3424 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3425 { 3426 if (enable) 3427 iwl_enable_interrupts(trans); 3428 else 3429 iwl_disable_interrupts(trans); 3430 } 3431 3432 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3433 { 3434 u32 inta_addr, sw_err_bit; 3435 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3436 3437 if (trans_pcie->msix_enabled) { 3438 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3439 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3440 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3441 else 3442 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3443 } else { 3444 inta_addr = CSR_INT; 3445 sw_err_bit = CSR_INT_BIT_SW_ERR; 3446 } 3447 3448 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3449 } 3450 3451 #define IWL_TRANS_COMMON_OPS \ 3452 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3453 .write8 = iwl_trans_pcie_write8, \ 3454 .write32 = iwl_trans_pcie_write32, \ 3455 .read32 = iwl_trans_pcie_read32, \ 3456 .read_prph = iwl_trans_pcie_read_prph, \ 3457 .write_prph = iwl_trans_pcie_write_prph, \ 3458 .read_mem = iwl_trans_pcie_read_mem, \ 3459 .write_mem = iwl_trans_pcie_write_mem, \ 3460 .read_config32 = iwl_trans_pcie_read_config32, \ 3461 .configure = iwl_trans_pcie_configure, \ 3462 .set_pmi = iwl_trans_pcie_set_pmi, \ 3463 .sw_reset = iwl_trans_pcie_sw_reset, \ 3464 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3465 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3466 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3467 .dump_data = iwl_trans_pcie_dump_data, \ 3468 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3469 .d3_resume = iwl_trans_pcie_d3_resume, \ 3470 .interrupts = iwl_trans_pci_interrupts, \ 3471 .sync_nmi = iwl_trans_pcie_sync_nmi \ 3472 3473 static const struct iwl_trans_ops trans_ops_pcie = { 3474 IWL_TRANS_COMMON_OPS, 3475 .start_hw = iwl_trans_pcie_start_hw, 3476 .fw_alive = iwl_trans_pcie_fw_alive, 3477 .start_fw = iwl_trans_pcie_start_fw, 3478 .stop_device = iwl_trans_pcie_stop_device, 3479 3480 .send_cmd = iwl_pcie_enqueue_hcmd, 3481 3482 .tx = iwl_trans_pcie_tx, 3483 .reclaim = iwl_txq_reclaim, 3484 3485 .txq_disable = iwl_trans_pcie_txq_disable, 3486 .txq_enable = iwl_trans_pcie_txq_enable, 3487 3488 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3489 3490 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3491 3492 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3493 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3494 #ifdef CONFIG_IWLWIFI_DEBUGFS 3495 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3496 #endif 3497 }; 3498 3499 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3500 IWL_TRANS_COMMON_OPS, 3501 .start_hw = iwl_trans_pcie_start_hw, 3502 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3503 .start_fw = iwl_trans_pcie_gen2_start_fw, 3504 .stop_device = iwl_trans_pcie_gen2_stop_device, 3505 3506 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3507 3508 .tx = iwl_txq_gen2_tx, 3509 .reclaim = iwl_txq_reclaim, 3510 3511 .set_q_ptrs = iwl_txq_set_q_ptrs, 3512 3513 .txq_alloc = iwl_txq_dyn_alloc, 3514 .txq_free = iwl_txq_dyn_free, 3515 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3516 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3517 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3518 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3519 #ifdef CONFIG_IWLWIFI_DEBUGFS 3520 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3521 #endif 3522 }; 3523 3524 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3525 const struct pci_device_id *ent, 3526 const struct iwl_cfg_trans_params *cfg_trans) 3527 { 3528 struct iwl_trans_pcie *trans_pcie; 3529 struct iwl_trans *trans; 3530 int ret, addr_size; 3531 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3532 void __iomem * const *table; 3533 3534 if (!cfg_trans->gen2) 3535 ops = &trans_ops_pcie; 3536 3537 ret = pcim_enable_device(pdev); 3538 if (ret) 3539 return ERR_PTR(ret); 3540 3541 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3542 cfg_trans); 3543 if (!trans) 3544 return ERR_PTR(-ENOMEM); 3545 3546 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3547 3548 trans_pcie->trans = trans; 3549 trans_pcie->opmode_down = true; 3550 spin_lock_init(&trans_pcie->irq_lock); 3551 spin_lock_init(&trans_pcie->reg_lock); 3552 spin_lock_init(&trans_pcie->alloc_page_lock); 3553 mutex_init(&trans_pcie->mutex); 3554 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3555 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3556 3557 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3558 WQ_HIGHPRI | WQ_UNBOUND, 1); 3559 if (!trans_pcie->rba.alloc_wq) { 3560 ret = -ENOMEM; 3561 goto out_free_trans; 3562 } 3563 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3564 3565 trans_pcie->debug_rfkill = -1; 3566 3567 if (!cfg_trans->base_params->pcie_l1_allowed) { 3568 /* 3569 * W/A - seems to solve weird behavior. We need to remove this 3570 * if we don't want to stay in L1 all the time. This wastes a 3571 * lot of power. 3572 */ 3573 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3574 PCIE_LINK_STATE_L1 | 3575 PCIE_LINK_STATE_CLKPM); 3576 } 3577 3578 trans_pcie->def_rx_queue = 0; 3579 3580 pci_set_master(pdev); 3581 3582 addr_size = trans->txqs.tfd.addr_size; 3583 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3584 if (ret) { 3585 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3586 /* both attempts failed: */ 3587 if (ret) { 3588 dev_err(&pdev->dev, "No suitable DMA available\n"); 3589 goto out_no_pci; 3590 } 3591 } 3592 3593 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3594 if (ret) { 3595 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3596 goto out_no_pci; 3597 } 3598 3599 table = pcim_iomap_table(pdev); 3600 if (!table) { 3601 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3602 ret = -ENOMEM; 3603 goto out_no_pci; 3604 } 3605 3606 trans_pcie->hw_base = table[0]; 3607 if (!trans_pcie->hw_base) { 3608 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3609 ret = -ENODEV; 3610 goto out_no_pci; 3611 } 3612 3613 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3614 * PCI Tx retries from interfering with C3 CPU state */ 3615 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3616 3617 trans_pcie->pci_dev = pdev; 3618 iwl_disable_interrupts(trans); 3619 3620 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3621 if (trans->hw_rev == 0xffffffff) { 3622 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3623 ret = -EIO; 3624 goto out_no_pci; 3625 } 3626 3627 /* 3628 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3629 * changed, and now the revision step also includes bit 0-1 (no more 3630 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3631 * in the old format. 3632 */ 3633 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3634 trans->hw_rev_step = trans->hw_rev & 0xF; 3635 else 3636 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3637 3638 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3639 3640 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3641 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3642 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3643 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3644 3645 init_waitqueue_head(&trans_pcie->sx_waitq); 3646 3647 3648 if (trans_pcie->msix_enabled) { 3649 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3650 if (ret) 3651 goto out_no_pci; 3652 } else { 3653 ret = iwl_pcie_alloc_ict(trans); 3654 if (ret) 3655 goto out_no_pci; 3656 3657 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3658 iwl_pcie_isr, 3659 iwl_pcie_irq_handler, 3660 IRQF_SHARED, DRV_NAME, trans); 3661 if (ret) { 3662 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3663 goto out_free_ict; 3664 } 3665 } 3666 3667 #ifdef CONFIG_IWLWIFI_DEBUGFS 3668 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3669 mutex_init(&trans_pcie->fw_mon_data.mutex); 3670 #endif 3671 3672 iwl_dbg_tlv_init(trans); 3673 3674 return trans; 3675 3676 out_free_ict: 3677 iwl_pcie_free_ict(trans); 3678 out_no_pci: 3679 destroy_workqueue(trans_pcie->rba.alloc_wq); 3680 out_free_trans: 3681 iwl_trans_free(trans); 3682 return ERR_PTR(ret); 3683 } 3684