1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 Intel Deutschland GmbH 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24 * USA 25 * 26 * The full GNU General Public License is included in this distribution 27 * in the file called COPYING. 28 * 29 * Contact Information: 30 * Intel Linux Wireless <linuxwifi@intel.com> 31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32 * 33 * BSD LICENSE 34 * 35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37 * Copyright(c) 2016 Intel Deutschland GmbH 38 * All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 44 * * Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * * Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in 48 * the documentation and/or other materials provided with the 49 * distribution. 50 * * Neither the name Intel Corporation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 * 66 *****************************************************************************/ 67 #include <linux/pci.h> 68 #include <linux/pci-aspm.h> 69 #include <linux/interrupt.h> 70 #include <linux/debugfs.h> 71 #include <linux/sched.h> 72 #include <linux/bitops.h> 73 #include <linux/gfp.h> 74 #include <linux/vmalloc.h> 75 #include <linux/pm_runtime.h> 76 77 #include "iwl-drv.h" 78 #include "iwl-trans.h" 79 #include "iwl-csr.h" 80 #include "iwl-prph.h" 81 #include "iwl-scd.h" 82 #include "iwl-agn-hw.h" 83 #include "iwl-fw-error-dump.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92 { 93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94 95 if (!trans_pcie->fw_mon_page) 96 return; 97 98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100 __free_pages(trans_pcie->fw_mon_page, 101 get_order(trans_pcie->fw_mon_size)); 102 trans_pcie->fw_mon_page = NULL; 103 trans_pcie->fw_mon_phys = 0; 104 trans_pcie->fw_mon_size = 0; 105 } 106 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108 { 109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110 struct page *page = NULL; 111 dma_addr_t phys; 112 u32 size = 0; 113 u8 power; 114 115 if (!max_power) { 116 /* default max_power is maximum */ 117 max_power = 26; 118 } else { 119 max_power += 11; 120 } 121 122 if (WARN(max_power > 26, 123 "External buffer size for monitor is too big %d, check the FW TLV\n", 124 max_power)) 125 return; 126 127 if (trans_pcie->fw_mon_page) { 128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129 trans_pcie->fw_mon_size, 130 DMA_FROM_DEVICE); 131 return; 132 } 133 134 phys = 0; 135 for (power = max_power; power >= 11; power--) { 136 int order; 137 138 size = BIT(power); 139 order = get_order(size); 140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141 order); 142 if (!page) 143 continue; 144 145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146 DMA_FROM_DEVICE); 147 if (dma_mapping_error(trans->dev, phys)) { 148 __free_pages(page, order); 149 page = NULL; 150 continue; 151 } 152 IWL_INFO(trans, 153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154 size, order); 155 break; 156 } 157 158 if (WARN_ON_ONCE(!page)) 159 return; 160 161 if (power != max_power) 162 IWL_ERR(trans, 163 "Sorry - debug buffer is only %luK while you requested %luK\n", 164 (unsigned long)BIT(power - 10), 165 (unsigned long)BIT(max_power - 10)); 166 167 trans_pcie->fw_mon_page = page; 168 trans_pcie->fw_mon_phys = phys; 169 trans_pcie->fw_mon_size = size; 170 } 171 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173 { 174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175 ((reg & 0x0000ffff) | (2 << 28))); 176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177 } 178 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180 { 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183 ((reg & 0x0000ffff) | (3 << 28))); 184 } 185 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187 { 188 if (trans->cfg->apmg_not_supported) 189 return; 190 191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194 ~APMG_PS_CTRL_MSK_PWR_SRC); 195 else 196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198 ~APMG_PS_CTRL_MSK_PWR_SRC); 199 } 200 201 /* PCI registers */ 202 #define PCI_CFG_RETRY_TIMEOUT 0x041 203 204 static void iwl_pcie_apm_config(struct iwl_trans *trans) 205 { 206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207 u16 lctl; 208 u16 cap; 209 210 /* 211 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212 * Check if BIOS (or OS) enabled L1-ASPM on this device. 213 * If so (likely), disable L0S, so device moves directly L0->L1; 214 * costs negligible amount of power savings. 215 * If not (unlikely), enable L0S, so there is at least some 216 * power savings, even without L1. 217 */ 218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221 else 222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224 225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229 trans->ltr_enabled ? "En" : "Dis"); 230 } 231 232 /* 233 * Start up NIC's basic functionality after it has been reset 234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235 * NOTE: This does not load uCode nor start the embedded processor 236 */ 237 static int iwl_pcie_apm_init(struct iwl_trans *trans) 238 { 239 int ret = 0; 240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 241 242 /* 243 * Use "set_bit" below rather than "write", to preserve any hardware 244 * bits already set by default after reset. 245 */ 246 247 /* Disable L0S exit timer (platform NMI Work/Around) */ 248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 251 252 /* 253 * Disable L0s without affecting L1; 254 * don't wait for ICH L0s (ICH bug W/A) 255 */ 256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 258 259 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 261 262 /* 263 * Enable HAP INTA (interrupt from management bus) to 264 * wake device's PCI Express link L1a -> L0s 265 */ 266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 268 269 iwl_pcie_apm_config(trans); 270 271 /* Configure analog phase-lock-loop before activating to D0A */ 272 if (trans->cfg->base_params->pll_cfg) 273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 274 275 /* 276 * Set "initialization complete" bit to move adapter from 277 * D0U* --> D0A* (powered-up active) state. 278 */ 279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 280 281 /* 282 * Wait for clock stabilization; once stabilized, access to 283 * device-internal resources is supported, e.g. iwl_write_prph() 284 * and accesses to uCode SRAM. 285 */ 286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 289 if (ret < 0) { 290 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 291 goto out; 292 } 293 294 if (trans->cfg->host_interrupt_operation_mode) { 295 /* 296 * This is a bit of an abuse - This is needed for 7260 / 3160 297 * only check host_interrupt_operation_mode even if this is 298 * not related to host_interrupt_operation_mode. 299 * 300 * Enable the oscillator to count wake up time for L1 exit. This 301 * consumes slightly more power (100uA) - but allows to be sure 302 * that we wake up from L1 on time. 303 * 304 * This looks weird: read twice the same register, discard the 305 * value, set a bit, and yet again, read that same register 306 * just to discard the value. But that's the way the hardware 307 * seems to like it. 308 */ 309 iwl_read_prph(trans, OSC_CLK); 310 iwl_read_prph(trans, OSC_CLK); 311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 312 iwl_read_prph(trans, OSC_CLK); 313 iwl_read_prph(trans, OSC_CLK); 314 } 315 316 /* 317 * Enable DMA clock and wait for it to stabilize. 318 * 319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 320 * bits do not disable clocks. This preserves any hardware 321 * bits already set by default in "CLK_CTRL_REG" after reset. 322 */ 323 if (!trans->cfg->apmg_not_supported) { 324 iwl_write_prph(trans, APMG_CLK_EN_REG, 325 APMG_CLK_VAL_DMA_CLK_RQT); 326 udelay(20); 327 328 /* Disable L1-Active */ 329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 331 332 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 334 APMG_RTC_INT_STT_RFKILL); 335 } 336 337 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 338 339 out: 340 return ret; 341 } 342 343 /* 344 * Enable LP XTAL to avoid HW bug where device may consume much power if 345 * FW is not loaded after device reset. LP XTAL is disabled by default 346 * after device HW reset. Do it only if XTAL is fed by internal source. 347 * Configure device's "persistence" mode to avoid resetting XTAL again when 348 * SHRD_HW_RST occurs in S3. 349 */ 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351 { 352 int ret; 353 u32 apmg_gp1_reg; 354 u32 apmg_xtal_cfg_reg; 355 u32 dl_cfg_reg; 356 357 /* Force XTAL ON */ 358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360 361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 363 usleep_range(1000, 2000); 364 365 /* 366 * Set "initialization complete" bit to move adapter from 367 * D0U* --> D0A* (powered-up active) state. 368 */ 369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 370 371 /* 372 * Wait for clock stabilization; once stabilized, access to 373 * device-internal resources is possible. 374 */ 375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378 25000); 379 if (WARN_ON(ret < 0)) { 380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 381 /* Release XTAL ON request */ 382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384 return; 385 } 386 387 /* 388 * Clear "disable persistence" to avoid LP XTAL resetting when 389 * SHRD_HW_RST is applied in S3. 390 */ 391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 392 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 393 394 /* 395 * Force APMG XTAL to be active to prevent its disabling by HW 396 * caused by APMG idle state. 397 */ 398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 399 SHR_APMG_XTAL_CFG_REG); 400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 401 apmg_xtal_cfg_reg | 402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 403 404 /* 405 * Reset entire device again - do controller reset (results in 406 * SHRD_HW_RST). Turn MAC off before proceeding. 407 */ 408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 409 usleep_range(1000, 2000); 410 411 /* Enable LP XTAL by indirect access through CSR */ 412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 414 SHR_APMG_GP1_WF_XTAL_LP_EN | 415 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 416 417 /* Clear delay line clock power up */ 418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 421 422 /* 423 * Enable persistence mode to avoid LP XTAL resetting when 424 * SHRD_HW_RST is applied in S3. 425 */ 426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 428 429 /* 430 * Clear "initialization complete" bit to move adapter from 431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 432 */ 433 iwl_clear_bit(trans, CSR_GP_CNTRL, 434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 435 436 /* Activates XTAL resources monitor */ 437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 438 CSR_MONITOR_XTAL_RESOURCES); 439 440 /* Release XTAL ON request */ 441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 443 udelay(10); 444 445 /* Release APMG XTAL */ 446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 447 apmg_xtal_cfg_reg & 448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 449 } 450 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 452 { 453 int ret = 0; 454 455 /* stop device's busmaster DMA activity */ 456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 457 458 ret = iwl_poll_bit(trans, CSR_RESET, 459 CSR_RESET_REG_FLAG_MASTER_DISABLED, 460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 461 if (ret < 0) 462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 463 464 IWL_DEBUG_INFO(trans, "stop master\n"); 465 466 return ret; 467 } 468 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 470 { 471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 472 473 if (op_mode_leave) { 474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 475 iwl_pcie_apm_init(trans); 476 477 /* inform ME that we are leaving */ 478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 480 APMG_PCIDEV_STT_VAL_WAKE_ME); 481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 483 CSR_RESET_LINK_PWR_MGMT_DISABLED); 484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485 CSR_HW_IF_CONFIG_REG_PREPARE | 486 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 487 mdelay(1); 488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 489 CSR_RESET_LINK_PWR_MGMT_DISABLED); 490 } 491 mdelay(5); 492 } 493 494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 495 496 /* Stop device's DMA activity */ 497 iwl_pcie_apm_stop_master(trans); 498 499 if (trans->cfg->lp_xtal_workaround) { 500 iwl_pcie_apm_lp_xtal_enable(trans); 501 return; 502 } 503 504 /* Reset the entire device */ 505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 506 usleep_range(1000, 2000); 507 508 /* 509 * Clear "initialization complete" bit to move adapter from 510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 511 */ 512 iwl_clear_bit(trans, CSR_GP_CNTRL, 513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 514 } 515 516 static int iwl_pcie_nic_init(struct iwl_trans *trans) 517 { 518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 519 520 /* nic_init */ 521 spin_lock(&trans_pcie->irq_lock); 522 iwl_pcie_apm_init(trans); 523 524 spin_unlock(&trans_pcie->irq_lock); 525 526 iwl_pcie_set_pwr(trans, false); 527 528 iwl_op_mode_nic_config(trans->op_mode); 529 530 /* Allocate the RX queue, or reset if it is already allocated */ 531 iwl_pcie_rx_init(trans); 532 533 /* Allocate or reset and init all Tx and Command queues */ 534 if (iwl_pcie_tx_init(trans)) 535 return -ENOMEM; 536 537 if (trans->cfg->base_params->shadow_reg_enable) { 538 /* enable shadow regs in HW */ 539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 541 } 542 543 return 0; 544 } 545 546 #define HW_READY_TIMEOUT (50) 547 548 /* Note: returns poll_bit return value, which is >= 0 if success */ 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 550 { 551 int ret; 552 553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 555 556 /* See if we got it */ 557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560 HW_READY_TIMEOUT); 561 562 if (ret >= 0) 563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 564 565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 566 return ret; 567 } 568 569 /* Note: returns standard 0/-ERROR code */ 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 571 { 572 int ret; 573 int t = 0; 574 int iter; 575 576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 577 578 ret = iwl_pcie_set_hw_ready(trans); 579 /* If the card is ready, exit 0 */ 580 if (ret >= 0) 581 return 0; 582 583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 584 CSR_RESET_LINK_PWR_MGMT_DISABLED); 585 usleep_range(1000, 2000); 586 587 for (iter = 0; iter < 10; iter++) { 588 /* If HW is not ready, prepare the conditions to check again */ 589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 590 CSR_HW_IF_CONFIG_REG_PREPARE); 591 592 do { 593 ret = iwl_pcie_set_hw_ready(trans); 594 if (ret >= 0) 595 return 0; 596 597 usleep_range(200, 1000); 598 t += 200; 599 } while (t < 150000); 600 msleep(25); 601 } 602 603 IWL_ERR(trans, "Couldn't prepare the card\n"); 604 605 return ret; 606 } 607 608 /* 609 * ucode 610 */ 611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 612 u32 dst_addr, dma_addr_t phy_addr, 613 u32 byte_cnt) 614 { 615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 617 618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 619 dst_addr); 620 621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 623 624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 625 (iwl_get_dma_hi_addr(phy_addr) 626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 627 628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 632 633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 637 } 638 639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans, 640 u32 dst_addr, dma_addr_t phy_addr, 641 u32 byte_cnt) 642 { 643 /* Stop DMA channel */ 644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0); 645 646 /* Configure SRAM address */ 647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR, 648 dst_addr); 649 650 /* Configure DRAM address - 64 bit */ 651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr); 652 653 /* Configure byte count to transfer */ 654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt); 655 656 /* Enable the DRAM2SRAM to start */ 657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP | 658 TFH_SRV_DMA_TO_DRIVER | 659 TFH_SRV_DMA_START); 660 } 661 662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 663 u32 dst_addr, dma_addr_t phy_addr, 664 u32 byte_cnt) 665 { 666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 667 unsigned long flags; 668 int ret; 669 670 trans_pcie->ucode_write_complete = false; 671 672 if (!iwl_trans_grab_nic_access(trans, &flags)) 673 return -EIO; 674 675 if (trans->cfg->use_tfh) 676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr, 677 byte_cnt); 678 else 679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 680 byte_cnt); 681 iwl_trans_release_nic_access(trans, &flags); 682 683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 684 trans_pcie->ucode_write_complete, 5 * HZ); 685 if (!ret) { 686 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 687 return -ETIMEDOUT; 688 } 689 690 return 0; 691 } 692 693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 694 const struct fw_desc *section) 695 { 696 u8 *v_addr; 697 dma_addr_t p_addr; 698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 699 int ret = 0; 700 701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 702 section_num); 703 704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 705 GFP_KERNEL | __GFP_NOWARN); 706 if (!v_addr) { 707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 708 chunk_sz = PAGE_SIZE; 709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 710 &p_addr, GFP_KERNEL); 711 if (!v_addr) 712 return -ENOMEM; 713 } 714 715 for (offset = 0; offset < section->len; offset += chunk_sz) { 716 u32 copy_size, dst_addr; 717 bool extended_addr = false; 718 719 copy_size = min_t(u32, chunk_sz, section->len - offset); 720 dst_addr = section->offset + offset; 721 722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 723 dst_addr <= IWL_FW_MEM_EXTENDED_END) 724 extended_addr = true; 725 726 if (extended_addr) 727 iwl_set_bits_prph(trans, LMPM_CHICK, 728 LMPM_CHICK_EXTENDED_ADDR_SPACE); 729 730 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 732 copy_size); 733 734 if (extended_addr) 735 iwl_clear_bits_prph(trans, LMPM_CHICK, 736 LMPM_CHICK_EXTENDED_ADDR_SPACE); 737 738 if (ret) { 739 IWL_ERR(trans, 740 "Could not load the [%d] uCode section\n", 741 section_num); 742 break; 743 } 744 } 745 746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 747 return ret; 748 } 749 750 /* 751 * Driver Takes the ownership on secure machine before FW load 752 * and prevent race with the BT load. 753 * W/A for ROM bug. (should be remove in the next Si step) 754 */ 755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 756 { 757 u32 val, loop = 1000; 758 759 /* 760 * Check the RSA semaphore is accessible. 761 * If the HW isn't locked and the rsa semaphore isn't accessible, 762 * we are in trouble. 763 */ 764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 765 if (val & (BIT(1) | BIT(17))) { 766 IWL_DEBUG_INFO(trans, 767 "can't access the RSA semaphore it is write protected\n"); 768 return 0; 769 } 770 771 /* take ownership on the AUX IF */ 772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 774 775 do { 776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 778 if (val == 0x1) { 779 iwl_write_prph(trans, RSA_ENABLE, 0); 780 return 0; 781 } 782 783 udelay(10); 784 loop--; 785 } while (loop > 0); 786 787 IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 788 return -EIO; 789 } 790 791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 792 const struct fw_img *image, 793 int cpu, 794 int *first_ucode_section) 795 { 796 int shift_param; 797 int i, ret = 0, sec_num = 0x1; 798 u32 val, last_read_idx = 0; 799 800 if (cpu == 1) { 801 shift_param = 0; 802 *first_ucode_section = 0; 803 } else { 804 shift_param = 16; 805 (*first_ucode_section)++; 806 } 807 808 for (i = *first_ucode_section; i < image->num_sec; i++) { 809 last_read_idx = i; 810 811 /* 812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 813 * CPU1 to CPU2. 814 * PAGING_SEPARATOR_SECTION delimiter - separate between 815 * CPU2 non paged to CPU2 paging sec. 816 */ 817 if (!image->sec[i].data || 818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 820 IWL_DEBUG_FW(trans, 821 "Break since Data not valid or Empty section, sec = %d\n", 822 i); 823 break; 824 } 825 826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 827 if (ret) 828 return ret; 829 830 /* Notify ucode of loaded section number and status */ 831 if (trans->cfg->use_tfh) { 832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS); 833 val = val | (sec_num << shift_param); 834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val); 835 } else { 836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 837 val = val | (sec_num << shift_param); 838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 839 } 840 sec_num = (sec_num << 1) | 0x1; 841 } 842 843 *first_ucode_section = last_read_idx; 844 845 iwl_enable_interrupts(trans); 846 847 if (trans->cfg->use_tfh) { 848 if (cpu == 1) 849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 850 0xFFFF); 851 else 852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 853 0xFFFFFFFF); 854 } else { 855 if (cpu == 1) 856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 857 0xFFFF); 858 else 859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 860 0xFFFFFFFF); 861 } 862 863 return 0; 864 } 865 866 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 867 const struct fw_img *image, 868 int cpu, 869 int *first_ucode_section) 870 { 871 int i, ret = 0; 872 u32 last_read_idx = 0; 873 874 if (cpu == 1) 875 *first_ucode_section = 0; 876 else 877 (*first_ucode_section)++; 878 879 for (i = *first_ucode_section; i < image->num_sec; i++) { 880 last_read_idx = i; 881 882 /* 883 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 884 * CPU1 to CPU2. 885 * PAGING_SEPARATOR_SECTION delimiter - separate between 886 * CPU2 non paged to CPU2 paging sec. 887 */ 888 if (!image->sec[i].data || 889 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 890 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 891 IWL_DEBUG_FW(trans, 892 "Break since Data not valid or Empty section, sec = %d\n", 893 i); 894 break; 895 } 896 897 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 898 if (ret) 899 return ret; 900 } 901 902 *first_ucode_section = last_read_idx; 903 904 return 0; 905 } 906 907 static void iwl_pcie_apply_destination(struct iwl_trans *trans) 908 { 909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 910 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 911 int i; 912 913 if (dest->version) 914 IWL_ERR(trans, 915 "DBG DEST version is %d - expect issues\n", 916 dest->version); 917 918 IWL_INFO(trans, "Applying debug destination %s\n", 919 get_fw_dbg_mode_string(dest->monitor_mode)); 920 921 if (dest->monitor_mode == EXTERNAL_MODE) 922 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 923 else 924 IWL_WARN(trans, "PCI should have external buffer debug\n"); 925 926 for (i = 0; i < trans->dbg_dest_reg_num; i++) { 927 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 928 u32 val = le32_to_cpu(dest->reg_ops[i].val); 929 930 switch (dest->reg_ops[i].op) { 931 case CSR_ASSIGN: 932 iwl_write32(trans, addr, val); 933 break; 934 case CSR_SETBIT: 935 iwl_set_bit(trans, addr, BIT(val)); 936 break; 937 case CSR_CLEARBIT: 938 iwl_clear_bit(trans, addr, BIT(val)); 939 break; 940 case PRPH_ASSIGN: 941 iwl_write_prph(trans, addr, val); 942 break; 943 case PRPH_SETBIT: 944 iwl_set_bits_prph(trans, addr, BIT(val)); 945 break; 946 case PRPH_CLEARBIT: 947 iwl_clear_bits_prph(trans, addr, BIT(val)); 948 break; 949 case PRPH_BLOCKBIT: 950 if (iwl_read_prph(trans, addr) & BIT(val)) { 951 IWL_ERR(trans, 952 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 953 val, addr); 954 goto monitor; 955 } 956 break; 957 default: 958 IWL_ERR(trans, "FW debug - unknown OP %d\n", 959 dest->reg_ops[i].op); 960 break; 961 } 962 } 963 964 monitor: 965 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 966 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 967 trans_pcie->fw_mon_phys >> dest->base_shift); 968 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 970 (trans_pcie->fw_mon_phys + 971 trans_pcie->fw_mon_size - 256) >> 972 dest->end_shift); 973 else 974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 975 (trans_pcie->fw_mon_phys + 976 trans_pcie->fw_mon_size) >> 977 dest->end_shift); 978 } 979 } 980 981 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 982 const struct fw_img *image) 983 { 984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 985 int ret = 0; 986 int first_ucode_section; 987 988 IWL_DEBUG_FW(trans, "working with %s CPU\n", 989 image->is_dual_cpus ? "Dual" : "Single"); 990 991 /* load to FW the binary non secured sections of CPU1 */ 992 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 993 if (ret) 994 return ret; 995 996 if (image->is_dual_cpus) { 997 /* set CPU2 header address */ 998 iwl_write_prph(trans, 999 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1000 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1001 1002 /* load to FW the binary sections of CPU2 */ 1003 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1004 &first_ucode_section); 1005 if (ret) 1006 return ret; 1007 } 1008 1009 /* supported for 7000 only for the moment */ 1010 if (iwlwifi_mod_params.fw_monitor && 1011 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1012 iwl_pcie_alloc_fw_monitor(trans, 0); 1013 1014 if (trans_pcie->fw_mon_size) { 1015 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1016 trans_pcie->fw_mon_phys >> 4); 1017 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1018 (trans_pcie->fw_mon_phys + 1019 trans_pcie->fw_mon_size) >> 4); 1020 } 1021 } else if (trans->dbg_dest_tlv) { 1022 iwl_pcie_apply_destination(trans); 1023 } 1024 1025 iwl_enable_interrupts(trans); 1026 1027 /* release CPU reset */ 1028 iwl_write32(trans, CSR_RESET, 0); 1029 1030 return 0; 1031 } 1032 1033 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1034 const struct fw_img *image) 1035 { 1036 int ret = 0; 1037 int first_ucode_section; 1038 1039 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1040 image->is_dual_cpus ? "Dual" : "Single"); 1041 1042 if (trans->dbg_dest_tlv) 1043 iwl_pcie_apply_destination(trans); 1044 1045 /* TODO: remove in the next Si step */ 1046 ret = iwl_pcie_rsa_race_bug_wa(trans); 1047 if (ret) 1048 return ret; 1049 1050 /* configure the ucode to be ready to get the secured image */ 1051 /* release CPU reset */ 1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1053 1054 /* load to FW the binary Secured sections of CPU1 */ 1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1056 &first_ucode_section); 1057 if (ret) 1058 return ret; 1059 1060 /* load to FW the binary sections of CPU2 */ 1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1062 &first_ucode_section); 1063 } 1064 1065 static bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans) 1066 { 1067 bool hw_rfkill = iwl_is_rfkill_set(trans); 1068 1069 if (hw_rfkill) 1070 set_bit(STATUS_RFKILL, &trans->status); 1071 else 1072 clear_bit(STATUS_RFKILL, &trans->status); 1073 1074 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1075 1076 return hw_rfkill; 1077 } 1078 1079 struct iwl_causes_list { 1080 u32 cause_num; 1081 u32 mask_reg; 1082 u8 addr; 1083 }; 1084 1085 static struct iwl_causes_list causes_list[] = { 1086 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1087 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1088 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1089 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1090 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1091 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1092 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1093 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1094 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1095 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1096 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1097 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1098 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1099 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1100 }; 1101 1102 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1103 { 1104 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1105 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1106 int i; 1107 1108 /* 1109 * Access all non RX causes and map them to the default irq. 1110 * In case we are missing at least one interrupt vector, 1111 * the first interrupt vector will serve non-RX and FBQ causes. 1112 */ 1113 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1114 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 1115 iwl_clear_bit(trans, causes_list[i].mask_reg, 1116 causes_list[i].cause_num); 1117 } 1118 } 1119 1120 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1121 { 1122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1123 u32 offset = 1124 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1125 u32 val, idx; 1126 1127 /* 1128 * The first RX queue - fallback queue, which is designated for 1129 * management frame, command responses etc, is always mapped to the 1130 * first interrupt vector. The other RX queues are mapped to 1131 * the other (N - 2) interrupt vectors. 1132 */ 1133 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1134 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1135 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1136 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1137 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1138 } 1139 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1140 1141 val = MSIX_FH_INT_CAUSES_Q(0); 1142 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1143 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1144 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1145 1146 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1147 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1148 } 1149 1150 static void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1151 { 1152 struct iwl_trans *trans = trans_pcie->trans; 1153 1154 if (!trans_pcie->msix_enabled) { 1155 if (trans->cfg->mq_rx_supported && 1156 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1157 iwl_write_prph(trans, UREG_CHICK, 1158 UREG_CHICK_MSI_ENABLE); 1159 return; 1160 } 1161 /* 1162 * The IVAR table needs to be configured again after reset, 1163 * but if the device is disabled, we can't write to 1164 * prph. 1165 */ 1166 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1167 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1168 1169 /* 1170 * Each cause from the causes list above and the RX causes is 1171 * represented as a byte in the IVAR table. The first nibble 1172 * represents the bound interrupt vector of the cause, the second 1173 * represents no auto clear for this cause. This will be set if its 1174 * interrupt vector is bound to serve other causes. 1175 */ 1176 iwl_pcie_map_rx_causes(trans); 1177 1178 iwl_pcie_map_non_rx_causes(trans); 1179 } 1180 1181 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1182 { 1183 struct iwl_trans *trans = trans_pcie->trans; 1184 1185 iwl_pcie_conf_msix_hw(trans_pcie); 1186 1187 if (!trans_pcie->msix_enabled) 1188 return; 1189 1190 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1191 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1192 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1193 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1194 } 1195 1196 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1197 { 1198 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1199 bool hw_rfkill, was_hw_rfkill; 1200 1201 lockdep_assert_held(&trans_pcie->mutex); 1202 1203 if (trans_pcie->is_down) 1204 return; 1205 1206 trans_pcie->is_down = true; 1207 1208 was_hw_rfkill = iwl_is_rfkill_set(trans); 1209 1210 /* tell the device to stop sending interrupts */ 1211 iwl_disable_interrupts(trans); 1212 1213 /* device going down, Stop using ICT table */ 1214 iwl_pcie_disable_ict(trans); 1215 1216 /* 1217 * If a HW restart happens during firmware loading, 1218 * then the firmware loading might call this function 1219 * and later it might be called again due to the 1220 * restart. So don't process again if the device is 1221 * already dead. 1222 */ 1223 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1224 IWL_DEBUG_INFO(trans, 1225 "DEVICE_ENABLED bit was set and is now cleared\n"); 1226 iwl_pcie_tx_stop(trans); 1227 iwl_pcie_rx_stop(trans); 1228 1229 /* Power-down device's busmaster DMA clocks */ 1230 if (!trans->cfg->apmg_not_supported) { 1231 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1232 APMG_CLK_VAL_DMA_CLK_RQT); 1233 udelay(5); 1234 } 1235 } 1236 1237 /* Make sure (redundant) we've released our request to stay awake */ 1238 iwl_clear_bit(trans, CSR_GP_CNTRL, 1239 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1240 1241 /* Stop the device, and put it in low power state */ 1242 iwl_pcie_apm_stop(trans, false); 1243 1244 /* stop and reset the on-board processor */ 1245 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1246 usleep_range(1000, 2000); 1247 1248 /* 1249 * Upon stop, the IVAR table gets erased, so msi-x won't 1250 * work. This causes a bug in RF-KILL flows, since the interrupt 1251 * that enables radio won't fire on the correct irq, and the 1252 * driver won't be able to handle the interrupt. 1253 * Configure the IVAR table again after reset. 1254 */ 1255 iwl_pcie_conf_msix_hw(trans_pcie); 1256 1257 /* 1258 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1259 * This is a bug in certain verions of the hardware. 1260 * Certain devices also keep sending HW RF kill interrupt all 1261 * the time, unless the interrupt is ACKed even if the interrupt 1262 * should be masked. Re-ACK all the interrupts here. 1263 */ 1264 iwl_disable_interrupts(trans); 1265 1266 /* clear all status bits */ 1267 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1268 clear_bit(STATUS_INT_ENABLED, &trans->status); 1269 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1270 clear_bit(STATUS_RFKILL, &trans->status); 1271 1272 /* 1273 * Even if we stop the HW, we still want the RF kill 1274 * interrupt 1275 */ 1276 iwl_enable_rfkill_int(trans); 1277 1278 /* 1279 * Check again since the RF kill state may have changed while 1280 * all the interrupts were disabled, in this case we couldn't 1281 * receive the RF kill interrupt and update the state in the 1282 * op_mode. 1283 * Don't call the op_mode if the rkfill state hasn't changed. 1284 * This allows the op_mode to call stop_device from the rfkill 1285 * notification without endless recursion. Under very rare 1286 * circumstances, we might have a small recursion if the rfkill 1287 * state changed exactly now while we were called from stop_device. 1288 * This is very unlikely but can happen and is supported. 1289 */ 1290 hw_rfkill = iwl_is_rfkill_set(trans); 1291 if (hw_rfkill) 1292 set_bit(STATUS_RFKILL, &trans->status); 1293 else 1294 clear_bit(STATUS_RFKILL, &trans->status); 1295 if (hw_rfkill != was_hw_rfkill) 1296 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1297 1298 /* re-take ownership to prevent other users from stealing the device */ 1299 iwl_pcie_prepare_card_hw(trans); 1300 } 1301 1302 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1303 { 1304 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1305 1306 if (trans_pcie->msix_enabled) { 1307 int i; 1308 1309 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1310 synchronize_irq(trans_pcie->msix_entries[i].vector); 1311 } else { 1312 synchronize_irq(trans_pcie->pci_dev->irq); 1313 } 1314 } 1315 1316 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1317 const struct fw_img *fw, bool run_in_rfkill) 1318 { 1319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1320 bool hw_rfkill; 1321 int ret; 1322 1323 /* This may fail if AMT took ownership of the device */ 1324 if (iwl_pcie_prepare_card_hw(trans)) { 1325 IWL_WARN(trans, "Exit HW not ready\n"); 1326 ret = -EIO; 1327 goto out; 1328 } 1329 1330 iwl_enable_rfkill_int(trans); 1331 1332 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1333 1334 /* 1335 * We enabled the RF-Kill interrupt and the handler may very 1336 * well be running. Disable the interrupts to make sure no other 1337 * interrupt can be fired. 1338 */ 1339 iwl_disable_interrupts(trans); 1340 1341 /* Make sure it finished running */ 1342 iwl_pcie_synchronize_irqs(trans); 1343 1344 mutex_lock(&trans_pcie->mutex); 1345 1346 /* If platform's RF_KILL switch is NOT set to KILL */ 1347 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1348 if (hw_rfkill && !run_in_rfkill) { 1349 ret = -ERFKILL; 1350 goto out; 1351 } 1352 1353 /* Someone called stop_device, don't try to start_fw */ 1354 if (trans_pcie->is_down) { 1355 IWL_WARN(trans, 1356 "Can't start_fw since the HW hasn't been started\n"); 1357 ret = -EIO; 1358 goto out; 1359 } 1360 1361 /* make sure rfkill handshake bits are cleared */ 1362 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1363 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1364 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1365 1366 /* clear (again), then enable host interrupts */ 1367 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1368 1369 ret = iwl_pcie_nic_init(trans); 1370 if (ret) { 1371 IWL_ERR(trans, "Unable to init nic\n"); 1372 goto out; 1373 } 1374 1375 /* 1376 * Now, we load the firmware and don't want to be interrupted, even 1377 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1378 * FH_TX interrupt which is needed to load the firmware). If the 1379 * RF-Kill switch is toggled, we will find out after having loaded 1380 * the firmware and return the proper value to the caller. 1381 */ 1382 iwl_enable_fw_load_int(trans); 1383 1384 /* really make sure rfkill handshake bits are cleared */ 1385 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1386 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1387 1388 /* Load the given image to the HW */ 1389 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1390 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1391 else 1392 ret = iwl_pcie_load_given_ucode(trans, fw); 1393 1394 /* re-check RF-Kill state since we may have missed the interrupt */ 1395 hw_rfkill = iwl_trans_check_hw_rf_kill(trans); 1396 if (hw_rfkill && !run_in_rfkill) 1397 ret = -ERFKILL; 1398 1399 out: 1400 mutex_unlock(&trans_pcie->mutex); 1401 return ret; 1402 } 1403 1404 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1405 { 1406 iwl_pcie_reset_ict(trans); 1407 iwl_pcie_tx_start(trans, scd_addr); 1408 } 1409 1410 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1411 { 1412 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1413 1414 mutex_lock(&trans_pcie->mutex); 1415 _iwl_trans_pcie_stop_device(trans, low_power); 1416 mutex_unlock(&trans_pcie->mutex); 1417 } 1418 1419 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1420 { 1421 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1422 IWL_TRANS_GET_PCIE_TRANS(trans); 1423 1424 lockdep_assert_held(&trans_pcie->mutex); 1425 1426 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1427 _iwl_trans_pcie_stop_device(trans, true); 1428 } 1429 1430 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1431 bool reset) 1432 { 1433 if (!reset) { 1434 /* Enable persistence mode to avoid reset */ 1435 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1436 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1437 } 1438 1439 iwl_disable_interrupts(trans); 1440 1441 /* 1442 * in testing mode, the host stays awake and the 1443 * hardware won't be reset (not even partially) 1444 */ 1445 if (test) 1446 return; 1447 1448 iwl_pcie_disable_ict(trans); 1449 1450 iwl_pcie_synchronize_irqs(trans); 1451 1452 iwl_clear_bit(trans, CSR_GP_CNTRL, 1453 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1454 iwl_clear_bit(trans, CSR_GP_CNTRL, 1455 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1456 1457 iwl_pcie_enable_rx_wake(trans, false); 1458 1459 if (reset) { 1460 /* 1461 * reset TX queues -- some of their registers reset during S3 1462 * so if we don't reset everything here the D3 image would try 1463 * to execute some invalid memory upon resume 1464 */ 1465 iwl_trans_pcie_tx_reset(trans); 1466 } 1467 1468 iwl_pcie_set_pwr(trans, true); 1469 } 1470 1471 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1472 enum iwl_d3_status *status, 1473 bool test, bool reset) 1474 { 1475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1476 u32 val; 1477 int ret; 1478 1479 if (test) { 1480 iwl_enable_interrupts(trans); 1481 *status = IWL_D3_STATUS_ALIVE; 1482 return 0; 1483 } 1484 1485 iwl_pcie_enable_rx_wake(trans, true); 1486 1487 /* 1488 * Reconfigure IVAR table in case of MSIX or reset ict table in 1489 * MSI mode since HW reset erased it. 1490 * Also enables interrupts - none will happen as 1491 * the device doesn't know we're waking it up, only when 1492 * the opmode actually tells it after this call. 1493 */ 1494 iwl_pcie_conf_msix_hw(trans_pcie); 1495 if (!trans_pcie->msix_enabled) 1496 iwl_pcie_reset_ict(trans); 1497 iwl_enable_interrupts(trans); 1498 1499 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1500 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1501 1502 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1503 udelay(2); 1504 1505 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1506 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1507 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1508 25000); 1509 if (ret < 0) { 1510 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1511 return ret; 1512 } 1513 1514 iwl_pcie_set_pwr(trans, false); 1515 1516 if (!reset) { 1517 iwl_clear_bit(trans, CSR_GP_CNTRL, 1518 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1519 } else { 1520 iwl_trans_pcie_tx_reset(trans); 1521 1522 ret = iwl_pcie_rx_init(trans); 1523 if (ret) { 1524 IWL_ERR(trans, 1525 "Failed to resume the device (RX reset)\n"); 1526 return ret; 1527 } 1528 } 1529 1530 val = iwl_read32(trans, CSR_RESET); 1531 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1532 *status = IWL_D3_STATUS_RESET; 1533 else 1534 *status = IWL_D3_STATUS_ALIVE; 1535 1536 return 0; 1537 } 1538 1539 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1540 struct iwl_trans *trans) 1541 { 1542 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1543 int max_irqs, num_irqs, i, ret, nr_online_cpus; 1544 u16 pci_cmd; 1545 1546 if (!trans->cfg->mq_rx_supported) 1547 goto enable_msi; 1548 1549 nr_online_cpus = num_online_cpus(); 1550 max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 1551 for (i = 0; i < max_irqs; i++) 1552 trans_pcie->msix_entries[i].entry = i; 1553 1554 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1555 MSIX_MIN_INTERRUPT_VECTORS, 1556 max_irqs); 1557 if (num_irqs < 0) { 1558 IWL_DEBUG_INFO(trans, 1559 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1560 num_irqs); 1561 goto enable_msi; 1562 } 1563 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1564 1565 IWL_DEBUG_INFO(trans, 1566 "MSI-X enabled. %d interrupt vectors were allocated\n", 1567 num_irqs); 1568 1569 /* 1570 * In case the OS provides fewer interrupts than requested, different 1571 * causes will share the same interrupt vector as follows: 1572 * One interrupt less: non rx causes shared with FBQ. 1573 * Two interrupts less: non rx causes shared with FBQ and RSS. 1574 * More than two interrupts: we will use fewer RSS queues. 1575 */ 1576 if (num_irqs <= nr_online_cpus) { 1577 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1578 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1579 IWL_SHARED_IRQ_FIRST_RSS; 1580 } else if (num_irqs == nr_online_cpus + 1) { 1581 trans_pcie->trans->num_rx_queues = num_irqs; 1582 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1583 } else { 1584 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1585 } 1586 1587 trans_pcie->alloc_vecs = num_irqs; 1588 trans_pcie->msix_enabled = true; 1589 return; 1590 1591 enable_msi: 1592 ret = pci_enable_msi(pdev); 1593 if (ret) { 1594 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1595 /* enable rfkill interrupt: hw bug w/a */ 1596 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1597 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1598 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1599 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1600 } 1601 } 1602 } 1603 1604 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1605 { 1606 int iter_rx_q, i, ret, cpu, offset; 1607 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1608 1609 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1610 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1611 offset = 1 + i; 1612 for (; i < iter_rx_q ; i++) { 1613 /* 1614 * Get the cpu prior to the place to search 1615 * (i.e. return will be > i - 1). 1616 */ 1617 cpu = cpumask_next(i - offset, cpu_online_mask); 1618 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1619 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1620 &trans_pcie->affinity_mask[i]); 1621 if (ret) 1622 IWL_ERR(trans_pcie->trans, 1623 "Failed to set affinity mask for IRQ %d\n", 1624 i); 1625 } 1626 } 1627 1628 static const char *queue_name(struct device *dev, 1629 struct iwl_trans_pcie *trans_p, int i) 1630 { 1631 if (trans_p->shared_vec_mask) { 1632 int vec = trans_p->shared_vec_mask & 1633 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1634 1635 if (i == 0) 1636 return DRV_NAME ": shared IRQ"; 1637 1638 return devm_kasprintf(dev, GFP_KERNEL, 1639 DRV_NAME ": queue %d", i + vec); 1640 } 1641 if (i == 0) 1642 return DRV_NAME ": default queue"; 1643 1644 if (i == trans_p->alloc_vecs - 1) 1645 return DRV_NAME ": exception"; 1646 1647 return devm_kasprintf(dev, GFP_KERNEL, 1648 DRV_NAME ": queue %d", i); 1649 } 1650 1651 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1652 struct iwl_trans_pcie *trans_pcie) 1653 { 1654 int i; 1655 1656 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1657 int ret; 1658 struct msix_entry *msix_entry; 1659 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1660 1661 if (!qname) 1662 return -ENOMEM; 1663 1664 msix_entry = &trans_pcie->msix_entries[i]; 1665 ret = devm_request_threaded_irq(&pdev->dev, 1666 msix_entry->vector, 1667 iwl_pcie_msix_isr, 1668 (i == trans_pcie->def_irq) ? 1669 iwl_pcie_irq_msix_handler : 1670 iwl_pcie_irq_rx_msix_handler, 1671 IRQF_SHARED, 1672 qname, 1673 msix_entry); 1674 if (ret) { 1675 IWL_ERR(trans_pcie->trans, 1676 "Error allocating IRQ %d\n", i); 1677 1678 return ret; 1679 } 1680 } 1681 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1682 1683 return 0; 1684 } 1685 1686 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1687 { 1688 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1689 int err; 1690 1691 lockdep_assert_held(&trans_pcie->mutex); 1692 1693 err = iwl_pcie_prepare_card_hw(trans); 1694 if (err) { 1695 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1696 return err; 1697 } 1698 1699 /* Reset the entire device */ 1700 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1701 usleep_range(1000, 2000); 1702 1703 iwl_pcie_apm_init(trans); 1704 1705 iwl_pcie_init_msix(trans_pcie); 1706 1707 /* From now on, the op_mode will be kept updated about RF kill state */ 1708 iwl_enable_rfkill_int(trans); 1709 1710 /* Set is_down to false here so that...*/ 1711 trans_pcie->is_down = false; 1712 1713 /* ...rfkill can call stop_device and set it false if needed */ 1714 iwl_trans_check_hw_rf_kill(trans); 1715 1716 /* Make sure we sync here, because we'll need full access later */ 1717 if (low_power) 1718 pm_runtime_resume(trans->dev); 1719 1720 return 0; 1721 } 1722 1723 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1724 { 1725 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1726 int ret; 1727 1728 mutex_lock(&trans_pcie->mutex); 1729 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1730 mutex_unlock(&trans_pcie->mutex); 1731 1732 return ret; 1733 } 1734 1735 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1736 { 1737 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1738 1739 mutex_lock(&trans_pcie->mutex); 1740 1741 /* disable interrupts - don't enable HW RF kill interrupt */ 1742 iwl_disable_interrupts(trans); 1743 1744 iwl_pcie_apm_stop(trans, true); 1745 1746 iwl_disable_interrupts(trans); 1747 1748 iwl_pcie_disable_ict(trans); 1749 1750 mutex_unlock(&trans_pcie->mutex); 1751 1752 iwl_pcie_synchronize_irqs(trans); 1753 } 1754 1755 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1756 { 1757 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1758 } 1759 1760 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1761 { 1762 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1763 } 1764 1765 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1766 { 1767 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1768 } 1769 1770 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1771 { 1772 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1773 ((reg & 0x000FFFFF) | (3 << 24))); 1774 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1775 } 1776 1777 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1778 u32 val) 1779 { 1780 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1781 ((addr & 0x000FFFFF) | (3 << 24))); 1782 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1783 } 1784 1785 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1786 const struct iwl_trans_config *trans_cfg) 1787 { 1788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1789 1790 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1791 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1792 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1793 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1794 trans_pcie->n_no_reclaim_cmds = 0; 1795 else 1796 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1797 if (trans_pcie->n_no_reclaim_cmds) 1798 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1799 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1800 1801 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1802 trans_pcie->rx_page_order = 1803 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1804 1805 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1806 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1807 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1808 1809 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1810 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1811 1812 trans->command_groups = trans_cfg->command_groups; 1813 trans->command_groups_size = trans_cfg->command_groups_size; 1814 1815 /* Initialize NAPI here - it should be before registering to mac80211 1816 * in the opmode but after the HW struct is allocated. 1817 * As this function may be called again in some corner cases don't 1818 * do anything if NAPI was already initialized. 1819 */ 1820 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1821 init_dummy_netdev(&trans_pcie->napi_dev); 1822 } 1823 1824 void iwl_trans_pcie_free(struct iwl_trans *trans) 1825 { 1826 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1827 int i; 1828 1829 iwl_pcie_synchronize_irqs(trans); 1830 1831 iwl_pcie_tx_free(trans); 1832 iwl_pcie_rx_free(trans); 1833 1834 if (trans_pcie->msix_enabled) { 1835 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1836 irq_set_affinity_hint( 1837 trans_pcie->msix_entries[i].vector, 1838 NULL); 1839 } 1840 1841 trans_pcie->msix_enabled = false; 1842 } else { 1843 iwl_pcie_free_ict(trans); 1844 } 1845 1846 iwl_pcie_free_fw_monitor(trans); 1847 1848 for_each_possible_cpu(i) { 1849 struct iwl_tso_hdr_page *p = 1850 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1851 1852 if (p->page) 1853 __free_page(p->page); 1854 } 1855 1856 free_percpu(trans_pcie->tso_hdr_page); 1857 mutex_destroy(&trans_pcie->mutex); 1858 iwl_trans_free(trans); 1859 } 1860 1861 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1862 { 1863 if (state) 1864 set_bit(STATUS_TPOWER_PMI, &trans->status); 1865 else 1866 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1867 } 1868 1869 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1870 unsigned long *flags) 1871 { 1872 int ret; 1873 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1874 1875 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1876 1877 if (trans_pcie->cmd_hold_nic_awake) 1878 goto out; 1879 1880 /* this bit wakes up the NIC */ 1881 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1882 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1883 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1884 udelay(2); 1885 1886 /* 1887 * These bits say the device is running, and should keep running for 1888 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1889 * but they do not indicate that embedded SRAM is restored yet; 1890 * 3945 and 4965 have volatile SRAM, and must save/restore contents 1891 * to/from host DRAM when sleeping/waking for power-saving. 1892 * Each direction takes approximately 1/4 millisecond; with this 1893 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1894 * series of register accesses are expected (e.g. reading Event Log), 1895 * to keep device from sleeping. 1896 * 1897 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1898 * SRAM is okay/restored. We don't check that here because this call 1899 * is just for hardware register access; but GP1 MAC_SLEEP check is a 1900 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1901 * 1902 * 5000 series and later (including 1000 series) have non-volatile SRAM, 1903 * and do not save/restore SRAM when power cycling. 1904 */ 1905 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1906 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1907 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1908 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1909 if (unlikely(ret < 0)) { 1910 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1911 WARN_ONCE(1, 1912 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 1913 iwl_read32(trans, CSR_GP_CNTRL)); 1914 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1915 return false; 1916 } 1917 1918 out: 1919 /* 1920 * Fool sparse by faking we release the lock - sparse will 1921 * track nic_access anyway. 1922 */ 1923 __release(&trans_pcie->reg_lock); 1924 return true; 1925 } 1926 1927 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1928 unsigned long *flags) 1929 { 1930 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1931 1932 lockdep_assert_held(&trans_pcie->reg_lock); 1933 1934 /* 1935 * Fool sparse by faking we acquiring the lock - sparse will 1936 * track nic_access anyway. 1937 */ 1938 __acquire(&trans_pcie->reg_lock); 1939 1940 if (trans_pcie->cmd_hold_nic_awake) 1941 goto out; 1942 1943 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1944 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1945 /* 1946 * Above we read the CSR_GP_CNTRL register, which will flush 1947 * any previous writes, but we need the write that clears the 1948 * MAC_ACCESS_REQ bit to be performed before any other writes 1949 * scheduled on different CPUs (after we drop reg_lock). 1950 */ 1951 mmiowb(); 1952 out: 1953 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1954 } 1955 1956 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1957 void *buf, int dwords) 1958 { 1959 unsigned long flags; 1960 int offs, ret = 0; 1961 u32 *vals = buf; 1962 1963 if (iwl_trans_grab_nic_access(trans, &flags)) { 1964 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1965 for (offs = 0; offs < dwords; offs++) 1966 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1967 iwl_trans_release_nic_access(trans, &flags); 1968 } else { 1969 ret = -EBUSY; 1970 } 1971 return ret; 1972 } 1973 1974 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1975 const void *buf, int dwords) 1976 { 1977 unsigned long flags; 1978 int offs, ret = 0; 1979 const u32 *vals = buf; 1980 1981 if (iwl_trans_grab_nic_access(trans, &flags)) { 1982 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1983 for (offs = 0; offs < dwords; offs++) 1984 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1985 vals ? vals[offs] : 0); 1986 iwl_trans_release_nic_access(trans, &flags); 1987 } else { 1988 ret = -EBUSY; 1989 } 1990 return ret; 1991 } 1992 1993 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1994 unsigned long txqs, 1995 bool freeze) 1996 { 1997 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1998 int queue; 1999 2000 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2001 struct iwl_txq *txq = &trans_pcie->txq[queue]; 2002 unsigned long now; 2003 2004 spin_lock_bh(&txq->lock); 2005 2006 now = jiffies; 2007 2008 if (txq->frozen == freeze) 2009 goto next_queue; 2010 2011 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2012 freeze ? "Freezing" : "Waking", queue); 2013 2014 txq->frozen = freeze; 2015 2016 if (txq->read_ptr == txq->write_ptr) 2017 goto next_queue; 2018 2019 if (freeze) { 2020 if (unlikely(time_after(now, 2021 txq->stuck_timer.expires))) { 2022 /* 2023 * The timer should have fired, maybe it is 2024 * spinning right now on the lock. 2025 */ 2026 goto next_queue; 2027 } 2028 /* remember how long until the timer fires */ 2029 txq->frozen_expiry_remainder = 2030 txq->stuck_timer.expires - now; 2031 del_timer(&txq->stuck_timer); 2032 goto next_queue; 2033 } 2034 2035 /* 2036 * Wake a non-empty queue -> arm timer with the 2037 * remainder before it froze 2038 */ 2039 mod_timer(&txq->stuck_timer, 2040 now + txq->frozen_expiry_remainder); 2041 2042 next_queue: 2043 spin_unlock_bh(&txq->lock); 2044 } 2045 } 2046 2047 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2048 { 2049 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2050 int i; 2051 2052 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2053 struct iwl_txq *txq = &trans_pcie->txq[i]; 2054 2055 if (i == trans_pcie->cmd_queue) 2056 continue; 2057 2058 spin_lock_bh(&txq->lock); 2059 2060 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2061 txq->block--; 2062 if (!txq->block) { 2063 iwl_write32(trans, HBUS_TARG_WRPTR, 2064 txq->write_ptr | (i << 8)); 2065 } 2066 } else if (block) { 2067 txq->block++; 2068 } 2069 2070 spin_unlock_bh(&txq->lock); 2071 } 2072 } 2073 2074 #define IWL_FLUSH_WAIT_MS 2000 2075 2076 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2077 { 2078 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2079 u32 scd_sram_addr; 2080 u8 buf[16]; 2081 int cnt; 2082 2083 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 2084 txq->read_ptr, txq->write_ptr); 2085 2086 if (trans->cfg->use_tfh) 2087 /* TODO: access new SCD registers and dump them */ 2088 return; 2089 2090 scd_sram_addr = trans_pcie->scd_base_addr + 2091 SCD_TX_STTS_QUEUE_OFFSET(txq->id); 2092 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 2093 2094 iwl_print_hex_error(trans, buf, sizeof(buf)); 2095 2096 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 2097 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 2098 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 2099 2100 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2101 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 2102 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2103 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2104 u32 tbl_dw = 2105 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 2106 SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 2107 2108 if (cnt & 0x1) 2109 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 2110 else 2111 tbl_dw = tbl_dw & 0x0000FFFF; 2112 2113 IWL_ERR(trans, 2114 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 2115 cnt, active ? "" : "in", fifo, tbl_dw, 2116 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 2117 (TFD_QUEUE_SIZE_MAX - 1), 2118 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 2119 } 2120 } 2121 2122 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 2123 { 2124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2125 struct iwl_txq *txq; 2126 int cnt; 2127 unsigned long now = jiffies; 2128 int ret = 0; 2129 2130 /* waiting for all the tx frames complete might take a while */ 2131 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2132 u8 wr_ptr; 2133 2134 if (cnt == trans_pcie->cmd_queue) 2135 continue; 2136 if (!test_bit(cnt, trans_pcie->queue_used)) 2137 continue; 2138 if (!(BIT(cnt) & txq_bm)) 2139 continue; 2140 2141 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 2142 txq = &trans_pcie->txq[cnt]; 2143 wr_ptr = ACCESS_ONCE(txq->write_ptr); 2144 2145 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) && 2146 !time_after(jiffies, 2147 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2148 u8 write_ptr = ACCESS_ONCE(txq->write_ptr); 2149 2150 if (WARN_ONCE(wr_ptr != write_ptr, 2151 "WR pointer moved while flushing %d -> %d\n", 2152 wr_ptr, write_ptr)) 2153 return -ETIMEDOUT; 2154 usleep_range(1000, 2000); 2155 } 2156 2157 if (txq->read_ptr != txq->write_ptr) { 2158 IWL_ERR(trans, 2159 "fail to flush all tx fifo queues Q %d\n", cnt); 2160 ret = -ETIMEDOUT; 2161 break; 2162 } 2163 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 2164 } 2165 2166 if (ret) 2167 iwl_trans_pcie_log_scd_error(trans, txq); 2168 2169 return ret; 2170 } 2171 2172 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2173 u32 mask, u32 value) 2174 { 2175 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2176 unsigned long flags; 2177 2178 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2179 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2180 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2181 } 2182 2183 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2184 { 2185 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2186 2187 if (iwlwifi_mod_params.d0i3_disable) 2188 return; 2189 2190 pm_runtime_get(&trans_pcie->pci_dev->dev); 2191 2192 #ifdef CONFIG_PM 2193 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2194 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2195 #endif /* CONFIG_PM */ 2196 } 2197 2198 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2199 { 2200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2201 2202 if (iwlwifi_mod_params.d0i3_disable) 2203 return; 2204 2205 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2206 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2207 2208 #ifdef CONFIG_PM 2209 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2210 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2211 #endif /* CONFIG_PM */ 2212 } 2213 2214 static const char *get_csr_string(int cmd) 2215 { 2216 #define IWL_CMD(x) case x: return #x 2217 switch (cmd) { 2218 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2219 IWL_CMD(CSR_INT_COALESCING); 2220 IWL_CMD(CSR_INT); 2221 IWL_CMD(CSR_INT_MASK); 2222 IWL_CMD(CSR_FH_INT_STATUS); 2223 IWL_CMD(CSR_GPIO_IN); 2224 IWL_CMD(CSR_RESET); 2225 IWL_CMD(CSR_GP_CNTRL); 2226 IWL_CMD(CSR_HW_REV); 2227 IWL_CMD(CSR_EEPROM_REG); 2228 IWL_CMD(CSR_EEPROM_GP); 2229 IWL_CMD(CSR_OTP_GP_REG); 2230 IWL_CMD(CSR_GIO_REG); 2231 IWL_CMD(CSR_GP_UCODE_REG); 2232 IWL_CMD(CSR_GP_DRIVER_REG); 2233 IWL_CMD(CSR_UCODE_DRV_GP1); 2234 IWL_CMD(CSR_UCODE_DRV_GP2); 2235 IWL_CMD(CSR_LED_REG); 2236 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2237 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2238 IWL_CMD(CSR_ANA_PLL_CFG); 2239 IWL_CMD(CSR_HW_REV_WA_REG); 2240 IWL_CMD(CSR_MONITOR_STATUS_REG); 2241 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2242 default: 2243 return "UNKNOWN"; 2244 } 2245 #undef IWL_CMD 2246 } 2247 2248 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2249 { 2250 int i; 2251 static const u32 csr_tbl[] = { 2252 CSR_HW_IF_CONFIG_REG, 2253 CSR_INT_COALESCING, 2254 CSR_INT, 2255 CSR_INT_MASK, 2256 CSR_FH_INT_STATUS, 2257 CSR_GPIO_IN, 2258 CSR_RESET, 2259 CSR_GP_CNTRL, 2260 CSR_HW_REV, 2261 CSR_EEPROM_REG, 2262 CSR_EEPROM_GP, 2263 CSR_OTP_GP_REG, 2264 CSR_GIO_REG, 2265 CSR_GP_UCODE_REG, 2266 CSR_GP_DRIVER_REG, 2267 CSR_UCODE_DRV_GP1, 2268 CSR_UCODE_DRV_GP2, 2269 CSR_LED_REG, 2270 CSR_DRAM_INT_TBL_REG, 2271 CSR_GIO_CHICKEN_BITS, 2272 CSR_ANA_PLL_CFG, 2273 CSR_MONITOR_STATUS_REG, 2274 CSR_HW_REV_WA_REG, 2275 CSR_DBG_HPET_MEM_REG 2276 }; 2277 IWL_ERR(trans, "CSR values:\n"); 2278 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2279 "CSR_INT_PERIODIC_REG)\n"); 2280 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2281 IWL_ERR(trans, " %25s: 0X%08x\n", 2282 get_csr_string(csr_tbl[i]), 2283 iwl_read32(trans, csr_tbl[i])); 2284 } 2285 } 2286 2287 #ifdef CONFIG_IWLWIFI_DEBUGFS 2288 /* create and remove of files */ 2289 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2290 if (!debugfs_create_file(#name, mode, parent, trans, \ 2291 &iwl_dbgfs_##name##_ops)) \ 2292 goto err; \ 2293 } while (0) 2294 2295 /* file operation */ 2296 #define DEBUGFS_READ_FILE_OPS(name) \ 2297 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2298 .read = iwl_dbgfs_##name##_read, \ 2299 .open = simple_open, \ 2300 .llseek = generic_file_llseek, \ 2301 }; 2302 2303 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2304 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2305 .write = iwl_dbgfs_##name##_write, \ 2306 .open = simple_open, \ 2307 .llseek = generic_file_llseek, \ 2308 }; 2309 2310 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2311 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2312 .write = iwl_dbgfs_##name##_write, \ 2313 .read = iwl_dbgfs_##name##_read, \ 2314 .open = simple_open, \ 2315 .llseek = generic_file_llseek, \ 2316 }; 2317 2318 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2319 char __user *user_buf, 2320 size_t count, loff_t *ppos) 2321 { 2322 struct iwl_trans *trans = file->private_data; 2323 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2324 struct iwl_txq *txq; 2325 char *buf; 2326 int pos = 0; 2327 int cnt; 2328 int ret; 2329 size_t bufsz; 2330 2331 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2332 2333 if (!trans_pcie->txq) 2334 return -EAGAIN; 2335 2336 buf = kzalloc(bufsz, GFP_KERNEL); 2337 if (!buf) 2338 return -ENOMEM; 2339 2340 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2341 txq = &trans_pcie->txq[cnt]; 2342 pos += scnprintf(buf + pos, bufsz - pos, 2343 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2344 cnt, txq->read_ptr, txq->write_ptr, 2345 !!test_bit(cnt, trans_pcie->queue_used), 2346 !!test_bit(cnt, trans_pcie->queue_stopped), 2347 txq->need_update, txq->frozen, 2348 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2349 } 2350 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2351 kfree(buf); 2352 return ret; 2353 } 2354 2355 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2356 char __user *user_buf, 2357 size_t count, loff_t *ppos) 2358 { 2359 struct iwl_trans *trans = file->private_data; 2360 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2361 char *buf; 2362 int pos = 0, i, ret; 2363 size_t bufsz = sizeof(buf); 2364 2365 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2366 2367 if (!trans_pcie->rxq) 2368 return -EAGAIN; 2369 2370 buf = kzalloc(bufsz, GFP_KERNEL); 2371 if (!buf) 2372 return -ENOMEM; 2373 2374 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2375 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2376 2377 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2378 i); 2379 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2380 rxq->read); 2381 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2382 rxq->write); 2383 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2384 rxq->write_actual); 2385 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2386 rxq->need_update); 2387 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2388 rxq->free_count); 2389 if (rxq->rb_stts) { 2390 pos += scnprintf(buf + pos, bufsz - pos, 2391 "\tclosed_rb_num: %u\n", 2392 le16_to_cpu(rxq->rb_stts->closed_rb_num) & 2393 0x0FFF); 2394 } else { 2395 pos += scnprintf(buf + pos, bufsz - pos, 2396 "\tclosed_rb_num: Not Allocated\n"); 2397 } 2398 } 2399 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2400 kfree(buf); 2401 2402 return ret; 2403 } 2404 2405 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2406 char __user *user_buf, 2407 size_t count, loff_t *ppos) 2408 { 2409 struct iwl_trans *trans = file->private_data; 2410 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2411 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2412 2413 int pos = 0; 2414 char *buf; 2415 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2416 ssize_t ret; 2417 2418 buf = kzalloc(bufsz, GFP_KERNEL); 2419 if (!buf) 2420 return -ENOMEM; 2421 2422 pos += scnprintf(buf + pos, bufsz - pos, 2423 "Interrupt Statistics Report:\n"); 2424 2425 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2426 isr_stats->hw); 2427 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2428 isr_stats->sw); 2429 if (isr_stats->sw || isr_stats->hw) { 2430 pos += scnprintf(buf + pos, bufsz - pos, 2431 "\tLast Restarting Code: 0x%X\n", 2432 isr_stats->err_code); 2433 } 2434 #ifdef CONFIG_IWLWIFI_DEBUG 2435 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2436 isr_stats->sch); 2437 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2438 isr_stats->alive); 2439 #endif 2440 pos += scnprintf(buf + pos, bufsz - pos, 2441 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2442 2443 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2444 isr_stats->ctkill); 2445 2446 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2447 isr_stats->wakeup); 2448 2449 pos += scnprintf(buf + pos, bufsz - pos, 2450 "Rx command responses:\t\t %u\n", isr_stats->rx); 2451 2452 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2453 isr_stats->tx); 2454 2455 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2456 isr_stats->unhandled); 2457 2458 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2459 kfree(buf); 2460 return ret; 2461 } 2462 2463 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2464 const char __user *user_buf, 2465 size_t count, loff_t *ppos) 2466 { 2467 struct iwl_trans *trans = file->private_data; 2468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2469 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2470 2471 char buf[8]; 2472 int buf_size; 2473 u32 reset_flag; 2474 2475 memset(buf, 0, sizeof(buf)); 2476 buf_size = min(count, sizeof(buf) - 1); 2477 if (copy_from_user(buf, user_buf, buf_size)) 2478 return -EFAULT; 2479 if (sscanf(buf, "%x", &reset_flag) != 1) 2480 return -EFAULT; 2481 if (reset_flag == 0) 2482 memset(isr_stats, 0, sizeof(*isr_stats)); 2483 2484 return count; 2485 } 2486 2487 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2488 const char __user *user_buf, 2489 size_t count, loff_t *ppos) 2490 { 2491 struct iwl_trans *trans = file->private_data; 2492 char buf[8]; 2493 int buf_size; 2494 int csr; 2495 2496 memset(buf, 0, sizeof(buf)); 2497 buf_size = min(count, sizeof(buf) - 1); 2498 if (copy_from_user(buf, user_buf, buf_size)) 2499 return -EFAULT; 2500 if (sscanf(buf, "%d", &csr) != 1) 2501 return -EFAULT; 2502 2503 iwl_pcie_dump_csr(trans); 2504 2505 return count; 2506 } 2507 2508 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2509 char __user *user_buf, 2510 size_t count, loff_t *ppos) 2511 { 2512 struct iwl_trans *trans = file->private_data; 2513 char *buf = NULL; 2514 ssize_t ret; 2515 2516 ret = iwl_dump_fh(trans, &buf); 2517 if (ret < 0) 2518 return ret; 2519 if (!buf) 2520 return -EINVAL; 2521 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2522 kfree(buf); 2523 return ret; 2524 } 2525 2526 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2527 DEBUGFS_READ_FILE_OPS(fh_reg); 2528 DEBUGFS_READ_FILE_OPS(rx_queue); 2529 DEBUGFS_READ_FILE_OPS(tx_queue); 2530 DEBUGFS_WRITE_FILE_OPS(csr); 2531 2532 /* Create the debugfs files and directories */ 2533 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2534 { 2535 struct dentry *dir = trans->dbgfs_dir; 2536 2537 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2538 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2539 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2540 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2541 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2542 return 0; 2543 2544 err: 2545 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2546 return -ENOMEM; 2547 } 2548 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2549 2550 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2551 { 2552 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2553 u32 cmdlen = 0; 2554 int i; 2555 2556 for (i = 0; i < trans_pcie->max_tbs; i++) 2557 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2558 2559 return cmdlen; 2560 } 2561 2562 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2563 struct iwl_fw_error_dump_data **data, 2564 int allocated_rb_nums) 2565 { 2566 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2567 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2568 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2569 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2570 u32 i, r, j, rb_len = 0; 2571 2572 spin_lock(&rxq->lock); 2573 2574 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2575 2576 for (i = rxq->read, j = 0; 2577 i != r && j < allocated_rb_nums; 2578 i = (i + 1) & RX_QUEUE_MASK, j++) { 2579 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2580 struct iwl_fw_error_dump_rb *rb; 2581 2582 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2583 DMA_FROM_DEVICE); 2584 2585 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2586 2587 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2588 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2589 rb = (void *)(*data)->data; 2590 rb->index = cpu_to_le32(i); 2591 memcpy(rb->data, page_address(rxb->page), max_len); 2592 /* remap the page for the free benefit */ 2593 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2594 max_len, 2595 DMA_FROM_DEVICE); 2596 2597 *data = iwl_fw_error_next_data(*data); 2598 } 2599 2600 spin_unlock(&rxq->lock); 2601 2602 return rb_len; 2603 } 2604 #define IWL_CSR_TO_DUMP (0x250) 2605 2606 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2607 struct iwl_fw_error_dump_data **data) 2608 { 2609 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2610 __le32 *val; 2611 int i; 2612 2613 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2614 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2615 val = (void *)(*data)->data; 2616 2617 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2618 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2619 2620 *data = iwl_fw_error_next_data(*data); 2621 2622 return csr_len; 2623 } 2624 2625 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2626 struct iwl_fw_error_dump_data **data) 2627 { 2628 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2629 unsigned long flags; 2630 __le32 *val; 2631 int i; 2632 2633 if (!iwl_trans_grab_nic_access(trans, &flags)) 2634 return 0; 2635 2636 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2637 (*data)->len = cpu_to_le32(fh_regs_len); 2638 val = (void *)(*data)->data; 2639 2640 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2641 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2642 2643 iwl_trans_release_nic_access(trans, &flags); 2644 2645 *data = iwl_fw_error_next_data(*data); 2646 2647 return sizeof(**data) + fh_regs_len; 2648 } 2649 2650 static u32 2651 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2652 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2653 u32 monitor_len) 2654 { 2655 u32 buf_size_in_dwords = (monitor_len >> 2); 2656 u32 *buffer = (u32 *)fw_mon_data->data; 2657 unsigned long flags; 2658 u32 i; 2659 2660 if (!iwl_trans_grab_nic_access(trans, &flags)) 2661 return 0; 2662 2663 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2664 for (i = 0; i < buf_size_in_dwords; i++) 2665 buffer[i] = iwl_read_prph_no_grab(trans, 2666 MON_DMARB_RD_DATA_ADDR); 2667 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2668 2669 iwl_trans_release_nic_access(trans, &flags); 2670 2671 return monitor_len; 2672 } 2673 2674 static u32 2675 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2676 struct iwl_fw_error_dump_data **data, 2677 u32 monitor_len) 2678 { 2679 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2680 u32 len = 0; 2681 2682 if ((trans_pcie->fw_mon_page && 2683 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2684 trans->dbg_dest_tlv) { 2685 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2686 u32 base, write_ptr, wrap_cnt; 2687 2688 /* If there was a dest TLV - use the values from there */ 2689 if (trans->dbg_dest_tlv) { 2690 write_ptr = 2691 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2692 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2693 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2694 } else { 2695 base = MON_BUFF_BASE_ADDR; 2696 write_ptr = MON_BUFF_WRPTR; 2697 wrap_cnt = MON_BUFF_CYCLE_CNT; 2698 } 2699 2700 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2701 fw_mon_data = (void *)(*data)->data; 2702 fw_mon_data->fw_mon_wr_ptr = 2703 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2704 fw_mon_data->fw_mon_cycle_cnt = 2705 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2706 fw_mon_data->fw_mon_base_ptr = 2707 cpu_to_le32(iwl_read_prph(trans, base)); 2708 2709 len += sizeof(**data) + sizeof(*fw_mon_data); 2710 if (trans_pcie->fw_mon_page) { 2711 /* 2712 * The firmware is now asserted, it won't write anything 2713 * to the buffer. CPU can take ownership to fetch the 2714 * data. The buffer will be handed back to the device 2715 * before the firmware will be restarted. 2716 */ 2717 dma_sync_single_for_cpu(trans->dev, 2718 trans_pcie->fw_mon_phys, 2719 trans_pcie->fw_mon_size, 2720 DMA_FROM_DEVICE); 2721 memcpy(fw_mon_data->data, 2722 page_address(trans_pcie->fw_mon_page), 2723 trans_pcie->fw_mon_size); 2724 2725 monitor_len = trans_pcie->fw_mon_size; 2726 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2727 /* 2728 * Update pointers to reflect actual values after 2729 * shifting 2730 */ 2731 base = iwl_read_prph(trans, base) << 2732 trans->dbg_dest_tlv->base_shift; 2733 iwl_trans_read_mem(trans, base, fw_mon_data->data, 2734 monitor_len / sizeof(u32)); 2735 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2736 monitor_len = 2737 iwl_trans_pci_dump_marbh_monitor(trans, 2738 fw_mon_data, 2739 monitor_len); 2740 } else { 2741 /* Didn't match anything - output no monitor data */ 2742 monitor_len = 0; 2743 } 2744 2745 len += monitor_len; 2746 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2747 } 2748 2749 return len; 2750 } 2751 2752 static struct iwl_trans_dump_data 2753 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2754 const struct iwl_fw_dbg_trigger_tlv *trigger) 2755 { 2756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2757 struct iwl_fw_error_dump_data *data; 2758 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2759 struct iwl_fw_error_dump_txcmd *txcmd; 2760 struct iwl_trans_dump_data *dump_data; 2761 u32 len, num_rbs; 2762 u32 monitor_len; 2763 int i, ptr; 2764 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2765 !trans->cfg->mq_rx_supported; 2766 2767 /* transport dump header */ 2768 len = sizeof(*dump_data); 2769 2770 /* host commands */ 2771 len += sizeof(*data) + 2772 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2773 2774 /* FW monitor */ 2775 if (trans_pcie->fw_mon_page) { 2776 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2777 trans_pcie->fw_mon_size; 2778 monitor_len = trans_pcie->fw_mon_size; 2779 } else if (trans->dbg_dest_tlv) { 2780 u32 base, end; 2781 2782 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2783 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2784 2785 base = iwl_read_prph(trans, base) << 2786 trans->dbg_dest_tlv->base_shift; 2787 end = iwl_read_prph(trans, end) << 2788 trans->dbg_dest_tlv->end_shift; 2789 2790 /* Make "end" point to the actual end */ 2791 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2792 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2793 end += (1 << trans->dbg_dest_tlv->end_shift); 2794 monitor_len = end - base; 2795 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2796 monitor_len; 2797 } else { 2798 monitor_len = 0; 2799 } 2800 2801 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2802 dump_data = vzalloc(len); 2803 if (!dump_data) 2804 return NULL; 2805 2806 data = (void *)dump_data->data; 2807 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2808 dump_data->len = len; 2809 2810 return dump_data; 2811 } 2812 2813 /* CSR registers */ 2814 len += sizeof(*data) + IWL_CSR_TO_DUMP; 2815 2816 /* FH registers */ 2817 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2818 2819 if (dump_rbs) { 2820 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2821 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2822 /* RBs */ 2823 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2824 & 0x0FFF; 2825 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2826 len += num_rbs * (sizeof(*data) + 2827 sizeof(struct iwl_fw_error_dump_rb) + 2828 (PAGE_SIZE << trans_pcie->rx_page_order)); 2829 } 2830 2831 dump_data = vzalloc(len); 2832 if (!dump_data) 2833 return NULL; 2834 2835 len = 0; 2836 data = (void *)dump_data->data; 2837 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2838 txcmd = (void *)data->data; 2839 spin_lock_bh(&cmdq->lock); 2840 ptr = cmdq->write_ptr; 2841 for (i = 0; i < cmdq->n_window; i++) { 2842 u8 idx = get_cmd_index(cmdq, ptr); 2843 u32 caplen, cmdlen; 2844 2845 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 2846 trans_pcie->tfd_size * ptr); 2847 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2848 2849 if (cmdlen) { 2850 len += sizeof(*txcmd) + caplen; 2851 txcmd->cmdlen = cpu_to_le32(cmdlen); 2852 txcmd->caplen = cpu_to_le32(caplen); 2853 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2854 txcmd = (void *)((u8 *)txcmd->data + caplen); 2855 } 2856 2857 ptr = iwl_queue_dec_wrap(ptr); 2858 } 2859 spin_unlock_bh(&cmdq->lock); 2860 2861 data->len = cpu_to_le32(len); 2862 len += sizeof(*data); 2863 data = iwl_fw_error_next_data(data); 2864 2865 len += iwl_trans_pcie_dump_csr(trans, &data); 2866 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2867 if (dump_rbs) 2868 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2869 2870 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2871 2872 dump_data->len = len; 2873 2874 return dump_data; 2875 } 2876 2877 #ifdef CONFIG_PM_SLEEP 2878 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 2879 { 2880 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2881 return iwl_pci_fw_enter_d0i3(trans); 2882 2883 return 0; 2884 } 2885 2886 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 2887 { 2888 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 2889 iwl_pci_fw_exit_d0i3(trans); 2890 } 2891 #endif /* CONFIG_PM_SLEEP */ 2892 2893 static const struct iwl_trans_ops trans_ops_pcie = { 2894 .start_hw = iwl_trans_pcie_start_hw, 2895 .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2896 .fw_alive = iwl_trans_pcie_fw_alive, 2897 .start_fw = iwl_trans_pcie_start_fw, 2898 .stop_device = iwl_trans_pcie_stop_device, 2899 2900 .d3_suspend = iwl_trans_pcie_d3_suspend, 2901 .d3_resume = iwl_trans_pcie_d3_resume, 2902 2903 #ifdef CONFIG_PM_SLEEP 2904 .suspend = iwl_trans_pcie_suspend, 2905 .resume = iwl_trans_pcie_resume, 2906 #endif /* CONFIG_PM_SLEEP */ 2907 2908 .send_cmd = iwl_trans_pcie_send_hcmd, 2909 2910 .tx = iwl_trans_pcie_tx, 2911 .reclaim = iwl_trans_pcie_reclaim, 2912 2913 .txq_disable = iwl_trans_pcie_txq_disable, 2914 .txq_enable = iwl_trans_pcie_txq_enable, 2915 2916 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table, 2917 2918 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 2919 2920 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2921 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 2922 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2923 2924 .write8 = iwl_trans_pcie_write8, 2925 .write32 = iwl_trans_pcie_write32, 2926 .read32 = iwl_trans_pcie_read32, 2927 .read_prph = iwl_trans_pcie_read_prph, 2928 .write_prph = iwl_trans_pcie_write_prph, 2929 .read_mem = iwl_trans_pcie_read_mem, 2930 .write_mem = iwl_trans_pcie_write_mem, 2931 .configure = iwl_trans_pcie_configure, 2932 .set_pmi = iwl_trans_pcie_set_pmi, 2933 .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2934 .release_nic_access = iwl_trans_pcie_release_nic_access, 2935 .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2936 2937 .ref = iwl_trans_pcie_ref, 2938 .unref = iwl_trans_pcie_unref, 2939 2940 .dump_data = iwl_trans_pcie_dump_data, 2941 }; 2942 2943 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2944 const struct pci_device_id *ent, 2945 const struct iwl_cfg *cfg) 2946 { 2947 struct iwl_trans_pcie *trans_pcie; 2948 struct iwl_trans *trans; 2949 int ret, addr_size; 2950 2951 ret = pcim_enable_device(pdev); 2952 if (ret) 2953 return ERR_PTR(ret); 2954 2955 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2956 &pdev->dev, cfg, &trans_ops_pcie, 0); 2957 if (!trans) 2958 return ERR_PTR(-ENOMEM); 2959 2960 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2961 2962 trans_pcie->trans = trans; 2963 spin_lock_init(&trans_pcie->irq_lock); 2964 spin_lock_init(&trans_pcie->reg_lock); 2965 mutex_init(&trans_pcie->mutex); 2966 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 2967 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 2968 if (!trans_pcie->tso_hdr_page) { 2969 ret = -ENOMEM; 2970 goto out_no_pci; 2971 } 2972 2973 2974 if (!cfg->base_params->pcie_l1_allowed) { 2975 /* 2976 * W/A - seems to solve weird behavior. We need to remove this 2977 * if we don't want to stay in L1 all the time. This wastes a 2978 * lot of power. 2979 */ 2980 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2981 PCIE_LINK_STATE_L1 | 2982 PCIE_LINK_STATE_CLKPM); 2983 } 2984 2985 if (cfg->use_tfh) { 2986 addr_size = 64; 2987 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 2988 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 2989 } else { 2990 addr_size = 36; 2991 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 2992 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 2993 } 2994 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 2995 2996 pci_set_master(pdev); 2997 2998 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2999 if (!ret) 3000 ret = pci_set_consistent_dma_mask(pdev, 3001 DMA_BIT_MASK(addr_size)); 3002 if (ret) { 3003 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3004 if (!ret) 3005 ret = pci_set_consistent_dma_mask(pdev, 3006 DMA_BIT_MASK(32)); 3007 /* both attempts failed: */ 3008 if (ret) { 3009 dev_err(&pdev->dev, "No suitable DMA available\n"); 3010 goto out_no_pci; 3011 } 3012 } 3013 3014 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3015 if (ret) { 3016 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3017 goto out_no_pci; 3018 } 3019 3020 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3021 if (!trans_pcie->hw_base) { 3022 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3023 ret = -ENODEV; 3024 goto out_no_pci; 3025 } 3026 3027 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3028 * PCI Tx retries from interfering with C3 CPU state */ 3029 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3030 3031 trans->dev = &pdev->dev; 3032 trans_pcie->pci_dev = pdev; 3033 iwl_disable_interrupts(trans); 3034 3035 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3036 /* 3037 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3038 * changed, and now the revision step also includes bit 0-1 (no more 3039 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3040 * in the old format. 3041 */ 3042 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 3043 unsigned long flags; 3044 3045 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3046 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3047 3048 ret = iwl_pcie_prepare_card_hw(trans); 3049 if (ret) { 3050 IWL_WARN(trans, "Exit HW not ready\n"); 3051 goto out_no_pci; 3052 } 3053 3054 /* 3055 * in-order to recognize C step driver should read chip version 3056 * id located at the AUX bus MISC address space. 3057 */ 3058 iwl_set_bit(trans, CSR_GP_CNTRL, 3059 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3060 udelay(2); 3061 3062 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3063 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3064 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3065 25000); 3066 if (ret < 0) { 3067 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3068 goto out_no_pci; 3069 } 3070 3071 if (iwl_trans_grab_nic_access(trans, &flags)) { 3072 u32 hw_step; 3073 3074 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3075 hw_step |= ENABLE_WFPM; 3076 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3077 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3078 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3079 if (hw_step == 0x3) 3080 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3081 (SILICON_C_STEP << 2); 3082 iwl_trans_release_nic_access(trans, &flags); 3083 } 3084 } 3085 3086 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3087 3088 iwl_pcie_set_interrupt_capa(pdev, trans); 3089 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3090 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3091 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3092 3093 /* Initialize the wait queue for commands */ 3094 init_waitqueue_head(&trans_pcie->wait_command_queue); 3095 3096 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3097 3098 if (trans_pcie->msix_enabled) { 3099 if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 3100 goto out_no_pci; 3101 } else { 3102 ret = iwl_pcie_alloc_ict(trans); 3103 if (ret) 3104 goto out_no_pci; 3105 3106 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3107 iwl_pcie_isr, 3108 iwl_pcie_irq_handler, 3109 IRQF_SHARED, DRV_NAME, trans); 3110 if (ret) { 3111 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3112 goto out_free_ict; 3113 } 3114 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3115 } 3116 3117 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3118 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3119 #else 3120 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3121 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3122 3123 return trans; 3124 3125 out_free_ict: 3126 iwl_pcie_free_ict(trans); 3127 out_no_pci: 3128 free_percpu(trans_pcie->tso_hdr_page); 3129 iwl_trans_free(trans); 3130 return ERR_PTR(ret); 3131 } 3132