1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11 * Copyright(c) 2018 Intel Corporation 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of version 2 of the GNU General Public License as 15 * published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope that it will be useful, but 18 * WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20 * General Public License for more details. 21 * 22 * The full GNU General Public License is included in this distribution 23 * in the file called COPYING. 24 * 25 * Contact Information: 26 * Intel Linux Wireless <linuxwifi@intel.com> 27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28 * 29 * BSD LICENSE 30 * 31 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34 * Copyright(c) 2018 Intel Corporation 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 41 * * Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * * Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in 45 * the documentation and/or other materials provided with the 46 * distribution. 47 * * Neither the name Intel Corporation nor the names of its 48 * contributors may be used to endorse or promote products derived 49 * from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 *****************************************************************************/ 64 #include <linux/pci.h> 65 #include <linux/pci-aspm.h> 66 #include <linux/interrupt.h> 67 #include <linux/debugfs.h> 68 #include <linux/sched.h> 69 #include <linux/bitops.h> 70 #include <linux/gfp.h> 71 #include <linux/vmalloc.h> 72 #include <linux/pm_runtime.h> 73 #include <linux/module.h> 74 #include <linux/wait.h> 75 76 #include "iwl-drv.h" 77 #include "iwl-trans.h" 78 #include "iwl-csr.h" 79 #include "iwl-prph.h" 80 #include "iwl-scd.h" 81 #include "iwl-agn-hw.h" 82 #include "fw/error-dump.h" 83 #include "fw/dbg.h" 84 #include "internal.h" 85 #include "iwl-fh.h" 86 87 /* extended range in FW SRAM */ 88 #define IWL_FW_MEM_EXTENDED_START 0x40000 89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90 91 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92 { 93 #define PCI_DUMP_SIZE 64 94 #define PREFIX_LEN 32 95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96 struct pci_dev *pdev = trans_pcie->pci_dev; 97 u32 i, pos, alloc_size, *ptr, *buf; 98 char *prefix; 99 100 if (trans_pcie->pcie_dbg_dumped_once) 101 return; 102 103 /* Should be a multiple of 4 */ 104 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105 /* Alloc a max size buffer */ 106 if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108 else 109 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110 buf = kmalloc(alloc_size, GFP_ATOMIC); 111 if (!buf) 112 return; 113 prefix = (char *)buf + alloc_size - PREFIX_LEN; 114 115 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116 117 /* Print wifi device registers */ 118 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119 IWL_ERR(trans, "iwlwifi device config registers:\n"); 120 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121 if (pci_read_config_dword(pdev, i, ptr)) 122 goto err_read; 123 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124 125 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127 *ptr = iwl_read32(trans, i); 128 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129 130 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131 if (pos) { 132 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134 if (pci_read_config_dword(pdev, pos + i, ptr)) 135 goto err_read; 136 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137 32, 4, buf, i, 0); 138 } 139 140 /* Print parent device registers next */ 141 if (!pdev->bus->self) 142 goto out; 143 144 pdev = pdev->bus->self; 145 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146 147 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148 pci_name(pdev)); 149 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150 if (pci_read_config_dword(pdev, i, ptr)) 151 goto err_read; 152 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153 154 /* Print root port AER registers */ 155 pos = 0; 156 pdev = pcie_find_root_port(pdev); 157 if (pdev) 158 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159 if (pos) { 160 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161 pci_name(pdev)); 162 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164 if (pci_read_config_dword(pdev, pos + i, ptr)) 165 goto err_read; 166 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167 4, buf, i, 0); 168 } 169 goto out; 170 171 err_read: 172 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173 IWL_ERR(trans, "Read failed at 0x%X\n", i); 174 out: 175 trans_pcie->pcie_dbg_dumped_once = 1; 176 kfree(buf); 177 } 178 179 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 180 { 181 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 182 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 183 BIT(trans->cfg->csr->flag_sw_reset)); 184 usleep_range(5000, 6000); 185 } 186 187 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 188 { 189 int i; 190 191 for (i = 0; i < trans->num_blocks; i++) { 192 dma_free_coherent(trans->dev, trans->fw_mon[i].size, 193 trans->fw_mon[i].block, 194 trans->fw_mon[i].physical); 195 trans->fw_mon[i].block = NULL; 196 trans->fw_mon[i].physical = 0; 197 trans->fw_mon[i].size = 0; 198 trans->num_blocks--; 199 } 200 } 201 202 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 203 u8 max_power, u8 min_power) 204 { 205 void *cpu_addr = NULL; 206 dma_addr_t phys = 0; 207 u32 size = 0; 208 u8 power; 209 210 for (power = max_power; power >= min_power; power--) { 211 size = BIT(power); 212 cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 213 GFP_KERNEL | __GFP_NOWARN | 214 __GFP_ZERO | __GFP_COMP); 215 if (!cpu_addr) 216 continue; 217 218 IWL_INFO(trans, 219 "Allocated 0x%08x bytes for firmware monitor.\n", 220 size); 221 break; 222 } 223 224 if (WARN_ON_ONCE(!cpu_addr)) 225 return; 226 227 if (power != max_power) 228 IWL_ERR(trans, 229 "Sorry - debug buffer is only %luK while you requested %luK\n", 230 (unsigned long)BIT(power - 10), 231 (unsigned long)BIT(max_power - 10)); 232 233 trans->fw_mon[trans->num_blocks].block = cpu_addr; 234 trans->fw_mon[trans->num_blocks].physical = phys; 235 trans->fw_mon[trans->num_blocks].size = size; 236 trans->num_blocks++; 237 } 238 239 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 240 { 241 if (!max_power) { 242 /* default max_power is maximum */ 243 max_power = 26; 244 } else { 245 max_power += 11; 246 } 247 248 if (WARN(max_power > 26, 249 "External buffer size for monitor is too big %d, check the FW TLV\n", 250 max_power)) 251 return; 252 253 /* 254 * This function allocats the default fw monitor. 255 * The optional additional ones will be allocated in runtime 256 */ 257 if (trans->num_blocks) 258 return; 259 260 iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 261 } 262 263 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 264 { 265 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 266 ((reg & 0x0000ffff) | (2 << 28))); 267 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 268 } 269 270 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 271 { 272 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 273 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274 ((reg & 0x0000ffff) | (3 << 28))); 275 } 276 277 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 278 { 279 if (trans->cfg->apmg_not_supported) 280 return; 281 282 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 283 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 284 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 285 ~APMG_PS_CTRL_MSK_PWR_SRC); 286 else 287 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 288 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 289 ~APMG_PS_CTRL_MSK_PWR_SRC); 290 } 291 292 /* PCI registers */ 293 #define PCI_CFG_RETRY_TIMEOUT 0x041 294 295 void iwl_pcie_apm_config(struct iwl_trans *trans) 296 { 297 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 298 u16 lctl; 299 u16 cap; 300 301 /* 302 * HW bug W/A for instability in PCIe bus L0S->L1 transition. 303 * Check if BIOS (or OS) enabled L1-ASPM on this device. 304 * If so (likely), disable L0S, so device moves directly L0->L1; 305 * costs negligible amount of power savings. 306 * If not (unlikely), enable L0S, so there is at least some 307 * power savings, even without L1. 308 */ 309 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 310 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 311 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 312 else 313 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 314 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 315 316 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 317 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 318 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 319 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 320 trans->ltr_enabled ? "En" : "Dis"); 321 } 322 323 /* 324 * Start up NIC's basic functionality after it has been reset 325 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 326 * NOTE: This does not load uCode nor start the embedded processor 327 */ 328 static int iwl_pcie_apm_init(struct iwl_trans *trans) 329 { 330 int ret; 331 332 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 333 334 /* 335 * Use "set_bit" below rather than "write", to preserve any hardware 336 * bits already set by default after reset. 337 */ 338 339 /* Disable L0S exit timer (platform NMI Work/Around) */ 340 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 341 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 342 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 343 344 /* 345 * Disable L0s without affecting L1; 346 * don't wait for ICH L0s (ICH bug W/A) 347 */ 348 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 349 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 350 351 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 352 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 353 354 /* 355 * Enable HAP INTA (interrupt from management bus) to 356 * wake device's PCI Express link L1a -> L0s 357 */ 358 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 359 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 360 361 iwl_pcie_apm_config(trans); 362 363 /* Configure analog phase-lock-loop before activating to D0A */ 364 if (trans->cfg->base_params->pll_cfg) 365 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 366 367 /* 368 * Set "initialization complete" bit to move adapter from 369 * D0U* --> D0A* (powered-up active) state. 370 */ 371 iwl_set_bit(trans, CSR_GP_CNTRL, 372 BIT(trans->cfg->csr->flag_init_done)); 373 374 /* 375 * Wait for clock stabilization; once stabilized, access to 376 * device-internal resources is supported, e.g. iwl_write_prph() 377 * and accesses to uCode SRAM. 378 */ 379 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 380 BIT(trans->cfg->csr->flag_mac_clock_ready), 381 BIT(trans->cfg->csr->flag_mac_clock_ready), 382 25000); 383 if (ret < 0) { 384 IWL_ERR(trans, "Failed to init the card\n"); 385 return ret; 386 } 387 388 if (trans->cfg->host_interrupt_operation_mode) { 389 /* 390 * This is a bit of an abuse - This is needed for 7260 / 3160 391 * only check host_interrupt_operation_mode even if this is 392 * not related to host_interrupt_operation_mode. 393 * 394 * Enable the oscillator to count wake up time for L1 exit. This 395 * consumes slightly more power (100uA) - but allows to be sure 396 * that we wake up from L1 on time. 397 * 398 * This looks weird: read twice the same register, discard the 399 * value, set a bit, and yet again, read that same register 400 * just to discard the value. But that's the way the hardware 401 * seems to like it. 402 */ 403 iwl_read_prph(trans, OSC_CLK); 404 iwl_read_prph(trans, OSC_CLK); 405 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 406 iwl_read_prph(trans, OSC_CLK); 407 iwl_read_prph(trans, OSC_CLK); 408 } 409 410 /* 411 * Enable DMA clock and wait for it to stabilize. 412 * 413 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 414 * bits do not disable clocks. This preserves any hardware 415 * bits already set by default in "CLK_CTRL_REG" after reset. 416 */ 417 if (!trans->cfg->apmg_not_supported) { 418 iwl_write_prph(trans, APMG_CLK_EN_REG, 419 APMG_CLK_VAL_DMA_CLK_RQT); 420 udelay(20); 421 422 /* Disable L1-Active */ 423 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 424 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 425 426 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 427 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 428 APMG_RTC_INT_STT_RFKILL); 429 } 430 431 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 432 433 return 0; 434 } 435 436 /* 437 * Enable LP XTAL to avoid HW bug where device may consume much power if 438 * FW is not loaded after device reset. LP XTAL is disabled by default 439 * after device HW reset. Do it only if XTAL is fed by internal source. 440 * Configure device's "persistence" mode to avoid resetting XTAL again when 441 * SHRD_HW_RST occurs in S3. 442 */ 443 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 444 { 445 int ret; 446 u32 apmg_gp1_reg; 447 u32 apmg_xtal_cfg_reg; 448 u32 dl_cfg_reg; 449 450 /* Force XTAL ON */ 451 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 452 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 453 454 iwl_trans_pcie_sw_reset(trans); 455 456 /* 457 * Set "initialization complete" bit to move adapter from 458 * D0U* --> D0A* (powered-up active) state. 459 */ 460 iwl_set_bit(trans, CSR_GP_CNTRL, 461 BIT(trans->cfg->csr->flag_init_done)); 462 463 /* 464 * Wait for clock stabilization; once stabilized, access to 465 * device-internal resources is possible. 466 */ 467 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 468 BIT(trans->cfg->csr->flag_mac_clock_ready), 469 BIT(trans->cfg->csr->flag_mac_clock_ready), 470 25000); 471 if (WARN_ON(ret < 0)) { 472 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 473 /* Release XTAL ON request */ 474 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 475 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 476 return; 477 } 478 479 /* 480 * Clear "disable persistence" to avoid LP XTAL resetting when 481 * SHRD_HW_RST is applied in S3. 482 */ 483 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 484 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 485 486 /* 487 * Force APMG XTAL to be active to prevent its disabling by HW 488 * caused by APMG idle state. 489 */ 490 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 491 SHR_APMG_XTAL_CFG_REG); 492 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 493 apmg_xtal_cfg_reg | 494 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 495 496 iwl_trans_pcie_sw_reset(trans); 497 498 /* Enable LP XTAL by indirect access through CSR */ 499 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 500 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 501 SHR_APMG_GP1_WF_XTAL_LP_EN | 502 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 503 504 /* Clear delay line clock power up */ 505 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 506 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 507 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 508 509 /* 510 * Enable persistence mode to avoid LP XTAL resetting when 511 * SHRD_HW_RST is applied in S3. 512 */ 513 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 514 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 515 516 /* 517 * Clear "initialization complete" bit to move adapter from 518 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 519 */ 520 iwl_clear_bit(trans, CSR_GP_CNTRL, 521 BIT(trans->cfg->csr->flag_init_done)); 522 523 /* Activates XTAL resources monitor */ 524 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 525 CSR_MONITOR_XTAL_RESOURCES); 526 527 /* Release XTAL ON request */ 528 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 529 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 530 udelay(10); 531 532 /* Release APMG XTAL */ 533 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 534 apmg_xtal_cfg_reg & 535 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 536 } 537 538 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 539 { 540 int ret; 541 542 /* stop device's busmaster DMA activity */ 543 iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 544 BIT(trans->cfg->csr->flag_stop_master)); 545 546 ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 547 BIT(trans->cfg->csr->flag_master_dis), 548 BIT(trans->cfg->csr->flag_master_dis), 100); 549 if (ret < 0) 550 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 551 552 IWL_DEBUG_INFO(trans, "stop master\n"); 553 } 554 555 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 556 { 557 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 558 559 if (op_mode_leave) { 560 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 561 iwl_pcie_apm_init(trans); 562 563 /* inform ME that we are leaving */ 564 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 565 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 566 APMG_PCIDEV_STT_VAL_WAKE_ME); 567 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 568 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 569 CSR_RESET_LINK_PWR_MGMT_DISABLED); 570 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 571 CSR_HW_IF_CONFIG_REG_PREPARE | 572 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 573 mdelay(1); 574 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 575 CSR_RESET_LINK_PWR_MGMT_DISABLED); 576 } 577 mdelay(5); 578 } 579 580 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 581 582 /* Stop device's DMA activity */ 583 iwl_pcie_apm_stop_master(trans); 584 585 if (trans->cfg->lp_xtal_workaround) { 586 iwl_pcie_apm_lp_xtal_enable(trans); 587 return; 588 } 589 590 iwl_trans_pcie_sw_reset(trans); 591 592 /* 593 * Clear "initialization complete" bit to move adapter from 594 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 595 */ 596 iwl_clear_bit(trans, CSR_GP_CNTRL, 597 BIT(trans->cfg->csr->flag_init_done)); 598 } 599 600 static int iwl_pcie_nic_init(struct iwl_trans *trans) 601 { 602 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 603 int ret; 604 605 /* nic_init */ 606 spin_lock(&trans_pcie->irq_lock); 607 ret = iwl_pcie_apm_init(trans); 608 spin_unlock(&trans_pcie->irq_lock); 609 610 if (ret) 611 return ret; 612 613 iwl_pcie_set_pwr(trans, false); 614 615 iwl_op_mode_nic_config(trans->op_mode); 616 617 /* Allocate the RX queue, or reset if it is already allocated */ 618 iwl_pcie_rx_init(trans); 619 620 /* Allocate or reset and init all Tx and Command queues */ 621 if (iwl_pcie_tx_init(trans)) 622 return -ENOMEM; 623 624 if (trans->cfg->base_params->shadow_reg_enable) { 625 /* enable shadow regs in HW */ 626 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 627 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 628 } 629 630 return 0; 631 } 632 633 #define HW_READY_TIMEOUT (50) 634 635 /* Note: returns poll_bit return value, which is >= 0 if success */ 636 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 637 { 638 int ret; 639 640 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 641 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 642 643 /* See if we got it */ 644 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 645 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 646 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 647 HW_READY_TIMEOUT); 648 649 if (ret >= 0) 650 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 651 652 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 653 return ret; 654 } 655 656 /* Note: returns standard 0/-ERROR code */ 657 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 658 { 659 int ret; 660 int t = 0; 661 int iter; 662 663 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 664 665 ret = iwl_pcie_set_hw_ready(trans); 666 /* If the card is ready, exit 0 */ 667 if (ret >= 0) 668 return 0; 669 670 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 671 CSR_RESET_LINK_PWR_MGMT_DISABLED); 672 usleep_range(1000, 2000); 673 674 for (iter = 0; iter < 10; iter++) { 675 /* If HW is not ready, prepare the conditions to check again */ 676 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 677 CSR_HW_IF_CONFIG_REG_PREPARE); 678 679 do { 680 ret = iwl_pcie_set_hw_ready(trans); 681 if (ret >= 0) 682 return 0; 683 684 usleep_range(200, 1000); 685 t += 200; 686 } while (t < 150000); 687 msleep(25); 688 } 689 690 IWL_ERR(trans, "Couldn't prepare the card\n"); 691 692 return ret; 693 } 694 695 /* 696 * ucode 697 */ 698 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 699 u32 dst_addr, dma_addr_t phy_addr, 700 u32 byte_cnt) 701 { 702 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 703 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 704 705 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 706 dst_addr); 707 708 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 709 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 710 711 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 712 (iwl_get_dma_hi_addr(phy_addr) 713 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 714 715 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 716 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 717 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 718 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 719 720 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 721 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 722 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 723 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 724 } 725 726 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 727 u32 dst_addr, dma_addr_t phy_addr, 728 u32 byte_cnt) 729 { 730 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 731 unsigned long flags; 732 int ret; 733 734 trans_pcie->ucode_write_complete = false; 735 736 if (!iwl_trans_grab_nic_access(trans, &flags)) 737 return -EIO; 738 739 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 740 byte_cnt); 741 iwl_trans_release_nic_access(trans, &flags); 742 743 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 744 trans_pcie->ucode_write_complete, 5 * HZ); 745 if (!ret) { 746 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 747 iwl_trans_pcie_dump_regs(trans); 748 return -ETIMEDOUT; 749 } 750 751 return 0; 752 } 753 754 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 755 const struct fw_desc *section) 756 { 757 u8 *v_addr; 758 dma_addr_t p_addr; 759 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 760 int ret = 0; 761 762 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 763 section_num); 764 765 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 766 GFP_KERNEL | __GFP_NOWARN); 767 if (!v_addr) { 768 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 769 chunk_sz = PAGE_SIZE; 770 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 771 &p_addr, GFP_KERNEL); 772 if (!v_addr) 773 return -ENOMEM; 774 } 775 776 for (offset = 0; offset < section->len; offset += chunk_sz) { 777 u32 copy_size, dst_addr; 778 bool extended_addr = false; 779 780 copy_size = min_t(u32, chunk_sz, section->len - offset); 781 dst_addr = section->offset + offset; 782 783 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 784 dst_addr <= IWL_FW_MEM_EXTENDED_END) 785 extended_addr = true; 786 787 if (extended_addr) 788 iwl_set_bits_prph(trans, LMPM_CHICK, 789 LMPM_CHICK_EXTENDED_ADDR_SPACE); 790 791 memcpy(v_addr, (u8 *)section->data + offset, copy_size); 792 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 793 copy_size); 794 795 if (extended_addr) 796 iwl_clear_bits_prph(trans, LMPM_CHICK, 797 LMPM_CHICK_EXTENDED_ADDR_SPACE); 798 799 if (ret) { 800 IWL_ERR(trans, 801 "Could not load the [%d] uCode section\n", 802 section_num); 803 break; 804 } 805 } 806 807 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 808 return ret; 809 } 810 811 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 812 const struct fw_img *image, 813 int cpu, 814 int *first_ucode_section) 815 { 816 int shift_param; 817 int i, ret = 0, sec_num = 0x1; 818 u32 val, last_read_idx = 0; 819 820 if (cpu == 1) { 821 shift_param = 0; 822 *first_ucode_section = 0; 823 } else { 824 shift_param = 16; 825 (*first_ucode_section)++; 826 } 827 828 for (i = *first_ucode_section; i < image->num_sec; i++) { 829 last_read_idx = i; 830 831 /* 832 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 833 * CPU1 to CPU2. 834 * PAGING_SEPARATOR_SECTION delimiter - separate between 835 * CPU2 non paged to CPU2 paging sec. 836 */ 837 if (!image->sec[i].data || 838 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 839 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 840 IWL_DEBUG_FW(trans, 841 "Break since Data not valid or Empty section, sec = %d\n", 842 i); 843 break; 844 } 845 846 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 847 if (ret) 848 return ret; 849 850 /* Notify ucode of loaded section number and status */ 851 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 852 val = val | (sec_num << shift_param); 853 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 854 855 sec_num = (sec_num << 1) | 0x1; 856 } 857 858 *first_ucode_section = last_read_idx; 859 860 iwl_enable_interrupts(trans); 861 862 if (trans->cfg->use_tfh) { 863 if (cpu == 1) 864 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 865 0xFFFF); 866 else 867 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 868 0xFFFFFFFF); 869 } else { 870 if (cpu == 1) 871 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 872 0xFFFF); 873 else 874 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 875 0xFFFFFFFF); 876 } 877 878 return 0; 879 } 880 881 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 882 const struct fw_img *image, 883 int cpu, 884 int *first_ucode_section) 885 { 886 int i, ret = 0; 887 u32 last_read_idx = 0; 888 889 if (cpu == 1) 890 *first_ucode_section = 0; 891 else 892 (*first_ucode_section)++; 893 894 for (i = *first_ucode_section; i < image->num_sec; i++) { 895 last_read_idx = i; 896 897 /* 898 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 899 * CPU1 to CPU2. 900 * PAGING_SEPARATOR_SECTION delimiter - separate between 901 * CPU2 non paged to CPU2 paging sec. 902 */ 903 if (!image->sec[i].data || 904 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 905 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 906 IWL_DEBUG_FW(trans, 907 "Break since Data not valid or Empty section, sec = %d\n", 908 i); 909 break; 910 } 911 912 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 913 if (ret) 914 return ret; 915 } 916 917 *first_ucode_section = last_read_idx; 918 919 return 0; 920 } 921 922 void iwl_pcie_apply_destination(struct iwl_trans *trans) 923 { 924 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 925 int i; 926 927 IWL_INFO(trans, "Applying debug destination %s\n", 928 get_fw_dbg_mode_string(dest->monitor_mode)); 929 930 if (dest->monitor_mode == EXTERNAL_MODE) 931 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 932 else 933 IWL_WARN(trans, "PCI should have external buffer debug\n"); 934 935 for (i = 0; i < trans->dbg_n_dest_reg; i++) { 936 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 937 u32 val = le32_to_cpu(dest->reg_ops[i].val); 938 939 switch (dest->reg_ops[i].op) { 940 case CSR_ASSIGN: 941 iwl_write32(trans, addr, val); 942 break; 943 case CSR_SETBIT: 944 iwl_set_bit(trans, addr, BIT(val)); 945 break; 946 case CSR_CLEARBIT: 947 iwl_clear_bit(trans, addr, BIT(val)); 948 break; 949 case PRPH_ASSIGN: 950 iwl_write_prph(trans, addr, val); 951 break; 952 case PRPH_SETBIT: 953 iwl_set_bits_prph(trans, addr, BIT(val)); 954 break; 955 case PRPH_CLEARBIT: 956 iwl_clear_bits_prph(trans, addr, BIT(val)); 957 break; 958 case PRPH_BLOCKBIT: 959 if (iwl_read_prph(trans, addr) & BIT(val)) { 960 IWL_ERR(trans, 961 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 962 val, addr); 963 goto monitor; 964 } 965 break; 966 default: 967 IWL_ERR(trans, "FW debug - unknown OP %d\n", 968 dest->reg_ops[i].op); 969 break; 970 } 971 } 972 973 monitor: 974 if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { 975 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 976 trans->fw_mon[0].physical >> dest->base_shift); 977 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 978 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 979 (trans->fw_mon[0].physical + 980 trans->fw_mon[0].size - 256) >> 981 dest->end_shift); 982 else 983 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 984 (trans->fw_mon[0].physical + 985 trans->fw_mon[0].size) >> 986 dest->end_shift); 987 } 988 } 989 990 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 991 const struct fw_img *image) 992 { 993 int ret = 0; 994 int first_ucode_section; 995 996 IWL_DEBUG_FW(trans, "working with %s CPU\n", 997 image->is_dual_cpus ? "Dual" : "Single"); 998 999 /* load to FW the binary non secured sections of CPU1 */ 1000 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1001 if (ret) 1002 return ret; 1003 1004 if (image->is_dual_cpus) { 1005 /* set CPU2 header address */ 1006 iwl_write_prph(trans, 1007 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1008 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1009 1010 /* load to FW the binary sections of CPU2 */ 1011 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1012 &first_ucode_section); 1013 if (ret) 1014 return ret; 1015 } 1016 1017 /* supported for 7000 only for the moment */ 1018 if (iwlwifi_mod_params.fw_monitor && 1019 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1020 iwl_pcie_alloc_fw_monitor(trans, 0); 1021 1022 if (trans->fw_mon[0].size) { 1023 iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1024 trans->fw_mon[0].physical >> 4); 1025 iwl_write_prph(trans, MON_BUFF_END_ADDR, 1026 (trans->fw_mon[0].physical + 1027 trans->fw_mon[0].size) >> 4); 1028 } 1029 } else if (trans->dbg_dest_tlv) { 1030 iwl_pcie_apply_destination(trans); 1031 } 1032 1033 iwl_enable_interrupts(trans); 1034 1035 /* release CPU reset */ 1036 iwl_write32(trans, CSR_RESET, 0); 1037 1038 return 0; 1039 } 1040 1041 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1042 const struct fw_img *image) 1043 { 1044 int ret = 0; 1045 int first_ucode_section; 1046 1047 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1048 image->is_dual_cpus ? "Dual" : "Single"); 1049 1050 if (trans->dbg_dest_tlv) 1051 iwl_pcie_apply_destination(trans); 1052 1053 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1054 iwl_read_prph(trans, WFPM_GP2)); 1055 1056 /* 1057 * Set default value. On resume reading the values that were 1058 * zeored can provide debug data on the resume flow. 1059 * This is for debugging only and has no functional impact. 1060 */ 1061 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1062 1063 /* configure the ucode to be ready to get the secured image */ 1064 /* release CPU reset */ 1065 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1066 1067 /* load to FW the binary Secured sections of CPU1 */ 1068 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1069 &first_ucode_section); 1070 if (ret) 1071 return ret; 1072 1073 /* load to FW the binary sections of CPU2 */ 1074 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1075 &first_ucode_section); 1076 } 1077 1078 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1079 { 1080 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1081 bool hw_rfkill = iwl_is_rfkill_set(trans); 1082 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083 bool report; 1084 1085 if (hw_rfkill) { 1086 set_bit(STATUS_RFKILL_HW, &trans->status); 1087 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1088 } else { 1089 clear_bit(STATUS_RFKILL_HW, &trans->status); 1090 if (trans_pcie->opmode_down) 1091 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1092 } 1093 1094 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1095 1096 if (prev != report) 1097 iwl_trans_pcie_rf_kill(trans, report); 1098 1099 return hw_rfkill; 1100 } 1101 1102 struct iwl_causes_list { 1103 u32 cause_num; 1104 u32 mask_reg; 1105 u8 addr; 1106 }; 1107 1108 static struct iwl_causes_list causes_list[] = { 1109 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1110 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1111 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1112 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1113 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1114 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1115 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1116 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1117 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1118 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1119 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1120 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1121 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1122 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1123 }; 1124 1125 static struct iwl_causes_list causes_list_v2[] = { 1126 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 1127 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 1128 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 1129 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 1130 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 1131 {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1132 {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 1133 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 1134 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 1135 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 1136 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 1137 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 1138 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 1139 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 1140 }; 1141 1142 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1143 { 1144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1145 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1146 int i, arr_size = 1147 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 1148 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 1149 1150 /* 1151 * Access all non RX causes and map them to the default irq. 1152 * In case we are missing at least one interrupt vector, 1153 * the first interrupt vector will serve non-RX and FBQ causes. 1154 */ 1155 for (i = 0; i < arr_size; i++) { 1156 struct iwl_causes_list *causes = 1157 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 1158 causes_list : causes_list_v2; 1159 1160 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1161 iwl_clear_bit(trans, causes[i].mask_reg, 1162 causes[i].cause_num); 1163 } 1164 } 1165 1166 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1167 { 1168 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1169 u32 offset = 1170 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1171 u32 val, idx; 1172 1173 /* 1174 * The first RX queue - fallback queue, which is designated for 1175 * management frame, command responses etc, is always mapped to the 1176 * first interrupt vector. The other RX queues are mapped to 1177 * the other (N - 2) interrupt vectors. 1178 */ 1179 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1180 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1181 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1182 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1183 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1184 } 1185 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1186 1187 val = MSIX_FH_INT_CAUSES_Q(0); 1188 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1189 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1190 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1191 1192 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1193 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1194 } 1195 1196 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1197 { 1198 struct iwl_trans *trans = trans_pcie->trans; 1199 1200 if (!trans_pcie->msix_enabled) { 1201 if (trans->cfg->mq_rx_supported && 1202 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1203 iwl_write_prph(trans, UREG_CHICK, 1204 UREG_CHICK_MSI_ENABLE); 1205 return; 1206 } 1207 /* 1208 * The IVAR table needs to be configured again after reset, 1209 * but if the device is disabled, we can't write to 1210 * prph. 1211 */ 1212 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1213 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1214 1215 /* 1216 * Each cause from the causes list above and the RX causes is 1217 * represented as a byte in the IVAR table. The first nibble 1218 * represents the bound interrupt vector of the cause, the second 1219 * represents no auto clear for this cause. This will be set if its 1220 * interrupt vector is bound to serve other causes. 1221 */ 1222 iwl_pcie_map_rx_causes(trans); 1223 1224 iwl_pcie_map_non_rx_causes(trans); 1225 } 1226 1227 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1228 { 1229 struct iwl_trans *trans = trans_pcie->trans; 1230 1231 iwl_pcie_conf_msix_hw(trans_pcie); 1232 1233 if (!trans_pcie->msix_enabled) 1234 return; 1235 1236 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1237 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1238 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1239 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1240 } 1241 1242 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1243 { 1244 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1245 1246 lockdep_assert_held(&trans_pcie->mutex); 1247 1248 if (trans_pcie->is_down) 1249 return; 1250 1251 trans_pcie->is_down = true; 1252 1253 /* Stop dbgc before stopping device */ 1254 _iwl_fw_dbg_stop_recording(trans, NULL); 1255 1256 /* tell the device to stop sending interrupts */ 1257 iwl_disable_interrupts(trans); 1258 1259 /* device going down, Stop using ICT table */ 1260 iwl_pcie_disable_ict(trans); 1261 1262 /* 1263 * If a HW restart happens during firmware loading, 1264 * then the firmware loading might call this function 1265 * and later it might be called again due to the 1266 * restart. So don't process again if the device is 1267 * already dead. 1268 */ 1269 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1270 IWL_DEBUG_INFO(trans, 1271 "DEVICE_ENABLED bit was set and is now cleared\n"); 1272 iwl_pcie_tx_stop(trans); 1273 iwl_pcie_rx_stop(trans); 1274 1275 /* Power-down device's busmaster DMA clocks */ 1276 if (!trans->cfg->apmg_not_supported) { 1277 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1278 APMG_CLK_VAL_DMA_CLK_RQT); 1279 udelay(5); 1280 } 1281 } 1282 1283 /* Make sure (redundant) we've released our request to stay awake */ 1284 iwl_clear_bit(trans, CSR_GP_CNTRL, 1285 BIT(trans->cfg->csr->flag_mac_access_req)); 1286 1287 /* Stop the device, and put it in low power state */ 1288 iwl_pcie_apm_stop(trans, false); 1289 1290 iwl_trans_pcie_sw_reset(trans); 1291 1292 /* 1293 * Upon stop, the IVAR table gets erased, so msi-x won't 1294 * work. This causes a bug in RF-KILL flows, since the interrupt 1295 * that enables radio won't fire on the correct irq, and the 1296 * driver won't be able to handle the interrupt. 1297 * Configure the IVAR table again after reset. 1298 */ 1299 iwl_pcie_conf_msix_hw(trans_pcie); 1300 1301 /* 1302 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1303 * This is a bug in certain verions of the hardware. 1304 * Certain devices also keep sending HW RF kill interrupt all 1305 * the time, unless the interrupt is ACKed even if the interrupt 1306 * should be masked. Re-ACK all the interrupts here. 1307 */ 1308 iwl_disable_interrupts(trans); 1309 1310 /* clear all status bits */ 1311 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1312 clear_bit(STATUS_INT_ENABLED, &trans->status); 1313 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1314 1315 /* 1316 * Even if we stop the HW, we still want the RF kill 1317 * interrupt 1318 */ 1319 iwl_enable_rfkill_int(trans); 1320 1321 /* re-take ownership to prevent other users from stealing the device */ 1322 iwl_pcie_prepare_card_hw(trans); 1323 } 1324 1325 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1326 { 1327 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1328 1329 if (trans_pcie->msix_enabled) { 1330 int i; 1331 1332 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1333 synchronize_irq(trans_pcie->msix_entries[i].vector); 1334 } else { 1335 synchronize_irq(trans_pcie->pci_dev->irq); 1336 } 1337 } 1338 1339 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1340 const struct fw_img *fw, bool run_in_rfkill) 1341 { 1342 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1343 bool hw_rfkill; 1344 int ret; 1345 1346 /* This may fail if AMT took ownership of the device */ 1347 if (iwl_pcie_prepare_card_hw(trans)) { 1348 IWL_WARN(trans, "Exit HW not ready\n"); 1349 ret = -EIO; 1350 goto out; 1351 } 1352 1353 iwl_enable_rfkill_int(trans); 1354 1355 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1356 1357 /* 1358 * We enabled the RF-Kill interrupt and the handler may very 1359 * well be running. Disable the interrupts to make sure no other 1360 * interrupt can be fired. 1361 */ 1362 iwl_disable_interrupts(trans); 1363 1364 /* Make sure it finished running */ 1365 iwl_pcie_synchronize_irqs(trans); 1366 1367 mutex_lock(&trans_pcie->mutex); 1368 1369 /* If platform's RF_KILL switch is NOT set to KILL */ 1370 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1371 if (hw_rfkill && !run_in_rfkill) { 1372 ret = -ERFKILL; 1373 goto out; 1374 } 1375 1376 /* Someone called stop_device, don't try to start_fw */ 1377 if (trans_pcie->is_down) { 1378 IWL_WARN(trans, 1379 "Can't start_fw since the HW hasn't been started\n"); 1380 ret = -EIO; 1381 goto out; 1382 } 1383 1384 /* make sure rfkill handshake bits are cleared */ 1385 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1386 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1387 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1388 1389 /* clear (again), then enable host interrupts */ 1390 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1391 1392 ret = iwl_pcie_nic_init(trans); 1393 if (ret) { 1394 IWL_ERR(trans, "Unable to init nic\n"); 1395 goto out; 1396 } 1397 1398 /* 1399 * Now, we load the firmware and don't want to be interrupted, even 1400 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1401 * FH_TX interrupt which is needed to load the firmware). If the 1402 * RF-Kill switch is toggled, we will find out after having loaded 1403 * the firmware and return the proper value to the caller. 1404 */ 1405 iwl_enable_fw_load_int(trans); 1406 1407 /* really make sure rfkill handshake bits are cleared */ 1408 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1409 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1410 1411 /* Load the given image to the HW */ 1412 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1413 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1414 else 1415 ret = iwl_pcie_load_given_ucode(trans, fw); 1416 1417 /* re-check RF-Kill state since we may have missed the interrupt */ 1418 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1419 if (hw_rfkill && !run_in_rfkill) 1420 ret = -ERFKILL; 1421 1422 out: 1423 mutex_unlock(&trans_pcie->mutex); 1424 return ret; 1425 } 1426 1427 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1428 { 1429 iwl_pcie_reset_ict(trans); 1430 iwl_pcie_tx_start(trans, scd_addr); 1431 } 1432 1433 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1434 bool was_in_rfkill) 1435 { 1436 bool hw_rfkill; 1437 1438 /* 1439 * Check again since the RF kill state may have changed while 1440 * all the interrupts were disabled, in this case we couldn't 1441 * receive the RF kill interrupt and update the state in the 1442 * op_mode. 1443 * Don't call the op_mode if the rkfill state hasn't changed. 1444 * This allows the op_mode to call stop_device from the rfkill 1445 * notification without endless recursion. Under very rare 1446 * circumstances, we might have a small recursion if the rfkill 1447 * state changed exactly now while we were called from stop_device. 1448 * This is very unlikely but can happen and is supported. 1449 */ 1450 hw_rfkill = iwl_is_rfkill_set(trans); 1451 if (hw_rfkill) { 1452 set_bit(STATUS_RFKILL_HW, &trans->status); 1453 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1454 } else { 1455 clear_bit(STATUS_RFKILL_HW, &trans->status); 1456 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1457 } 1458 if (hw_rfkill != was_in_rfkill) 1459 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1460 } 1461 1462 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1463 { 1464 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1465 bool was_in_rfkill; 1466 1467 mutex_lock(&trans_pcie->mutex); 1468 trans_pcie->opmode_down = true; 1469 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1470 _iwl_trans_pcie_stop_device(trans, low_power); 1471 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1472 mutex_unlock(&trans_pcie->mutex); 1473 } 1474 1475 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1476 { 1477 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1478 IWL_TRANS_GET_PCIE_TRANS(trans); 1479 1480 lockdep_assert_held(&trans_pcie->mutex); 1481 1482 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1483 state ? "disabled" : "enabled"); 1484 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1485 if (trans->cfg->gen2) 1486 _iwl_trans_pcie_gen2_stop_device(trans, true); 1487 else 1488 _iwl_trans_pcie_stop_device(trans, true); 1489 } 1490 } 1491 1492 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1493 bool reset) 1494 { 1495 if (!reset) { 1496 /* Enable persistence mode to avoid reset */ 1497 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1498 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1499 } 1500 1501 iwl_disable_interrupts(trans); 1502 1503 /* 1504 * in testing mode, the host stays awake and the 1505 * hardware won't be reset (not even partially) 1506 */ 1507 if (test) 1508 return; 1509 1510 iwl_pcie_disable_ict(trans); 1511 1512 iwl_pcie_synchronize_irqs(trans); 1513 1514 iwl_clear_bit(trans, CSR_GP_CNTRL, 1515 BIT(trans->cfg->csr->flag_mac_access_req)); 1516 iwl_clear_bit(trans, CSR_GP_CNTRL, 1517 BIT(trans->cfg->csr->flag_init_done)); 1518 1519 iwl_pcie_enable_rx_wake(trans, false); 1520 1521 if (reset) { 1522 /* 1523 * reset TX queues -- some of their registers reset during S3 1524 * so if we don't reset everything here the D3 image would try 1525 * to execute some invalid memory upon resume 1526 */ 1527 iwl_trans_pcie_tx_reset(trans); 1528 } 1529 1530 iwl_pcie_set_pwr(trans, true); 1531 } 1532 1533 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1534 enum iwl_d3_status *status, 1535 bool test, bool reset) 1536 { 1537 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1538 u32 val; 1539 int ret; 1540 1541 if (test) { 1542 iwl_enable_interrupts(trans); 1543 *status = IWL_D3_STATUS_ALIVE; 1544 return 0; 1545 } 1546 1547 iwl_pcie_enable_rx_wake(trans, true); 1548 1549 iwl_set_bit(trans, CSR_GP_CNTRL, 1550 BIT(trans->cfg->csr->flag_mac_access_req)); 1551 iwl_set_bit(trans, CSR_GP_CNTRL, 1552 BIT(trans->cfg->csr->flag_init_done)); 1553 1554 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1555 udelay(2); 1556 1557 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1558 BIT(trans->cfg->csr->flag_mac_clock_ready), 1559 BIT(trans->cfg->csr->flag_mac_clock_ready), 1560 25000); 1561 if (ret < 0) { 1562 IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1563 return ret; 1564 } 1565 1566 /* 1567 * Reconfigure IVAR table in case of MSIX or reset ict table in 1568 * MSI mode since HW reset erased it. 1569 * Also enables interrupts - none will happen as 1570 * the device doesn't know we're waking it up, only when 1571 * the opmode actually tells it after this call. 1572 */ 1573 iwl_pcie_conf_msix_hw(trans_pcie); 1574 if (!trans_pcie->msix_enabled) 1575 iwl_pcie_reset_ict(trans); 1576 iwl_enable_interrupts(trans); 1577 1578 iwl_pcie_set_pwr(trans, false); 1579 1580 if (!reset) { 1581 iwl_clear_bit(trans, CSR_GP_CNTRL, 1582 BIT(trans->cfg->csr->flag_mac_access_req)); 1583 } else { 1584 iwl_trans_pcie_tx_reset(trans); 1585 1586 ret = iwl_pcie_rx_init(trans); 1587 if (ret) { 1588 IWL_ERR(trans, 1589 "Failed to resume the device (RX reset)\n"); 1590 return ret; 1591 } 1592 } 1593 1594 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1595 iwl_read_prph(trans, WFPM_GP2)); 1596 1597 val = iwl_read32(trans, CSR_RESET); 1598 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1599 *status = IWL_D3_STATUS_RESET; 1600 else 1601 *status = IWL_D3_STATUS_ALIVE; 1602 1603 return 0; 1604 } 1605 1606 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1607 struct iwl_trans *trans) 1608 { 1609 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1610 int max_irqs, num_irqs, i, ret; 1611 u16 pci_cmd; 1612 1613 if (!trans->cfg->mq_rx_supported) 1614 goto enable_msi; 1615 1616 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 1617 for (i = 0; i < max_irqs; i++) 1618 trans_pcie->msix_entries[i].entry = i; 1619 1620 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1621 MSIX_MIN_INTERRUPT_VECTORS, 1622 max_irqs); 1623 if (num_irqs < 0) { 1624 IWL_DEBUG_INFO(trans, 1625 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1626 num_irqs); 1627 goto enable_msi; 1628 } 1629 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1630 1631 IWL_DEBUG_INFO(trans, 1632 "MSI-X enabled. %d interrupt vectors were allocated\n", 1633 num_irqs); 1634 1635 /* 1636 * In case the OS provides fewer interrupts than requested, different 1637 * causes will share the same interrupt vector as follows: 1638 * One interrupt less: non rx causes shared with FBQ. 1639 * Two interrupts less: non rx causes shared with FBQ and RSS. 1640 * More than two interrupts: we will use fewer RSS queues. 1641 */ 1642 if (num_irqs <= max_irqs - 2) { 1643 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1644 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1645 IWL_SHARED_IRQ_FIRST_RSS; 1646 } else if (num_irqs == max_irqs - 1) { 1647 trans_pcie->trans->num_rx_queues = num_irqs; 1648 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1649 } else { 1650 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1651 } 1652 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1653 1654 trans_pcie->alloc_vecs = num_irqs; 1655 trans_pcie->msix_enabled = true; 1656 return; 1657 1658 enable_msi: 1659 ret = pci_enable_msi(pdev); 1660 if (ret) { 1661 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1662 /* enable rfkill interrupt: hw bug w/a */ 1663 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1664 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1665 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1666 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1667 } 1668 } 1669 } 1670 1671 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1672 { 1673 int iter_rx_q, i, ret, cpu, offset; 1674 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1675 1676 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1677 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1678 offset = 1 + i; 1679 for (; i < iter_rx_q ; i++) { 1680 /* 1681 * Get the cpu prior to the place to search 1682 * (i.e. return will be > i - 1). 1683 */ 1684 cpu = cpumask_next(i - offset, cpu_online_mask); 1685 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1686 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1687 &trans_pcie->affinity_mask[i]); 1688 if (ret) 1689 IWL_ERR(trans_pcie->trans, 1690 "Failed to set affinity mask for IRQ %d\n", 1691 i); 1692 } 1693 } 1694 1695 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1696 struct iwl_trans_pcie *trans_pcie) 1697 { 1698 int i; 1699 1700 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1701 int ret; 1702 struct msix_entry *msix_entry; 1703 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1704 1705 if (!qname) 1706 return -ENOMEM; 1707 1708 msix_entry = &trans_pcie->msix_entries[i]; 1709 ret = devm_request_threaded_irq(&pdev->dev, 1710 msix_entry->vector, 1711 iwl_pcie_msix_isr, 1712 (i == trans_pcie->def_irq) ? 1713 iwl_pcie_irq_msix_handler : 1714 iwl_pcie_irq_rx_msix_handler, 1715 IRQF_SHARED, 1716 qname, 1717 msix_entry); 1718 if (ret) { 1719 IWL_ERR(trans_pcie->trans, 1720 "Error allocating IRQ %d\n", i); 1721 1722 return ret; 1723 } 1724 } 1725 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1726 1727 return 0; 1728 } 1729 1730 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1731 { 1732 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1733 u32 hpm; 1734 int err; 1735 1736 lockdep_assert_held(&trans_pcie->mutex); 1737 1738 err = iwl_pcie_prepare_card_hw(trans); 1739 if (err) { 1740 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1741 return err; 1742 } 1743 1744 hpm = iwl_trans_read_prph(trans, HPM_DEBUG); 1745 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1746 if (iwl_trans_read_prph(trans, PREG_PRPH_WPROT_0) & 1747 PREG_WFPM_ACCESS) { 1748 IWL_ERR(trans, 1749 "Error, can not clear persistence bit\n"); 1750 return -EPERM; 1751 } 1752 iwl_trans_write_prph(trans, HPM_DEBUG, hpm & ~PERSISTENCE_BIT); 1753 } 1754 1755 iwl_trans_pcie_sw_reset(trans); 1756 1757 err = iwl_pcie_apm_init(trans); 1758 if (err) 1759 return err; 1760 1761 iwl_pcie_init_msix(trans_pcie); 1762 1763 /* From now on, the op_mode will be kept updated about RF kill state */ 1764 iwl_enable_rfkill_int(trans); 1765 1766 trans_pcie->opmode_down = false; 1767 1768 /* Set is_down to false here so that...*/ 1769 trans_pcie->is_down = false; 1770 1771 /* ...rfkill can call stop_device and set it false if needed */ 1772 iwl_pcie_check_hw_rf_kill(trans); 1773 1774 /* Make sure we sync here, because we'll need full access later */ 1775 if (low_power) 1776 pm_runtime_resume(trans->dev); 1777 1778 return 0; 1779 } 1780 1781 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1782 { 1783 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1784 int ret; 1785 1786 mutex_lock(&trans_pcie->mutex); 1787 ret = _iwl_trans_pcie_start_hw(trans, low_power); 1788 mutex_unlock(&trans_pcie->mutex); 1789 1790 return ret; 1791 } 1792 1793 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1794 { 1795 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1796 1797 mutex_lock(&trans_pcie->mutex); 1798 1799 /* disable interrupts - don't enable HW RF kill interrupt */ 1800 iwl_disable_interrupts(trans); 1801 1802 iwl_pcie_apm_stop(trans, true); 1803 1804 iwl_disable_interrupts(trans); 1805 1806 iwl_pcie_disable_ict(trans); 1807 1808 mutex_unlock(&trans_pcie->mutex); 1809 1810 iwl_pcie_synchronize_irqs(trans); 1811 } 1812 1813 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1814 { 1815 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1816 } 1817 1818 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1819 { 1820 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1821 } 1822 1823 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1824 { 1825 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1826 } 1827 1828 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1829 { 1830 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 1831 return 0x00FFFFFF; 1832 else 1833 return 0x000FFFFF; 1834 } 1835 1836 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1837 { 1838 u32 mask = iwl_trans_pcie_prph_msk(trans); 1839 1840 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1841 ((reg & mask) | (3 << 24))); 1842 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1843 } 1844 1845 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1846 u32 val) 1847 { 1848 u32 mask = iwl_trans_pcie_prph_msk(trans); 1849 1850 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1851 ((addr & mask) | (3 << 24))); 1852 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1853 } 1854 1855 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1856 const struct iwl_trans_config *trans_cfg) 1857 { 1858 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1859 1860 trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1861 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1862 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1863 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1864 trans_pcie->n_no_reclaim_cmds = 0; 1865 else 1866 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1867 if (trans_pcie->n_no_reclaim_cmds) 1868 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1869 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1870 1871 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 1872 trans_pcie->rx_page_order = 1873 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1874 1875 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1876 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1877 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1878 1879 trans_pcie->page_offs = trans_cfg->cb_data_offs; 1880 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1881 1882 trans->command_groups = trans_cfg->command_groups; 1883 trans->command_groups_size = trans_cfg->command_groups_size; 1884 1885 /* Initialize NAPI here - it should be before registering to mac80211 1886 * in the opmode but after the HW struct is allocated. 1887 * As this function may be called again in some corner cases don't 1888 * do anything if NAPI was already initialized. 1889 */ 1890 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1891 init_dummy_netdev(&trans_pcie->napi_dev); 1892 } 1893 1894 void iwl_trans_pcie_free(struct iwl_trans *trans) 1895 { 1896 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1897 int i; 1898 1899 iwl_pcie_synchronize_irqs(trans); 1900 1901 if (trans->cfg->gen2) 1902 iwl_pcie_gen2_tx_free(trans); 1903 else 1904 iwl_pcie_tx_free(trans); 1905 iwl_pcie_rx_free(trans); 1906 1907 if (trans_pcie->rba.alloc_wq) { 1908 destroy_workqueue(trans_pcie->rba.alloc_wq); 1909 trans_pcie->rba.alloc_wq = NULL; 1910 } 1911 1912 if (trans_pcie->msix_enabled) { 1913 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1914 irq_set_affinity_hint( 1915 trans_pcie->msix_entries[i].vector, 1916 NULL); 1917 } 1918 1919 trans_pcie->msix_enabled = false; 1920 } else { 1921 iwl_pcie_free_ict(trans); 1922 } 1923 1924 iwl_pcie_free_fw_monitor(trans); 1925 1926 for_each_possible_cpu(i) { 1927 struct iwl_tso_hdr_page *p = 1928 per_cpu_ptr(trans_pcie->tso_hdr_page, i); 1929 1930 if (p->page) 1931 __free_page(p->page); 1932 } 1933 1934 free_percpu(trans_pcie->tso_hdr_page); 1935 mutex_destroy(&trans_pcie->mutex); 1936 iwl_trans_free(trans); 1937 } 1938 1939 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1940 { 1941 if (state) 1942 set_bit(STATUS_TPOWER_PMI, &trans->status); 1943 else 1944 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1945 } 1946 1947 struct iwl_trans_pcie_removal { 1948 struct pci_dev *pdev; 1949 struct work_struct work; 1950 }; 1951 1952 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 1953 { 1954 struct iwl_trans_pcie_removal *removal = 1955 container_of(wk, struct iwl_trans_pcie_removal, work); 1956 struct pci_dev *pdev = removal->pdev; 1957 char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 1958 1959 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 1960 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 1961 pci_lock_rescan_remove(); 1962 pci_dev_put(pdev); 1963 pci_stop_and_remove_bus_device(pdev); 1964 pci_unlock_rescan_remove(); 1965 1966 kfree(removal); 1967 module_put(THIS_MODULE); 1968 } 1969 1970 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1971 unsigned long *flags) 1972 { 1973 int ret; 1974 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1975 1976 spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1977 1978 if (trans_pcie->cmd_hold_nic_awake) 1979 goto out; 1980 1981 /* this bit wakes up the NIC */ 1982 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1983 BIT(trans->cfg->csr->flag_mac_access_req)); 1984 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1985 udelay(2); 1986 1987 /* 1988 * These bits say the device is running, and should keep running for 1989 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1990 * but they do not indicate that embedded SRAM is restored yet; 1991 * HW with volatile SRAM must save/restore contents to/from 1992 * host DRAM when sleeping/waking for power-saving. 1993 * Each direction takes approximately 1/4 millisecond; with this 1994 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1995 * series of register accesses are expected (e.g. reading Event Log), 1996 * to keep device from sleeping. 1997 * 1998 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1999 * SRAM is okay/restored. We don't check that here because this call 2000 * is just for hardware register access; but GP1 MAC_SLEEP 2001 * check is a good idea before accessing the SRAM of HW with 2002 * volatile SRAM (e.g. reading Event Log). 2003 * 2004 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2005 * and do not save/restore SRAM when power cycling. 2006 */ 2007 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2008 BIT(trans->cfg->csr->flag_val_mac_access_en), 2009 (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2010 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2011 if (unlikely(ret < 0)) { 2012 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2013 2014 WARN_ONCE(1, 2015 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2016 cntrl); 2017 2018 iwl_trans_pcie_dump_regs(trans); 2019 2020 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 2021 struct iwl_trans_pcie_removal *removal; 2022 2023 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2024 goto err; 2025 2026 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2027 2028 /* 2029 * get a module reference to avoid doing this 2030 * while unloading anyway and to avoid 2031 * scheduling a work with code that's being 2032 * removed. 2033 */ 2034 if (!try_module_get(THIS_MODULE)) { 2035 IWL_ERR(trans, 2036 "Module is being unloaded - abort\n"); 2037 goto err; 2038 } 2039 2040 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2041 if (!removal) { 2042 module_put(THIS_MODULE); 2043 goto err; 2044 } 2045 /* 2046 * we don't need to clear this flag, because 2047 * the trans will be freed and reallocated. 2048 */ 2049 set_bit(STATUS_TRANS_DEAD, &trans->status); 2050 2051 removal->pdev = to_pci_dev(trans->dev); 2052 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2053 pci_dev_get(removal->pdev); 2054 schedule_work(&removal->work); 2055 } else { 2056 iwl_write32(trans, CSR_RESET, 2057 CSR_RESET_REG_FLAG_FORCE_NMI); 2058 } 2059 2060 err: 2061 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2062 return false; 2063 } 2064 2065 out: 2066 /* 2067 * Fool sparse by faking we release the lock - sparse will 2068 * track nic_access anyway. 2069 */ 2070 __release(&trans_pcie->reg_lock); 2071 return true; 2072 } 2073 2074 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2075 unsigned long *flags) 2076 { 2077 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2078 2079 lockdep_assert_held(&trans_pcie->reg_lock); 2080 2081 /* 2082 * Fool sparse by faking we acquiring the lock - sparse will 2083 * track nic_access anyway. 2084 */ 2085 __acquire(&trans_pcie->reg_lock); 2086 2087 if (trans_pcie->cmd_hold_nic_awake) 2088 goto out; 2089 2090 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2091 BIT(trans->cfg->csr->flag_mac_access_req)); 2092 /* 2093 * Above we read the CSR_GP_CNTRL register, which will flush 2094 * any previous writes, but we need the write that clears the 2095 * MAC_ACCESS_REQ bit to be performed before any other writes 2096 * scheduled on different CPUs (after we drop reg_lock). 2097 */ 2098 mmiowb(); 2099 out: 2100 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2101 } 2102 2103 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2104 void *buf, int dwords) 2105 { 2106 unsigned long flags; 2107 int offs, ret = 0; 2108 u32 *vals = buf; 2109 2110 if (iwl_trans_grab_nic_access(trans, &flags)) { 2111 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2112 for (offs = 0; offs < dwords; offs++) 2113 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2114 iwl_trans_release_nic_access(trans, &flags); 2115 } else { 2116 ret = -EBUSY; 2117 } 2118 return ret; 2119 } 2120 2121 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2122 const void *buf, int dwords) 2123 { 2124 unsigned long flags; 2125 int offs, ret = 0; 2126 const u32 *vals = buf; 2127 2128 if (iwl_trans_grab_nic_access(trans, &flags)) { 2129 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2130 for (offs = 0; offs < dwords; offs++) 2131 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2132 vals ? vals[offs] : 0); 2133 iwl_trans_release_nic_access(trans, &flags); 2134 } else { 2135 ret = -EBUSY; 2136 } 2137 return ret; 2138 } 2139 2140 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2141 unsigned long txqs, 2142 bool freeze) 2143 { 2144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2145 int queue; 2146 2147 for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2148 struct iwl_txq *txq = trans_pcie->txq[queue]; 2149 unsigned long now; 2150 2151 spin_lock_bh(&txq->lock); 2152 2153 now = jiffies; 2154 2155 if (txq->frozen == freeze) 2156 goto next_queue; 2157 2158 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2159 freeze ? "Freezing" : "Waking", queue); 2160 2161 txq->frozen = freeze; 2162 2163 if (txq->read_ptr == txq->write_ptr) 2164 goto next_queue; 2165 2166 if (freeze) { 2167 if (unlikely(time_after(now, 2168 txq->stuck_timer.expires))) { 2169 /* 2170 * The timer should have fired, maybe it is 2171 * spinning right now on the lock. 2172 */ 2173 goto next_queue; 2174 } 2175 /* remember how long until the timer fires */ 2176 txq->frozen_expiry_remainder = 2177 txq->stuck_timer.expires - now; 2178 del_timer(&txq->stuck_timer); 2179 goto next_queue; 2180 } 2181 2182 /* 2183 * Wake a non-empty queue -> arm timer with the 2184 * remainder before it froze 2185 */ 2186 mod_timer(&txq->stuck_timer, 2187 now + txq->frozen_expiry_remainder); 2188 2189 next_queue: 2190 spin_unlock_bh(&txq->lock); 2191 } 2192 } 2193 2194 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2195 { 2196 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2197 int i; 2198 2199 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2200 struct iwl_txq *txq = trans_pcie->txq[i]; 2201 2202 if (i == trans_pcie->cmd_queue) 2203 continue; 2204 2205 spin_lock_bh(&txq->lock); 2206 2207 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2208 txq->block--; 2209 if (!txq->block) { 2210 iwl_write32(trans, HBUS_TARG_WRPTR, 2211 txq->write_ptr | (i << 8)); 2212 } 2213 } else if (block) { 2214 txq->block++; 2215 } 2216 2217 spin_unlock_bh(&txq->lock); 2218 } 2219 } 2220 2221 #define IWL_FLUSH_WAIT_MS 2000 2222 2223 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 2224 { 2225 u32 txq_id = txq->id; 2226 u32 status; 2227 bool active; 2228 u8 fifo; 2229 2230 if (trans->cfg->use_tfh) { 2231 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2232 txq->read_ptr, txq->write_ptr); 2233 /* TODO: access new SCD registers and dump them */ 2234 return; 2235 } 2236 2237 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2238 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2239 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 2240 2241 IWL_ERR(trans, 2242 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2243 txq_id, active ? "" : "in", fifo, 2244 jiffies_to_msecs(txq->wd_timeout), 2245 txq->read_ptr, txq->write_ptr, 2246 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2247 (trans->cfg->base_params->max_tfd_queue_size - 1), 2248 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2249 (trans->cfg->base_params->max_tfd_queue_size - 1), 2250 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 2251 } 2252 2253 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2254 struct iwl_trans_rxq_dma_data *data) 2255 { 2256 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2257 2258 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2259 return -EINVAL; 2260 2261 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2262 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2263 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2264 data->fr_bd_wid = 0; 2265 2266 return 0; 2267 } 2268 2269 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2270 { 2271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2272 struct iwl_txq *txq; 2273 unsigned long now = jiffies; 2274 u8 wr_ptr; 2275 2276 /* Make sure the NIC is still alive in the bus */ 2277 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2278 return -ENODEV; 2279 2280 if (!test_bit(txq_idx, trans_pcie->queue_used)) 2281 return -EINVAL; 2282 2283 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2284 txq = trans_pcie->txq[txq_idx]; 2285 wr_ptr = READ_ONCE(txq->write_ptr); 2286 2287 while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2288 !time_after(jiffies, 2289 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2290 u8 write_ptr = READ_ONCE(txq->write_ptr); 2291 2292 if (WARN_ONCE(wr_ptr != write_ptr, 2293 "WR pointer moved while flushing %d -> %d\n", 2294 wr_ptr, write_ptr)) 2295 return -ETIMEDOUT; 2296 usleep_range(1000, 2000); 2297 } 2298 2299 if (txq->read_ptr != txq->write_ptr) { 2300 IWL_ERR(trans, 2301 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2302 iwl_trans_pcie_log_scd_error(trans, txq); 2303 return -ETIMEDOUT; 2304 } 2305 2306 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2307 2308 return 0; 2309 } 2310 2311 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2312 { 2313 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2314 int cnt; 2315 int ret = 0; 2316 2317 /* waiting for all the tx frames complete might take a while */ 2318 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2319 2320 if (cnt == trans_pcie->cmd_queue) 2321 continue; 2322 if (!test_bit(cnt, trans_pcie->queue_used)) 2323 continue; 2324 if (!(BIT(cnt) & txq_bm)) 2325 continue; 2326 2327 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2328 if (ret) 2329 break; 2330 } 2331 2332 return ret; 2333 } 2334 2335 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2336 u32 mask, u32 value) 2337 { 2338 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2339 unsigned long flags; 2340 2341 spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2342 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2343 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2344 } 2345 2346 static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2347 { 2348 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2349 2350 if (iwlwifi_mod_params.d0i3_disable) 2351 return; 2352 2353 pm_runtime_get(&trans_pcie->pci_dev->dev); 2354 2355 #ifdef CONFIG_PM 2356 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2357 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2358 #endif /* CONFIG_PM */ 2359 } 2360 2361 static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2362 { 2363 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2364 2365 if (iwlwifi_mod_params.d0i3_disable) 2366 return; 2367 2368 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2369 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2370 2371 #ifdef CONFIG_PM 2372 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 2373 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 2374 #endif /* CONFIG_PM */ 2375 } 2376 2377 static const char *get_csr_string(int cmd) 2378 { 2379 #define IWL_CMD(x) case x: return #x 2380 switch (cmd) { 2381 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2382 IWL_CMD(CSR_INT_COALESCING); 2383 IWL_CMD(CSR_INT); 2384 IWL_CMD(CSR_INT_MASK); 2385 IWL_CMD(CSR_FH_INT_STATUS); 2386 IWL_CMD(CSR_GPIO_IN); 2387 IWL_CMD(CSR_RESET); 2388 IWL_CMD(CSR_GP_CNTRL); 2389 IWL_CMD(CSR_HW_REV); 2390 IWL_CMD(CSR_EEPROM_REG); 2391 IWL_CMD(CSR_EEPROM_GP); 2392 IWL_CMD(CSR_OTP_GP_REG); 2393 IWL_CMD(CSR_GIO_REG); 2394 IWL_CMD(CSR_GP_UCODE_REG); 2395 IWL_CMD(CSR_GP_DRIVER_REG); 2396 IWL_CMD(CSR_UCODE_DRV_GP1); 2397 IWL_CMD(CSR_UCODE_DRV_GP2); 2398 IWL_CMD(CSR_LED_REG); 2399 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2400 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2401 IWL_CMD(CSR_ANA_PLL_CFG); 2402 IWL_CMD(CSR_HW_REV_WA_REG); 2403 IWL_CMD(CSR_MONITOR_STATUS_REG); 2404 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2405 default: 2406 return "UNKNOWN"; 2407 } 2408 #undef IWL_CMD 2409 } 2410 2411 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2412 { 2413 int i; 2414 static const u32 csr_tbl[] = { 2415 CSR_HW_IF_CONFIG_REG, 2416 CSR_INT_COALESCING, 2417 CSR_INT, 2418 CSR_INT_MASK, 2419 CSR_FH_INT_STATUS, 2420 CSR_GPIO_IN, 2421 CSR_RESET, 2422 CSR_GP_CNTRL, 2423 CSR_HW_REV, 2424 CSR_EEPROM_REG, 2425 CSR_EEPROM_GP, 2426 CSR_OTP_GP_REG, 2427 CSR_GIO_REG, 2428 CSR_GP_UCODE_REG, 2429 CSR_GP_DRIVER_REG, 2430 CSR_UCODE_DRV_GP1, 2431 CSR_UCODE_DRV_GP2, 2432 CSR_LED_REG, 2433 CSR_DRAM_INT_TBL_REG, 2434 CSR_GIO_CHICKEN_BITS, 2435 CSR_ANA_PLL_CFG, 2436 CSR_MONITOR_STATUS_REG, 2437 CSR_HW_REV_WA_REG, 2438 CSR_DBG_HPET_MEM_REG 2439 }; 2440 IWL_ERR(trans, "CSR values:\n"); 2441 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2442 "CSR_INT_PERIODIC_REG)\n"); 2443 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2444 IWL_ERR(trans, " %25s: 0X%08x\n", 2445 get_csr_string(csr_tbl[i]), 2446 iwl_read32(trans, csr_tbl[i])); 2447 } 2448 } 2449 2450 #ifdef CONFIG_IWLWIFI_DEBUGFS 2451 /* create and remove of files */ 2452 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2453 if (!debugfs_create_file(#name, mode, parent, trans, \ 2454 &iwl_dbgfs_##name##_ops)) \ 2455 goto err; \ 2456 } while (0) 2457 2458 /* file operation */ 2459 #define DEBUGFS_READ_FILE_OPS(name) \ 2460 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2461 .read = iwl_dbgfs_##name##_read, \ 2462 .open = simple_open, \ 2463 .llseek = generic_file_llseek, \ 2464 }; 2465 2466 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2467 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2468 .write = iwl_dbgfs_##name##_write, \ 2469 .open = simple_open, \ 2470 .llseek = generic_file_llseek, \ 2471 }; 2472 2473 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2474 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2475 .write = iwl_dbgfs_##name##_write, \ 2476 .read = iwl_dbgfs_##name##_read, \ 2477 .open = simple_open, \ 2478 .llseek = generic_file_llseek, \ 2479 }; 2480 2481 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2482 char __user *user_buf, 2483 size_t count, loff_t *ppos) 2484 { 2485 struct iwl_trans *trans = file->private_data; 2486 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2487 struct iwl_txq *txq; 2488 char *buf; 2489 int pos = 0; 2490 int cnt; 2491 int ret; 2492 size_t bufsz; 2493 2494 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2495 2496 if (!trans_pcie->txq_memory) 2497 return -EAGAIN; 2498 2499 buf = kzalloc(bufsz, GFP_KERNEL); 2500 if (!buf) 2501 return -ENOMEM; 2502 2503 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2504 txq = trans_pcie->txq[cnt]; 2505 pos += scnprintf(buf + pos, bufsz - pos, 2506 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2507 cnt, txq->read_ptr, txq->write_ptr, 2508 !!test_bit(cnt, trans_pcie->queue_used), 2509 !!test_bit(cnt, trans_pcie->queue_stopped), 2510 txq->need_update, txq->frozen, 2511 (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2512 } 2513 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2514 kfree(buf); 2515 return ret; 2516 } 2517 2518 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2519 char __user *user_buf, 2520 size_t count, loff_t *ppos) 2521 { 2522 struct iwl_trans *trans = file->private_data; 2523 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2524 char *buf; 2525 int pos = 0, i, ret; 2526 size_t bufsz = sizeof(buf); 2527 2528 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2529 2530 if (!trans_pcie->rxq) 2531 return -EAGAIN; 2532 2533 buf = kzalloc(bufsz, GFP_KERNEL); 2534 if (!buf) 2535 return -ENOMEM; 2536 2537 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2538 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2539 2540 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2541 i); 2542 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2543 rxq->read); 2544 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2545 rxq->write); 2546 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2547 rxq->write_actual); 2548 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2549 rxq->need_update); 2550 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2551 rxq->free_count); 2552 if (rxq->rb_stts) { 2553 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2554 rxq)); 2555 pos += scnprintf(buf + pos, bufsz - pos, 2556 "\tclosed_rb_num: %u\n", 2557 r & 0x0FFF); 2558 } else { 2559 pos += scnprintf(buf + pos, bufsz - pos, 2560 "\tclosed_rb_num: Not Allocated\n"); 2561 } 2562 } 2563 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2564 kfree(buf); 2565 2566 return ret; 2567 } 2568 2569 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2570 char __user *user_buf, 2571 size_t count, loff_t *ppos) 2572 { 2573 struct iwl_trans *trans = file->private_data; 2574 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2575 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2576 2577 int pos = 0; 2578 char *buf; 2579 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2580 ssize_t ret; 2581 2582 buf = kzalloc(bufsz, GFP_KERNEL); 2583 if (!buf) 2584 return -ENOMEM; 2585 2586 pos += scnprintf(buf + pos, bufsz - pos, 2587 "Interrupt Statistics Report:\n"); 2588 2589 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2590 isr_stats->hw); 2591 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2592 isr_stats->sw); 2593 if (isr_stats->sw || isr_stats->hw) { 2594 pos += scnprintf(buf + pos, bufsz - pos, 2595 "\tLast Restarting Code: 0x%X\n", 2596 isr_stats->err_code); 2597 } 2598 #ifdef CONFIG_IWLWIFI_DEBUG 2599 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2600 isr_stats->sch); 2601 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2602 isr_stats->alive); 2603 #endif 2604 pos += scnprintf(buf + pos, bufsz - pos, 2605 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2606 2607 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2608 isr_stats->ctkill); 2609 2610 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2611 isr_stats->wakeup); 2612 2613 pos += scnprintf(buf + pos, bufsz - pos, 2614 "Rx command responses:\t\t %u\n", isr_stats->rx); 2615 2616 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2617 isr_stats->tx); 2618 2619 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2620 isr_stats->unhandled); 2621 2622 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2623 kfree(buf); 2624 return ret; 2625 } 2626 2627 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2628 const char __user *user_buf, 2629 size_t count, loff_t *ppos) 2630 { 2631 struct iwl_trans *trans = file->private_data; 2632 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2633 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2634 u32 reset_flag; 2635 int ret; 2636 2637 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2638 if (ret) 2639 return ret; 2640 if (reset_flag == 0) 2641 memset(isr_stats, 0, sizeof(*isr_stats)); 2642 2643 return count; 2644 } 2645 2646 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2647 const char __user *user_buf, 2648 size_t count, loff_t *ppos) 2649 { 2650 struct iwl_trans *trans = file->private_data; 2651 2652 iwl_pcie_dump_csr(trans); 2653 2654 return count; 2655 } 2656 2657 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2658 char __user *user_buf, 2659 size_t count, loff_t *ppos) 2660 { 2661 struct iwl_trans *trans = file->private_data; 2662 char *buf = NULL; 2663 ssize_t ret; 2664 2665 ret = iwl_dump_fh(trans, &buf); 2666 if (ret < 0) 2667 return ret; 2668 if (!buf) 2669 return -EINVAL; 2670 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2671 kfree(buf); 2672 return ret; 2673 } 2674 2675 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2676 char __user *user_buf, 2677 size_t count, loff_t *ppos) 2678 { 2679 struct iwl_trans *trans = file->private_data; 2680 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2681 char buf[100]; 2682 int pos; 2683 2684 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2685 trans_pcie->debug_rfkill, 2686 !(iwl_read32(trans, CSR_GP_CNTRL) & 2687 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2688 2689 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2690 } 2691 2692 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2693 const char __user *user_buf, 2694 size_t count, loff_t *ppos) 2695 { 2696 struct iwl_trans *trans = file->private_data; 2697 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2698 bool old = trans_pcie->debug_rfkill; 2699 int ret; 2700 2701 ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2702 if (ret) 2703 return ret; 2704 if (old == trans_pcie->debug_rfkill) 2705 return count; 2706 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2707 old, trans_pcie->debug_rfkill); 2708 iwl_pcie_handle_rfkill_irq(trans); 2709 2710 return count; 2711 } 2712 2713 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2714 struct file *file) 2715 { 2716 struct iwl_trans *trans = inode->i_private; 2717 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2718 2719 if (!trans->dbg_dest_tlv || 2720 trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) { 2721 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2722 return -ENOENT; 2723 } 2724 2725 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2726 return -EBUSY; 2727 2728 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2729 return simple_open(inode, file); 2730 } 2731 2732 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2733 struct file *file) 2734 { 2735 struct iwl_trans_pcie *trans_pcie = 2736 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2737 2738 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2739 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2740 return 0; 2741 } 2742 2743 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2744 void *buf, ssize_t *size, 2745 ssize_t *bytes_copied) 2746 { 2747 int buf_size_left = count - *bytes_copied; 2748 2749 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2750 if (*size > buf_size_left) 2751 *size = buf_size_left; 2752 2753 *size -= copy_to_user(user_buf, buf, *size); 2754 *bytes_copied += *size; 2755 2756 if (buf_size_left == *size) 2757 return true; 2758 return false; 2759 } 2760 2761 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2762 char __user *user_buf, 2763 size_t count, loff_t *ppos) 2764 { 2765 struct iwl_trans *trans = file->private_data; 2766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2767 void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf; 2768 struct cont_rec *data = &trans_pcie->fw_mon_data; 2769 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2770 ssize_t size, bytes_copied = 0; 2771 bool b_full; 2772 2773 if (trans->dbg_dest_tlv) { 2774 write_ptr_addr = 2775 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2776 wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2777 } else { 2778 write_ptr_addr = MON_BUFF_WRPTR; 2779 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2780 } 2781 2782 if (unlikely(!trans->dbg_rec_on)) 2783 return 0; 2784 2785 mutex_lock(&data->mutex); 2786 if (data->state == 2787 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2788 mutex_unlock(&data->mutex); 2789 return 0; 2790 } 2791 2792 /* write_ptr position in bytes rather then DW */ 2793 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2794 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2795 2796 if (data->prev_wrap_cnt == wrap_cnt) { 2797 size = write_ptr - data->prev_wr_ptr; 2798 curr_buf = cpu_addr + data->prev_wr_ptr; 2799 b_full = iwl_write_to_user_buf(user_buf, count, 2800 curr_buf, &size, 2801 &bytes_copied); 2802 data->prev_wr_ptr += size; 2803 2804 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2805 write_ptr < data->prev_wr_ptr) { 2806 size = trans->fw_mon[0].size - data->prev_wr_ptr; 2807 curr_buf = cpu_addr + data->prev_wr_ptr; 2808 b_full = iwl_write_to_user_buf(user_buf, count, 2809 curr_buf, &size, 2810 &bytes_copied); 2811 data->prev_wr_ptr += size; 2812 2813 if (!b_full) { 2814 size = write_ptr; 2815 b_full = iwl_write_to_user_buf(user_buf, count, 2816 cpu_addr, &size, 2817 &bytes_copied); 2818 data->prev_wr_ptr = size; 2819 data->prev_wrap_cnt++; 2820 } 2821 } else { 2822 if (data->prev_wrap_cnt == wrap_cnt - 1 && 2823 write_ptr > data->prev_wr_ptr) 2824 IWL_WARN(trans, 2825 "write pointer passed previous write pointer, start copying from the beginning\n"); 2826 else if (!unlikely(data->prev_wrap_cnt == 0 && 2827 data->prev_wr_ptr == 0)) 2828 IWL_WARN(trans, 2829 "monitor data is out of sync, start copying from the beginning\n"); 2830 2831 size = write_ptr; 2832 b_full = iwl_write_to_user_buf(user_buf, count, 2833 cpu_addr, &size, 2834 &bytes_copied); 2835 data->prev_wr_ptr = size; 2836 data->prev_wrap_cnt = wrap_cnt; 2837 } 2838 2839 mutex_unlock(&data->mutex); 2840 2841 return bytes_copied; 2842 } 2843 2844 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2845 DEBUGFS_READ_FILE_OPS(fh_reg); 2846 DEBUGFS_READ_FILE_OPS(rx_queue); 2847 DEBUGFS_READ_FILE_OPS(tx_queue); 2848 DEBUGFS_WRITE_FILE_OPS(csr); 2849 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2850 2851 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2852 .read = iwl_dbgfs_monitor_data_read, 2853 .open = iwl_dbgfs_monitor_data_open, 2854 .release = iwl_dbgfs_monitor_data_release, 2855 }; 2856 2857 /* Create the debugfs files and directories */ 2858 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2859 { 2860 struct dentry *dir = trans->dbgfs_dir; 2861 2862 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 2863 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 2864 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 2865 DEBUGFS_ADD_FILE(csr, dir, 0200); 2866 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 2867 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2868 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2869 return 0; 2870 2871 err: 2872 IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2873 return -ENOMEM; 2874 } 2875 2876 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2877 { 2878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2879 struct cont_rec *data = &trans_pcie->fw_mon_data; 2880 2881 mutex_lock(&data->mutex); 2882 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2883 mutex_unlock(&data->mutex); 2884 } 2885 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2886 2887 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2888 { 2889 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2890 u32 cmdlen = 0; 2891 int i; 2892 2893 for (i = 0; i < trans_pcie->max_tbs; i++) 2894 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2895 2896 return cmdlen; 2897 } 2898 2899 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2900 struct iwl_fw_error_dump_data **data, 2901 int allocated_rb_nums) 2902 { 2903 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2904 int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2905 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 2906 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2907 u32 i, r, j, rb_len = 0; 2908 2909 spin_lock(&rxq->lock); 2910 2911 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2912 2913 for (i = rxq->read, j = 0; 2914 i != r && j < allocated_rb_nums; 2915 i = (i + 1) & RX_QUEUE_MASK, j++) { 2916 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2917 struct iwl_fw_error_dump_rb *rb; 2918 2919 dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2920 DMA_FROM_DEVICE); 2921 2922 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2923 2924 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2925 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2926 rb = (void *)(*data)->data; 2927 rb->index = cpu_to_le32(i); 2928 memcpy(rb->data, page_address(rxb->page), max_len); 2929 /* remap the page for the free benefit */ 2930 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2931 max_len, 2932 DMA_FROM_DEVICE); 2933 2934 *data = iwl_fw_error_next_data(*data); 2935 } 2936 2937 spin_unlock(&rxq->lock); 2938 2939 return rb_len; 2940 } 2941 #define IWL_CSR_TO_DUMP (0x250) 2942 2943 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2944 struct iwl_fw_error_dump_data **data) 2945 { 2946 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2947 __le32 *val; 2948 int i; 2949 2950 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2951 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2952 val = (void *)(*data)->data; 2953 2954 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2955 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2956 2957 *data = iwl_fw_error_next_data(*data); 2958 2959 return csr_len; 2960 } 2961 2962 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2963 struct iwl_fw_error_dump_data **data) 2964 { 2965 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2966 unsigned long flags; 2967 __le32 *val; 2968 int i; 2969 2970 if (!iwl_trans_grab_nic_access(trans, &flags)) 2971 return 0; 2972 2973 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2974 (*data)->len = cpu_to_le32(fh_regs_len); 2975 val = (void *)(*data)->data; 2976 2977 if (!trans->cfg->gen2) 2978 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2979 i += sizeof(u32)) 2980 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2981 else 2982 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2983 i += sizeof(u32)) 2984 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2985 i)); 2986 2987 iwl_trans_release_nic_access(trans, &flags); 2988 2989 *data = iwl_fw_error_next_data(*data); 2990 2991 return sizeof(**data) + fh_regs_len; 2992 } 2993 2994 static u32 2995 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2996 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2997 u32 monitor_len) 2998 { 2999 u32 buf_size_in_dwords = (monitor_len >> 2); 3000 u32 *buffer = (u32 *)fw_mon_data->data; 3001 unsigned long flags; 3002 u32 i; 3003 3004 if (!iwl_trans_grab_nic_access(trans, &flags)) 3005 return 0; 3006 3007 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3008 for (i = 0; i < buf_size_in_dwords; i++) 3009 buffer[i] = iwl_read_prph_no_grab(trans, 3010 MON_DMARB_RD_DATA_ADDR); 3011 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3012 3013 iwl_trans_release_nic_access(trans, &flags); 3014 3015 return monitor_len; 3016 } 3017 3018 static u32 3019 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3020 struct iwl_fw_error_dump_data **data, 3021 u32 monitor_len) 3022 { 3023 u32 len = 0; 3024 3025 if ((trans->num_blocks && 3026 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 3027 trans->dbg_dest_tlv) { 3028 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3029 u32 base, write_ptr, wrap_cnt; 3030 3031 /* If there was a dest TLV - use the values from there */ 3032 if (trans->dbg_dest_tlv) { 3033 write_ptr = 3034 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 3035 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 3036 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3037 } else { 3038 base = MON_BUFF_BASE_ADDR; 3039 write_ptr = MON_BUFF_WRPTR; 3040 wrap_cnt = MON_BUFF_CYCLE_CNT; 3041 } 3042 3043 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3044 fw_mon_data = (void *)(*data)->data; 3045 fw_mon_data->fw_mon_wr_ptr = 3046 cpu_to_le32(iwl_read_prph(trans, write_ptr)); 3047 fw_mon_data->fw_mon_cycle_cnt = 3048 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3049 fw_mon_data->fw_mon_base_ptr = 3050 cpu_to_le32(iwl_read_prph(trans, base)); 3051 3052 len += sizeof(**data) + sizeof(*fw_mon_data); 3053 if (trans->num_blocks) { 3054 memcpy(fw_mon_data->data, 3055 trans->fw_mon[0].block, 3056 trans->fw_mon[0].size); 3057 3058 monitor_len = trans->fw_mon[0].size; 3059 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 3060 /* 3061 * Update pointers to reflect actual values after 3062 * shifting 3063 */ 3064 if (trans->dbg_dest_tlv->version) { 3065 base = (iwl_read_prph(trans, base) & 3066 IWL_LDBG_M2S_BUF_BA_MSK) << 3067 trans->dbg_dest_tlv->base_shift; 3068 base *= IWL_M2S_UNIT_SIZE; 3069 base += trans->cfg->smem_offset; 3070 } else { 3071 base = iwl_read_prph(trans, base) << 3072 trans->dbg_dest_tlv->base_shift; 3073 } 3074 3075 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3076 monitor_len / sizeof(u32)); 3077 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 3078 monitor_len = 3079 iwl_trans_pci_dump_marbh_monitor(trans, 3080 fw_mon_data, 3081 monitor_len); 3082 } else { 3083 /* Didn't match anything - output no monitor data */ 3084 monitor_len = 0; 3085 } 3086 3087 len += monitor_len; 3088 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3089 } 3090 3091 return len; 3092 } 3093 3094 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, int *len) 3095 { 3096 if (trans->num_blocks) { 3097 *len += sizeof(struct iwl_fw_error_dump_data) + 3098 sizeof(struct iwl_fw_error_dump_fw_mon) + 3099 trans->fw_mon[0].size; 3100 return trans->fw_mon[0].size; 3101 } else if (trans->dbg_dest_tlv) { 3102 u32 base, end, cfg_reg, monitor_len; 3103 3104 if (trans->dbg_dest_tlv->version == 1) { 3105 cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3106 cfg_reg = iwl_read_prph(trans, cfg_reg); 3107 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3108 trans->dbg_dest_tlv->base_shift; 3109 base *= IWL_M2S_UNIT_SIZE; 3110 base += trans->cfg->smem_offset; 3111 3112 monitor_len = 3113 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3114 trans->dbg_dest_tlv->end_shift; 3115 monitor_len *= IWL_M2S_UNIT_SIZE; 3116 } else { 3117 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3118 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 3119 3120 base = iwl_read_prph(trans, base) << 3121 trans->dbg_dest_tlv->base_shift; 3122 end = iwl_read_prph(trans, end) << 3123 trans->dbg_dest_tlv->end_shift; 3124 3125 /* Make "end" point to the actual end */ 3126 if (trans->cfg->device_family >= 3127 IWL_DEVICE_FAMILY_8000 || 3128 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 3129 end += (1 << trans->dbg_dest_tlv->end_shift); 3130 monitor_len = end - base; 3131 } 3132 *len += sizeof(struct iwl_fw_error_dump_data) + 3133 sizeof(struct iwl_fw_error_dump_fw_mon) + 3134 monitor_len; 3135 return monitor_len; 3136 } 3137 return 0; 3138 } 3139 3140 static struct iwl_trans_dump_data 3141 *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3142 u32 dump_mask) 3143 { 3144 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3145 struct iwl_fw_error_dump_data *data; 3146 struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3147 struct iwl_fw_error_dump_txcmd *txcmd; 3148 struct iwl_trans_dump_data *dump_data; 3149 u32 len, num_rbs = 0; 3150 u32 monitor_len; 3151 int i, ptr; 3152 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3153 !trans->cfg->mq_rx_supported && 3154 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3155 3156 if (!dump_mask) 3157 return NULL; 3158 3159 /* transport dump header */ 3160 len = sizeof(*dump_data); 3161 3162 /* host commands */ 3163 len += sizeof(*data) + 3164 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 3165 3166 /* FW monitor */ 3167 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3168 3169 if (dump_mask == BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) { 3170 dump_data = vzalloc(len); 3171 if (!dump_data) 3172 return NULL; 3173 3174 data = (void *)dump_data->data; 3175 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3176 dump_data->len = len; 3177 3178 return dump_data; 3179 } 3180 3181 /* CSR registers */ 3182 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3183 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3184 3185 /* FH registers */ 3186 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3187 if (trans->cfg->gen2) 3188 len += sizeof(*data) + 3189 (FH_MEM_UPPER_BOUND_GEN2 - 3190 FH_MEM_LOWER_BOUND_GEN2); 3191 else 3192 len += sizeof(*data) + 3193 (FH_MEM_UPPER_BOUND - 3194 FH_MEM_LOWER_BOUND); 3195 } 3196 3197 if (dump_rbs) { 3198 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3199 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3200 /* RBs */ 3201 num_rbs = 3202 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3203 & 0x0FFF; 3204 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3205 len += num_rbs * (sizeof(*data) + 3206 sizeof(struct iwl_fw_error_dump_rb) + 3207 (PAGE_SIZE << trans_pcie->rx_page_order)); 3208 } 3209 3210 /* Paged memory for gen2 HW */ 3211 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3212 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 3213 len += sizeof(*data) + 3214 sizeof(struct iwl_fw_error_dump_paging) + 3215 trans_pcie->init_dram.paging[i].size; 3216 3217 dump_data = vzalloc(len); 3218 if (!dump_data) 3219 return NULL; 3220 3221 len = 0; 3222 data = (void *)dump_data->data; 3223 3224 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { 3225 u16 tfd_size = trans_pcie->tfd_size; 3226 3227 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3228 txcmd = (void *)data->data; 3229 spin_lock_bh(&cmdq->lock); 3230 ptr = cmdq->write_ptr; 3231 for (i = 0; i < cmdq->n_window; i++) { 3232 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3233 u32 caplen, cmdlen; 3234 3235 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3236 cmdq->tfds + 3237 tfd_size * ptr); 3238 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3239 3240 if (cmdlen) { 3241 len += sizeof(*txcmd) + caplen; 3242 txcmd->cmdlen = cpu_to_le32(cmdlen); 3243 txcmd->caplen = cpu_to_le32(caplen); 3244 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3245 caplen); 3246 txcmd = (void *)((u8 *)txcmd->data + caplen); 3247 } 3248 3249 ptr = iwl_queue_dec_wrap(trans, ptr); 3250 } 3251 spin_unlock_bh(&cmdq->lock); 3252 3253 data->len = cpu_to_le32(len); 3254 len += sizeof(*data); 3255 data = iwl_fw_error_next_data(data); 3256 } 3257 3258 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3259 len += iwl_trans_pcie_dump_csr(trans, &data); 3260 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3261 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3262 if (dump_rbs) 3263 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3264 3265 /* Paged memory for gen2 HW */ 3266 if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3267 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 3268 struct iwl_fw_error_dump_paging *paging; 3269 dma_addr_t addr = 3270 trans_pcie->init_dram.paging[i].physical; 3271 u32 page_len = trans_pcie->init_dram.paging[i].size; 3272 3273 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3274 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3275 paging = (void *)data->data; 3276 paging->index = cpu_to_le32(i); 3277 dma_sync_single_for_cpu(trans->dev, addr, page_len, 3278 DMA_BIDIRECTIONAL); 3279 memcpy(paging->data, 3280 trans_pcie->init_dram.paging[i].block, page_len); 3281 data = iwl_fw_error_next_data(data); 3282 3283 len += sizeof(*data) + sizeof(*paging) + page_len; 3284 } 3285 } 3286 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3287 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3288 3289 dump_data->len = len; 3290 3291 return dump_data; 3292 } 3293 3294 #ifdef CONFIG_PM_SLEEP 3295 static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 3296 { 3297 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3298 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3299 return iwl_pci_fw_enter_d0i3(trans); 3300 3301 return 0; 3302 } 3303 3304 static void iwl_trans_pcie_resume(struct iwl_trans *trans) 3305 { 3306 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3307 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 3308 iwl_pci_fw_exit_d0i3(trans); 3309 } 3310 #endif /* CONFIG_PM_SLEEP */ 3311 3312 #define IWL_TRANS_COMMON_OPS \ 3313 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3314 .write8 = iwl_trans_pcie_write8, \ 3315 .write32 = iwl_trans_pcie_write32, \ 3316 .read32 = iwl_trans_pcie_read32, \ 3317 .read_prph = iwl_trans_pcie_read_prph, \ 3318 .write_prph = iwl_trans_pcie_write_prph, \ 3319 .read_mem = iwl_trans_pcie_read_mem, \ 3320 .write_mem = iwl_trans_pcie_write_mem, \ 3321 .configure = iwl_trans_pcie_configure, \ 3322 .set_pmi = iwl_trans_pcie_set_pmi, \ 3323 .sw_reset = iwl_trans_pcie_sw_reset, \ 3324 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3325 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3326 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3327 .ref = iwl_trans_pcie_ref, \ 3328 .unref = iwl_trans_pcie_unref, \ 3329 .dump_data = iwl_trans_pcie_dump_data, \ 3330 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3331 .d3_resume = iwl_trans_pcie_d3_resume 3332 3333 #ifdef CONFIG_PM_SLEEP 3334 #define IWL_TRANS_PM_OPS \ 3335 .suspend = iwl_trans_pcie_suspend, \ 3336 .resume = iwl_trans_pcie_resume, 3337 #else 3338 #define IWL_TRANS_PM_OPS 3339 #endif /* CONFIG_PM_SLEEP */ 3340 3341 static const struct iwl_trans_ops trans_ops_pcie = { 3342 IWL_TRANS_COMMON_OPS, 3343 IWL_TRANS_PM_OPS 3344 .start_hw = iwl_trans_pcie_start_hw, 3345 .fw_alive = iwl_trans_pcie_fw_alive, 3346 .start_fw = iwl_trans_pcie_start_fw, 3347 .stop_device = iwl_trans_pcie_stop_device, 3348 3349 .send_cmd = iwl_trans_pcie_send_hcmd, 3350 3351 .tx = iwl_trans_pcie_tx, 3352 .reclaim = iwl_trans_pcie_reclaim, 3353 3354 .txq_disable = iwl_trans_pcie_txq_disable, 3355 .txq_enable = iwl_trans_pcie_txq_enable, 3356 3357 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3358 3359 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3360 3361 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 3362 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3363 #ifdef CONFIG_IWLWIFI_DEBUGFS 3364 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3365 #endif 3366 }; 3367 3368 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3369 IWL_TRANS_COMMON_OPS, 3370 IWL_TRANS_PM_OPS 3371 .start_hw = iwl_trans_pcie_start_hw, 3372 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3373 .start_fw = iwl_trans_pcie_gen2_start_fw, 3374 .stop_device = iwl_trans_pcie_gen2_stop_device, 3375 3376 .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3377 3378 .tx = iwl_trans_pcie_gen2_tx, 3379 .reclaim = iwl_trans_pcie_reclaim, 3380 3381 .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 3382 .txq_free = iwl_trans_pcie_dyn_txq_free, 3383 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3384 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3385 #ifdef CONFIG_IWLWIFI_DEBUGFS 3386 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3387 #endif 3388 }; 3389 3390 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3391 const struct pci_device_id *ent, 3392 const struct iwl_cfg *cfg) 3393 { 3394 struct iwl_trans_pcie *trans_pcie; 3395 struct iwl_trans *trans; 3396 int ret, addr_size; 3397 3398 ret = pcim_enable_device(pdev); 3399 if (ret) 3400 return ERR_PTR(ret); 3401 3402 if (cfg->gen2) 3403 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3404 &pdev->dev, cfg, &trans_ops_pcie_gen2); 3405 else 3406 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3407 &pdev->dev, cfg, &trans_ops_pcie); 3408 if (!trans) 3409 return ERR_PTR(-ENOMEM); 3410 3411 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3412 3413 trans_pcie->trans = trans; 3414 trans_pcie->opmode_down = true; 3415 spin_lock_init(&trans_pcie->irq_lock); 3416 spin_lock_init(&trans_pcie->reg_lock); 3417 mutex_init(&trans_pcie->mutex); 3418 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3419 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3420 if (!trans_pcie->tso_hdr_page) { 3421 ret = -ENOMEM; 3422 goto out_no_pci; 3423 } 3424 3425 3426 if (!cfg->base_params->pcie_l1_allowed) { 3427 /* 3428 * W/A - seems to solve weird behavior. We need to remove this 3429 * if we don't want to stay in L1 all the time. This wastes a 3430 * lot of power. 3431 */ 3432 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3433 PCIE_LINK_STATE_L1 | 3434 PCIE_LINK_STATE_CLKPM); 3435 } 3436 3437 trans_pcie->def_rx_queue = 0; 3438 3439 if (cfg->use_tfh) { 3440 addr_size = 64; 3441 trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 3442 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 3443 } else { 3444 addr_size = 36; 3445 trans_pcie->max_tbs = IWL_NUM_OF_TBS; 3446 trans_pcie->tfd_size = sizeof(struct iwl_tfd); 3447 } 3448 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 3449 3450 pci_set_master(pdev); 3451 3452 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3453 if (!ret) 3454 ret = pci_set_consistent_dma_mask(pdev, 3455 DMA_BIT_MASK(addr_size)); 3456 if (ret) { 3457 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3458 if (!ret) 3459 ret = pci_set_consistent_dma_mask(pdev, 3460 DMA_BIT_MASK(32)); 3461 /* both attempts failed: */ 3462 if (ret) { 3463 dev_err(&pdev->dev, "No suitable DMA available\n"); 3464 goto out_no_pci; 3465 } 3466 } 3467 3468 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3469 if (ret) { 3470 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3471 goto out_no_pci; 3472 } 3473 3474 trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3475 if (!trans_pcie->hw_base) { 3476 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3477 ret = -ENODEV; 3478 goto out_no_pci; 3479 } 3480 3481 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3482 * PCI Tx retries from interfering with C3 CPU state */ 3483 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3484 3485 trans_pcie->pci_dev = pdev; 3486 iwl_disable_interrupts(trans); 3487 3488 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3489 if (trans->hw_rev == 0xffffffff) { 3490 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3491 ret = -EIO; 3492 goto out_no_pci; 3493 } 3494 3495 /* 3496 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3497 * changed, and now the revision step also includes bit 0-1 (no more 3498 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3499 * in the old format. 3500 */ 3501 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3502 unsigned long flags; 3503 3504 trans->hw_rev = (trans->hw_rev & 0xfff0) | 3505 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3506 3507 ret = iwl_pcie_prepare_card_hw(trans); 3508 if (ret) { 3509 IWL_WARN(trans, "Exit HW not ready\n"); 3510 goto out_no_pci; 3511 } 3512 3513 /* 3514 * in-order to recognize C step driver should read chip version 3515 * id located at the AUX bus MISC address space. 3516 */ 3517 iwl_set_bit(trans, CSR_GP_CNTRL, 3518 BIT(trans->cfg->csr->flag_init_done)); 3519 udelay(2); 3520 3521 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3522 BIT(trans->cfg->csr->flag_mac_clock_ready), 3523 BIT(trans->cfg->csr->flag_mac_clock_ready), 3524 25000); 3525 if (ret < 0) { 3526 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 3527 goto out_no_pci; 3528 } 3529 3530 if (iwl_trans_grab_nic_access(trans, &flags)) { 3531 u32 hw_step; 3532 3533 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3534 hw_step |= ENABLE_WFPM; 3535 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 3536 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3537 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3538 if (hw_step == 0x3) 3539 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3540 (SILICON_C_STEP << 2); 3541 iwl_trans_release_nic_access(trans, &flags); 3542 } 3543 } 3544 3545 /* 3546 * 9000-series integrated A-step has a problem with suspend/resume 3547 * and sometimes even causes the whole platform to get stuck. This 3548 * workaround makes the hardware not go into the problematic state. 3549 */ 3550 if (trans->cfg->integrated && 3551 trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3552 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3553 iwl_set_bit(trans, CSR_HOST_CHICKEN, 3554 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3555 3556 #if IS_ENABLED(CONFIG_IWLMVM) 3557 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3558 3559 if (cfg == &iwl22000_2ax_cfg_hr) { 3560 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3561 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3562 trans->cfg = &iwl22000_2ax_cfg_hr; 3563 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3564 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3565 trans->cfg = &iwl22000_2ax_cfg_jf; 3566 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3567 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3568 IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3569 ret = -EINVAL; 3570 goto out_no_pci; 3571 } else { 3572 IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3573 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3574 ret = -EINVAL; 3575 goto out_no_pci; 3576 } 3577 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3578 CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3579 u32 hw_status; 3580 3581 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3582 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 3583 /* 3584 * b step fw is the same for physical card and fpga 3585 */ 3586 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3587 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 3588 CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 3589 trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 3590 } else { 3591 /* 3592 * a step no FPGA 3593 */ 3594 trans->cfg = &iwl22000_2ac_cfg_hr; 3595 } 3596 } 3597 #endif 3598 3599 iwl_pcie_set_interrupt_capa(pdev, trans); 3600 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3601 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3602 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3603 3604 /* Initialize the wait queue for commands */ 3605 init_waitqueue_head(&trans_pcie->wait_command_queue); 3606 3607 init_waitqueue_head(&trans_pcie->d0i3_waitq); 3608 3609 if (trans_pcie->msix_enabled) { 3610 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3611 if (ret) 3612 goto out_no_pci; 3613 } else { 3614 ret = iwl_pcie_alloc_ict(trans); 3615 if (ret) 3616 goto out_no_pci; 3617 3618 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3619 iwl_pcie_isr, 3620 iwl_pcie_irq_handler, 3621 IRQF_SHARED, DRV_NAME, trans); 3622 if (ret) { 3623 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3624 goto out_free_ict; 3625 } 3626 trans_pcie->inta_mask = CSR_INI_SET_MASK; 3627 } 3628 3629 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3630 WQ_HIGHPRI | WQ_UNBOUND, 1); 3631 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3632 3633 #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3634 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3635 #else 3636 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3637 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3638 3639 #ifdef CONFIG_IWLWIFI_DEBUGFS 3640 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3641 mutex_init(&trans_pcie->fw_mon_data.mutex); 3642 #endif 3643 3644 return trans; 3645 3646 out_free_ict: 3647 iwl_pcie_free_ict(trans); 3648 out_no_pci: 3649 free_percpu(trans_pcie->tso_hdr_page); 3650 iwl_trans_free(trans); 3651 return ERR_PTR(ret); 3652 } 3653