18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 27e705c121SKalle Valo #include "internal.h" 28e705c121SKalle Valo #include "iwl-fh.h" 296654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 30e705c121SKalle Valo 31e705c121SKalle Valo /* extended range in FW SRAM */ 32e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 34e705c121SKalle Valo 354290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 36a6d24fadSRajat Jain { 37c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 38c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 39c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 40a6d24fadSRajat Jain #define PREFIX_LEN 32 41a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 42a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 43a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 44a6d24fadSRajat Jain char *prefix; 45a6d24fadSRajat Jain 46a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 47a6d24fadSRajat Jain return; 48a6d24fadSRajat Jain 49a6d24fadSRajat Jain /* Should be a multiple of 4 */ 50a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 51c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho 54a6d24fadSRajat Jain /* Alloc a max size buffer */ 55a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 56c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho 60a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 61a6d24fadSRajat Jain if (!buf) 62a6d24fadSRajat Jain return; 63a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 64a6d24fadSRajat Jain 65a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 66a6d24fadSRajat Jain 67a6d24fadSRajat Jain /* Print wifi device registers */ 68a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 69a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 70a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 71a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 72a6d24fadSRajat Jain goto err_read; 73a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 74a6d24fadSRajat Jain 75a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 76c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 77a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 78a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79a6d24fadSRajat Jain 80a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 81a6d24fadSRajat Jain if (pos) { 82a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 83a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 84a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 85a6d24fadSRajat Jain goto err_read; 86a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 87a6d24fadSRajat Jain 32, 4, buf, i, 0); 88a6d24fadSRajat Jain } 89a6d24fadSRajat Jain 90a6d24fadSRajat Jain /* Print parent device registers next */ 91a6d24fadSRajat Jain if (!pdev->bus->self) 92a6d24fadSRajat Jain goto out; 93a6d24fadSRajat Jain 94a6d24fadSRajat Jain pdev = pdev->bus->self; 95a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 96a6d24fadSRajat Jain 97a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 98a6d24fadSRajat Jain pci_name(pdev)); 99c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 100a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 101a6d24fadSRajat Jain goto err_read; 102a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Print root port AER registers */ 105a6d24fadSRajat Jain pos = 0; 106a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 107a6d24fadSRajat Jain if (pdev) 108a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 109a6d24fadSRajat Jain if (pos) { 110a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 111a6d24fadSRajat Jain pci_name(pdev)); 112a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 113a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 114a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 115a6d24fadSRajat Jain goto err_read; 116a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 117a6d24fadSRajat Jain 4, buf, i, 0); 118a6d24fadSRajat Jain } 119f3402d6dSSara Sharon goto out; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain err_read: 122a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 123a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 124a6d24fadSRajat Jain out: 125a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 126a6d24fadSRajat Jain kfree(buf); 127a6d24fadSRajat Jain } 128a6d24fadSRajat Jain 129870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 130870c2a11SGolan Ben Ami { 131870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1326dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 133870c2a11SGolan Ben Ami usleep_range(5000, 6000); 134870c2a11SGolan Ben Ami } 135870c2a11SGolan Ben Ami 136e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 137e705c121SKalle Valo { 13869f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 139e705c121SKalle Valo 14069f0e505SShahar S Matityahu if (!fw_mon->size) 14169f0e505SShahar S Matityahu return; 14269f0e505SShahar S Matityahu 14369f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 14469f0e505SShahar S Matityahu fw_mon->physical); 14569f0e505SShahar S Matityahu 14669f0e505SShahar S Matityahu fw_mon->block = NULL; 14769f0e505SShahar S Matityahu fw_mon->physical = 0; 14869f0e505SShahar S Matityahu fw_mon->size = 0; 149e705c121SKalle Valo } 150e705c121SKalle Valo 15188964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 15288964b2eSSara Sharon u8 max_power, u8 min_power) 153e705c121SKalle Valo { 15469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 15569f0e505SShahar S Matityahu void *block = NULL; 15669f0e505SShahar S Matityahu dma_addr_t physical = 0; 157e705c121SKalle Valo u32 size = 0; 158e705c121SKalle Valo u8 power; 159e705c121SKalle Valo 16069f0e505SShahar S Matityahu if (fw_mon->size) 16169f0e505SShahar S Matityahu return; 16269f0e505SShahar S Matityahu 16388964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 164e705c121SKalle Valo size = BIT(power); 16569f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1662d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 16769f0e505SShahar S Matityahu if (!block) 168e705c121SKalle Valo continue; 169e705c121SKalle Valo 170e705c121SKalle Valo IWL_INFO(trans, 171c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 172c5f97542SShahar S Matityahu size); 173e705c121SKalle Valo break; 174e705c121SKalle Valo } 175e705c121SKalle Valo 17669f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 177e705c121SKalle Valo return; 178e705c121SKalle Valo 179e705c121SKalle Valo if (power != max_power) 180e705c121SKalle Valo IWL_ERR(trans, 181e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 182e705c121SKalle Valo (unsigned long)BIT(power - 10), 183e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 184e705c121SKalle Valo 18569f0e505SShahar S Matityahu fw_mon->block = block; 18669f0e505SShahar S Matityahu fw_mon->physical = physical; 18769f0e505SShahar S Matityahu fw_mon->size = size; 18888964b2eSSara Sharon } 18988964b2eSSara Sharon 19088964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 19188964b2eSSara Sharon { 19288964b2eSSara Sharon if (!max_power) { 19388964b2eSSara Sharon /* default max_power is maximum */ 19488964b2eSSara Sharon max_power = 26; 19588964b2eSSara Sharon } else { 19688964b2eSSara Sharon max_power += 11; 19788964b2eSSara Sharon } 19888964b2eSSara Sharon 19988964b2eSSara Sharon if (WARN(max_power > 26, 20088964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 20188964b2eSSara Sharon max_power)) 20288964b2eSSara Sharon return; 20388964b2eSSara Sharon 20469f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 20588964b2eSSara Sharon return; 20688964b2eSSara Sharon 20788964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 208e705c121SKalle Valo } 209e705c121SKalle Valo 210e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 211e705c121SKalle Valo { 212e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 213e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 214e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 215e705c121SKalle Valo } 216e705c121SKalle Valo 217e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 218e705c121SKalle Valo { 219e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 220e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 221e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 222e705c121SKalle Valo } 223e705c121SKalle Valo 224e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 225e705c121SKalle Valo { 226e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 227e705c121SKalle Valo return; 228e705c121SKalle Valo 229e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 230e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 231e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 232e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 233e705c121SKalle Valo else 234e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 235e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 236e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 237e705c121SKalle Valo } 238e705c121SKalle Valo 239e705c121SKalle Valo /* PCI registers */ 240e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 241e705c121SKalle Valo 242eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 243e705c121SKalle Valo { 244e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245e705c121SKalle Valo u16 lctl; 246e705c121SKalle Valo u16 cap; 247e705c121SKalle Valo 248e705c121SKalle Valo /* 249cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 250cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 251cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 252e705c121SKalle Valo */ 2533d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 254cc894b85SLuca Coelho 255cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 256e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 257e705c121SKalle Valo 258e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 259e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 260d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 261e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 262e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 263e705c121SKalle Valo } 264e705c121SKalle Valo 265e705c121SKalle Valo /* 266e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 267e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 268e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 269e705c121SKalle Valo */ 270e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 271e705c121SKalle Valo { 27252b6e168SEmmanuel Grumbach int ret; 27352b6e168SEmmanuel Grumbach 274e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 275e705c121SKalle Valo 276e705c121SKalle Valo /* 277e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 278e705c121SKalle Valo * bits already set by default after reset. 279e705c121SKalle Valo */ 280e705c121SKalle Valo 281e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 282286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 283e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 284e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 285e705c121SKalle Valo 286e705c121SKalle Valo /* 287e705c121SKalle Valo * Disable L0s without affecting L1; 288e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 289e705c121SKalle Valo */ 290e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 291e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 292e705c121SKalle Valo 293e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 294e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 295e705c121SKalle Valo 296e705c121SKalle Valo /* 297e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 298e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 299e705c121SKalle Valo */ 300e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 301e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 302e705c121SKalle Valo 303e705c121SKalle Valo iwl_pcie_apm_config(trans); 304e705c121SKalle Valo 305e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 306286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 30777d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 308e705c121SKalle Valo 3097d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 310c96b5eecSJohannes Berg if (ret) 31152b6e168SEmmanuel Grumbach return ret; 312e705c121SKalle Valo 313e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 314e705c121SKalle Valo /* 315e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 316e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 317e705c121SKalle Valo * not related to host_interrupt_operation_mode. 318e705c121SKalle Valo * 319e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 320e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 321e705c121SKalle Valo * that we wake up from L1 on time. 322e705c121SKalle Valo * 323e705c121SKalle Valo * This looks weird: read twice the same register, discard the 324e705c121SKalle Valo * value, set a bit, and yet again, read that same register 325e705c121SKalle Valo * just to discard the value. But that's the way the hardware 326e705c121SKalle Valo * seems to like it. 327e705c121SKalle Valo */ 328e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 329e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 330e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 331e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 332e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo /* 336e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 337e705c121SKalle Valo * 338e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 339e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 340e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 341e705c121SKalle Valo */ 342e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 343e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 344e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 345e705c121SKalle Valo udelay(20); 346e705c121SKalle Valo 347e705c121SKalle Valo /* Disable L1-Active */ 348e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 349e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 350e705c121SKalle Valo 351e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 352e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 353e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 354e705c121SKalle Valo } 355e705c121SKalle Valo 356e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 357e705c121SKalle Valo 35852b6e168SEmmanuel Grumbach return 0; 359e705c121SKalle Valo } 360e705c121SKalle Valo 361e705c121SKalle Valo /* 362e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 363e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 364e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 365e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 366e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 367e705c121SKalle Valo */ 368e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 369e705c121SKalle Valo { 370e705c121SKalle Valo int ret; 371e705c121SKalle Valo u32 apmg_gp1_reg; 372e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 373e705c121SKalle Valo u32 dl_cfg_reg; 374e705c121SKalle Valo 375e705c121SKalle Valo /* Force XTAL ON */ 376e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 377e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 378e705c121SKalle Valo 379870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 380e705c121SKalle Valo 3817d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 382c96b5eecSJohannes Berg if (WARN_ON(ret)) { 383e705c121SKalle Valo /* Release XTAL ON request */ 384e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 385e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo /* 390e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 391e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 392e705c121SKalle Valo */ 393e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 394e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 395e705c121SKalle Valo 396e705c121SKalle Valo /* 397e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 398e705c121SKalle Valo * caused by APMG idle state. 399e705c121SKalle Valo */ 400e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 401e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 402e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 403e705c121SKalle Valo apmg_xtal_cfg_reg | 404e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 405e705c121SKalle Valo 406870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 407e705c121SKalle Valo 408e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 409e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 410e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 411e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 412e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Clear delay line clock power up */ 415e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 417e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 418e705c121SKalle Valo 419e705c121SKalle Valo /* 420e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 421e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 422e705c121SKalle Valo */ 423e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 424e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 425e705c121SKalle Valo 426e705c121SKalle Valo /* 427e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 428e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 429e705c121SKalle Valo */ 4306dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 431e705c121SKalle Valo 432e705c121SKalle Valo /* Activates XTAL resources monitor */ 433e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 434e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 435e705c121SKalle Valo 436e705c121SKalle Valo /* Release XTAL ON request */ 437e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 438e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 439e705c121SKalle Valo udelay(10); 440e705c121SKalle Valo 441e705c121SKalle Valo /* Release APMG XTAL */ 442e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 443e705c121SKalle Valo apmg_xtal_cfg_reg & 444e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 445e705c121SKalle Valo } 446e705c121SKalle Valo 447e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 448e705c121SKalle Valo { 449e8c8935eSJohannes Berg int ret; 450e705c121SKalle Valo 451e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4529ce041f5SJohannes Berg 4539ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4549ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4559ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4569ce041f5SJohannes Berg 4579ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4589ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4599ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4609ce041f5SJohannes Berg 100); 4619ce041f5SJohannes Berg } else { 4626dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 463e705c121SKalle Valo 4646dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4656dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4666dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4679ce041f5SJohannes Berg } 4689ce041f5SJohannes Berg 469e705c121SKalle Valo if (ret < 0) 470e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 471e705c121SKalle Valo 472e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 473e705c121SKalle Valo } 474e705c121SKalle Valo 475e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 476e705c121SKalle Valo { 477e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 478e705c121SKalle Valo 479e705c121SKalle Valo if (op_mode_leave) { 480e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 481e705c121SKalle Valo iwl_pcie_apm_init(trans); 482e705c121SKalle Valo 483e705c121SKalle Valo /* inform ME that we are leaving */ 484286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 485e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 486e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 487286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 48879b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 489e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 490e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 491e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 492e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 493e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 494e705c121SKalle Valo mdelay(1); 495e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 496e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 497e705c121SKalle Valo } 498e705c121SKalle Valo mdelay(5); 499e705c121SKalle Valo } 500e705c121SKalle Valo 501e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 502e705c121SKalle Valo 503e705c121SKalle Valo /* Stop device's DMA activity */ 504e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 505e705c121SKalle Valo 506e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 507e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 508e705c121SKalle Valo return; 509e705c121SKalle Valo } 510e705c121SKalle Valo 511870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 512e705c121SKalle Valo 513e705c121SKalle Valo /* 514e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 515e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 516e705c121SKalle Valo */ 5176dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 518e705c121SKalle Valo } 519e705c121SKalle Valo 520e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 521e705c121SKalle Valo { 522e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 52352b6e168SEmmanuel Grumbach int ret; 524e705c121SKalle Valo 525e705c121SKalle Valo /* nic_init */ 52625edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 52752b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 52825edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 529e705c121SKalle Valo 53052b6e168SEmmanuel Grumbach if (ret) 53152b6e168SEmmanuel Grumbach return ret; 53252b6e168SEmmanuel Grumbach 533e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 534e705c121SKalle Valo 535e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 536e705c121SKalle Valo 537e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5389cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5399cf671d6SEmmanuel Grumbach if (ret) 5409cf671d6SEmmanuel Grumbach return ret; 541e705c121SKalle Valo 542e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5439cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5449cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 545e705c121SKalle Valo return -ENOMEM; 5469cf671d6SEmmanuel Grumbach } 547e705c121SKalle Valo 548286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 549e705c121SKalle Valo /* enable shadow regs in HW */ 550e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 551e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 552e705c121SKalle Valo } 553e705c121SKalle Valo 554e705c121SKalle Valo return 0; 555e705c121SKalle Valo } 556e705c121SKalle Valo 557e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 558e705c121SKalle Valo 559e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 560e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 561e705c121SKalle Valo { 562e705c121SKalle Valo int ret; 563e705c121SKalle Valo 564e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 565e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 566e705c121SKalle Valo 567e705c121SKalle Valo /* See if we got it */ 568e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 569e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 570e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 571e705c121SKalle Valo HW_READY_TIMEOUT); 572e705c121SKalle Valo 573e705c121SKalle Valo if (ret >= 0) 574e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 575e705c121SKalle Valo 576e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 577e705c121SKalle Valo return ret; 578e705c121SKalle Valo } 579e705c121SKalle Valo 580e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 581eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 582e705c121SKalle Valo { 583e705c121SKalle Valo int ret; 584e705c121SKalle Valo int t = 0; 585e705c121SKalle Valo int iter; 586e705c121SKalle Valo 587e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 588e705c121SKalle Valo 589e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 590e705c121SKalle Valo /* If the card is ready, exit 0 */ 591e705c121SKalle Valo if (ret >= 0) 592e705c121SKalle Valo return 0; 593e705c121SKalle Valo 594e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 595e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 596192185d6SJohannes Berg usleep_range(1000, 2000); 597e705c121SKalle Valo 598e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 599e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 600e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 601e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 602e705c121SKalle Valo 603e705c121SKalle Valo do { 604e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 605e705c121SKalle Valo if (ret >= 0) 606e705c121SKalle Valo return 0; 607e705c121SKalle Valo 608e705c121SKalle Valo usleep_range(200, 1000); 609e705c121SKalle Valo t += 200; 610e705c121SKalle Valo } while (t < 150000); 611e705c121SKalle Valo msleep(25); 612e705c121SKalle Valo } 613e705c121SKalle Valo 614e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 615e705c121SKalle Valo 616e705c121SKalle Valo return ret; 617e705c121SKalle Valo } 618e705c121SKalle Valo 619e705c121SKalle Valo /* 620e705c121SKalle Valo * ucode 621e705c121SKalle Valo */ 622564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 623564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 624564cdce7SSara Sharon u32 byte_cnt) 625e705c121SKalle Valo { 626bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 627e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 628e705c121SKalle Valo 629bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 630e705c121SKalle Valo dst_addr); 631e705c121SKalle Valo 632bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 633e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 634e705c121SKalle Valo 635bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 636e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 637e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 638e705c121SKalle Valo 639bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 640bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 641bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 642e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 643e705c121SKalle Valo 644bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 645e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 646e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 647e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 648564cdce7SSara Sharon } 649e705c121SKalle Valo 650564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 651564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 652564cdce7SSara Sharon u32 byte_cnt) 653564cdce7SSara Sharon { 654564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 655564cdce7SSara Sharon int ret; 656564cdce7SSara Sharon 657564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 658564cdce7SSara Sharon 6591ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 660564cdce7SSara Sharon return -EIO; 661564cdce7SSara Sharon 662564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 663564cdce7SSara Sharon byte_cnt); 6641ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 665bac842daSEmmanuel Grumbach 666e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 667e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 668e705c121SKalle Valo if (!ret) { 669e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 670fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 671e705c121SKalle Valo return -ETIMEDOUT; 672e705c121SKalle Valo } 673e705c121SKalle Valo 674e705c121SKalle Valo return 0; 675e705c121SKalle Valo } 676e705c121SKalle Valo 677e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 678e705c121SKalle Valo const struct fw_desc *section) 679e705c121SKalle Valo { 680e705c121SKalle Valo u8 *v_addr; 681e705c121SKalle Valo dma_addr_t p_addr; 682e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 683e705c121SKalle Valo int ret = 0; 684e705c121SKalle Valo 685e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 686e705c121SKalle Valo section_num); 687e705c121SKalle Valo 688e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 689e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 690e705c121SKalle Valo if (!v_addr) { 691e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 692e705c121SKalle Valo chunk_sz = PAGE_SIZE; 693e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 694e705c121SKalle Valo &p_addr, GFP_KERNEL); 695e705c121SKalle Valo if (!v_addr) 696e705c121SKalle Valo return -ENOMEM; 697e705c121SKalle Valo } 698e705c121SKalle Valo 699e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 700e705c121SKalle Valo u32 copy_size, dst_addr; 701e705c121SKalle Valo bool extended_addr = false; 702e705c121SKalle Valo 703e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 704e705c121SKalle Valo dst_addr = section->offset + offset; 705e705c121SKalle Valo 706e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 707e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 708e705c121SKalle Valo extended_addr = true; 709e705c121SKalle Valo 710e705c121SKalle Valo if (extended_addr) 711e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 712e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 713e705c121SKalle Valo 714e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 715e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 716e705c121SKalle Valo copy_size); 717e705c121SKalle Valo 718e705c121SKalle Valo if (extended_addr) 719e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 720e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 721e705c121SKalle Valo 722e705c121SKalle Valo if (ret) { 723e705c121SKalle Valo IWL_ERR(trans, 724e705c121SKalle Valo "Could not load the [%d] uCode section\n", 725e705c121SKalle Valo section_num); 726e705c121SKalle Valo break; 727e705c121SKalle Valo } 728e705c121SKalle Valo } 729e705c121SKalle Valo 730e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 731e705c121SKalle Valo return ret; 732e705c121SKalle Valo } 733e705c121SKalle Valo 734e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 735e705c121SKalle Valo const struct fw_img *image, 736e705c121SKalle Valo int cpu, 737e705c121SKalle Valo int *first_ucode_section) 738e705c121SKalle Valo { 739e705c121SKalle Valo int shift_param; 740e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 741e705c121SKalle Valo u32 val, last_read_idx = 0; 742e705c121SKalle Valo 743e705c121SKalle Valo if (cpu == 1) { 744e705c121SKalle Valo shift_param = 0; 745e705c121SKalle Valo *first_ucode_section = 0; 746e705c121SKalle Valo } else { 747e705c121SKalle Valo shift_param = 16; 748e705c121SKalle Valo (*first_ucode_section)++; 749e705c121SKalle Valo } 750e705c121SKalle Valo 751eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 752e705c121SKalle Valo last_read_idx = i; 753e705c121SKalle Valo 754e705c121SKalle Valo /* 755e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 756e705c121SKalle Valo * CPU1 to CPU2. 757e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 758e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 759e705c121SKalle Valo */ 760e705c121SKalle Valo if (!image->sec[i].data || 761e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 762e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 763e705c121SKalle Valo IWL_DEBUG_FW(trans, 764e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 765e705c121SKalle Valo i); 766e705c121SKalle Valo break; 767e705c121SKalle Valo } 768e705c121SKalle Valo 769e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 770e705c121SKalle Valo if (ret) 771e705c121SKalle Valo return ret; 772e705c121SKalle Valo 773d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 774e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 775e705c121SKalle Valo val = val | (sec_num << shift_param); 776e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 777eda50cdeSSara Sharon 778e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 779e705c121SKalle Valo } 780e705c121SKalle Valo 781e705c121SKalle Valo *first_ucode_section = last_read_idx; 782e705c121SKalle Valo 7832aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 7842aabdbdcSEmmanuel Grumbach 785286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 786e705c121SKalle Valo if (cpu == 1) 787d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 788d6a2c5c7SSara Sharon 0xFFFF); 789e705c121SKalle Valo else 790d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 791d6a2c5c7SSara Sharon 0xFFFFFFFF); 792d6a2c5c7SSara Sharon } else { 793d6a2c5c7SSara Sharon if (cpu == 1) 794d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 795d6a2c5c7SSara Sharon 0xFFFF); 796d6a2c5c7SSara Sharon else 797d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 798d6a2c5c7SSara Sharon 0xFFFFFFFF); 799d6a2c5c7SSara Sharon } 800e705c121SKalle Valo 801e705c121SKalle Valo return 0; 802e705c121SKalle Valo } 803e705c121SKalle Valo 804e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 805e705c121SKalle Valo const struct fw_img *image, 806e705c121SKalle Valo int cpu, 807e705c121SKalle Valo int *first_ucode_section) 808e705c121SKalle Valo { 809e705c121SKalle Valo int i, ret = 0; 810e705c121SKalle Valo u32 last_read_idx = 0; 811e705c121SKalle Valo 8123ce4a038SKirtika Ruchandani if (cpu == 1) 813e705c121SKalle Valo *first_ucode_section = 0; 8143ce4a038SKirtika Ruchandani else 815e705c121SKalle Valo (*first_ucode_section)++; 816e705c121SKalle Valo 817eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 818e705c121SKalle Valo last_read_idx = i; 819e705c121SKalle Valo 820e705c121SKalle Valo /* 821e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 822e705c121SKalle Valo * CPU1 to CPU2. 823e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 824e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 825e705c121SKalle Valo */ 826e705c121SKalle Valo if (!image->sec[i].data || 827e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 828e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 829e705c121SKalle Valo IWL_DEBUG_FW(trans, 830e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 831e705c121SKalle Valo i); 832e705c121SKalle Valo break; 833e705c121SKalle Valo } 834e705c121SKalle Valo 835e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 836e705c121SKalle Valo if (ret) 837e705c121SKalle Valo return ret; 838e705c121SKalle Valo } 839e705c121SKalle Valo 840e705c121SKalle Valo *first_ucode_section = last_read_idx; 841e705c121SKalle Valo 842e705c121SKalle Valo return 0; 843e705c121SKalle Valo } 844e705c121SKalle Valo 845593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 846593fae3eSShahar S Matityahu { 847593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 848593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 849593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 850593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 851593fae3eSShahar S Matityahu 852593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 853593fae3eSShahar S Matityahu return; 854593fae3eSShahar S Matityahu 855593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 856593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 857593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 858593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 859593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 860593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 861593fae3eSShahar S Matityahu 862593fae3eSShahar S Matityahu return; 863593fae3eSShahar S Matityahu } 864593fae3eSShahar S Matityahu 865593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 866593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 867593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 868593fae3eSShahar S Matityahu return; 869593fae3eSShahar S Matityahu 870593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 871593fae3eSShahar S Matityahu 872593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 873593fae3eSShahar S Matityahu alloc_id); 874593fae3eSShahar S Matityahu 875593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 876593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 877593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 878593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 879593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 880593fae3eSShahar S Matityahu } 881593fae3eSShahar S Matityahu 882c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 883e705c121SKalle Valo { 88491c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 88569f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 886e705c121SKalle Valo int i; 887e705c121SKalle Valo 888a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 889593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 8907a14c23dSSara Sharon return; 8917a14c23dSSara Sharon } 8927a14c23dSSara Sharon 893e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 894e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 895e705c121SKalle Valo 896e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 897e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 898e705c121SKalle Valo else 899e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 900e705c121SKalle Valo 90191c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 902e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 903e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 904e705c121SKalle Valo 905e705c121SKalle Valo switch (dest->reg_ops[i].op) { 906e705c121SKalle Valo case CSR_ASSIGN: 907e705c121SKalle Valo iwl_write32(trans, addr, val); 908e705c121SKalle Valo break; 909e705c121SKalle Valo case CSR_SETBIT: 910e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 911e705c121SKalle Valo break; 912e705c121SKalle Valo case CSR_CLEARBIT: 913e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 914e705c121SKalle Valo break; 915e705c121SKalle Valo case PRPH_ASSIGN: 916e705c121SKalle Valo iwl_write_prph(trans, addr, val); 917e705c121SKalle Valo break; 918e705c121SKalle Valo case PRPH_SETBIT: 919e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 920e705c121SKalle Valo break; 921e705c121SKalle Valo case PRPH_CLEARBIT: 922e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 923e705c121SKalle Valo break; 924e705c121SKalle Valo case PRPH_BLOCKBIT: 925e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 926e705c121SKalle Valo IWL_ERR(trans, 927e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 928e705c121SKalle Valo val, addr); 929e705c121SKalle Valo goto monitor; 930e705c121SKalle Valo } 931e705c121SKalle Valo break; 932e705c121SKalle Valo default: 933e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 934e705c121SKalle Valo dest->reg_ops[i].op); 935e705c121SKalle Valo break; 936e705c121SKalle Valo } 937e705c121SKalle Valo } 938e705c121SKalle Valo 939e705c121SKalle Valo monitor: 94069f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 941e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 94269f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 943286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 944e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 94569f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 94669f0e505SShahar S Matityahu 256) >> dest->end_shift); 94762d7476dSEmmanuel Grumbach else 94862d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 94969f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 95062d7476dSEmmanuel Grumbach dest->end_shift); 951e705c121SKalle Valo } 952e705c121SKalle Valo } 953e705c121SKalle Valo 954e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 955e705c121SKalle Valo const struct fw_img *image) 956e705c121SKalle Valo { 957e705c121SKalle Valo int ret = 0; 958e705c121SKalle Valo int first_ucode_section; 959e705c121SKalle Valo 960e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 961e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 962e705c121SKalle Valo 963e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 964e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 965e705c121SKalle Valo if (ret) 966e705c121SKalle Valo return ret; 967e705c121SKalle Valo 968e705c121SKalle Valo if (image->is_dual_cpus) { 969e705c121SKalle Valo /* set CPU2 header address */ 970e705c121SKalle Valo iwl_write_prph(trans, 971e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 972e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 973e705c121SKalle Valo 974e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 975e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 976e705c121SKalle Valo &first_ucode_section); 977e705c121SKalle Valo if (ret) 978e705c121SKalle Valo return ret; 979e705c121SKalle Valo } 980e705c121SKalle Valo 9819efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 982e705c121SKalle Valo iwl_pcie_apply_destination(trans); 983e705c121SKalle Valo 9842aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 9852aabdbdcSEmmanuel Grumbach 986e705c121SKalle Valo /* release CPU reset */ 987e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 988e705c121SKalle Valo 989e705c121SKalle Valo return 0; 990e705c121SKalle Valo } 991e705c121SKalle Valo 992e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 993e705c121SKalle Valo const struct fw_img *image) 994e705c121SKalle Valo { 995e705c121SKalle Valo int ret = 0; 996e705c121SKalle Valo int first_ucode_section; 997e705c121SKalle Valo 998e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 999e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1000e705c121SKalle Valo 10017a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1002e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1003e705c121SKalle Valo 100482ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 100582ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 100682ea7966SSara Sharon 100782ea7966SSara Sharon /* 100882ea7966SSara Sharon * Set default value. On resume reading the values that were 100982ea7966SSara Sharon * zeored can provide debug data on the resume flow. 101082ea7966SSara Sharon * This is for debugging only and has no functional impact. 101182ea7966SSara Sharon */ 101282ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 101382ea7966SSara Sharon 1014e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1015e705c121SKalle Valo /* release CPU reset */ 1016e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1017e705c121SKalle Valo 1018e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1019e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1020e705c121SKalle Valo &first_ucode_section); 1021e705c121SKalle Valo if (ret) 1022e705c121SKalle Valo return ret; 1023e705c121SKalle Valo 1024e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1025e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1026e705c121SKalle Valo &first_ucode_section); 1027e705c121SKalle Valo } 1028e705c121SKalle Valo 10299ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1030727c02dfSSara Sharon { 1031326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1032727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1033326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1034326477e4SJohannes Berg bool report; 1035727c02dfSSara Sharon 1036326477e4SJohannes Berg if (hw_rfkill) { 1037326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1038326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1039326477e4SJohannes Berg } else { 1040326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1041326477e4SJohannes Berg if (trans_pcie->opmode_down) 1042326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1043326477e4SJohannes Berg } 1044727c02dfSSara Sharon 1045326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1046326477e4SJohannes Berg 1047326477e4SJohannes Berg if (prev != report) 1048326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1049727c02dfSSara Sharon 1050727c02dfSSara Sharon return hw_rfkill; 1051727c02dfSSara Sharon } 1052727c02dfSSara Sharon 10537ca00409SHaim Dreyfuss struct iwl_causes_list { 10547ca00409SHaim Dreyfuss u32 cause_num; 10557ca00409SHaim Dreyfuss u32 mask_reg; 10567ca00409SHaim Dreyfuss u8 addr; 10577ca00409SHaim Dreyfuss }; 10587ca00409SHaim Dreyfuss 10597ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 10607ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10617ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10627ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10637ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10647ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10657ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1066906d4eb8SJohannes Berg {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10677ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10687ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 10697ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 10707ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 10717ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 10727ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 10737ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 10747ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 10757ca00409SHaim Dreyfuss }; 10767ca00409SHaim Dreyfuss 10777ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 10787ca00409SHaim Dreyfuss { 10797ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10807ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 10813681021fSJohannes Berg int i, arr_size = ARRAY_SIZE(causes_list); 10823681021fSJohannes Berg struct iwl_causes_list *causes = causes_list; 10837ca00409SHaim Dreyfuss 10847ca00409SHaim Dreyfuss /* 10857ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 10867ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 10877ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 10887ca00409SHaim Dreyfuss */ 10899b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 10909b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 10919b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 10929b58419eSGolan Ben Ami causes[i].cause_num); 10937ca00409SHaim Dreyfuss } 10947ca00409SHaim Dreyfuss } 10957ca00409SHaim Dreyfuss 10967ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 10977ca00409SHaim Dreyfuss { 10987ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10997ca00409SHaim Dreyfuss u32 offset = 11007ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11017ca00409SHaim Dreyfuss u32 val, idx; 11027ca00409SHaim Dreyfuss 11037ca00409SHaim Dreyfuss /* 11047ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11057ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11067ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11077ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11087ca00409SHaim Dreyfuss */ 11097ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11107ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11117ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11127ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11137ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11147ca00409SHaim Dreyfuss } 11157ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11167ca00409SHaim Dreyfuss 11177ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11187ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11197ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11207ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11217ca00409SHaim Dreyfuss 11227ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11237ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11247ca00409SHaim Dreyfuss } 11257ca00409SHaim Dreyfuss 112677c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11277ca00409SHaim Dreyfuss { 11287ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11297ca00409SHaim Dreyfuss 11307ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1131286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1132d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1133ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11347ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11357ca00409SHaim Dreyfuss return; 11367ca00409SHaim Dreyfuss } 1137d7270d61SHaim Dreyfuss /* 1138d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1139d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1140d7270d61SHaim Dreyfuss * prph. 1141d7270d61SHaim Dreyfuss */ 1142d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1143ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11447ca00409SHaim Dreyfuss 11457ca00409SHaim Dreyfuss /* 11467ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11477ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11487ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11497ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11507ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11517ca00409SHaim Dreyfuss */ 11527ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 11537ca00409SHaim Dreyfuss 11547ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 115583730058SHaim Dreyfuss } 11567ca00409SHaim Dreyfuss 115783730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 115883730058SHaim Dreyfuss { 115983730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 116083730058SHaim Dreyfuss 116183730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 116283730058SHaim Dreyfuss 116383730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 116483730058SHaim Dreyfuss return; 116583730058SHaim Dreyfuss 116683730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 11677ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 116883730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 11697ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 11707ca00409SHaim Dreyfuss } 11717ca00409SHaim Dreyfuss 1172bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1173e705c121SKalle Valo { 1174e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1175e705c121SKalle Valo 1176e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1177e705c121SKalle Valo 1178e705c121SKalle Valo if (trans_pcie->is_down) 1179e705c121SKalle Valo return; 1180e705c121SKalle Valo 1181e705c121SKalle Valo trans_pcie->is_down = true; 1182e705c121SKalle Valo 1183e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1184e705c121SKalle Valo iwl_disable_interrupts(trans); 1185e705c121SKalle Valo 1186e705c121SKalle Valo /* device going down, Stop using ICT table */ 1187e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1188e705c121SKalle Valo 1189e705c121SKalle Valo /* 1190e705c121SKalle Valo * If a HW restart happens during firmware loading, 1191e705c121SKalle Valo * then the firmware loading might call this function 1192e705c121SKalle Valo * and later it might be called again due to the 1193e705c121SKalle Valo * restart. So don't process again if the device is 1194e705c121SKalle Valo * already dead. 1195e705c121SKalle Valo */ 1196e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1197a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1198a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1199e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1200e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1201e705c121SKalle Valo 1202e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1203e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1204e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1205e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1206e705c121SKalle Valo udelay(5); 1207e705c121SKalle Valo } 1208e705c121SKalle Valo } 1209e705c121SKalle Valo 1210e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1211e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12126dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1213e705c121SKalle Valo 1214e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1215e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1216e705c121SKalle Valo 1217870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1218e705c121SKalle Valo 1219e705c121SKalle Valo /* 1220f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1221f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1222f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1223f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1224f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1225f4a1f04aSGolan Ben Ami */ 1226f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1227f4a1f04aSGolan Ben Ami 1228f4a1f04aSGolan Ben Ami /* 1229e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1230e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1231e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1232e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1233e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1234e705c121SKalle Valo */ 1235e705c121SKalle Valo iwl_disable_interrupts(trans); 1236e705c121SKalle Valo 1237e705c121SKalle Valo /* clear all status bits */ 1238e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1239e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1240e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1241e705c121SKalle Valo 1242e705c121SKalle Valo /* 1243e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1244e705c121SKalle Valo * interrupt 1245e705c121SKalle Valo */ 1246e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1247e705c121SKalle Valo 1248a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1249e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1250e705c121SKalle Valo } 1251e705c121SKalle Valo 1252eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 12532e5d4a8fSHaim Dreyfuss { 12542e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12552e5d4a8fSHaim Dreyfuss 12562e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 12572e5d4a8fSHaim Dreyfuss int i; 12582e5d4a8fSHaim Dreyfuss 1259496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 12602e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 12612e5d4a8fSHaim Dreyfuss } else { 12622e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 12632e5d4a8fSHaim Dreyfuss } 12642e5d4a8fSHaim Dreyfuss } 12652e5d4a8fSHaim Dreyfuss 1266a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1267a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1268a6bd005fSEmmanuel Grumbach { 1269a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1270a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1271a6bd005fSEmmanuel Grumbach int ret; 1272a6bd005fSEmmanuel Grumbach 1273a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1274a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1275a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1276a6bd005fSEmmanuel Grumbach ret = -EIO; 1277a6bd005fSEmmanuel Grumbach goto out; 1278a6bd005fSEmmanuel Grumbach } 1279a6bd005fSEmmanuel Grumbach 1280a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1281a6bd005fSEmmanuel Grumbach 1282a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1283a6bd005fSEmmanuel Grumbach 1284a6bd005fSEmmanuel Grumbach /* 1285a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1286a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1287a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1288a6bd005fSEmmanuel Grumbach */ 1289a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1290a6bd005fSEmmanuel Grumbach 1291a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 12922e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1293a6bd005fSEmmanuel Grumbach 1294a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1295a6bd005fSEmmanuel Grumbach 1296a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 12979ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1298a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1299a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1300a6bd005fSEmmanuel Grumbach goto out; 1301a6bd005fSEmmanuel Grumbach } 1302a6bd005fSEmmanuel Grumbach 1303a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1304a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1305a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1306a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 130720aa99bbSAnton Protopopov ret = -EIO; 1308a6bd005fSEmmanuel Grumbach goto out; 1309a6bd005fSEmmanuel Grumbach } 1310a6bd005fSEmmanuel Grumbach 1311a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1312a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1313a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1314a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1315a6bd005fSEmmanuel Grumbach 1316a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1317a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1318a6bd005fSEmmanuel Grumbach 1319a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1320a6bd005fSEmmanuel Grumbach if (ret) { 1321a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1322a6bd005fSEmmanuel Grumbach goto out; 1323a6bd005fSEmmanuel Grumbach } 1324a6bd005fSEmmanuel Grumbach 1325a6bd005fSEmmanuel Grumbach /* 1326a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1327a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1328a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1329a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1330a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1331a6bd005fSEmmanuel Grumbach */ 1332a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1333a6bd005fSEmmanuel Grumbach 1334a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1335a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1336a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1337a6bd005fSEmmanuel Grumbach 1338a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1339286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1340a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1341a6bd005fSEmmanuel Grumbach else 1342a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1343a6bd005fSEmmanuel Grumbach 1344a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13459ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1346a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1347a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1348a6bd005fSEmmanuel Grumbach 1349a6bd005fSEmmanuel Grumbach out: 1350a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1351a6bd005fSEmmanuel Grumbach return ret; 1352a6bd005fSEmmanuel Grumbach } 1353a6bd005fSEmmanuel Grumbach 1354a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1355a6bd005fSEmmanuel Grumbach { 1356a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1357a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1358a6bd005fSEmmanuel Grumbach } 1359a6bd005fSEmmanuel Grumbach 1360326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1361326477e4SJohannes Berg bool was_in_rfkill) 1362326477e4SJohannes Berg { 1363326477e4SJohannes Berg bool hw_rfkill; 1364326477e4SJohannes Berg 1365326477e4SJohannes Berg /* 1366326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1367326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1368326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1369326477e4SJohannes Berg * op_mode. 1370326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1371326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1372326477e4SJohannes Berg * notification without endless recursion. Under very rare 1373326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1374326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1375326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1376326477e4SJohannes Berg */ 1377326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1378326477e4SJohannes Berg if (hw_rfkill) { 1379326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1380326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1381326477e4SJohannes Berg } else { 1382326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1383326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1384326477e4SJohannes Berg } 1385326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1386326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1387326477e4SJohannes Berg } 1388326477e4SJohannes Berg 1389bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1390e705c121SKalle Valo { 1391e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1392326477e4SJohannes Berg bool was_in_rfkill; 1393e705c121SKalle Valo 1394d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1395d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1396d0129315SMordechay Goodstein NULL); 1397d0129315SMordechay Goodstein 1398e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1399326477e4SJohannes Berg trans_pcie->opmode_down = true; 1400326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1401bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1402326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1403e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1404e705c121SKalle Valo } 1405e705c121SKalle Valo 1406e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1407e705c121SKalle Valo { 1408e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1409e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1410e705c121SKalle Valo 1411e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1412e705c121SKalle Valo 1413326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1414326477e4SJohannes Berg state ? "disabled" : "enabled"); 141577c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1416286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1417bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 141877c09bc8SSara Sharon else 1419bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1420e705c121SKalle Valo } 142177c09bc8SSara Sharon } 1422e705c121SKalle Valo 1423e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1424e5f3f215SHaim Dreyfuss bool test, bool reset) 1425e705c121SKalle Valo { 1426e705c121SKalle Valo iwl_disable_interrupts(trans); 1427e705c121SKalle Valo 1428e705c121SKalle Valo /* 1429e705c121SKalle Valo * in testing mode, the host stays awake and the 1430e705c121SKalle Valo * hardware won't be reset (not even partially) 1431e705c121SKalle Valo */ 1432e705c121SKalle Valo if (test) 1433e705c121SKalle Valo return; 1434e705c121SKalle Valo 1435e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1436e705c121SKalle Valo 14372e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1438e705c121SKalle Valo 1439e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14406dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14416dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1442e705c121SKalle Valo 144323ae6128SMatti Gottlieb if (reset) { 1444e705c121SKalle Valo /* 1445e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1446e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1447e705c121SKalle Valo * to execute some invalid memory upon resume 1448e705c121SKalle Valo */ 1449e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1450e705c121SKalle Valo } 1451e705c121SKalle Valo 1452e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1453e705c121SKalle Valo } 1454e705c121SKalle Valo 1455e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1456e5f3f215SHaim Dreyfuss bool reset) 1457e5f3f215SHaim Dreyfuss { 1458e5f3f215SHaim Dreyfuss int ret; 1459e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1460e5f3f215SHaim Dreyfuss 1461771db3a1SHaim Dreyfuss if (!reset) 1462e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1463e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1464e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1465e5f3f215SHaim Dreyfuss 1466e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1467e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1468e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1469e5f3f215SHaim Dreyfuss 1470e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1471e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1472e5f3f215SHaim Dreyfuss /* 1473e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1474e5f3f215SHaim Dreyfuss */ 1475e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1476e5f3f215SHaim Dreyfuss 1477e5f3f215SHaim Dreyfuss if (!ret) { 1478e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1479e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1480e5f3f215SHaim Dreyfuss } 1481e5f3f215SHaim Dreyfuss } 1482e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1483e5f3f215SHaim Dreyfuss 1484e5f3f215SHaim Dreyfuss return 0; 1485e5f3f215SHaim Dreyfuss } 1486e5f3f215SHaim Dreyfuss 1487e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1488e705c121SKalle Valo enum iwl_d3_status *status, 148923ae6128SMatti Gottlieb bool test, bool reset) 1490e705c121SKalle Valo { 1491d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1492e705c121SKalle Valo u32 val; 1493e705c121SKalle Valo int ret; 1494e705c121SKalle Valo 1495e705c121SKalle Valo if (test) { 1496e705c121SKalle Valo iwl_enable_interrupts(trans); 1497e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1498e5f3f215SHaim Dreyfuss goto out; 1499e705c121SKalle Valo } 1500e705c121SKalle Valo 1501a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15026dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1503e705c121SKalle Valo 15047d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1505c96b5eecSJohannes Berg if (ret) 1506e705c121SKalle Valo return ret; 1507e705c121SKalle Valo 1508f98ad635SEmmanuel Grumbach /* 1509f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1510f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1511f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1512f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1513f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1514f98ad635SEmmanuel Grumbach */ 1515f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1516f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1517f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1518f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1519f98ad635SEmmanuel Grumbach 1520e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1521e705c121SKalle Valo 152223ae6128SMatti Gottlieb if (!reset) { 1523e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15246dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1525e705c121SKalle Valo } else { 1526e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1527e705c121SKalle Valo 1528e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1529e705c121SKalle Valo if (ret) { 1530e705c121SKalle Valo IWL_ERR(trans, 1531e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1532e705c121SKalle Valo return ret; 1533e705c121SKalle Valo } 1534e705c121SKalle Valo } 1535e705c121SKalle Valo 153682ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1537ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 153882ea7966SSara Sharon 1539e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1540e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1541e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1542e705c121SKalle Valo else 1543e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1544e705c121SKalle Valo 1545e5f3f215SHaim Dreyfuss out: 1546e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1547e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1548e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1549e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1550e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1551e5f3f215SHaim Dreyfuss 1552e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1553e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1554e5f3f215SHaim Dreyfuss /* 1555e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1556e5f3f215SHaim Dreyfuss */ 1557e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1558e5f3f215SHaim Dreyfuss 1559e5f3f215SHaim Dreyfuss if (!ret) { 1560e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1561e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1562e5f3f215SHaim Dreyfuss } 1563e5f3f215SHaim Dreyfuss } 1564e705c121SKalle Valo return 0; 1565e705c121SKalle Valo } 1566e705c121SKalle Valo 15670c18714aSLuca Coelho static void 15680c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15690c18714aSLuca Coelho struct iwl_trans *trans, 15700c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 15712e5d4a8fSHaim Dreyfuss { 15722e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1573ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15742e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15750cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 15762e5d4a8fSHaim Dreyfuss 15770c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 157806f4b081SSara Sharon goto enable_msi; 157906f4b081SSara Sharon 15800cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 15810cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 15820cd38f4dSMordechay Goodstein 15830cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 158406f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15852e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15862e5d4a8fSHaim Dreyfuss 158706f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15882e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 158906f4b081SSara Sharon max_irqs); 159006f4b081SSara Sharon if (num_irqs < 0) { 1591496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 159206f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 159306f4b081SSara Sharon num_irqs); 159406f4b081SSara Sharon goto enable_msi; 1595496d83caSHaim Dreyfuss } 159606f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1597496d83caSHaim Dreyfuss 15982e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 159906f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 160006f4b081SSara Sharon num_irqs); 160106f4b081SSara Sharon 1602496d83caSHaim Dreyfuss /* 160306f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 160406f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1605496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1606496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1607496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1608496d83caSHaim Dreyfuss */ 1609ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 161006f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1611496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1612496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1613ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 161406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1615496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1616496d83caSHaim Dreyfuss } else { 161706f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1618496d83caSHaim Dreyfuss } 16199d401222SMordechay Goodstein 16209d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16219d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16229d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16239d401222SMordechay Goodstein 1624ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16252e5d4a8fSHaim Dreyfuss 162606f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1627496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16282e5d4a8fSHaim Dreyfuss return; 16292e5d4a8fSHaim Dreyfuss 163006f4b081SSara Sharon enable_msi: 163106f4b081SSara Sharon ret = pci_enable_msi(pdev); 163206f4b081SSara Sharon if (ret) { 163306f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16342e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16352e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16362e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16372e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16382e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16392e5d4a8fSHaim Dreyfuss } 16402e5d4a8fSHaim Dreyfuss } 16412e5d4a8fSHaim Dreyfuss } 16422e5d4a8fSHaim Dreyfuss 16437c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16447c8d91ebSHaim Dreyfuss { 16457c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16467c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16477c8d91ebSHaim Dreyfuss 16487c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16497c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16507c8d91ebSHaim Dreyfuss offset = 1 + i; 16517c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16527c8d91ebSHaim Dreyfuss /* 16537c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16547c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16557c8d91ebSHaim Dreyfuss */ 16567c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16577c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16587c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16597c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16607c8d91ebSHaim Dreyfuss if (ret) 16617c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16627c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 166357e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 16647c8d91ebSHaim Dreyfuss } 16657c8d91ebSHaim Dreyfuss } 16667c8d91ebSHaim Dreyfuss 16672e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16682e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16692e5d4a8fSHaim Dreyfuss { 1670496d83caSHaim Dreyfuss int i; 16712e5d4a8fSHaim Dreyfuss 1672496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16732e5d4a8fSHaim Dreyfuss int ret; 16745a41a86cSSharon Dvir struct msix_entry *msix_entry; 167564fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 167664fa3affSSharon Dvir 167764fa3affSSharon Dvir if (!qname) 167864fa3affSSharon Dvir return -ENOMEM; 16792e5d4a8fSHaim Dreyfuss 16805a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16815a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16825a41a86cSSharon Dvir msix_entry->vector, 16832e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1684496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16852e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16862e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16872e5d4a8fSHaim Dreyfuss IRQF_SHARED, 168864fa3affSSharon Dvir qname, 16895a41a86cSSharon Dvir msix_entry); 16902e5d4a8fSHaim Dreyfuss if (ret) { 16912e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16922e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16935a41a86cSSharon Dvir 16942e5d4a8fSHaim Dreyfuss return ret; 16952e5d4a8fSHaim Dreyfuss } 16962e5d4a8fSHaim Dreyfuss } 16977c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 16982e5d4a8fSHaim Dreyfuss 16992e5d4a8fSHaim Dreyfuss return 0; 17002e5d4a8fSHaim Dreyfuss } 17012e5d4a8fSHaim Dreyfuss 170244f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 170344f61b5cSShahar S Matityahu { 170444f61b5cSShahar S Matityahu u32 hpm, wprot; 170544f61b5cSShahar S Matityahu 1706286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 170744f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 170844f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 170944f61b5cSShahar S Matityahu break; 171044f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 171144f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 171244f61b5cSShahar S Matityahu break; 171344f61b5cSShahar S Matityahu default: 171444f61b5cSShahar S Matityahu return 0; 171544f61b5cSShahar S Matityahu } 171644f61b5cSShahar S Matityahu 171744f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 171844f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 171944f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 172044f61b5cSShahar S Matityahu 172144f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 172244f61b5cSShahar S Matityahu IWL_ERR(trans, 172344f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 172444f61b5cSShahar S Matityahu return -EPERM; 172544f61b5cSShahar S Matityahu } 172644f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 172744f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 172844f61b5cSShahar S Matityahu } 172944f61b5cSShahar S Matityahu 173044f61b5cSShahar S Matityahu return 0; 173144f61b5cSShahar S Matityahu } 173244f61b5cSShahar S Matityahu 17330df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17340df36b90SLuca Coelho { 17350df36b90SLuca Coelho int ret; 17360df36b90SLuca Coelho 17370df36b90SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 17380df36b90SLuca Coelho if (ret < 0) 17390df36b90SLuca Coelho return ret; 17400df36b90SLuca Coelho 17410df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17420df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17430df36b90SLuca Coelho udelay(20); 17440df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17450df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 17460df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 17470df36b90SLuca Coelho udelay(20); 17480df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 17490df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17500df36b90SLuca Coelho 17510df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 17520df36b90SLuca Coelho 17530df36b90SLuca Coelho return 0; 17540df36b90SLuca Coelho } 17550df36b90SLuca Coelho 1756bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1757e705c121SKalle Valo { 1758e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1759e705c121SKalle Valo int err; 1760e705c121SKalle Valo 1761e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1762e705c121SKalle Valo 1763e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1764e705c121SKalle Valo if (err) { 1765e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1766e705c121SKalle Valo return err; 1767e705c121SKalle Valo } 1768e705c121SKalle Valo 176944f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 177044f61b5cSShahar S Matityahu if (err) 177144f61b5cSShahar S Matityahu return err; 17728954e1ebSShahar S Matityahu 1773870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1774e705c121SKalle Valo 17750df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 17767897dfa2SLuca Coelho trans->trans_cfg->integrated) { 17770df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 17780df36b90SLuca Coelho if (err) 17790df36b90SLuca Coelho return err; 17800df36b90SLuca Coelho } 17810df36b90SLuca Coelho 178252b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 178352b6e168SEmmanuel Grumbach if (err) 178452b6e168SEmmanuel Grumbach return err; 1785e705c121SKalle Valo 17862e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 178783730058SHaim Dreyfuss 1788e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1789e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1790e705c121SKalle Valo 1791326477e4SJohannes Berg trans_pcie->opmode_down = false; 1792326477e4SJohannes Berg 1793e705c121SKalle Valo /* Set is_down to false here so that...*/ 1794e705c121SKalle Valo trans_pcie->is_down = false; 1795e705c121SKalle Valo 1796e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17979ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1798e705c121SKalle Valo 1799e705c121SKalle Valo return 0; 1800e705c121SKalle Valo } 1801e705c121SKalle Valo 1802bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1803e705c121SKalle Valo { 1804e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1805e705c121SKalle Valo int ret; 1806e705c121SKalle Valo 1807e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1808bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1809e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1810e705c121SKalle Valo 1811e705c121SKalle Valo return ret; 1812e705c121SKalle Valo } 1813e705c121SKalle Valo 1814e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1815e705c121SKalle Valo { 1816e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1817e705c121SKalle Valo 1818e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1819e705c121SKalle Valo 1820e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1821e705c121SKalle Valo iwl_disable_interrupts(trans); 1822e705c121SKalle Valo 1823e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1824e705c121SKalle Valo 1825e705c121SKalle Valo iwl_disable_interrupts(trans); 1826e705c121SKalle Valo 1827e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1828e705c121SKalle Valo 1829e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1830e705c121SKalle Valo 18312e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1832e705c121SKalle Valo } 1833e705c121SKalle Valo 1834e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1835e705c121SKalle Valo { 1836e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1837e705c121SKalle Valo } 1838e705c121SKalle Valo 1839e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1840e705c121SKalle Valo { 1841e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1842e705c121SKalle Valo } 1843e705c121SKalle Valo 1844e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1845e705c121SKalle Valo { 1846e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1847e705c121SKalle Valo } 1848e705c121SKalle Valo 184984fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 185084fb372cSSara Sharon { 18513681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 185284fb372cSSara Sharon return 0x00FFFFFF; 185384fb372cSSara Sharon else 185484fb372cSSara Sharon return 0x000FFFFF; 185584fb372cSSara Sharon } 185684fb372cSSara Sharon 1857e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1858e705c121SKalle Valo { 185984fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 186084fb372cSSara Sharon 1861e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 186284fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1863e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1864e705c121SKalle Valo } 1865e705c121SKalle Valo 1866e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1867e705c121SKalle Valo u32 val) 1868e705c121SKalle Valo { 186984fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 187084fb372cSSara Sharon 1871e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 187284fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1873e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1874e705c121SKalle Valo } 1875e705c121SKalle Valo 1876e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1877e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1878e705c121SKalle Valo { 1879e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1880e705c121SKalle Valo 18816ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 18826ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 18836ac57200SJohannes Berg 18844f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 18854f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 18864f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 188722852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 188822852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 188922852fadSMordechay Goodstein 1890e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1891e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1892e705c121SKalle Valo else 1893e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1894e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1895e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1896e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1897e705c121SKalle Valo 18986c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18996c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19006c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 190180084e35SJohannes Berg trans_pcie->rx_buf_bytes = 190280084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1903cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1904cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1905cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1906e705c121SKalle Valo 19078e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1908e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1909e705c121SKalle Valo 191039bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 191139bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 191239bdb17eSSharon Dvir 1913e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1914e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1915e705c121SKalle Valo * As this function may be called again in some corner cases don't 1916e705c121SKalle Valo * do anything if NAPI was already initialized. 1917e705c121SKalle Valo */ 1918bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1919e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1920906d4eb8SJohannes Berg 1921906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1922e705c121SKalle Valo } 1923e705c121SKalle Valo 1924e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1925e705c121SKalle Valo { 1926e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19276eb5e529SEmmanuel Grumbach int i; 1928e705c121SKalle Valo 19292e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1930e705c121SKalle Valo 1931286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 19320cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 193313a3a390SSara Sharon else 1934e705c121SKalle Valo iwl_pcie_tx_free(trans); 1935e705c121SKalle Valo iwl_pcie_rx_free(trans); 1936e705c121SKalle Valo 193710a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 193810a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 193910a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 194010a54d81SLuca Coelho } 194110a54d81SLuca Coelho 19422e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19437c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19447c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19457c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19467c8d91ebSHaim Dreyfuss NULL); 19477c8d91ebSHaim Dreyfuss } 19482e5d4a8fSHaim Dreyfuss 19492e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19502e5d4a8fSHaim Dreyfuss } else { 1951e705c121SKalle Valo iwl_pcie_free_ict(trans); 19522e5d4a8fSHaim Dreyfuss } 1953e705c121SKalle Valo 1954e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1955e705c121SKalle Valo 195669725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 195769725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 195869725928SLuca Coelho trans_pcie->pnvm_dram.block, 195969725928SLuca Coelho trans_pcie->pnvm_dram.physical); 196069725928SLuca Coelho 19619dad325fSLuca Coelho if (trans_pcie->reduce_power_dram.size) 19629dad325fSLuca Coelho dma_free_coherent(trans->dev, 19639dad325fSLuca Coelho trans_pcie->reduce_power_dram.size, 19649dad325fSLuca Coelho trans_pcie->reduce_power_dram.block, 19659dad325fSLuca Coelho trans_pcie->reduce_power_dram.physical); 19669dad325fSLuca Coelho 1967a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1968e705c121SKalle Valo iwl_trans_free(trans); 1969e705c121SKalle Valo } 1970e705c121SKalle Valo 1971e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1972e705c121SKalle Valo { 1973e705c121SKalle Valo if (state) 1974e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1975e705c121SKalle Valo else 1976e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1977e705c121SKalle Valo } 1978e705c121SKalle Valo 197949564a80SLuca Coelho struct iwl_trans_pcie_removal { 198049564a80SLuca Coelho struct pci_dev *pdev; 198149564a80SLuca Coelho struct work_struct work; 198249564a80SLuca Coelho }; 198349564a80SLuca Coelho 198449564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 198549564a80SLuca Coelho { 198649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 198749564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 198849564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1989aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 199049564a80SLuca Coelho 199149564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 199249564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 199349564a80SLuca Coelho pci_lock_rescan_remove(); 199449564a80SLuca Coelho pci_dev_put(pdev); 199549564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 199649564a80SLuca Coelho pci_unlock_rescan_remove(); 199749564a80SLuca Coelho 199849564a80SLuca Coelho kfree(removal); 199949564a80SLuca Coelho module_put(THIS_MODULE); 200049564a80SLuca Coelho } 200149564a80SLuca Coelho 2002c544d89bSJohannes Berg /* 2003c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2004c544d89bSJohannes Berg * already disabled. 2005c544d89bSJohannes Berg */ 2006c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2007e705c121SKalle Valo { 2008e705c121SKalle Valo int ret; 2009e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20109ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 20119ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 20129ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 20139ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2014e705c121SKalle Valo 2015c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2016e705c121SKalle Valo 2017e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2018e705c121SKalle Valo goto out; 2019e705c121SKalle Valo 20209ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 20219ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 20229ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20239ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20249ce041f5SJohannes Berg } 20259ce041f5SJohannes Berg 2026e705c121SKalle Valo /* this bit wakes up the NIC */ 20279ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2028286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2029e705c121SKalle Valo udelay(2); 2030e705c121SKalle Valo 2031e705c121SKalle Valo /* 2032e705c121SKalle Valo * These bits say the device is running, and should keep running for 2033e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2034e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2035fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2036fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2037e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2038e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2039e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2040e705c121SKalle Valo * to keep device from sleeping. 2041e705c121SKalle Valo * 2042e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2043e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2044fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2045fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2046fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2047e705c121SKalle Valo * 2048e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2049e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2050e705c121SKalle Valo */ 20519ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2052e705c121SKalle Valo if (unlikely(ret < 0)) { 205349564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 205449564a80SLuca Coelho 2055e705c121SKalle Valo WARN_ONCE(1, 2056e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 205749564a80SLuca Coelho cntrl); 205849564a80SLuca Coelho 205949564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 206049564a80SLuca Coelho 206149564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 206249564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 206349564a80SLuca Coelho 2064f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 206549564a80SLuca Coelho goto err; 206649564a80SLuca Coelho 206749564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 206849564a80SLuca Coelho 206949564a80SLuca Coelho /* 207049564a80SLuca Coelho * get a module reference to avoid doing this 207149564a80SLuca Coelho * while unloading anyway and to avoid 207249564a80SLuca Coelho * scheduling a work with code that's being 207349564a80SLuca Coelho * removed. 207449564a80SLuca Coelho */ 207549564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 207649564a80SLuca Coelho IWL_ERR(trans, 207749564a80SLuca Coelho "Module is being unloaded - abort\n"); 207849564a80SLuca Coelho goto err; 207949564a80SLuca Coelho } 208049564a80SLuca Coelho 208149564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 208249564a80SLuca Coelho if (!removal) { 208349564a80SLuca Coelho module_put(THIS_MODULE); 208449564a80SLuca Coelho goto err; 208549564a80SLuca Coelho } 208649564a80SLuca Coelho /* 208749564a80SLuca Coelho * we don't need to clear this flag, because 208849564a80SLuca Coelho * the trans will be freed and reallocated. 208949564a80SLuca Coelho */ 2090f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 209149564a80SLuca Coelho 209249564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 209349564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 209449564a80SLuca Coelho pci_dev_get(removal->pdev); 209549564a80SLuca Coelho schedule_work(&removal->work); 209649564a80SLuca Coelho } else { 209749564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 209849564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 209949564a80SLuca Coelho } 210049564a80SLuca Coelho 210149564a80SLuca Coelho err: 2102c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2103e705c121SKalle Valo return false; 2104e705c121SKalle Valo } 2105e705c121SKalle Valo 2106e705c121SKalle Valo out: 2107e705c121SKalle Valo /* 2108e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2109e705c121SKalle Valo * track nic_access anyway. 2110e705c121SKalle Valo */ 2111e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2112e705c121SKalle Valo return true; 2113e705c121SKalle Valo } 2114e705c121SKalle Valo 2115c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2116c544d89bSJohannes Berg { 2117c544d89bSJohannes Berg bool ret; 2118c544d89bSJohannes Berg 2119c544d89bSJohannes Berg local_bh_disable(); 2120c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2121c544d89bSJohannes Berg if (ret) { 2122c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2123c544d89bSJohannes Berg return ret; 2124c544d89bSJohannes Berg } 2125c544d89bSJohannes Berg local_bh_enable(); 2126c544d89bSJohannes Berg return false; 2127c544d89bSJohannes Berg } 2128c544d89bSJohannes Berg 21291ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2130e705c121SKalle Valo { 2131e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2132e705c121SKalle Valo 2133e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2134e705c121SKalle Valo 2135e705c121SKalle Valo /* 2136e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2137e705c121SKalle Valo * track nic_access anyway. 2138e705c121SKalle Valo */ 2139e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2140e705c121SKalle Valo 2141e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2142e705c121SKalle Valo goto out; 2143e705c121SKalle Valo 2144e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21456dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2146e705c121SKalle Valo /* 2147e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2148e705c121SKalle Valo * any previous writes, but we need the write that clears the 2149e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2150e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2151e705c121SKalle Valo */ 2152e705c121SKalle Valo out: 2153874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2154e705c121SKalle Valo } 2155e705c121SKalle Valo 2156e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2157e705c121SKalle Valo void *buf, int dwords) 2158e705c121SKalle Valo { 215904516706SJohannes Berg int offs = 0; 2160e705c121SKalle Valo u32 *vals = buf; 2161e705c121SKalle Valo 216204516706SJohannes Berg while (offs < dwords) { 216304516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 216467013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 21653d372c4eSJohannes Berg bool resched = false; 216604516706SJohannes Berg 21671ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 216804516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 216904516706SJohannes Berg addr + 4 * offs); 217004516706SJohannes Berg 217104516706SJohannes Berg while (offs < dwords) { 217204516706SJohannes Berg vals[offs] = iwl_read32(trans, 217304516706SJohannes Berg HBUS_TARG_MEM_RDAT); 217404516706SJohannes Berg offs++; 217504516706SJohannes Berg 21763d372c4eSJohannes Berg if (time_after(jiffies, end)) { 21773d372c4eSJohannes Berg resched = true; 217804516706SJohannes Berg break; 217904516706SJohannes Berg } 21803d372c4eSJohannes Berg } 21811ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 21823d372c4eSJohannes Berg 21833d372c4eSJohannes Berg if (resched) 21843d372c4eSJohannes Berg cond_resched(); 2185e705c121SKalle Valo } else { 218604516706SJohannes Berg return -EBUSY; 2187e705c121SKalle Valo } 218804516706SJohannes Berg } 218904516706SJohannes Berg 219004516706SJohannes Berg return 0; 2191e705c121SKalle Valo } 2192e705c121SKalle Valo 2193e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2194e705c121SKalle Valo const void *buf, int dwords) 2195e705c121SKalle Valo { 2196e705c121SKalle Valo int offs, ret = 0; 2197e705c121SKalle Valo const u32 *vals = buf; 2198e705c121SKalle Valo 21991ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2200e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2201e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2202e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2203e705c121SKalle Valo vals ? vals[offs] : 0); 22041ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2205e705c121SKalle Valo } else { 2206e705c121SKalle Valo ret = -EBUSY; 2207e705c121SKalle Valo } 2208e705c121SKalle Valo return ret; 2209e705c121SKalle Valo } 2210e705c121SKalle Valo 22117f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22127f1fe1d4SLuca Coelho u32 *val) 22137f1fe1d4SLuca Coelho { 22147f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 22157f1fe1d4SLuca Coelho ofs, val); 22167f1fe1d4SLuca Coelho } 22177f1fe1d4SLuca Coelho 22180cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22190cd58eaaSEmmanuel Grumbach { 22200cd58eaaSEmmanuel Grumbach int i; 22210cd58eaaSEmmanuel Grumbach 2222286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 22234f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 22240cd58eaaSEmmanuel Grumbach 22254f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 22260cd58eaaSEmmanuel Grumbach continue; 22270cd58eaaSEmmanuel Grumbach 22280cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22290cd58eaaSEmmanuel Grumbach 22300cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22310cd58eaaSEmmanuel Grumbach txq->block--; 22320cd58eaaSEmmanuel Grumbach if (!txq->block) { 22330cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2234bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22350cd58eaaSEmmanuel Grumbach } 22360cd58eaaSEmmanuel Grumbach } else if (block) { 22370cd58eaaSEmmanuel Grumbach txq->block++; 22380cd58eaaSEmmanuel Grumbach } 22390cd58eaaSEmmanuel Grumbach 22400cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22410cd58eaaSEmmanuel Grumbach } 22420cd58eaaSEmmanuel Grumbach } 22430cd58eaaSEmmanuel Grumbach 2244e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2245e705c121SKalle Valo 224692536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 224792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 224892536c96SSara Sharon { 224992536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 225092536c96SSara Sharon 225192536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 225292536c96SSara Sharon return -EINVAL; 225392536c96SSara Sharon 225492536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 225592536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 225692536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 225792536c96SSara Sharon data->fr_bd_wid = 0; 225892536c96SSara Sharon 225992536c96SSara Sharon return 0; 226092536c96SSara Sharon } 226192536c96SSara Sharon 2262d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2263e705c121SKalle Valo { 2264e705c121SKalle Valo struct iwl_txq *txq; 2265e705c121SKalle Valo unsigned long now = jiffies; 22662ae48edcSSara Sharon bool overflow_tx; 2267e705c121SKalle Valo u8 wr_ptr; 2268e705c121SKalle Valo 22692b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2270f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2271f60c9e59SEmmanuel Grumbach return -ENODEV; 22722b3fae66SMatt Chen 22734f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2274d6d517b7SSara Sharon return -EINVAL; 2275e705c121SKalle Valo 2276d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 22774f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 22782ae48edcSSara Sharon 22792ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22802ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22812ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22822ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22832ae48edcSSara Sharon 22846aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2285e705c121SKalle Valo 22862ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22872ae48edcSSara Sharon overflow_tx) && 2288e705c121SKalle Valo !time_after(jiffies, 2289e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22906aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2291e705c121SKalle Valo 22922ae48edcSSara Sharon /* 22932ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22942ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 22952ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 22962ae48edcSSara Sharon */ 22972ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2298e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2299e705c121SKalle Valo wr_ptr, write_ptr)) 2300e705c121SKalle Valo return -ETIMEDOUT; 23012ae48edcSSara Sharon wr_ptr = write_ptr; 23022ae48edcSSara Sharon 2303192185d6SJohannes Berg usleep_range(1000, 2000); 23042ae48edcSSara Sharon 23052ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23062ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23072ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23082ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2309e705c121SKalle Valo } 2310e705c121SKalle Valo 2311bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2312e705c121SKalle Valo IWL_ERR(trans, 2313d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 23140cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2315d6d517b7SSara Sharon return -ETIMEDOUT; 2316e705c121SKalle Valo } 2317e705c121SKalle Valo 2318d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2319d6d517b7SSara Sharon 2320d6d517b7SSara Sharon return 0; 2321d6d517b7SSara Sharon } 2322d6d517b7SSara Sharon 2323d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2324d6d517b7SSara Sharon { 2325d6d517b7SSara Sharon int cnt; 2326d6d517b7SSara Sharon int ret = 0; 2327d6d517b7SSara Sharon 2328d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 232979b6c8feSLuca Coelho for (cnt = 0; 2330286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 233179b6c8feSLuca Coelho cnt++) { 2332d6d517b7SSara Sharon 23334f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2334d6d517b7SSara Sharon continue; 23354f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2336d6d517b7SSara Sharon continue; 2337d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2338d6d517b7SSara Sharon continue; 2339d6d517b7SSara Sharon 2340d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 234138398efbSSara Sharon if (ret) 2342d6d517b7SSara Sharon break; 2343d6d517b7SSara Sharon } 2344e705c121SKalle Valo 2345e705c121SKalle Valo return ret; 2346e705c121SKalle Valo } 2347e705c121SKalle Valo 2348e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2349e705c121SKalle Valo u32 mask, u32 value) 2350e705c121SKalle Valo { 2351e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2352e705c121SKalle Valo 2353874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2354e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2355874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2356e705c121SKalle Valo } 2357e705c121SKalle Valo 2358e705c121SKalle Valo static const char *get_csr_string(int cmd) 2359e705c121SKalle Valo { 2360e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2361e705c121SKalle Valo switch (cmd) { 2362e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2363e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2364e705c121SKalle Valo IWL_CMD(CSR_INT); 2365e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2366e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2367e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2368e705c121SKalle Valo IWL_CMD(CSR_RESET); 2369e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2370e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2371e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2372e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2373e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2374e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2375e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2376e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2377e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2378e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2379e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2380e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2381e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2382e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2383e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2384e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2385e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2386e705c121SKalle Valo default: 2387e705c121SKalle Valo return "UNKNOWN"; 2388e705c121SKalle Valo } 2389e705c121SKalle Valo #undef IWL_CMD 2390e705c121SKalle Valo } 2391e705c121SKalle Valo 2392e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2393e705c121SKalle Valo { 2394e705c121SKalle Valo int i; 2395e705c121SKalle Valo static const u32 csr_tbl[] = { 2396e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2397e705c121SKalle Valo CSR_INT_COALESCING, 2398e705c121SKalle Valo CSR_INT, 2399e705c121SKalle Valo CSR_INT_MASK, 2400e705c121SKalle Valo CSR_FH_INT_STATUS, 2401e705c121SKalle Valo CSR_GPIO_IN, 2402e705c121SKalle Valo CSR_RESET, 2403e705c121SKalle Valo CSR_GP_CNTRL, 2404e705c121SKalle Valo CSR_HW_REV, 2405e705c121SKalle Valo CSR_EEPROM_REG, 2406e705c121SKalle Valo CSR_EEPROM_GP, 2407e705c121SKalle Valo CSR_OTP_GP_REG, 2408e705c121SKalle Valo CSR_GIO_REG, 2409e705c121SKalle Valo CSR_GP_UCODE_REG, 2410e705c121SKalle Valo CSR_GP_DRIVER_REG, 2411e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2412e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2413e705c121SKalle Valo CSR_LED_REG, 2414e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2415e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2416e705c121SKalle Valo CSR_ANA_PLL_CFG, 2417e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2418e705c121SKalle Valo CSR_HW_REV_WA_REG, 2419e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2420e705c121SKalle Valo }; 2421e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2422e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2423e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2424e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2425e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2426e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2427e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2428e705c121SKalle Valo } 2429e705c121SKalle Valo } 2430e705c121SKalle Valo 2431e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2432e705c121SKalle Valo /* create and remove of files */ 2433e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2434cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2435cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2436e705c121SKalle Valo } while (0) 2437e705c121SKalle Valo 2438e705c121SKalle Valo /* file operation */ 2439e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2440e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2441e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2442e705c121SKalle Valo .open = simple_open, \ 2443e705c121SKalle Valo .llseek = generic_file_llseek, \ 2444e705c121SKalle Valo }; 2445e705c121SKalle Valo 2446e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2447e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2448e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2449e705c121SKalle Valo .open = simple_open, \ 2450e705c121SKalle Valo .llseek = generic_file_llseek, \ 2451e705c121SKalle Valo }; 2452e705c121SKalle Valo 2453e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2454e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2455e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2456e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2457e705c121SKalle Valo .open = simple_open, \ 2458e705c121SKalle Valo .llseek = generic_file_llseek, \ 2459e705c121SKalle Valo }; 2460e705c121SKalle Valo 2461df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2462df67a1beSJohannes Berg struct iwl_trans *trans; 2463df67a1beSJohannes Berg }; 2464df67a1beSJohannes Berg 2465df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2466df67a1beSJohannes Berg loff_t pos; 2467df67a1beSJohannes Berg }; 2468df67a1beSJohannes Berg 2469df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2470e705c121SKalle Valo { 2471df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2472df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2473df67a1beSJohannes Berg 2474df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2475df67a1beSJohannes Berg return NULL; 2476df67a1beSJohannes Berg 2477df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2478df67a1beSJohannes Berg if (!state) 2479df67a1beSJohannes Berg return NULL; 2480df67a1beSJohannes Berg state->pos = *pos; 2481df67a1beSJohannes Berg return state; 2482df67a1beSJohannes Berg } 2483df67a1beSJohannes Berg 2484df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2485df67a1beSJohannes Berg void *v, loff_t *pos) 2486df67a1beSJohannes Berg { 2487df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2488df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2489df67a1beSJohannes Berg 2490df67a1beSJohannes Berg *pos = ++state->pos; 2491df67a1beSJohannes Berg 2492df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2493df67a1beSJohannes Berg return NULL; 2494df67a1beSJohannes Berg 2495df67a1beSJohannes Berg return state; 2496df67a1beSJohannes Berg } 2497df67a1beSJohannes Berg 2498df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2499df67a1beSJohannes Berg { 2500df67a1beSJohannes Berg kfree(v); 2501df67a1beSJohannes Berg } 2502df67a1beSJohannes Berg 2503df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2504df67a1beSJohannes Berg { 2505df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2506df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2507df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 25084f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2509e705c121SKalle Valo 2510df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2511df67a1beSJohannes Berg (unsigned int)state->pos, 25124f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 25134f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2514df67a1beSJohannes Berg if (txq) 2515df67a1beSJohannes Berg seq_printf(seq, 251695a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2517df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 251895a9e44fSJohannes Berg txq->need_update, txq->frozen, 251995a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2520df67a1beSJohannes Berg else 2521df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2522e705c121SKalle Valo 25234f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2524df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2525df67a1beSJohannes Berg seq_puts(seq, "\n"); 2526e705c121SKalle Valo 2527df67a1beSJohannes Berg return 0; 2528df67a1beSJohannes Berg } 2529df67a1beSJohannes Berg 2530df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2531df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2532df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2533df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2534df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2535df67a1beSJohannes Berg }; 2536df67a1beSJohannes Berg 2537df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2538df67a1beSJohannes Berg { 2539df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2540df67a1beSJohannes Berg 2541df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2542df67a1beSJohannes Berg sizeof(*priv)); 2543df67a1beSJohannes Berg 2544df67a1beSJohannes Berg if (!priv) 2545e705c121SKalle Valo return -ENOMEM; 2546e705c121SKalle Valo 2547df67a1beSJohannes Berg priv->trans = inode->i_private; 2548df67a1beSJohannes Berg return 0; 2549e705c121SKalle Valo } 2550e705c121SKalle Valo 2551e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2552e705c121SKalle Valo char __user *user_buf, 2553e705c121SKalle Valo size_t count, loff_t *ppos) 2554e705c121SKalle Valo { 2555e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2556e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 255778485054SSara Sharon char *buf; 255878485054SSara Sharon int pos = 0, i, ret; 2559eb3dc36eSColin Ian King size_t bufsz; 2560e705c121SKalle Valo 256178485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 256278485054SSara Sharon 256378485054SSara Sharon if (!trans_pcie->rxq) 256478485054SSara Sharon return -EAGAIN; 256578485054SSara Sharon 256678485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 256778485054SSara Sharon if (!buf) 256878485054SSara Sharon return -ENOMEM; 256978485054SSara Sharon 257078485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 257178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 257278485054SSara Sharon 257378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 257478485054SSara Sharon i); 257578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2576e705c121SKalle Valo rxq->read); 257778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2578e705c121SKalle Valo rxq->write); 257978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2580e705c121SKalle Valo rxq->write_actual); 258178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2582e705c121SKalle Valo rxq->need_update); 258378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2584e705c121SKalle Valo rxq->free_count); 2585e705c121SKalle Valo if (rxq->rb_stts) { 25860307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25870307c839SGolan Ben Ami rxq)); 258878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 258978485054SSara Sharon "\tclosed_rb_num: %u\n", 25900307c839SGolan Ben Ami r & 0x0FFF); 2591e705c121SKalle Valo } else { 2592e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 259378485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2594e705c121SKalle Valo } 259578485054SSara Sharon } 259678485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 259778485054SSara Sharon kfree(buf); 259878485054SSara Sharon 259978485054SSara Sharon return ret; 2600e705c121SKalle Valo } 2601e705c121SKalle Valo 2602e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2603e705c121SKalle Valo char __user *user_buf, 2604e705c121SKalle Valo size_t count, loff_t *ppos) 2605e705c121SKalle Valo { 2606e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2607e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2608e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2609e705c121SKalle Valo 2610e705c121SKalle Valo int pos = 0; 2611e705c121SKalle Valo char *buf; 2612e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2613e705c121SKalle Valo ssize_t ret; 2614e705c121SKalle Valo 2615e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2616e705c121SKalle Valo if (!buf) 2617e705c121SKalle Valo return -ENOMEM; 2618e705c121SKalle Valo 2619e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2620e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2621e705c121SKalle Valo 2622e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2623e705c121SKalle Valo isr_stats->hw); 2624e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2625e705c121SKalle Valo isr_stats->sw); 2626e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2627e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2628e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2629e705c121SKalle Valo isr_stats->err_code); 2630e705c121SKalle Valo } 2631e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2632e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2633e705c121SKalle Valo isr_stats->sch); 2634e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2635e705c121SKalle Valo isr_stats->alive); 2636e705c121SKalle Valo #endif 2637e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2638e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2639e705c121SKalle Valo 2640e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2641e705c121SKalle Valo isr_stats->ctkill); 2642e705c121SKalle Valo 2643e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2644e705c121SKalle Valo isr_stats->wakeup); 2645e705c121SKalle Valo 2646e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2647e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2648e705c121SKalle Valo 2649e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2650e705c121SKalle Valo isr_stats->tx); 2651e705c121SKalle Valo 2652e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2653e705c121SKalle Valo isr_stats->unhandled); 2654e705c121SKalle Valo 2655e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2656e705c121SKalle Valo kfree(buf); 2657e705c121SKalle Valo return ret; 2658e705c121SKalle Valo } 2659e705c121SKalle Valo 2660e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2661e705c121SKalle Valo const char __user *user_buf, 2662e705c121SKalle Valo size_t count, loff_t *ppos) 2663e705c121SKalle Valo { 2664e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2665e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2666e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2667e705c121SKalle Valo u32 reset_flag; 2668078f1131SJohannes Berg int ret; 2669e705c121SKalle Valo 2670078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2671078f1131SJohannes Berg if (ret) 2672078f1131SJohannes Berg return ret; 2673e705c121SKalle Valo if (reset_flag == 0) 2674e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2675e705c121SKalle Valo 2676e705c121SKalle Valo return count; 2677e705c121SKalle Valo } 2678e705c121SKalle Valo 2679e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2680e705c121SKalle Valo const char __user *user_buf, 2681e705c121SKalle Valo size_t count, loff_t *ppos) 2682e705c121SKalle Valo { 2683e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2684e705c121SKalle Valo 2685e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2686e705c121SKalle Valo 2687e705c121SKalle Valo return count; 2688e705c121SKalle Valo } 2689e705c121SKalle Valo 2690e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2691e705c121SKalle Valo char __user *user_buf, 2692e705c121SKalle Valo size_t count, loff_t *ppos) 2693e705c121SKalle Valo { 2694e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2695e705c121SKalle Valo char *buf = NULL; 2696e705c121SKalle Valo ssize_t ret; 2697e705c121SKalle Valo 2698e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2699e705c121SKalle Valo if (ret < 0) 2700e705c121SKalle Valo return ret; 2701e705c121SKalle Valo if (!buf) 2702e705c121SKalle Valo return -EINVAL; 2703e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2704e705c121SKalle Valo kfree(buf); 2705e705c121SKalle Valo return ret; 2706e705c121SKalle Valo } 2707e705c121SKalle Valo 2708fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2709fa4de7f7SJohannes Berg char __user *user_buf, 2710fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2711fa4de7f7SJohannes Berg { 2712fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2713fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2714fa4de7f7SJohannes Berg char buf[100]; 2715fa4de7f7SJohannes Berg int pos; 2716fa4de7f7SJohannes Berg 2717fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2718fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2719fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2720fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2721fa4de7f7SJohannes Berg 2722fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2723fa4de7f7SJohannes Berg } 2724fa4de7f7SJohannes Berg 2725fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2726fa4de7f7SJohannes Berg const char __user *user_buf, 2727fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2728fa4de7f7SJohannes Berg { 2729fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2730fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2731c5bf4fa1SJohannes Berg bool new_value; 2732fa4de7f7SJohannes Berg int ret; 2733fa4de7f7SJohannes Berg 2734c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2735fa4de7f7SJohannes Berg if (ret) 2736fa4de7f7SJohannes Berg return ret; 2737c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2738fa4de7f7SJohannes Berg return count; 2739fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2740c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2741c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2742fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2743fa4de7f7SJohannes Berg 2744fa4de7f7SJohannes Berg return count; 2745fa4de7f7SJohannes Berg } 2746fa4de7f7SJohannes Berg 2747f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2748f7805b33SLior Cohen struct file *file) 2749f7805b33SLior Cohen { 2750f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2751f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2752f7805b33SLior Cohen 275391c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 275491c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2755f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2756f7805b33SLior Cohen return -ENOENT; 2757f7805b33SLior Cohen } 2758f7805b33SLior Cohen 2759f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2760f7805b33SLior Cohen return -EBUSY; 2761f7805b33SLior Cohen 2762f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2763f7805b33SLior Cohen return simple_open(inode, file); 2764f7805b33SLior Cohen } 2765f7805b33SLior Cohen 2766f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2767f7805b33SLior Cohen struct file *file) 2768f7805b33SLior Cohen { 2769f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2770f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2771f7805b33SLior Cohen 2772f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2773f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2774f7805b33SLior Cohen return 0; 2775f7805b33SLior Cohen } 2776f7805b33SLior Cohen 2777f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2778f7805b33SLior Cohen void *buf, ssize_t *size, 2779f7805b33SLior Cohen ssize_t *bytes_copied) 2780f7805b33SLior Cohen { 2781f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2782f7805b33SLior Cohen 2783f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2784f7805b33SLior Cohen if (*size > buf_size_left) 2785f7805b33SLior Cohen *size = buf_size_left; 2786f7805b33SLior Cohen 2787f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2788f7805b33SLior Cohen *bytes_copied += *size; 2789f7805b33SLior Cohen 2790f7805b33SLior Cohen if (buf_size_left == *size) 2791f7805b33SLior Cohen return true; 2792f7805b33SLior Cohen return false; 2793f7805b33SLior Cohen } 2794f7805b33SLior Cohen 2795f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2796f7805b33SLior Cohen char __user *user_buf, 2797f7805b33SLior Cohen size_t count, loff_t *ppos) 2798f7805b33SLior Cohen { 2799f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2800f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 280169f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2802f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2803f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2804f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2805f7805b33SLior Cohen bool b_full; 2806f7805b33SLior Cohen 280791c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2808f7805b33SLior Cohen write_ptr_addr = 280991c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 281091c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2811f7805b33SLior Cohen } else { 2812f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2813f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2814f7805b33SLior Cohen } 2815f7805b33SLior Cohen 281691c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2817f7805b33SLior Cohen return 0; 2818f7805b33SLior Cohen 2819f7805b33SLior Cohen mutex_lock(&data->mutex); 2820f7805b33SLior Cohen if (data->state == 2821f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2822f7805b33SLior Cohen mutex_unlock(&data->mutex); 2823f7805b33SLior Cohen return 0; 2824f7805b33SLior Cohen } 2825f7805b33SLior Cohen 2826f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2827f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2828f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2829f7805b33SLior Cohen 2830f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2831f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2832f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2833f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2834f7805b33SLior Cohen curr_buf, &size, 2835f7805b33SLior Cohen &bytes_copied); 2836f7805b33SLior Cohen data->prev_wr_ptr += size; 2837f7805b33SLior Cohen 2838f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2839f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 284069f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2841f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2842f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2843f7805b33SLior Cohen curr_buf, &size, 2844f7805b33SLior Cohen &bytes_copied); 2845f7805b33SLior Cohen data->prev_wr_ptr += size; 2846f7805b33SLior Cohen 2847f7805b33SLior Cohen if (!b_full) { 2848f7805b33SLior Cohen size = write_ptr; 2849f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2850f7805b33SLior Cohen cpu_addr, &size, 2851f7805b33SLior Cohen &bytes_copied); 2852f7805b33SLior Cohen data->prev_wr_ptr = size; 2853f7805b33SLior Cohen data->prev_wrap_cnt++; 2854f7805b33SLior Cohen } 2855f7805b33SLior Cohen } else { 2856f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2857f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2858f7805b33SLior Cohen IWL_WARN(trans, 2859f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2860f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2861f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2862f7805b33SLior Cohen IWL_WARN(trans, 2863f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2864f7805b33SLior Cohen 2865f7805b33SLior Cohen size = write_ptr; 2866f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2867f7805b33SLior Cohen cpu_addr, &size, 2868f7805b33SLior Cohen &bytes_copied); 2869f7805b33SLior Cohen data->prev_wr_ptr = size; 2870f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2871f7805b33SLior Cohen } 2872f7805b33SLior Cohen 2873f7805b33SLior Cohen mutex_unlock(&data->mutex); 2874f7805b33SLior Cohen 2875f7805b33SLior Cohen return bytes_copied; 2876f7805b33SLior Cohen } 2877f7805b33SLior Cohen 2878aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 2879aa899e68SJohannes Berg char __user *user_buf, 2880aa899e68SJohannes Berg size_t count, loff_t *ppos) 2881aa899e68SJohannes Berg { 2882aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 2883aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2884aa899e68SJohannes Berg 2885aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 2886aa899e68SJohannes Berg return -ENODEV; 2887aa899e68SJohannes Berg 2888aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 2889aa899e68SJohannes Berg trans_pcie->rf_name, 2890aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 2891aa899e68SJohannes Berg } 2892aa899e68SJohannes Berg 2893e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2894e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2895e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2896e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2897fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2898aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 2899aa899e68SJohannes Berg 2900df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2901df67a1beSJohannes Berg .owner = THIS_MODULE, 2902df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2903df67a1beSJohannes Berg .read = seq_read, 2904df67a1beSJohannes Berg .llseek = seq_lseek, 2905df67a1beSJohannes Berg .release = seq_release_private, 2906df67a1beSJohannes Berg }; 2907e705c121SKalle Valo 2908f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2909f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2910f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2911f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2912f7805b33SLior Cohen }; 2913f7805b33SLior Cohen 2914f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2915cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2916e705c121SKalle Valo { 2917f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2918f8a1edb7SJohannes Berg 29192ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 29202ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 29212ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 29222ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 29232ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 29242ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2925f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2926aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 2927e705c121SKalle Valo } 2928f7805b33SLior Cohen 2929f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2930f7805b33SLior Cohen { 2931f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2932f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2933f7805b33SLior Cohen 2934f7805b33SLior Cohen mutex_lock(&data->mutex); 2935f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2936f7805b33SLior Cohen mutex_unlock(&data->mutex); 2937f7805b33SLior Cohen } 2938e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2939e705c121SKalle Valo 29406983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2941e705c121SKalle Valo { 2942e705c121SKalle Valo u32 cmdlen = 0; 2943e705c121SKalle Valo int i; 2944e705c121SKalle Valo 2945885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 29460179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 2947e705c121SKalle Valo 2948e705c121SKalle Valo return cmdlen; 2949e705c121SKalle Valo } 2950e705c121SKalle Valo 2951e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2952e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2953e705c121SKalle Valo int allocated_rb_nums) 2954e705c121SKalle Valo { 2955e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 295680084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 295778485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 295878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2959e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2960e705c121SKalle Valo 2961e705c121SKalle Valo spin_lock(&rxq->lock); 2962e705c121SKalle Valo 29630307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2964e705c121SKalle Valo 2965e705c121SKalle Valo for (i = rxq->read, j = 0; 2966e705c121SKalle Valo i != r && j < allocated_rb_nums; 2967e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2968e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2969e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2970e705c121SKalle Valo 297159a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 297259a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 2973e705c121SKalle Valo 2974e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2975e705c121SKalle Valo 2976e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2977e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2978e705c121SKalle Valo rb = (void *)(*data)->data; 2979e705c121SKalle Valo rb->index = cpu_to_le32(i); 2980e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2981e705c121SKalle Valo 2982e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2983e705c121SKalle Valo } 2984e705c121SKalle Valo 2985e705c121SKalle Valo spin_unlock(&rxq->lock); 2986e705c121SKalle Valo 2987e705c121SKalle Valo return rb_len; 2988e705c121SKalle Valo } 2989e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2990e705c121SKalle Valo 2991e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2992e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2993e705c121SKalle Valo { 2994e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2995e705c121SKalle Valo __le32 *val; 2996e705c121SKalle Valo int i; 2997e705c121SKalle Valo 2998e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2999e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3000e705c121SKalle Valo val = (void *)(*data)->data; 3001e705c121SKalle Valo 3002e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3003e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3004e705c121SKalle Valo 3005e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3006e705c121SKalle Valo 3007e705c121SKalle Valo return csr_len; 3008e705c121SKalle Valo } 3009e705c121SKalle Valo 3010e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3011e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3012e705c121SKalle Valo { 3013e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3014e705c121SKalle Valo __le32 *val; 3015e705c121SKalle Valo int i; 3016e705c121SKalle Valo 30171ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3018e705c121SKalle Valo return 0; 3019e705c121SKalle Valo 3020e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3021e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3022e705c121SKalle Valo val = (void *)(*data)->data; 3023e705c121SKalle Valo 3024286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3025723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3026723b45e2SLiad Kaufman i += sizeof(u32)) 3027e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3028723b45e2SLiad Kaufman else 3029ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3030ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3031723b45e2SLiad Kaufman i += sizeof(u32)) 3032723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3033723b45e2SLiad Kaufman i)); 3034e705c121SKalle Valo 30351ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3036e705c121SKalle Valo 3037e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3038e705c121SKalle Valo 3039e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3040e705c121SKalle Valo } 3041e705c121SKalle Valo 3042e705c121SKalle Valo static u32 3043e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3044e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3045e705c121SKalle Valo u32 monitor_len) 3046e705c121SKalle Valo { 3047e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3048e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3049e705c121SKalle Valo u32 i; 3050e705c121SKalle Valo 30511ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3052e705c121SKalle Valo return 0; 3053e705c121SKalle Valo 3054ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3055e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3056ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 305714ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3058ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3059e705c121SKalle Valo 30601ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3061e705c121SKalle Valo 3062e705c121SKalle Valo return monitor_len; 3063e705c121SKalle Valo } 3064e705c121SKalle Valo 30657a14c23dSSara Sharon static void 30667a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30677a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30687a14c23dSSara Sharon { 3069c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30707a14c23dSSara Sharon 3071286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3072c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3073c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3074c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3075c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 307691c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 307791c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 307891c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 307991c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30807a14c23dSSara Sharon } else { 30817a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30827a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30837a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30847a14c23dSSara Sharon } 3085c88580e1SShahar S Matityahu 3086c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30877a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30887a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30897a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30907a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3091286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3092c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3093c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3094c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3095cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3096cc598782SRotem Saado write_ptr_val >>= 2; 3097c88580e1SShahar S Matityahu } 3098c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30997a14c23dSSara Sharon } 31007a14c23dSSara Sharon 3101e705c121SKalle Valo static u32 3102e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3103e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3104e705c121SKalle Valo u32 monitor_len) 3105e705c121SKalle Valo { 310669f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3107e705c121SKalle Valo u32 len = 0; 3108e705c121SKalle Valo 310991c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 311069f0e505SShahar S Matityahu (fw_mon->size && 3111286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3112286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3113e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3114e705c121SKalle Valo 3115e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3116e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 31177a14c23dSSara Sharon 31187a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3119e705c121SKalle Valo 3120e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 312169f0e505SShahar S Matityahu if (fw_mon->size) { 312269f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 312369f0e505SShahar S Matityahu monitor_len = fw_mon->size; 312491c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 31257a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3126e705c121SKalle Valo /* 3127e705c121SKalle Valo * Update pointers to reflect actual values after 3128e705c121SKalle Valo * shifting 3129e705c121SKalle Valo */ 313091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3131fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3132fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 313391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3134fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3135fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3136fd527eb5SGolan Ben Ami } else { 3137e705c121SKalle Valo base = iwl_read_prph(trans, base) << 313891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3139fd527eb5SGolan Ben Ami } 3140fd527eb5SGolan Ben Ami 3141e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3142e705c121SKalle Valo monitor_len / sizeof(u32)); 314391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3144e705c121SKalle Valo monitor_len = 3145e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3146e705c121SKalle Valo fw_mon_data, 3147e705c121SKalle Valo monitor_len); 3148e705c121SKalle Valo } else { 3149e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3150e705c121SKalle Valo monitor_len = 0; 3151e705c121SKalle Valo } 3152e705c121SKalle Valo 3153e705c121SKalle Valo len += monitor_len; 3154e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3155e705c121SKalle Valo } 3156e705c121SKalle Valo 3157e705c121SKalle Valo return len; 3158e705c121SKalle Valo } 3159e705c121SKalle Valo 316093079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3161e705c121SKalle Valo { 316269f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3163da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3164da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 316569f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 316669f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 316791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3168da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3169e705c121SKalle Valo 317091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 317191c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3172fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3173fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 317491c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3175fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3176fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3177fd527eb5SGolan Ben Ami 3178fd527eb5SGolan Ben Ami monitor_len = 3179fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 318091c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3181fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3182fd527eb5SGolan Ben Ami } else { 318391c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 318491c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3185e705c121SKalle Valo 3186e705c121SKalle Valo base = iwl_read_prph(trans, base) << 318791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3188e705c121SKalle Valo end = iwl_read_prph(trans, end) << 318991c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3190e705c121SKalle Valo 3191e705c121SKalle Valo /* Make "end" point to the actual end */ 3192286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3193fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 319491c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 319591c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3196e705c121SKalle Valo monitor_len = end - base; 3197fd527eb5SGolan Ben Ami } 3198da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3199da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3200e705c121SKalle Valo monitor_len; 3201da752717SShahar S Matityahu return monitor_len; 3202e705c121SKalle Valo } 3203da752717SShahar S Matityahu return 0; 3204da752717SShahar S Matityahu } 3205da752717SShahar S Matityahu 3206*fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3207*fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3208*fdb70083SJohannes Berg u32 dump_mask, 3209*fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3210*fdb70083SJohannes Berg void *sanitize_ctx) 3211da752717SShahar S Matityahu { 3212da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3213da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 32144f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3215da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3216da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3217fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3218da752717SShahar S Matityahu int i, ptr; 3219da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3220286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 322179f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 322279f033f6SSara Sharon 322379f033f6SSara Sharon if (!dump_mask) 322479f033f6SSara Sharon return NULL; 3225da752717SShahar S Matityahu 3226da752717SShahar S Matityahu /* transport dump header */ 3227da752717SShahar S Matityahu len = sizeof(*dump_data); 3228da752717SShahar S Matityahu 3229da752717SShahar S Matityahu /* host commands */ 3230e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3231da752717SShahar S Matityahu len += sizeof(*data) + 32328672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 32338672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3234da752717SShahar S Matityahu 3235da752717SShahar S Matityahu /* FW monitor */ 3236fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3237da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3238e705c121SKalle Valo 3239e705c121SKalle Valo /* CSR registers */ 324079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3241e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3242e705c121SKalle Valo 3243e705c121SKalle Valo /* FH registers */ 324479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3245286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3246723b45e2SLiad Kaufman len += sizeof(*data) + 3247ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3248ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3249723b45e2SLiad Kaufman else 3250723b45e2SLiad Kaufman len += sizeof(*data) + 3251520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3252520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3253520f03eaSShahar S Matityahu } 3254e705c121SKalle Valo 3255e705c121SKalle Valo if (dump_rbs) { 325678485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 325778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3258e705c121SKalle Valo /* RBs */ 32590307c839SGolan Ben Ami num_rbs = 32600307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3261e705c121SKalle Valo & 0x0FFF; 326278485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3263e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3264e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3265e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3266e705c121SKalle Valo } 3267e705c121SKalle Valo 32685538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3269286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3270505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32715538409bSLiad Kaufman len += sizeof(*data) + 32725538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3273505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32745538409bSLiad Kaufman 3275e705c121SKalle Valo dump_data = vzalloc(len); 3276e705c121SKalle Valo if (!dump_data) 3277e705c121SKalle Valo return NULL; 3278e705c121SKalle Valo 3279e705c121SKalle Valo len = 0; 3280e705c121SKalle Valo data = (void *)dump_data->data; 3281520f03eaSShahar S Matityahu 3282e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3283885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3284520f03eaSShahar S Matityahu 3285e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3286e705c121SKalle Valo txcmd = (void *)data->data; 3287e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3288bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3289bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32900cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 329108326a97SJohannes Berg u8 tfdidx; 3292e705c121SKalle Valo u32 caplen, cmdlen; 3293e705c121SKalle Valo 329408326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 329508326a97SJohannes Berg tfdidx = idx; 329608326a97SJohannes Berg else 329708326a97SJohannes Berg tfdidx = ptr; 329808326a97SJohannes Berg 3299520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 330008326a97SJohannes Berg (u8 *)cmdq->tfds + 330108326a97SJohannes Berg tfd_size * tfdidx); 3302e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3303e705c121SKalle Valo 3304e705c121SKalle Valo if (cmdlen) { 3305e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3306e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3307e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3308520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3309520f03eaSShahar S Matityahu caplen); 3310*fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3311*fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3312*fdb70083SJohannes Berg txcmd->data, 3313*fdb70083SJohannes Berg caplen); 3314e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3315e705c121SKalle Valo } 3316e705c121SKalle Valo 33170cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3318e705c121SKalle Valo } 3319e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3320e705c121SKalle Valo 3321e705c121SKalle Valo data->len = cpu_to_le32(len); 3322e705c121SKalle Valo len += sizeof(*data); 3323e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3324520f03eaSShahar S Matityahu } 3325e705c121SKalle Valo 332679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3327e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 332879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3329e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3330e705c121SKalle Valo if (dump_rbs) 3331e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3332e705c121SKalle Valo 33335538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3334286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 333579b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3336505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 33375538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3338505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 33395538409bSLiad Kaufman 33405538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 33415538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 33425538409bSLiad Kaufman paging = (void *)data->data; 33435538409bSLiad Kaufman paging->index = cpu_to_le32(i); 33445538409bSLiad Kaufman memcpy(paging->data, 3345505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 33465538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33475538409bSLiad Kaufman 33485538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33495538409bSLiad Kaufman } 33505538409bSLiad Kaufman } 335179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3352e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3353e705c121SKalle Valo 3354e705c121SKalle Valo dump_data->len = len; 3355e705c121SKalle Valo 3356e705c121SKalle Valo return dump_data; 3357e705c121SKalle Valo } 3358e705c121SKalle Valo 33593161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 33604cbb8e50SLuciano Coelho { 33613161a34dSMordechay Goodstein if (enable) 33623161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 33633161a34dSMordechay Goodstein else 33643161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 33654cbb8e50SLuciano Coelho } 33664cbb8e50SLuciano Coelho 33673161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 33684cbb8e50SLuciano Coelho { 33693161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 33703161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 33713161a34dSMordechay Goodstein 33723161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 33733161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 33743161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 33753161a34dSMordechay Goodstein } else { 33763161a34dSMordechay Goodstein inta_addr = CSR_INT; 33773161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 33784cbb8e50SLuciano Coelho } 33793161a34dSMordechay Goodstein 33803161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 33813161a34dSMordechay Goodstein } 33824cbb8e50SLuciano Coelho 3383623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3384623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3385623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3386623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3387623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3388623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3389623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3390623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3391623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 33927f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3393623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3394623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3395870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3396623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3397623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3398623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3399623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3400623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3401d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 34023161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 34033161a34dSMordechay Goodstein .sync_nmi = iwl_trans_pcie_sync_nmi \ 3404623e7766SSara Sharon 3405e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3406623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3407e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3408e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3409e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3410e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3411e705c121SKalle Valo 341213f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3413e705c121SKalle Valo 3414e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3415a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3416e705c121SKalle Valo 3417e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3418e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3419e705c121SKalle Valo 342042db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 342142db09c1SLiad Kaufman 3422d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3423d6d517b7SSara Sharon 3424a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 34250cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3426f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3427f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3428f7805b33SLior Cohen #endif 3429623e7766SSara Sharon }; 3430e705c121SKalle Valo 3431623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3432623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3433623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3434eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3435eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 343677c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3437e705c121SKalle Valo 343813f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3439e705c121SKalle Valo 34400cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3441a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3442623e7766SSara Sharon 3443a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3444ba7136f3SAlex Malamud 34450cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 34460cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3447d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 344892536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 34496654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 34509dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3451f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3452f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3453f7805b33SLior Cohen #endif 3454e705c121SKalle Valo }; 3455e705c121SKalle Valo 3456e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3457e705c121SKalle Valo const struct pci_device_id *ent, 34587e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3459e705c121SKalle Valo { 3460e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3461e705c121SKalle Valo struct iwl_trans *trans; 3462fda1bd0dSMordechay Goodstein int ret, addr_size; 3463a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3464f00c3f9eSJohannes Berg void __iomem * const *table; 3465a89c72ffSJohannes Berg 3466fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3467a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3468e705c121SKalle Valo 34695a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 34705a41a86cSSharon Dvir if (ret) 34715a41a86cSSharon Dvir return ERR_PTR(ret); 34725a41a86cSSharon Dvir 3473a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3474fda1bd0dSMordechay Goodstein cfg_trans); 3475e705c121SKalle Valo if (!trans) 3476e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3477e705c121SKalle Valo 3478e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3479e705c121SKalle Valo 3480e705c121SKalle Valo trans_pcie->trans = trans; 3481326477e4SJohannes Berg trans_pcie->opmode_down = true; 3482e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3483e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3484cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3485e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3486e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3487906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 34888188a18eSJohannes Berg 34898188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 34908188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 34918188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 34928188a18eSJohannes Berg ret = -ENOMEM; 34938188a18eSJohannes Berg goto out_free_trans; 34948188a18eSJohannes Berg } 34958188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 34968188a18eSJohannes Berg 3497c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3498e705c121SKalle Valo 34997e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3500e705c121SKalle Valo /* 3501e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3502e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3503e705c121SKalle Valo * lot of power. 3504e705c121SKalle Valo */ 3505e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3506e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3507e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3508e705c121SKalle Valo } 3509e705c121SKalle Valo 35109416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 35119416560eSGolan Ben Ami 3512e705c121SKalle Valo pci_set_master(pdev); 3513e705c121SKalle Valo 3514885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3515ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3516e705c121SKalle Valo if (ret) { 3517ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3518e705c121SKalle Valo /* both attempts failed: */ 3519e705c121SKalle Valo if (ret) { 3520e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 35215a41a86cSSharon Dvir goto out_no_pci; 3522e705c121SKalle Valo } 3523e705c121SKalle Valo } 3524e705c121SKalle Valo 35255a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3526e705c121SKalle Valo if (ret) { 35275a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 35285a41a86cSSharon Dvir goto out_no_pci; 3529e705c121SKalle Valo } 3530e705c121SKalle Valo 3531f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3532f00c3f9eSJohannes Berg if (!table) { 35335a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3534f00c3f9eSJohannes Berg ret = -ENOMEM; 3535f00c3f9eSJohannes Berg goto out_no_pci; 3536f00c3f9eSJohannes Berg } 3537f00c3f9eSJohannes Berg 3538f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3539f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3540f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3541e705c121SKalle Valo ret = -ENODEV; 35425a41a86cSSharon Dvir goto out_no_pci; 3543e705c121SKalle Valo } 3544e705c121SKalle Valo 3545e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3546e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3547e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3548e705c121SKalle Valo 3549e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3550e705c121SKalle Valo iwl_disable_interrupts(trans); 3551e705c121SKalle Valo 3552e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35539a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35549a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35559a098a89SRajat Jain ret = -EIO; 35569a098a89SRajat Jain goto out_no_pci; 35579a098a89SRajat Jain } 35589a098a89SRajat Jain 3559e705c121SKalle Valo /* 3560e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3561e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3562e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3563e705c121SKalle Valo * in the old format. 3564e705c121SKalle Valo */ 35654adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3566e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3567e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3568e705c121SKalle Valo 356999be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 357099be6166SLuca Coelho 35717e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3572e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3573e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3574e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3575e705c121SKalle Valo 3576e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3577e5f3f215SHaim Dreyfuss 3578c239feecSJohannes Berg 35792e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 35802388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 35812388bd7bSDan Carpenter if (ret) 35825a41a86cSSharon Dvir goto out_no_pci; 35832e5d4a8fSHaim Dreyfuss } else { 3584e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3585e705c121SKalle Valo if (ret) 35865a41a86cSSharon Dvir goto out_no_pci; 3587e705c121SKalle Valo 35885a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 35895a41a86cSSharon Dvir iwl_pcie_isr, 3590e705c121SKalle Valo iwl_pcie_irq_handler, 3591e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3592e705c121SKalle Valo if (ret) { 3593e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3594e705c121SKalle Valo goto out_free_ict; 3595e705c121SKalle Valo } 35962e5d4a8fSHaim Dreyfuss } 3597e705c121SKalle Valo 3598f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3599f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3600f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3601f7805b33SLior Cohen #endif 3602f7805b33SLior Cohen 3603a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3604a9248de4SShahar S Matityahu 3605e705c121SKalle Valo return trans; 3606e705c121SKalle Valo 3607e705c121SKalle Valo out_free_ict: 3608e705c121SKalle Valo iwl_pcie_free_ict(trans); 3609e705c121SKalle Valo out_no_pci: 36108188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 36118188a18eSJohannes Berg out_free_trans: 3612e705c121SKalle Valo iwl_trans_free(trans); 3613e705c121SKalle Valo return ERR_PTR(ret); 3614e705c121SKalle Valo } 3615