18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 3583c58e3SJohannes Berg * Copyright (C) 2007-2015, 2018-2023 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 276d19a5ebSEmmanuel Grumbach #include "mei/iwl-mei.h" 28e705c121SKalle Valo #include "internal.h" 29e705c121SKalle Valo #include "iwl-fh.h" 306654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 31e705c121SKalle Valo 32e705c121SKalle Valo /* extended range in FW SRAM */ 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 34e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35e705c121SKalle Valo 364290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37a6d24fadSRajat Jain { 38c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 39c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 40c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 41a6d24fadSRajat Jain #define PREFIX_LEN 32 42a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 44a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 45a6d24fadSRajat Jain char *prefix; 46a6d24fadSRajat Jain 47a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 48a6d24fadSRajat Jain return; 49a6d24fadSRajat Jain 50a6d24fadSRajat Jain /* Should be a multiple of 4 */ 51a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54c4d3f2eeSLuca Coelho 55a6d24fadSRajat Jain /* Alloc a max size buffer */ 56a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60c4d3f2eeSLuca Coelho 61a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 62a6d24fadSRajat Jain if (!buf) 63a6d24fadSRajat Jain return; 64a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 65a6d24fadSRajat Jain 66a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67a6d24fadSRajat Jain 68a6d24fadSRajat Jain /* Print wifi device registers */ 69a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 71a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 73a6d24fadSRajat Jain goto err_read; 74a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75a6d24fadSRajat Jain 76a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 79a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80a6d24fadSRajat Jain 81a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82a6d24fadSRajat Jain if (pos) { 83a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 86a6d24fadSRajat Jain goto err_read; 87a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88a6d24fadSRajat Jain 32, 4, buf, i, 0); 89a6d24fadSRajat Jain } 90a6d24fadSRajat Jain 91a6d24fadSRajat Jain /* Print parent device registers next */ 92a6d24fadSRajat Jain if (!pdev->bus->self) 93a6d24fadSRajat Jain goto out; 94a6d24fadSRajat Jain 95a6d24fadSRajat Jain pdev = pdev->bus->self; 96a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97a6d24fadSRajat Jain 98a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99a6d24fadSRajat Jain pci_name(pdev)); 100c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 102a6d24fadSRajat Jain goto err_read; 103a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Print root port AER registers */ 106a6d24fadSRajat Jain pos = 0; 107a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 108a6d24fadSRajat Jain if (pdev) 109a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110a6d24fadSRajat Jain if (pos) { 111a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112a6d24fadSRajat Jain pci_name(pdev)); 113a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 116a6d24fadSRajat Jain goto err_read; 117a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118a6d24fadSRajat Jain 4, buf, i, 0); 119a6d24fadSRajat Jain } 120f3402d6dSSara Sharon goto out; 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain err_read: 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 125a6d24fadSRajat Jain out: 126a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 127a6d24fadSRajat Jain kfree(buf); 128a6d24fadSRajat Jain } 129a6d24fadSRajat Jain 13015bf5ac6SJohannes Berg static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 13115bf5ac6SJohannes Berg bool retake_ownership) 132870c2a11SGolan Ben Ami { 133870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 134ec80c231SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1351b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_GP_CNTRL, 1361b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_SW_RESET); 137ec80c231SJohannes Berg usleep_range(10000, 20000); 138ec80c231SJohannes Berg } else { 1391b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_RESET, 1401b6598c3SRoee Goldfiner CSR_RESET_REG_FLAG_SW_RESET); 141870c2a11SGolan Ben Ami usleep_range(5000, 6000); 142ec80c231SJohannes Berg } 14315bf5ac6SJohannes Berg 14415bf5ac6SJohannes Berg if (retake_ownership) 14515bf5ac6SJohannes Berg return iwl_pcie_prepare_card_hw(trans); 14615bf5ac6SJohannes Berg 14715bf5ac6SJohannes Berg return 0; 148870c2a11SGolan Ben Ami } 149870c2a11SGolan Ben Ami 150e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 151e705c121SKalle Valo { 15269f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 153e705c121SKalle Valo 15469f0e505SShahar S Matityahu if (!fw_mon->size) 15569f0e505SShahar S Matityahu return; 15669f0e505SShahar S Matityahu 15769f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 15869f0e505SShahar S Matityahu fw_mon->physical); 15969f0e505SShahar S Matityahu 16069f0e505SShahar S Matityahu fw_mon->block = NULL; 16169f0e505SShahar S Matityahu fw_mon->physical = 0; 16269f0e505SShahar S Matityahu fw_mon->size = 0; 163e705c121SKalle Valo } 164e705c121SKalle Valo 16588964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 166855e2f60SJohannes Berg u8 max_power) 167e705c121SKalle Valo { 16869f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 16969f0e505SShahar S Matityahu void *block = NULL; 17069f0e505SShahar S Matityahu dma_addr_t physical = 0; 171e705c121SKalle Valo u32 size = 0; 172e705c121SKalle Valo u8 power; 173e705c121SKalle Valo 174583c58e3SJohannes Berg if (fw_mon->size) { 175583c58e3SJohannes Berg memset(fw_mon->block, 0, fw_mon->size); 17669f0e505SShahar S Matityahu return; 177583c58e3SJohannes Berg } 17869f0e505SShahar S Matityahu 179855e2f60SJohannes Berg /* need at least 2 KiB, so stop at 11 */ 180855e2f60SJohannes Berg for (power = max_power; power >= 11; power--) { 181e705c121SKalle Valo size = BIT(power); 18269f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1832d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 18469f0e505SShahar S Matityahu if (!block) 185e705c121SKalle Valo continue; 186e705c121SKalle Valo 187e705c121SKalle Valo IWL_INFO(trans, 188c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 189c5f97542SShahar S Matityahu size); 190e705c121SKalle Valo break; 191e705c121SKalle Valo } 192e705c121SKalle Valo 19369f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 194e705c121SKalle Valo return; 195e705c121SKalle Valo 196e705c121SKalle Valo if (power != max_power) 197e705c121SKalle Valo IWL_ERR(trans, 198e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 199e705c121SKalle Valo (unsigned long)BIT(power - 10), 200e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 201e705c121SKalle Valo 20269f0e505SShahar S Matityahu fw_mon->block = block; 20369f0e505SShahar S Matityahu fw_mon->physical = physical; 20469f0e505SShahar S Matityahu fw_mon->size = size; 20588964b2eSSara Sharon } 20688964b2eSSara Sharon 20788964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 20888964b2eSSara Sharon { 20988964b2eSSara Sharon if (!max_power) { 21088964b2eSSara Sharon /* default max_power is maximum */ 21188964b2eSSara Sharon max_power = 26; 21288964b2eSSara Sharon } else { 21388964b2eSSara Sharon max_power += 11; 21488964b2eSSara Sharon } 21588964b2eSSara Sharon 21688964b2eSSara Sharon if (WARN(max_power > 26, 21788964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 21888964b2eSSara Sharon max_power)) 21988964b2eSSara Sharon return; 22088964b2eSSara Sharon 221855e2f60SJohannes Berg iwl_pcie_alloc_fw_monitor_block(trans, max_power); 222e705c121SKalle Valo } 223e705c121SKalle Valo 224e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 225e705c121SKalle Valo { 226e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 227e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 228e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 229e705c121SKalle Valo } 230e705c121SKalle Valo 231e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 232e705c121SKalle Valo { 233e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 234e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 235e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 236e705c121SKalle Valo } 237e705c121SKalle Valo 238e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 239e705c121SKalle Valo { 240e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 241e705c121SKalle Valo return; 242e705c121SKalle Valo 243e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 244e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 245e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 246e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 247e705c121SKalle Valo else 248e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 249e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 250e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 251e705c121SKalle Valo } 252e705c121SKalle Valo 253e705c121SKalle Valo /* PCI registers */ 254e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 255e705c121SKalle Valo 256eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 257e705c121SKalle Valo { 258e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 259e705c121SKalle Valo u16 lctl; 260e705c121SKalle Valo u16 cap; 261e705c121SKalle Valo 262e705c121SKalle Valo /* 263cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 264cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 265cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 266e705c121SKalle Valo */ 2673d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 268cc894b85SLuca Coelho 269cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 270e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 271e705c121SKalle Valo 272e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 273e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 274d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 275e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 276e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 277e705c121SKalle Valo } 278e705c121SKalle Valo 279e705c121SKalle Valo /* 280e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 281e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 282e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 283e705c121SKalle Valo */ 284e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 285e705c121SKalle Valo { 28652b6e168SEmmanuel Grumbach int ret; 28752b6e168SEmmanuel Grumbach 288e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 289e705c121SKalle Valo 290e705c121SKalle Valo /* 291e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 292e705c121SKalle Valo * bits already set by default after reset. 293e705c121SKalle Valo */ 294e705c121SKalle Valo 295e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 296286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 297e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 298e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 299e705c121SKalle Valo 300e705c121SKalle Valo /* 301e705c121SKalle Valo * Disable L0s without affecting L1; 302e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 303e705c121SKalle Valo */ 304e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 305e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 306e705c121SKalle Valo 307e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 308e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 309e705c121SKalle Valo 310e705c121SKalle Valo /* 311e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 312e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 313e705c121SKalle Valo */ 314e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 315e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 316e705c121SKalle Valo 317e705c121SKalle Valo iwl_pcie_apm_config(trans); 318e705c121SKalle Valo 319e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 320286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 32177d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 322e705c121SKalle Valo 323425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 324c96b5eecSJohannes Berg if (ret) 32552b6e168SEmmanuel Grumbach return ret; 326e705c121SKalle Valo 327e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 328e705c121SKalle Valo /* 329e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 330e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 331e705c121SKalle Valo * not related to host_interrupt_operation_mode. 332e705c121SKalle Valo * 333e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 334e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 335e705c121SKalle Valo * that we wake up from L1 on time. 336e705c121SKalle Valo * 337e705c121SKalle Valo * This looks weird: read twice the same register, discard the 338e705c121SKalle Valo * value, set a bit, and yet again, read that same register 339e705c121SKalle Valo * just to discard the value. But that's the way the hardware 340e705c121SKalle Valo * seems to like it. 341e705c121SKalle Valo */ 342e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 343e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 344e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 345e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 346e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 347e705c121SKalle Valo } 348e705c121SKalle Valo 349e705c121SKalle Valo /* 350e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 351e705c121SKalle Valo * 352e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 353e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 354e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 355e705c121SKalle Valo */ 356e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 357e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 358e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 359e705c121SKalle Valo udelay(20); 360e705c121SKalle Valo 361e705c121SKalle Valo /* Disable L1-Active */ 362e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 363e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 364e705c121SKalle Valo 365e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 366e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 367e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 368e705c121SKalle Valo } 369e705c121SKalle Valo 370e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 371e705c121SKalle Valo 37252b6e168SEmmanuel Grumbach return 0; 373e705c121SKalle Valo } 374e705c121SKalle Valo 375e705c121SKalle Valo /* 376e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 377e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 378e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 379e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 380e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 381e705c121SKalle Valo */ 382e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 383e705c121SKalle Valo { 384e705c121SKalle Valo int ret; 385e705c121SKalle Valo u32 apmg_gp1_reg; 386e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 387e705c121SKalle Valo u32 dl_cfg_reg; 388e705c121SKalle Valo 389e705c121SKalle Valo /* Force XTAL ON */ 390e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 391e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 392e705c121SKalle Valo 39315bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 394e705c121SKalle Valo 39515bf5ac6SJohannes Berg if (!ret) 396425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 39715bf5ac6SJohannes Berg 398c96b5eecSJohannes Berg if (WARN_ON(ret)) { 399e705c121SKalle Valo /* Release XTAL ON request */ 400e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 401e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 402e705c121SKalle Valo return; 403e705c121SKalle Valo } 404e705c121SKalle Valo 405e705c121SKalle Valo /* 406e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 407e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 408e705c121SKalle Valo */ 409e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 410e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 411e705c121SKalle Valo 412e705c121SKalle Valo /* 413e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 414e705c121SKalle Valo * caused by APMG idle state. 415e705c121SKalle Valo */ 416e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 417e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 418e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 419e705c121SKalle Valo apmg_xtal_cfg_reg | 420e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 421e705c121SKalle Valo 42215bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 42315bf5ac6SJohannes Berg if (ret) 42415bf5ac6SJohannes Berg IWL_ERR(trans, 42515bf5ac6SJohannes Berg "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 426e705c121SKalle Valo 427e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 428e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 429e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 430e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 431e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 432e705c121SKalle Valo 433e705c121SKalle Valo /* Clear delay line clock power up */ 434e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 435e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 436e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 437e705c121SKalle Valo 438e705c121SKalle Valo /* 439e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 440e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 441e705c121SKalle Valo */ 442e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 443e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 444e705c121SKalle Valo 445e705c121SKalle Valo /* 446e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 447e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 448e705c121SKalle Valo */ 4496dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 450e705c121SKalle Valo 451e705c121SKalle Valo /* Activates XTAL resources monitor */ 452e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 453e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 454e705c121SKalle Valo 455e705c121SKalle Valo /* Release XTAL ON request */ 456e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 457e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 458e705c121SKalle Valo udelay(10); 459e705c121SKalle Valo 460e705c121SKalle Valo /* Release APMG XTAL */ 461e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 462e705c121SKalle Valo apmg_xtal_cfg_reg & 463e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 464e705c121SKalle Valo } 465e705c121SKalle Valo 466e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 467e705c121SKalle Valo { 468e8c8935eSJohannes Berg int ret; 469e705c121SKalle Valo 470e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4719ce041f5SJohannes Berg 4729ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4739ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4749ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4759ce041f5SJohannes Berg 4769ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4779ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4789ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4799ce041f5SJohannes Berg 100); 480ec80c231SJohannes Berg usleep_range(10000, 20000); 4819ce041f5SJohannes Berg } else { 4826dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 483e705c121SKalle Valo 4846dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4856dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4866dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4879ce041f5SJohannes Berg } 4889ce041f5SJohannes Berg 489e705c121SKalle Valo if (ret < 0) 490e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 491e705c121SKalle Valo 492e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 493e705c121SKalle Valo } 494e705c121SKalle Valo 495e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 496e705c121SKalle Valo { 497e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 498e705c121SKalle Valo 499e705c121SKalle Valo if (op_mode_leave) { 500e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 501e705c121SKalle Valo iwl_pcie_apm_init(trans); 502e705c121SKalle Valo 503e705c121SKalle Valo /* inform ME that we are leaving */ 504286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 505e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 506e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 507286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 50879b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 509e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 510e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 511e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 512e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 513e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 514e705c121SKalle Valo mdelay(1); 515e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 516e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 517e705c121SKalle Valo } 518e705c121SKalle Valo mdelay(5); 519e705c121SKalle Valo } 520e705c121SKalle Valo 521e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 522e705c121SKalle Valo 523e705c121SKalle Valo /* Stop device's DMA activity */ 524e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 525e705c121SKalle Valo 526e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 527e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 528e705c121SKalle Valo return; 529e705c121SKalle Valo } 530e705c121SKalle Valo 53115bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, false); 532e705c121SKalle Valo 533e705c121SKalle Valo /* 534e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 535e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 536e705c121SKalle Valo */ 5376dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 538e705c121SKalle Valo } 539e705c121SKalle Valo 540e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 541e705c121SKalle Valo { 542e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 54352b6e168SEmmanuel Grumbach int ret; 544e705c121SKalle Valo 545e705c121SKalle Valo /* nic_init */ 54625edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 54752b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 54825edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 549e705c121SKalle Valo 55052b6e168SEmmanuel Grumbach if (ret) 55152b6e168SEmmanuel Grumbach return ret; 55252b6e168SEmmanuel Grumbach 553e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 554e705c121SKalle Valo 555e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 556e705c121SKalle Valo 557e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5589cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5599cf671d6SEmmanuel Grumbach if (ret) 5609cf671d6SEmmanuel Grumbach return ret; 561e705c121SKalle Valo 562e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5639cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5649cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 565e705c121SKalle Valo return -ENOMEM; 5669cf671d6SEmmanuel Grumbach } 567e705c121SKalle Valo 568286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 569e705c121SKalle Valo /* enable shadow regs in HW */ 570e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 571e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 572e705c121SKalle Valo } 573e705c121SKalle Valo 574e705c121SKalle Valo return 0; 575e705c121SKalle Valo } 576e705c121SKalle Valo 577e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 578e705c121SKalle Valo 579e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 580e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 581e705c121SKalle Valo { 582e705c121SKalle Valo int ret; 583e705c121SKalle Valo 584e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 585e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 586e705c121SKalle Valo 587e705c121SKalle Valo /* See if we got it */ 588e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 589e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 590e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 591e705c121SKalle Valo HW_READY_TIMEOUT); 592e705c121SKalle Valo 593e705c121SKalle Valo if (ret >= 0) 594e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 595e705c121SKalle Valo 596e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 597e705c121SKalle Valo return ret; 598e705c121SKalle Valo } 599e705c121SKalle Valo 600e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 601eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 602e705c121SKalle Valo { 603e705c121SKalle Valo int ret; 604e705c121SKalle Valo int iter; 605e705c121SKalle Valo 606e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 607e705c121SKalle Valo 608e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 609e705c121SKalle Valo /* If the card is ready, exit 0 */ 6106d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6116d19a5ebSEmmanuel Grumbach trans->csme_own = false; 612e705c121SKalle Valo return 0; 6136d19a5ebSEmmanuel Grumbach } 614e705c121SKalle Valo 615e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 616e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 617192185d6SJohannes Berg usleep_range(1000, 2000); 618e705c121SKalle Valo 619e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 62028965ec0SEmmanuel Grumbach int t = 0; 62128965ec0SEmmanuel Grumbach 622e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 623e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 624e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 625e705c121SKalle Valo 626e705c121SKalle Valo do { 627e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 6286d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6296d19a5ebSEmmanuel Grumbach trans->csme_own = false; 630e705c121SKalle Valo return 0; 6316d19a5ebSEmmanuel Grumbach } 6326d19a5ebSEmmanuel Grumbach 6336d19a5ebSEmmanuel Grumbach if (iwl_mei_is_connected()) { 6346d19a5ebSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 6356d19a5ebSEmmanuel Grumbach "Couldn't prepare the card but SAP is connected\n"); 6366d19a5ebSEmmanuel Grumbach trans->csme_own = true; 6376d19a5ebSEmmanuel Grumbach if (trans->trans_cfg->device_family != 6386d19a5ebSEmmanuel Grumbach IWL_DEVICE_FAMILY_9000) 6396d19a5ebSEmmanuel Grumbach IWL_ERR(trans, 6406d19a5ebSEmmanuel Grumbach "SAP not supported for this NIC family\n"); 6416d19a5ebSEmmanuel Grumbach 6426d19a5ebSEmmanuel Grumbach return -EBUSY; 6436d19a5ebSEmmanuel Grumbach } 644e705c121SKalle Valo 645e705c121SKalle Valo usleep_range(200, 1000); 646e705c121SKalle Valo t += 200; 647e705c121SKalle Valo } while (t < 150000); 648e705c121SKalle Valo msleep(25); 649e705c121SKalle Valo } 650e705c121SKalle Valo 651e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 652e705c121SKalle Valo 653e705c121SKalle Valo return ret; 654e705c121SKalle Valo } 655e705c121SKalle Valo 656e705c121SKalle Valo /* 657e705c121SKalle Valo * ucode 658e705c121SKalle Valo */ 659564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 660564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 661564cdce7SSara Sharon u32 byte_cnt) 662e705c121SKalle Valo { 663bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 664e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 665e705c121SKalle Valo 666bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 667e705c121SKalle Valo dst_addr); 668e705c121SKalle Valo 669bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 670e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 671e705c121SKalle Valo 672bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 673e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 674e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 675e705c121SKalle Valo 676bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 677bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 678bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 679e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 680e705c121SKalle Valo 681bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 682e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 683e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 684e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 685564cdce7SSara Sharon } 686e705c121SKalle Valo 687564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 688564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 689564cdce7SSara Sharon u32 byte_cnt) 690564cdce7SSara Sharon { 691564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 692564cdce7SSara Sharon int ret; 693564cdce7SSara Sharon 694564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 695564cdce7SSara Sharon 6961ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 697564cdce7SSara Sharon return -EIO; 698564cdce7SSara Sharon 699564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 700564cdce7SSara Sharon byte_cnt); 7011ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 702bac842daSEmmanuel Grumbach 703e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 704e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 705e705c121SKalle Valo if (!ret) { 706e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 707fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 708e705c121SKalle Valo return -ETIMEDOUT; 709e705c121SKalle Valo } 710e705c121SKalle Valo 711e705c121SKalle Valo return 0; 712e705c121SKalle Valo } 713e705c121SKalle Valo 714e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 715e705c121SKalle Valo const struct fw_desc *section) 716e705c121SKalle Valo { 717e705c121SKalle Valo u8 *v_addr; 718e705c121SKalle Valo dma_addr_t p_addr; 719e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 720e705c121SKalle Valo int ret = 0; 721e705c121SKalle Valo 722e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 723e705c121SKalle Valo section_num); 724e705c121SKalle Valo 725e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 726e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 727e705c121SKalle Valo if (!v_addr) { 728e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 729e705c121SKalle Valo chunk_sz = PAGE_SIZE; 730e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 731e705c121SKalle Valo &p_addr, GFP_KERNEL); 732e705c121SKalle Valo if (!v_addr) 733e705c121SKalle Valo return -ENOMEM; 734e705c121SKalle Valo } 735e705c121SKalle Valo 736e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 737e705c121SKalle Valo u32 copy_size, dst_addr; 738e705c121SKalle Valo bool extended_addr = false; 739e705c121SKalle Valo 740e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 741e705c121SKalle Valo dst_addr = section->offset + offset; 742e705c121SKalle Valo 743e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 744e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 745e705c121SKalle Valo extended_addr = true; 746e705c121SKalle Valo 747e705c121SKalle Valo if (extended_addr) 748e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 749e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 750e705c121SKalle Valo 75173c289baSBjoern A. Zeeb memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 752e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 753e705c121SKalle Valo copy_size); 754e705c121SKalle Valo 755e705c121SKalle Valo if (extended_addr) 756e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 757e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 758e705c121SKalle Valo 759e705c121SKalle Valo if (ret) { 760e705c121SKalle Valo IWL_ERR(trans, 761e705c121SKalle Valo "Could not load the [%d] uCode section\n", 762e705c121SKalle Valo section_num); 763e705c121SKalle Valo break; 764e705c121SKalle Valo } 765e705c121SKalle Valo } 766e705c121SKalle Valo 767e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 768e705c121SKalle Valo return ret; 769e705c121SKalle Valo } 770e705c121SKalle Valo 771e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 772e705c121SKalle Valo const struct fw_img *image, 773e705c121SKalle Valo int cpu, 774e705c121SKalle Valo int *first_ucode_section) 775e705c121SKalle Valo { 776e705c121SKalle Valo int shift_param; 777e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 778e705c121SKalle Valo u32 val, last_read_idx = 0; 779e705c121SKalle Valo 780e705c121SKalle Valo if (cpu == 1) { 781e705c121SKalle Valo shift_param = 0; 782e705c121SKalle Valo *first_ucode_section = 0; 783e705c121SKalle Valo } else { 784e705c121SKalle Valo shift_param = 16; 785e705c121SKalle Valo (*first_ucode_section)++; 786e705c121SKalle Valo } 787e705c121SKalle Valo 788eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 789e705c121SKalle Valo last_read_idx = i; 790e705c121SKalle Valo 791e705c121SKalle Valo /* 792e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 793e705c121SKalle Valo * CPU1 to CPU2. 794e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 795e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 796e705c121SKalle Valo */ 797e705c121SKalle Valo if (!image->sec[i].data || 798e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 799e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 800e705c121SKalle Valo IWL_DEBUG_FW(trans, 801e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 802e705c121SKalle Valo i); 803e705c121SKalle Valo break; 804e705c121SKalle Valo } 805e705c121SKalle Valo 806e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 807e705c121SKalle Valo if (ret) 808e705c121SKalle Valo return ret; 809e705c121SKalle Valo 810d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 811e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 812e705c121SKalle Valo val = val | (sec_num << shift_param); 813e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 814eda50cdeSSara Sharon 815e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 816e705c121SKalle Valo } 817e705c121SKalle Valo 818e705c121SKalle Valo *first_ucode_section = last_read_idx; 819e705c121SKalle Valo 8202aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8212aabdbdcSEmmanuel Grumbach 82212a89f01SJohannes Berg if (trans->trans_cfg->gen2) { 823e705c121SKalle Valo if (cpu == 1) 824d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825d6a2c5c7SSara Sharon 0xFFFF); 826e705c121SKalle Valo else 827d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 828d6a2c5c7SSara Sharon 0xFFFFFFFF); 829d6a2c5c7SSara Sharon } else { 830d6a2c5c7SSara Sharon if (cpu == 1) 831d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832d6a2c5c7SSara Sharon 0xFFFF); 833d6a2c5c7SSara Sharon else 834d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 835d6a2c5c7SSara Sharon 0xFFFFFFFF); 836d6a2c5c7SSara Sharon } 837e705c121SKalle Valo 838e705c121SKalle Valo return 0; 839e705c121SKalle Valo } 840e705c121SKalle Valo 841e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 842e705c121SKalle Valo const struct fw_img *image, 843e705c121SKalle Valo int cpu, 844e705c121SKalle Valo int *first_ucode_section) 845e705c121SKalle Valo { 846e705c121SKalle Valo int i, ret = 0; 847e705c121SKalle Valo u32 last_read_idx = 0; 848e705c121SKalle Valo 8493ce4a038SKirtika Ruchandani if (cpu == 1) 850e705c121SKalle Valo *first_ucode_section = 0; 8513ce4a038SKirtika Ruchandani else 852e705c121SKalle Valo (*first_ucode_section)++; 853e705c121SKalle Valo 854eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 855e705c121SKalle Valo last_read_idx = i; 856e705c121SKalle Valo 857e705c121SKalle Valo /* 858e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 859e705c121SKalle Valo * CPU1 to CPU2. 860e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 861e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 862e705c121SKalle Valo */ 863e705c121SKalle Valo if (!image->sec[i].data || 864e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 865e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 866e705c121SKalle Valo IWL_DEBUG_FW(trans, 867e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 868e705c121SKalle Valo i); 869e705c121SKalle Valo break; 870e705c121SKalle Valo } 871e705c121SKalle Valo 872e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 873e705c121SKalle Valo if (ret) 874e705c121SKalle Valo return ret; 875e705c121SKalle Valo } 876e705c121SKalle Valo 877e705c121SKalle Valo *first_ucode_section = last_read_idx; 878e705c121SKalle Valo 879e705c121SKalle Valo return 0; 880e705c121SKalle Valo } 881e705c121SKalle Valo 882593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 883593fae3eSShahar S Matityahu { 884593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 885593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 886593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 887593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 888593fae3eSShahar S Matityahu 889593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 890593fae3eSShahar S Matityahu return; 891593fae3eSShahar S Matityahu 892593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 893593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 894593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 895593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 896593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 897593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 898593fae3eSShahar S Matityahu 899593fae3eSShahar S Matityahu return; 900593fae3eSShahar S Matityahu } 901593fae3eSShahar S Matityahu 902593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 903593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 904593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 905593fae3eSShahar S Matityahu return; 906593fae3eSShahar S Matityahu 907593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 908593fae3eSShahar S Matityahu 909593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 910593fae3eSShahar S Matityahu alloc_id); 911593fae3eSShahar S Matityahu 912593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 913593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 914593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 915593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 916593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 917593fae3eSShahar S Matityahu } 918593fae3eSShahar S Matityahu 919c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 920e705c121SKalle Valo { 92191c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 92269f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 923e705c121SKalle Valo int i; 924e705c121SKalle Valo 925a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 926593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9277a14c23dSSara Sharon return; 9287a14c23dSSara Sharon } 9297a14c23dSSara Sharon 930e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 931e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 932e705c121SKalle Valo 933e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 934e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 935e705c121SKalle Valo else 936e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 937e705c121SKalle Valo 93891c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 939e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 940e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 941e705c121SKalle Valo 942e705c121SKalle Valo switch (dest->reg_ops[i].op) { 943e705c121SKalle Valo case CSR_ASSIGN: 944e705c121SKalle Valo iwl_write32(trans, addr, val); 945e705c121SKalle Valo break; 946e705c121SKalle Valo case CSR_SETBIT: 947e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 948e705c121SKalle Valo break; 949e705c121SKalle Valo case CSR_CLEARBIT: 950e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 951e705c121SKalle Valo break; 952e705c121SKalle Valo case PRPH_ASSIGN: 953e705c121SKalle Valo iwl_write_prph(trans, addr, val); 954e705c121SKalle Valo break; 955e705c121SKalle Valo case PRPH_SETBIT: 956e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 957e705c121SKalle Valo break; 958e705c121SKalle Valo case PRPH_CLEARBIT: 959e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 960e705c121SKalle Valo break; 961e705c121SKalle Valo case PRPH_BLOCKBIT: 962e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 963e705c121SKalle Valo IWL_ERR(trans, 964e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 965e705c121SKalle Valo val, addr); 966e705c121SKalle Valo goto monitor; 967e705c121SKalle Valo } 968e705c121SKalle Valo break; 969e705c121SKalle Valo default: 970e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 971e705c121SKalle Valo dest->reg_ops[i].op); 972e705c121SKalle Valo break; 973e705c121SKalle Valo } 974e705c121SKalle Valo } 975e705c121SKalle Valo 976e705c121SKalle Valo monitor: 97769f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 978e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 97969f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 980286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 981e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98269f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 98369f0e505SShahar S Matityahu 256) >> dest->end_shift); 98462d7476dSEmmanuel Grumbach else 98562d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98669f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 98762d7476dSEmmanuel Grumbach dest->end_shift); 988e705c121SKalle Valo } 989e705c121SKalle Valo } 990e705c121SKalle Valo 991e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 992e705c121SKalle Valo const struct fw_img *image) 993e705c121SKalle Valo { 994e705c121SKalle Valo int ret = 0; 995e705c121SKalle Valo int first_ucode_section; 996e705c121SKalle Valo 997e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 998e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 999e705c121SKalle Valo 1000e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1001e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1002e705c121SKalle Valo if (ret) 1003e705c121SKalle Valo return ret; 1004e705c121SKalle Valo 1005e705c121SKalle Valo if (image->is_dual_cpus) { 1006e705c121SKalle Valo /* set CPU2 header address */ 1007e705c121SKalle Valo iwl_write_prph(trans, 1008e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1009e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1010e705c121SKalle Valo 1011e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1012e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1013e705c121SKalle Valo &first_ucode_section); 1014e705c121SKalle Valo if (ret) 1015e705c121SKalle Valo return ret; 1016e705c121SKalle Valo } 1017e705c121SKalle Valo 10189efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 1019e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1020e705c121SKalle Valo 10212aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10222aabdbdcSEmmanuel Grumbach 1023e705c121SKalle Valo /* release CPU reset */ 1024e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1025e705c121SKalle Valo 1026e705c121SKalle Valo return 0; 1027e705c121SKalle Valo } 1028e705c121SKalle Valo 1029e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1030e705c121SKalle Valo const struct fw_img *image) 1031e705c121SKalle Valo { 1032e705c121SKalle Valo int ret = 0; 1033e705c121SKalle Valo int first_ucode_section; 1034e705c121SKalle Valo 1035e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1036e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1037e705c121SKalle Valo 10387a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1039e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1040e705c121SKalle Valo 104182ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 104282ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 104382ea7966SSara Sharon 104482ea7966SSara Sharon /* 104582ea7966SSara Sharon * Set default value. On resume reading the values that were 104682ea7966SSara Sharon * zeored can provide debug data on the resume flow. 104782ea7966SSara Sharon * This is for debugging only and has no functional impact. 104882ea7966SSara Sharon */ 104982ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 105082ea7966SSara Sharon 1051e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1052e705c121SKalle Valo /* release CPU reset */ 1053e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1054e705c121SKalle Valo 1055e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1056e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1057e705c121SKalle Valo &first_ucode_section); 1058e705c121SKalle Valo if (ret) 1059e705c121SKalle Valo return ret; 1060e705c121SKalle Valo 1061e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1062e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1063e705c121SKalle Valo &first_ucode_section); 1064e705c121SKalle Valo } 1065e705c121SKalle Valo 10669ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1067727c02dfSSara Sharon { 1068326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1069727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1070326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1071326477e4SJohannes Berg bool report; 1072727c02dfSSara Sharon 1073326477e4SJohannes Berg if (hw_rfkill) { 1074326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1075326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1076326477e4SJohannes Berg } else { 1077326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1078326477e4SJohannes Berg if (trans_pcie->opmode_down) 1079326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080326477e4SJohannes Berg } 1081727c02dfSSara Sharon 1082326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083326477e4SJohannes Berg 1084326477e4SJohannes Berg if (prev != report) 1085326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1086727c02dfSSara Sharon 1087727c02dfSSara Sharon return hw_rfkill; 1088727c02dfSSara Sharon } 1089727c02dfSSara Sharon 10907ca00409SHaim Dreyfuss struct iwl_causes_list { 1091c1918196SJohannes Berg u16 mask_reg; 1092c1918196SJohannes Berg u8 bit; 10937ca00409SHaim Dreyfuss u8 addr; 10947ca00409SHaim Dreyfuss }; 10957ca00409SHaim Dreyfuss 10969c683731SJohannes Berg #define IWL_CAUSE(reg, mask) \ 1097c1918196SJohannes Berg { \ 1098c1918196SJohannes Berg .mask_reg = reg, \ 1099c1918196SJohannes Berg .bit = ilog2(mask), \ 1100c1918196SJohannes Berg .addr = ilog2(mask) + \ 1101c1918196SJohannes Berg ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1102c1918196SJohannes Berg (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1103c1918196SJohannes Berg 0xffff), /* causes overflow warning */ \ 1104c1918196SJohannes Berg } 1105c1918196SJohannes Berg 1106571836a0SMike Golant static const struct iwl_causes_list causes_list_common[] = { 11079c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 11089c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 11099c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 11109c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 11119c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 11129c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 11139c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 11149c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 11159c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 11169c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 11179c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 11189c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 11199c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 11209c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 11217ca00409SHaim Dreyfuss }; 11227ca00409SHaim Dreyfuss 1123571836a0SMike Golant static const struct iwl_causes_list causes_list_pre_bz[] = { 11249c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1125571836a0SMike Golant }; 11267ca00409SHaim Dreyfuss 1127571836a0SMike Golant static const struct iwl_causes_list causes_list_bz[] = { 11289c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1129571836a0SMike Golant }; 1130571836a0SMike Golant 1131571836a0SMike Golant static void iwl_pcie_map_list(struct iwl_trans *trans, 1132571836a0SMike Golant const struct iwl_causes_list *causes, 1133571836a0SMike Golant int arr_size, int val) 1134571836a0SMike Golant { 1135571836a0SMike Golant int i; 1136571836a0SMike Golant 11379b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11389b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11399b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 1140c1918196SJohannes Berg BIT(causes[i].bit)); 11417ca00409SHaim Dreyfuss } 11427ca00409SHaim Dreyfuss } 11437ca00409SHaim Dreyfuss 1144571836a0SMike Golant static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1145571836a0SMike Golant { 1146571836a0SMike Golant struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1147571836a0SMike Golant int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1148571836a0SMike Golant /* 1149571836a0SMike Golant * Access all non RX causes and map them to the default irq. 1150571836a0SMike Golant * In case we are missing at least one interrupt vector, 1151571836a0SMike Golant * the first interrupt vector will serve non-RX and FBQ causes. 1152571836a0SMike Golant */ 1153571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_common, 1154571836a0SMike Golant ARRAY_SIZE(causes_list_common), val); 1155571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1156571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_bz, 1157571836a0SMike Golant ARRAY_SIZE(causes_list_bz), val); 1158571836a0SMike Golant else 1159571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_pre_bz, 1160571836a0SMike Golant ARRAY_SIZE(causes_list_pre_bz), val); 1161571836a0SMike Golant } 1162571836a0SMike Golant 11637ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11647ca00409SHaim Dreyfuss { 11657ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11667ca00409SHaim Dreyfuss u32 offset = 11677ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11687ca00409SHaim Dreyfuss u32 val, idx; 11697ca00409SHaim Dreyfuss 11707ca00409SHaim Dreyfuss /* 11717ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11727ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11737ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11747ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11757ca00409SHaim Dreyfuss */ 11767ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11777ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11787ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11797ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11807ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11817ca00409SHaim Dreyfuss } 11827ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11837ca00409SHaim Dreyfuss 11847ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11857ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11867ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11877ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11887ca00409SHaim Dreyfuss 11897ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11907ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11917ca00409SHaim Dreyfuss } 11927ca00409SHaim Dreyfuss 119377c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11947ca00409SHaim Dreyfuss { 11957ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11967ca00409SHaim Dreyfuss 11977ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1198286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1199d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1200ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 12017ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 12027ca00409SHaim Dreyfuss return; 12037ca00409SHaim Dreyfuss } 1204d7270d61SHaim Dreyfuss /* 1205d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1206d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1207d7270d61SHaim Dreyfuss * prph. 1208d7270d61SHaim Dreyfuss */ 1209d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1210ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12117ca00409SHaim Dreyfuss 12127ca00409SHaim Dreyfuss /* 12137ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12147ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12157ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12167ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12177ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12187ca00409SHaim Dreyfuss */ 12197ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12207ca00409SHaim Dreyfuss 12217ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 122283730058SHaim Dreyfuss } 12237ca00409SHaim Dreyfuss 122483730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122583730058SHaim Dreyfuss { 122683730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122783730058SHaim Dreyfuss 122883730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122983730058SHaim Dreyfuss 123083730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 123183730058SHaim Dreyfuss return; 123283730058SHaim Dreyfuss 123383730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12347ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123583730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12367ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12377ca00409SHaim Dreyfuss } 12387ca00409SHaim Dreyfuss 1239bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1240e705c121SKalle Valo { 1241e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1242e705c121SKalle Valo 1243e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1244e705c121SKalle Valo 1245e705c121SKalle Valo if (trans_pcie->is_down) 1246e705c121SKalle Valo return; 1247e705c121SKalle Valo 1248e705c121SKalle Valo trans_pcie->is_down = true; 1249e705c121SKalle Valo 1250e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1251e705c121SKalle Valo iwl_disable_interrupts(trans); 1252e705c121SKalle Valo 1253e705c121SKalle Valo /* device going down, Stop using ICT table */ 1254e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1255e705c121SKalle Valo 1256e705c121SKalle Valo /* 1257e705c121SKalle Valo * If a HW restart happens during firmware loading, 1258e705c121SKalle Valo * then the firmware loading might call this function 1259e705c121SKalle Valo * and later it might be called again due to the 1260e705c121SKalle Valo * restart. So don't process again if the device is 1261e705c121SKalle Valo * already dead. 1262e705c121SKalle Valo */ 1263e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1264a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1265a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1266*f1f2e068SJohannes Berg iwl_pcie_synchronize_irqs(trans); 12675af2bb31SGregory Greenman iwl_pcie_rx_napi_sync(trans); 1268e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1269e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1270e705c121SKalle Valo 1271e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1272e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1273e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1274e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1275e705c121SKalle Valo udelay(5); 1276e705c121SKalle Valo } 1277e705c121SKalle Valo } 1278e705c121SKalle Valo 1279e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 12801b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 12811b6598c3SRoee Goldfiner iwl_clear_bit(trans, CSR_GP_CNTRL, 12821b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 12831b6598c3SRoee Goldfiner else 1284e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12856dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1286e705c121SKalle Valo 1287e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1288e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1289e705c121SKalle Valo 129015bf5ac6SJohannes Berg /* re-take ownership to prevent other users from stealing the device */ 129115bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, true); 1292e705c121SKalle Valo 1293e705c121SKalle Valo /* 1294f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1295f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1296f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1297f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1298f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1299f4a1f04aSGolan Ben Ami */ 1300f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1301f4a1f04aSGolan Ben Ami 1302f4a1f04aSGolan Ben Ami /* 1303e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1304e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1305e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1306e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1307e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1308e705c121SKalle Valo */ 1309e705c121SKalle Valo iwl_disable_interrupts(trans); 1310e705c121SKalle Valo 1311e705c121SKalle Valo /* clear all status bits */ 1312e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1313e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1314e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1315e705c121SKalle Valo 1316e705c121SKalle Valo /* 1317e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1318e705c121SKalle Valo * interrupt 1319e705c121SKalle Valo */ 1320e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1321e705c121SKalle Valo } 1322e705c121SKalle Valo 1323eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13242e5d4a8fSHaim Dreyfuss { 13252e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13262e5d4a8fSHaim Dreyfuss 13272e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13282e5d4a8fSHaim Dreyfuss int i; 13292e5d4a8fSHaim Dreyfuss 1330496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13312e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13322e5d4a8fSHaim Dreyfuss } else { 13332e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13342e5d4a8fSHaim Dreyfuss } 13352e5d4a8fSHaim Dreyfuss } 13362e5d4a8fSHaim Dreyfuss 1337a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1338a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1339a6bd005fSEmmanuel Grumbach { 1340a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1341a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1342a6bd005fSEmmanuel Grumbach int ret; 1343a6bd005fSEmmanuel Grumbach 1344a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1345a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1346a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1347e9848aedSJohannes Berg return -EIO; 1348a6bd005fSEmmanuel Grumbach } 1349a6bd005fSEmmanuel Grumbach 1350a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1351a6bd005fSEmmanuel Grumbach 1352a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1353a6bd005fSEmmanuel Grumbach 1354a6bd005fSEmmanuel Grumbach /* 1355a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1356a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1357a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1358a6bd005fSEmmanuel Grumbach */ 1359a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1360a6bd005fSEmmanuel Grumbach 1361a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13622e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1363a6bd005fSEmmanuel Grumbach 1364a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1365a6bd005fSEmmanuel Grumbach 1366a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13679ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1368a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1369a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1370a6bd005fSEmmanuel Grumbach goto out; 1371a6bd005fSEmmanuel Grumbach } 1372a6bd005fSEmmanuel Grumbach 1373a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1374a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1375a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1376a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 137720aa99bbSAnton Protopopov ret = -EIO; 1378a6bd005fSEmmanuel Grumbach goto out; 1379a6bd005fSEmmanuel Grumbach } 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1382a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1383a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1384a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1385a6bd005fSEmmanuel Grumbach 1386a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1387a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1388a6bd005fSEmmanuel Grumbach 1389a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1390a6bd005fSEmmanuel Grumbach if (ret) { 1391a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1392a6bd005fSEmmanuel Grumbach goto out; 1393a6bd005fSEmmanuel Grumbach } 1394a6bd005fSEmmanuel Grumbach 1395a6bd005fSEmmanuel Grumbach /* 1396a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1397a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1398a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1399a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1400a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1401a6bd005fSEmmanuel Grumbach */ 1402a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1403a6bd005fSEmmanuel Grumbach 1404a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1405a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1406a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1407a6bd005fSEmmanuel Grumbach 1408a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1409286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1410a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1411a6bd005fSEmmanuel Grumbach else 1412a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1413a6bd005fSEmmanuel Grumbach 1414a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14159ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1416a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1417a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1418a6bd005fSEmmanuel Grumbach 1419a6bd005fSEmmanuel Grumbach out: 1420a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1421a6bd005fSEmmanuel Grumbach return ret; 1422a6bd005fSEmmanuel Grumbach } 1423a6bd005fSEmmanuel Grumbach 1424a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1425a6bd005fSEmmanuel Grumbach { 1426a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1427a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1428a6bd005fSEmmanuel Grumbach } 1429a6bd005fSEmmanuel Grumbach 1430326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1431326477e4SJohannes Berg bool was_in_rfkill) 1432326477e4SJohannes Berg { 1433326477e4SJohannes Berg bool hw_rfkill; 1434326477e4SJohannes Berg 1435326477e4SJohannes Berg /* 1436326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1437326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1438326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1439326477e4SJohannes Berg * op_mode. 1440326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1441326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1442326477e4SJohannes Berg * notification without endless recursion. Under very rare 1443326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1444326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1445326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1446326477e4SJohannes Berg */ 1447326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1448326477e4SJohannes Berg if (hw_rfkill) { 1449326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1450326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1451326477e4SJohannes Berg } else { 1452326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1453326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1454326477e4SJohannes Berg } 1455326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1456326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1457326477e4SJohannes Berg } 1458326477e4SJohannes Berg 1459bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1460e705c121SKalle Valo { 1461e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1462326477e4SJohannes Berg bool was_in_rfkill; 1463e705c121SKalle Valo 1464d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1465d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1466d0129315SMordechay Goodstein NULL); 1467d0129315SMordechay Goodstein 1468e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1469326477e4SJohannes Berg trans_pcie->opmode_down = true; 1470326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1471bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1472326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1473e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1474e705c121SKalle Valo } 1475e705c121SKalle Valo 1476e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1477e705c121SKalle Valo { 1478e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1479e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1480e705c121SKalle Valo 1481e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1482e705c121SKalle Valo 1483326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1484326477e4SJohannes Berg state ? "disabled" : "enabled"); 148577c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1486286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1487bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 148877c09bc8SSara Sharon else 1489bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1490e705c121SKalle Valo } 149177c09bc8SSara Sharon } 1492e705c121SKalle Valo 1493e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1494e5f3f215SHaim Dreyfuss bool test, bool reset) 1495e705c121SKalle Valo { 1496e705c121SKalle Valo iwl_disable_interrupts(trans); 1497e705c121SKalle Valo 1498e705c121SKalle Valo /* 1499e705c121SKalle Valo * in testing mode, the host stays awake and the 1500e705c121SKalle Valo * hardware won't be reset (not even partially) 1501e705c121SKalle Valo */ 1502e705c121SKalle Valo if (test) 1503e705c121SKalle Valo return; 1504e705c121SKalle Valo 1505e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1506e705c121SKalle Valo 15072e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1508e705c121SKalle Valo 1509e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15106dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 15116dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1512e705c121SKalle Valo 151323ae6128SMatti Gottlieb if (reset) { 1514e705c121SKalle Valo /* 1515e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1516e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1517e705c121SKalle Valo * to execute some invalid memory upon resume 1518e705c121SKalle Valo */ 1519e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1520e705c121SKalle Valo } 1521e705c121SKalle Valo 1522e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1523e705c121SKalle Valo } 1524e705c121SKalle Valo 1525af08571dSHaim Dreyfuss static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1526af08571dSHaim Dreyfuss { 1527af08571dSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1528af08571dSHaim Dreyfuss int ret; 1529af08571dSHaim Dreyfuss 1530277f56a1SAvraham Stern if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1531af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1532af08571dSHaim Dreyfuss suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1533af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1534277f56a1SAvraham Stern else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1535af08571dSHaim Dreyfuss iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1536af08571dSHaim Dreyfuss suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1537af08571dSHaim Dreyfuss CSR_IPC_SLEEP_CONTROL_RESUME); 1538277f56a1SAvraham Stern else 1539af08571dSHaim Dreyfuss return 0; 1540af08571dSHaim Dreyfuss 1541af08571dSHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1542af08571dSHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1543af08571dSHaim Dreyfuss 1544af08571dSHaim Dreyfuss /* Invalidate it toward next suspend or resume */ 1545af08571dSHaim Dreyfuss trans_pcie->sx_complete = false; 1546af08571dSHaim Dreyfuss 1547af08571dSHaim Dreyfuss if (!ret) { 1548af08571dSHaim Dreyfuss IWL_ERR(trans, "Timeout %s D3\n", 1549af08571dSHaim Dreyfuss suspend ? "entering" : "exiting"); 1550af08571dSHaim Dreyfuss return -ETIMEDOUT; 1551af08571dSHaim Dreyfuss } 1552af08571dSHaim Dreyfuss 1553af08571dSHaim Dreyfuss return 0; 1554af08571dSHaim Dreyfuss } 1555af08571dSHaim Dreyfuss 1556e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1557e5f3f215SHaim Dreyfuss bool reset) 1558e5f3f215SHaim Dreyfuss { 1559e5f3f215SHaim Dreyfuss int ret; 1560e5f3f215SHaim Dreyfuss 1561771db3a1SHaim Dreyfuss if (!reset) 1562e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1563e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1564e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1565e5f3f215SHaim Dreyfuss 1566af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, true); 1567af08571dSHaim Dreyfuss if (ret) 1568af08571dSHaim Dreyfuss return ret; 1569e5f3f215SHaim Dreyfuss 1570e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1571e5f3f215SHaim Dreyfuss 1572e5f3f215SHaim Dreyfuss return 0; 1573e5f3f215SHaim Dreyfuss } 1574e5f3f215SHaim Dreyfuss 1575e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1576e705c121SKalle Valo enum iwl_d3_status *status, 157723ae6128SMatti Gottlieb bool test, bool reset) 1578e705c121SKalle Valo { 1579d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1580e705c121SKalle Valo u32 val; 1581e705c121SKalle Valo int ret; 1582e705c121SKalle Valo 1583e705c121SKalle Valo if (test) { 1584e705c121SKalle Valo iwl_enable_interrupts(trans); 1585e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1586af08571dSHaim Dreyfuss ret = 0; 1587e5f3f215SHaim Dreyfuss goto out; 1588e705c121SKalle Valo } 1589e705c121SKalle Valo 1590a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15916dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1592e705c121SKalle Valo 1593425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 1594c96b5eecSJohannes Berg if (ret) 1595e705c121SKalle Valo return ret; 1596e705c121SKalle Valo 1597f98ad635SEmmanuel Grumbach /* 1598f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1599f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1600f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1601f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1602f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1603f98ad635SEmmanuel Grumbach */ 1604f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1605f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1606f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1607f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1608f98ad635SEmmanuel Grumbach 1609e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1610e705c121SKalle Valo 161123ae6128SMatti Gottlieb if (!reset) { 1612e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 16136dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1614e705c121SKalle Valo } else { 1615e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1616e705c121SKalle Valo 1617e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1618e705c121SKalle Valo if (ret) { 1619e705c121SKalle Valo IWL_ERR(trans, 1620e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1621e705c121SKalle Valo return ret; 1622e705c121SKalle Valo } 1623e705c121SKalle Valo } 1624e705c121SKalle Valo 162582ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1626ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 162782ea7966SSara Sharon 1628e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1629e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1630e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1631e705c121SKalle Valo else 1632e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1633e705c121SKalle Valo 1634e5f3f215SHaim Dreyfuss out: 1635af08571dSHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE) 1636af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, false); 1637e5f3f215SHaim Dreyfuss 1638af08571dSHaim Dreyfuss return ret; 1639e705c121SKalle Valo } 1640e705c121SKalle Valo 16410c18714aSLuca Coelho static void 16420c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16430c18714aSLuca Coelho struct iwl_trans *trans, 16440c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16452e5d4a8fSHaim Dreyfuss { 16462e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1647ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16482e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16490cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 16502e5d4a8fSHaim Dreyfuss 16510c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 165206f4b081SSara Sharon goto enable_msi; 165306f4b081SSara Sharon 16540cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 16550cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 16560cd38f4dSMordechay Goodstein 16570cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 165806f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16592e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16602e5d4a8fSHaim Dreyfuss 166106f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16622e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 166306f4b081SSara Sharon max_irqs); 166406f4b081SSara Sharon if (num_irqs < 0) { 1665496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 166606f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 166706f4b081SSara Sharon num_irqs); 166806f4b081SSara Sharon goto enable_msi; 1669496d83caSHaim Dreyfuss } 167006f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1671496d83caSHaim Dreyfuss 16722e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 167306f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 167406f4b081SSara Sharon num_irqs); 167506f4b081SSara Sharon 1676496d83caSHaim Dreyfuss /* 167706f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 167806f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1679496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1680496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1681496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1682496d83caSHaim Dreyfuss */ 1683ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 168406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1685496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1686496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1687ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 168806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1689496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1690496d83caSHaim Dreyfuss } else { 169106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1692496d83caSHaim Dreyfuss } 16939d401222SMordechay Goodstein 16949d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16959d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16969d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16979d401222SMordechay Goodstein 1698ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16992e5d4a8fSHaim Dreyfuss 170006f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1701496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 17022e5d4a8fSHaim Dreyfuss return; 17032e5d4a8fSHaim Dreyfuss 170406f4b081SSara Sharon enable_msi: 170506f4b081SSara Sharon ret = pci_enable_msi(pdev); 170606f4b081SSara Sharon if (ret) { 170706f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 17082e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 17092e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 17102e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 17112e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 17122e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 17132e5d4a8fSHaim Dreyfuss } 17142e5d4a8fSHaim Dreyfuss } 17152e5d4a8fSHaim Dreyfuss } 17162e5d4a8fSHaim Dreyfuss 17177c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 17187c8d91ebSHaim Dreyfuss { 17197c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 17207c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17217c8d91ebSHaim Dreyfuss 17227c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 17237c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 17247c8d91ebSHaim Dreyfuss offset = 1 + i; 17257c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 17267c8d91ebSHaim Dreyfuss /* 17277c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 17287c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17297c8d91ebSHaim Dreyfuss */ 17307c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17317c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17327c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17337c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17347c8d91ebSHaim Dreyfuss if (ret) 17357c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17367c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 173757e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 17387c8d91ebSHaim Dreyfuss } 17397c8d91ebSHaim Dreyfuss } 17407c8d91ebSHaim Dreyfuss 17412e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17422e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17432e5d4a8fSHaim Dreyfuss { 1744496d83caSHaim Dreyfuss int i; 17452e5d4a8fSHaim Dreyfuss 1746496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17472e5d4a8fSHaim Dreyfuss int ret; 17485a41a86cSSharon Dvir struct msix_entry *msix_entry; 174964fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 175064fa3affSSharon Dvir 175164fa3affSSharon Dvir if (!qname) 175264fa3affSSharon Dvir return -ENOMEM; 17532e5d4a8fSHaim Dreyfuss 17545a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17555a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17565a41a86cSSharon Dvir msix_entry->vector, 17572e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1758496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17592e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17602e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17612e5d4a8fSHaim Dreyfuss IRQF_SHARED, 176264fa3affSSharon Dvir qname, 17635a41a86cSSharon Dvir msix_entry); 17642e5d4a8fSHaim Dreyfuss if (ret) { 17652e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17662e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17675a41a86cSSharon Dvir 17682e5d4a8fSHaim Dreyfuss return ret; 17692e5d4a8fSHaim Dreyfuss } 17702e5d4a8fSHaim Dreyfuss } 17717c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17722e5d4a8fSHaim Dreyfuss 17732e5d4a8fSHaim Dreyfuss return 0; 17742e5d4a8fSHaim Dreyfuss } 17752e5d4a8fSHaim Dreyfuss 177644f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 177744f61b5cSShahar S Matityahu { 177844f61b5cSShahar S Matityahu u32 hpm, wprot; 177944f61b5cSShahar S Matityahu 1780286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 178144f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 178244f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 178344f61b5cSShahar S Matityahu break; 178444f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 178544f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 178644f61b5cSShahar S Matityahu break; 178744f61b5cSShahar S Matityahu default: 178844f61b5cSShahar S Matityahu return 0; 178944f61b5cSShahar S Matityahu } 179044f61b5cSShahar S Matityahu 179144f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1792d4f1a50cSJohannes Berg if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 179344f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 179444f61b5cSShahar S Matityahu 179544f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 179644f61b5cSShahar S Matityahu IWL_ERR(trans, 179744f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 179844f61b5cSShahar S Matityahu return -EPERM; 179944f61b5cSShahar S Matityahu } 180044f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 180144f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 180244f61b5cSShahar S Matityahu } 180344f61b5cSShahar S Matityahu 180444f61b5cSShahar S Matityahu return 0; 180544f61b5cSShahar S Matityahu } 180644f61b5cSShahar S Matityahu 18070df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 18080df36b90SLuca Coelho { 18090df36b90SLuca Coelho int ret; 18100df36b90SLuca Coelho 1811425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 18120df36b90SLuca Coelho if (ret < 0) 18130df36b90SLuca Coelho return ret; 18140df36b90SLuca Coelho 18150df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18160df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18170df36b90SLuca Coelho udelay(20); 18180df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18190df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 18200df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 18210df36b90SLuca Coelho udelay(20); 18220df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 18230df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18240df36b90SLuca Coelho 182515bf5ac6SJohannes Berg return iwl_trans_pcie_sw_reset(trans, true); 18260df36b90SLuca Coelho } 18270df36b90SLuca Coelho 1828bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1829e705c121SKalle Valo { 1830e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831e705c121SKalle Valo int err; 1832e705c121SKalle Valo 1833e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1834e705c121SKalle Valo 1835e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1836e705c121SKalle Valo if (err) { 1837e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1838e705c121SKalle Valo return err; 1839e705c121SKalle Valo } 1840e705c121SKalle Valo 184144f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 184244f61b5cSShahar S Matityahu if (err) 184344f61b5cSShahar S Matityahu return err; 18448954e1ebSShahar S Matityahu 184515bf5ac6SJohannes Berg err = iwl_trans_pcie_sw_reset(trans, true); 184615bf5ac6SJohannes Berg if (err) 184715bf5ac6SJohannes Berg return err; 1848e705c121SKalle Valo 18490df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18507897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18510df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18520df36b90SLuca Coelho if (err) 18530df36b90SLuca Coelho return err; 18540df36b90SLuca Coelho } 18550df36b90SLuca Coelho 185652b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 185752b6e168SEmmanuel Grumbach if (err) 185852b6e168SEmmanuel Grumbach return err; 1859e705c121SKalle Valo 18602e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 186183730058SHaim Dreyfuss 1862e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1863e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1864e705c121SKalle Valo 1865326477e4SJohannes Berg trans_pcie->opmode_down = false; 1866326477e4SJohannes Berg 1867e705c121SKalle Valo /* Set is_down to false here so that...*/ 1868e705c121SKalle Valo trans_pcie->is_down = false; 1869e705c121SKalle Valo 1870e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18719ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1872e705c121SKalle Valo 1873e705c121SKalle Valo return 0; 1874e705c121SKalle Valo } 1875e705c121SKalle Valo 1876bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1877e705c121SKalle Valo { 1878e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1879e705c121SKalle Valo int ret; 1880e705c121SKalle Valo 1881e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1882bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1883e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1884e705c121SKalle Valo 1885e705c121SKalle Valo return ret; 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 1888e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1889e705c121SKalle Valo { 1890e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1891e705c121SKalle Valo 1892e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1893e705c121SKalle Valo 1894e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1895e705c121SKalle Valo iwl_disable_interrupts(trans); 1896e705c121SKalle Valo 1897e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1898e705c121SKalle Valo 1899e705c121SKalle Valo iwl_disable_interrupts(trans); 1900e705c121SKalle Valo 1901e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1902e705c121SKalle Valo 1903e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1904e705c121SKalle Valo 19052e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1906e705c121SKalle Valo } 1907e705c121SKalle Valo 1908e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1909e705c121SKalle Valo { 1910e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1911e705c121SKalle Valo } 1912e705c121SKalle Valo 1913e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1914e705c121SKalle Valo { 1915e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1916e705c121SKalle Valo } 1917e705c121SKalle Valo 1918e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1919e705c121SKalle Valo { 1920e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1921e705c121SKalle Valo } 1922e705c121SKalle Valo 192384fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 192484fb372cSSara Sharon { 19253681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 192684fb372cSSara Sharon return 0x00FFFFFF; 192784fb372cSSara Sharon else 192884fb372cSSara Sharon return 0x000FFFFF; 192984fb372cSSara Sharon } 193084fb372cSSara Sharon 1931e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1932e705c121SKalle Valo { 193384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 193484fb372cSSara Sharon 1935e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 193684fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1937e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1938e705c121SKalle Valo } 1939e705c121SKalle Valo 1940e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1941e705c121SKalle Valo u32 val) 1942e705c121SKalle Valo { 194384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 194484fb372cSSara Sharon 1945e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 194684fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1947e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1948e705c121SKalle Valo } 1949e705c121SKalle Valo 1950e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1951e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1952e705c121SKalle Valo { 1953e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1954e705c121SKalle Valo 19556ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 19566ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 19576ac57200SJohannes Berg 19584f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 19594f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 19604f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 196122852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 196222852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1963227f2597SJohannes Berg trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 196422852fadSMordechay Goodstein 1965e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1966e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1967e705c121SKalle Valo else 1968e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1969e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1970e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1971e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1972e705c121SKalle Valo 19736c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19746c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19756c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 197680084e35SJohannes Berg trans_pcie->rx_buf_bytes = 197780084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1978cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1979cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1980cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1981e705c121SKalle Valo 19828e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1983e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1984e705c121SKalle Valo 198539bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 198639bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 198739bdb17eSSharon Dvir 1988e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1989e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1990e705c121SKalle Valo * As this function may be called again in some corner cases don't 1991e705c121SKalle Valo * do anything if NAPI was already initialized. 1992e705c121SKalle Valo */ 1993bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1994e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1995906d4eb8SJohannes Berg 1996906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1997e705c121SKalle Valo } 1998e705c121SKalle Valo 19997c9c8477SAlon Giladi void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 2000f6fa5835SAlon Giladi struct device *dev) 2001f6fa5835SAlon Giladi { 2002f6fa5835SAlon Giladi u8 i; 20037c9c8477SAlon Giladi struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 2004f6fa5835SAlon Giladi 20057c9c8477SAlon Giladi /* free DRAM payloads */ 20067c9c8477SAlon Giladi for (i = 0; i < dram_regions->n_regions; i++) { 20077c9c8477SAlon Giladi dma_free_coherent(dev, dram_regions->drams[i].size, 20087c9c8477SAlon Giladi dram_regions->drams[i].block, 20097c9c8477SAlon Giladi dram_regions->drams[i].physical); 2010f6fa5835SAlon Giladi } 20117c9c8477SAlon Giladi dram_regions->n_regions = 0; 201263b9e7b9SAlon Giladi 20137c9c8477SAlon Giladi /* free DRAM addresses array */ 201463b9e7b9SAlon Giladi if (desc_dram->block) { 201563b9e7b9SAlon Giladi dma_free_coherent(dev, desc_dram->size, 201663b9e7b9SAlon Giladi desc_dram->block, 201763b9e7b9SAlon Giladi desc_dram->physical); 201863b9e7b9SAlon Giladi } 20197c9c8477SAlon Giladi memset(desc_dram, 0, sizeof(*desc_dram)); 2020f6fa5835SAlon Giladi } 2021f6fa5835SAlon Giladi 2022c83031afSJohannes Berg static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 2023c83031afSJohannes Berg { 2024c83031afSJohannes Berg iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); 2025c83031afSJohannes Berg } 2026c83031afSJohannes Berg 2027c83031afSJohannes Berg static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 2028c83031afSJohannes Berg { 2029c83031afSJohannes Berg struct iwl_cmd_header_wide bad_cmd = { 2030c83031afSJohannes Berg .cmd = INVALID_WR_PTR_CMD, 2031c83031afSJohannes Berg .group_id = DEBUG_GROUP, 2032c83031afSJohannes Berg .sequence = cpu_to_le16(0xffff), 2033c83031afSJohannes Berg .length = cpu_to_le16(0), 2034c83031afSJohannes Berg .version = 0, 2035c83031afSJohannes Berg }; 2036c83031afSJohannes Berg int ret; 2037c83031afSJohannes Berg 2038c83031afSJohannes Berg ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, 2039c83031afSJohannes Berg sizeof(bad_cmd)); 2040c83031afSJohannes Berg if (ret) 2041c83031afSJohannes Berg return ret; 2042c83031afSJohannes Berg memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 2043c83031afSJohannes Berg return 0; 2044c83031afSJohannes Berg } 2045c83031afSJohannes Berg 2046e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 2047e705c121SKalle Valo { 2048e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20496eb5e529SEmmanuel Grumbach int i; 2050e705c121SKalle Valo 20512e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 2052e705c121SKalle Valo 2053286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 20540cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 205513a3a390SSara Sharon else 2056e705c121SKalle Valo iwl_pcie_tx_free(trans); 2057e705c121SKalle Valo iwl_pcie_rx_free(trans); 2058e705c121SKalle Valo 205910a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 206010a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 206110a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 206210a54d81SLuca Coelho } 206310a54d81SLuca Coelho 20642e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 20657c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 20667c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 20677c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 20687c8d91ebSHaim Dreyfuss NULL); 20697c8d91ebSHaim Dreyfuss } 20702e5d4a8fSHaim Dreyfuss 20712e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 20722e5d4a8fSHaim Dreyfuss } else { 2073e705c121SKalle Valo iwl_pcie_free_ict(trans); 20742e5d4a8fSHaim Dreyfuss } 2075e705c121SKalle Valo 2076c83031afSJohannes Berg iwl_pcie_free_invalid_tx_cmd(trans); 2077c83031afSJohannes Berg 2078e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 2079e705c121SKalle Valo 20807c9c8477SAlon Giladi iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 20817c9c8477SAlon Giladi trans->dev); 20827c9c8477SAlon Giladi iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 20837c9c8477SAlon Giladi trans->dev); 20849dad325fSLuca Coelho 2085a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2086e705c121SKalle Valo iwl_trans_free(trans); 2087e705c121SKalle Valo } 2088e705c121SKalle Valo 2089e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2090e705c121SKalle Valo { 2091e705c121SKalle Valo if (state) 2092e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2093e705c121SKalle Valo else 2094e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2095e705c121SKalle Valo } 2096e705c121SKalle Valo 209749564a80SLuca Coelho struct iwl_trans_pcie_removal { 209849564a80SLuca Coelho struct pci_dev *pdev; 209949564a80SLuca Coelho struct work_struct work; 2100b8133439SAvraham Stern bool rescan; 210149564a80SLuca Coelho }; 210249564a80SLuca Coelho 210349564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 210449564a80SLuca Coelho { 210549564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 210649564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 210749564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2108aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2109b8133439SAvraham Stern struct pci_bus *bus = pdev->bus; 211049564a80SLuca Coelho 211149564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 211249564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 211349564a80SLuca Coelho pci_lock_rescan_remove(); 211449564a80SLuca Coelho pci_dev_put(pdev); 211549564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 2116b8133439SAvraham Stern if (removal->rescan) 2117b8133439SAvraham Stern pci_rescan_bus(bus->parent); 211849564a80SLuca Coelho pci_unlock_rescan_remove(); 211949564a80SLuca Coelho 212049564a80SLuca Coelho kfree(removal); 212149564a80SLuca Coelho module_put(THIS_MODULE); 212249564a80SLuca Coelho } 212349564a80SLuca Coelho 2124b8133439SAvraham Stern void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2125b8133439SAvraham Stern { 2126b8133439SAvraham Stern struct iwl_trans_pcie_removal *removal; 2127b8133439SAvraham Stern 2128b8133439SAvraham Stern if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2129b8133439SAvraham Stern return; 2130b8133439SAvraham Stern 2131b8133439SAvraham Stern IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2132b8133439SAvraham Stern 2133b8133439SAvraham Stern /* 2134b8133439SAvraham Stern * get a module reference to avoid doing this 2135b8133439SAvraham Stern * while unloading anyway and to avoid 2136b8133439SAvraham Stern * scheduling a work with code that's being 2137b8133439SAvraham Stern * removed. 2138b8133439SAvraham Stern */ 2139b8133439SAvraham Stern if (!try_module_get(THIS_MODULE)) { 2140b8133439SAvraham Stern IWL_ERR(trans, 2141b8133439SAvraham Stern "Module is being unloaded - abort\n"); 2142b8133439SAvraham Stern return; 2143b8133439SAvraham Stern } 2144b8133439SAvraham Stern 2145b8133439SAvraham Stern removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2146b8133439SAvraham Stern if (!removal) { 2147b8133439SAvraham Stern module_put(THIS_MODULE); 2148b8133439SAvraham Stern return; 2149b8133439SAvraham Stern } 2150b8133439SAvraham Stern /* 2151b8133439SAvraham Stern * we don't need to clear this flag, because 2152b8133439SAvraham Stern * the trans will be freed and reallocated. 2153b8133439SAvraham Stern */ 2154b8133439SAvraham Stern set_bit(STATUS_TRANS_DEAD, &trans->status); 2155b8133439SAvraham Stern 2156b8133439SAvraham Stern removal->pdev = to_pci_dev(trans->dev); 2157b8133439SAvraham Stern removal->rescan = rescan; 2158b8133439SAvraham Stern INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2159b8133439SAvraham Stern pci_dev_get(removal->pdev); 2160b8133439SAvraham Stern schedule_work(&removal->work); 2161b8133439SAvraham Stern } 2162b8133439SAvraham Stern EXPORT_SYMBOL(iwl_trans_pcie_remove); 2163b8133439SAvraham Stern 2164c544d89bSJohannes Berg /* 2165c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2166c544d89bSJohannes Berg * already disabled. 2167c544d89bSJohannes Berg */ 2168c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2169e705c121SKalle Valo { 2170e705c121SKalle Valo int ret; 2171e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21729ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 21739ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 21749ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 21759ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2176e705c121SKalle Valo 2177c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2178e705c121SKalle Valo 2179e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2180e705c121SKalle Valo goto out; 2181e705c121SKalle Valo 21829ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 21839ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 21849ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21859ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21869ce041f5SJohannes Berg } 21879ce041f5SJohannes Berg 2188e705c121SKalle Valo /* this bit wakes up the NIC */ 21899ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2190286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2191e705c121SKalle Valo udelay(2); 2192e705c121SKalle Valo 2193e705c121SKalle Valo /* 2194e705c121SKalle Valo * These bits say the device is running, and should keep running for 2195e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2196e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2197fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2198fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2199e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2200e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2201e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2202e705c121SKalle Valo * to keep device from sleeping. 2203e705c121SKalle Valo * 2204e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2205e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2206fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2207fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2208fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2209e705c121SKalle Valo * 2210e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2211e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2212e705c121SKalle Valo */ 22139ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2214e705c121SKalle Valo if (unlikely(ret < 0)) { 221549564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 221649564a80SLuca Coelho 2217e705c121SKalle Valo WARN_ONCE(1, 2218e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 221949564a80SLuca Coelho cntrl); 222049564a80SLuca Coelho 222149564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 222249564a80SLuca Coelho 2223b8133439SAvraham Stern if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2224b8133439SAvraham Stern iwl_trans_pcie_remove(trans, false); 2225b8133439SAvraham Stern else 222649564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 222749564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 222849564a80SLuca Coelho 2229c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2230e705c121SKalle Valo return false; 2231e705c121SKalle Valo } 2232e705c121SKalle Valo 2233e705c121SKalle Valo out: 2234e705c121SKalle Valo /* 2235e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2236e705c121SKalle Valo * track nic_access anyway. 2237e705c121SKalle Valo */ 2238e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2239e705c121SKalle Valo return true; 2240e705c121SKalle Valo } 2241e705c121SKalle Valo 2242c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2243c544d89bSJohannes Berg { 2244c544d89bSJohannes Berg bool ret; 2245c544d89bSJohannes Berg 2246c544d89bSJohannes Berg local_bh_disable(); 2247c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2248c544d89bSJohannes Berg if (ret) { 2249c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2250c544d89bSJohannes Berg return ret; 2251c544d89bSJohannes Berg } 2252c544d89bSJohannes Berg local_bh_enable(); 2253c544d89bSJohannes Berg return false; 2254c544d89bSJohannes Berg } 2255c544d89bSJohannes Berg 22561ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2257e705c121SKalle Valo { 2258e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2259e705c121SKalle Valo 2260e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2261e705c121SKalle Valo 2262e705c121SKalle Valo /* 2263e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2264e705c121SKalle Valo * track nic_access anyway. 2265e705c121SKalle Valo */ 2266e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2267e705c121SKalle Valo 2268e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2269e705c121SKalle Valo goto out; 22701b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 22711b6598c3SRoee Goldfiner __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22721b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 22731b6598c3SRoee Goldfiner else 2274e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22756dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2276e705c121SKalle Valo /* 2277e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2278e705c121SKalle Valo * any previous writes, but we need the write that clears the 2279e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2280e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2281e705c121SKalle Valo */ 2282e705c121SKalle Valo out: 2283874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2284e705c121SKalle Valo } 2285e705c121SKalle Valo 2286e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2287e705c121SKalle Valo void *buf, int dwords) 2288e705c121SKalle Valo { 228904516706SJohannes Berg int offs = 0; 2290e705c121SKalle Valo u32 *vals = buf; 2291e705c121SKalle Valo 229204516706SJohannes Berg while (offs < dwords) { 229304516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 229467013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 22953d372c4eSJohannes Berg bool resched = false; 229604516706SJohannes Berg 22971ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 229804516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 229904516706SJohannes Berg addr + 4 * offs); 230004516706SJohannes Berg 230104516706SJohannes Berg while (offs < dwords) { 230204516706SJohannes Berg vals[offs] = iwl_read32(trans, 230304516706SJohannes Berg HBUS_TARG_MEM_RDAT); 230404516706SJohannes Berg offs++; 230504516706SJohannes Berg 23063d372c4eSJohannes Berg if (time_after(jiffies, end)) { 23073d372c4eSJohannes Berg resched = true; 230804516706SJohannes Berg break; 230904516706SJohannes Berg } 23103d372c4eSJohannes Berg } 23111ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 23123d372c4eSJohannes Berg 23133d372c4eSJohannes Berg if (resched) 23143d372c4eSJohannes Berg cond_resched(); 2315e705c121SKalle Valo } else { 231604516706SJohannes Berg return -EBUSY; 2317e705c121SKalle Valo } 231804516706SJohannes Berg } 231904516706SJohannes Berg 232004516706SJohannes Berg return 0; 2321e705c121SKalle Valo } 2322e705c121SKalle Valo 2323e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2324e705c121SKalle Valo const void *buf, int dwords) 2325e705c121SKalle Valo { 2326e705c121SKalle Valo int offs, ret = 0; 2327e705c121SKalle Valo const u32 *vals = buf; 2328e705c121SKalle Valo 23291ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2330e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2331e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2332e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2333e705c121SKalle Valo vals ? vals[offs] : 0); 23341ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2335e705c121SKalle Valo } else { 2336e705c121SKalle Valo ret = -EBUSY; 2337e705c121SKalle Valo } 2338e705c121SKalle Valo return ret; 2339e705c121SKalle Valo } 2340e705c121SKalle Valo 23417f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 23427f1fe1d4SLuca Coelho u32 *val) 23437f1fe1d4SLuca Coelho { 23447f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 23457f1fe1d4SLuca Coelho ofs, val); 23467f1fe1d4SLuca Coelho } 23477f1fe1d4SLuca Coelho 23480cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 23490cd58eaaSEmmanuel Grumbach { 23500cd58eaaSEmmanuel Grumbach int i; 23510cd58eaaSEmmanuel Grumbach 2352286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 23534f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 23540cd58eaaSEmmanuel Grumbach 23554f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 23560cd58eaaSEmmanuel Grumbach continue; 23570cd58eaaSEmmanuel Grumbach 23580cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 23590cd58eaaSEmmanuel Grumbach 23600cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 23610cd58eaaSEmmanuel Grumbach txq->block--; 23620cd58eaaSEmmanuel Grumbach if (!txq->block) { 23630cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2364bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 23650cd58eaaSEmmanuel Grumbach } 23660cd58eaaSEmmanuel Grumbach } else if (block) { 23670cd58eaaSEmmanuel Grumbach txq->block++; 23680cd58eaaSEmmanuel Grumbach } 23690cd58eaaSEmmanuel Grumbach 23700cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 23710cd58eaaSEmmanuel Grumbach } 23720cd58eaaSEmmanuel Grumbach } 23730cd58eaaSEmmanuel Grumbach 2374e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2375e705c121SKalle Valo 237692536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 237792536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 237892536c96SSara Sharon { 237992536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 238092536c96SSara Sharon 238192536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 238292536c96SSara Sharon return -EINVAL; 238392536c96SSara Sharon 238492536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 238592536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 238692536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 238792536c96SSara Sharon data->fr_bd_wid = 0; 238892536c96SSara Sharon 238992536c96SSara Sharon return 0; 239092536c96SSara Sharon } 239192536c96SSara Sharon 2392d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2393e705c121SKalle Valo { 2394e705c121SKalle Valo struct iwl_txq *txq; 2395e705c121SKalle Valo unsigned long now = jiffies; 23962ae48edcSSara Sharon bool overflow_tx; 2397e705c121SKalle Valo u8 wr_ptr; 2398e705c121SKalle Valo 23992b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2400f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2401f60c9e59SEmmanuel Grumbach return -ENODEV; 24022b3fae66SMatt Chen 24034f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2404d6d517b7SSara Sharon return -EINVAL; 2405e705c121SKalle Valo 2406d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 24074f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 24082ae48edcSSara Sharon 24092ae48edcSSara Sharon spin_lock_bh(&txq->lock); 24102ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 24112ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 24122ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 24132ae48edcSSara Sharon 24146aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2415e705c121SKalle Valo 24162ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 24172ae48edcSSara Sharon overflow_tx) && 2418e705c121SKalle Valo !time_after(jiffies, 2419e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 24206aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2421e705c121SKalle Valo 24222ae48edcSSara Sharon /* 24232ae48edcSSara Sharon * If write pointer moved during the wait, warn only 24242ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 24252ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 24262ae48edcSSara Sharon */ 24272ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2428e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2429e705c121SKalle Valo wr_ptr, write_ptr)) 2430e705c121SKalle Valo return -ETIMEDOUT; 24312ae48edcSSara Sharon wr_ptr = write_ptr; 24322ae48edcSSara Sharon 2433192185d6SJohannes Berg usleep_range(1000, 2000); 24342ae48edcSSara Sharon 24352ae48edcSSara Sharon spin_lock_bh(&txq->lock); 24362ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 24372ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 24382ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2439e705c121SKalle Valo } 2440e705c121SKalle Valo 2441bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2442e705c121SKalle Valo IWL_ERR(trans, 2443d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 24440cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2445d6d517b7SSara Sharon return -ETIMEDOUT; 2446e705c121SKalle Valo } 2447e705c121SKalle Valo 2448d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2449d6d517b7SSara Sharon 2450d6d517b7SSara Sharon return 0; 2451d6d517b7SSara Sharon } 2452d6d517b7SSara Sharon 2453d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2454d6d517b7SSara Sharon { 2455d6d517b7SSara Sharon int cnt; 2456d6d517b7SSara Sharon int ret = 0; 2457d6d517b7SSara Sharon 2458d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 245979b6c8feSLuca Coelho for (cnt = 0; 2460286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 246179b6c8feSLuca Coelho cnt++) { 2462d6d517b7SSara Sharon 24634f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2464d6d517b7SSara Sharon continue; 24654f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2466d6d517b7SSara Sharon continue; 2467d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2468d6d517b7SSara Sharon continue; 2469d6d517b7SSara Sharon 2470d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 247138398efbSSara Sharon if (ret) 2472d6d517b7SSara Sharon break; 2473d6d517b7SSara Sharon } 2474e705c121SKalle Valo 2475e705c121SKalle Valo return ret; 2476e705c121SKalle Valo } 2477e705c121SKalle Valo 2478e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2479e705c121SKalle Valo u32 mask, u32 value) 2480e705c121SKalle Valo { 2481e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2482e705c121SKalle Valo 2483874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2484e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2485874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2486e705c121SKalle Valo } 2487e705c121SKalle Valo 2488e705c121SKalle Valo static const char *get_csr_string(int cmd) 2489e705c121SKalle Valo { 2490e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2491e705c121SKalle Valo switch (cmd) { 2492e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2493e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2494e705c121SKalle Valo IWL_CMD(CSR_INT); 2495e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2496e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2497e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2498e705c121SKalle Valo IWL_CMD(CSR_RESET); 2499e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2500e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2501e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2502e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2503e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2504e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2505e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2506e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2507e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2508e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2509e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2510e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2511e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2512e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2513e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2514e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2515e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2516e705c121SKalle Valo default: 2517e705c121SKalle Valo return "UNKNOWN"; 2518e705c121SKalle Valo } 2519e705c121SKalle Valo #undef IWL_CMD 2520e705c121SKalle Valo } 2521e705c121SKalle Valo 2522e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2523e705c121SKalle Valo { 2524e705c121SKalle Valo int i; 2525e705c121SKalle Valo static const u32 csr_tbl[] = { 2526e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2527e705c121SKalle Valo CSR_INT_COALESCING, 2528e705c121SKalle Valo CSR_INT, 2529e705c121SKalle Valo CSR_INT_MASK, 2530e705c121SKalle Valo CSR_FH_INT_STATUS, 2531e705c121SKalle Valo CSR_GPIO_IN, 2532e705c121SKalle Valo CSR_RESET, 2533e705c121SKalle Valo CSR_GP_CNTRL, 2534e705c121SKalle Valo CSR_HW_REV, 2535e705c121SKalle Valo CSR_EEPROM_REG, 2536e705c121SKalle Valo CSR_EEPROM_GP, 2537e705c121SKalle Valo CSR_OTP_GP_REG, 2538e705c121SKalle Valo CSR_GIO_REG, 2539e705c121SKalle Valo CSR_GP_UCODE_REG, 2540e705c121SKalle Valo CSR_GP_DRIVER_REG, 2541e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2542e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2543e705c121SKalle Valo CSR_LED_REG, 2544e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2545e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2546e705c121SKalle Valo CSR_ANA_PLL_CFG, 2547e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2548e705c121SKalle Valo CSR_HW_REV_WA_REG, 2549e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2550e705c121SKalle Valo }; 2551e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2552e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2553e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2554e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2555e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2556e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2557e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2558e705c121SKalle Valo } 2559e705c121SKalle Valo } 2560e705c121SKalle Valo 2561e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2562e705c121SKalle Valo /* create and remove of files */ 2563e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2564cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2565cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2566e705c121SKalle Valo } while (0) 2567e705c121SKalle Valo 2568e705c121SKalle Valo /* file operation */ 2569e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2570e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2571e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2572e705c121SKalle Valo .open = simple_open, \ 2573e705c121SKalle Valo .llseek = generic_file_llseek, \ 2574e705c121SKalle Valo }; 2575e705c121SKalle Valo 2576e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2577e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2578e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2579e705c121SKalle Valo .open = simple_open, \ 2580e705c121SKalle Valo .llseek = generic_file_llseek, \ 2581e705c121SKalle Valo }; 2582e705c121SKalle Valo 2583e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2584e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2585e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2586e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2587e705c121SKalle Valo .open = simple_open, \ 2588e705c121SKalle Valo .llseek = generic_file_llseek, \ 2589e705c121SKalle Valo }; 2590e705c121SKalle Valo 2591df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2592df67a1beSJohannes Berg struct iwl_trans *trans; 2593df67a1beSJohannes Berg }; 2594df67a1beSJohannes Berg 2595df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2596df67a1beSJohannes Berg loff_t pos; 2597df67a1beSJohannes Berg }; 2598df67a1beSJohannes Berg 2599df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2600e705c121SKalle Valo { 2601df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2602df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2603df67a1beSJohannes Berg 2604df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2605df67a1beSJohannes Berg return NULL; 2606df67a1beSJohannes Berg 2607df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2608df67a1beSJohannes Berg if (!state) 2609df67a1beSJohannes Berg return NULL; 2610df67a1beSJohannes Berg state->pos = *pos; 2611df67a1beSJohannes Berg return state; 2612df67a1beSJohannes Berg } 2613df67a1beSJohannes Berg 2614df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2615df67a1beSJohannes Berg void *v, loff_t *pos) 2616df67a1beSJohannes Berg { 2617df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2618df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2619df67a1beSJohannes Berg 2620df67a1beSJohannes Berg *pos = ++state->pos; 2621df67a1beSJohannes Berg 2622df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2623df67a1beSJohannes Berg return NULL; 2624df67a1beSJohannes Berg 2625df67a1beSJohannes Berg return state; 2626df67a1beSJohannes Berg } 2627df67a1beSJohannes Berg 2628df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2629df67a1beSJohannes Berg { 2630df67a1beSJohannes Berg kfree(v); 2631df67a1beSJohannes Berg } 2632df67a1beSJohannes Berg 2633df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2634df67a1beSJohannes Berg { 2635df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2636df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2637df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 26384f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2639e705c121SKalle Valo 2640df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2641df67a1beSJohannes Berg (unsigned int)state->pos, 26424f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 26434f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2644df67a1beSJohannes Berg if (txq) 2645df67a1beSJohannes Berg seq_printf(seq, 264695a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2647df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 264895a9e44fSJohannes Berg txq->need_update, txq->frozen, 264995a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2650df67a1beSJohannes Berg else 2651df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2652e705c121SKalle Valo 26534f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2654df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2655df67a1beSJohannes Berg seq_puts(seq, "\n"); 2656e705c121SKalle Valo 2657df67a1beSJohannes Berg return 0; 2658df67a1beSJohannes Berg } 2659df67a1beSJohannes Berg 2660df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2661df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2662df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2663df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2664df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2665df67a1beSJohannes Berg }; 2666df67a1beSJohannes Berg 2667df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2668df67a1beSJohannes Berg { 2669df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2670df67a1beSJohannes Berg 2671df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2672df67a1beSJohannes Berg sizeof(*priv)); 2673df67a1beSJohannes Berg 2674df67a1beSJohannes Berg if (!priv) 2675e705c121SKalle Valo return -ENOMEM; 2676e705c121SKalle Valo 2677df67a1beSJohannes Berg priv->trans = inode->i_private; 2678df67a1beSJohannes Berg return 0; 2679e705c121SKalle Valo } 2680e705c121SKalle Valo 2681e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2682e705c121SKalle Valo char __user *user_buf, 2683e705c121SKalle Valo size_t count, loff_t *ppos) 2684e705c121SKalle Valo { 2685e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2686e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 268778485054SSara Sharon char *buf; 268878485054SSara Sharon int pos = 0, i, ret; 2689eb3dc36eSColin Ian King size_t bufsz; 2690e705c121SKalle Valo 269178485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 269278485054SSara Sharon 269378485054SSara Sharon if (!trans_pcie->rxq) 269478485054SSara Sharon return -EAGAIN; 269578485054SSara Sharon 269678485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 269778485054SSara Sharon if (!buf) 269878485054SSara Sharon return -ENOMEM; 269978485054SSara Sharon 270078485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 270178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 270278485054SSara Sharon 270378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 270478485054SSara Sharon i); 270578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2706e705c121SKalle Valo rxq->read); 270778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2708e705c121SKalle Valo rxq->write); 270978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2710e705c121SKalle Valo rxq->write_actual); 271178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2712e705c121SKalle Valo rxq->need_update); 271378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2714e705c121SKalle Valo rxq->free_count); 2715e705c121SKalle Valo if (rxq->rb_stts) { 27160307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 27170307c839SGolan Ben Ami rxq)); 271878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 271978485054SSara Sharon "\tclosed_rb_num: %u\n", 27200307c839SGolan Ben Ami r & 0x0FFF); 2721e705c121SKalle Valo } else { 2722e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 272378485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2724e705c121SKalle Valo } 272578485054SSara Sharon } 272678485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 272778485054SSara Sharon kfree(buf); 272878485054SSara Sharon 272978485054SSara Sharon return ret; 2730e705c121SKalle Valo } 2731e705c121SKalle Valo 2732e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2733e705c121SKalle Valo char __user *user_buf, 2734e705c121SKalle Valo size_t count, loff_t *ppos) 2735e705c121SKalle Valo { 2736e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2737e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2738e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2739e705c121SKalle Valo 2740e705c121SKalle Valo int pos = 0; 2741e705c121SKalle Valo char *buf; 2742e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2743e705c121SKalle Valo ssize_t ret; 2744e705c121SKalle Valo 2745e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2746e705c121SKalle Valo if (!buf) 2747e705c121SKalle Valo return -ENOMEM; 2748e705c121SKalle Valo 2749e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2750e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2751e705c121SKalle Valo 2752e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2753e705c121SKalle Valo isr_stats->hw); 2754e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2755e705c121SKalle Valo isr_stats->sw); 2756e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2757e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2758e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2759e705c121SKalle Valo isr_stats->err_code); 2760e705c121SKalle Valo } 2761e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2762e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2763e705c121SKalle Valo isr_stats->sch); 2764e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2765e705c121SKalle Valo isr_stats->alive); 2766e705c121SKalle Valo #endif 2767e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2768e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2769e705c121SKalle Valo 2770e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2771e705c121SKalle Valo isr_stats->ctkill); 2772e705c121SKalle Valo 2773e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2774e705c121SKalle Valo isr_stats->wakeup); 2775e705c121SKalle Valo 2776e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2777e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2778e705c121SKalle Valo 2779e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2780e705c121SKalle Valo isr_stats->tx); 2781e705c121SKalle Valo 2782e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2783e705c121SKalle Valo isr_stats->unhandled); 2784e705c121SKalle Valo 2785e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2786e705c121SKalle Valo kfree(buf); 2787e705c121SKalle Valo return ret; 2788e705c121SKalle Valo } 2789e705c121SKalle Valo 2790e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2791e705c121SKalle Valo const char __user *user_buf, 2792e705c121SKalle Valo size_t count, loff_t *ppos) 2793e705c121SKalle Valo { 2794e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2795e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2796e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2797e705c121SKalle Valo u32 reset_flag; 2798078f1131SJohannes Berg int ret; 2799e705c121SKalle Valo 2800078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2801078f1131SJohannes Berg if (ret) 2802078f1131SJohannes Berg return ret; 2803e705c121SKalle Valo if (reset_flag == 0) 2804e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2805e705c121SKalle Valo 2806e705c121SKalle Valo return count; 2807e705c121SKalle Valo } 2808e705c121SKalle Valo 2809e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2810e705c121SKalle Valo const char __user *user_buf, 2811e705c121SKalle Valo size_t count, loff_t *ppos) 2812e705c121SKalle Valo { 2813e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2814e705c121SKalle Valo 2815e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2816e705c121SKalle Valo 2817e705c121SKalle Valo return count; 2818e705c121SKalle Valo } 2819e705c121SKalle Valo 2820e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2821e705c121SKalle Valo char __user *user_buf, 2822e705c121SKalle Valo size_t count, loff_t *ppos) 2823e705c121SKalle Valo { 2824e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2825e705c121SKalle Valo char *buf = NULL; 2826e705c121SKalle Valo ssize_t ret; 2827e705c121SKalle Valo 2828e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2829e705c121SKalle Valo if (ret < 0) 2830e705c121SKalle Valo return ret; 2831e705c121SKalle Valo if (!buf) 2832e705c121SKalle Valo return -EINVAL; 2833e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2834e705c121SKalle Valo kfree(buf); 2835e705c121SKalle Valo return ret; 2836e705c121SKalle Valo } 2837e705c121SKalle Valo 2838fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2839fa4de7f7SJohannes Berg char __user *user_buf, 2840fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2841fa4de7f7SJohannes Berg { 2842fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2843fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2844fa4de7f7SJohannes Berg char buf[100]; 2845fa4de7f7SJohannes Berg int pos; 2846fa4de7f7SJohannes Berg 2847fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2848fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2849fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2850fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2851fa4de7f7SJohannes Berg 2852fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2853fa4de7f7SJohannes Berg } 2854fa4de7f7SJohannes Berg 2855fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2856fa4de7f7SJohannes Berg const char __user *user_buf, 2857fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2858fa4de7f7SJohannes Berg { 2859fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2860fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2861c5bf4fa1SJohannes Berg bool new_value; 2862fa4de7f7SJohannes Berg int ret; 2863fa4de7f7SJohannes Berg 2864c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2865fa4de7f7SJohannes Berg if (ret) 2866fa4de7f7SJohannes Berg return ret; 2867c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2868fa4de7f7SJohannes Berg return count; 2869fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2870c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2871c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2872fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2873fa4de7f7SJohannes Berg 2874fa4de7f7SJohannes Berg return count; 2875fa4de7f7SJohannes Berg } 2876fa4de7f7SJohannes Berg 2877f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2878f7805b33SLior Cohen struct file *file) 2879f7805b33SLior Cohen { 2880f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2881f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2882f7805b33SLior Cohen 288391c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 288491c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2885f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2886f7805b33SLior Cohen return -ENOENT; 2887f7805b33SLior Cohen } 2888f7805b33SLior Cohen 2889f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2890f7805b33SLior Cohen return -EBUSY; 2891f7805b33SLior Cohen 2892f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2893f7805b33SLior Cohen return simple_open(inode, file); 2894f7805b33SLior Cohen } 2895f7805b33SLior Cohen 2896f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2897f7805b33SLior Cohen struct file *file) 2898f7805b33SLior Cohen { 2899f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2900f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2901f7805b33SLior Cohen 2902f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2903f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2904f7805b33SLior Cohen return 0; 2905f7805b33SLior Cohen } 2906f7805b33SLior Cohen 2907f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2908f7805b33SLior Cohen void *buf, ssize_t *size, 2909f7805b33SLior Cohen ssize_t *bytes_copied) 2910f7805b33SLior Cohen { 291158d1b717SHyunwoo Kim ssize_t buf_size_left = count - *bytes_copied; 2912f7805b33SLior Cohen 2913f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2914f7805b33SLior Cohen if (*size > buf_size_left) 2915f7805b33SLior Cohen *size = buf_size_left; 2916f7805b33SLior Cohen 2917f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2918f7805b33SLior Cohen *bytes_copied += *size; 2919f7805b33SLior Cohen 2920f7805b33SLior Cohen if (buf_size_left == *size) 2921f7805b33SLior Cohen return true; 2922f7805b33SLior Cohen return false; 2923f7805b33SLior Cohen } 2924f7805b33SLior Cohen 2925f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2926f7805b33SLior Cohen char __user *user_buf, 2927f7805b33SLior Cohen size_t count, loff_t *ppos) 2928f7805b33SLior Cohen { 2929f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2930f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 29313827cb59SJohannes Berg u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2932f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2933f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2934f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2935f7805b33SLior Cohen bool b_full; 2936f7805b33SLior Cohen 293791c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2938f7805b33SLior Cohen write_ptr_addr = 293991c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 294091c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2941f7805b33SLior Cohen } else { 2942f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2943f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2944f7805b33SLior Cohen } 2945f7805b33SLior Cohen 294691c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2947f7805b33SLior Cohen return 0; 2948f7805b33SLior Cohen 2949f7805b33SLior Cohen mutex_lock(&data->mutex); 2950f7805b33SLior Cohen if (data->state == 2951f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2952f7805b33SLior Cohen mutex_unlock(&data->mutex); 2953f7805b33SLior Cohen return 0; 2954f7805b33SLior Cohen } 2955f7805b33SLior Cohen 2956f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2957f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2958f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2959f7805b33SLior Cohen 2960f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2961f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2962f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2963f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2964f7805b33SLior Cohen curr_buf, &size, 2965f7805b33SLior Cohen &bytes_copied); 2966f7805b33SLior Cohen data->prev_wr_ptr += size; 2967f7805b33SLior Cohen 2968f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2969f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 297069f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2971f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2972f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2973f7805b33SLior Cohen curr_buf, &size, 2974f7805b33SLior Cohen &bytes_copied); 2975f7805b33SLior Cohen data->prev_wr_ptr += size; 2976f7805b33SLior Cohen 2977f7805b33SLior Cohen if (!b_full) { 2978f7805b33SLior Cohen size = write_ptr; 2979f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2980f7805b33SLior Cohen cpu_addr, &size, 2981f7805b33SLior Cohen &bytes_copied); 2982f7805b33SLior Cohen data->prev_wr_ptr = size; 2983f7805b33SLior Cohen data->prev_wrap_cnt++; 2984f7805b33SLior Cohen } 2985f7805b33SLior Cohen } else { 2986f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2987f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2988f7805b33SLior Cohen IWL_WARN(trans, 2989f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2990f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2991f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2992f7805b33SLior Cohen IWL_WARN(trans, 2993f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2994f7805b33SLior Cohen 2995f7805b33SLior Cohen size = write_ptr; 2996f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2997f7805b33SLior Cohen cpu_addr, &size, 2998f7805b33SLior Cohen &bytes_copied); 2999f7805b33SLior Cohen data->prev_wr_ptr = size; 3000f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 3001f7805b33SLior Cohen } 3002f7805b33SLior Cohen 3003f7805b33SLior Cohen mutex_unlock(&data->mutex); 3004f7805b33SLior Cohen 3005f7805b33SLior Cohen return bytes_copied; 3006f7805b33SLior Cohen } 3007f7805b33SLior Cohen 3008aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 3009aa899e68SJohannes Berg char __user *user_buf, 3010aa899e68SJohannes Berg size_t count, loff_t *ppos) 3011aa899e68SJohannes Berg { 3012aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 3013aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3014aa899e68SJohannes Berg 3015aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 3016aa899e68SJohannes Berg return -ENODEV; 3017aa899e68SJohannes Berg 3018aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 3019aa899e68SJohannes Berg trans_pcie->rf_name, 3020aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 3021aa899e68SJohannes Berg } 3022aa899e68SJohannes Berg 3023e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3024e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 3025e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 3026e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 3027fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3028aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 3029aa899e68SJohannes Berg 3030df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3031df67a1beSJohannes Berg .owner = THIS_MODULE, 3032df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 3033df67a1beSJohannes Berg .read = seq_read, 3034df67a1beSJohannes Berg .llseek = seq_lseek, 3035df67a1beSJohannes Berg .release = seq_release_private, 3036df67a1beSJohannes Berg }; 3037e705c121SKalle Valo 3038f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3039f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 3040f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 3041f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 3042f7805b33SLior Cohen }; 3043f7805b33SLior Cohen 3044f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 3045cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3046e705c121SKalle Valo { 3047f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 3048f8a1edb7SJohannes Berg 30492ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 30502ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 30512ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 30522ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 30532ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 30542ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3055f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3056aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 3057e705c121SKalle Valo } 3058f7805b33SLior Cohen 3059f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3060f7805b33SLior Cohen { 3061f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3062f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 3063f7805b33SLior Cohen 3064f7805b33SLior Cohen mutex_lock(&data->mutex); 3065f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3066f7805b33SLior Cohen mutex_unlock(&data->mutex); 3067f7805b33SLior Cohen } 3068e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3069e705c121SKalle Valo 30706983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3071e705c121SKalle Valo { 3072e705c121SKalle Valo u32 cmdlen = 0; 3073e705c121SKalle Valo int i; 3074e705c121SKalle Valo 3075885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 30760179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3077e705c121SKalle Valo 3078e705c121SKalle Valo return cmdlen; 3079e705c121SKalle Valo } 3080e705c121SKalle Valo 3081e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3082e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3083e705c121SKalle Valo int allocated_rb_nums) 3084e705c121SKalle Valo { 3085e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 308680084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 308778485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 308878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3089e705c121SKalle Valo u32 i, r, j, rb_len = 0; 3090e705c121SKalle Valo 3091e705c121SKalle Valo spin_lock(&rxq->lock); 3092e705c121SKalle Valo 30930307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3094e705c121SKalle Valo 3095e705c121SKalle Valo for (i = rxq->read, j = 0; 3096e705c121SKalle Valo i != r && j < allocated_rb_nums; 3097e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3098e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3099e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3100e705c121SKalle Valo 310159a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 310259a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 3103e705c121SKalle Valo 3104e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3105e705c121SKalle Valo 3106e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3107e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3108e705c121SKalle Valo rb = (void *)(*data)->data; 3109e705c121SKalle Valo rb->index = cpu_to_le32(i); 3110e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3111e705c121SKalle Valo 3112e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3113e705c121SKalle Valo } 3114e705c121SKalle Valo 3115e705c121SKalle Valo spin_unlock(&rxq->lock); 3116e705c121SKalle Valo 3117e705c121SKalle Valo return rb_len; 3118e705c121SKalle Valo } 3119e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3120e705c121SKalle Valo 3121e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3122e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3123e705c121SKalle Valo { 3124e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3125e705c121SKalle Valo __le32 *val; 3126e705c121SKalle Valo int i; 3127e705c121SKalle Valo 3128e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3129e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3130e705c121SKalle Valo val = (void *)(*data)->data; 3131e705c121SKalle Valo 3132e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3133e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3134e705c121SKalle Valo 3135e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3136e705c121SKalle Valo 3137e705c121SKalle Valo return csr_len; 3138e705c121SKalle Valo } 3139e705c121SKalle Valo 3140e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3141e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3142e705c121SKalle Valo { 3143e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3144e705c121SKalle Valo __le32 *val; 3145e705c121SKalle Valo int i; 3146e705c121SKalle Valo 31471ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3148e705c121SKalle Valo return 0; 3149e705c121SKalle Valo 3150e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3151e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3152e705c121SKalle Valo val = (void *)(*data)->data; 3153e705c121SKalle Valo 3154286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3155723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3156723b45e2SLiad Kaufman i += sizeof(u32)) 3157e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3158723b45e2SLiad Kaufman else 3159ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3160ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3161723b45e2SLiad Kaufman i += sizeof(u32)) 3162723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3163723b45e2SLiad Kaufman i)); 3164e705c121SKalle Valo 31651ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3166e705c121SKalle Valo 3167e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3168e705c121SKalle Valo 3169e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3170e705c121SKalle Valo } 3171e705c121SKalle Valo 3172e705c121SKalle Valo static u32 3173e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3174e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3175e705c121SKalle Valo u32 monitor_len) 3176e705c121SKalle Valo { 3177e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3178e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3179e705c121SKalle Valo u32 i; 3180e705c121SKalle Valo 31811ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3182e705c121SKalle Valo return 0; 3183e705c121SKalle Valo 3184ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3185e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3186ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 318714ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3188ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3189e705c121SKalle Valo 31901ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3191e705c121SKalle Valo 3192e705c121SKalle Valo return monitor_len; 3193e705c121SKalle Valo } 3194e705c121SKalle Valo 31957a14c23dSSara Sharon static void 31967a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31977a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31987a14c23dSSara Sharon { 3199c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 32007a14c23dSSara Sharon 3201286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3202c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3203c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3204c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3205c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 320691c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 320791c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 320891c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 320991c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 32107a14c23dSSara Sharon } else { 32117a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 32127a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 32137a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 32147a14c23dSSara Sharon } 3215c88580e1SShahar S Matityahu 3216c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 32177a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 32187a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 32197a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 32207a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3221286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3222c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3223c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3224c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3225cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3226cc598782SRotem Saado write_ptr_val >>= 2; 3227c88580e1SShahar S Matityahu } 3228c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 32297a14c23dSSara Sharon } 32307a14c23dSSara Sharon 3231e705c121SKalle Valo static u32 3232e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3233e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3234e705c121SKalle Valo u32 monitor_len) 3235e705c121SKalle Valo { 323669f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3237e705c121SKalle Valo u32 len = 0; 3238e705c121SKalle Valo 323991c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 324069f0e505SShahar S Matityahu (fw_mon->size && 3241286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3242286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3243e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3244e705c121SKalle Valo 3245e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3246e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 32477a14c23dSSara Sharon 32487a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3249e705c121SKalle Valo 3250e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 325169f0e505SShahar S Matityahu if (fw_mon->size) { 325269f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 325369f0e505SShahar S Matityahu monitor_len = fw_mon->size; 325491c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 32557a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3256e705c121SKalle Valo /* 3257e705c121SKalle Valo * Update pointers to reflect actual values after 3258e705c121SKalle Valo * shifting 3259e705c121SKalle Valo */ 326091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3261fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3262fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 326391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3264fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3265fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3266fd527eb5SGolan Ben Ami } else { 3267e705c121SKalle Valo base = iwl_read_prph(trans, base) << 326891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3269fd527eb5SGolan Ben Ami } 3270fd527eb5SGolan Ben Ami 3271e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3272e705c121SKalle Valo monitor_len / sizeof(u32)); 327391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3274e705c121SKalle Valo monitor_len = 3275e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3276e705c121SKalle Valo fw_mon_data, 3277e705c121SKalle Valo monitor_len); 3278e705c121SKalle Valo } else { 3279e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3280e705c121SKalle Valo monitor_len = 0; 3281e705c121SKalle Valo } 3282e705c121SKalle Valo 3283e705c121SKalle Valo len += monitor_len; 3284e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3285e705c121SKalle Valo } 3286e705c121SKalle Valo 3287e705c121SKalle Valo return len; 3288e705c121SKalle Valo } 3289e705c121SKalle Valo 329093079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3291e705c121SKalle Valo { 329269f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3293da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3294da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 329569f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 329669f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 329791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3298da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3299e705c121SKalle Valo 330091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 330191c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3302fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3303fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 330491c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3305fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3306fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3307fd527eb5SGolan Ben Ami 3308fd527eb5SGolan Ben Ami monitor_len = 3309fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 331091c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3311fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3312fd527eb5SGolan Ben Ami } else { 331391c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 331491c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3315e705c121SKalle Valo 3316e705c121SKalle Valo base = iwl_read_prph(trans, base) << 331791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3318e705c121SKalle Valo end = iwl_read_prph(trans, end) << 331991c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3320e705c121SKalle Valo 3321e705c121SKalle Valo /* Make "end" point to the actual end */ 3322286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3323fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 332491c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 332591c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3326e705c121SKalle Valo monitor_len = end - base; 3327fd527eb5SGolan Ben Ami } 3328da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3329da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3330e705c121SKalle Valo monitor_len; 3331da752717SShahar S Matityahu return monitor_len; 3332e705c121SKalle Valo } 3333da752717SShahar S Matityahu return 0; 3334da752717SShahar S Matityahu } 3335da752717SShahar S Matityahu 3336fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3337fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3338fdb70083SJohannes Berg u32 dump_mask, 3339fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3340fdb70083SJohannes Berg void *sanitize_ctx) 3341da752717SShahar S Matityahu { 3342da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3343da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 33444f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3345da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3346da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3347fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3348da752717SShahar S Matityahu int i, ptr; 3349da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3350286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 335179f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 335279f033f6SSara Sharon 335379f033f6SSara Sharon if (!dump_mask) 335479f033f6SSara Sharon return NULL; 3355da752717SShahar S Matityahu 3356da752717SShahar S Matityahu /* transport dump header */ 3357da752717SShahar S Matityahu len = sizeof(*dump_data); 3358da752717SShahar S Matityahu 3359da752717SShahar S Matityahu /* host commands */ 3360e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3361da752717SShahar S Matityahu len += sizeof(*data) + 33628672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 33638672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3364da752717SShahar S Matityahu 3365da752717SShahar S Matityahu /* FW monitor */ 3366fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3367da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3368e705c121SKalle Valo 3369e705c121SKalle Valo /* CSR registers */ 337079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3371e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3372e705c121SKalle Valo 3373e705c121SKalle Valo /* FH registers */ 337479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3375286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3376723b45e2SLiad Kaufman len += sizeof(*data) + 3377ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3378ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3379723b45e2SLiad Kaufman else 3380723b45e2SLiad Kaufman len += sizeof(*data) + 3381520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3382520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3383520f03eaSShahar S Matityahu } 3384e705c121SKalle Valo 3385e705c121SKalle Valo if (dump_rbs) { 338678485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 338778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3388e705c121SKalle Valo /* RBs */ 33890307c839SGolan Ben Ami num_rbs = 33900307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3391e705c121SKalle Valo & 0x0FFF; 339278485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3393e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3394e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3395e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3396e705c121SKalle Valo } 3397e705c121SKalle Valo 33985538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3399286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3400505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 34015538409bSLiad Kaufman len += sizeof(*data) + 34025538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3403505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 34045538409bSLiad Kaufman 3405e705c121SKalle Valo dump_data = vzalloc(len); 3406e705c121SKalle Valo if (!dump_data) 3407e705c121SKalle Valo return NULL; 3408e705c121SKalle Valo 3409e705c121SKalle Valo len = 0; 3410e705c121SKalle Valo data = (void *)dump_data->data; 3411520f03eaSShahar S Matityahu 3412e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3413885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3414520f03eaSShahar S Matityahu 3415e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3416e705c121SKalle Valo txcmd = (void *)data->data; 3417e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3418bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3419bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 34200cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 342108326a97SJohannes Berg u8 tfdidx; 3422e705c121SKalle Valo u32 caplen, cmdlen; 3423e705c121SKalle Valo 342412a89f01SJohannes Berg if (trans->trans_cfg->gen2) 342508326a97SJohannes Berg tfdidx = idx; 342608326a97SJohannes Berg else 342708326a97SJohannes Berg tfdidx = ptr; 342808326a97SJohannes Berg 3429520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 343008326a97SJohannes Berg (u8 *)cmdq->tfds + 343108326a97SJohannes Berg tfd_size * tfdidx); 3432e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3433e705c121SKalle Valo 3434e705c121SKalle Valo if (cmdlen) { 3435e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3436e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3437e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3438520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3439520f03eaSShahar S Matityahu caplen); 3440fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3441fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3442fdb70083SJohannes Berg txcmd->data, 3443fdb70083SJohannes Berg caplen); 3444e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3445e705c121SKalle Valo } 3446e705c121SKalle Valo 34470cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3448e705c121SKalle Valo } 3449e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3450e705c121SKalle Valo 3451e705c121SKalle Valo data->len = cpu_to_le32(len); 3452e705c121SKalle Valo len += sizeof(*data); 3453e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3454520f03eaSShahar S Matityahu } 3455e705c121SKalle Valo 345679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3457e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 345879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3459e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3460e705c121SKalle Valo if (dump_rbs) 3461e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3462e705c121SKalle Valo 34635538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3464286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 346579b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3466505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 34675538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3468505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 34695538409bSLiad Kaufman 34705538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 34715538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 34725538409bSLiad Kaufman paging = (void *)data->data; 34735538409bSLiad Kaufman paging->index = cpu_to_le32(i); 34745538409bSLiad Kaufman memcpy(paging->data, 3475505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 34765538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 34775538409bSLiad Kaufman 34785538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 34795538409bSLiad Kaufman } 34805538409bSLiad Kaufman } 348179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3482e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3483e705c121SKalle Valo 3484e705c121SKalle Valo dump_data->len = len; 3485e705c121SKalle Valo 3486e705c121SKalle Valo return dump_data; 3487e705c121SKalle Valo } 3488e705c121SKalle Valo 34893161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 34904cbb8e50SLuciano Coelho { 34913161a34dSMordechay Goodstein if (enable) 34923161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 34933161a34dSMordechay Goodstein else 34943161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 34954cbb8e50SLuciano Coelho } 34964cbb8e50SLuciano Coelho 34973161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 34984cbb8e50SLuciano Coelho { 34993161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 35003161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 35013161a34dSMordechay Goodstein 35023161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 35033161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3504571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3505571836a0SMike Golant sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3506571836a0SMike Golant else 35073161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 35083161a34dSMordechay Goodstein } else { 35093161a34dSMordechay Goodstein inta_addr = CSR_INT; 35103161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 35114cbb8e50SLuciano Coelho } 35123161a34dSMordechay Goodstein 35133161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 35143161a34dSMordechay Goodstein } 35154cbb8e50SLuciano Coelho 3516623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3517623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3518623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3519623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3520623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3521623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3522623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3523623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3524623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 35257f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3526623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3527623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3528870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3529623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3530623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3531623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3532623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3533623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3534d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 35353161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 3536c0941aceSMukesh Sisodiya .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3537c0941aceSMukesh Sisodiya .imr_dma_data = iwl_trans_pcie_copy_imr \ 3538623e7766SSara Sharon 3539e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3540623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3541e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3542e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3543e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3544e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3545e705c121SKalle Valo 354613f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3547e705c121SKalle Valo 3548e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3549a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3550e705c121SKalle Valo 3551e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3552e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3553e705c121SKalle Valo 355442db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 355542db09c1SLiad Kaufman 3556d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3557d6d517b7SSara Sharon 3558a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 35590cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3560f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3561f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3562f7805b33SLior Cohen #endif 3563623e7766SSara Sharon }; 3564e705c121SKalle Valo 3565623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3566623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3567623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3568eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3569eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 357077c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3571e705c121SKalle Valo 357213f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3573e705c121SKalle Valo 35740cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3575a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3576623e7766SSara Sharon 3577a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3578ba7136f3SAlex Malamud 35790cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 35800cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3581d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 358292536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3583194d1f84SAlon Giladi .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm, 35846654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3585c738fb61SAlon Giladi .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power, 35869dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3587f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3588f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3589f7805b33SLior Cohen #endif 3590e705c121SKalle Valo }; 3591e705c121SKalle Valo 3592e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3593e705c121SKalle Valo const struct pci_device_id *ent, 35947e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3595e705c121SKalle Valo { 3596e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3597e705c121SKalle Valo struct iwl_trans *trans; 3598fda1bd0dSMordechay Goodstein int ret, addr_size; 3599a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3600f00c3f9eSJohannes Berg void __iomem * const *table; 3601a89c72ffSJohannes Berg 3602fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3603a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3604e705c121SKalle Valo 36055a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 36065a41a86cSSharon Dvir if (ret) 36075a41a86cSSharon Dvir return ERR_PTR(ret); 36085a41a86cSSharon Dvir 3609a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3610fda1bd0dSMordechay Goodstein cfg_trans); 3611e705c121SKalle Valo if (!trans) 3612e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3613e705c121SKalle Valo 3614e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3615e705c121SKalle Valo 3616e705c121SKalle Valo trans_pcie->trans = trans; 3617326477e4SJohannes Berg trans_pcie->opmode_down = true; 3618e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3619e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3620cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3621e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3622e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3623906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3624c0941aceSMukesh Sisodiya init_waitqueue_head(&trans_pcie->imr_waitq); 36258188a18eSJohannes Berg 36268188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 36274c1b3f26STejun Heo WQ_HIGHPRI | WQ_UNBOUND, 0); 36288188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 36298188a18eSJohannes Berg ret = -ENOMEM; 36308188a18eSJohannes Berg goto out_free_trans; 36318188a18eSJohannes Berg } 36328188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 36338188a18eSJohannes Berg 3634c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3635e705c121SKalle Valo 36367e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3637e705c121SKalle Valo /* 3638e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3639e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3640e705c121SKalle Valo * lot of power. 3641e705c121SKalle Valo */ 3642e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3643e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3644e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3645e705c121SKalle Valo } 3646e705c121SKalle Valo 3647e705c121SKalle Valo pci_set_master(pdev); 3648e705c121SKalle Valo 3649885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3650ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3651e705c121SKalle Valo if (ret) { 3652ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3653e705c121SKalle Valo /* both attempts failed: */ 3654e705c121SKalle Valo if (ret) { 3655e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 36565a41a86cSSharon Dvir goto out_no_pci; 3657e705c121SKalle Valo } 3658e705c121SKalle Valo } 3659e705c121SKalle Valo 36605a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3661e705c121SKalle Valo if (ret) { 36625a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 36635a41a86cSSharon Dvir goto out_no_pci; 3664e705c121SKalle Valo } 3665e705c121SKalle Valo 3666f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3667f00c3f9eSJohannes Berg if (!table) { 36685a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3669f00c3f9eSJohannes Berg ret = -ENOMEM; 3670f00c3f9eSJohannes Berg goto out_no_pci; 3671f00c3f9eSJohannes Berg } 3672f00c3f9eSJohannes Berg 3673f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3674f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3675f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3676e705c121SKalle Valo ret = -ENODEV; 36775a41a86cSSharon Dvir goto out_no_pci; 3678e705c121SKalle Valo } 3679e705c121SKalle Valo 3680e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3681e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3682e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3683e705c121SKalle Valo 3684e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3685e705c121SKalle Valo iwl_disable_interrupts(trans); 3686e705c121SKalle Valo 3687e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 36889a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 36899a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 36909a098a89SRajat Jain ret = -EIO; 36919a098a89SRajat Jain goto out_no_pci; 36929a098a89SRajat Jain } 36939a098a89SRajat Jain 3694e705c121SKalle Valo /* 3695e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3696e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3697e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3698e705c121SKalle Valo * in the old format. 3699e705c121SKalle Valo */ 37004adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 370155c6d8f8SMike Golant trans->hw_rev_step = trans->hw_rev & 0xF; 370255c6d8f8SMike Golant else 370355c6d8f8SMike Golant trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3704e705c121SKalle Valo 370599be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 370699be6166SLuca Coelho 37077e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3708e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3709e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3710e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3711e705c121SKalle Valo 3712e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3713e5f3f215SHaim Dreyfuss 3714c83031afSJohannes Berg ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3715c83031afSJohannes Berg if (ret) 3716c83031afSJohannes Berg goto out_no_pci; 3717c239feecSJohannes Berg 37182e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 37192388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 37202388bd7bSDan Carpenter if (ret) 37215a41a86cSSharon Dvir goto out_no_pci; 37222e5d4a8fSHaim Dreyfuss } else { 3723e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3724e705c121SKalle Valo if (ret) 37255a41a86cSSharon Dvir goto out_no_pci; 3726e705c121SKalle Valo 37275a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 37285a41a86cSSharon Dvir iwl_pcie_isr, 3729e705c121SKalle Valo iwl_pcie_irq_handler, 3730e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3731e705c121SKalle Valo if (ret) { 3732e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3733e705c121SKalle Valo goto out_free_ict; 3734e705c121SKalle Valo } 37352e5d4a8fSHaim Dreyfuss } 3736e705c121SKalle Valo 3737f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3738f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3739f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3740f7805b33SLior Cohen #endif 3741f7805b33SLior Cohen 3742a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3743a9248de4SShahar S Matityahu 3744e705c121SKalle Valo return trans; 3745e705c121SKalle Valo 3746e705c121SKalle Valo out_free_ict: 3747e705c121SKalle Valo iwl_pcie_free_ict(trans); 3748e705c121SKalle Valo out_no_pci: 37498188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 37508188a18eSJohannes Berg out_free_trans: 3751e705c121SKalle Valo iwl_trans_free(trans); 3752e705c121SKalle Valo return ERR_PTR(ret); 3753e705c121SKalle Valo } 3754c0941aceSMukesh Sisodiya 3755c0941aceSMukesh Sisodiya void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3756c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3757c0941aceSMukesh Sisodiya { 3758c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_UREG_CHICK, 3759c0941aceSMukesh Sisodiya iwl_read_prph(trans, IMR_UREG_CHICK) | 3760c0941aceSMukesh Sisodiya IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3761c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3762c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3763c0941aceSMukesh Sisodiya (u32)(src_addr & 0xFFFFFFFF)); 3764c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3765c0941aceSMukesh Sisodiya iwl_get_dma_hi_addr(src_addr)); 3766c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3767c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3768c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3769c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3770c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3771c0941aceSMukesh Sisodiya } 3772c0941aceSMukesh Sisodiya 3773c0941aceSMukesh Sisodiya int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3774c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3775c0941aceSMukesh Sisodiya { 3776c0941aceSMukesh Sisodiya struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3777c0941aceSMukesh Sisodiya int ret = -1; 3778c0941aceSMukesh Sisodiya 3779c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_REQUESTED; 3780c0941aceSMukesh Sisodiya iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3781c0941aceSMukesh Sisodiya ret = wait_event_timeout(trans_pcie->imr_waitq, 3782c0941aceSMukesh Sisodiya trans_pcie->imr_status != 3783c0941aceSMukesh Sisodiya IMR_D2S_REQUESTED, 5 * HZ); 3784c0941aceSMukesh Sisodiya if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3785c0941aceSMukesh Sisodiya IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3786c0941aceSMukesh Sisodiya iwl_trans_pcie_dump_regs(trans); 3787c0941aceSMukesh Sisodiya return -ETIMEDOUT; 3788c0941aceSMukesh Sisodiya } 3789c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_IDLE; 3790c0941aceSMukesh Sisodiya return 0; 3791c0941aceSMukesh Sisodiya } 3792