18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 27e705c121SKalle Valo #include "internal.h" 28e705c121SKalle Valo #include "iwl-fh.h" 296654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 30e705c121SKalle Valo 31e705c121SKalle Valo /* extended range in FW SRAM */ 32e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 34e705c121SKalle Valo 354290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 36a6d24fadSRajat Jain { 37c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 38c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 39c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 40a6d24fadSRajat Jain #define PREFIX_LEN 32 41a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 42a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 43a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 44a6d24fadSRajat Jain char *prefix; 45a6d24fadSRajat Jain 46a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 47a6d24fadSRajat Jain return; 48a6d24fadSRajat Jain 49a6d24fadSRajat Jain /* Should be a multiple of 4 */ 50a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 51c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho 54a6d24fadSRajat Jain /* Alloc a max size buffer */ 55a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 56c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho 60a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 61a6d24fadSRajat Jain if (!buf) 62a6d24fadSRajat Jain return; 63a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 64a6d24fadSRajat Jain 65a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 66a6d24fadSRajat Jain 67a6d24fadSRajat Jain /* Print wifi device registers */ 68a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 69a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 70a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 71a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 72a6d24fadSRajat Jain goto err_read; 73a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 74a6d24fadSRajat Jain 75a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 76c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 77a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 78a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79a6d24fadSRajat Jain 80a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 81a6d24fadSRajat Jain if (pos) { 82a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 83a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 84a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 85a6d24fadSRajat Jain goto err_read; 86a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 87a6d24fadSRajat Jain 32, 4, buf, i, 0); 88a6d24fadSRajat Jain } 89a6d24fadSRajat Jain 90a6d24fadSRajat Jain /* Print parent device registers next */ 91a6d24fadSRajat Jain if (!pdev->bus->self) 92a6d24fadSRajat Jain goto out; 93a6d24fadSRajat Jain 94a6d24fadSRajat Jain pdev = pdev->bus->self; 95a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 96a6d24fadSRajat Jain 97a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 98a6d24fadSRajat Jain pci_name(pdev)); 99c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 100a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 101a6d24fadSRajat Jain goto err_read; 102a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Print root port AER registers */ 105a6d24fadSRajat Jain pos = 0; 106a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 107a6d24fadSRajat Jain if (pdev) 108a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 109a6d24fadSRajat Jain if (pos) { 110a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 111a6d24fadSRajat Jain pci_name(pdev)); 112a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 113a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 114a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 115a6d24fadSRajat Jain goto err_read; 116a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 117a6d24fadSRajat Jain 4, buf, i, 0); 118a6d24fadSRajat Jain } 119f3402d6dSSara Sharon goto out; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain err_read: 122a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 123a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 124a6d24fadSRajat Jain out: 125a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 126a6d24fadSRajat Jain kfree(buf); 127a6d24fadSRajat Jain } 128a6d24fadSRajat Jain 129870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 130870c2a11SGolan Ben Ami { 131870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1326dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 133870c2a11SGolan Ben Ami usleep_range(5000, 6000); 134870c2a11SGolan Ben Ami } 135870c2a11SGolan Ben Ami 136e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 137e705c121SKalle Valo { 13869f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 139e705c121SKalle Valo 14069f0e505SShahar S Matityahu if (!fw_mon->size) 14169f0e505SShahar S Matityahu return; 14269f0e505SShahar S Matityahu 14369f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 14469f0e505SShahar S Matityahu fw_mon->physical); 14569f0e505SShahar S Matityahu 14669f0e505SShahar S Matityahu fw_mon->block = NULL; 14769f0e505SShahar S Matityahu fw_mon->physical = 0; 14869f0e505SShahar S Matityahu fw_mon->size = 0; 149e705c121SKalle Valo } 150e705c121SKalle Valo 15188964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 15288964b2eSSara Sharon u8 max_power, u8 min_power) 153e705c121SKalle Valo { 15469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 15569f0e505SShahar S Matityahu void *block = NULL; 15669f0e505SShahar S Matityahu dma_addr_t physical = 0; 157e705c121SKalle Valo u32 size = 0; 158e705c121SKalle Valo u8 power; 159e705c121SKalle Valo 16069f0e505SShahar S Matityahu if (fw_mon->size) 16169f0e505SShahar S Matityahu return; 16269f0e505SShahar S Matityahu 16388964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 164e705c121SKalle Valo size = BIT(power); 16569f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1662d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 16769f0e505SShahar S Matityahu if (!block) 168e705c121SKalle Valo continue; 169e705c121SKalle Valo 170e705c121SKalle Valo IWL_INFO(trans, 171c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 172c5f97542SShahar S Matityahu size); 173e705c121SKalle Valo break; 174e705c121SKalle Valo } 175e705c121SKalle Valo 17669f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 177e705c121SKalle Valo return; 178e705c121SKalle Valo 179e705c121SKalle Valo if (power != max_power) 180e705c121SKalle Valo IWL_ERR(trans, 181e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 182e705c121SKalle Valo (unsigned long)BIT(power - 10), 183e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 184e705c121SKalle Valo 18569f0e505SShahar S Matityahu fw_mon->block = block; 18669f0e505SShahar S Matityahu fw_mon->physical = physical; 18769f0e505SShahar S Matityahu fw_mon->size = size; 18888964b2eSSara Sharon } 18988964b2eSSara Sharon 19088964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 19188964b2eSSara Sharon { 19288964b2eSSara Sharon if (!max_power) { 19388964b2eSSara Sharon /* default max_power is maximum */ 19488964b2eSSara Sharon max_power = 26; 19588964b2eSSara Sharon } else { 19688964b2eSSara Sharon max_power += 11; 19788964b2eSSara Sharon } 19888964b2eSSara Sharon 19988964b2eSSara Sharon if (WARN(max_power > 26, 20088964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 20188964b2eSSara Sharon max_power)) 20288964b2eSSara Sharon return; 20388964b2eSSara Sharon 20469f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 20588964b2eSSara Sharon return; 20688964b2eSSara Sharon 20788964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 208e705c121SKalle Valo } 209e705c121SKalle Valo 210e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 211e705c121SKalle Valo { 212e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 213e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 214e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 215e705c121SKalle Valo } 216e705c121SKalle Valo 217e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 218e705c121SKalle Valo { 219e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 220e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 221e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 222e705c121SKalle Valo } 223e705c121SKalle Valo 224e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 225e705c121SKalle Valo { 226e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 227e705c121SKalle Valo return; 228e705c121SKalle Valo 229e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 230e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 231e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 232e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 233e705c121SKalle Valo else 234e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 235e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 236e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 237e705c121SKalle Valo } 238e705c121SKalle Valo 239e705c121SKalle Valo /* PCI registers */ 240e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 241e705c121SKalle Valo 242eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 243e705c121SKalle Valo { 244e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245e705c121SKalle Valo u16 lctl; 246e705c121SKalle Valo u16 cap; 247e705c121SKalle Valo 248e705c121SKalle Valo /* 249cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 250cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 251cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 252e705c121SKalle Valo */ 2533d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 254cc894b85SLuca Coelho 255cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 256e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 257e705c121SKalle Valo 258e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 259e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 260d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 261e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 262e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 263e705c121SKalle Valo } 264e705c121SKalle Valo 265e705c121SKalle Valo /* 266e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 267e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 268e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 269e705c121SKalle Valo */ 270e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 271e705c121SKalle Valo { 27252b6e168SEmmanuel Grumbach int ret; 27352b6e168SEmmanuel Grumbach 274e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 275e705c121SKalle Valo 276e705c121SKalle Valo /* 277e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 278e705c121SKalle Valo * bits already set by default after reset. 279e705c121SKalle Valo */ 280e705c121SKalle Valo 281e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 282286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 283e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 284e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 285e705c121SKalle Valo 286e705c121SKalle Valo /* 287e705c121SKalle Valo * Disable L0s without affecting L1; 288e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 289e705c121SKalle Valo */ 290e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 291e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 292e705c121SKalle Valo 293e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 294e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 295e705c121SKalle Valo 296e705c121SKalle Valo /* 297e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 298e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 299e705c121SKalle Valo */ 300e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 301e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 302e705c121SKalle Valo 303e705c121SKalle Valo iwl_pcie_apm_config(trans); 304e705c121SKalle Valo 305e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 306286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 30777d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 308e705c121SKalle Valo 3097d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 310c96b5eecSJohannes Berg if (ret) 31152b6e168SEmmanuel Grumbach return ret; 312e705c121SKalle Valo 313e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 314e705c121SKalle Valo /* 315e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 316e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 317e705c121SKalle Valo * not related to host_interrupt_operation_mode. 318e705c121SKalle Valo * 319e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 320e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 321e705c121SKalle Valo * that we wake up from L1 on time. 322e705c121SKalle Valo * 323e705c121SKalle Valo * This looks weird: read twice the same register, discard the 324e705c121SKalle Valo * value, set a bit, and yet again, read that same register 325e705c121SKalle Valo * just to discard the value. But that's the way the hardware 326e705c121SKalle Valo * seems to like it. 327e705c121SKalle Valo */ 328e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 329e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 330e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 331e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 332e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo /* 336e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 337e705c121SKalle Valo * 338e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 339e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 340e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 341e705c121SKalle Valo */ 342e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 343e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 344e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 345e705c121SKalle Valo udelay(20); 346e705c121SKalle Valo 347e705c121SKalle Valo /* Disable L1-Active */ 348e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 349e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 350e705c121SKalle Valo 351e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 352e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 353e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 354e705c121SKalle Valo } 355e705c121SKalle Valo 356e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 357e705c121SKalle Valo 35852b6e168SEmmanuel Grumbach return 0; 359e705c121SKalle Valo } 360e705c121SKalle Valo 361e705c121SKalle Valo /* 362e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 363e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 364e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 365e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 366e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 367e705c121SKalle Valo */ 368e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 369e705c121SKalle Valo { 370e705c121SKalle Valo int ret; 371e705c121SKalle Valo u32 apmg_gp1_reg; 372e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 373e705c121SKalle Valo u32 dl_cfg_reg; 374e705c121SKalle Valo 375e705c121SKalle Valo /* Force XTAL ON */ 376e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 377e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 378e705c121SKalle Valo 379870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 380e705c121SKalle Valo 3817d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 382c96b5eecSJohannes Berg if (WARN_ON(ret)) { 383e705c121SKalle Valo /* Release XTAL ON request */ 384e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 385e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo /* 390e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 391e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 392e705c121SKalle Valo */ 393e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 394e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 395e705c121SKalle Valo 396e705c121SKalle Valo /* 397e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 398e705c121SKalle Valo * caused by APMG idle state. 399e705c121SKalle Valo */ 400e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 401e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 402e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 403e705c121SKalle Valo apmg_xtal_cfg_reg | 404e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 405e705c121SKalle Valo 406870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 407e705c121SKalle Valo 408e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 409e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 410e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 411e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 412e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Clear delay line clock power up */ 415e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 417e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 418e705c121SKalle Valo 419e705c121SKalle Valo /* 420e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 421e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 422e705c121SKalle Valo */ 423e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 424e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 425e705c121SKalle Valo 426e705c121SKalle Valo /* 427e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 428e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 429e705c121SKalle Valo */ 4306dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 431e705c121SKalle Valo 432e705c121SKalle Valo /* Activates XTAL resources monitor */ 433e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 434e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 435e705c121SKalle Valo 436e705c121SKalle Valo /* Release XTAL ON request */ 437e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 438e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 439e705c121SKalle Valo udelay(10); 440e705c121SKalle Valo 441e705c121SKalle Valo /* Release APMG XTAL */ 442e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 443e705c121SKalle Valo apmg_xtal_cfg_reg & 444e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 445e705c121SKalle Valo } 446e705c121SKalle Valo 447e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 448e705c121SKalle Valo { 449e8c8935eSJohannes Berg int ret; 450e705c121SKalle Valo 451e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4526dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 453e705c121SKalle Valo 4546dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4556dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4566dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 457e705c121SKalle Valo if (ret < 0) 458e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 459e705c121SKalle Valo 460e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 461e705c121SKalle Valo } 462e705c121SKalle Valo 463e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 464e705c121SKalle Valo { 465e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 466e705c121SKalle Valo 467e705c121SKalle Valo if (op_mode_leave) { 468e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 469e705c121SKalle Valo iwl_pcie_apm_init(trans); 470e705c121SKalle Valo 471e705c121SKalle Valo /* inform ME that we are leaving */ 472286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 473e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 474e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 475286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 47679b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 477e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 478e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 479e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 480e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 481e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 482e705c121SKalle Valo mdelay(1); 483e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 484e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 485e705c121SKalle Valo } 486e705c121SKalle Valo mdelay(5); 487e705c121SKalle Valo } 488e705c121SKalle Valo 489e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 490e705c121SKalle Valo 491e705c121SKalle Valo /* Stop device's DMA activity */ 492e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 493e705c121SKalle Valo 494e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 495e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 496e705c121SKalle Valo return; 497e705c121SKalle Valo } 498e705c121SKalle Valo 499870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 500e705c121SKalle Valo 501e705c121SKalle Valo /* 502e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 503e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 504e705c121SKalle Valo */ 5056dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 506e705c121SKalle Valo } 507e705c121SKalle Valo 508e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 509e705c121SKalle Valo { 510e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 51152b6e168SEmmanuel Grumbach int ret; 512e705c121SKalle Valo 513e705c121SKalle Valo /* nic_init */ 51425edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 51552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 51625edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 517e705c121SKalle Valo 51852b6e168SEmmanuel Grumbach if (ret) 51952b6e168SEmmanuel Grumbach return ret; 52052b6e168SEmmanuel Grumbach 521e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 522e705c121SKalle Valo 523e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 524e705c121SKalle Valo 525e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5269cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5279cf671d6SEmmanuel Grumbach if (ret) 5289cf671d6SEmmanuel Grumbach return ret; 529e705c121SKalle Valo 530e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5319cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5329cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 533e705c121SKalle Valo return -ENOMEM; 5349cf671d6SEmmanuel Grumbach } 535e705c121SKalle Valo 536286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 537e705c121SKalle Valo /* enable shadow regs in HW */ 538e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 539e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 540e705c121SKalle Valo } 541e705c121SKalle Valo 542e705c121SKalle Valo return 0; 543e705c121SKalle Valo } 544e705c121SKalle Valo 545e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 546e705c121SKalle Valo 547e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 548e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 549e705c121SKalle Valo { 550e705c121SKalle Valo int ret; 551e705c121SKalle Valo 552e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 553e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 554e705c121SKalle Valo 555e705c121SKalle Valo /* See if we got it */ 556e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 557e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 558e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 559e705c121SKalle Valo HW_READY_TIMEOUT); 560e705c121SKalle Valo 561e705c121SKalle Valo if (ret >= 0) 562e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 563e705c121SKalle Valo 564e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 565e705c121SKalle Valo return ret; 566e705c121SKalle Valo } 567e705c121SKalle Valo 568e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 569eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 570e705c121SKalle Valo { 571e705c121SKalle Valo int ret; 572e705c121SKalle Valo int t = 0; 573e705c121SKalle Valo int iter; 574e705c121SKalle Valo 575e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 576e705c121SKalle Valo 577e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 578e705c121SKalle Valo /* If the card is ready, exit 0 */ 579e705c121SKalle Valo if (ret >= 0) 580e705c121SKalle Valo return 0; 581e705c121SKalle Valo 582e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 583e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 584192185d6SJohannes Berg usleep_range(1000, 2000); 585e705c121SKalle Valo 586e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 587e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 588e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 589e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 590e705c121SKalle Valo 591e705c121SKalle Valo do { 592e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 593e705c121SKalle Valo if (ret >= 0) 594e705c121SKalle Valo return 0; 595e705c121SKalle Valo 596e705c121SKalle Valo usleep_range(200, 1000); 597e705c121SKalle Valo t += 200; 598e705c121SKalle Valo } while (t < 150000); 599e705c121SKalle Valo msleep(25); 600e705c121SKalle Valo } 601e705c121SKalle Valo 602e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 603e705c121SKalle Valo 604e705c121SKalle Valo return ret; 605e705c121SKalle Valo } 606e705c121SKalle Valo 607e705c121SKalle Valo /* 608e705c121SKalle Valo * ucode 609e705c121SKalle Valo */ 610564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 611564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 612564cdce7SSara Sharon u32 byte_cnt) 613e705c121SKalle Valo { 614bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 615e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 616e705c121SKalle Valo 617bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 618e705c121SKalle Valo dst_addr); 619e705c121SKalle Valo 620bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 621e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 622e705c121SKalle Valo 623bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 624e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 625e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 626e705c121SKalle Valo 627bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 628bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 629bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 630e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 631e705c121SKalle Valo 632bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 633e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 634e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 635e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 636564cdce7SSara Sharon } 637e705c121SKalle Valo 638564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 639564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 640564cdce7SSara Sharon u32 byte_cnt) 641564cdce7SSara Sharon { 642564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 643564cdce7SSara Sharon int ret; 644564cdce7SSara Sharon 645564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 646564cdce7SSara Sharon 6471ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 648564cdce7SSara Sharon return -EIO; 649564cdce7SSara Sharon 650564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 651564cdce7SSara Sharon byte_cnt); 6521ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 653bac842daSEmmanuel Grumbach 654e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 655e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 656e705c121SKalle Valo if (!ret) { 657e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 658fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 659e705c121SKalle Valo return -ETIMEDOUT; 660e705c121SKalle Valo } 661e705c121SKalle Valo 662e705c121SKalle Valo return 0; 663e705c121SKalle Valo } 664e705c121SKalle Valo 665e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 666e705c121SKalle Valo const struct fw_desc *section) 667e705c121SKalle Valo { 668e705c121SKalle Valo u8 *v_addr; 669e705c121SKalle Valo dma_addr_t p_addr; 670e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 671e705c121SKalle Valo int ret = 0; 672e705c121SKalle Valo 673e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 674e705c121SKalle Valo section_num); 675e705c121SKalle Valo 676e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 677e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 678e705c121SKalle Valo if (!v_addr) { 679e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 680e705c121SKalle Valo chunk_sz = PAGE_SIZE; 681e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 682e705c121SKalle Valo &p_addr, GFP_KERNEL); 683e705c121SKalle Valo if (!v_addr) 684e705c121SKalle Valo return -ENOMEM; 685e705c121SKalle Valo } 686e705c121SKalle Valo 687e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 688e705c121SKalle Valo u32 copy_size, dst_addr; 689e705c121SKalle Valo bool extended_addr = false; 690e705c121SKalle Valo 691e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 692e705c121SKalle Valo dst_addr = section->offset + offset; 693e705c121SKalle Valo 694e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 695e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 696e705c121SKalle Valo extended_addr = true; 697e705c121SKalle Valo 698e705c121SKalle Valo if (extended_addr) 699e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 700e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 701e705c121SKalle Valo 702e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 703e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 704e705c121SKalle Valo copy_size); 705e705c121SKalle Valo 706e705c121SKalle Valo if (extended_addr) 707e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 708e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 709e705c121SKalle Valo 710e705c121SKalle Valo if (ret) { 711e705c121SKalle Valo IWL_ERR(trans, 712e705c121SKalle Valo "Could not load the [%d] uCode section\n", 713e705c121SKalle Valo section_num); 714e705c121SKalle Valo break; 715e705c121SKalle Valo } 716e705c121SKalle Valo } 717e705c121SKalle Valo 718e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 719e705c121SKalle Valo return ret; 720e705c121SKalle Valo } 721e705c121SKalle Valo 722e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 723e705c121SKalle Valo const struct fw_img *image, 724e705c121SKalle Valo int cpu, 725e705c121SKalle Valo int *first_ucode_section) 726e705c121SKalle Valo { 727e705c121SKalle Valo int shift_param; 728e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 729e705c121SKalle Valo u32 val, last_read_idx = 0; 730e705c121SKalle Valo 731e705c121SKalle Valo if (cpu == 1) { 732e705c121SKalle Valo shift_param = 0; 733e705c121SKalle Valo *first_ucode_section = 0; 734e705c121SKalle Valo } else { 735e705c121SKalle Valo shift_param = 16; 736e705c121SKalle Valo (*first_ucode_section)++; 737e705c121SKalle Valo } 738e705c121SKalle Valo 739eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 740e705c121SKalle Valo last_read_idx = i; 741e705c121SKalle Valo 742e705c121SKalle Valo /* 743e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 744e705c121SKalle Valo * CPU1 to CPU2. 745e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 746e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 747e705c121SKalle Valo */ 748e705c121SKalle Valo if (!image->sec[i].data || 749e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 750e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 751e705c121SKalle Valo IWL_DEBUG_FW(trans, 752e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 753e705c121SKalle Valo i); 754e705c121SKalle Valo break; 755e705c121SKalle Valo } 756e705c121SKalle Valo 757e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 758e705c121SKalle Valo if (ret) 759e705c121SKalle Valo return ret; 760e705c121SKalle Valo 761d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 762e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 763e705c121SKalle Valo val = val | (sec_num << shift_param); 764e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 765eda50cdeSSara Sharon 766e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 767e705c121SKalle Valo } 768e705c121SKalle Valo 769e705c121SKalle Valo *first_ucode_section = last_read_idx; 770e705c121SKalle Valo 7712aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 7722aabdbdcSEmmanuel Grumbach 773286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 774e705c121SKalle Valo if (cpu == 1) 775d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 776d6a2c5c7SSara Sharon 0xFFFF); 777e705c121SKalle Valo else 778d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 779d6a2c5c7SSara Sharon 0xFFFFFFFF); 780d6a2c5c7SSara Sharon } else { 781d6a2c5c7SSara Sharon if (cpu == 1) 782d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 783d6a2c5c7SSara Sharon 0xFFFF); 784d6a2c5c7SSara Sharon else 785d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 786d6a2c5c7SSara Sharon 0xFFFFFFFF); 787d6a2c5c7SSara Sharon } 788e705c121SKalle Valo 789e705c121SKalle Valo return 0; 790e705c121SKalle Valo } 791e705c121SKalle Valo 792e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 793e705c121SKalle Valo const struct fw_img *image, 794e705c121SKalle Valo int cpu, 795e705c121SKalle Valo int *first_ucode_section) 796e705c121SKalle Valo { 797e705c121SKalle Valo int i, ret = 0; 798e705c121SKalle Valo u32 last_read_idx = 0; 799e705c121SKalle Valo 8003ce4a038SKirtika Ruchandani if (cpu == 1) 801e705c121SKalle Valo *first_ucode_section = 0; 8023ce4a038SKirtika Ruchandani else 803e705c121SKalle Valo (*first_ucode_section)++; 804e705c121SKalle Valo 805eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 806e705c121SKalle Valo last_read_idx = i; 807e705c121SKalle Valo 808e705c121SKalle Valo /* 809e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 810e705c121SKalle Valo * CPU1 to CPU2. 811e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 812e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 813e705c121SKalle Valo */ 814e705c121SKalle Valo if (!image->sec[i].data || 815e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 816e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 817e705c121SKalle Valo IWL_DEBUG_FW(trans, 818e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 819e705c121SKalle Valo i); 820e705c121SKalle Valo break; 821e705c121SKalle Valo } 822e705c121SKalle Valo 823e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 824e705c121SKalle Valo if (ret) 825e705c121SKalle Valo return ret; 826e705c121SKalle Valo } 827e705c121SKalle Valo 828e705c121SKalle Valo *first_ucode_section = last_read_idx; 829e705c121SKalle Valo 830e705c121SKalle Valo return 0; 831e705c121SKalle Valo } 832e705c121SKalle Valo 833593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 834593fae3eSShahar S Matityahu { 835593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 836593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 837593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 838593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 839593fae3eSShahar S Matityahu 840593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 841593fae3eSShahar S Matityahu return; 842593fae3eSShahar S Matityahu 843593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 844593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 845593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 846593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 847593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 848593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 849593fae3eSShahar S Matityahu 850593fae3eSShahar S Matityahu return; 851593fae3eSShahar S Matityahu } 852593fae3eSShahar S Matityahu 853593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 854593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 855593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 856593fae3eSShahar S Matityahu return; 857593fae3eSShahar S Matityahu 858593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 859593fae3eSShahar S Matityahu 860593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 861593fae3eSShahar S Matityahu alloc_id); 862593fae3eSShahar S Matityahu 863593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 864593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 865593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 866593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 867593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 868593fae3eSShahar S Matityahu } 869593fae3eSShahar S Matityahu 870c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 871e705c121SKalle Valo { 87291c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 87369f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 874e705c121SKalle Valo int i; 875e705c121SKalle Valo 876a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 877593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 8787a14c23dSSara Sharon return; 8797a14c23dSSara Sharon } 8807a14c23dSSara Sharon 881e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 882e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 883e705c121SKalle Valo 884e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 885e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 886e705c121SKalle Valo else 887e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 888e705c121SKalle Valo 88991c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 890e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 891e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 892e705c121SKalle Valo 893e705c121SKalle Valo switch (dest->reg_ops[i].op) { 894e705c121SKalle Valo case CSR_ASSIGN: 895e705c121SKalle Valo iwl_write32(trans, addr, val); 896e705c121SKalle Valo break; 897e705c121SKalle Valo case CSR_SETBIT: 898e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 899e705c121SKalle Valo break; 900e705c121SKalle Valo case CSR_CLEARBIT: 901e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 902e705c121SKalle Valo break; 903e705c121SKalle Valo case PRPH_ASSIGN: 904e705c121SKalle Valo iwl_write_prph(trans, addr, val); 905e705c121SKalle Valo break; 906e705c121SKalle Valo case PRPH_SETBIT: 907e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 908e705c121SKalle Valo break; 909e705c121SKalle Valo case PRPH_CLEARBIT: 910e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 911e705c121SKalle Valo break; 912e705c121SKalle Valo case PRPH_BLOCKBIT: 913e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 914e705c121SKalle Valo IWL_ERR(trans, 915e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 916e705c121SKalle Valo val, addr); 917e705c121SKalle Valo goto monitor; 918e705c121SKalle Valo } 919e705c121SKalle Valo break; 920e705c121SKalle Valo default: 921e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 922e705c121SKalle Valo dest->reg_ops[i].op); 923e705c121SKalle Valo break; 924e705c121SKalle Valo } 925e705c121SKalle Valo } 926e705c121SKalle Valo 927e705c121SKalle Valo monitor: 92869f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 929e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 93069f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 931286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 932e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93369f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 93469f0e505SShahar S Matityahu 256) >> dest->end_shift); 93562d7476dSEmmanuel Grumbach else 93662d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93769f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 93862d7476dSEmmanuel Grumbach dest->end_shift); 939e705c121SKalle Valo } 940e705c121SKalle Valo } 941e705c121SKalle Valo 942e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 943e705c121SKalle Valo const struct fw_img *image) 944e705c121SKalle Valo { 945e705c121SKalle Valo int ret = 0; 946e705c121SKalle Valo int first_ucode_section; 947e705c121SKalle Valo 948e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 949e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 950e705c121SKalle Valo 951e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 952e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 953e705c121SKalle Valo if (ret) 954e705c121SKalle Valo return ret; 955e705c121SKalle Valo 956e705c121SKalle Valo if (image->is_dual_cpus) { 957e705c121SKalle Valo /* set CPU2 header address */ 958e705c121SKalle Valo iwl_write_prph(trans, 959e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 960e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 961e705c121SKalle Valo 962e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 963e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 964e705c121SKalle Valo &first_ucode_section); 965e705c121SKalle Valo if (ret) 966e705c121SKalle Valo return ret; 967e705c121SKalle Valo } 968e705c121SKalle Valo 9699efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 970e705c121SKalle Valo iwl_pcie_apply_destination(trans); 971e705c121SKalle Valo 9722aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 9732aabdbdcSEmmanuel Grumbach 974e705c121SKalle Valo /* release CPU reset */ 975e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 976e705c121SKalle Valo 977e705c121SKalle Valo return 0; 978e705c121SKalle Valo } 979e705c121SKalle Valo 980e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 981e705c121SKalle Valo const struct fw_img *image) 982e705c121SKalle Valo { 983e705c121SKalle Valo int ret = 0; 984e705c121SKalle Valo int first_ucode_section; 985e705c121SKalle Valo 986e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 987e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 988e705c121SKalle Valo 9897a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 990e705c121SKalle Valo iwl_pcie_apply_destination(trans); 991e705c121SKalle Valo 99282ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 99382ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 99482ea7966SSara Sharon 99582ea7966SSara Sharon /* 99682ea7966SSara Sharon * Set default value. On resume reading the values that were 99782ea7966SSara Sharon * zeored can provide debug data on the resume flow. 99882ea7966SSara Sharon * This is for debugging only and has no functional impact. 99982ea7966SSara Sharon */ 100082ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 100182ea7966SSara Sharon 1002e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1003e705c121SKalle Valo /* release CPU reset */ 1004e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1005e705c121SKalle Valo 1006e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1007e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1008e705c121SKalle Valo &first_ucode_section); 1009e705c121SKalle Valo if (ret) 1010e705c121SKalle Valo return ret; 1011e705c121SKalle Valo 1012e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1013e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1014e705c121SKalle Valo &first_ucode_section); 1015e705c121SKalle Valo } 1016e705c121SKalle Valo 10179ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1018727c02dfSSara Sharon { 1019326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1020727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1021326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1022326477e4SJohannes Berg bool report; 1023727c02dfSSara Sharon 1024326477e4SJohannes Berg if (hw_rfkill) { 1025326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1026326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1027326477e4SJohannes Berg } else { 1028326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1029326477e4SJohannes Berg if (trans_pcie->opmode_down) 1030326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1031326477e4SJohannes Berg } 1032727c02dfSSara Sharon 1033326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1034326477e4SJohannes Berg 1035326477e4SJohannes Berg if (prev != report) 1036326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1037727c02dfSSara Sharon 1038727c02dfSSara Sharon return hw_rfkill; 1039727c02dfSSara Sharon } 1040727c02dfSSara Sharon 10417ca00409SHaim Dreyfuss struct iwl_causes_list { 10427ca00409SHaim Dreyfuss u32 cause_num; 10437ca00409SHaim Dreyfuss u32 mask_reg; 10447ca00409SHaim Dreyfuss u8 addr; 10457ca00409SHaim Dreyfuss }; 10467ca00409SHaim Dreyfuss 10477ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 10487ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10497ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10507ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10517ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10527ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10537ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1054906d4eb8SJohannes Berg {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10557ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10567ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 10577ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 10587ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 10597ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 10607ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 10617ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 10627ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 10637ca00409SHaim Dreyfuss }; 10647ca00409SHaim Dreyfuss 10657ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 10667ca00409SHaim Dreyfuss { 10677ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10687ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 10693681021fSJohannes Berg int i, arr_size = ARRAY_SIZE(causes_list); 10703681021fSJohannes Berg struct iwl_causes_list *causes = causes_list; 10717ca00409SHaim Dreyfuss 10727ca00409SHaim Dreyfuss /* 10737ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 10747ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 10757ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 10767ca00409SHaim Dreyfuss */ 10779b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 10789b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 10799b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 10809b58419eSGolan Ben Ami causes[i].cause_num); 10817ca00409SHaim Dreyfuss } 10827ca00409SHaim Dreyfuss } 10837ca00409SHaim Dreyfuss 10847ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 10857ca00409SHaim Dreyfuss { 10867ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10877ca00409SHaim Dreyfuss u32 offset = 10887ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 10897ca00409SHaim Dreyfuss u32 val, idx; 10907ca00409SHaim Dreyfuss 10917ca00409SHaim Dreyfuss /* 10927ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 10937ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 10947ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 10957ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 10967ca00409SHaim Dreyfuss */ 10977ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 10987ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 10997ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11007ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11017ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11027ca00409SHaim Dreyfuss } 11037ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11047ca00409SHaim Dreyfuss 11057ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11067ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11077ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11087ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11097ca00409SHaim Dreyfuss 11107ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11117ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11127ca00409SHaim Dreyfuss } 11137ca00409SHaim Dreyfuss 111477c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11157ca00409SHaim Dreyfuss { 11167ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11177ca00409SHaim Dreyfuss 11187ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1119286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1120d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1121ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11227ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11237ca00409SHaim Dreyfuss return; 11247ca00409SHaim Dreyfuss } 1125d7270d61SHaim Dreyfuss /* 1126d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1127d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1128d7270d61SHaim Dreyfuss * prph. 1129d7270d61SHaim Dreyfuss */ 1130d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1131ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11327ca00409SHaim Dreyfuss 11337ca00409SHaim Dreyfuss /* 11347ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11357ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11367ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11377ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11387ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11397ca00409SHaim Dreyfuss */ 11407ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 11417ca00409SHaim Dreyfuss 11427ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 114383730058SHaim Dreyfuss } 11447ca00409SHaim Dreyfuss 114583730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 114683730058SHaim Dreyfuss { 114783730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 114883730058SHaim Dreyfuss 114983730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 115083730058SHaim Dreyfuss 115183730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 115283730058SHaim Dreyfuss return; 115383730058SHaim Dreyfuss 115483730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 11557ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 115683730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 11577ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 11587ca00409SHaim Dreyfuss } 11597ca00409SHaim Dreyfuss 1160bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1161e705c121SKalle Valo { 1162e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1163e705c121SKalle Valo 1164e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1165e705c121SKalle Valo 1166e705c121SKalle Valo if (trans_pcie->is_down) 1167e705c121SKalle Valo return; 1168e705c121SKalle Valo 1169e705c121SKalle Valo trans_pcie->is_down = true; 1170e705c121SKalle Valo 1171e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1172e705c121SKalle Valo iwl_disable_interrupts(trans); 1173e705c121SKalle Valo 1174e705c121SKalle Valo /* device going down, Stop using ICT table */ 1175e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1176e705c121SKalle Valo 1177e705c121SKalle Valo /* 1178e705c121SKalle Valo * If a HW restart happens during firmware loading, 1179e705c121SKalle Valo * then the firmware loading might call this function 1180e705c121SKalle Valo * and later it might be called again due to the 1181e705c121SKalle Valo * restart. So don't process again if the device is 1182e705c121SKalle Valo * already dead. 1183e705c121SKalle Valo */ 1184e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1185a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1186a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1187e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1188e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1189e705c121SKalle Valo 1190e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1191e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1192e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1193e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1194e705c121SKalle Valo udelay(5); 1195e705c121SKalle Valo } 1196e705c121SKalle Valo } 1197e705c121SKalle Valo 1198e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1199e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12006dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1201e705c121SKalle Valo 1202e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1203e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1204e705c121SKalle Valo 1205870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1206e705c121SKalle Valo 1207e705c121SKalle Valo /* 1208f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1209f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1210f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1211f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1212f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1213f4a1f04aSGolan Ben Ami */ 1214f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1215f4a1f04aSGolan Ben Ami 1216f4a1f04aSGolan Ben Ami /* 1217e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1218e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1219e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1220e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1221e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1222e705c121SKalle Valo */ 1223e705c121SKalle Valo iwl_disable_interrupts(trans); 1224e705c121SKalle Valo 1225e705c121SKalle Valo /* clear all status bits */ 1226e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1227e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1228e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1229e705c121SKalle Valo 1230e705c121SKalle Valo /* 1231e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1232e705c121SKalle Valo * interrupt 1233e705c121SKalle Valo */ 1234e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1235e705c121SKalle Valo 1236a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1237e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1238e705c121SKalle Valo } 1239e705c121SKalle Valo 1240eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 12412e5d4a8fSHaim Dreyfuss { 12422e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12432e5d4a8fSHaim Dreyfuss 12442e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 12452e5d4a8fSHaim Dreyfuss int i; 12462e5d4a8fSHaim Dreyfuss 1247496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 12482e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 12492e5d4a8fSHaim Dreyfuss } else { 12502e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 12512e5d4a8fSHaim Dreyfuss } 12522e5d4a8fSHaim Dreyfuss } 12532e5d4a8fSHaim Dreyfuss 1254a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1255a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1256a6bd005fSEmmanuel Grumbach { 1257a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1258a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1259a6bd005fSEmmanuel Grumbach int ret; 1260a6bd005fSEmmanuel Grumbach 1261a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1262a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1263a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1264a6bd005fSEmmanuel Grumbach ret = -EIO; 1265a6bd005fSEmmanuel Grumbach goto out; 1266a6bd005fSEmmanuel Grumbach } 1267a6bd005fSEmmanuel Grumbach 1268a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1269a6bd005fSEmmanuel Grumbach 1270a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1271a6bd005fSEmmanuel Grumbach 1272a6bd005fSEmmanuel Grumbach /* 1273a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1274a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1275a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1276a6bd005fSEmmanuel Grumbach */ 1277a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1278a6bd005fSEmmanuel Grumbach 1279a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 12802e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1281a6bd005fSEmmanuel Grumbach 1282a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1283a6bd005fSEmmanuel Grumbach 1284a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 12859ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1286a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1287a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1288a6bd005fSEmmanuel Grumbach goto out; 1289a6bd005fSEmmanuel Grumbach } 1290a6bd005fSEmmanuel Grumbach 1291a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1292a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1293a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1294a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 129520aa99bbSAnton Protopopov ret = -EIO; 1296a6bd005fSEmmanuel Grumbach goto out; 1297a6bd005fSEmmanuel Grumbach } 1298a6bd005fSEmmanuel Grumbach 1299a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1300a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1301a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1302a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1303a6bd005fSEmmanuel Grumbach 1304a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1305a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1306a6bd005fSEmmanuel Grumbach 1307a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1308a6bd005fSEmmanuel Grumbach if (ret) { 1309a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1310a6bd005fSEmmanuel Grumbach goto out; 1311a6bd005fSEmmanuel Grumbach } 1312a6bd005fSEmmanuel Grumbach 1313a6bd005fSEmmanuel Grumbach /* 1314a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1315a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1316a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1317a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1318a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1319a6bd005fSEmmanuel Grumbach */ 1320a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1321a6bd005fSEmmanuel Grumbach 1322a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1323a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1324a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1325a6bd005fSEmmanuel Grumbach 1326a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1327286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1328a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1329a6bd005fSEmmanuel Grumbach else 1330a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1331a6bd005fSEmmanuel Grumbach 1332a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13339ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1334a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1335a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1336a6bd005fSEmmanuel Grumbach 1337a6bd005fSEmmanuel Grumbach out: 1338a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1339a6bd005fSEmmanuel Grumbach return ret; 1340a6bd005fSEmmanuel Grumbach } 1341a6bd005fSEmmanuel Grumbach 1342a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1343a6bd005fSEmmanuel Grumbach { 1344a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1345a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1346a6bd005fSEmmanuel Grumbach } 1347a6bd005fSEmmanuel Grumbach 1348326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1349326477e4SJohannes Berg bool was_in_rfkill) 1350326477e4SJohannes Berg { 1351326477e4SJohannes Berg bool hw_rfkill; 1352326477e4SJohannes Berg 1353326477e4SJohannes Berg /* 1354326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1355326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1356326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1357326477e4SJohannes Berg * op_mode. 1358326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1359326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1360326477e4SJohannes Berg * notification without endless recursion. Under very rare 1361326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1362326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1363326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1364326477e4SJohannes Berg */ 1365326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1366326477e4SJohannes Berg if (hw_rfkill) { 1367326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1368326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1369326477e4SJohannes Berg } else { 1370326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1371326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1372326477e4SJohannes Berg } 1373326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1374326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1375326477e4SJohannes Berg } 1376326477e4SJohannes Berg 1377bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1378e705c121SKalle Valo { 1379e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1380326477e4SJohannes Berg bool was_in_rfkill; 1381e705c121SKalle Valo 1382d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1383d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1384d0129315SMordechay Goodstein NULL); 1385d0129315SMordechay Goodstein 1386e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1387326477e4SJohannes Berg trans_pcie->opmode_down = true; 1388326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1389bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1390326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1391e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1392e705c121SKalle Valo } 1393e705c121SKalle Valo 1394e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1395e705c121SKalle Valo { 1396e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1397e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1398e705c121SKalle Valo 1399e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1400e705c121SKalle Valo 1401326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1402326477e4SJohannes Berg state ? "disabled" : "enabled"); 140377c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1404286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1405bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 140677c09bc8SSara Sharon else 1407bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1408e705c121SKalle Valo } 140977c09bc8SSara Sharon } 1410e705c121SKalle Valo 1411e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1412e5f3f215SHaim Dreyfuss bool test, bool reset) 1413e705c121SKalle Valo { 1414e705c121SKalle Valo iwl_disable_interrupts(trans); 1415e705c121SKalle Valo 1416e705c121SKalle Valo /* 1417e705c121SKalle Valo * in testing mode, the host stays awake and the 1418e705c121SKalle Valo * hardware won't be reset (not even partially) 1419e705c121SKalle Valo */ 1420e705c121SKalle Valo if (test) 1421e705c121SKalle Valo return; 1422e705c121SKalle Valo 1423e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1424e705c121SKalle Valo 14252e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1426e705c121SKalle Valo 1427e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14286dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14296dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1430e705c121SKalle Valo 143123ae6128SMatti Gottlieb if (reset) { 1432e705c121SKalle Valo /* 1433e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1434e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1435e705c121SKalle Valo * to execute some invalid memory upon resume 1436e705c121SKalle Valo */ 1437e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1438e705c121SKalle Valo } 1439e705c121SKalle Valo 1440e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1441e705c121SKalle Valo } 1442e705c121SKalle Valo 1443e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1444e5f3f215SHaim Dreyfuss bool reset) 1445e5f3f215SHaim Dreyfuss { 1446e5f3f215SHaim Dreyfuss int ret; 1447e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1448e5f3f215SHaim Dreyfuss 1449771db3a1SHaim Dreyfuss if (!reset) 1450e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1451e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1452e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1453e5f3f215SHaim Dreyfuss 1454e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1455e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1456e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1457e5f3f215SHaim Dreyfuss 1458e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1459e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1460e5f3f215SHaim Dreyfuss /* 1461e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1462e5f3f215SHaim Dreyfuss */ 1463e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1464e5f3f215SHaim Dreyfuss 1465e5f3f215SHaim Dreyfuss if (!ret) { 1466e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1467e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1468e5f3f215SHaim Dreyfuss } 1469e5f3f215SHaim Dreyfuss } 1470e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1471e5f3f215SHaim Dreyfuss 1472e5f3f215SHaim Dreyfuss return 0; 1473e5f3f215SHaim Dreyfuss } 1474e5f3f215SHaim Dreyfuss 1475e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1476e705c121SKalle Valo enum iwl_d3_status *status, 147723ae6128SMatti Gottlieb bool test, bool reset) 1478e705c121SKalle Valo { 1479d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1480e705c121SKalle Valo u32 val; 1481e705c121SKalle Valo int ret; 1482e705c121SKalle Valo 1483e705c121SKalle Valo if (test) { 1484e705c121SKalle Valo iwl_enable_interrupts(trans); 1485e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1486e5f3f215SHaim Dreyfuss goto out; 1487e705c121SKalle Valo } 1488e705c121SKalle Valo 1489a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 14906dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1491e705c121SKalle Valo 14927d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1493c96b5eecSJohannes Berg if (ret) 1494e705c121SKalle Valo return ret; 1495e705c121SKalle Valo 1496f98ad635SEmmanuel Grumbach /* 1497f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1498f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1499f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1500f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1501f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1502f98ad635SEmmanuel Grumbach */ 1503f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1504f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1505f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1506f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1507f98ad635SEmmanuel Grumbach 1508e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1509e705c121SKalle Valo 151023ae6128SMatti Gottlieb if (!reset) { 1511e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15126dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1513e705c121SKalle Valo } else { 1514e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1515e705c121SKalle Valo 1516e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1517e705c121SKalle Valo if (ret) { 1518e705c121SKalle Valo IWL_ERR(trans, 1519e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1520e705c121SKalle Valo return ret; 1521e705c121SKalle Valo } 1522e705c121SKalle Valo } 1523e705c121SKalle Valo 152482ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1525ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 152682ea7966SSara Sharon 1527e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1528e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1529e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1530e705c121SKalle Valo else 1531e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1532e705c121SKalle Valo 1533e5f3f215SHaim Dreyfuss out: 1534e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1535e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1536e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1537e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1538e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1539e5f3f215SHaim Dreyfuss 1540e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1541e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1542e5f3f215SHaim Dreyfuss /* 1543e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1544e5f3f215SHaim Dreyfuss */ 1545e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1546e5f3f215SHaim Dreyfuss 1547e5f3f215SHaim Dreyfuss if (!ret) { 1548e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1549e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1550e5f3f215SHaim Dreyfuss } 1551e5f3f215SHaim Dreyfuss } 1552e705c121SKalle Valo return 0; 1553e705c121SKalle Valo } 1554e705c121SKalle Valo 15550c18714aSLuca Coelho static void 15560c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15570c18714aSLuca Coelho struct iwl_trans *trans, 15580c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 15592e5d4a8fSHaim Dreyfuss { 15602e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1561ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15622e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15630cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 15642e5d4a8fSHaim Dreyfuss 15650c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 156606f4b081SSara Sharon goto enable_msi; 156706f4b081SSara Sharon 15680cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 15690cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 15700cd38f4dSMordechay Goodstein 15710cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 157206f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15732e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15742e5d4a8fSHaim Dreyfuss 157506f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15762e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 157706f4b081SSara Sharon max_irqs); 157806f4b081SSara Sharon if (num_irqs < 0) { 1579496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 158006f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 158106f4b081SSara Sharon num_irqs); 158206f4b081SSara Sharon goto enable_msi; 1583496d83caSHaim Dreyfuss } 158406f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1585496d83caSHaim Dreyfuss 15862e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 158706f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 158806f4b081SSara Sharon num_irqs); 158906f4b081SSara Sharon 1590496d83caSHaim Dreyfuss /* 159106f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 159206f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1593496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1594496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1595496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1596496d83caSHaim Dreyfuss */ 1597ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 159806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1599496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1600496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1601ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 160206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1603496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1604496d83caSHaim Dreyfuss } else { 160506f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1606496d83caSHaim Dreyfuss } 16079d401222SMordechay Goodstein 16089d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16099d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16109d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16119d401222SMordechay Goodstein 1612ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16132e5d4a8fSHaim Dreyfuss 161406f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1615496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16162e5d4a8fSHaim Dreyfuss return; 16172e5d4a8fSHaim Dreyfuss 161806f4b081SSara Sharon enable_msi: 161906f4b081SSara Sharon ret = pci_enable_msi(pdev); 162006f4b081SSara Sharon if (ret) { 162106f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16222e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16232e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16242e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16252e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16262e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16272e5d4a8fSHaim Dreyfuss } 16282e5d4a8fSHaim Dreyfuss } 16292e5d4a8fSHaim Dreyfuss } 16302e5d4a8fSHaim Dreyfuss 16317c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16327c8d91ebSHaim Dreyfuss { 16337c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16347c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16357c8d91ebSHaim Dreyfuss 16367c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16377c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16387c8d91ebSHaim Dreyfuss offset = 1 + i; 16397c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16407c8d91ebSHaim Dreyfuss /* 16417c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16427c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16437c8d91ebSHaim Dreyfuss */ 16447c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16457c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16467c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16477c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16487c8d91ebSHaim Dreyfuss if (ret) 16497c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16507c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16517c8d91ebSHaim Dreyfuss i); 16527c8d91ebSHaim Dreyfuss } 16537c8d91ebSHaim Dreyfuss } 16547c8d91ebSHaim Dreyfuss 16552e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16562e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16572e5d4a8fSHaim Dreyfuss { 1658496d83caSHaim Dreyfuss int i; 16592e5d4a8fSHaim Dreyfuss 1660496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16612e5d4a8fSHaim Dreyfuss int ret; 16625a41a86cSSharon Dvir struct msix_entry *msix_entry; 166364fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 166464fa3affSSharon Dvir 166564fa3affSSharon Dvir if (!qname) 166664fa3affSSharon Dvir return -ENOMEM; 16672e5d4a8fSHaim Dreyfuss 16685a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16695a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16705a41a86cSSharon Dvir msix_entry->vector, 16712e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1672496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16732e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16742e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16752e5d4a8fSHaim Dreyfuss IRQF_SHARED, 167664fa3affSSharon Dvir qname, 16775a41a86cSSharon Dvir msix_entry); 16782e5d4a8fSHaim Dreyfuss if (ret) { 16792e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16802e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16815a41a86cSSharon Dvir 16822e5d4a8fSHaim Dreyfuss return ret; 16832e5d4a8fSHaim Dreyfuss } 16842e5d4a8fSHaim Dreyfuss } 16857c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 16862e5d4a8fSHaim Dreyfuss 16872e5d4a8fSHaim Dreyfuss return 0; 16882e5d4a8fSHaim Dreyfuss } 16892e5d4a8fSHaim Dreyfuss 169044f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 169144f61b5cSShahar S Matityahu { 169244f61b5cSShahar S Matityahu u32 hpm, wprot; 169344f61b5cSShahar S Matityahu 1694286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 169544f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 169644f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 169744f61b5cSShahar S Matityahu break; 169844f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 169944f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 170044f61b5cSShahar S Matityahu break; 170144f61b5cSShahar S Matityahu default: 170244f61b5cSShahar S Matityahu return 0; 170344f61b5cSShahar S Matityahu } 170444f61b5cSShahar S Matityahu 170544f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 170644f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 170744f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 170844f61b5cSShahar S Matityahu 170944f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 171044f61b5cSShahar S Matityahu IWL_ERR(trans, 171144f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 171244f61b5cSShahar S Matityahu return -EPERM; 171344f61b5cSShahar S Matityahu } 171444f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 171544f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 171644f61b5cSShahar S Matityahu } 171744f61b5cSShahar S Matityahu 171844f61b5cSShahar S Matityahu return 0; 171944f61b5cSShahar S Matityahu } 172044f61b5cSShahar S Matityahu 17210df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17220df36b90SLuca Coelho { 17230df36b90SLuca Coelho int ret; 17240df36b90SLuca Coelho 17250df36b90SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 17260df36b90SLuca Coelho if (ret < 0) 17270df36b90SLuca Coelho return ret; 17280df36b90SLuca Coelho 17290df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17300df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17310df36b90SLuca Coelho udelay(20); 17320df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17330df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 17340df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 17350df36b90SLuca Coelho udelay(20); 17360df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 17370df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17380df36b90SLuca Coelho 17390df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 17400df36b90SLuca Coelho 17410df36b90SLuca Coelho return 0; 17420df36b90SLuca Coelho } 17430df36b90SLuca Coelho 1744bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1745e705c121SKalle Valo { 1746e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1747e705c121SKalle Valo int err; 1748e705c121SKalle Valo 1749e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1750e705c121SKalle Valo 1751e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1752e705c121SKalle Valo if (err) { 1753e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1754e705c121SKalle Valo return err; 1755e705c121SKalle Valo } 1756e705c121SKalle Valo 175744f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 175844f61b5cSShahar S Matityahu if (err) 175944f61b5cSShahar S Matityahu return err; 17608954e1ebSShahar S Matityahu 1761870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1762e705c121SKalle Valo 17630df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 17647897dfa2SLuca Coelho trans->trans_cfg->integrated) { 17650df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 17660df36b90SLuca Coelho if (err) 17670df36b90SLuca Coelho return err; 17680df36b90SLuca Coelho } 17690df36b90SLuca Coelho 177052b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 177152b6e168SEmmanuel Grumbach if (err) 177252b6e168SEmmanuel Grumbach return err; 1773e705c121SKalle Valo 17742e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 177583730058SHaim Dreyfuss 1776e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1777e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1778e705c121SKalle Valo 1779326477e4SJohannes Berg trans_pcie->opmode_down = false; 1780326477e4SJohannes Berg 1781e705c121SKalle Valo /* Set is_down to false here so that...*/ 1782e705c121SKalle Valo trans_pcie->is_down = false; 1783e705c121SKalle Valo 1784e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17859ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1786e705c121SKalle Valo 1787e705c121SKalle Valo return 0; 1788e705c121SKalle Valo } 1789e705c121SKalle Valo 1790bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1791e705c121SKalle Valo { 1792e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1793e705c121SKalle Valo int ret; 1794e705c121SKalle Valo 1795e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1796bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1797e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1798e705c121SKalle Valo 1799e705c121SKalle Valo return ret; 1800e705c121SKalle Valo } 1801e705c121SKalle Valo 1802e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1803e705c121SKalle Valo { 1804e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1805e705c121SKalle Valo 1806e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1807e705c121SKalle Valo 1808e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1809e705c121SKalle Valo iwl_disable_interrupts(trans); 1810e705c121SKalle Valo 1811e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1812e705c121SKalle Valo 1813e705c121SKalle Valo iwl_disable_interrupts(trans); 1814e705c121SKalle Valo 1815e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1816e705c121SKalle Valo 1817e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1818e705c121SKalle Valo 18192e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1820e705c121SKalle Valo } 1821e705c121SKalle Valo 1822e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1823e705c121SKalle Valo { 1824e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1825e705c121SKalle Valo } 1826e705c121SKalle Valo 1827e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1828e705c121SKalle Valo { 1829e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1830e705c121SKalle Valo } 1831e705c121SKalle Valo 1832e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1833e705c121SKalle Valo { 1834e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1835e705c121SKalle Valo } 1836e705c121SKalle Valo 183784fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 183884fb372cSSara Sharon { 18393681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 184084fb372cSSara Sharon return 0x00FFFFFF; 184184fb372cSSara Sharon else 184284fb372cSSara Sharon return 0x000FFFFF; 184384fb372cSSara Sharon } 184484fb372cSSara Sharon 1845e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1846e705c121SKalle Valo { 184784fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 184884fb372cSSara Sharon 1849e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 185084fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1851e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1852e705c121SKalle Valo } 1853e705c121SKalle Valo 1854e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1855e705c121SKalle Valo u32 val) 1856e705c121SKalle Valo { 185784fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 185884fb372cSSara Sharon 1859e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 186084fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1861e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1862e705c121SKalle Valo } 1863e705c121SKalle Valo 1864e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1865e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1866e705c121SKalle Valo { 1867e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1868e705c121SKalle Valo 18694f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 18704f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 18714f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 187222852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 187322852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 187422852fadSMordechay Goodstein 1875e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1876e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1877e705c121SKalle Valo else 1878e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1879e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1880e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1881e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1882e705c121SKalle Valo 18836c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18846c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18856c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 188680084e35SJohannes Berg trans_pcie->rx_buf_bytes = 188780084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1888cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1889cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1890cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1891e705c121SKalle Valo 18928e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1893e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1894e705c121SKalle Valo 189539bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 189639bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 189739bdb17eSSharon Dvir 1898e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1899e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1900e705c121SKalle Valo * As this function may be called again in some corner cases don't 1901e705c121SKalle Valo * do anything if NAPI was already initialized. 1902e705c121SKalle Valo */ 1903bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1904e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1905906d4eb8SJohannes Berg 1906906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1907e705c121SKalle Valo } 1908e705c121SKalle Valo 1909e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1910e705c121SKalle Valo { 1911e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19126eb5e529SEmmanuel Grumbach int i; 1913e705c121SKalle Valo 19142e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1915e705c121SKalle Valo 1916286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 19170cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 191813a3a390SSara Sharon else 1919e705c121SKalle Valo iwl_pcie_tx_free(trans); 1920e705c121SKalle Valo iwl_pcie_rx_free(trans); 1921e705c121SKalle Valo 192210a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 192310a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 192410a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 192510a54d81SLuca Coelho } 192610a54d81SLuca Coelho 19272e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19287c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19297c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19307c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19317c8d91ebSHaim Dreyfuss NULL); 19327c8d91ebSHaim Dreyfuss } 19332e5d4a8fSHaim Dreyfuss 19342e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19352e5d4a8fSHaim Dreyfuss } else { 1936e705c121SKalle Valo iwl_pcie_free_ict(trans); 19372e5d4a8fSHaim Dreyfuss } 1938e705c121SKalle Valo 1939e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1940e705c121SKalle Valo 194169725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 194269725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 194369725928SLuca Coelho trans_pcie->pnvm_dram.block, 194469725928SLuca Coelho trans_pcie->pnvm_dram.physical); 194569725928SLuca Coelho 1946a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1947e705c121SKalle Valo iwl_trans_free(trans); 1948e705c121SKalle Valo } 1949e705c121SKalle Valo 1950e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1951e705c121SKalle Valo { 1952e705c121SKalle Valo if (state) 1953e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1954e705c121SKalle Valo else 1955e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1956e705c121SKalle Valo } 1957e705c121SKalle Valo 195849564a80SLuca Coelho struct iwl_trans_pcie_removal { 195949564a80SLuca Coelho struct pci_dev *pdev; 196049564a80SLuca Coelho struct work_struct work; 196149564a80SLuca Coelho }; 196249564a80SLuca Coelho 196349564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 196449564a80SLuca Coelho { 196549564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 196649564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 196749564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1968aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 196949564a80SLuca Coelho 197049564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 197149564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 197249564a80SLuca Coelho pci_lock_rescan_remove(); 197349564a80SLuca Coelho pci_dev_put(pdev); 197449564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 197549564a80SLuca Coelho pci_unlock_rescan_remove(); 197649564a80SLuca Coelho 197749564a80SLuca Coelho kfree(removal); 197849564a80SLuca Coelho module_put(THIS_MODULE); 197949564a80SLuca Coelho } 198049564a80SLuca Coelho 1981c544d89bSJohannes Berg /* 1982c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 1983c544d89bSJohannes Berg * already disabled. 1984c544d89bSJohannes Berg */ 1985c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 1986e705c121SKalle Valo { 1987e705c121SKalle Valo int ret; 1988e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1989e705c121SKalle Valo 1990c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 1991e705c121SKalle Valo 1992e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1993e705c121SKalle Valo goto out; 1994e705c121SKalle Valo 1995e705c121SKalle Valo /* this bit wakes up the NIC */ 1996e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 19976dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1998286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1999e705c121SKalle Valo udelay(2); 2000e705c121SKalle Valo 2001e705c121SKalle Valo /* 2002e705c121SKalle Valo * These bits say the device is running, and should keep running for 2003e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2004e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2005fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2006fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2007e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2008e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2009e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2010e705c121SKalle Valo * to keep device from sleeping. 2011e705c121SKalle Valo * 2012e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2013e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2014fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2015fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2016fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2017e705c121SKalle Valo * 2018e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2019e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2020e705c121SKalle Valo */ 2021e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 20226dece0e9SLuca Coelho CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 20236dece0e9SLuca Coelho (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2024e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2025e705c121SKalle Valo if (unlikely(ret < 0)) { 202649564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 202749564a80SLuca Coelho 2028e705c121SKalle Valo WARN_ONCE(1, 2029e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 203049564a80SLuca Coelho cntrl); 203149564a80SLuca Coelho 203249564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 203349564a80SLuca Coelho 203449564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 203549564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 203649564a80SLuca Coelho 2037f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 203849564a80SLuca Coelho goto err; 203949564a80SLuca Coelho 204049564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 204149564a80SLuca Coelho 204249564a80SLuca Coelho /* 204349564a80SLuca Coelho * get a module reference to avoid doing this 204449564a80SLuca Coelho * while unloading anyway and to avoid 204549564a80SLuca Coelho * scheduling a work with code that's being 204649564a80SLuca Coelho * removed. 204749564a80SLuca Coelho */ 204849564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 204949564a80SLuca Coelho IWL_ERR(trans, 205049564a80SLuca Coelho "Module is being unloaded - abort\n"); 205149564a80SLuca Coelho goto err; 205249564a80SLuca Coelho } 205349564a80SLuca Coelho 205449564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 205549564a80SLuca Coelho if (!removal) { 205649564a80SLuca Coelho module_put(THIS_MODULE); 205749564a80SLuca Coelho goto err; 205849564a80SLuca Coelho } 205949564a80SLuca Coelho /* 206049564a80SLuca Coelho * we don't need to clear this flag, because 206149564a80SLuca Coelho * the trans will be freed and reallocated. 206249564a80SLuca Coelho */ 2063f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 206449564a80SLuca Coelho 206549564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 206649564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 206749564a80SLuca Coelho pci_dev_get(removal->pdev); 206849564a80SLuca Coelho schedule_work(&removal->work); 206949564a80SLuca Coelho } else { 207049564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 207149564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 207249564a80SLuca Coelho } 207349564a80SLuca Coelho 207449564a80SLuca Coelho err: 2075c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2076e705c121SKalle Valo return false; 2077e705c121SKalle Valo } 2078e705c121SKalle Valo 2079e705c121SKalle Valo out: 2080e705c121SKalle Valo /* 2081e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2082e705c121SKalle Valo * track nic_access anyway. 2083e705c121SKalle Valo */ 2084e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2085e705c121SKalle Valo return true; 2086e705c121SKalle Valo } 2087e705c121SKalle Valo 2088c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2089c544d89bSJohannes Berg { 2090c544d89bSJohannes Berg bool ret; 2091c544d89bSJohannes Berg 2092c544d89bSJohannes Berg local_bh_disable(); 2093c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2094c544d89bSJohannes Berg if (ret) { 2095c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2096c544d89bSJohannes Berg return ret; 2097c544d89bSJohannes Berg } 2098c544d89bSJohannes Berg local_bh_enable(); 2099c544d89bSJohannes Berg return false; 2100c544d89bSJohannes Berg } 2101c544d89bSJohannes Berg 21021ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2103e705c121SKalle Valo { 2104e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2105e705c121SKalle Valo 2106e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2107e705c121SKalle Valo 2108e705c121SKalle Valo /* 2109e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2110e705c121SKalle Valo * track nic_access anyway. 2111e705c121SKalle Valo */ 2112e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2113e705c121SKalle Valo 2114e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2115e705c121SKalle Valo goto out; 2116e705c121SKalle Valo 2117e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21186dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2119e705c121SKalle Valo /* 2120e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2121e705c121SKalle Valo * any previous writes, but we need the write that clears the 2122e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2123e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2124e705c121SKalle Valo */ 2125e705c121SKalle Valo out: 2126874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2127e705c121SKalle Valo } 2128e705c121SKalle Valo 2129e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2130e705c121SKalle Valo void *buf, int dwords) 2131e705c121SKalle Valo { 213204516706SJohannes Berg int offs = 0; 2133e705c121SKalle Valo u32 *vals = buf; 2134e705c121SKalle Valo 213504516706SJohannes Berg while (offs < dwords) { 213604516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 213767013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 21383d372c4eSJohannes Berg bool resched = false; 213904516706SJohannes Berg 21401ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 214104516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 214204516706SJohannes Berg addr + 4 * offs); 214304516706SJohannes Berg 214404516706SJohannes Berg while (offs < dwords) { 214504516706SJohannes Berg vals[offs] = iwl_read32(trans, 214604516706SJohannes Berg HBUS_TARG_MEM_RDAT); 214704516706SJohannes Berg offs++; 214804516706SJohannes Berg 21493d372c4eSJohannes Berg if (time_after(jiffies, end)) { 21503d372c4eSJohannes Berg resched = true; 215104516706SJohannes Berg break; 215204516706SJohannes Berg } 21533d372c4eSJohannes Berg } 21541ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 21553d372c4eSJohannes Berg 21563d372c4eSJohannes Berg if (resched) 21573d372c4eSJohannes Berg cond_resched(); 2158e705c121SKalle Valo } else { 215904516706SJohannes Berg return -EBUSY; 2160e705c121SKalle Valo } 216104516706SJohannes Berg } 216204516706SJohannes Berg 216304516706SJohannes Berg return 0; 2164e705c121SKalle Valo } 2165e705c121SKalle Valo 2166e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2167e705c121SKalle Valo const void *buf, int dwords) 2168e705c121SKalle Valo { 2169e705c121SKalle Valo int offs, ret = 0; 2170e705c121SKalle Valo const u32 *vals = buf; 2171e705c121SKalle Valo 21721ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2173e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2174e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2175e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2176e705c121SKalle Valo vals ? vals[offs] : 0); 21771ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2178e705c121SKalle Valo } else { 2179e705c121SKalle Valo ret = -EBUSY; 2180e705c121SKalle Valo } 2181e705c121SKalle Valo return ret; 2182e705c121SKalle Valo } 2183e705c121SKalle Valo 21847f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 21857f1fe1d4SLuca Coelho u32 *val) 21867f1fe1d4SLuca Coelho { 21877f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 21887f1fe1d4SLuca Coelho ofs, val); 21897f1fe1d4SLuca Coelho } 21907f1fe1d4SLuca Coelho 21910cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21920cd58eaaSEmmanuel Grumbach { 21930cd58eaaSEmmanuel Grumbach int i; 21940cd58eaaSEmmanuel Grumbach 2195286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 21964f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 21970cd58eaaSEmmanuel Grumbach 21984f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 21990cd58eaaSEmmanuel Grumbach continue; 22000cd58eaaSEmmanuel Grumbach 22010cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22020cd58eaaSEmmanuel Grumbach 22030cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22040cd58eaaSEmmanuel Grumbach txq->block--; 22050cd58eaaSEmmanuel Grumbach if (!txq->block) { 22060cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2207bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22080cd58eaaSEmmanuel Grumbach } 22090cd58eaaSEmmanuel Grumbach } else if (block) { 22100cd58eaaSEmmanuel Grumbach txq->block++; 22110cd58eaaSEmmanuel Grumbach } 22120cd58eaaSEmmanuel Grumbach 22130cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22140cd58eaaSEmmanuel Grumbach } 22150cd58eaaSEmmanuel Grumbach } 22160cd58eaaSEmmanuel Grumbach 2217e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2218e705c121SKalle Valo 221992536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 222092536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 222192536c96SSara Sharon { 222292536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 222392536c96SSara Sharon 222492536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 222592536c96SSara Sharon return -EINVAL; 222692536c96SSara Sharon 222792536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 222892536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 222992536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 223092536c96SSara Sharon data->fr_bd_wid = 0; 223192536c96SSara Sharon 223292536c96SSara Sharon return 0; 223392536c96SSara Sharon } 223492536c96SSara Sharon 2235d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2236e705c121SKalle Valo { 2237e705c121SKalle Valo struct iwl_txq *txq; 2238e705c121SKalle Valo unsigned long now = jiffies; 22392ae48edcSSara Sharon bool overflow_tx; 2240e705c121SKalle Valo u8 wr_ptr; 2241e705c121SKalle Valo 22422b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2243f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2244f60c9e59SEmmanuel Grumbach return -ENODEV; 22452b3fae66SMatt Chen 22464f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2247d6d517b7SSara Sharon return -EINVAL; 2248e705c121SKalle Valo 2249d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 22504f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 22512ae48edcSSara Sharon 22522ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22532ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22542ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22552ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22562ae48edcSSara Sharon 22576aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2258e705c121SKalle Valo 22592ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22602ae48edcSSara Sharon overflow_tx) && 2261e705c121SKalle Valo !time_after(jiffies, 2262e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22636aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2264e705c121SKalle Valo 22652ae48edcSSara Sharon /* 22662ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22672ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 22682ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 22692ae48edcSSara Sharon */ 22702ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2271e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2272e705c121SKalle Valo wr_ptr, write_ptr)) 2273e705c121SKalle Valo return -ETIMEDOUT; 22742ae48edcSSara Sharon wr_ptr = write_ptr; 22752ae48edcSSara Sharon 2276192185d6SJohannes Berg usleep_range(1000, 2000); 22772ae48edcSSara Sharon 22782ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22792ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22802ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22812ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2282e705c121SKalle Valo } 2283e705c121SKalle Valo 2284bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2285e705c121SKalle Valo IWL_ERR(trans, 2286d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 22870cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2288d6d517b7SSara Sharon return -ETIMEDOUT; 2289e705c121SKalle Valo } 2290e705c121SKalle Valo 2291d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2292d6d517b7SSara Sharon 2293d6d517b7SSara Sharon return 0; 2294d6d517b7SSara Sharon } 2295d6d517b7SSara Sharon 2296d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2297d6d517b7SSara Sharon { 2298d6d517b7SSara Sharon int cnt; 2299d6d517b7SSara Sharon int ret = 0; 2300d6d517b7SSara Sharon 2301d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 230279b6c8feSLuca Coelho for (cnt = 0; 2303286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 230479b6c8feSLuca Coelho cnt++) { 2305d6d517b7SSara Sharon 23064f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2307d6d517b7SSara Sharon continue; 23084f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2309d6d517b7SSara Sharon continue; 2310d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2311d6d517b7SSara Sharon continue; 2312d6d517b7SSara Sharon 2313d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 231438398efbSSara Sharon if (ret) 2315d6d517b7SSara Sharon break; 2316d6d517b7SSara Sharon } 2317e705c121SKalle Valo 2318e705c121SKalle Valo return ret; 2319e705c121SKalle Valo } 2320e705c121SKalle Valo 2321e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2322e705c121SKalle Valo u32 mask, u32 value) 2323e705c121SKalle Valo { 2324e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2325e705c121SKalle Valo 2326874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2327e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2328874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2329e705c121SKalle Valo } 2330e705c121SKalle Valo 2331e705c121SKalle Valo static const char *get_csr_string(int cmd) 2332e705c121SKalle Valo { 2333e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2334e705c121SKalle Valo switch (cmd) { 2335e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2336e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2337e705c121SKalle Valo IWL_CMD(CSR_INT); 2338e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2339e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2340e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2341e705c121SKalle Valo IWL_CMD(CSR_RESET); 2342e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2343e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2344e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2345e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2346e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2347e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2348e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2349e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2350e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2351e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2352e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2353e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2354e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2355e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2356e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2357e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2358e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2359e705c121SKalle Valo default: 2360e705c121SKalle Valo return "UNKNOWN"; 2361e705c121SKalle Valo } 2362e705c121SKalle Valo #undef IWL_CMD 2363e705c121SKalle Valo } 2364e705c121SKalle Valo 2365e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2366e705c121SKalle Valo { 2367e705c121SKalle Valo int i; 2368e705c121SKalle Valo static const u32 csr_tbl[] = { 2369e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2370e705c121SKalle Valo CSR_INT_COALESCING, 2371e705c121SKalle Valo CSR_INT, 2372e705c121SKalle Valo CSR_INT_MASK, 2373e705c121SKalle Valo CSR_FH_INT_STATUS, 2374e705c121SKalle Valo CSR_GPIO_IN, 2375e705c121SKalle Valo CSR_RESET, 2376e705c121SKalle Valo CSR_GP_CNTRL, 2377e705c121SKalle Valo CSR_HW_REV, 2378e705c121SKalle Valo CSR_EEPROM_REG, 2379e705c121SKalle Valo CSR_EEPROM_GP, 2380e705c121SKalle Valo CSR_OTP_GP_REG, 2381e705c121SKalle Valo CSR_GIO_REG, 2382e705c121SKalle Valo CSR_GP_UCODE_REG, 2383e705c121SKalle Valo CSR_GP_DRIVER_REG, 2384e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2385e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2386e705c121SKalle Valo CSR_LED_REG, 2387e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2388e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2389e705c121SKalle Valo CSR_ANA_PLL_CFG, 2390e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2391e705c121SKalle Valo CSR_HW_REV_WA_REG, 2392e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2393e705c121SKalle Valo }; 2394e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2395e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2396e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2397e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2398e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2399e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2400e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2401e705c121SKalle Valo } 2402e705c121SKalle Valo } 2403e705c121SKalle Valo 2404e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2405e705c121SKalle Valo /* create and remove of files */ 2406e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2407cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2408cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2409e705c121SKalle Valo } while (0) 2410e705c121SKalle Valo 2411e705c121SKalle Valo /* file operation */ 2412e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2413e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2414e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2415e705c121SKalle Valo .open = simple_open, \ 2416e705c121SKalle Valo .llseek = generic_file_llseek, \ 2417e705c121SKalle Valo }; 2418e705c121SKalle Valo 2419e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2420e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2421e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2422e705c121SKalle Valo .open = simple_open, \ 2423e705c121SKalle Valo .llseek = generic_file_llseek, \ 2424e705c121SKalle Valo }; 2425e705c121SKalle Valo 2426e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2427e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2428e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2429e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2430e705c121SKalle Valo .open = simple_open, \ 2431e705c121SKalle Valo .llseek = generic_file_llseek, \ 2432e705c121SKalle Valo }; 2433e705c121SKalle Valo 2434df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2435df67a1beSJohannes Berg struct iwl_trans *trans; 2436df67a1beSJohannes Berg }; 2437df67a1beSJohannes Berg 2438df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2439df67a1beSJohannes Berg loff_t pos; 2440df67a1beSJohannes Berg }; 2441df67a1beSJohannes Berg 2442df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2443e705c121SKalle Valo { 2444df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2445df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2446df67a1beSJohannes Berg 2447df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2448df67a1beSJohannes Berg return NULL; 2449df67a1beSJohannes Berg 2450df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2451df67a1beSJohannes Berg if (!state) 2452df67a1beSJohannes Berg return NULL; 2453df67a1beSJohannes Berg state->pos = *pos; 2454df67a1beSJohannes Berg return state; 2455df67a1beSJohannes Berg } 2456df67a1beSJohannes Berg 2457df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2458df67a1beSJohannes Berg void *v, loff_t *pos) 2459df67a1beSJohannes Berg { 2460df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2461df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2462df67a1beSJohannes Berg 2463df67a1beSJohannes Berg *pos = ++state->pos; 2464df67a1beSJohannes Berg 2465df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2466df67a1beSJohannes Berg return NULL; 2467df67a1beSJohannes Berg 2468df67a1beSJohannes Berg return state; 2469df67a1beSJohannes Berg } 2470df67a1beSJohannes Berg 2471df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2472df67a1beSJohannes Berg { 2473df67a1beSJohannes Berg kfree(v); 2474df67a1beSJohannes Berg } 2475df67a1beSJohannes Berg 2476df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2477df67a1beSJohannes Berg { 2478df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2479df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2480df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 24814f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2482e705c121SKalle Valo 2483df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2484df67a1beSJohannes Berg (unsigned int)state->pos, 24854f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 24864f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2487df67a1beSJohannes Berg if (txq) 2488df67a1beSJohannes Berg seq_printf(seq, 248995a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2490df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 249195a9e44fSJohannes Berg txq->need_update, txq->frozen, 249295a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2493df67a1beSJohannes Berg else 2494df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2495e705c121SKalle Valo 24964f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2497df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2498df67a1beSJohannes Berg seq_puts(seq, "\n"); 2499e705c121SKalle Valo 2500df67a1beSJohannes Berg return 0; 2501df67a1beSJohannes Berg } 2502df67a1beSJohannes Berg 2503df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2504df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2505df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2506df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2507df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2508df67a1beSJohannes Berg }; 2509df67a1beSJohannes Berg 2510df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2511df67a1beSJohannes Berg { 2512df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2513df67a1beSJohannes Berg 2514df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2515df67a1beSJohannes Berg sizeof(*priv)); 2516df67a1beSJohannes Berg 2517df67a1beSJohannes Berg if (!priv) 2518e705c121SKalle Valo return -ENOMEM; 2519e705c121SKalle Valo 2520df67a1beSJohannes Berg priv->trans = inode->i_private; 2521df67a1beSJohannes Berg return 0; 2522e705c121SKalle Valo } 2523e705c121SKalle Valo 2524e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2525e705c121SKalle Valo char __user *user_buf, 2526e705c121SKalle Valo size_t count, loff_t *ppos) 2527e705c121SKalle Valo { 2528e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2529e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 253078485054SSara Sharon char *buf; 253178485054SSara Sharon int pos = 0, i, ret; 2532eb3dc36eSColin Ian King size_t bufsz; 2533e705c121SKalle Valo 253478485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 253578485054SSara Sharon 253678485054SSara Sharon if (!trans_pcie->rxq) 253778485054SSara Sharon return -EAGAIN; 253878485054SSara Sharon 253978485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 254078485054SSara Sharon if (!buf) 254178485054SSara Sharon return -ENOMEM; 254278485054SSara Sharon 254378485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 254478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 254578485054SSara Sharon 254678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 254778485054SSara Sharon i); 254878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2549e705c121SKalle Valo rxq->read); 255078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2551e705c121SKalle Valo rxq->write); 255278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2553e705c121SKalle Valo rxq->write_actual); 255478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2555e705c121SKalle Valo rxq->need_update); 255678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2557e705c121SKalle Valo rxq->free_count); 2558e705c121SKalle Valo if (rxq->rb_stts) { 25590307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25600307c839SGolan Ben Ami rxq)); 256178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 256278485054SSara Sharon "\tclosed_rb_num: %u\n", 25630307c839SGolan Ben Ami r & 0x0FFF); 2564e705c121SKalle Valo } else { 2565e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 256678485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2567e705c121SKalle Valo } 256878485054SSara Sharon } 256978485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 257078485054SSara Sharon kfree(buf); 257178485054SSara Sharon 257278485054SSara Sharon return ret; 2573e705c121SKalle Valo } 2574e705c121SKalle Valo 2575e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2576e705c121SKalle Valo char __user *user_buf, 2577e705c121SKalle Valo size_t count, loff_t *ppos) 2578e705c121SKalle Valo { 2579e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2580e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2581e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2582e705c121SKalle Valo 2583e705c121SKalle Valo int pos = 0; 2584e705c121SKalle Valo char *buf; 2585e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2586e705c121SKalle Valo ssize_t ret; 2587e705c121SKalle Valo 2588e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2589e705c121SKalle Valo if (!buf) 2590e705c121SKalle Valo return -ENOMEM; 2591e705c121SKalle Valo 2592e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2593e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2594e705c121SKalle Valo 2595e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2596e705c121SKalle Valo isr_stats->hw); 2597e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2598e705c121SKalle Valo isr_stats->sw); 2599e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2600e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2601e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2602e705c121SKalle Valo isr_stats->err_code); 2603e705c121SKalle Valo } 2604e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2605e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2606e705c121SKalle Valo isr_stats->sch); 2607e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2608e705c121SKalle Valo isr_stats->alive); 2609e705c121SKalle Valo #endif 2610e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2611e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2612e705c121SKalle Valo 2613e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2614e705c121SKalle Valo isr_stats->ctkill); 2615e705c121SKalle Valo 2616e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2617e705c121SKalle Valo isr_stats->wakeup); 2618e705c121SKalle Valo 2619e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2620e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2621e705c121SKalle Valo 2622e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2623e705c121SKalle Valo isr_stats->tx); 2624e705c121SKalle Valo 2625e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2626e705c121SKalle Valo isr_stats->unhandled); 2627e705c121SKalle Valo 2628e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2629e705c121SKalle Valo kfree(buf); 2630e705c121SKalle Valo return ret; 2631e705c121SKalle Valo } 2632e705c121SKalle Valo 2633e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2634e705c121SKalle Valo const char __user *user_buf, 2635e705c121SKalle Valo size_t count, loff_t *ppos) 2636e705c121SKalle Valo { 2637e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2638e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2639e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2640e705c121SKalle Valo u32 reset_flag; 2641078f1131SJohannes Berg int ret; 2642e705c121SKalle Valo 2643078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2644078f1131SJohannes Berg if (ret) 2645078f1131SJohannes Berg return ret; 2646e705c121SKalle Valo if (reset_flag == 0) 2647e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2648e705c121SKalle Valo 2649e705c121SKalle Valo return count; 2650e705c121SKalle Valo } 2651e705c121SKalle Valo 2652e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2653e705c121SKalle Valo const char __user *user_buf, 2654e705c121SKalle Valo size_t count, loff_t *ppos) 2655e705c121SKalle Valo { 2656e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2657e705c121SKalle Valo 2658e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2659e705c121SKalle Valo 2660e705c121SKalle Valo return count; 2661e705c121SKalle Valo } 2662e705c121SKalle Valo 2663e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2664e705c121SKalle Valo char __user *user_buf, 2665e705c121SKalle Valo size_t count, loff_t *ppos) 2666e705c121SKalle Valo { 2667e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2668e705c121SKalle Valo char *buf = NULL; 2669e705c121SKalle Valo ssize_t ret; 2670e705c121SKalle Valo 2671e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2672e705c121SKalle Valo if (ret < 0) 2673e705c121SKalle Valo return ret; 2674e705c121SKalle Valo if (!buf) 2675e705c121SKalle Valo return -EINVAL; 2676e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2677e705c121SKalle Valo kfree(buf); 2678e705c121SKalle Valo return ret; 2679e705c121SKalle Valo } 2680e705c121SKalle Valo 2681fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2682fa4de7f7SJohannes Berg char __user *user_buf, 2683fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2684fa4de7f7SJohannes Berg { 2685fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2686fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2687fa4de7f7SJohannes Berg char buf[100]; 2688fa4de7f7SJohannes Berg int pos; 2689fa4de7f7SJohannes Berg 2690fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2691fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2692fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2693fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2694fa4de7f7SJohannes Berg 2695fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2696fa4de7f7SJohannes Berg } 2697fa4de7f7SJohannes Berg 2698fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2699fa4de7f7SJohannes Berg const char __user *user_buf, 2700fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2701fa4de7f7SJohannes Berg { 2702fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2703fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2704c5bf4fa1SJohannes Berg bool new_value; 2705fa4de7f7SJohannes Berg int ret; 2706fa4de7f7SJohannes Berg 2707c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2708fa4de7f7SJohannes Berg if (ret) 2709fa4de7f7SJohannes Berg return ret; 2710c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2711fa4de7f7SJohannes Berg return count; 2712fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2713c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2714c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2715fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2716fa4de7f7SJohannes Berg 2717fa4de7f7SJohannes Berg return count; 2718fa4de7f7SJohannes Berg } 2719fa4de7f7SJohannes Berg 2720f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2721f7805b33SLior Cohen struct file *file) 2722f7805b33SLior Cohen { 2723f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2724f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2725f7805b33SLior Cohen 272691c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 272791c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2728f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2729f7805b33SLior Cohen return -ENOENT; 2730f7805b33SLior Cohen } 2731f7805b33SLior Cohen 2732f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2733f7805b33SLior Cohen return -EBUSY; 2734f7805b33SLior Cohen 2735f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2736f7805b33SLior Cohen return simple_open(inode, file); 2737f7805b33SLior Cohen } 2738f7805b33SLior Cohen 2739f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2740f7805b33SLior Cohen struct file *file) 2741f7805b33SLior Cohen { 2742f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2743f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2744f7805b33SLior Cohen 2745f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2746f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2747f7805b33SLior Cohen return 0; 2748f7805b33SLior Cohen } 2749f7805b33SLior Cohen 2750f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2751f7805b33SLior Cohen void *buf, ssize_t *size, 2752f7805b33SLior Cohen ssize_t *bytes_copied) 2753f7805b33SLior Cohen { 2754f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2755f7805b33SLior Cohen 2756f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2757f7805b33SLior Cohen if (*size > buf_size_left) 2758f7805b33SLior Cohen *size = buf_size_left; 2759f7805b33SLior Cohen 2760f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2761f7805b33SLior Cohen *bytes_copied += *size; 2762f7805b33SLior Cohen 2763f7805b33SLior Cohen if (buf_size_left == *size) 2764f7805b33SLior Cohen return true; 2765f7805b33SLior Cohen return false; 2766f7805b33SLior Cohen } 2767f7805b33SLior Cohen 2768f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2769f7805b33SLior Cohen char __user *user_buf, 2770f7805b33SLior Cohen size_t count, loff_t *ppos) 2771f7805b33SLior Cohen { 2772f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2773f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 277469f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2775f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2776f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2777f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2778f7805b33SLior Cohen bool b_full; 2779f7805b33SLior Cohen 278091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2781f7805b33SLior Cohen write_ptr_addr = 278291c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 278391c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2784f7805b33SLior Cohen } else { 2785f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2786f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2787f7805b33SLior Cohen } 2788f7805b33SLior Cohen 278991c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2790f7805b33SLior Cohen return 0; 2791f7805b33SLior Cohen 2792f7805b33SLior Cohen mutex_lock(&data->mutex); 2793f7805b33SLior Cohen if (data->state == 2794f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2795f7805b33SLior Cohen mutex_unlock(&data->mutex); 2796f7805b33SLior Cohen return 0; 2797f7805b33SLior Cohen } 2798f7805b33SLior Cohen 2799f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2800f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2801f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2802f7805b33SLior Cohen 2803f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2804f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2805f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2806f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2807f7805b33SLior Cohen curr_buf, &size, 2808f7805b33SLior Cohen &bytes_copied); 2809f7805b33SLior Cohen data->prev_wr_ptr += size; 2810f7805b33SLior Cohen 2811f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2812f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 281369f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2814f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2815f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2816f7805b33SLior Cohen curr_buf, &size, 2817f7805b33SLior Cohen &bytes_copied); 2818f7805b33SLior Cohen data->prev_wr_ptr += size; 2819f7805b33SLior Cohen 2820f7805b33SLior Cohen if (!b_full) { 2821f7805b33SLior Cohen size = write_ptr; 2822f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2823f7805b33SLior Cohen cpu_addr, &size, 2824f7805b33SLior Cohen &bytes_copied); 2825f7805b33SLior Cohen data->prev_wr_ptr = size; 2826f7805b33SLior Cohen data->prev_wrap_cnt++; 2827f7805b33SLior Cohen } 2828f7805b33SLior Cohen } else { 2829f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2830f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2831f7805b33SLior Cohen IWL_WARN(trans, 2832f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2833f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2834f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2835f7805b33SLior Cohen IWL_WARN(trans, 2836f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2837f7805b33SLior Cohen 2838f7805b33SLior Cohen size = write_ptr; 2839f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2840f7805b33SLior Cohen cpu_addr, &size, 2841f7805b33SLior Cohen &bytes_copied); 2842f7805b33SLior Cohen data->prev_wr_ptr = size; 2843f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2844f7805b33SLior Cohen } 2845f7805b33SLior Cohen 2846f7805b33SLior Cohen mutex_unlock(&data->mutex); 2847f7805b33SLior Cohen 2848f7805b33SLior Cohen return bytes_copied; 2849f7805b33SLior Cohen } 2850f7805b33SLior Cohen 2851e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2852e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2853e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2854e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2855fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2856df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2857df67a1beSJohannes Berg .owner = THIS_MODULE, 2858df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2859df67a1beSJohannes Berg .read = seq_read, 2860df67a1beSJohannes Berg .llseek = seq_lseek, 2861df67a1beSJohannes Berg .release = seq_release_private, 2862df67a1beSJohannes Berg }; 2863e705c121SKalle Valo 2864f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2865f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2866f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2867f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2868f7805b33SLior Cohen }; 2869f7805b33SLior Cohen 2870f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2871cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2872e705c121SKalle Valo { 2873f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2874f8a1edb7SJohannes Berg 28752ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28762ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28772ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28782ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28792ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28802ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2881f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2882e705c121SKalle Valo } 2883f7805b33SLior Cohen 2884f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2885f7805b33SLior Cohen { 2886f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2887f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2888f7805b33SLior Cohen 2889f7805b33SLior Cohen mutex_lock(&data->mutex); 2890f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2891f7805b33SLior Cohen mutex_unlock(&data->mutex); 2892f7805b33SLior Cohen } 2893e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2894e705c121SKalle Valo 28956983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2896e705c121SKalle Valo { 2897e705c121SKalle Valo u32 cmdlen = 0; 2898e705c121SKalle Valo int i; 2899e705c121SKalle Valo 2900885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 29010179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 2902e705c121SKalle Valo 2903e705c121SKalle Valo return cmdlen; 2904e705c121SKalle Valo } 2905e705c121SKalle Valo 2906e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2907e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2908e705c121SKalle Valo int allocated_rb_nums) 2909e705c121SKalle Valo { 2910e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 291180084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 291278485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 291378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2914e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2915e705c121SKalle Valo 2916e705c121SKalle Valo spin_lock(&rxq->lock); 2917e705c121SKalle Valo 29180307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2919e705c121SKalle Valo 2920e705c121SKalle Valo for (i = rxq->read, j = 0; 2921e705c121SKalle Valo i != r && j < allocated_rb_nums; 2922e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2923e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2924e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2925e705c121SKalle Valo 2926e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2927e705c121SKalle Valo DMA_FROM_DEVICE); 2928e705c121SKalle Valo 2929e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2930e705c121SKalle Valo 2931e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2932e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2933e705c121SKalle Valo rb = (void *)(*data)->data; 2934e705c121SKalle Valo rb->index = cpu_to_le32(i); 2935e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2936e705c121SKalle Valo /* remap the page for the free benefit */ 2937cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, rxb->page, 2938cfdc20efSJohannes Berg rxb->offset, max_len, 2939e705c121SKalle Valo DMA_FROM_DEVICE); 2940e705c121SKalle Valo 2941e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2942e705c121SKalle Valo } 2943e705c121SKalle Valo 2944e705c121SKalle Valo spin_unlock(&rxq->lock); 2945e705c121SKalle Valo 2946e705c121SKalle Valo return rb_len; 2947e705c121SKalle Valo } 2948e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2949e705c121SKalle Valo 2950e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2951e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2952e705c121SKalle Valo { 2953e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2954e705c121SKalle Valo __le32 *val; 2955e705c121SKalle Valo int i; 2956e705c121SKalle Valo 2957e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2958e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2959e705c121SKalle Valo val = (void *)(*data)->data; 2960e705c121SKalle Valo 2961e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2962e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2963e705c121SKalle Valo 2964e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2965e705c121SKalle Valo 2966e705c121SKalle Valo return csr_len; 2967e705c121SKalle Valo } 2968e705c121SKalle Valo 2969e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2970e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2971e705c121SKalle Valo { 2972e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2973e705c121SKalle Valo __le32 *val; 2974e705c121SKalle Valo int i; 2975e705c121SKalle Valo 29761ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 2977e705c121SKalle Valo return 0; 2978e705c121SKalle Valo 2979e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2980e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2981e705c121SKalle Valo val = (void *)(*data)->data; 2982e705c121SKalle Valo 2983286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 2984723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2985723b45e2SLiad Kaufman i += sizeof(u32)) 2986e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2987723b45e2SLiad Kaufman else 2988ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2989ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2990723b45e2SLiad Kaufman i += sizeof(u32)) 2991723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2992723b45e2SLiad Kaufman i)); 2993e705c121SKalle Valo 29941ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2995e705c121SKalle Valo 2996e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2997e705c121SKalle Valo 2998e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2999e705c121SKalle Valo } 3000e705c121SKalle Valo 3001e705c121SKalle Valo static u32 3002e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3003e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3004e705c121SKalle Valo u32 monitor_len) 3005e705c121SKalle Valo { 3006e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3007e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3008e705c121SKalle Valo u32 i; 3009e705c121SKalle Valo 30101ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3011e705c121SKalle Valo return 0; 3012e705c121SKalle Valo 3013ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3014e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3015ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 301614ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3017ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3018e705c121SKalle Valo 30191ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3020e705c121SKalle Valo 3021e705c121SKalle Valo return monitor_len; 3022e705c121SKalle Valo } 3023e705c121SKalle Valo 30247a14c23dSSara Sharon static void 30257a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30267a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30277a14c23dSSara Sharon { 3028c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30297a14c23dSSara Sharon 3030286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3031c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3032c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3033c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3034c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 303591c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 303691c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 303791c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 303891c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30397a14c23dSSara Sharon } else { 30407a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30417a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30427a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30437a14c23dSSara Sharon } 3044c88580e1SShahar S Matityahu 3045c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30467a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30477a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30487a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30497a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3050286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3051c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3052c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3053c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3054cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3055cc598782SRotem Saado write_ptr_val >>= 2; 3056c88580e1SShahar S Matityahu } 3057c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30587a14c23dSSara Sharon } 30597a14c23dSSara Sharon 3060e705c121SKalle Valo static u32 3061e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3062e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3063e705c121SKalle Valo u32 monitor_len) 3064e705c121SKalle Valo { 306569f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3066e705c121SKalle Valo u32 len = 0; 3067e705c121SKalle Valo 306891c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 306969f0e505SShahar S Matityahu (fw_mon->size && 3070286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3071286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3072e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3073e705c121SKalle Valo 3074e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3075e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30767a14c23dSSara Sharon 30777a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3078e705c121SKalle Valo 3079e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 308069f0e505SShahar S Matityahu if (fw_mon->size) { 308169f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 308269f0e505SShahar S Matityahu monitor_len = fw_mon->size; 308391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 30847a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3085e705c121SKalle Valo /* 3086e705c121SKalle Valo * Update pointers to reflect actual values after 3087e705c121SKalle Valo * shifting 3088e705c121SKalle Valo */ 308991c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3090fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3091fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 309291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3093fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3094fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3095fd527eb5SGolan Ben Ami } else { 3096e705c121SKalle Valo base = iwl_read_prph(trans, base) << 309791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3098fd527eb5SGolan Ben Ami } 3099fd527eb5SGolan Ben Ami 3100e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3101e705c121SKalle Valo monitor_len / sizeof(u32)); 310291c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3103e705c121SKalle Valo monitor_len = 3104e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3105e705c121SKalle Valo fw_mon_data, 3106e705c121SKalle Valo monitor_len); 3107e705c121SKalle Valo } else { 3108e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3109e705c121SKalle Valo monitor_len = 0; 3110e705c121SKalle Valo } 3111e705c121SKalle Valo 3112e705c121SKalle Valo len += monitor_len; 3113e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3114e705c121SKalle Valo } 3115e705c121SKalle Valo 3116e705c121SKalle Valo return len; 3117e705c121SKalle Valo } 3118e705c121SKalle Valo 311993079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3120e705c121SKalle Valo { 312169f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3122da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3123da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 312469f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 312569f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 312691c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3127da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3128e705c121SKalle Valo 312991c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 313091c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3131fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3132fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 313391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3134fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3135fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3136fd527eb5SGolan Ben Ami 3137fd527eb5SGolan Ben Ami monitor_len = 3138fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 313991c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3140fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3141fd527eb5SGolan Ben Ami } else { 314291c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 314391c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3144e705c121SKalle Valo 3145e705c121SKalle Valo base = iwl_read_prph(trans, base) << 314691c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3147e705c121SKalle Valo end = iwl_read_prph(trans, end) << 314891c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3149e705c121SKalle Valo 3150e705c121SKalle Valo /* Make "end" point to the actual end */ 3151286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3152fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 315391c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 315491c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3155e705c121SKalle Valo monitor_len = end - base; 3156fd527eb5SGolan Ben Ami } 3157da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3158da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3159e705c121SKalle Valo monitor_len; 3160da752717SShahar S Matityahu return monitor_len; 3161e705c121SKalle Valo } 3162da752717SShahar S Matityahu return 0; 3163da752717SShahar S Matityahu } 3164da752717SShahar S Matityahu 3165da752717SShahar S Matityahu static struct iwl_trans_dump_data 3166da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 316779f033f6SSara Sharon u32 dump_mask) 3168da752717SShahar S Matityahu { 3169da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3170da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 31714f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3172da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3173da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3174fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3175da752717SShahar S Matityahu int i, ptr; 3176da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3177286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 317879f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 317979f033f6SSara Sharon 318079f033f6SSara Sharon if (!dump_mask) 318179f033f6SSara Sharon return NULL; 3182da752717SShahar S Matityahu 3183da752717SShahar S Matityahu /* transport dump header */ 3184da752717SShahar S Matityahu len = sizeof(*dump_data); 3185da752717SShahar S Matityahu 3186da752717SShahar S Matityahu /* host commands */ 3187e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3188da752717SShahar S Matityahu len += sizeof(*data) + 31898672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 31908672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3191da752717SShahar S Matityahu 3192da752717SShahar S Matityahu /* FW monitor */ 3193fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3194da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3195e705c121SKalle Valo 3196e705c121SKalle Valo /* CSR registers */ 319779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3198e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3199e705c121SKalle Valo 3200e705c121SKalle Valo /* FH registers */ 320179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3202286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3203723b45e2SLiad Kaufman len += sizeof(*data) + 3204ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3205ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3206723b45e2SLiad Kaufman else 3207723b45e2SLiad Kaufman len += sizeof(*data) + 3208520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3209520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3210520f03eaSShahar S Matityahu } 3211e705c121SKalle Valo 3212e705c121SKalle Valo if (dump_rbs) { 321378485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 321478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3215e705c121SKalle Valo /* RBs */ 32160307c839SGolan Ben Ami num_rbs = 32170307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3218e705c121SKalle Valo & 0x0FFF; 321978485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3220e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3221e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3222e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3223e705c121SKalle Valo } 3224e705c121SKalle Valo 32255538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3226286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3227505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32285538409bSLiad Kaufman len += sizeof(*data) + 32295538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3230505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32315538409bSLiad Kaufman 3232e705c121SKalle Valo dump_data = vzalloc(len); 3233e705c121SKalle Valo if (!dump_data) 3234e705c121SKalle Valo return NULL; 3235e705c121SKalle Valo 3236e705c121SKalle Valo len = 0; 3237e705c121SKalle Valo data = (void *)dump_data->data; 3238520f03eaSShahar S Matityahu 3239e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3240885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3241520f03eaSShahar S Matityahu 3242e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3243e705c121SKalle Valo txcmd = (void *)data->data; 3244e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3245bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3246bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32470cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 324808326a97SJohannes Berg u8 tfdidx; 3249e705c121SKalle Valo u32 caplen, cmdlen; 3250e705c121SKalle Valo 325108326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 325208326a97SJohannes Berg tfdidx = idx; 325308326a97SJohannes Berg else 325408326a97SJohannes Berg tfdidx = ptr; 325508326a97SJohannes Berg 3256520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 325708326a97SJohannes Berg (u8 *)cmdq->tfds + 325808326a97SJohannes Berg tfd_size * tfdidx); 3259e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3260e705c121SKalle Valo 3261e705c121SKalle Valo if (cmdlen) { 3262e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3263e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3264e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3265520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3266520f03eaSShahar S Matityahu caplen); 3267e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3268e705c121SKalle Valo } 3269e705c121SKalle Valo 32700cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3271e705c121SKalle Valo } 3272e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3273e705c121SKalle Valo 3274e705c121SKalle Valo data->len = cpu_to_le32(len); 3275e705c121SKalle Valo len += sizeof(*data); 3276e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3277520f03eaSShahar S Matityahu } 3278e705c121SKalle Valo 327979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3280e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 328179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3282e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3283e705c121SKalle Valo if (dump_rbs) 3284e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3285e705c121SKalle Valo 32865538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3287286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 328879b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3289505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 32905538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3291505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 32925538409bSLiad Kaufman 32935538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 32945538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 32955538409bSLiad Kaufman paging = (void *)data->data; 32965538409bSLiad Kaufman paging->index = cpu_to_le32(i); 32975538409bSLiad Kaufman memcpy(paging->data, 3298505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 32995538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33005538409bSLiad Kaufman 33015538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33025538409bSLiad Kaufman } 33035538409bSLiad Kaufman } 330479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3305e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3306e705c121SKalle Valo 3307e705c121SKalle Valo dump_data->len = len; 3308e705c121SKalle Valo 3309e705c121SKalle Valo return dump_data; 3310e705c121SKalle Valo } 3311e705c121SKalle Valo 33123161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 33134cbb8e50SLuciano Coelho { 33143161a34dSMordechay Goodstein if (enable) 33153161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 33163161a34dSMordechay Goodstein else 33173161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 33184cbb8e50SLuciano Coelho } 33194cbb8e50SLuciano Coelho 33203161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 33214cbb8e50SLuciano Coelho { 33223161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 33233161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 33243161a34dSMordechay Goodstein 33253161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 33263161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 33273161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 33283161a34dSMordechay Goodstein } else { 33293161a34dSMordechay Goodstein inta_addr = CSR_INT; 33303161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 33314cbb8e50SLuciano Coelho } 33323161a34dSMordechay Goodstein 33333161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 33343161a34dSMordechay Goodstein } 33354cbb8e50SLuciano Coelho 3336623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3337623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3338623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3339623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3340623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3341623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3342623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3343623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3344623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 33457f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3346623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3347623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3348870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3349623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3350623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3351623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3352623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3353623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3354d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 33553161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 33563161a34dSMordechay Goodstein .sync_nmi = iwl_trans_pcie_sync_nmi \ 3357623e7766SSara Sharon 3358e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3359623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3360e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3361e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3362e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3363e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3364e705c121SKalle Valo 336513f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3366e705c121SKalle Valo 3367e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3368a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3369e705c121SKalle Valo 3370e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3371e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3372e705c121SKalle Valo 337342db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 337442db09c1SLiad Kaufman 3375d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3376d6d517b7SSara Sharon 3377a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 33780cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3379f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3380f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3381f7805b33SLior Cohen #endif 3382623e7766SSara Sharon }; 3383e705c121SKalle Valo 3384623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3385623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3386623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3387eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3388eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 338977c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3390e705c121SKalle Valo 339113f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3392e705c121SKalle Valo 33930cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3394a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3395623e7766SSara Sharon 3396a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3397ba7136f3SAlex Malamud 33980cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 33990cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3400d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 340192536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 34026654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3403f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3404f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3405f7805b33SLior Cohen #endif 3406e705c121SKalle Valo }; 3407e705c121SKalle Valo 3408e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3409e705c121SKalle Valo const struct pci_device_id *ent, 34107e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3411e705c121SKalle Valo { 3412e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3413e705c121SKalle Valo struct iwl_trans *trans; 3414fda1bd0dSMordechay Goodstein int ret, addr_size; 3415a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3416*f00c3f9eSJohannes Berg void __iomem * const *table; 3417a89c72ffSJohannes Berg 3418fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3419a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3420e705c121SKalle Valo 34215a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 34225a41a86cSSharon Dvir if (ret) 34235a41a86cSSharon Dvir return ERR_PTR(ret); 34245a41a86cSSharon Dvir 3425a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3426fda1bd0dSMordechay Goodstein cfg_trans); 3427e705c121SKalle Valo if (!trans) 3428e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3429e705c121SKalle Valo 3430e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3431e705c121SKalle Valo 3432e705c121SKalle Valo trans_pcie->trans = trans; 3433326477e4SJohannes Berg trans_pcie->opmode_down = true; 3434e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3435e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3436cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3437e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3438e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3439906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 34408188a18eSJohannes Berg 34418188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 34428188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 34438188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 34448188a18eSJohannes Berg ret = -ENOMEM; 34458188a18eSJohannes Berg goto out_free_trans; 34468188a18eSJohannes Berg } 34478188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 34488188a18eSJohannes Berg 3449c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3450e705c121SKalle Valo 34517e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3452e705c121SKalle Valo /* 3453e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3454e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3455e705c121SKalle Valo * lot of power. 3456e705c121SKalle Valo */ 3457e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3458e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3459e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3460e705c121SKalle Valo } 3461e705c121SKalle Valo 34629416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34639416560eSGolan Ben Ami 3464e705c121SKalle Valo pci_set_master(pdev); 3465e705c121SKalle Valo 3466885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 346796a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3468e705c121SKalle Valo if (!ret) 346996a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 347096a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3471e705c121SKalle Valo if (ret) { 3472e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3473e705c121SKalle Valo if (!ret) 3474e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3475e705c121SKalle Valo DMA_BIT_MASK(32)); 3476e705c121SKalle Valo /* both attempts failed: */ 3477e705c121SKalle Valo if (ret) { 3478e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34795a41a86cSSharon Dvir goto out_no_pci; 3480e705c121SKalle Valo } 3481e705c121SKalle Valo } 3482e705c121SKalle Valo 34835a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3484e705c121SKalle Valo if (ret) { 34855a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34865a41a86cSSharon Dvir goto out_no_pci; 3487e705c121SKalle Valo } 3488e705c121SKalle Valo 3489*f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3490*f00c3f9eSJohannes Berg if (!table) { 34915a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3492*f00c3f9eSJohannes Berg ret = -ENOMEM; 3493*f00c3f9eSJohannes Berg goto out_no_pci; 3494*f00c3f9eSJohannes Berg } 3495*f00c3f9eSJohannes Berg 3496*f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3497*f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3498*f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3499e705c121SKalle Valo ret = -ENODEV; 35005a41a86cSSharon Dvir goto out_no_pci; 3501e705c121SKalle Valo } 3502e705c121SKalle Valo 3503e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3504e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3505e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3506e705c121SKalle Valo 3507e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3508e705c121SKalle Valo iwl_disable_interrupts(trans); 3509e705c121SKalle Valo 3510e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35119a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35129a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35139a098a89SRajat Jain ret = -EIO; 35149a098a89SRajat Jain goto out_no_pci; 35159a098a89SRajat Jain } 35169a098a89SRajat Jain 3517e705c121SKalle Valo /* 3518e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3519e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3520e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3521e705c121SKalle Valo * in the old format. 3522e705c121SKalle Valo */ 35234adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3524e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3525e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3526e705c121SKalle Valo 352799be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 352899be6166SLuca Coelho 35297e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3530e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3531e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3532e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3533e705c121SKalle Valo 3534e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3535e5f3f215SHaim Dreyfuss 3536c239feecSJohannes Berg 35372e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 35382388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 35392388bd7bSDan Carpenter if (ret) 35405a41a86cSSharon Dvir goto out_no_pci; 35412e5d4a8fSHaim Dreyfuss } else { 3542e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3543e705c121SKalle Valo if (ret) 35445a41a86cSSharon Dvir goto out_no_pci; 3545e705c121SKalle Valo 35465a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 35475a41a86cSSharon Dvir iwl_pcie_isr, 3548e705c121SKalle Valo iwl_pcie_irq_handler, 3549e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3550e705c121SKalle Valo if (ret) { 3551e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3552e705c121SKalle Valo goto out_free_ict; 3553e705c121SKalle Valo } 35542e5d4a8fSHaim Dreyfuss } 3555e705c121SKalle Valo 3556f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3557f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3558f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3559f7805b33SLior Cohen #endif 3560f7805b33SLior Cohen 3561a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3562a9248de4SShahar S Matityahu 3563e705c121SKalle Valo return trans; 3564e705c121SKalle Valo 3565e705c121SKalle Valo out_free_ict: 3566e705c121SKalle Valo iwl_pcie_free_ict(trans); 3567e705c121SKalle Valo out_no_pci: 35688188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 35698188a18eSJohannes Berg out_free_trans: 3570e705c121SKalle Valo iwl_trans_free(trans); 3571e705c121SKalle Valo return ERR_PTR(ret); 3572e705c121SKalle Valo } 3573