1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/pci-aspm.h> 66e705c121SKalle Valo #include <linux/interrupt.h> 67e705c121SKalle Valo #include <linux/debugfs.h> 68e705c121SKalle Valo #include <linux/sched.h> 69e705c121SKalle Valo #include <linux/bitops.h> 70e705c121SKalle Valo #include <linux/gfp.h> 71e705c121SKalle Valo #include <linux/vmalloc.h> 72b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 7349564a80SLuca Coelho #include <linux/module.h> 74f7805b33SLior Cohen #include <linux/wait.h> 75e705c121SKalle Valo 76e705c121SKalle Valo #include "iwl-drv.h" 77e705c121SKalle Valo #include "iwl-trans.h" 78e705c121SKalle Valo #include "iwl-csr.h" 79e705c121SKalle Valo #include "iwl-prph.h" 80e705c121SKalle Valo #include "iwl-scd.h" 81e705c121SKalle Valo #include "iwl-agn-hw.h" 82d962f9b1SJohannes Berg #include "fw/error-dump.h" 83520f03eaSShahar S Matityahu #include "fw/dbg.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 914290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92a6d24fadSRajat Jain { 93a6d24fadSRajat Jain #define PCI_DUMP_SIZE 64 94a6d24fadSRajat Jain #define PREFIX_LEN 32 95a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 97a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 98a6d24fadSRajat Jain char *prefix; 99a6d24fadSRajat Jain 100a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 101a6d24fadSRajat Jain return; 102a6d24fadSRajat Jain 103a6d24fadSRajat Jain /* Should be a multiple of 4 */ 104a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105a6d24fadSRajat Jain /* Alloc a max size buffer */ 106a6d24fadSRajat Jain if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108a6d24fadSRajat Jain else 109a6d24fadSRajat Jain alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 111a6d24fadSRajat Jain if (!buf) 112a6d24fadSRajat Jain return; 113a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 114a6d24fadSRajat Jain 115a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116a6d24fadSRajat Jain 117a6d24fadSRajat Jain /* Print wifi device registers */ 118a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 120a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 122a6d24fadSRajat Jain goto err_read; 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain 125a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 128a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129a6d24fadSRajat Jain 130a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131a6d24fadSRajat Jain if (pos) { 132a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 135a6d24fadSRajat Jain goto err_read; 136a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137a6d24fadSRajat Jain 32, 4, buf, i, 0); 138a6d24fadSRajat Jain } 139a6d24fadSRajat Jain 140a6d24fadSRajat Jain /* Print parent device registers next */ 141a6d24fadSRajat Jain if (!pdev->bus->self) 142a6d24fadSRajat Jain goto out; 143a6d24fadSRajat Jain 144a6d24fadSRajat Jain pdev = pdev->bus->self; 145a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146a6d24fadSRajat Jain 147a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148a6d24fadSRajat Jain pci_name(pdev)); 149a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 151a6d24fadSRajat Jain goto err_read; 152a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153a6d24fadSRajat Jain 154a6d24fadSRajat Jain /* Print root port AER registers */ 155a6d24fadSRajat Jain pos = 0; 156a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 157a6d24fadSRajat Jain if (pdev) 158a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159a6d24fadSRajat Jain if (pos) { 160a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161a6d24fadSRajat Jain pci_name(pdev)); 162a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 165a6d24fadSRajat Jain goto err_read; 166a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167a6d24fadSRajat Jain 4, buf, i, 0); 168a6d24fadSRajat Jain } 169f3402d6dSSara Sharon goto out; 170a6d24fadSRajat Jain 171a6d24fadSRajat Jain err_read: 172a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 174a6d24fadSRajat Jain out: 175a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 176a6d24fadSRajat Jain kfree(buf); 177a6d24fadSRajat Jain } 178a6d24fadSRajat Jain 179870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 180870c2a11SGolan Ben Ami { 181870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 182a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 183a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 184870c2a11SGolan Ben Ami usleep_range(5000, 6000); 185870c2a11SGolan Ben Ami } 186870c2a11SGolan Ben Ami 187e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 188e705c121SKalle Valo { 18988964b2eSSara Sharon int i; 190e705c121SKalle Valo 19188964b2eSSara Sharon for (i = 0; i < trans->num_blocks; i++) { 19288964b2eSSara Sharon dma_free_coherent(trans->dev, trans->fw_mon[i].size, 19388964b2eSSara Sharon trans->fw_mon[i].block, 19488964b2eSSara Sharon trans->fw_mon[i].physical); 19588964b2eSSara Sharon trans->fw_mon[i].block = NULL; 19688964b2eSSara Sharon trans->fw_mon[i].physical = 0; 19788964b2eSSara Sharon trans->fw_mon[i].size = 0; 19888964b2eSSara Sharon trans->num_blocks--; 19988964b2eSSara Sharon } 200e705c121SKalle Valo } 201e705c121SKalle Valo 20288964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20388964b2eSSara Sharon u8 max_power, u8 min_power) 204e705c121SKalle Valo { 205c5f97542SShahar S Matityahu void *cpu_addr = NULL; 20688964b2eSSara Sharon dma_addr_t phys = 0; 207e705c121SKalle Valo u32 size = 0; 208e705c121SKalle Valo u8 power; 209e705c121SKalle Valo 21088964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 211e705c121SKalle Valo size = BIT(power); 212c5f97542SShahar S Matityahu cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 213c5f97542SShahar S Matityahu GFP_KERNEL | __GFP_NOWARN | 214c5f97542SShahar S Matityahu __GFP_ZERO | __GFP_COMP); 215c5f97542SShahar S Matityahu if (!cpu_addr) 216e705c121SKalle Valo continue; 217e705c121SKalle Valo 218e705c121SKalle Valo IWL_INFO(trans, 219c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 220c5f97542SShahar S Matityahu size); 221e705c121SKalle Valo break; 222e705c121SKalle Valo } 223e705c121SKalle Valo 224c5f97542SShahar S Matityahu if (WARN_ON_ONCE(!cpu_addr)) 225e705c121SKalle Valo return; 226e705c121SKalle Valo 227e705c121SKalle Valo if (power != max_power) 228e705c121SKalle Valo IWL_ERR(trans, 229e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 230e705c121SKalle Valo (unsigned long)BIT(power - 10), 231e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 232e705c121SKalle Valo 23388964b2eSSara Sharon trans->fw_mon[trans->num_blocks].block = cpu_addr; 23488964b2eSSara Sharon trans->fw_mon[trans->num_blocks].physical = phys; 23588964b2eSSara Sharon trans->fw_mon[trans->num_blocks].size = size; 23688964b2eSSara Sharon trans->num_blocks++; 23788964b2eSSara Sharon } 23888964b2eSSara Sharon 23988964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24088964b2eSSara Sharon { 24188964b2eSSara Sharon if (!max_power) { 24288964b2eSSara Sharon /* default max_power is maximum */ 24388964b2eSSara Sharon max_power = 26; 24488964b2eSSara Sharon } else { 24588964b2eSSara Sharon max_power += 11; 24688964b2eSSara Sharon } 24788964b2eSSara Sharon 24888964b2eSSara Sharon if (WARN(max_power > 26, 24988964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25088964b2eSSara Sharon max_power)) 25188964b2eSSara Sharon return; 25288964b2eSSara Sharon 25388964b2eSSara Sharon /* 25488964b2eSSara Sharon * This function allocats the default fw monitor. 25588964b2eSSara Sharon * The optional additional ones will be allocated in runtime 25688964b2eSSara Sharon */ 25788964b2eSSara Sharon if (trans->num_blocks) 25888964b2eSSara Sharon return; 25988964b2eSSara Sharon 26088964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 261e705c121SKalle Valo } 262e705c121SKalle Valo 263e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 264e705c121SKalle Valo { 265e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 266e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 267e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 268e705c121SKalle Valo } 269e705c121SKalle Valo 270e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 271e705c121SKalle Valo { 272e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 273e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 275e705c121SKalle Valo } 276e705c121SKalle Valo 277e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 278e705c121SKalle Valo { 279e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 280e705c121SKalle Valo return; 281e705c121SKalle Valo 282e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 283e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 284e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 285e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 286e705c121SKalle Valo else 287e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 288e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 289e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo /* PCI registers */ 293e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 294e705c121SKalle Valo 295eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 296e705c121SKalle Valo { 297e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 298e705c121SKalle Valo u16 lctl; 299e705c121SKalle Valo u16 cap; 300e705c121SKalle Valo 301e705c121SKalle Valo /* 302e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 303e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 304e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 305e705c121SKalle Valo * costs negligible amount of power savings. 306e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 307e705c121SKalle Valo * power savings, even without L1. 308e705c121SKalle Valo */ 309e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 310e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 311e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 312e705c121SKalle Valo else 313e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 314e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 315e705c121SKalle Valo 316e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 317e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 318d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 319e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 320e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 321e705c121SKalle Valo } 322e705c121SKalle Valo 323e705c121SKalle Valo /* 324e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 325e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 326e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 327e705c121SKalle Valo */ 328e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 329e705c121SKalle Valo { 33052b6e168SEmmanuel Grumbach int ret; 33152b6e168SEmmanuel Grumbach 332e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 336e705c121SKalle Valo * bits already set by default after reset. 337e705c121SKalle Valo */ 338e705c121SKalle Valo 339e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3406e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 341e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 342e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 343e705c121SKalle Valo 344e705c121SKalle Valo /* 345e705c121SKalle Valo * Disable L0s without affecting L1; 346e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 347e705c121SKalle Valo */ 348e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 349e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 350e705c121SKalle Valo 351e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 352e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 353e705c121SKalle Valo 354e705c121SKalle Valo /* 355e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 356e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 357e705c121SKalle Valo */ 358e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 359e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 360e705c121SKalle Valo 361e705c121SKalle Valo iwl_pcie_apm_config(trans); 362e705c121SKalle Valo 363e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 36477d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 36577d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 366e705c121SKalle Valo 367c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 368c96b5eecSJohannes Berg if (ret) 36952b6e168SEmmanuel Grumbach return ret; 370e705c121SKalle Valo 371e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 372e705c121SKalle Valo /* 373e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 374e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 375e705c121SKalle Valo * not related to host_interrupt_operation_mode. 376e705c121SKalle Valo * 377e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 378e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 379e705c121SKalle Valo * that we wake up from L1 on time. 380e705c121SKalle Valo * 381e705c121SKalle Valo * This looks weird: read twice the same register, discard the 382e705c121SKalle Valo * value, set a bit, and yet again, read that same register 383e705c121SKalle Valo * just to discard the value. But that's the way the hardware 384e705c121SKalle Valo * seems to like it. 385e705c121SKalle Valo */ 386e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 387e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 388e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 389e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 390e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 391e705c121SKalle Valo } 392e705c121SKalle Valo 393e705c121SKalle Valo /* 394e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 395e705c121SKalle Valo * 396e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 397e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 398e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 399e705c121SKalle Valo */ 400e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 401e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 402e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 403e705c121SKalle Valo udelay(20); 404e705c121SKalle Valo 405e705c121SKalle Valo /* Disable L1-Active */ 406e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 407e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 408e705c121SKalle Valo 409e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 410e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 411e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 412e705c121SKalle Valo } 413e705c121SKalle Valo 414e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 415e705c121SKalle Valo 41652b6e168SEmmanuel Grumbach return 0; 417e705c121SKalle Valo } 418e705c121SKalle Valo 419e705c121SKalle Valo /* 420e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 421e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 422e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 423e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 424e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 425e705c121SKalle Valo */ 426e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 427e705c121SKalle Valo { 428e705c121SKalle Valo int ret; 429e705c121SKalle Valo u32 apmg_gp1_reg; 430e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 431e705c121SKalle Valo u32 dl_cfg_reg; 432e705c121SKalle Valo 433e705c121SKalle Valo /* Force XTAL ON */ 434e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 435e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 436e705c121SKalle Valo 437870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 438e705c121SKalle Valo 439c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 440c96b5eecSJohannes Berg if (WARN_ON(ret)) { 441e705c121SKalle Valo /* Release XTAL ON request */ 442e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 443e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 444e705c121SKalle Valo return; 445e705c121SKalle Valo } 446e705c121SKalle Valo 447e705c121SKalle Valo /* 448e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 449e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 450e705c121SKalle Valo */ 451e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 452e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 453e705c121SKalle Valo 454e705c121SKalle Valo /* 455e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 456e705c121SKalle Valo * caused by APMG idle state. 457e705c121SKalle Valo */ 458e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 459e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 460e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 461e705c121SKalle Valo apmg_xtal_cfg_reg | 462e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 463e705c121SKalle Valo 464870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 465e705c121SKalle Valo 466e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 467e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 468e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 469e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 470e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 471e705c121SKalle Valo 472e705c121SKalle Valo /* Clear delay line clock power up */ 473e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 474e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 475e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 476e705c121SKalle Valo 477e705c121SKalle Valo /* 478e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 479e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 480e705c121SKalle Valo */ 481e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 482e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 483e705c121SKalle Valo 484e705c121SKalle Valo /* 485e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 486e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 487e705c121SKalle Valo */ 488e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 489a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 490e705c121SKalle Valo 491e705c121SKalle Valo /* Activates XTAL resources monitor */ 492e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 493e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 494e705c121SKalle Valo 495e705c121SKalle Valo /* Release XTAL ON request */ 496e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 497e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 498e705c121SKalle Valo udelay(10); 499e705c121SKalle Valo 500e705c121SKalle Valo /* Release APMG XTAL */ 501e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 502e705c121SKalle Valo apmg_xtal_cfg_reg & 503e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 504e705c121SKalle Valo } 505e705c121SKalle Valo 506e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 507e705c121SKalle Valo { 508e8c8935eSJohannes Berg int ret; 509e705c121SKalle Valo 510e705c121SKalle Valo /* stop device's busmaster DMA activity */ 511a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 512a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 513e705c121SKalle Valo 514a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 515a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 516a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 517e705c121SKalle Valo if (ret < 0) 518e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 519e705c121SKalle Valo 520e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 521e705c121SKalle Valo } 522e705c121SKalle Valo 523e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 524e705c121SKalle Valo { 525e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 526e705c121SKalle Valo 527e705c121SKalle Valo if (op_mode_leave) { 528e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 529e705c121SKalle Valo iwl_pcie_apm_init(trans); 530e705c121SKalle Valo 531e705c121SKalle Valo /* inform ME that we are leaving */ 532e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 533e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 534e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5356e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 536e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 537e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 538e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 539e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 540e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 541e705c121SKalle Valo mdelay(1); 542e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 544e705c121SKalle Valo } 545e705c121SKalle Valo mdelay(5); 546e705c121SKalle Valo } 547e705c121SKalle Valo 548e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 549e705c121SKalle Valo 550e705c121SKalle Valo /* Stop device's DMA activity */ 551e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 552e705c121SKalle Valo 553e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 554e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 555e705c121SKalle Valo return; 556e705c121SKalle Valo } 557e705c121SKalle Valo 558870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 559e705c121SKalle Valo 560e705c121SKalle Valo /* 561e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 562e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 563e705c121SKalle Valo */ 564e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 565a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 566e705c121SKalle Valo } 567e705c121SKalle Valo 568e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 569e705c121SKalle Valo { 570e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 57152b6e168SEmmanuel Grumbach int ret; 572e705c121SKalle Valo 573e705c121SKalle Valo /* nic_init */ 574e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 57552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 576e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 577e705c121SKalle Valo 57852b6e168SEmmanuel Grumbach if (ret) 57952b6e168SEmmanuel Grumbach return ret; 58052b6e168SEmmanuel Grumbach 581e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 582e705c121SKalle Valo 583e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 584e705c121SKalle Valo 585e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 586e705c121SKalle Valo iwl_pcie_rx_init(trans); 587e705c121SKalle Valo 588e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 589e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 590e705c121SKalle Valo return -ENOMEM; 591e705c121SKalle Valo 592e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 593e705c121SKalle Valo /* enable shadow regs in HW */ 594e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 595e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 596e705c121SKalle Valo } 597e705c121SKalle Valo 598e705c121SKalle Valo return 0; 599e705c121SKalle Valo } 600e705c121SKalle Valo 601e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 602e705c121SKalle Valo 603e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 604e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 605e705c121SKalle Valo { 606e705c121SKalle Valo int ret; 607e705c121SKalle Valo 608e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 609e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 610e705c121SKalle Valo 611e705c121SKalle Valo /* See if we got it */ 612e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 613e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 614e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 615e705c121SKalle Valo HW_READY_TIMEOUT); 616e705c121SKalle Valo 617e705c121SKalle Valo if (ret >= 0) 618e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 619e705c121SKalle Valo 620e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 621e705c121SKalle Valo return ret; 622e705c121SKalle Valo } 623e705c121SKalle Valo 624e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 625eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 626e705c121SKalle Valo { 627e705c121SKalle Valo int ret; 628e705c121SKalle Valo int t = 0; 629e705c121SKalle Valo int iter; 630e705c121SKalle Valo 631e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 632e705c121SKalle Valo 633e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 634e705c121SKalle Valo /* If the card is ready, exit 0 */ 635e705c121SKalle Valo if (ret >= 0) 636e705c121SKalle Valo return 0; 637e705c121SKalle Valo 638e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 639e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 640192185d6SJohannes Berg usleep_range(1000, 2000); 641e705c121SKalle Valo 642e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 643e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 644e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 645e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 646e705c121SKalle Valo 647e705c121SKalle Valo do { 648e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 649e705c121SKalle Valo if (ret >= 0) 650e705c121SKalle Valo return 0; 651e705c121SKalle Valo 652e705c121SKalle Valo usleep_range(200, 1000); 653e705c121SKalle Valo t += 200; 654e705c121SKalle Valo } while (t < 150000); 655e705c121SKalle Valo msleep(25); 656e705c121SKalle Valo } 657e705c121SKalle Valo 658e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 659e705c121SKalle Valo 660e705c121SKalle Valo return ret; 661e705c121SKalle Valo } 662e705c121SKalle Valo 663e705c121SKalle Valo /* 664e705c121SKalle Valo * ucode 665e705c121SKalle Valo */ 666564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 667564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 668564cdce7SSara Sharon u32 byte_cnt) 669e705c121SKalle Valo { 670bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 671e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 672e705c121SKalle Valo 673bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 674e705c121SKalle Valo dst_addr); 675e705c121SKalle Valo 676bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 677e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 678e705c121SKalle Valo 679bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 680e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 681e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 682e705c121SKalle Valo 683bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 684bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 685bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 686e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 687e705c121SKalle Valo 688bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 689e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 690e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 691e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 692564cdce7SSara Sharon } 693e705c121SKalle Valo 694564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 695564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 696564cdce7SSara Sharon u32 byte_cnt) 697564cdce7SSara Sharon { 698564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 699564cdce7SSara Sharon unsigned long flags; 700564cdce7SSara Sharon int ret; 701564cdce7SSara Sharon 702564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 703564cdce7SSara Sharon 704564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 705564cdce7SSara Sharon return -EIO; 706564cdce7SSara Sharon 707564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 708564cdce7SSara Sharon byte_cnt); 709bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 710bac842daSEmmanuel Grumbach 711e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 712e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 713e705c121SKalle Valo if (!ret) { 714e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 715fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 716e705c121SKalle Valo return -ETIMEDOUT; 717e705c121SKalle Valo } 718e705c121SKalle Valo 719e705c121SKalle Valo return 0; 720e705c121SKalle Valo } 721e705c121SKalle Valo 722e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 723e705c121SKalle Valo const struct fw_desc *section) 724e705c121SKalle Valo { 725e705c121SKalle Valo u8 *v_addr; 726e705c121SKalle Valo dma_addr_t p_addr; 727e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 728e705c121SKalle Valo int ret = 0; 729e705c121SKalle Valo 730e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 731e705c121SKalle Valo section_num); 732e705c121SKalle Valo 733e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 734e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 735e705c121SKalle Valo if (!v_addr) { 736e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 737e705c121SKalle Valo chunk_sz = PAGE_SIZE; 738e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 739e705c121SKalle Valo &p_addr, GFP_KERNEL); 740e705c121SKalle Valo if (!v_addr) 741e705c121SKalle Valo return -ENOMEM; 742e705c121SKalle Valo } 743e705c121SKalle Valo 744e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 745e705c121SKalle Valo u32 copy_size, dst_addr; 746e705c121SKalle Valo bool extended_addr = false; 747e705c121SKalle Valo 748e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 749e705c121SKalle Valo dst_addr = section->offset + offset; 750e705c121SKalle Valo 751e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 752e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 753e705c121SKalle Valo extended_addr = true; 754e705c121SKalle Valo 755e705c121SKalle Valo if (extended_addr) 756e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 757e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 758e705c121SKalle Valo 759e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 760e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 761e705c121SKalle Valo copy_size); 762e705c121SKalle Valo 763e705c121SKalle Valo if (extended_addr) 764e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 765e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 766e705c121SKalle Valo 767e705c121SKalle Valo if (ret) { 768e705c121SKalle Valo IWL_ERR(trans, 769e705c121SKalle Valo "Could not load the [%d] uCode section\n", 770e705c121SKalle Valo section_num); 771e705c121SKalle Valo break; 772e705c121SKalle Valo } 773e705c121SKalle Valo } 774e705c121SKalle Valo 775e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 776e705c121SKalle Valo return ret; 777e705c121SKalle Valo } 778e705c121SKalle Valo 779e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 780e705c121SKalle Valo const struct fw_img *image, 781e705c121SKalle Valo int cpu, 782e705c121SKalle Valo int *first_ucode_section) 783e705c121SKalle Valo { 784e705c121SKalle Valo int shift_param; 785e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 786e705c121SKalle Valo u32 val, last_read_idx = 0; 787e705c121SKalle Valo 788e705c121SKalle Valo if (cpu == 1) { 789e705c121SKalle Valo shift_param = 0; 790e705c121SKalle Valo *first_ucode_section = 0; 791e705c121SKalle Valo } else { 792e705c121SKalle Valo shift_param = 16; 793e705c121SKalle Valo (*first_ucode_section)++; 794e705c121SKalle Valo } 795e705c121SKalle Valo 796eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 797e705c121SKalle Valo last_read_idx = i; 798e705c121SKalle Valo 799e705c121SKalle Valo /* 800e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 801e705c121SKalle Valo * CPU1 to CPU2. 802e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 803e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 804e705c121SKalle Valo */ 805e705c121SKalle Valo if (!image->sec[i].data || 806e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 807e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 808e705c121SKalle Valo IWL_DEBUG_FW(trans, 809e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 810e705c121SKalle Valo i); 811e705c121SKalle Valo break; 812e705c121SKalle Valo } 813e705c121SKalle Valo 814e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 815e705c121SKalle Valo if (ret) 816e705c121SKalle Valo return ret; 817e705c121SKalle Valo 818d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 819e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 820e705c121SKalle Valo val = val | (sec_num << shift_param); 821e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 822eda50cdeSSara Sharon 823e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 824e705c121SKalle Valo } 825e705c121SKalle Valo 826e705c121SKalle Valo *first_ucode_section = last_read_idx; 827e705c121SKalle Valo 8282aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8292aabdbdcSEmmanuel Grumbach 830d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 831e705c121SKalle Valo if (cpu == 1) 832d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 833d6a2c5c7SSara Sharon 0xFFFF); 834e705c121SKalle Valo else 835d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 836d6a2c5c7SSara Sharon 0xFFFFFFFF); 837d6a2c5c7SSara Sharon } else { 838d6a2c5c7SSara Sharon if (cpu == 1) 839d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 840d6a2c5c7SSara Sharon 0xFFFF); 841d6a2c5c7SSara Sharon else 842d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 843d6a2c5c7SSara Sharon 0xFFFFFFFF); 844d6a2c5c7SSara Sharon } 845e705c121SKalle Valo 846e705c121SKalle Valo return 0; 847e705c121SKalle Valo } 848e705c121SKalle Valo 849e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 850e705c121SKalle Valo const struct fw_img *image, 851e705c121SKalle Valo int cpu, 852e705c121SKalle Valo int *first_ucode_section) 853e705c121SKalle Valo { 854e705c121SKalle Valo int i, ret = 0; 855e705c121SKalle Valo u32 last_read_idx = 0; 856e705c121SKalle Valo 8573ce4a038SKirtika Ruchandani if (cpu == 1) 858e705c121SKalle Valo *first_ucode_section = 0; 8593ce4a038SKirtika Ruchandani else 860e705c121SKalle Valo (*first_ucode_section)++; 861e705c121SKalle Valo 862eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 863e705c121SKalle Valo last_read_idx = i; 864e705c121SKalle Valo 865e705c121SKalle Valo /* 866e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 867e705c121SKalle Valo * CPU1 to CPU2. 868e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 869e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 870e705c121SKalle Valo */ 871e705c121SKalle Valo if (!image->sec[i].data || 872e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 873e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 874e705c121SKalle Valo IWL_DEBUG_FW(trans, 875e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 876e705c121SKalle Valo i); 877e705c121SKalle Valo break; 878e705c121SKalle Valo } 879e705c121SKalle Valo 880e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 881e705c121SKalle Valo if (ret) 882e705c121SKalle Valo return ret; 883e705c121SKalle Valo } 884e705c121SKalle Valo 885e705c121SKalle Valo *first_ucode_section = last_read_idx; 886e705c121SKalle Valo 887e705c121SKalle Valo return 0; 888e705c121SKalle Valo } 889e705c121SKalle Valo 890c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 891e705c121SKalle Valo { 892fd527eb5SGolan Ben Ami const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 893e705c121SKalle Valo int i; 894e705c121SKalle Valo 8957a14c23dSSara Sharon if (trans->ini_valid) { 8967a14c23dSSara Sharon if (!trans->num_blocks) 8977a14c23dSSara Sharon return; 8987a14c23dSSara Sharon 899ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 9007a14c23dSSara Sharon trans->fw_mon[0].physical >> 9017a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 902ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 9037a14c23dSSara Sharon (trans->fw_mon[0].physical + 9047a14c23dSSara Sharon trans->fw_mon[0].size - 256) >> 9057a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 9067a14c23dSSara Sharon return; 9077a14c23dSSara Sharon } 9087a14c23dSSara Sharon 909e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 910e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 911e705c121SKalle Valo 912e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 913e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 914e705c121SKalle Valo else 915e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 916e705c121SKalle Valo 91717b809c9SSara Sharon for (i = 0; i < trans->dbg_n_dest_reg; i++) { 918e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 919e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 920e705c121SKalle Valo 921e705c121SKalle Valo switch (dest->reg_ops[i].op) { 922e705c121SKalle Valo case CSR_ASSIGN: 923e705c121SKalle Valo iwl_write32(trans, addr, val); 924e705c121SKalle Valo break; 925e705c121SKalle Valo case CSR_SETBIT: 926e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 927e705c121SKalle Valo break; 928e705c121SKalle Valo case CSR_CLEARBIT: 929e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 930e705c121SKalle Valo break; 931e705c121SKalle Valo case PRPH_ASSIGN: 932e705c121SKalle Valo iwl_write_prph(trans, addr, val); 933e705c121SKalle Valo break; 934e705c121SKalle Valo case PRPH_SETBIT: 935e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 936e705c121SKalle Valo break; 937e705c121SKalle Valo case PRPH_CLEARBIT: 938e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 939e705c121SKalle Valo break; 940e705c121SKalle Valo case PRPH_BLOCKBIT: 941e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 942e705c121SKalle Valo IWL_ERR(trans, 943e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 944e705c121SKalle Valo val, addr); 945e705c121SKalle Valo goto monitor; 946e705c121SKalle Valo } 947e705c121SKalle Valo break; 948e705c121SKalle Valo default: 949e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 950e705c121SKalle Valo dest->reg_ops[i].op); 951e705c121SKalle Valo break; 952e705c121SKalle Valo } 953e705c121SKalle Valo } 954e705c121SKalle Valo 955e705c121SKalle Valo monitor: 95688964b2eSSara Sharon if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { 957e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 95888964b2eSSara Sharon trans->fw_mon[0].physical >> dest->base_shift); 9596e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 960e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 96188964b2eSSara Sharon (trans->fw_mon[0].physical + 96288964b2eSSara Sharon trans->fw_mon[0].size - 256) >> 96362d7476dSEmmanuel Grumbach dest->end_shift); 96462d7476dSEmmanuel Grumbach else 96562d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 96688964b2eSSara Sharon (trans->fw_mon[0].physical + 96788964b2eSSara Sharon trans->fw_mon[0].size) >> 96862d7476dSEmmanuel Grumbach dest->end_shift); 969e705c121SKalle Valo } 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 973e705c121SKalle Valo const struct fw_img *image) 974e705c121SKalle Valo { 975e705c121SKalle Valo int ret = 0; 976e705c121SKalle Valo int first_ucode_section; 977e705c121SKalle Valo 978e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 979e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 980e705c121SKalle Valo 981e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 982e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 983e705c121SKalle Valo if (ret) 984e705c121SKalle Valo return ret; 985e705c121SKalle Valo 986e705c121SKalle Valo if (image->is_dual_cpus) { 987e705c121SKalle Valo /* set CPU2 header address */ 988e705c121SKalle Valo iwl_write_prph(trans, 989e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 990e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 991e705c121SKalle Valo 992e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 993e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 994e705c121SKalle Valo &first_ucode_section); 995e705c121SKalle Valo if (ret) 996e705c121SKalle Valo return ret; 997e705c121SKalle Valo } 998e705c121SKalle Valo 999e705c121SKalle Valo /* supported for 7000 only for the moment */ 1000e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1001e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1002e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1003e705c121SKalle Valo 100488964b2eSSara Sharon if (trans->fw_mon[0].size) { 1005e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 100688964b2eSSara Sharon trans->fw_mon[0].physical >> 4); 1007e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 100888964b2eSSara Sharon (trans->fw_mon[0].physical + 100988964b2eSSara Sharon trans->fw_mon[0].size) >> 4); 1010e705c121SKalle Valo } 10117a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1012e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1013e705c121SKalle Valo } 1014e705c121SKalle Valo 10152aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10162aabdbdcSEmmanuel Grumbach 1017e705c121SKalle Valo /* release CPU reset */ 1018e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1019e705c121SKalle Valo 1020e705c121SKalle Valo return 0; 1021e705c121SKalle Valo } 1022e705c121SKalle Valo 1023e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1024e705c121SKalle Valo const struct fw_img *image) 1025e705c121SKalle Valo { 1026e705c121SKalle Valo int ret = 0; 1027e705c121SKalle Valo int first_ucode_section; 1028e705c121SKalle Valo 1029e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1030e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1031e705c121SKalle Valo 10327a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1033e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1034e705c121SKalle Valo 103582ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 103682ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 103782ea7966SSara Sharon 103882ea7966SSara Sharon /* 103982ea7966SSara Sharon * Set default value. On resume reading the values that were 104082ea7966SSara Sharon * zeored can provide debug data on the resume flow. 104182ea7966SSara Sharon * This is for debugging only and has no functional impact. 104282ea7966SSara Sharon */ 104382ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 104482ea7966SSara Sharon 1045e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1046e705c121SKalle Valo /* release CPU reset */ 1047e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1048e705c121SKalle Valo 1049e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1050e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1051e705c121SKalle Valo &first_ucode_section); 1052e705c121SKalle Valo if (ret) 1053e705c121SKalle Valo return ret; 1054e705c121SKalle Valo 1055e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1056e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1057e705c121SKalle Valo &first_ucode_section); 1058e705c121SKalle Valo } 1059e705c121SKalle Valo 10609ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1061727c02dfSSara Sharon { 1062326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1063727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1064326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1065326477e4SJohannes Berg bool report; 1066727c02dfSSara Sharon 1067326477e4SJohannes Berg if (hw_rfkill) { 1068326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1069326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1070326477e4SJohannes Berg } else { 1071326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1072326477e4SJohannes Berg if (trans_pcie->opmode_down) 1073326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1074326477e4SJohannes Berg } 1075727c02dfSSara Sharon 1076326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1077326477e4SJohannes Berg 1078326477e4SJohannes Berg if (prev != report) 1079326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1080727c02dfSSara Sharon 1081727c02dfSSara Sharon return hw_rfkill; 1082727c02dfSSara Sharon } 1083727c02dfSSara Sharon 10847ca00409SHaim Dreyfuss struct iwl_causes_list { 10857ca00409SHaim Dreyfuss u32 cause_num; 10867ca00409SHaim Dreyfuss u32 mask_reg; 10877ca00409SHaim Dreyfuss u8 addr; 10887ca00409SHaim Dreyfuss }; 10897ca00409SHaim Dreyfuss 10907ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 10917ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10927ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10937ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10947ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10957ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10967ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1097ff911dcaSShaul Triebitz {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10987ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10997ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11007ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11017ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11027ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11037ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11047ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11057ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11067ca00409SHaim Dreyfuss }; 11077ca00409SHaim Dreyfuss 11089b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11099b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11109b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11119b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11129b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11139b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11149b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11159b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11169b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11179b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11189b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11199b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11209b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11219b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11229b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11239b58419eSGolan Ben Ami }; 11249b58419eSGolan Ben Ami 11257ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11267ca00409SHaim Dreyfuss { 11277ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11287ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11299b58419eSGolan Ben Ami int i, arr_size = 1130ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11319b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11327ca00409SHaim Dreyfuss 11337ca00409SHaim Dreyfuss /* 11347ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11357ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11367ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11377ca00409SHaim Dreyfuss */ 11389b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11399b58419eSGolan Ben Ami struct iwl_causes_list *causes = 1140ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11419b58419eSGolan Ben Ami causes_list : causes_list_v2; 11429b58419eSGolan Ben Ami 11439b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11449b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11459b58419eSGolan Ben Ami causes[i].cause_num); 11467ca00409SHaim Dreyfuss } 11477ca00409SHaim Dreyfuss } 11487ca00409SHaim Dreyfuss 11497ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11507ca00409SHaim Dreyfuss { 11517ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11527ca00409SHaim Dreyfuss u32 offset = 11537ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11547ca00409SHaim Dreyfuss u32 val, idx; 11557ca00409SHaim Dreyfuss 11567ca00409SHaim Dreyfuss /* 11577ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11587ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11597ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11607ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11617ca00409SHaim Dreyfuss */ 11627ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11637ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11647ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11657ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11667ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11677ca00409SHaim Dreyfuss } 11687ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11697ca00409SHaim Dreyfuss 11707ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11717ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11727ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11737ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11747ca00409SHaim Dreyfuss 11757ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11767ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11777ca00409SHaim Dreyfuss } 11787ca00409SHaim Dreyfuss 117977c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11807ca00409SHaim Dreyfuss { 11817ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11827ca00409SHaim Dreyfuss 11837ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1184d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1185d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1186ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11877ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11887ca00409SHaim Dreyfuss return; 11897ca00409SHaim Dreyfuss } 1190d7270d61SHaim Dreyfuss /* 1191d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1192d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1193d7270d61SHaim Dreyfuss * prph. 1194d7270d61SHaim Dreyfuss */ 1195d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1196ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11977ca00409SHaim Dreyfuss 11987ca00409SHaim Dreyfuss /* 11997ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12007ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12017ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12027ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12037ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12047ca00409SHaim Dreyfuss */ 12057ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12067ca00409SHaim Dreyfuss 12077ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 120883730058SHaim Dreyfuss } 12097ca00409SHaim Dreyfuss 121083730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 121183730058SHaim Dreyfuss { 121283730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 121383730058SHaim Dreyfuss 121483730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 121583730058SHaim Dreyfuss 121683730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 121783730058SHaim Dreyfuss return; 121883730058SHaim Dreyfuss 121983730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12207ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 122183730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12227ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12237ca00409SHaim Dreyfuss } 12247ca00409SHaim Dreyfuss 1225e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1226e705c121SKalle Valo { 1227e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1228e705c121SKalle Valo 1229e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1230e705c121SKalle Valo 1231e705c121SKalle Valo if (trans_pcie->is_down) 1232e705c121SKalle Valo return; 1233e705c121SKalle Valo 1234e705c121SKalle Valo trans_pcie->is_down = true; 1235e705c121SKalle Valo 12360232d2cdSSara Sharon /* Stop dbgc before stopping device */ 12375cfe79c8SSara Sharon _iwl_fw_dbg_stop_recording(trans, NULL); 12380232d2cdSSara Sharon 1239e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1240e705c121SKalle Valo iwl_disable_interrupts(trans); 1241e705c121SKalle Valo 1242e705c121SKalle Valo /* device going down, Stop using ICT table */ 1243e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1244e705c121SKalle Valo 1245e705c121SKalle Valo /* 1246e705c121SKalle Valo * If a HW restart happens during firmware loading, 1247e705c121SKalle Valo * then the firmware loading might call this function 1248e705c121SKalle Valo * and later it might be called again due to the 1249e705c121SKalle Valo * restart. So don't process again if the device is 1250e705c121SKalle Valo * already dead. 1251e705c121SKalle Valo */ 1252e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1253a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1254a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1255e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1256e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1257e705c121SKalle Valo 1258e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1259e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1260e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1261e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1262e705c121SKalle Valo udelay(5); 1263e705c121SKalle Valo } 1264e705c121SKalle Valo } 1265e705c121SKalle Valo 1266e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1267e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1268a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1269e705c121SKalle Valo 1270e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1271e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1272e705c121SKalle Valo 1273870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1274e705c121SKalle Valo 1275e705c121SKalle Valo /* 1276f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1277f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1278f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1279f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1280f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1281f4a1f04aSGolan Ben Ami */ 1282f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1283f4a1f04aSGolan Ben Ami 1284f4a1f04aSGolan Ben Ami /* 1285e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1286e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1287e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1288e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1289e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1290e705c121SKalle Valo */ 1291e705c121SKalle Valo iwl_disable_interrupts(trans); 1292e705c121SKalle Valo 1293e705c121SKalle Valo /* clear all status bits */ 1294e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1295e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1296e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1297e705c121SKalle Valo 1298e705c121SKalle Valo /* 1299e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1300e705c121SKalle Valo * interrupt 1301e705c121SKalle Valo */ 1302e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1303e705c121SKalle Valo 1304a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1305e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1306e705c121SKalle Valo } 1307e705c121SKalle Valo 1308eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13092e5d4a8fSHaim Dreyfuss { 13102e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13112e5d4a8fSHaim Dreyfuss 13122e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13132e5d4a8fSHaim Dreyfuss int i; 13142e5d4a8fSHaim Dreyfuss 1315496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13162e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13172e5d4a8fSHaim Dreyfuss } else { 13182e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13192e5d4a8fSHaim Dreyfuss } 13202e5d4a8fSHaim Dreyfuss } 13212e5d4a8fSHaim Dreyfuss 1322a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1323a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1324a6bd005fSEmmanuel Grumbach { 1325a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1326a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1327a6bd005fSEmmanuel Grumbach int ret; 1328a6bd005fSEmmanuel Grumbach 1329a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1330a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1331a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1332a6bd005fSEmmanuel Grumbach ret = -EIO; 1333a6bd005fSEmmanuel Grumbach goto out; 1334a6bd005fSEmmanuel Grumbach } 1335a6bd005fSEmmanuel Grumbach 1336a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1337a6bd005fSEmmanuel Grumbach 1338a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1339a6bd005fSEmmanuel Grumbach 1340a6bd005fSEmmanuel Grumbach /* 1341a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1342a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1343a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1344a6bd005fSEmmanuel Grumbach */ 1345a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1346a6bd005fSEmmanuel Grumbach 1347a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13482e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1349a6bd005fSEmmanuel Grumbach 1350a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1351a6bd005fSEmmanuel Grumbach 1352a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13539ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1354a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1355a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1356a6bd005fSEmmanuel Grumbach goto out; 1357a6bd005fSEmmanuel Grumbach } 1358a6bd005fSEmmanuel Grumbach 1359a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1360a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1361a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1362a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136320aa99bbSAnton Protopopov ret = -EIO; 1364a6bd005fSEmmanuel Grumbach goto out; 1365a6bd005fSEmmanuel Grumbach } 1366a6bd005fSEmmanuel Grumbach 1367a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1368a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1369a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1370a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1371a6bd005fSEmmanuel Grumbach 1372a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1373a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1374a6bd005fSEmmanuel Grumbach 1375a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1376a6bd005fSEmmanuel Grumbach if (ret) { 1377a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1378a6bd005fSEmmanuel Grumbach goto out; 1379a6bd005fSEmmanuel Grumbach } 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach /* 1382a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1383a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1384a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1385a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1386a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1387a6bd005fSEmmanuel Grumbach */ 1388a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1389a6bd005fSEmmanuel Grumbach 1390a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1391a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1392a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1393a6bd005fSEmmanuel Grumbach 1394a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 13956e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1396a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1397a6bd005fSEmmanuel Grumbach else 1398a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1399a6bd005fSEmmanuel Grumbach 1400a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14019ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1402a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1403a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1404a6bd005fSEmmanuel Grumbach 1405a6bd005fSEmmanuel Grumbach out: 1406a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1407a6bd005fSEmmanuel Grumbach return ret; 1408a6bd005fSEmmanuel Grumbach } 1409a6bd005fSEmmanuel Grumbach 1410a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1411a6bd005fSEmmanuel Grumbach { 1412a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1413a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1414a6bd005fSEmmanuel Grumbach } 1415a6bd005fSEmmanuel Grumbach 1416326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1417326477e4SJohannes Berg bool was_in_rfkill) 1418326477e4SJohannes Berg { 1419326477e4SJohannes Berg bool hw_rfkill; 1420326477e4SJohannes Berg 1421326477e4SJohannes Berg /* 1422326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1423326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1424326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1425326477e4SJohannes Berg * op_mode. 1426326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1427326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1428326477e4SJohannes Berg * notification without endless recursion. Under very rare 1429326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1430326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1431326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1432326477e4SJohannes Berg */ 1433326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1434326477e4SJohannes Berg if (hw_rfkill) { 1435326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1436326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1437326477e4SJohannes Berg } else { 1438326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1439326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1440326477e4SJohannes Berg } 1441326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1442326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1443326477e4SJohannes Berg } 1444326477e4SJohannes Berg 1445e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1446e705c121SKalle Valo { 1447e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1448326477e4SJohannes Berg bool was_in_rfkill; 1449e705c121SKalle Valo 1450e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1451326477e4SJohannes Berg trans_pcie->opmode_down = true; 1452326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1453e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1454326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1455e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1456e705c121SKalle Valo } 1457e705c121SKalle Valo 1458e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1459e705c121SKalle Valo { 1460e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1461e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1462e705c121SKalle Valo 1463e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1464e705c121SKalle Valo 1465326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1466326477e4SJohannes Berg state ? "disabled" : "enabled"); 146777c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 146877c09bc8SSara Sharon if (trans->cfg->gen2) 146977c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 147077c09bc8SSara Sharon else 1471e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1472e705c121SKalle Valo } 147377c09bc8SSara Sharon } 1474e705c121SKalle Valo 147523ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 147623ae6128SMatti Gottlieb bool reset) 1477e705c121SKalle Valo { 147823ae6128SMatti Gottlieb if (!reset) { 1479e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1480e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1481e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1482e705c121SKalle Valo } 1483e705c121SKalle Valo 1484e705c121SKalle Valo iwl_disable_interrupts(trans); 1485e705c121SKalle Valo 1486e705c121SKalle Valo /* 1487e705c121SKalle Valo * in testing mode, the host stays awake and the 1488e705c121SKalle Valo * hardware won't be reset (not even partially) 1489e705c121SKalle Valo */ 1490e705c121SKalle Valo if (test) 1491e705c121SKalle Valo return; 1492e705c121SKalle Valo 1493e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1494e705c121SKalle Valo 14952e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1496e705c121SKalle Valo 1497e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1498a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1499e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1500a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1501e705c121SKalle Valo 150223ae6128SMatti Gottlieb if (reset) { 1503e705c121SKalle Valo /* 1504e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1505e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1506e705c121SKalle Valo * to execute some invalid memory upon resume 1507e705c121SKalle Valo */ 1508e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1509e705c121SKalle Valo } 1510e705c121SKalle Valo 1511e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1512e705c121SKalle Valo } 1513e705c121SKalle Valo 1514e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1515e705c121SKalle Valo enum iwl_d3_status *status, 151623ae6128SMatti Gottlieb bool test, bool reset) 1517e705c121SKalle Valo { 1518d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1519e705c121SKalle Valo u32 val; 1520e705c121SKalle Valo int ret; 1521e705c121SKalle Valo 1522e705c121SKalle Valo if (test) { 1523e705c121SKalle Valo iwl_enable_interrupts(trans); 1524e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1525e705c121SKalle Valo return 0; 1526e705c121SKalle Valo } 1527e705c121SKalle Valo 1528a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1529a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1530e705c121SKalle Valo 1531c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 1532c96b5eecSJohannes Berg if (ret) 1533e705c121SKalle Valo return ret; 1534e705c121SKalle Valo 1535f98ad635SEmmanuel Grumbach /* 1536f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1537f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1538f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1539f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1540f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1541f98ad635SEmmanuel Grumbach */ 1542f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1543f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1544f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1545f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1546f98ad635SEmmanuel Grumbach 1547e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1548e705c121SKalle Valo 154923ae6128SMatti Gottlieb if (!reset) { 1550e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1551a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1552e705c121SKalle Valo } else { 1553e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1554e705c121SKalle Valo 1555e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1556e705c121SKalle Valo if (ret) { 1557e705c121SKalle Valo IWL_ERR(trans, 1558e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1559e705c121SKalle Valo return ret; 1560e705c121SKalle Valo } 1561e705c121SKalle Valo } 1562e705c121SKalle Valo 156382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1564ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 156582ea7966SSara Sharon 1566e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1567e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1568e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1569e705c121SKalle Valo else 1570e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1571e705c121SKalle Valo 1572e705c121SKalle Valo return 0; 1573e705c121SKalle Valo } 1574e705c121SKalle Valo 15752e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15762e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 15772e5d4a8fSHaim Dreyfuss { 15782e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1579ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15802e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15812e5d4a8fSHaim Dreyfuss 158206f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 158306f4b081SSara Sharon goto enable_msi; 158406f4b081SSara Sharon 1585ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 158606f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15872e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15882e5d4a8fSHaim Dreyfuss 158906f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15902e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 159106f4b081SSara Sharon max_irqs); 159206f4b081SSara Sharon if (num_irqs < 0) { 1593496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 159406f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 159506f4b081SSara Sharon num_irqs); 159606f4b081SSara Sharon goto enable_msi; 1597496d83caSHaim Dreyfuss } 159806f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1599496d83caSHaim Dreyfuss 16002e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 160106f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 160206f4b081SSara Sharon num_irqs); 160306f4b081SSara Sharon 1604496d83caSHaim Dreyfuss /* 160506f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 160606f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1607496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1608496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1609496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1610496d83caSHaim Dreyfuss */ 1611ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 161206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1613496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1614496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1615ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 161606f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1617496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1618496d83caSHaim Dreyfuss } else { 161906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1620496d83caSHaim Dreyfuss } 1621ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16222e5d4a8fSHaim Dreyfuss 162306f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1624496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16252e5d4a8fSHaim Dreyfuss return; 16262e5d4a8fSHaim Dreyfuss 162706f4b081SSara Sharon enable_msi: 162806f4b081SSara Sharon ret = pci_enable_msi(pdev); 162906f4b081SSara Sharon if (ret) { 163006f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16312e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16322e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16332e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16342e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16352e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16362e5d4a8fSHaim Dreyfuss } 16372e5d4a8fSHaim Dreyfuss } 16382e5d4a8fSHaim Dreyfuss } 16392e5d4a8fSHaim Dreyfuss 16407c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16417c8d91ebSHaim Dreyfuss { 16427c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16437c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16447c8d91ebSHaim Dreyfuss 16457c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16467c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16477c8d91ebSHaim Dreyfuss offset = 1 + i; 16487c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16497c8d91ebSHaim Dreyfuss /* 16507c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16517c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16527c8d91ebSHaim Dreyfuss */ 16537c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16547c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16557c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16567c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16577c8d91ebSHaim Dreyfuss if (ret) 16587c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16597c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16607c8d91ebSHaim Dreyfuss i); 16617c8d91ebSHaim Dreyfuss } 16627c8d91ebSHaim Dreyfuss } 16637c8d91ebSHaim Dreyfuss 16642e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16652e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16662e5d4a8fSHaim Dreyfuss { 1667496d83caSHaim Dreyfuss int i; 16682e5d4a8fSHaim Dreyfuss 1669496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16702e5d4a8fSHaim Dreyfuss int ret; 16715a41a86cSSharon Dvir struct msix_entry *msix_entry; 167264fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 167364fa3affSSharon Dvir 167464fa3affSSharon Dvir if (!qname) 167564fa3affSSharon Dvir return -ENOMEM; 16762e5d4a8fSHaim Dreyfuss 16775a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16785a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16795a41a86cSSharon Dvir msix_entry->vector, 16802e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1681496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16822e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16832e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16842e5d4a8fSHaim Dreyfuss IRQF_SHARED, 168564fa3affSSharon Dvir qname, 16865a41a86cSSharon Dvir msix_entry); 16872e5d4a8fSHaim Dreyfuss if (ret) { 16882e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16892e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16905a41a86cSSharon Dvir 16912e5d4a8fSHaim Dreyfuss return ret; 16922e5d4a8fSHaim Dreyfuss } 16932e5d4a8fSHaim Dreyfuss } 16947c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 16952e5d4a8fSHaim Dreyfuss 16962e5d4a8fSHaim Dreyfuss return 0; 16972e5d4a8fSHaim Dreyfuss } 16982e5d4a8fSHaim Dreyfuss 1699e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1700e705c121SKalle Valo { 1701e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17028954e1ebSShahar S Matityahu u32 hpm; 1703e705c121SKalle Valo int err; 1704e705c121SKalle Valo 1705e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1706e705c121SKalle Valo 1707e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1708e705c121SKalle Valo if (err) { 1709e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1710e705c121SKalle Valo return err; 1711e705c121SKalle Valo } 1712e705c121SKalle Valo 1713ea695b7cSShaul Triebitz hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 17148954e1ebSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 1715ea695b7cSShaul Triebitz int wfpm_val = iwl_read_umac_prph_no_grab(trans, 1716ea695b7cSShaul Triebitz PREG_PRPH_WPROT_0); 1717ea695b7cSShaul Triebitz 1718ea695b7cSShaul Triebitz if (wfpm_val & PREG_WFPM_ACCESS) { 17198954e1ebSShahar S Matityahu IWL_ERR(trans, 17208954e1ebSShahar S Matityahu "Error, can not clear persistence bit\n"); 17218954e1ebSShahar S Matityahu return -EPERM; 17228954e1ebSShahar S Matityahu } 1723ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1724ea695b7cSShaul Triebitz hpm & ~PERSISTENCE_BIT); 17258954e1ebSShahar S Matityahu } 17268954e1ebSShahar S Matityahu 1727870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1728e705c121SKalle Valo 172952b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 173052b6e168SEmmanuel Grumbach if (err) 173152b6e168SEmmanuel Grumbach return err; 1732e705c121SKalle Valo 17332e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 173483730058SHaim Dreyfuss 1735e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1736e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1737e705c121SKalle Valo 1738326477e4SJohannes Berg trans_pcie->opmode_down = false; 1739326477e4SJohannes Berg 1740e705c121SKalle Valo /* Set is_down to false here so that...*/ 1741e705c121SKalle Valo trans_pcie->is_down = false; 1742e705c121SKalle Valo 1743e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17449ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1745e705c121SKalle Valo 17464cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 17474cbb8e50SLuciano Coelho if (low_power) 17484cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 17494cbb8e50SLuciano Coelho 1750e705c121SKalle Valo return 0; 1751e705c121SKalle Valo } 1752e705c121SKalle Valo 1753e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1754e705c121SKalle Valo { 1755e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1756e705c121SKalle Valo int ret; 1757e705c121SKalle Valo 1758e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1759e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1760e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1761e705c121SKalle Valo 1762e705c121SKalle Valo return ret; 1763e705c121SKalle Valo } 1764e705c121SKalle Valo 1765e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1766e705c121SKalle Valo { 1767e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1768e705c121SKalle Valo 1769e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1770e705c121SKalle Valo 1771e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1772e705c121SKalle Valo iwl_disable_interrupts(trans); 1773e705c121SKalle Valo 1774e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1775e705c121SKalle Valo 1776e705c121SKalle Valo iwl_disable_interrupts(trans); 1777e705c121SKalle Valo 1778e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1779e705c121SKalle Valo 1780e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1781e705c121SKalle Valo 17822e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1783e705c121SKalle Valo } 1784e705c121SKalle Valo 1785e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1786e705c121SKalle Valo { 1787e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1788e705c121SKalle Valo } 1789e705c121SKalle Valo 1790e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1791e705c121SKalle Valo { 1792e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1793e705c121SKalle Valo } 1794e705c121SKalle Valo 1795e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1796e705c121SKalle Valo { 1797e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1798e705c121SKalle Valo } 1799e705c121SKalle Valo 180084fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 180184fb372cSSara Sharon { 180284fb372cSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 180384fb372cSSara Sharon return 0x00FFFFFF; 180484fb372cSSara Sharon else 180584fb372cSSara Sharon return 0x000FFFFF; 180684fb372cSSara Sharon } 180784fb372cSSara Sharon 1808e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1809e705c121SKalle Valo { 181084fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 181184fb372cSSara Sharon 1812e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 181384fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1814e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1815e705c121SKalle Valo } 1816e705c121SKalle Valo 1817e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1818e705c121SKalle Valo u32 val) 1819e705c121SKalle Valo { 182084fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 182184fb372cSSara Sharon 1822e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 182384fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1824e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1825e705c121SKalle Valo } 1826e705c121SKalle Valo 1827e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1828e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1829e705c121SKalle Valo { 1830e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831e705c121SKalle Valo 1832e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1833e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1834e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1835e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1836e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1837e705c121SKalle Valo else 1838e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1839e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1840e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1841e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1842e705c121SKalle Valo 18436c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18446c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18456c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1846e705c121SKalle Valo 1847e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1848e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 184941837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1850e705c121SKalle Valo 185121cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 185221cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 185321cb3222SJohannes Berg 185439bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 185539bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 185639bdb17eSSharon Dvir 1857e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1858e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1859e705c121SKalle Valo * As this function may be called again in some corner cases don't 1860e705c121SKalle Valo * do anything if NAPI was already initialized. 1861e705c121SKalle Valo */ 1862bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1863e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1864e705c121SKalle Valo } 1865e705c121SKalle Valo 1866e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1867e705c121SKalle Valo { 1868e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18696eb5e529SEmmanuel Grumbach int i; 1870e705c121SKalle Valo 18712e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1872e705c121SKalle Valo 187313a3a390SSara Sharon if (trans->cfg->gen2) 187413a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 187513a3a390SSara Sharon else 1876e705c121SKalle Valo iwl_pcie_tx_free(trans); 1877e705c121SKalle Valo iwl_pcie_rx_free(trans); 1878e705c121SKalle Valo 187910a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 188010a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 188110a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 188210a54d81SLuca Coelho } 188310a54d81SLuca Coelho 18842e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 18857c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 18867c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 18877c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 18887c8d91ebSHaim Dreyfuss NULL); 18897c8d91ebSHaim Dreyfuss } 18902e5d4a8fSHaim Dreyfuss 18912e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 18922e5d4a8fSHaim Dreyfuss } else { 1893e705c121SKalle Valo iwl_pcie_free_ict(trans); 18942e5d4a8fSHaim Dreyfuss } 1895e705c121SKalle Valo 1896e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1897e705c121SKalle Valo 18986eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 18996eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19006eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19016eb5e529SEmmanuel Grumbach 19026eb5e529SEmmanuel Grumbach if (p->page) 19036eb5e529SEmmanuel Grumbach __free_page(p->page); 19046eb5e529SEmmanuel Grumbach } 19056eb5e529SEmmanuel Grumbach 19066eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1907a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1908e705c121SKalle Valo iwl_trans_free(trans); 1909e705c121SKalle Valo } 1910e705c121SKalle Valo 1911e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1912e705c121SKalle Valo { 1913e705c121SKalle Valo if (state) 1914e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1915e705c121SKalle Valo else 1916e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1917e705c121SKalle Valo } 1918e705c121SKalle Valo 191949564a80SLuca Coelho struct iwl_trans_pcie_removal { 192049564a80SLuca Coelho struct pci_dev *pdev; 192149564a80SLuca Coelho struct work_struct work; 192249564a80SLuca Coelho }; 192349564a80SLuca Coelho 192449564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 192549564a80SLuca Coelho { 192649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 192749564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 192849564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1929aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 193049564a80SLuca Coelho 193149564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 193249564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 193349564a80SLuca Coelho pci_lock_rescan_remove(); 193449564a80SLuca Coelho pci_dev_put(pdev); 193549564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 193649564a80SLuca Coelho pci_unlock_rescan_remove(); 193749564a80SLuca Coelho 193849564a80SLuca Coelho kfree(removal); 193949564a80SLuca Coelho module_put(THIS_MODULE); 194049564a80SLuca Coelho } 194149564a80SLuca Coelho 194223ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1943e705c121SKalle Valo unsigned long *flags) 1944e705c121SKalle Valo { 1945e705c121SKalle Valo int ret; 1946e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1947e705c121SKalle Valo 1948e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1949e705c121SKalle Valo 1950e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1951e705c121SKalle Valo goto out; 1952e705c121SKalle Valo 1953e705c121SKalle Valo /* this bit wakes up the NIC */ 1954e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1955a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19566e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1957e705c121SKalle Valo udelay(2); 1958e705c121SKalle Valo 1959e705c121SKalle Valo /* 1960e705c121SKalle Valo * These bits say the device is running, and should keep running for 1961e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1962e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1963fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1964fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1965e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1966e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1967e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1968e705c121SKalle Valo * to keep device from sleeping. 1969e705c121SKalle Valo * 1970e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1971e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1972fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 1973fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 1974fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 1975e705c121SKalle Valo * 1976e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1977e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1978e705c121SKalle Valo */ 1979e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1980a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 1981a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 1982e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1983e705c121SKalle Valo if (unlikely(ret < 0)) { 198449564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 198549564a80SLuca Coelho 1986e705c121SKalle Valo WARN_ONCE(1, 1987e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 198849564a80SLuca Coelho cntrl); 198949564a80SLuca Coelho 199049564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 199149564a80SLuca Coelho 199249564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 199349564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 199449564a80SLuca Coelho 1995f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 199649564a80SLuca Coelho goto err; 199749564a80SLuca Coelho 199849564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 199949564a80SLuca Coelho 200049564a80SLuca Coelho /* 200149564a80SLuca Coelho * get a module reference to avoid doing this 200249564a80SLuca Coelho * while unloading anyway and to avoid 200349564a80SLuca Coelho * scheduling a work with code that's being 200449564a80SLuca Coelho * removed. 200549564a80SLuca Coelho */ 200649564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 200749564a80SLuca Coelho IWL_ERR(trans, 200849564a80SLuca Coelho "Module is being unloaded - abort\n"); 200949564a80SLuca Coelho goto err; 201049564a80SLuca Coelho } 201149564a80SLuca Coelho 201249564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 201349564a80SLuca Coelho if (!removal) { 201449564a80SLuca Coelho module_put(THIS_MODULE); 201549564a80SLuca Coelho goto err; 201649564a80SLuca Coelho } 201749564a80SLuca Coelho /* 201849564a80SLuca Coelho * we don't need to clear this flag, because 201949564a80SLuca Coelho * the trans will be freed and reallocated. 202049564a80SLuca Coelho */ 2021f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 202249564a80SLuca Coelho 202349564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 202449564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 202549564a80SLuca Coelho pci_dev_get(removal->pdev); 202649564a80SLuca Coelho schedule_work(&removal->work); 202749564a80SLuca Coelho } else { 202849564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 202949564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 203049564a80SLuca Coelho } 203149564a80SLuca Coelho 203249564a80SLuca Coelho err: 2033e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2034e705c121SKalle Valo return false; 2035e705c121SKalle Valo } 2036e705c121SKalle Valo 2037e705c121SKalle Valo out: 2038e705c121SKalle Valo /* 2039e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2040e705c121SKalle Valo * track nic_access anyway. 2041e705c121SKalle Valo */ 2042e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2043e705c121SKalle Valo return true; 2044e705c121SKalle Valo } 2045e705c121SKalle Valo 2046e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2047e705c121SKalle Valo unsigned long *flags) 2048e705c121SKalle Valo { 2049e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2050e705c121SKalle Valo 2051e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2052e705c121SKalle Valo 2053e705c121SKalle Valo /* 2054e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2055e705c121SKalle Valo * track nic_access anyway. 2056e705c121SKalle Valo */ 2057e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2058e705c121SKalle Valo 2059e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2060e705c121SKalle Valo goto out; 2061e705c121SKalle Valo 2062e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2063a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2064e705c121SKalle Valo /* 2065e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2066e705c121SKalle Valo * any previous writes, but we need the write that clears the 2067e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2068e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2069e705c121SKalle Valo */ 2070e705c121SKalle Valo mmiowb(); 2071e705c121SKalle Valo out: 2072e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2073e705c121SKalle Valo } 2074e705c121SKalle Valo 2075e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2076e705c121SKalle Valo void *buf, int dwords) 2077e705c121SKalle Valo { 2078e705c121SKalle Valo unsigned long flags; 2079e705c121SKalle Valo int offs, ret = 0; 2080e705c121SKalle Valo u32 *vals = buf; 2081e705c121SKalle Valo 208223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2083e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2084e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2085e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2086e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2087e705c121SKalle Valo } else { 2088e705c121SKalle Valo ret = -EBUSY; 2089e705c121SKalle Valo } 2090e705c121SKalle Valo return ret; 2091e705c121SKalle Valo } 2092e705c121SKalle Valo 2093e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2094e705c121SKalle Valo const void *buf, int dwords) 2095e705c121SKalle Valo { 2096e705c121SKalle Valo unsigned long flags; 2097e705c121SKalle Valo int offs, ret = 0; 2098e705c121SKalle Valo const u32 *vals = buf; 2099e705c121SKalle Valo 210023ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2101e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2102e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2103e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2104e705c121SKalle Valo vals ? vals[offs] : 0); 2105e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2106e705c121SKalle Valo } else { 2107e705c121SKalle Valo ret = -EBUSY; 2108e705c121SKalle Valo } 2109e705c121SKalle Valo return ret; 2110e705c121SKalle Valo } 2111e705c121SKalle Valo 2112e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2113e705c121SKalle Valo unsigned long txqs, 2114e705c121SKalle Valo bool freeze) 2115e705c121SKalle Valo { 2116e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2117e705c121SKalle Valo int queue; 2118e705c121SKalle Valo 2119e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2120b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2121e705c121SKalle Valo unsigned long now; 2122e705c121SKalle Valo 2123e705c121SKalle Valo spin_lock_bh(&txq->lock); 2124e705c121SKalle Valo 2125e705c121SKalle Valo now = jiffies; 2126e705c121SKalle Valo 2127e705c121SKalle Valo if (txq->frozen == freeze) 2128e705c121SKalle Valo goto next_queue; 2129e705c121SKalle Valo 2130e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2131e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2132e705c121SKalle Valo 2133e705c121SKalle Valo txq->frozen = freeze; 2134e705c121SKalle Valo 2135bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2136e705c121SKalle Valo goto next_queue; 2137e705c121SKalle Valo 2138e705c121SKalle Valo if (freeze) { 2139e705c121SKalle Valo if (unlikely(time_after(now, 2140e705c121SKalle Valo txq->stuck_timer.expires))) { 2141e705c121SKalle Valo /* 2142e705c121SKalle Valo * The timer should have fired, maybe it is 2143e705c121SKalle Valo * spinning right now on the lock. 2144e705c121SKalle Valo */ 2145e705c121SKalle Valo goto next_queue; 2146e705c121SKalle Valo } 2147e705c121SKalle Valo /* remember how long until the timer fires */ 2148e705c121SKalle Valo txq->frozen_expiry_remainder = 2149e705c121SKalle Valo txq->stuck_timer.expires - now; 2150e705c121SKalle Valo del_timer(&txq->stuck_timer); 2151e705c121SKalle Valo goto next_queue; 2152e705c121SKalle Valo } 2153e705c121SKalle Valo 2154e705c121SKalle Valo /* 2155e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2156e705c121SKalle Valo * remainder before it froze 2157e705c121SKalle Valo */ 2158e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2159e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2160e705c121SKalle Valo 2161e705c121SKalle Valo next_queue: 2162e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2163e705c121SKalle Valo } 2164e705c121SKalle Valo } 2165e705c121SKalle Valo 21660cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21670cd58eaaSEmmanuel Grumbach { 21680cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21690cd58eaaSEmmanuel Grumbach int i; 21700cd58eaaSEmmanuel Grumbach 21710cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2172b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 21730cd58eaaSEmmanuel Grumbach 21740cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 21750cd58eaaSEmmanuel Grumbach continue; 21760cd58eaaSEmmanuel Grumbach 21770cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 21780cd58eaaSEmmanuel Grumbach 21790cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 21800cd58eaaSEmmanuel Grumbach txq->block--; 21810cd58eaaSEmmanuel Grumbach if (!txq->block) { 21820cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2183bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 21840cd58eaaSEmmanuel Grumbach } 21850cd58eaaSEmmanuel Grumbach } else if (block) { 21860cd58eaaSEmmanuel Grumbach txq->block++; 21870cd58eaaSEmmanuel Grumbach } 21880cd58eaaSEmmanuel Grumbach 21890cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 21900cd58eaaSEmmanuel Grumbach } 21910cd58eaaSEmmanuel Grumbach } 21920cd58eaaSEmmanuel Grumbach 2193e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2194e705c121SKalle Valo 219538398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 219638398efbSSara Sharon { 2197afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2198afb84431SEmmanuel Grumbach u32 status; 2199afb84431SEmmanuel Grumbach bool active; 2200afb84431SEmmanuel Grumbach u8 fifo; 220138398efbSSara Sharon 2202afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2203afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2204bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2205ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2206ae79785fSSara Sharon return; 2207afb84431SEmmanuel Grumbach } 2208ae79785fSSara Sharon 2209afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2210afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2211afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 221238398efbSSara Sharon 221338398efbSSara Sharon IWL_ERR(trans, 2214afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2215afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2216afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2217afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2218afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 22197b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2220afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 22217b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2222afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 222338398efbSSara Sharon } 222438398efbSSara Sharon 222592536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 222692536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 222792536c96SSara Sharon { 222892536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 222992536c96SSara Sharon 223092536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 223192536c96SSara Sharon return -EINVAL; 223292536c96SSara Sharon 223392536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 223492536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 223592536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 223692536c96SSara Sharon data->fr_bd_wid = 0; 223792536c96SSara Sharon 223892536c96SSara Sharon return 0; 223992536c96SSara Sharon } 224092536c96SSara Sharon 2241d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2242e705c121SKalle Valo { 2243e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2244e705c121SKalle Valo struct iwl_txq *txq; 2245e705c121SKalle Valo unsigned long now = jiffies; 22462ae48edcSSara Sharon bool overflow_tx; 2247e705c121SKalle Valo u8 wr_ptr; 2248e705c121SKalle Valo 22492b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2250f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2251f60c9e59SEmmanuel Grumbach return -ENODEV; 22522b3fae66SMatt Chen 2253d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2254d6d517b7SSara Sharon return -EINVAL; 2255e705c121SKalle Valo 2256d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2257d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22582ae48edcSSara Sharon 22592ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22602ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22612ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22622ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22632ae48edcSSara Sharon 22646aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2265e705c121SKalle Valo 22662ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22672ae48edcSSara Sharon overflow_tx) && 2268e705c121SKalle Valo !time_after(jiffies, 2269e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22706aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2271e705c121SKalle Valo 22722ae48edcSSara Sharon /* 22732ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22742ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 22752ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 22762ae48edcSSara Sharon */ 22772ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2278e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2279e705c121SKalle Valo wr_ptr, write_ptr)) 2280e705c121SKalle Valo return -ETIMEDOUT; 22812ae48edcSSara Sharon wr_ptr = write_ptr; 22822ae48edcSSara Sharon 2283192185d6SJohannes Berg usleep_range(1000, 2000); 22842ae48edcSSara Sharon 22852ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22862ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22872ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22882ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2289e705c121SKalle Valo } 2290e705c121SKalle Valo 2291bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2292e705c121SKalle Valo IWL_ERR(trans, 2293d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2294d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2295d6d517b7SSara Sharon return -ETIMEDOUT; 2296e705c121SKalle Valo } 2297e705c121SKalle Valo 2298d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2299d6d517b7SSara Sharon 2300d6d517b7SSara Sharon return 0; 2301d6d517b7SSara Sharon } 2302d6d517b7SSara Sharon 2303d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2304d6d517b7SSara Sharon { 2305d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2306d6d517b7SSara Sharon int cnt; 2307d6d517b7SSara Sharon int ret = 0; 2308d6d517b7SSara Sharon 2309d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2310d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2311d6d517b7SSara Sharon 2312d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2313d6d517b7SSara Sharon continue; 2314d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2315d6d517b7SSara Sharon continue; 2316d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2317d6d517b7SSara Sharon continue; 2318d6d517b7SSara Sharon 2319d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 232038398efbSSara Sharon if (ret) 2321d6d517b7SSara Sharon break; 2322d6d517b7SSara Sharon } 2323e705c121SKalle Valo 2324e705c121SKalle Valo return ret; 2325e705c121SKalle Valo } 2326e705c121SKalle Valo 2327e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2328e705c121SKalle Valo u32 mask, u32 value) 2329e705c121SKalle Valo { 2330e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2331e705c121SKalle Valo unsigned long flags; 2332e705c121SKalle Valo 2333e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2334e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2335e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2336e705c121SKalle Valo } 2337e705c121SKalle Valo 2338c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2339e705c121SKalle Valo { 2340e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2341e705c121SKalle Valo 2342e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2343e705c121SKalle Valo return; 2344e705c121SKalle Valo 2345b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 23465d93f3a2SLuca Coelho 23475d93f3a2SLuca Coelho #ifdef CONFIG_PM 23485d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23495d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23505d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2351e705c121SKalle Valo } 2352e705c121SKalle Valo 2353c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2354e705c121SKalle Valo { 2355e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2356e705c121SKalle Valo 2357e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2358e705c121SKalle Valo return; 2359e705c121SKalle Valo 2360b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2361b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2362b3ff1270SLuca Coelho 23635d93f3a2SLuca Coelho #ifdef CONFIG_PM 23645d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23655d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23665d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2367e705c121SKalle Valo } 2368e705c121SKalle Valo 2369e705c121SKalle Valo static const char *get_csr_string(int cmd) 2370e705c121SKalle Valo { 2371e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2372e705c121SKalle Valo switch (cmd) { 2373e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2374e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2375e705c121SKalle Valo IWL_CMD(CSR_INT); 2376e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2377e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2378e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2379e705c121SKalle Valo IWL_CMD(CSR_RESET); 2380e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2381e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2382e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2383e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2384e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2385e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2386e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2387e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2388e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2389e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2390e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2391e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2392e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2393e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2394e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2395e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2396e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2397e705c121SKalle Valo default: 2398e705c121SKalle Valo return "UNKNOWN"; 2399e705c121SKalle Valo } 2400e705c121SKalle Valo #undef IWL_CMD 2401e705c121SKalle Valo } 2402e705c121SKalle Valo 2403e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2404e705c121SKalle Valo { 2405e705c121SKalle Valo int i; 2406e705c121SKalle Valo static const u32 csr_tbl[] = { 2407e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2408e705c121SKalle Valo CSR_INT_COALESCING, 2409e705c121SKalle Valo CSR_INT, 2410e705c121SKalle Valo CSR_INT_MASK, 2411e705c121SKalle Valo CSR_FH_INT_STATUS, 2412e705c121SKalle Valo CSR_GPIO_IN, 2413e705c121SKalle Valo CSR_RESET, 2414e705c121SKalle Valo CSR_GP_CNTRL, 2415e705c121SKalle Valo CSR_HW_REV, 2416e705c121SKalle Valo CSR_EEPROM_REG, 2417e705c121SKalle Valo CSR_EEPROM_GP, 2418e705c121SKalle Valo CSR_OTP_GP_REG, 2419e705c121SKalle Valo CSR_GIO_REG, 2420e705c121SKalle Valo CSR_GP_UCODE_REG, 2421e705c121SKalle Valo CSR_GP_DRIVER_REG, 2422e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2423e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2424e705c121SKalle Valo CSR_LED_REG, 2425e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2426e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2427e705c121SKalle Valo CSR_ANA_PLL_CFG, 2428e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2429e705c121SKalle Valo CSR_HW_REV_WA_REG, 2430e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2431e705c121SKalle Valo }; 2432e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2433e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2434e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2435e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2436e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2437e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2438e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2439e705c121SKalle Valo } 2440e705c121SKalle Valo } 2441e705c121SKalle Valo 2442e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2443e705c121SKalle Valo /* create and remove of files */ 2444e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2445cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2446cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2447e705c121SKalle Valo } while (0) 2448e705c121SKalle Valo 2449e705c121SKalle Valo /* file operation */ 2450e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2451e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2452e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2453e705c121SKalle Valo .open = simple_open, \ 2454e705c121SKalle Valo .llseek = generic_file_llseek, \ 2455e705c121SKalle Valo }; 2456e705c121SKalle Valo 2457e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2458e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2459e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2460e705c121SKalle Valo .open = simple_open, \ 2461e705c121SKalle Valo .llseek = generic_file_llseek, \ 2462e705c121SKalle Valo }; 2463e705c121SKalle Valo 2464e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2465e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2466e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2467e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2468e705c121SKalle Valo .open = simple_open, \ 2469e705c121SKalle Valo .llseek = generic_file_llseek, \ 2470e705c121SKalle Valo }; 2471e705c121SKalle Valo 2472e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2473e705c121SKalle Valo char __user *user_buf, 2474e705c121SKalle Valo size_t count, loff_t *ppos) 2475e705c121SKalle Valo { 2476e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2477e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2478e705c121SKalle Valo struct iwl_txq *txq; 2479e705c121SKalle Valo char *buf; 2480e705c121SKalle Valo int pos = 0; 2481e705c121SKalle Valo int cnt; 2482e705c121SKalle Valo int ret; 2483e705c121SKalle Valo size_t bufsz; 2484e705c121SKalle Valo 2485e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2486e705c121SKalle Valo 2487b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2488e705c121SKalle Valo return -EAGAIN; 2489e705c121SKalle Valo 2490e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2491e705c121SKalle Valo if (!buf) 2492e705c121SKalle Valo return -ENOMEM; 2493e705c121SKalle Valo 2494e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2495b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2496e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2497e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2498bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2499e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2500e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2501e705c121SKalle Valo txq->need_update, txq->frozen, 2502e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2503e705c121SKalle Valo } 2504e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2505e705c121SKalle Valo kfree(buf); 2506e705c121SKalle Valo return ret; 2507e705c121SKalle Valo } 2508e705c121SKalle Valo 2509e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2510e705c121SKalle Valo char __user *user_buf, 2511e705c121SKalle Valo size_t count, loff_t *ppos) 2512e705c121SKalle Valo { 2513e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2514e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251578485054SSara Sharon char *buf; 251678485054SSara Sharon int pos = 0, i, ret; 251778485054SSara Sharon size_t bufsz = sizeof(buf); 2518e705c121SKalle Valo 251978485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 252078485054SSara Sharon 252178485054SSara Sharon if (!trans_pcie->rxq) 252278485054SSara Sharon return -EAGAIN; 252378485054SSara Sharon 252478485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 252578485054SSara Sharon if (!buf) 252678485054SSara Sharon return -ENOMEM; 252778485054SSara Sharon 252878485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 252978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 253078485054SSara Sharon 253178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 253278485054SSara Sharon i); 253378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2534e705c121SKalle Valo rxq->read); 253578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2536e705c121SKalle Valo rxq->write); 253778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2538e705c121SKalle Valo rxq->write_actual); 253978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2540e705c121SKalle Valo rxq->need_update); 254178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2542e705c121SKalle Valo rxq->free_count); 2543e705c121SKalle Valo if (rxq->rb_stts) { 25440307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25450307c839SGolan Ben Ami rxq)); 254678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 254778485054SSara Sharon "\tclosed_rb_num: %u\n", 25480307c839SGolan Ben Ami r & 0x0FFF); 2549e705c121SKalle Valo } else { 2550e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 255178485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2552e705c121SKalle Valo } 255378485054SSara Sharon } 255478485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 255578485054SSara Sharon kfree(buf); 255678485054SSara Sharon 255778485054SSara Sharon return ret; 2558e705c121SKalle Valo } 2559e705c121SKalle Valo 2560e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2561e705c121SKalle Valo char __user *user_buf, 2562e705c121SKalle Valo size_t count, loff_t *ppos) 2563e705c121SKalle Valo { 2564e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2565e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2566e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2567e705c121SKalle Valo 2568e705c121SKalle Valo int pos = 0; 2569e705c121SKalle Valo char *buf; 2570e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2571e705c121SKalle Valo ssize_t ret; 2572e705c121SKalle Valo 2573e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2574e705c121SKalle Valo if (!buf) 2575e705c121SKalle Valo return -ENOMEM; 2576e705c121SKalle Valo 2577e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2578e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2579e705c121SKalle Valo 2580e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2581e705c121SKalle Valo isr_stats->hw); 2582e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2583e705c121SKalle Valo isr_stats->sw); 2584e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2585e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2586e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2587e705c121SKalle Valo isr_stats->err_code); 2588e705c121SKalle Valo } 2589e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2590e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2591e705c121SKalle Valo isr_stats->sch); 2592e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2593e705c121SKalle Valo isr_stats->alive); 2594e705c121SKalle Valo #endif 2595e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2596e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2597e705c121SKalle Valo 2598e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2599e705c121SKalle Valo isr_stats->ctkill); 2600e705c121SKalle Valo 2601e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2602e705c121SKalle Valo isr_stats->wakeup); 2603e705c121SKalle Valo 2604e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2605e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2606e705c121SKalle Valo 2607e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2608e705c121SKalle Valo isr_stats->tx); 2609e705c121SKalle Valo 2610e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2611e705c121SKalle Valo isr_stats->unhandled); 2612e705c121SKalle Valo 2613e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2614e705c121SKalle Valo kfree(buf); 2615e705c121SKalle Valo return ret; 2616e705c121SKalle Valo } 2617e705c121SKalle Valo 2618e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2619e705c121SKalle Valo const char __user *user_buf, 2620e705c121SKalle Valo size_t count, loff_t *ppos) 2621e705c121SKalle Valo { 2622e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2623e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2624e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2625e705c121SKalle Valo u32 reset_flag; 2626078f1131SJohannes Berg int ret; 2627e705c121SKalle Valo 2628078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2629078f1131SJohannes Berg if (ret) 2630078f1131SJohannes Berg return ret; 2631e705c121SKalle Valo if (reset_flag == 0) 2632e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2633e705c121SKalle Valo 2634e705c121SKalle Valo return count; 2635e705c121SKalle Valo } 2636e705c121SKalle Valo 2637e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2638e705c121SKalle Valo const char __user *user_buf, 2639e705c121SKalle Valo size_t count, loff_t *ppos) 2640e705c121SKalle Valo { 2641e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2642e705c121SKalle Valo 2643e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2644e705c121SKalle Valo 2645e705c121SKalle Valo return count; 2646e705c121SKalle Valo } 2647e705c121SKalle Valo 2648e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2649e705c121SKalle Valo char __user *user_buf, 2650e705c121SKalle Valo size_t count, loff_t *ppos) 2651e705c121SKalle Valo { 2652e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2653e705c121SKalle Valo char *buf = NULL; 2654e705c121SKalle Valo ssize_t ret; 2655e705c121SKalle Valo 2656e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2657e705c121SKalle Valo if (ret < 0) 2658e705c121SKalle Valo return ret; 2659e705c121SKalle Valo if (!buf) 2660e705c121SKalle Valo return -EINVAL; 2661e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2662e705c121SKalle Valo kfree(buf); 2663e705c121SKalle Valo return ret; 2664e705c121SKalle Valo } 2665e705c121SKalle Valo 2666fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2667fa4de7f7SJohannes Berg char __user *user_buf, 2668fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2669fa4de7f7SJohannes Berg { 2670fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2671fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2672fa4de7f7SJohannes Berg char buf[100]; 2673fa4de7f7SJohannes Berg int pos; 2674fa4de7f7SJohannes Berg 2675fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2676fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2677fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2678fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2679fa4de7f7SJohannes Berg 2680fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2681fa4de7f7SJohannes Berg } 2682fa4de7f7SJohannes Berg 2683fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2684fa4de7f7SJohannes Berg const char __user *user_buf, 2685fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2686fa4de7f7SJohannes Berg { 2687fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2688fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2689fa4de7f7SJohannes Berg bool old = trans_pcie->debug_rfkill; 2690fa4de7f7SJohannes Berg int ret; 2691fa4de7f7SJohannes Berg 2692fa4de7f7SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2693fa4de7f7SJohannes Berg if (ret) 2694fa4de7f7SJohannes Berg return ret; 2695fa4de7f7SJohannes Berg if (old == trans_pcie->debug_rfkill) 2696fa4de7f7SJohannes Berg return count; 2697fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2698fa4de7f7SJohannes Berg old, trans_pcie->debug_rfkill); 2699fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2700fa4de7f7SJohannes Berg 2701fa4de7f7SJohannes Berg return count; 2702fa4de7f7SJohannes Berg } 2703fa4de7f7SJohannes Berg 2704f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2705f7805b33SLior Cohen struct file *file) 2706f7805b33SLior Cohen { 2707f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2708f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2709f7805b33SLior Cohen 2710f7805b33SLior Cohen if (!trans->dbg_dest_tlv || 2711f7805b33SLior Cohen trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) { 2712f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2713f7805b33SLior Cohen return -ENOENT; 2714f7805b33SLior Cohen } 2715f7805b33SLior Cohen 2716f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2717f7805b33SLior Cohen return -EBUSY; 2718f7805b33SLior Cohen 2719f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2720f7805b33SLior Cohen return simple_open(inode, file); 2721f7805b33SLior Cohen } 2722f7805b33SLior Cohen 2723f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2724f7805b33SLior Cohen struct file *file) 2725f7805b33SLior Cohen { 2726f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2727f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2728f7805b33SLior Cohen 2729f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2730f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2731f7805b33SLior Cohen return 0; 2732f7805b33SLior Cohen } 2733f7805b33SLior Cohen 2734f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2735f7805b33SLior Cohen void *buf, ssize_t *size, 2736f7805b33SLior Cohen ssize_t *bytes_copied) 2737f7805b33SLior Cohen { 2738f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2739f7805b33SLior Cohen 2740f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2741f7805b33SLior Cohen if (*size > buf_size_left) 2742f7805b33SLior Cohen *size = buf_size_left; 2743f7805b33SLior Cohen 2744f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2745f7805b33SLior Cohen *bytes_copied += *size; 2746f7805b33SLior Cohen 2747f7805b33SLior Cohen if (buf_size_left == *size) 2748f7805b33SLior Cohen return true; 2749f7805b33SLior Cohen return false; 2750f7805b33SLior Cohen } 2751f7805b33SLior Cohen 2752f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2753f7805b33SLior Cohen char __user *user_buf, 2754f7805b33SLior Cohen size_t count, loff_t *ppos) 2755f7805b33SLior Cohen { 2756f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2757f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2758f7805b33SLior Cohen void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf; 2759f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2760f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2761f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2762f7805b33SLior Cohen bool b_full; 2763f7805b33SLior Cohen 2764f7805b33SLior Cohen if (trans->dbg_dest_tlv) { 2765f7805b33SLior Cohen write_ptr_addr = 2766f7805b33SLior Cohen le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2767f7805b33SLior Cohen wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2768f7805b33SLior Cohen } else { 2769f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2770f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2771f7805b33SLior Cohen } 2772f7805b33SLior Cohen 2773f7805b33SLior Cohen if (unlikely(!trans->dbg_rec_on)) 2774f7805b33SLior Cohen return 0; 2775f7805b33SLior Cohen 2776f7805b33SLior Cohen mutex_lock(&data->mutex); 2777f7805b33SLior Cohen if (data->state == 2778f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2779f7805b33SLior Cohen mutex_unlock(&data->mutex); 2780f7805b33SLior Cohen return 0; 2781f7805b33SLior Cohen } 2782f7805b33SLior Cohen 2783f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2784f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2785f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2786f7805b33SLior Cohen 2787f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2788f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2789f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2790f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2791f7805b33SLior Cohen curr_buf, &size, 2792f7805b33SLior Cohen &bytes_copied); 2793f7805b33SLior Cohen data->prev_wr_ptr += size; 2794f7805b33SLior Cohen 2795f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2796f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 2797f7805b33SLior Cohen size = trans->fw_mon[0].size - data->prev_wr_ptr; 2798f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2799f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2800f7805b33SLior Cohen curr_buf, &size, 2801f7805b33SLior Cohen &bytes_copied); 2802f7805b33SLior Cohen data->prev_wr_ptr += size; 2803f7805b33SLior Cohen 2804f7805b33SLior Cohen if (!b_full) { 2805f7805b33SLior Cohen size = write_ptr; 2806f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2807f7805b33SLior Cohen cpu_addr, &size, 2808f7805b33SLior Cohen &bytes_copied); 2809f7805b33SLior Cohen data->prev_wr_ptr = size; 2810f7805b33SLior Cohen data->prev_wrap_cnt++; 2811f7805b33SLior Cohen } 2812f7805b33SLior Cohen } else { 2813f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2814f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2815f7805b33SLior Cohen IWL_WARN(trans, 2816f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2817f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2818f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2819f7805b33SLior Cohen IWL_WARN(trans, 2820f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2821f7805b33SLior Cohen 2822f7805b33SLior Cohen size = write_ptr; 2823f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2824f7805b33SLior Cohen cpu_addr, &size, 2825f7805b33SLior Cohen &bytes_copied); 2826f7805b33SLior Cohen data->prev_wr_ptr = size; 2827f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2828f7805b33SLior Cohen } 2829f7805b33SLior Cohen 2830f7805b33SLior Cohen mutex_unlock(&data->mutex); 2831f7805b33SLior Cohen 2832f7805b33SLior Cohen return bytes_copied; 2833f7805b33SLior Cohen } 2834f7805b33SLior Cohen 2835e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2836e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2837e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2838e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2839e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2840fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2841e705c121SKalle Valo 2842f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2843f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2844f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2845f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2846f7805b33SLior Cohen }; 2847f7805b33SLior Cohen 2848f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2849cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2850e705c121SKalle Valo { 2851f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2852f8a1edb7SJohannes Berg 28532ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28542ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28552ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28562ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28572ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28582ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2859f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2860e705c121SKalle Valo } 2861f7805b33SLior Cohen 2862f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2863f7805b33SLior Cohen { 2864f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2865f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2866f7805b33SLior Cohen 2867f7805b33SLior Cohen mutex_lock(&data->mutex); 2868f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2869f7805b33SLior Cohen mutex_unlock(&data->mutex); 2870f7805b33SLior Cohen } 2871e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2872e705c121SKalle Valo 28736983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2874e705c121SKalle Valo { 28753cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2876e705c121SKalle Valo u32 cmdlen = 0; 2877e705c121SKalle Valo int i; 2878e705c121SKalle Valo 28793cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 28806983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2881e705c121SKalle Valo 2882e705c121SKalle Valo return cmdlen; 2883e705c121SKalle Valo } 2884e705c121SKalle Valo 2885e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2886e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2887e705c121SKalle Valo int allocated_rb_nums) 2888e705c121SKalle Valo { 2889e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2890e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 289178485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 289278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2893e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2894e705c121SKalle Valo 2895e705c121SKalle Valo spin_lock(&rxq->lock); 2896e705c121SKalle Valo 28970307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2898e705c121SKalle Valo 2899e705c121SKalle Valo for (i = rxq->read, j = 0; 2900e705c121SKalle Valo i != r && j < allocated_rb_nums; 2901e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2902e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2903e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2904e705c121SKalle Valo 2905e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2906e705c121SKalle Valo DMA_FROM_DEVICE); 2907e705c121SKalle Valo 2908e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2909e705c121SKalle Valo 2910e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2911e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2912e705c121SKalle Valo rb = (void *)(*data)->data; 2913e705c121SKalle Valo rb->index = cpu_to_le32(i); 2914e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2915e705c121SKalle Valo /* remap the page for the free benefit */ 2916e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2917e705c121SKalle Valo max_len, 2918e705c121SKalle Valo DMA_FROM_DEVICE); 2919e705c121SKalle Valo 2920e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2921e705c121SKalle Valo } 2922e705c121SKalle Valo 2923e705c121SKalle Valo spin_unlock(&rxq->lock); 2924e705c121SKalle Valo 2925e705c121SKalle Valo return rb_len; 2926e705c121SKalle Valo } 2927e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2928e705c121SKalle Valo 2929e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2930e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2931e705c121SKalle Valo { 2932e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2933e705c121SKalle Valo __le32 *val; 2934e705c121SKalle Valo int i; 2935e705c121SKalle Valo 2936e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2937e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2938e705c121SKalle Valo val = (void *)(*data)->data; 2939e705c121SKalle Valo 2940e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2941e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2942e705c121SKalle Valo 2943e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2944e705c121SKalle Valo 2945e705c121SKalle Valo return csr_len; 2946e705c121SKalle Valo } 2947e705c121SKalle Valo 2948e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2949e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2950e705c121SKalle Valo { 2951e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2952e705c121SKalle Valo unsigned long flags; 2953e705c121SKalle Valo __le32 *val; 2954e705c121SKalle Valo int i; 2955e705c121SKalle Valo 295623ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2957e705c121SKalle Valo return 0; 2958e705c121SKalle Valo 2959e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2960e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2961e705c121SKalle Valo val = (void *)(*data)->data; 2962e705c121SKalle Valo 2963723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2964723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2965723b45e2SLiad Kaufman i += sizeof(u32)) 2966e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2967723b45e2SLiad Kaufman else 2968ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2969ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2970723b45e2SLiad Kaufman i += sizeof(u32)) 2971723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2972723b45e2SLiad Kaufman i)); 2973e705c121SKalle Valo 2974e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2975e705c121SKalle Valo 2976e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2977e705c121SKalle Valo 2978e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2979e705c121SKalle Valo } 2980e705c121SKalle Valo 2981e705c121SKalle Valo static u32 2982e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2983e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2984e705c121SKalle Valo u32 monitor_len) 2985e705c121SKalle Valo { 2986e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2987e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2988e705c121SKalle Valo unsigned long flags; 2989e705c121SKalle Valo u32 i; 2990e705c121SKalle Valo 299123ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2992e705c121SKalle Valo return 0; 2993e705c121SKalle Valo 2994ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2995e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 2996ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 299714ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 2998ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2999e705c121SKalle Valo 3000e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3001e705c121SKalle Valo 3002e705c121SKalle Valo return monitor_len; 3003e705c121SKalle Valo } 3004e705c121SKalle Valo 30057a14c23dSSara Sharon static void 30067a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30077a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30087a14c23dSSara Sharon { 3009c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30107a14c23dSSara Sharon 3011c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3012c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3013c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3014c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3015c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3016c88580e1SShahar S Matityahu } else if (trans->ini_valid) { 3017ea695b7cSShaul Triebitz base = iwl_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2); 3018ea695b7cSShaul Triebitz write_ptr = iwl_umac_prph(trans, MON_BUFF_WRPTR_VER2); 3019ea695b7cSShaul Triebitz wrap_cnt = iwl_umac_prph(trans, MON_BUFF_CYCLE_CNT_VER2); 30207a14c23dSSara Sharon } else if (trans->dbg_dest_tlv) { 30217a14c23dSSara Sharon write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 30227a14c23dSSara Sharon wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 30237a14c23dSSara Sharon base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 30247a14c23dSSara Sharon } else { 30257a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30267a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30277a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30287a14c23dSSara Sharon } 3029c88580e1SShahar S Matityahu 3030c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30317a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30327a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30337a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30347a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3035c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3036c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3037c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3038c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3039c88580e1SShahar S Matityahu } 3040c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30417a14c23dSSara Sharon } 30427a14c23dSSara Sharon 3043e705c121SKalle Valo static u32 3044e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3045e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3046e705c121SKalle Valo u32 monitor_len) 3047e705c121SKalle Valo { 3048e705c121SKalle Valo u32 len = 0; 3049e705c121SKalle Valo 305088964b2eSSara Sharon if ((trans->num_blocks && 3051c88580e1SShahar S Matityahu (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3052c88580e1SShahar S Matityahu trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210 || 3053c88580e1SShahar S Matityahu trans->ini_valid)) || 3054c88580e1SShahar S Matityahu (trans->dbg_dest_tlv && !trans->ini_valid)) { 3055e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3056e705c121SKalle Valo 3057e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3058e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30597a14c23dSSara Sharon 30607a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3061e705c121SKalle Valo 3062e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 306388964b2eSSara Sharon if (trans->num_blocks) { 3064e705c121SKalle Valo memcpy(fw_mon_data->data, 306588964b2eSSara Sharon trans->fw_mon[0].block, 306688964b2eSSara Sharon trans->fw_mon[0].size); 3067e705c121SKalle Valo 306888964b2eSSara Sharon monitor_len = trans->fw_mon[0].size; 3069e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 30707a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3071e705c121SKalle Valo /* 3072e705c121SKalle Valo * Update pointers to reflect actual values after 3073e705c121SKalle Valo * shifting 3074e705c121SKalle Valo */ 3075fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version) { 3076fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3077fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 3078fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 3079fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3080fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3081fd527eb5SGolan Ben Ami } else { 3082e705c121SKalle Valo base = iwl_read_prph(trans, base) << 3083e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 3084fd527eb5SGolan Ben Ami } 3085fd527eb5SGolan Ben Ami 3086e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3087e705c121SKalle Valo monitor_len / sizeof(u32)); 3088e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 3089e705c121SKalle Valo monitor_len = 3090e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3091e705c121SKalle Valo fw_mon_data, 3092e705c121SKalle Valo monitor_len); 3093e705c121SKalle Valo } else { 3094e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3095e705c121SKalle Valo monitor_len = 0; 3096e705c121SKalle Valo } 3097e705c121SKalle Valo 3098e705c121SKalle Valo len += monitor_len; 3099e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3100e705c121SKalle Valo } 3101e705c121SKalle Valo 3102e705c121SKalle Valo return len; 3103e705c121SKalle Valo } 3104e705c121SKalle Valo 310593079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3106e705c121SKalle Valo { 310788964b2eSSara Sharon if (trans->num_blocks) { 3108da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3109da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 311088964b2eSSara Sharon trans->fw_mon[0].size; 311188964b2eSSara Sharon return trans->fw_mon[0].size; 3112e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 3113da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3114e705c121SKalle Valo 3115fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version == 1) { 3116fd527eb5SGolan Ben Ami cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3117fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3118fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3119fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 3120fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3121fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3122fd527eb5SGolan Ben Ami 3123fd527eb5SGolan Ben Ami monitor_len = 3124fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3125fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->end_shift; 3126fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3127fd527eb5SGolan Ben Ami } else { 3128e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3129e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 3130e705c121SKalle Valo 3131e705c121SKalle Valo base = iwl_read_prph(trans, base) << 3132e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 3133e705c121SKalle Valo end = iwl_read_prph(trans, end) << 3134e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 3135e705c121SKalle Valo 3136e705c121SKalle Valo /* Make "end" point to the actual end */ 3137fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 3138fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 3139e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 3140e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 3141e705c121SKalle Valo monitor_len = end - base; 3142fd527eb5SGolan Ben Ami } 3143da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3144da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3145e705c121SKalle Valo monitor_len; 3146da752717SShahar S Matityahu return monitor_len; 3147e705c121SKalle Valo } 3148da752717SShahar S Matityahu return 0; 3149da752717SShahar S Matityahu } 3150da752717SShahar S Matityahu 3151da752717SShahar S Matityahu static struct iwl_trans_dump_data 3152da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 315379f033f6SSara Sharon u32 dump_mask) 3154da752717SShahar S Matityahu { 3155da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3156da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3157da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3158da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3159da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3160fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3161da752717SShahar S Matityahu int i, ptr; 3162da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3163da752717SShahar S Matityahu !trans->cfg->mq_rx_supported && 316479f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 316579f033f6SSara Sharon 316679f033f6SSara Sharon if (!dump_mask) 316779f033f6SSara Sharon return NULL; 3168da752717SShahar S Matityahu 3169da752717SShahar S Matityahu /* transport dump header */ 3170da752717SShahar S Matityahu len = sizeof(*dump_data); 3171da752717SShahar S Matityahu 3172da752717SShahar S Matityahu /* host commands */ 31738672aad3SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) 3174da752717SShahar S Matityahu len += sizeof(*data) + 31758672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 31768672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3177da752717SShahar S Matityahu 3178da752717SShahar S Matityahu /* FW monitor */ 3179fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3180da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3181e705c121SKalle Valo 3182e705c121SKalle Valo /* CSR registers */ 318379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3184e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3185e705c121SKalle Valo 3186e705c121SKalle Valo /* FH registers */ 318779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3188723b45e2SLiad Kaufman if (trans->cfg->gen2) 3189723b45e2SLiad Kaufman len += sizeof(*data) + 3190ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3191ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3192723b45e2SLiad Kaufman else 3193723b45e2SLiad Kaufman len += sizeof(*data) + 3194520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3195520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3196520f03eaSShahar S Matityahu } 3197e705c121SKalle Valo 3198e705c121SKalle Valo if (dump_rbs) { 319978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 320078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3201e705c121SKalle Valo /* RBs */ 32020307c839SGolan Ben Ami num_rbs = 32030307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3204e705c121SKalle Valo & 0x0FFF; 320578485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3206e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3207e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3208e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3209e705c121SKalle Valo } 3210e705c121SKalle Valo 32115538409bSLiad Kaufman /* Paged memory for gen2 HW */ 321279f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3213505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32145538409bSLiad Kaufman len += sizeof(*data) + 32155538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3216505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32175538409bSLiad Kaufman 3218e705c121SKalle Valo dump_data = vzalloc(len); 3219e705c121SKalle Valo if (!dump_data) 3220e705c121SKalle Valo return NULL; 3221e705c121SKalle Valo 3222e705c121SKalle Valo len = 0; 3223e705c121SKalle Valo data = (void *)dump_data->data; 3224520f03eaSShahar S Matityahu 322579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { 3226520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3227520f03eaSShahar S Matityahu 3228e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3229e705c121SKalle Valo txcmd = (void *)data->data; 3230e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3231bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3232bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32334ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3234e705c121SKalle Valo u32 caplen, cmdlen; 3235e705c121SKalle Valo 3236520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3237520f03eaSShahar S Matityahu cmdq->tfds + 3238520f03eaSShahar S Matityahu tfd_size * ptr); 3239e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3240e705c121SKalle Valo 3241e705c121SKalle Valo if (cmdlen) { 3242e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3243e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3244e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3245520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3246520f03eaSShahar S Matityahu caplen); 3247e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3248e705c121SKalle Valo } 3249e705c121SKalle Valo 32507b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3251e705c121SKalle Valo } 3252e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3253e705c121SKalle Valo 3254e705c121SKalle Valo data->len = cpu_to_le32(len); 3255e705c121SKalle Valo len += sizeof(*data); 3256e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3257520f03eaSShahar S Matityahu } 3258e705c121SKalle Valo 325979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3260e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 326179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3262e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3263e705c121SKalle Valo if (dump_rbs) 3264e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3265e705c121SKalle Valo 32665538409bSLiad Kaufman /* Paged memory for gen2 HW */ 326779f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3268505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 32695538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3270505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 32715538409bSLiad Kaufman 32725538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 32735538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 32745538409bSLiad Kaufman paging = (void *)data->data; 32755538409bSLiad Kaufman paging->index = cpu_to_le32(i); 32765538409bSLiad Kaufman memcpy(paging->data, 3277505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 32785538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 32795538409bSLiad Kaufman 32805538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 32815538409bSLiad Kaufman } 32825538409bSLiad Kaufman } 328379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3284e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3285e705c121SKalle Valo 3286e705c121SKalle Valo dump_data->len = len; 3287e705c121SKalle Valo 3288e705c121SKalle Valo return dump_data; 3289e705c121SKalle Valo } 3290e705c121SKalle Valo 32914cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 32924cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 32934cbb8e50SLuciano Coelho { 3294e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3295e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 32964cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 32974cbb8e50SLuciano Coelho 32984cbb8e50SLuciano Coelho return 0; 32994cbb8e50SLuciano Coelho } 33004cbb8e50SLuciano Coelho 33014cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 33024cbb8e50SLuciano Coelho { 3303e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3304e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 33054cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 33064cbb8e50SLuciano Coelho } 33074cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 33084cbb8e50SLuciano Coelho 3309623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3310623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3311623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3312623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3313623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3314623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3315623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3316623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3317623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3318623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3319623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3320870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3321623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3322623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3323623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3324623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3325623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3326623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3327623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3328623e7766SSara Sharon .d3_resume = iwl_trans_pcie_d3_resume 3329623e7766SSara Sharon 3330623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3331623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3332623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3333623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3334623e7766SSara Sharon #else 3335623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3336623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3337623e7766SSara Sharon 3338e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3339623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3340623e7766SSara Sharon IWL_TRANS_PM_OPS 3341e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3342e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3343e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3344e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3345e705c121SKalle Valo 3346e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3347e705c121SKalle Valo 3348e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3349e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3350e705c121SKalle Valo 3351e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3352e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3353e705c121SKalle Valo 335442db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 335542db09c1SLiad Kaufman 3356d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3357d6d517b7SSara Sharon 3358e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 33590cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3360f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3361f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3362f7805b33SLior Cohen #endif 3363623e7766SSara Sharon }; 3364e705c121SKalle Valo 3365623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3366623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3367623e7766SSara Sharon IWL_TRANS_PM_OPS 3368623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3369eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3370eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 337177c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3372e705c121SKalle Valo 3373ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3374e705c121SKalle Valo 3375ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3376623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3377623e7766SSara Sharon 33786b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 33796b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3380d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 338192536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3382f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3383f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3384f7805b33SLior Cohen #endif 3385e705c121SKalle Valo }; 3386e705c121SKalle Valo 3387e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3388e705c121SKalle Valo const struct pci_device_id *ent, 3389e705c121SKalle Valo const struct iwl_cfg *cfg) 3390e705c121SKalle Valo { 3391e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3392e705c121SKalle Valo struct iwl_trans *trans; 339396a6497bSSara Sharon int ret, addr_size; 3394e705c121SKalle Valo 33955a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 33965a41a86cSSharon Dvir if (ret) 33975a41a86cSSharon Dvir return ERR_PTR(ret); 33985a41a86cSSharon Dvir 3399623e7766SSara Sharon if (cfg->gen2) 3400623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3401623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3402623e7766SSara Sharon else 3403e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 34041ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3405e705c121SKalle Valo if (!trans) 3406e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3407e705c121SKalle Valo 3408e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3409e705c121SKalle Valo 3410e705c121SKalle Valo trans_pcie->trans = trans; 3411326477e4SJohannes Berg trans_pcie->opmode_down = true; 3412e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3413e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3414e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3415e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 34166eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 34176eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 34186eb5e529SEmmanuel Grumbach ret = -ENOMEM; 34196eb5e529SEmmanuel Grumbach goto out_no_pci; 34206eb5e529SEmmanuel Grumbach } 3421e705c121SKalle Valo 3422e705c121SKalle Valo 3423e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3424e705c121SKalle Valo /* 3425e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3426e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3427e705c121SKalle Valo * lot of power. 3428e705c121SKalle Valo */ 3429e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3430e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3431e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3432e705c121SKalle Valo } 3433e705c121SKalle Valo 34349416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34359416560eSGolan Ben Ami 34366983ba69SSara Sharon if (cfg->use_tfh) { 34372c6262b7SSara Sharon addr_size = 64; 34383cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 34398352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 34406983ba69SSara Sharon } else { 34412c6262b7SSara Sharon addr_size = 36; 34423cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 34436983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 34446983ba69SSara Sharon } 34453cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 34463cd1980bSSara Sharon 3447e705c121SKalle Valo pci_set_master(pdev); 3448e705c121SKalle Valo 344996a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3450e705c121SKalle Valo if (!ret) 345196a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 345296a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3453e705c121SKalle Valo if (ret) { 3454e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3455e705c121SKalle Valo if (!ret) 3456e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3457e705c121SKalle Valo DMA_BIT_MASK(32)); 3458e705c121SKalle Valo /* both attempts failed: */ 3459e705c121SKalle Valo if (ret) { 3460e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34615a41a86cSSharon Dvir goto out_no_pci; 3462e705c121SKalle Valo } 3463e705c121SKalle Valo } 3464e705c121SKalle Valo 34655a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3466e705c121SKalle Valo if (ret) { 34675a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34685a41a86cSSharon Dvir goto out_no_pci; 3469e705c121SKalle Valo } 3470e705c121SKalle Valo 34715a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3472e705c121SKalle Valo if (!trans_pcie->hw_base) { 34735a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3474e705c121SKalle Valo ret = -ENODEV; 34755a41a86cSSharon Dvir goto out_no_pci; 3476e705c121SKalle Valo } 3477e705c121SKalle Valo 3478e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3479e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3480e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3481e705c121SKalle Valo 3482e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3483e705c121SKalle Valo iwl_disable_interrupts(trans); 3484e705c121SKalle Valo 3485e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 34869a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 34879a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 34889a098a89SRajat Jain ret = -EIO; 34899a098a89SRajat Jain goto out_no_pci; 34909a098a89SRajat Jain } 34919a098a89SRajat Jain 3492e705c121SKalle Valo /* 3493e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3494e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3495e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3496e705c121SKalle Valo * in the old format. 3497e705c121SKalle Valo */ 34986e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3499e705c121SKalle Valo unsigned long flags; 3500e705c121SKalle Valo 3501e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3502e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3503e705c121SKalle Valo 3504e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3505e705c121SKalle Valo if (ret) { 3506e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 35075a41a86cSSharon Dvir goto out_no_pci; 3508e705c121SKalle Valo } 3509e705c121SKalle Valo 3510e705c121SKalle Valo /* 3511e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3512e705c121SKalle Valo * id located at the AUX bus MISC address space. 3513e705c121SKalle Valo */ 3514c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 3515c96b5eecSJohannes Berg if (ret) 35165a41a86cSSharon Dvir goto out_no_pci; 3517e705c121SKalle Valo 351823ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3519e705c121SKalle Valo u32 hw_step; 3520e705c121SKalle Valo 3521ea695b7cSShaul Triebitz hw_step = iwl_read_umac_prph_no_grab(trans, 3522ea695b7cSShaul Triebitz WFPM_CTRL_REG); 3523e705c121SKalle Valo hw_step |= ENABLE_WFPM; 3524ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, 3525ea695b7cSShaul Triebitz hw_step); 352614ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3527e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3528e705c121SKalle Valo if (hw_step == 0x3) 3529e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3530e705c121SKalle Valo (SILICON_C_STEP << 2); 3531e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3532e705c121SKalle Valo } 3533e705c121SKalle Valo } 3534e705c121SKalle Valo 353599be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 353699be6166SLuca Coelho 3537f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 35381afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 353933708052SLuca Coelho 3540ff911dcaSShaul Triebitz if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { 3541ff911dcaSShaul Triebitz if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { 3542ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; 3543ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3544ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3545ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; 3546ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3547ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { 3548ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_so_gf_a0; 35495bd757a6SShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 35505bd757a6SShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) { 35515bd757a6SShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_so_gf4_a0; 3552ff911dcaSShaul Triebitz } 3553085486deSIhab Zhaika } else if (cfg == &iwl_ax101_cfg_qu_hr) { 355433708052SLuca Coelho if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 355533708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3556085486deSIhab Zhaika trans->cfg = &iwl_ax101_cfg_qu_hr; 3557b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3558b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3559b1bbc1a6SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_jf; 3560b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3561b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3562b1bbc1a6SLuca Coelho IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3563b1bbc1a6SLuca Coelho ret = -EINVAL; 3564b1bbc1a6SLuca Coelho goto out_no_pci; 3565b1bbc1a6SLuca Coelho } else { 3566b1bbc1a6SLuca Coelho IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3567b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3568b1bbc1a6SLuca Coelho ret = -EINVAL; 3569b1bbc1a6SLuca Coelho goto out_no_pci; 3570b1bbc1a6SLuca Coelho } 3571b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 35728093bb6dSLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 357399be6166SLuca Coelho (trans->cfg != &iwl22260_2ax_cfg || 357499be6166SLuca Coelho trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) { 3575f6586b69STzipi Peres u32 hw_status; 3576f6586b69STzipi Peres 3577f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 357833708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 357933708052SLuca Coelho /* 358033708052SLuca Coelho * b step fw is the same for physical card and fpga 358133708052SLuca Coelho */ 358233708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 358333708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 358433708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 358533708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 358633708052SLuca Coelho } else { 358733708052SLuca Coelho /* 358833708052SLuca Coelho * a step no FPGA 358933708052SLuca Coelho */ 35902f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3591f6586b69STzipi Peres } 359233708052SLuca Coelho } 3593f6586b69STzipi Peres #endif 35941afb0ae4SHaim Dreyfuss 35952e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3596e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3597e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3598e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3599e705c121SKalle Valo 3600e705c121SKalle Valo /* Initialize the wait queue for commands */ 3601e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3602e705c121SKalle Valo 36034cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 36044cbb8e50SLuciano Coelho 36052e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36062388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36072388bd7bSDan Carpenter if (ret) 36085a41a86cSSharon Dvir goto out_no_pci; 36092e5d4a8fSHaim Dreyfuss } else { 3610e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3611e705c121SKalle Valo if (ret) 36125a41a86cSSharon Dvir goto out_no_pci; 3613e705c121SKalle Valo 36145a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36155a41a86cSSharon Dvir iwl_pcie_isr, 3616e705c121SKalle Valo iwl_pcie_irq_handler, 3617e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3618e705c121SKalle Valo if (ret) { 3619e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3620e705c121SKalle Valo goto out_free_ict; 3621e705c121SKalle Valo } 3622e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 36232e5d4a8fSHaim Dreyfuss } 3624e705c121SKalle Valo 362510a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 362610a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 362710a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 362810a54d81SLuca Coelho 3629b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3630b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3631b3ff1270SLuca Coelho #else 3632b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3633b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3634b3ff1270SLuca Coelho 3635f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3636f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3637f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3638f7805b33SLior Cohen #endif 3639f7805b33SLior Cohen 3640e705c121SKalle Valo return trans; 3641e705c121SKalle Valo 3642e705c121SKalle Valo out_free_ict: 3643e705c121SKalle Valo iwl_pcie_free_ict(trans); 3644e705c121SKalle Valo out_no_pci: 36456eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3646e705c121SKalle Valo iwl_trans_free(trans); 3647e705c121SKalle Valo return ERR_PTR(ret); 3648e705c121SKalle Valo } 3649b8a7547dSShahar S Matityahu 3650b8a7547dSShahar S Matityahu void iwl_trans_sync_nmi(struct iwl_trans *trans) 3651b8a7547dSShahar S Matityahu { 3652b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3653b8a7547dSShahar S Matityahu 3654b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3655b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3656b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 3657b8a7547dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, 3658b8a7547dSShahar S Matityahu CSR_MSIX_HW_INT_CAUSES_AD); 3659b8a7547dSShahar S Matityahu 3660b8a7547dSShahar S Matityahu /* Error detected by uCode */ 3661b8a7547dSShahar S Matityahu if (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) { 3662b8a7547dSShahar S Matityahu /* Clear causes register */ 3663b8a7547dSShahar S Matityahu iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, 3664b8a7547dSShahar S Matityahu inta_hw & 3665b8a7547dSShahar S Matityahu MSIX_HW_INT_CAUSES_REG_SW_ERR); 3666b8a7547dSShahar S Matityahu break; 3667b8a7547dSShahar S Matityahu } 3668b8a7547dSShahar S Matityahu 3669b8a7547dSShahar S Matityahu mdelay(1); 3670b8a7547dSShahar S Matityahu } 3671b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3672b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3673b8a7547dSShahar S Matityahu } 3674