1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/pci-aspm.h> 66e705c121SKalle Valo #include <linux/interrupt.h> 67e705c121SKalle Valo #include <linux/debugfs.h> 68e705c121SKalle Valo #include <linux/sched.h> 69e705c121SKalle Valo #include <linux/bitops.h> 70e705c121SKalle Valo #include <linux/gfp.h> 71e705c121SKalle Valo #include <linux/vmalloc.h> 7249564a80SLuca Coelho #include <linux/module.h> 73f7805b33SLior Cohen #include <linux/wait.h> 74e705c121SKalle Valo 75e705c121SKalle Valo #include "iwl-drv.h" 76e705c121SKalle Valo #include "iwl-trans.h" 77e705c121SKalle Valo #include "iwl-csr.h" 78e705c121SKalle Valo #include "iwl-prph.h" 79e705c121SKalle Valo #include "iwl-scd.h" 80e705c121SKalle Valo #include "iwl-agn-hw.h" 81d962f9b1SJohannes Berg #include "fw/error-dump.h" 82520f03eaSShahar S Matityahu #include "fw/dbg.h" 83e705c121SKalle Valo #include "internal.h" 84e705c121SKalle Valo #include "iwl-fh.h" 85e705c121SKalle Valo 86e705c121SKalle Valo /* extended range in FW SRAM */ 87e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 89e705c121SKalle Valo 904290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 91a6d24fadSRajat Jain { 92c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 93c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 94c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 95a6d24fadSRajat Jain #define PREFIX_LEN 32 96a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 97a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 98a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 99a6d24fadSRajat Jain char *prefix; 100a6d24fadSRajat Jain 101a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 102a6d24fadSRajat Jain return; 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Should be a multiple of 4 */ 105a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 106c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 107c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 108c4d3f2eeSLuca Coelho 109a6d24fadSRajat Jain /* Alloc a max size buffer */ 110a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 111c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 112c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 113c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 114c4d3f2eeSLuca Coelho 115a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 116a6d24fadSRajat Jain if (!buf) 117a6d24fadSRajat Jain return; 118a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 119a6d24fadSRajat Jain 120a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain /* Print wifi device registers */ 123a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 124a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 125a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 126a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 127a6d24fadSRajat Jain goto err_read; 128a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129a6d24fadSRajat Jain 130a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 131c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 132a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 133a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 134a6d24fadSRajat Jain 135a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 136a6d24fadSRajat Jain if (pos) { 137a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 138a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 139a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 140a6d24fadSRajat Jain goto err_read; 141a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 142a6d24fadSRajat Jain 32, 4, buf, i, 0); 143a6d24fadSRajat Jain } 144a6d24fadSRajat Jain 145a6d24fadSRajat Jain /* Print parent device registers next */ 146a6d24fadSRajat Jain if (!pdev->bus->self) 147a6d24fadSRajat Jain goto out; 148a6d24fadSRajat Jain 149a6d24fadSRajat Jain pdev = pdev->bus->self; 150a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 151a6d24fadSRajat Jain 152a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 153a6d24fadSRajat Jain pci_name(pdev)); 154c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 155a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 156a6d24fadSRajat Jain goto err_read; 157a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 158a6d24fadSRajat Jain 159a6d24fadSRajat Jain /* Print root port AER registers */ 160a6d24fadSRajat Jain pos = 0; 161a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 162a6d24fadSRajat Jain if (pdev) 163a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 164a6d24fadSRajat Jain if (pos) { 165a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 166a6d24fadSRajat Jain pci_name(pdev)); 167a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 168a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 169a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 170a6d24fadSRajat Jain goto err_read; 171a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 172a6d24fadSRajat Jain 4, buf, i, 0); 173a6d24fadSRajat Jain } 174f3402d6dSSara Sharon goto out; 175a6d24fadSRajat Jain 176a6d24fadSRajat Jain err_read: 177a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 178a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 179a6d24fadSRajat Jain out: 180a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 181a6d24fadSRajat Jain kfree(buf); 182a6d24fadSRajat Jain } 183a6d24fadSRajat Jain 184870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 185870c2a11SGolan Ben Ami { 186870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 187a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 188a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 189870c2a11SGolan Ben Ami usleep_range(5000, 6000); 190870c2a11SGolan Ben Ami } 191870c2a11SGolan Ben Ami 192e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 193e705c121SKalle Valo { 19488964b2eSSara Sharon int i; 195e705c121SKalle Valo 19691c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.num_blocks; i++) { 19791c28b83SShahar S Matityahu dma_free_coherent(trans->dev, trans->dbg.fw_mon[i].size, 19891c28b83SShahar S Matityahu trans->dbg.fw_mon[i].block, 19991c28b83SShahar S Matityahu trans->dbg.fw_mon[i].physical); 20091c28b83SShahar S Matityahu trans->dbg.fw_mon[i].block = NULL; 20191c28b83SShahar S Matityahu trans->dbg.fw_mon[i].physical = 0; 20291c28b83SShahar S Matityahu trans->dbg.fw_mon[i].size = 0; 20391c28b83SShahar S Matityahu trans->dbg.num_blocks--; 20488964b2eSSara Sharon } 205e705c121SKalle Valo } 206e705c121SKalle Valo 20788964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20888964b2eSSara Sharon u8 max_power, u8 min_power) 209e705c121SKalle Valo { 210c5f97542SShahar S Matityahu void *cpu_addr = NULL; 21188964b2eSSara Sharon dma_addr_t phys = 0; 212e705c121SKalle Valo u32 size = 0; 213e705c121SKalle Valo u8 power; 214e705c121SKalle Valo 21588964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 216e705c121SKalle Valo size = BIT(power); 217c5f97542SShahar S Matityahu cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 218c5f97542SShahar S Matityahu GFP_KERNEL | __GFP_NOWARN | 219c5f97542SShahar S Matityahu __GFP_ZERO | __GFP_COMP); 220c5f97542SShahar S Matityahu if (!cpu_addr) 221e705c121SKalle Valo continue; 222e705c121SKalle Valo 223e705c121SKalle Valo IWL_INFO(trans, 224c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 225c5f97542SShahar S Matityahu size); 226e705c121SKalle Valo break; 227e705c121SKalle Valo } 228e705c121SKalle Valo 229c5f97542SShahar S Matityahu if (WARN_ON_ONCE(!cpu_addr)) 230e705c121SKalle Valo return; 231e705c121SKalle Valo 232e705c121SKalle Valo if (power != max_power) 233e705c121SKalle Valo IWL_ERR(trans, 234e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 235e705c121SKalle Valo (unsigned long)BIT(power - 10), 236e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 237e705c121SKalle Valo 23891c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].block = cpu_addr; 23991c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys; 24091c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].size = size; 24191c28b83SShahar S Matityahu trans->dbg.num_blocks++; 24288964b2eSSara Sharon } 24388964b2eSSara Sharon 24488964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24588964b2eSSara Sharon { 24688964b2eSSara Sharon if (!max_power) { 24788964b2eSSara Sharon /* default max_power is maximum */ 24888964b2eSSara Sharon max_power = 26; 24988964b2eSSara Sharon } else { 25088964b2eSSara Sharon max_power += 11; 25188964b2eSSara Sharon } 25288964b2eSSara Sharon 25388964b2eSSara Sharon if (WARN(max_power > 26, 25488964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25588964b2eSSara Sharon max_power)) 25688964b2eSSara Sharon return; 25788964b2eSSara Sharon 25888964b2eSSara Sharon /* 25988964b2eSSara Sharon * This function allocats the default fw monitor. 26088964b2eSSara Sharon * The optional additional ones will be allocated in runtime 26188964b2eSSara Sharon */ 26291c28b83SShahar S Matityahu if (trans->dbg.num_blocks) 26388964b2eSSara Sharon return; 26488964b2eSSara Sharon 26588964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 266e705c121SKalle Valo } 267e705c121SKalle Valo 268e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 269e705c121SKalle Valo { 270e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 271e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 272e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 273e705c121SKalle Valo } 274e705c121SKalle Valo 275e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 276e705c121SKalle Valo { 277e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 278e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 279e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 280e705c121SKalle Valo } 281e705c121SKalle Valo 282e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 283e705c121SKalle Valo { 284e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 285e705c121SKalle Valo return; 286e705c121SKalle Valo 287e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 288e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 289e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 290e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 291e705c121SKalle Valo else 292e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 293e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 294e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 295e705c121SKalle Valo } 296e705c121SKalle Valo 297e705c121SKalle Valo /* PCI registers */ 298e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 299e705c121SKalle Valo 300eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 301e705c121SKalle Valo { 302e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 303e705c121SKalle Valo u16 lctl; 304e705c121SKalle Valo u16 cap; 305e705c121SKalle Valo 306e705c121SKalle Valo /* 307e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 308e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 309e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 310e705c121SKalle Valo * costs negligible amount of power savings. 311e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 312e705c121SKalle Valo * power savings, even without L1. 313e705c121SKalle Valo */ 314e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 315e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 316e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 317e705c121SKalle Valo else 318e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 319e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 320e705c121SKalle Valo 321e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 322e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 323d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 324e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 325e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 326e705c121SKalle Valo } 327e705c121SKalle Valo 328e705c121SKalle Valo /* 329e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 330e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 331e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 332e705c121SKalle Valo */ 333e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 334e705c121SKalle Valo { 33552b6e168SEmmanuel Grumbach int ret; 33652b6e168SEmmanuel Grumbach 337e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 338e705c121SKalle Valo 339e705c121SKalle Valo /* 340e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 341e705c121SKalle Valo * bits already set by default after reset. 342e705c121SKalle Valo */ 343e705c121SKalle Valo 344e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3456e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 346e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 347e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 348e705c121SKalle Valo 349e705c121SKalle Valo /* 350e705c121SKalle Valo * Disable L0s without affecting L1; 351e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 352e705c121SKalle Valo */ 353e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 354e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 355e705c121SKalle Valo 356e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 357e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 358e705c121SKalle Valo 359e705c121SKalle Valo /* 360e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 361e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 362e705c121SKalle Valo */ 363e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 364e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 365e705c121SKalle Valo 366e705c121SKalle Valo iwl_pcie_apm_config(trans); 367e705c121SKalle Valo 368e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 36977d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 37077d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 371e705c121SKalle Valo 372c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 373c96b5eecSJohannes Berg if (ret) 37452b6e168SEmmanuel Grumbach return ret; 375e705c121SKalle Valo 376e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 377e705c121SKalle Valo /* 378e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 379e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 380e705c121SKalle Valo * not related to host_interrupt_operation_mode. 381e705c121SKalle Valo * 382e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 383e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 384e705c121SKalle Valo * that we wake up from L1 on time. 385e705c121SKalle Valo * 386e705c121SKalle Valo * This looks weird: read twice the same register, discard the 387e705c121SKalle Valo * value, set a bit, and yet again, read that same register 388e705c121SKalle Valo * just to discard the value. But that's the way the hardware 389e705c121SKalle Valo * seems to like it. 390e705c121SKalle Valo */ 391e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 392e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 393e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 394e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 395e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 396e705c121SKalle Valo } 397e705c121SKalle Valo 398e705c121SKalle Valo /* 399e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 400e705c121SKalle Valo * 401e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 402e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 403e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 404e705c121SKalle Valo */ 405e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 406e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 407e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 408e705c121SKalle Valo udelay(20); 409e705c121SKalle Valo 410e705c121SKalle Valo /* Disable L1-Active */ 411e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 412e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 415e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 416e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 417e705c121SKalle Valo } 418e705c121SKalle Valo 419e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 420e705c121SKalle Valo 42152b6e168SEmmanuel Grumbach return 0; 422e705c121SKalle Valo } 423e705c121SKalle Valo 424e705c121SKalle Valo /* 425e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 426e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 427e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 428e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 429e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 430e705c121SKalle Valo */ 431e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 432e705c121SKalle Valo { 433e705c121SKalle Valo int ret; 434e705c121SKalle Valo u32 apmg_gp1_reg; 435e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 436e705c121SKalle Valo u32 dl_cfg_reg; 437e705c121SKalle Valo 438e705c121SKalle Valo /* Force XTAL ON */ 439e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 440e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 441e705c121SKalle Valo 442870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 443e705c121SKalle Valo 444c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 445c96b5eecSJohannes Berg if (WARN_ON(ret)) { 446e705c121SKalle Valo /* Release XTAL ON request */ 447e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 448e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 449e705c121SKalle Valo return; 450e705c121SKalle Valo } 451e705c121SKalle Valo 452e705c121SKalle Valo /* 453e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 454e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 455e705c121SKalle Valo */ 456e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 457e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 458e705c121SKalle Valo 459e705c121SKalle Valo /* 460e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 461e705c121SKalle Valo * caused by APMG idle state. 462e705c121SKalle Valo */ 463e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 464e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 465e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 466e705c121SKalle Valo apmg_xtal_cfg_reg | 467e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 468e705c121SKalle Valo 469870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 470e705c121SKalle Valo 471e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 472e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 473e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 474e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 475e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 476e705c121SKalle Valo 477e705c121SKalle Valo /* Clear delay line clock power up */ 478e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 479e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 480e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 481e705c121SKalle Valo 482e705c121SKalle Valo /* 483e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 484e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 485e705c121SKalle Valo */ 486e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 487e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 488e705c121SKalle Valo 489e705c121SKalle Valo /* 490e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 491e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 492e705c121SKalle Valo */ 493e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 494a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 495e705c121SKalle Valo 496e705c121SKalle Valo /* Activates XTAL resources monitor */ 497e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 498e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 499e705c121SKalle Valo 500e705c121SKalle Valo /* Release XTAL ON request */ 501e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 502e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 503e705c121SKalle Valo udelay(10); 504e705c121SKalle Valo 505e705c121SKalle Valo /* Release APMG XTAL */ 506e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 507e705c121SKalle Valo apmg_xtal_cfg_reg & 508e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 509e705c121SKalle Valo } 510e705c121SKalle Valo 511e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 512e705c121SKalle Valo { 513e8c8935eSJohannes Berg int ret; 514e705c121SKalle Valo 515e705c121SKalle Valo /* stop device's busmaster DMA activity */ 516a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 517a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 518e705c121SKalle Valo 519a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 520a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 521a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 522e705c121SKalle Valo if (ret < 0) 523e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 524e705c121SKalle Valo 525e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 526e705c121SKalle Valo } 527e705c121SKalle Valo 528e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 529e705c121SKalle Valo { 530e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 531e705c121SKalle Valo 532e705c121SKalle Valo if (op_mode_leave) { 533e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 534e705c121SKalle Valo iwl_pcie_apm_init(trans); 535e705c121SKalle Valo 536e705c121SKalle Valo /* inform ME that we are leaving */ 537e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 538e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 539e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5406e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 541e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 542e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 543e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 544e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 545e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 546e705c121SKalle Valo mdelay(1); 547e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 548e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 549e705c121SKalle Valo } 550e705c121SKalle Valo mdelay(5); 551e705c121SKalle Valo } 552e705c121SKalle Valo 553e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 554e705c121SKalle Valo 555e705c121SKalle Valo /* Stop device's DMA activity */ 556e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 557e705c121SKalle Valo 558e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 559e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 560e705c121SKalle Valo return; 561e705c121SKalle Valo } 562e705c121SKalle Valo 563870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 564e705c121SKalle Valo 565e705c121SKalle Valo /* 566e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 567e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 568e705c121SKalle Valo */ 569e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 570a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 571e705c121SKalle Valo } 572e705c121SKalle Valo 573e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 574e705c121SKalle Valo { 575e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 57652b6e168SEmmanuel Grumbach int ret; 577e705c121SKalle Valo 578e705c121SKalle Valo /* nic_init */ 579e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 58052b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 581e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 582e705c121SKalle Valo 58352b6e168SEmmanuel Grumbach if (ret) 58452b6e168SEmmanuel Grumbach return ret; 58552b6e168SEmmanuel Grumbach 586e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 587e705c121SKalle Valo 588e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 589e705c121SKalle Valo 590e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 591e705c121SKalle Valo iwl_pcie_rx_init(trans); 592e705c121SKalle Valo 593e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 594e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 595e705c121SKalle Valo return -ENOMEM; 596e705c121SKalle Valo 597e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 598e705c121SKalle Valo /* enable shadow regs in HW */ 599e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 600e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 601e705c121SKalle Valo } 602e705c121SKalle Valo 603e705c121SKalle Valo return 0; 604e705c121SKalle Valo } 605e705c121SKalle Valo 606e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 607e705c121SKalle Valo 608e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 609e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 610e705c121SKalle Valo { 611e705c121SKalle Valo int ret; 612e705c121SKalle Valo 613e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 614e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 615e705c121SKalle Valo 616e705c121SKalle Valo /* See if we got it */ 617e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 618e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 619e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 620e705c121SKalle Valo HW_READY_TIMEOUT); 621e705c121SKalle Valo 622e705c121SKalle Valo if (ret >= 0) 623e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 624e705c121SKalle Valo 625e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 626e705c121SKalle Valo return ret; 627e705c121SKalle Valo } 628e705c121SKalle Valo 629e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 630eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 631e705c121SKalle Valo { 632e705c121SKalle Valo int ret; 633e705c121SKalle Valo int t = 0; 634e705c121SKalle Valo int iter; 635e705c121SKalle Valo 636e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 637e705c121SKalle Valo 638e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 639e705c121SKalle Valo /* If the card is ready, exit 0 */ 640e705c121SKalle Valo if (ret >= 0) 641e705c121SKalle Valo return 0; 642e705c121SKalle Valo 643e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 644e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 645192185d6SJohannes Berg usleep_range(1000, 2000); 646e705c121SKalle Valo 647e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 648e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 649e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 650e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 651e705c121SKalle Valo 652e705c121SKalle Valo do { 653e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 654e705c121SKalle Valo if (ret >= 0) 655e705c121SKalle Valo return 0; 656e705c121SKalle Valo 657e705c121SKalle Valo usleep_range(200, 1000); 658e705c121SKalle Valo t += 200; 659e705c121SKalle Valo } while (t < 150000); 660e705c121SKalle Valo msleep(25); 661e705c121SKalle Valo } 662e705c121SKalle Valo 663e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 664e705c121SKalle Valo 665e705c121SKalle Valo return ret; 666e705c121SKalle Valo } 667e705c121SKalle Valo 668e705c121SKalle Valo /* 669e705c121SKalle Valo * ucode 670e705c121SKalle Valo */ 671564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 672564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 673564cdce7SSara Sharon u32 byte_cnt) 674e705c121SKalle Valo { 675bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 676e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 677e705c121SKalle Valo 678bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 679e705c121SKalle Valo dst_addr); 680e705c121SKalle Valo 681bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 682e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 683e705c121SKalle Valo 684bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 685e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 686e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 687e705c121SKalle Valo 688bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 689bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 690bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 691e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 692e705c121SKalle Valo 693bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 694e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 695e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 696e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 697564cdce7SSara Sharon } 698e705c121SKalle Valo 699564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 700564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 701564cdce7SSara Sharon u32 byte_cnt) 702564cdce7SSara Sharon { 703564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 704564cdce7SSara Sharon unsigned long flags; 705564cdce7SSara Sharon int ret; 706564cdce7SSara Sharon 707564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 708564cdce7SSara Sharon 709564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 710564cdce7SSara Sharon return -EIO; 711564cdce7SSara Sharon 712564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 713564cdce7SSara Sharon byte_cnt); 714bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 715bac842daSEmmanuel Grumbach 716e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 717e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 718e705c121SKalle Valo if (!ret) { 719e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 720fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 721e705c121SKalle Valo return -ETIMEDOUT; 722e705c121SKalle Valo } 723e705c121SKalle Valo 724e705c121SKalle Valo return 0; 725e705c121SKalle Valo } 726e705c121SKalle Valo 727e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 728e705c121SKalle Valo const struct fw_desc *section) 729e705c121SKalle Valo { 730e705c121SKalle Valo u8 *v_addr; 731e705c121SKalle Valo dma_addr_t p_addr; 732e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 733e705c121SKalle Valo int ret = 0; 734e705c121SKalle Valo 735e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 736e705c121SKalle Valo section_num); 737e705c121SKalle Valo 738e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 739e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 740e705c121SKalle Valo if (!v_addr) { 741e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 742e705c121SKalle Valo chunk_sz = PAGE_SIZE; 743e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 744e705c121SKalle Valo &p_addr, GFP_KERNEL); 745e705c121SKalle Valo if (!v_addr) 746e705c121SKalle Valo return -ENOMEM; 747e705c121SKalle Valo } 748e705c121SKalle Valo 749e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 750e705c121SKalle Valo u32 copy_size, dst_addr; 751e705c121SKalle Valo bool extended_addr = false; 752e705c121SKalle Valo 753e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 754e705c121SKalle Valo dst_addr = section->offset + offset; 755e705c121SKalle Valo 756e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 757e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 758e705c121SKalle Valo extended_addr = true; 759e705c121SKalle Valo 760e705c121SKalle Valo if (extended_addr) 761e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 762e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 763e705c121SKalle Valo 764e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 765e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 766e705c121SKalle Valo copy_size); 767e705c121SKalle Valo 768e705c121SKalle Valo if (extended_addr) 769e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 770e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 771e705c121SKalle Valo 772e705c121SKalle Valo if (ret) { 773e705c121SKalle Valo IWL_ERR(trans, 774e705c121SKalle Valo "Could not load the [%d] uCode section\n", 775e705c121SKalle Valo section_num); 776e705c121SKalle Valo break; 777e705c121SKalle Valo } 778e705c121SKalle Valo } 779e705c121SKalle Valo 780e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 781e705c121SKalle Valo return ret; 782e705c121SKalle Valo } 783e705c121SKalle Valo 784e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 785e705c121SKalle Valo const struct fw_img *image, 786e705c121SKalle Valo int cpu, 787e705c121SKalle Valo int *first_ucode_section) 788e705c121SKalle Valo { 789e705c121SKalle Valo int shift_param; 790e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 791e705c121SKalle Valo u32 val, last_read_idx = 0; 792e705c121SKalle Valo 793e705c121SKalle Valo if (cpu == 1) { 794e705c121SKalle Valo shift_param = 0; 795e705c121SKalle Valo *first_ucode_section = 0; 796e705c121SKalle Valo } else { 797e705c121SKalle Valo shift_param = 16; 798e705c121SKalle Valo (*first_ucode_section)++; 799e705c121SKalle Valo } 800e705c121SKalle Valo 801eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 802e705c121SKalle Valo last_read_idx = i; 803e705c121SKalle Valo 804e705c121SKalle Valo /* 805e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 806e705c121SKalle Valo * CPU1 to CPU2. 807e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 808e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 809e705c121SKalle Valo */ 810e705c121SKalle Valo if (!image->sec[i].data || 811e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 812e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 813e705c121SKalle Valo IWL_DEBUG_FW(trans, 814e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 815e705c121SKalle Valo i); 816e705c121SKalle Valo break; 817e705c121SKalle Valo } 818e705c121SKalle Valo 819e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 820e705c121SKalle Valo if (ret) 821e705c121SKalle Valo return ret; 822e705c121SKalle Valo 823d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 824e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 825e705c121SKalle Valo val = val | (sec_num << shift_param); 826e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 827eda50cdeSSara Sharon 828e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 829e705c121SKalle Valo } 830e705c121SKalle Valo 831e705c121SKalle Valo *first_ucode_section = last_read_idx; 832e705c121SKalle Valo 8332aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8342aabdbdcSEmmanuel Grumbach 835d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 836e705c121SKalle Valo if (cpu == 1) 837d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 838d6a2c5c7SSara Sharon 0xFFFF); 839e705c121SKalle Valo else 840d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 841d6a2c5c7SSara Sharon 0xFFFFFFFF); 842d6a2c5c7SSara Sharon } else { 843d6a2c5c7SSara Sharon if (cpu == 1) 844d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 845d6a2c5c7SSara Sharon 0xFFFF); 846d6a2c5c7SSara Sharon else 847d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 848d6a2c5c7SSara Sharon 0xFFFFFFFF); 849d6a2c5c7SSara Sharon } 850e705c121SKalle Valo 851e705c121SKalle Valo return 0; 852e705c121SKalle Valo } 853e705c121SKalle Valo 854e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 855e705c121SKalle Valo const struct fw_img *image, 856e705c121SKalle Valo int cpu, 857e705c121SKalle Valo int *first_ucode_section) 858e705c121SKalle Valo { 859e705c121SKalle Valo int i, ret = 0; 860e705c121SKalle Valo u32 last_read_idx = 0; 861e705c121SKalle Valo 8623ce4a038SKirtika Ruchandani if (cpu == 1) 863e705c121SKalle Valo *first_ucode_section = 0; 8643ce4a038SKirtika Ruchandani else 865e705c121SKalle Valo (*first_ucode_section)++; 866e705c121SKalle Valo 867eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 868e705c121SKalle Valo last_read_idx = i; 869e705c121SKalle Valo 870e705c121SKalle Valo /* 871e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 872e705c121SKalle Valo * CPU1 to CPU2. 873e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 874e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 875e705c121SKalle Valo */ 876e705c121SKalle Valo if (!image->sec[i].data || 877e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 878e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 879e705c121SKalle Valo IWL_DEBUG_FW(trans, 880e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 881e705c121SKalle Valo i); 882e705c121SKalle Valo break; 883e705c121SKalle Valo } 884e705c121SKalle Valo 885e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 886e705c121SKalle Valo if (ret) 887e705c121SKalle Valo return ret; 888e705c121SKalle Valo } 889e705c121SKalle Valo 890e705c121SKalle Valo *first_ucode_section = last_read_idx; 891e705c121SKalle Valo 892e705c121SKalle Valo return 0; 893e705c121SKalle Valo } 894e705c121SKalle Valo 895c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 896e705c121SKalle Valo { 89791c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 898e705c121SKalle Valo int i; 899e705c121SKalle Valo 90091c28b83SShahar S Matityahu if (trans->dbg.ini_valid) { 90191c28b83SShahar S Matityahu if (!trans->dbg.num_blocks) 9027a14c23dSSara Sharon return; 9037a14c23dSSara Sharon 90453032e6eSShahar S Matityahu IWL_DEBUG_FW(trans, 90553032e6eSShahar S Matityahu "WRT: applying DRAM buffer[0] destination\n"); 906ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 90791c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 9087a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 909ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 91091c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 91191c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size - 256) >> 9127a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 9137a14c23dSSara Sharon return; 9147a14c23dSSara Sharon } 9157a14c23dSSara Sharon 916e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 917e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 918e705c121SKalle Valo 919e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 920e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 921e705c121SKalle Valo else 922e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 923e705c121SKalle Valo 92491c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 925e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 926e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 927e705c121SKalle Valo 928e705c121SKalle Valo switch (dest->reg_ops[i].op) { 929e705c121SKalle Valo case CSR_ASSIGN: 930e705c121SKalle Valo iwl_write32(trans, addr, val); 931e705c121SKalle Valo break; 932e705c121SKalle Valo case CSR_SETBIT: 933e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 934e705c121SKalle Valo break; 935e705c121SKalle Valo case CSR_CLEARBIT: 936e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 937e705c121SKalle Valo break; 938e705c121SKalle Valo case PRPH_ASSIGN: 939e705c121SKalle Valo iwl_write_prph(trans, addr, val); 940e705c121SKalle Valo break; 941e705c121SKalle Valo case PRPH_SETBIT: 942e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 943e705c121SKalle Valo break; 944e705c121SKalle Valo case PRPH_CLEARBIT: 945e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 946e705c121SKalle Valo break; 947e705c121SKalle Valo case PRPH_BLOCKBIT: 948e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 949e705c121SKalle Valo IWL_ERR(trans, 950e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 951e705c121SKalle Valo val, addr); 952e705c121SKalle Valo goto monitor; 953e705c121SKalle Valo } 954e705c121SKalle Valo break; 955e705c121SKalle Valo default: 956e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 957e705c121SKalle Valo dest->reg_ops[i].op); 958e705c121SKalle Valo break; 959e705c121SKalle Valo } 960e705c121SKalle Valo } 961e705c121SKalle Valo 962e705c121SKalle Valo monitor: 96391c28b83SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && trans->dbg.fw_mon[0].size) { 964e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 96591c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 96691c28b83SShahar S Matityahu dest->base_shift); 9676e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 968e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 96991c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 97091c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size - 256) >> 97162d7476dSEmmanuel Grumbach dest->end_shift); 97262d7476dSEmmanuel Grumbach else 97362d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97491c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 97591c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size) >> 97662d7476dSEmmanuel Grumbach dest->end_shift); 977e705c121SKalle Valo } 978e705c121SKalle Valo } 979e705c121SKalle Valo 980e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 981e705c121SKalle Valo const struct fw_img *image) 982e705c121SKalle Valo { 983e705c121SKalle Valo int ret = 0; 984e705c121SKalle Valo int first_ucode_section; 985e705c121SKalle Valo 986e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 987e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 988e705c121SKalle Valo 989e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 990e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 991e705c121SKalle Valo if (ret) 992e705c121SKalle Valo return ret; 993e705c121SKalle Valo 994e705c121SKalle Valo if (image->is_dual_cpus) { 995e705c121SKalle Valo /* set CPU2 header address */ 996e705c121SKalle Valo iwl_write_prph(trans, 997e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 998e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 999e705c121SKalle Valo 1000e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1001e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1002e705c121SKalle Valo &first_ucode_section); 1003e705c121SKalle Valo if (ret) 1004e705c121SKalle Valo return ret; 1005e705c121SKalle Valo } 1006e705c121SKalle Valo 1007e705c121SKalle Valo /* supported for 7000 only for the moment */ 1008e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1009e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1010e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1011e705c121SKalle Valo 101291c28b83SShahar S Matityahu if (trans->dbg.fw_mon[0].size) { 1013e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 101491c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 4); 1015e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 101691c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 101791c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size) >> 4); 1018e705c121SKalle Valo } 10197a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1020e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1021e705c121SKalle Valo } 1022e705c121SKalle Valo 10232aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10242aabdbdcSEmmanuel Grumbach 1025e705c121SKalle Valo /* release CPU reset */ 1026e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1027e705c121SKalle Valo 1028e705c121SKalle Valo return 0; 1029e705c121SKalle Valo } 1030e705c121SKalle Valo 1031e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1032e705c121SKalle Valo const struct fw_img *image) 1033e705c121SKalle Valo { 1034e705c121SKalle Valo int ret = 0; 1035e705c121SKalle Valo int first_ucode_section; 1036e705c121SKalle Valo 1037e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1038e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1039e705c121SKalle Valo 10407a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1041e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1042e705c121SKalle Valo 104382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 104482ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 104582ea7966SSara Sharon 104682ea7966SSara Sharon /* 104782ea7966SSara Sharon * Set default value. On resume reading the values that were 104882ea7966SSara Sharon * zeored can provide debug data on the resume flow. 104982ea7966SSara Sharon * This is for debugging only and has no functional impact. 105082ea7966SSara Sharon */ 105182ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 105282ea7966SSara Sharon 1053e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1054e705c121SKalle Valo /* release CPU reset */ 1055e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1056e705c121SKalle Valo 1057e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1058e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1059e705c121SKalle Valo &first_ucode_section); 1060e705c121SKalle Valo if (ret) 1061e705c121SKalle Valo return ret; 1062e705c121SKalle Valo 1063e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1064e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1065e705c121SKalle Valo &first_ucode_section); 1066e705c121SKalle Valo } 1067e705c121SKalle Valo 10689ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1069727c02dfSSara Sharon { 1070326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1071727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1072326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1073326477e4SJohannes Berg bool report; 1074727c02dfSSara Sharon 1075326477e4SJohannes Berg if (hw_rfkill) { 1076326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1077326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1078326477e4SJohannes Berg } else { 1079326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1080326477e4SJohannes Berg if (trans_pcie->opmode_down) 1081326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1082326477e4SJohannes Berg } 1083727c02dfSSara Sharon 1084326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1085326477e4SJohannes Berg 1086326477e4SJohannes Berg if (prev != report) 1087326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1088727c02dfSSara Sharon 1089727c02dfSSara Sharon return hw_rfkill; 1090727c02dfSSara Sharon } 1091727c02dfSSara Sharon 10927ca00409SHaim Dreyfuss struct iwl_causes_list { 10937ca00409SHaim Dreyfuss u32 cause_num; 10947ca00409SHaim Dreyfuss u32 mask_reg; 10957ca00409SHaim Dreyfuss u8 addr; 10967ca00409SHaim Dreyfuss }; 10977ca00409SHaim Dreyfuss 10987ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 10997ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11007ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11017ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11027ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11037ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11047ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1105ff911dcaSShaul Triebitz {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 11067ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11077ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11087ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11097ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11107ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11117ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11127ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11137ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11147ca00409SHaim Dreyfuss }; 11157ca00409SHaim Dreyfuss 11169b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11179b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11189b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11199b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11209b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11219b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11229b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11239b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11249b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11259b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11269b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11279b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11289b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11299b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11309b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11319b58419eSGolan Ben Ami }; 11329b58419eSGolan Ben Ami 11337ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11347ca00409SHaim Dreyfuss { 11357ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11367ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11379b58419eSGolan Ben Ami int i, arr_size = 1138ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11399b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11407ca00409SHaim Dreyfuss 11417ca00409SHaim Dreyfuss /* 11427ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11437ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11447ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11457ca00409SHaim Dreyfuss */ 11469b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11479b58419eSGolan Ben Ami struct iwl_causes_list *causes = 1148ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11499b58419eSGolan Ben Ami causes_list : causes_list_v2; 11509b58419eSGolan Ben Ami 11519b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11529b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11539b58419eSGolan Ben Ami causes[i].cause_num); 11547ca00409SHaim Dreyfuss } 11557ca00409SHaim Dreyfuss } 11567ca00409SHaim Dreyfuss 11577ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11587ca00409SHaim Dreyfuss { 11597ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11607ca00409SHaim Dreyfuss u32 offset = 11617ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11627ca00409SHaim Dreyfuss u32 val, idx; 11637ca00409SHaim Dreyfuss 11647ca00409SHaim Dreyfuss /* 11657ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11667ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11677ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11687ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11697ca00409SHaim Dreyfuss */ 11707ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11717ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11727ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11737ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11747ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11757ca00409SHaim Dreyfuss } 11767ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11777ca00409SHaim Dreyfuss 11787ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11797ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11807ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11817ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11827ca00409SHaim Dreyfuss 11837ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11847ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11857ca00409SHaim Dreyfuss } 11867ca00409SHaim Dreyfuss 118777c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11887ca00409SHaim Dreyfuss { 11897ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11907ca00409SHaim Dreyfuss 11917ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1192d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1193d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1194ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11957ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11967ca00409SHaim Dreyfuss return; 11977ca00409SHaim Dreyfuss } 1198d7270d61SHaim Dreyfuss /* 1199d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1200d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1201d7270d61SHaim Dreyfuss * prph. 1202d7270d61SHaim Dreyfuss */ 1203d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1204ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12057ca00409SHaim Dreyfuss 12067ca00409SHaim Dreyfuss /* 12077ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12087ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12097ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12107ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12117ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12127ca00409SHaim Dreyfuss */ 12137ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12147ca00409SHaim Dreyfuss 12157ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 121683730058SHaim Dreyfuss } 12177ca00409SHaim Dreyfuss 121883730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 121983730058SHaim Dreyfuss { 122083730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122183730058SHaim Dreyfuss 122283730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122383730058SHaim Dreyfuss 122483730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 122583730058SHaim Dreyfuss return; 122683730058SHaim Dreyfuss 122783730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12287ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 122983730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12307ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12317ca00409SHaim Dreyfuss } 12327ca00409SHaim Dreyfuss 1233bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1234e705c121SKalle Valo { 1235e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1236e705c121SKalle Valo 1237e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1238e705c121SKalle Valo 1239e705c121SKalle Valo if (trans_pcie->is_down) 1240e705c121SKalle Valo return; 1241e705c121SKalle Valo 1242e705c121SKalle Valo trans_pcie->is_down = true; 1243e705c121SKalle Valo 1244e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1245e705c121SKalle Valo iwl_disable_interrupts(trans); 1246e705c121SKalle Valo 1247e705c121SKalle Valo /* device going down, Stop using ICT table */ 1248e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1249e705c121SKalle Valo 1250e705c121SKalle Valo /* 1251e705c121SKalle Valo * If a HW restart happens during firmware loading, 1252e705c121SKalle Valo * then the firmware loading might call this function 1253e705c121SKalle Valo * and later it might be called again due to the 1254e705c121SKalle Valo * restart. So don't process again if the device is 1255e705c121SKalle Valo * already dead. 1256e705c121SKalle Valo */ 1257e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1258a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1259a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1260e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1261e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1262e705c121SKalle Valo 1263e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1264e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1265e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1266e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1267e705c121SKalle Valo udelay(5); 1268e705c121SKalle Valo } 1269e705c121SKalle Valo } 1270e705c121SKalle Valo 1271e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1272e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1273a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1274e705c121SKalle Valo 1275e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1276e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1277e705c121SKalle Valo 1278870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1279e705c121SKalle Valo 1280e705c121SKalle Valo /* 1281f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1282f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1283f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1284f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1285f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1286f4a1f04aSGolan Ben Ami */ 1287f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1288f4a1f04aSGolan Ben Ami 1289f4a1f04aSGolan Ben Ami /* 1290e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1291e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1292e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1293e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1294e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1295e705c121SKalle Valo */ 1296e705c121SKalle Valo iwl_disable_interrupts(trans); 1297e705c121SKalle Valo 1298e705c121SKalle Valo /* clear all status bits */ 1299e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1300e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1301e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1302e705c121SKalle Valo 1303e705c121SKalle Valo /* 1304e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1305e705c121SKalle Valo * interrupt 1306e705c121SKalle Valo */ 1307e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1308e705c121SKalle Valo 1309a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1310e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1311e705c121SKalle Valo } 1312e705c121SKalle Valo 1313eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13142e5d4a8fSHaim Dreyfuss { 13152e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13162e5d4a8fSHaim Dreyfuss 13172e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13182e5d4a8fSHaim Dreyfuss int i; 13192e5d4a8fSHaim Dreyfuss 1320496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13212e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13222e5d4a8fSHaim Dreyfuss } else { 13232e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13242e5d4a8fSHaim Dreyfuss } 13252e5d4a8fSHaim Dreyfuss } 13262e5d4a8fSHaim Dreyfuss 1327a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1328a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1329a6bd005fSEmmanuel Grumbach { 1330a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1331a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1332a6bd005fSEmmanuel Grumbach int ret; 1333a6bd005fSEmmanuel Grumbach 1334a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1335a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1336a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1337a6bd005fSEmmanuel Grumbach ret = -EIO; 1338a6bd005fSEmmanuel Grumbach goto out; 1339a6bd005fSEmmanuel Grumbach } 1340a6bd005fSEmmanuel Grumbach 1341a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1342a6bd005fSEmmanuel Grumbach 1343a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1344a6bd005fSEmmanuel Grumbach 1345a6bd005fSEmmanuel Grumbach /* 1346a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1347a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1348a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1349a6bd005fSEmmanuel Grumbach */ 1350a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1351a6bd005fSEmmanuel Grumbach 1352a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13532e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1354a6bd005fSEmmanuel Grumbach 1355a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1356a6bd005fSEmmanuel Grumbach 1357a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13589ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1359a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1360a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1361a6bd005fSEmmanuel Grumbach goto out; 1362a6bd005fSEmmanuel Grumbach } 1363a6bd005fSEmmanuel Grumbach 1364a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1365a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1366a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1367a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136820aa99bbSAnton Protopopov ret = -EIO; 1369a6bd005fSEmmanuel Grumbach goto out; 1370a6bd005fSEmmanuel Grumbach } 1371a6bd005fSEmmanuel Grumbach 1372a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1373a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1374a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1375a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1376a6bd005fSEmmanuel Grumbach 1377a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1378a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1379a6bd005fSEmmanuel Grumbach 1380a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1381a6bd005fSEmmanuel Grumbach if (ret) { 1382a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1383a6bd005fSEmmanuel Grumbach goto out; 1384a6bd005fSEmmanuel Grumbach } 1385a6bd005fSEmmanuel Grumbach 1386a6bd005fSEmmanuel Grumbach /* 1387a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1388a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1389a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1390a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1391a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1392a6bd005fSEmmanuel Grumbach */ 1393a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1394a6bd005fSEmmanuel Grumbach 1395a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1396a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1397a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1398a6bd005fSEmmanuel Grumbach 1399a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 14006e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1401a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1402a6bd005fSEmmanuel Grumbach else 1403a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1404a6bd005fSEmmanuel Grumbach 1405a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14069ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1407a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1408a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1409a6bd005fSEmmanuel Grumbach 1410a6bd005fSEmmanuel Grumbach out: 1411a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1412a6bd005fSEmmanuel Grumbach return ret; 1413a6bd005fSEmmanuel Grumbach } 1414a6bd005fSEmmanuel Grumbach 1415a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1416a6bd005fSEmmanuel Grumbach { 1417a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1418a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1419a6bd005fSEmmanuel Grumbach } 1420a6bd005fSEmmanuel Grumbach 1421326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1422326477e4SJohannes Berg bool was_in_rfkill) 1423326477e4SJohannes Berg { 1424326477e4SJohannes Berg bool hw_rfkill; 1425326477e4SJohannes Berg 1426326477e4SJohannes Berg /* 1427326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1428326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1429326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1430326477e4SJohannes Berg * op_mode. 1431326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1432326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1433326477e4SJohannes Berg * notification without endless recursion. Under very rare 1434326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1435326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1436326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1437326477e4SJohannes Berg */ 1438326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1439326477e4SJohannes Berg if (hw_rfkill) { 1440326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1441326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1442326477e4SJohannes Berg } else { 1443326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1444326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1445326477e4SJohannes Berg } 1446326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1447326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1448326477e4SJohannes Berg } 1449326477e4SJohannes Berg 1450bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1451e705c121SKalle Valo { 1452e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1453326477e4SJohannes Berg bool was_in_rfkill; 1454e705c121SKalle Valo 1455e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1456326477e4SJohannes Berg trans_pcie->opmode_down = true; 1457326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1458bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1459326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1460e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1461e705c121SKalle Valo } 1462e705c121SKalle Valo 1463e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1464e705c121SKalle Valo { 1465e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1466e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1467e705c121SKalle Valo 1468e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1469e705c121SKalle Valo 1470326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1471326477e4SJohannes Berg state ? "disabled" : "enabled"); 147277c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 147377c09bc8SSara Sharon if (trans->cfg->gen2) 1474bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 147577c09bc8SSara Sharon else 1476bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1477e705c121SKalle Valo } 147877c09bc8SSara Sharon } 1479e705c121SKalle Valo 148023ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 148123ae6128SMatti Gottlieb bool reset) 1482e705c121SKalle Valo { 148323ae6128SMatti Gottlieb if (!reset) { 1484e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1485e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1486e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1487e705c121SKalle Valo } 1488e705c121SKalle Valo 1489e705c121SKalle Valo iwl_disable_interrupts(trans); 1490e705c121SKalle Valo 1491e705c121SKalle Valo /* 1492e705c121SKalle Valo * in testing mode, the host stays awake and the 1493e705c121SKalle Valo * hardware won't be reset (not even partially) 1494e705c121SKalle Valo */ 1495e705c121SKalle Valo if (test) 1496e705c121SKalle Valo return; 1497e705c121SKalle Valo 1498e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1499e705c121SKalle Valo 15002e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1501e705c121SKalle Valo 1502e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1503a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1504e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1505a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1506e705c121SKalle Valo 150723ae6128SMatti Gottlieb if (reset) { 1508e705c121SKalle Valo /* 1509e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1510e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1511e705c121SKalle Valo * to execute some invalid memory upon resume 1512e705c121SKalle Valo */ 1513e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1514e705c121SKalle Valo } 1515e705c121SKalle Valo 1516e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1517e705c121SKalle Valo } 1518e705c121SKalle Valo 1519e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1520e705c121SKalle Valo enum iwl_d3_status *status, 152123ae6128SMatti Gottlieb bool test, bool reset) 1522e705c121SKalle Valo { 1523d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1524e705c121SKalle Valo u32 val; 1525e705c121SKalle Valo int ret; 1526e705c121SKalle Valo 1527e705c121SKalle Valo if (test) { 1528e705c121SKalle Valo iwl_enable_interrupts(trans); 1529e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1530e705c121SKalle Valo return 0; 1531e705c121SKalle Valo } 1532e705c121SKalle Valo 1533a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1534a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1535e705c121SKalle Valo 1536c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 1537c96b5eecSJohannes Berg if (ret) 1538e705c121SKalle Valo return ret; 1539e705c121SKalle Valo 1540f98ad635SEmmanuel Grumbach /* 1541f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1542f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1543f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1544f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1545f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1546f98ad635SEmmanuel Grumbach */ 1547f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1548f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1549f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1550f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1551f98ad635SEmmanuel Grumbach 1552e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1553e705c121SKalle Valo 155423ae6128SMatti Gottlieb if (!reset) { 1555e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1556a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1557e705c121SKalle Valo } else { 1558e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1559e705c121SKalle Valo 1560e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1561e705c121SKalle Valo if (ret) { 1562e705c121SKalle Valo IWL_ERR(trans, 1563e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1564e705c121SKalle Valo return ret; 1565e705c121SKalle Valo } 1566e705c121SKalle Valo } 1567e705c121SKalle Valo 156882ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1569ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 157082ea7966SSara Sharon 1571e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1572e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1573e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1574e705c121SKalle Valo else 1575e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1576e705c121SKalle Valo 1577e705c121SKalle Valo return 0; 1578e705c121SKalle Valo } 1579e705c121SKalle Valo 15802e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15812e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 15822e5d4a8fSHaim Dreyfuss { 15832e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1584ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15852e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15862e5d4a8fSHaim Dreyfuss 158706f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 158806f4b081SSara Sharon goto enable_msi; 158906f4b081SSara Sharon 1590ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 159106f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15922e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15932e5d4a8fSHaim Dreyfuss 159406f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15952e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 159606f4b081SSara Sharon max_irqs); 159706f4b081SSara Sharon if (num_irqs < 0) { 1598496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 159906f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 160006f4b081SSara Sharon num_irqs); 160106f4b081SSara Sharon goto enable_msi; 1602496d83caSHaim Dreyfuss } 160306f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1604496d83caSHaim Dreyfuss 16052e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 160606f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 160706f4b081SSara Sharon num_irqs); 160806f4b081SSara Sharon 1609496d83caSHaim Dreyfuss /* 161006f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 161106f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1612496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1613496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1614496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1615496d83caSHaim Dreyfuss */ 1616ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 161706f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1618496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1619496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1620ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 162106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1622496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1623496d83caSHaim Dreyfuss } else { 162406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1625496d83caSHaim Dreyfuss } 1626ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16272e5d4a8fSHaim Dreyfuss 162806f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1629496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16302e5d4a8fSHaim Dreyfuss return; 16312e5d4a8fSHaim Dreyfuss 163206f4b081SSara Sharon enable_msi: 163306f4b081SSara Sharon ret = pci_enable_msi(pdev); 163406f4b081SSara Sharon if (ret) { 163506f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16362e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16372e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16382e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16392e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16402e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16412e5d4a8fSHaim Dreyfuss } 16422e5d4a8fSHaim Dreyfuss } 16432e5d4a8fSHaim Dreyfuss } 16442e5d4a8fSHaim Dreyfuss 16457c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16467c8d91ebSHaim Dreyfuss { 16477c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16487c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16497c8d91ebSHaim Dreyfuss 16507c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16517c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16527c8d91ebSHaim Dreyfuss offset = 1 + i; 16537c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16547c8d91ebSHaim Dreyfuss /* 16557c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16567c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16577c8d91ebSHaim Dreyfuss */ 16587c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16597c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16607c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16617c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16627c8d91ebSHaim Dreyfuss if (ret) 16637c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16647c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16657c8d91ebSHaim Dreyfuss i); 16667c8d91ebSHaim Dreyfuss } 16677c8d91ebSHaim Dreyfuss } 16687c8d91ebSHaim Dreyfuss 16692e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16702e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16712e5d4a8fSHaim Dreyfuss { 1672496d83caSHaim Dreyfuss int i; 16732e5d4a8fSHaim Dreyfuss 1674496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16752e5d4a8fSHaim Dreyfuss int ret; 16765a41a86cSSharon Dvir struct msix_entry *msix_entry; 167764fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 167864fa3affSSharon Dvir 167964fa3affSSharon Dvir if (!qname) 168064fa3affSSharon Dvir return -ENOMEM; 16812e5d4a8fSHaim Dreyfuss 16825a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16835a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16845a41a86cSSharon Dvir msix_entry->vector, 16852e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1686496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16872e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16882e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16892e5d4a8fSHaim Dreyfuss IRQF_SHARED, 169064fa3affSSharon Dvir qname, 16915a41a86cSSharon Dvir msix_entry); 16922e5d4a8fSHaim Dreyfuss if (ret) { 16932e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16942e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16955a41a86cSSharon Dvir 16962e5d4a8fSHaim Dreyfuss return ret; 16972e5d4a8fSHaim Dreyfuss } 16982e5d4a8fSHaim Dreyfuss } 16997c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17002e5d4a8fSHaim Dreyfuss 17012e5d4a8fSHaim Dreyfuss return 0; 17022e5d4a8fSHaim Dreyfuss } 17032e5d4a8fSHaim Dreyfuss 170444f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 170544f61b5cSShahar S Matityahu { 170644f61b5cSShahar S Matityahu u32 hpm, wprot; 170744f61b5cSShahar S Matityahu 170844f61b5cSShahar S Matityahu switch (trans->cfg->device_family) { 170944f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 171044f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 171144f61b5cSShahar S Matityahu break; 171244f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 171344f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 171444f61b5cSShahar S Matityahu break; 171544f61b5cSShahar S Matityahu default: 171644f61b5cSShahar S Matityahu return 0; 171744f61b5cSShahar S Matityahu } 171844f61b5cSShahar S Matityahu 171944f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 172044f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 172144f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 172244f61b5cSShahar S Matityahu 172344f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 172444f61b5cSShahar S Matityahu IWL_ERR(trans, 172544f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 172644f61b5cSShahar S Matityahu return -EPERM; 172744f61b5cSShahar S Matityahu } 172844f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 172944f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 173044f61b5cSShahar S Matityahu } 173144f61b5cSShahar S Matityahu 173244f61b5cSShahar S Matityahu return 0; 173344f61b5cSShahar S Matityahu } 173444f61b5cSShahar S Matityahu 1735bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1736e705c121SKalle Valo { 1737e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1738e705c121SKalle Valo int err; 1739e705c121SKalle Valo 1740e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1741e705c121SKalle Valo 1742e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1743e705c121SKalle Valo if (err) { 1744e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1745e705c121SKalle Valo return err; 1746e705c121SKalle Valo } 1747e705c121SKalle Valo 174844f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 174944f61b5cSShahar S Matityahu if (err) 175044f61b5cSShahar S Matityahu return err; 17518954e1ebSShahar S Matityahu 1752870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1753e705c121SKalle Valo 175452b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 175552b6e168SEmmanuel Grumbach if (err) 175652b6e168SEmmanuel Grumbach return err; 1757e705c121SKalle Valo 17582e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 175983730058SHaim Dreyfuss 1760e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1761e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1762e705c121SKalle Valo 1763326477e4SJohannes Berg trans_pcie->opmode_down = false; 1764326477e4SJohannes Berg 1765e705c121SKalle Valo /* Set is_down to false here so that...*/ 1766e705c121SKalle Valo trans_pcie->is_down = false; 1767e705c121SKalle Valo 1768e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17699ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1770e705c121SKalle Valo 1771e705c121SKalle Valo return 0; 1772e705c121SKalle Valo } 1773e705c121SKalle Valo 1774bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1775e705c121SKalle Valo { 1776e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1777e705c121SKalle Valo int ret; 1778e705c121SKalle Valo 1779e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1780bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1781e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1782e705c121SKalle Valo 1783e705c121SKalle Valo return ret; 1784e705c121SKalle Valo } 1785e705c121SKalle Valo 1786e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1787e705c121SKalle Valo { 1788e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1789e705c121SKalle Valo 1790e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1791e705c121SKalle Valo 1792e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1793e705c121SKalle Valo iwl_disable_interrupts(trans); 1794e705c121SKalle Valo 1795e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1796e705c121SKalle Valo 1797e705c121SKalle Valo iwl_disable_interrupts(trans); 1798e705c121SKalle Valo 1799e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1800e705c121SKalle Valo 1801e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1802e705c121SKalle Valo 18032e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1804e705c121SKalle Valo } 1805e705c121SKalle Valo 1806e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1807e705c121SKalle Valo { 1808e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1809e705c121SKalle Valo } 1810e705c121SKalle Valo 1811e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1812e705c121SKalle Valo { 1813e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1814e705c121SKalle Valo } 1815e705c121SKalle Valo 1816e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1817e705c121SKalle Valo { 1818e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1819e705c121SKalle Valo } 1820e705c121SKalle Valo 182184fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 182284fb372cSSara Sharon { 182384fb372cSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 182484fb372cSSara Sharon return 0x00FFFFFF; 182584fb372cSSara Sharon else 182684fb372cSSara Sharon return 0x000FFFFF; 182784fb372cSSara Sharon } 182884fb372cSSara Sharon 1829e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1830e705c121SKalle Valo { 183184fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 183284fb372cSSara Sharon 1833e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 183484fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1835e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1836e705c121SKalle Valo } 1837e705c121SKalle Valo 1838e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1839e705c121SKalle Valo u32 val) 1840e705c121SKalle Valo { 184184fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 184284fb372cSSara Sharon 1843e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 184484fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1845e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1846e705c121SKalle Valo } 1847e705c121SKalle Valo 1848e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1849e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1850e705c121SKalle Valo { 1851e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1852e705c121SKalle Valo 1853e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1854e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1855e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1856e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1857e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1858e705c121SKalle Valo else 1859e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1860e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1861e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1862e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1863e705c121SKalle Valo 18646c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18656c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18666c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1867e705c121SKalle Valo 1868e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1869e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 187041837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1871e705c121SKalle Valo 187221cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 187321cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 187421cb3222SJohannes Berg 187539bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 187639bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 187739bdb17eSSharon Dvir 1878e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1879e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1880e705c121SKalle Valo * As this function may be called again in some corner cases don't 1881e705c121SKalle Valo * do anything if NAPI was already initialized. 1882e705c121SKalle Valo */ 1883bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1884e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1885e705c121SKalle Valo } 1886e705c121SKalle Valo 1887e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1888e705c121SKalle Valo { 1889e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18906eb5e529SEmmanuel Grumbach int i; 1891e705c121SKalle Valo 18922e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1893e705c121SKalle Valo 189413a3a390SSara Sharon if (trans->cfg->gen2) 189513a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 189613a3a390SSara Sharon else 1897e705c121SKalle Valo iwl_pcie_tx_free(trans); 1898e705c121SKalle Valo iwl_pcie_rx_free(trans); 1899e705c121SKalle Valo 190010a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 190110a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 190210a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 190310a54d81SLuca Coelho } 190410a54d81SLuca Coelho 19052e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19067c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19077c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19087c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19097c8d91ebSHaim Dreyfuss NULL); 19107c8d91ebSHaim Dreyfuss } 19112e5d4a8fSHaim Dreyfuss 19122e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19132e5d4a8fSHaim Dreyfuss } else { 1914e705c121SKalle Valo iwl_pcie_free_ict(trans); 19152e5d4a8fSHaim Dreyfuss } 1916e705c121SKalle Valo 1917e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1918e705c121SKalle Valo 19196eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19206eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19216eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19226eb5e529SEmmanuel Grumbach 19236eb5e529SEmmanuel Grumbach if (p->page) 19246eb5e529SEmmanuel Grumbach __free_page(p->page); 19256eb5e529SEmmanuel Grumbach } 19266eb5e529SEmmanuel Grumbach 19276eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1928a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1929e705c121SKalle Valo iwl_trans_free(trans); 1930e705c121SKalle Valo } 1931e705c121SKalle Valo 1932e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1933e705c121SKalle Valo { 1934e705c121SKalle Valo if (state) 1935e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1936e705c121SKalle Valo else 1937e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1938e705c121SKalle Valo } 1939e705c121SKalle Valo 194049564a80SLuca Coelho struct iwl_trans_pcie_removal { 194149564a80SLuca Coelho struct pci_dev *pdev; 194249564a80SLuca Coelho struct work_struct work; 194349564a80SLuca Coelho }; 194449564a80SLuca Coelho 194549564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 194649564a80SLuca Coelho { 194749564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 194849564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 194949564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1950aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 195149564a80SLuca Coelho 195249564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 195349564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 195449564a80SLuca Coelho pci_lock_rescan_remove(); 195549564a80SLuca Coelho pci_dev_put(pdev); 195649564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 195749564a80SLuca Coelho pci_unlock_rescan_remove(); 195849564a80SLuca Coelho 195949564a80SLuca Coelho kfree(removal); 196049564a80SLuca Coelho module_put(THIS_MODULE); 196149564a80SLuca Coelho } 196249564a80SLuca Coelho 196323ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1964e705c121SKalle Valo unsigned long *flags) 1965e705c121SKalle Valo { 1966e705c121SKalle Valo int ret; 1967e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1968e705c121SKalle Valo 1969e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1970e705c121SKalle Valo 1971e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1972e705c121SKalle Valo goto out; 1973e705c121SKalle Valo 1974e705c121SKalle Valo /* this bit wakes up the NIC */ 1975e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1976a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19776e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1978e705c121SKalle Valo udelay(2); 1979e705c121SKalle Valo 1980e705c121SKalle Valo /* 1981e705c121SKalle Valo * These bits say the device is running, and should keep running for 1982e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1983e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1984fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1985fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1986e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1987e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1988e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1989e705c121SKalle Valo * to keep device from sleeping. 1990e705c121SKalle Valo * 1991e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1992e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1993fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 1994fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 1995fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 1996e705c121SKalle Valo * 1997e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1998e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1999e705c121SKalle Valo */ 2000e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2001a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 2002a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2003e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2004e705c121SKalle Valo if (unlikely(ret < 0)) { 200549564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 200649564a80SLuca Coelho 2007e705c121SKalle Valo WARN_ONCE(1, 2008e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 200949564a80SLuca Coelho cntrl); 201049564a80SLuca Coelho 201149564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 201249564a80SLuca Coelho 201349564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 201449564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 201549564a80SLuca Coelho 2016f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 201749564a80SLuca Coelho goto err; 201849564a80SLuca Coelho 201949564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 202049564a80SLuca Coelho 202149564a80SLuca Coelho /* 202249564a80SLuca Coelho * get a module reference to avoid doing this 202349564a80SLuca Coelho * while unloading anyway and to avoid 202449564a80SLuca Coelho * scheduling a work with code that's being 202549564a80SLuca Coelho * removed. 202649564a80SLuca Coelho */ 202749564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 202849564a80SLuca Coelho IWL_ERR(trans, 202949564a80SLuca Coelho "Module is being unloaded - abort\n"); 203049564a80SLuca Coelho goto err; 203149564a80SLuca Coelho } 203249564a80SLuca Coelho 203349564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 203449564a80SLuca Coelho if (!removal) { 203549564a80SLuca Coelho module_put(THIS_MODULE); 203649564a80SLuca Coelho goto err; 203749564a80SLuca Coelho } 203849564a80SLuca Coelho /* 203949564a80SLuca Coelho * we don't need to clear this flag, because 204049564a80SLuca Coelho * the trans will be freed and reallocated. 204149564a80SLuca Coelho */ 2042f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 204349564a80SLuca Coelho 204449564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 204549564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 204649564a80SLuca Coelho pci_dev_get(removal->pdev); 204749564a80SLuca Coelho schedule_work(&removal->work); 204849564a80SLuca Coelho } else { 204949564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 205049564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 205149564a80SLuca Coelho } 205249564a80SLuca Coelho 205349564a80SLuca Coelho err: 2054e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2055e705c121SKalle Valo return false; 2056e705c121SKalle Valo } 2057e705c121SKalle Valo 2058e705c121SKalle Valo out: 2059e705c121SKalle Valo /* 2060e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2061e705c121SKalle Valo * track nic_access anyway. 2062e705c121SKalle Valo */ 2063e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2064e705c121SKalle Valo return true; 2065e705c121SKalle Valo } 2066e705c121SKalle Valo 2067e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2068e705c121SKalle Valo unsigned long *flags) 2069e705c121SKalle Valo { 2070e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2071e705c121SKalle Valo 2072e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2073e705c121SKalle Valo 2074e705c121SKalle Valo /* 2075e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2076e705c121SKalle Valo * track nic_access anyway. 2077e705c121SKalle Valo */ 2078e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2079e705c121SKalle Valo 2080e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2081e705c121SKalle Valo goto out; 2082e705c121SKalle Valo 2083e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2084a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2085e705c121SKalle Valo /* 2086e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2087e705c121SKalle Valo * any previous writes, but we need the write that clears the 2088e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2089e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2090e705c121SKalle Valo */ 2091e705c121SKalle Valo out: 2092e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2093e705c121SKalle Valo } 2094e705c121SKalle Valo 2095e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2096e705c121SKalle Valo void *buf, int dwords) 2097e705c121SKalle Valo { 2098e705c121SKalle Valo unsigned long flags; 2099e705c121SKalle Valo int offs, ret = 0; 2100e705c121SKalle Valo u32 *vals = buf; 2101e705c121SKalle Valo 210223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2103e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2104e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2105e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2106e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2107e705c121SKalle Valo } else { 2108e705c121SKalle Valo ret = -EBUSY; 2109e705c121SKalle Valo } 2110e705c121SKalle Valo return ret; 2111e705c121SKalle Valo } 2112e705c121SKalle Valo 2113e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2114e705c121SKalle Valo const void *buf, int dwords) 2115e705c121SKalle Valo { 2116e705c121SKalle Valo unsigned long flags; 2117e705c121SKalle Valo int offs, ret = 0; 2118e705c121SKalle Valo const u32 *vals = buf; 2119e705c121SKalle Valo 212023ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2121e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2122e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2123e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2124e705c121SKalle Valo vals ? vals[offs] : 0); 2125e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2126e705c121SKalle Valo } else { 2127e705c121SKalle Valo ret = -EBUSY; 2128e705c121SKalle Valo } 2129e705c121SKalle Valo return ret; 2130e705c121SKalle Valo } 2131e705c121SKalle Valo 2132e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2133e705c121SKalle Valo unsigned long txqs, 2134e705c121SKalle Valo bool freeze) 2135e705c121SKalle Valo { 2136e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2137e705c121SKalle Valo int queue; 2138e705c121SKalle Valo 2139e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2140b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2141e705c121SKalle Valo unsigned long now; 2142e705c121SKalle Valo 2143e705c121SKalle Valo spin_lock_bh(&txq->lock); 2144e705c121SKalle Valo 2145e705c121SKalle Valo now = jiffies; 2146e705c121SKalle Valo 2147e705c121SKalle Valo if (txq->frozen == freeze) 2148e705c121SKalle Valo goto next_queue; 2149e705c121SKalle Valo 2150e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2151e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2152e705c121SKalle Valo 2153e705c121SKalle Valo txq->frozen = freeze; 2154e705c121SKalle Valo 2155bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2156e705c121SKalle Valo goto next_queue; 2157e705c121SKalle Valo 2158e705c121SKalle Valo if (freeze) { 2159e705c121SKalle Valo if (unlikely(time_after(now, 2160e705c121SKalle Valo txq->stuck_timer.expires))) { 2161e705c121SKalle Valo /* 2162e705c121SKalle Valo * The timer should have fired, maybe it is 2163e705c121SKalle Valo * spinning right now on the lock. 2164e705c121SKalle Valo */ 2165e705c121SKalle Valo goto next_queue; 2166e705c121SKalle Valo } 2167e705c121SKalle Valo /* remember how long until the timer fires */ 2168e705c121SKalle Valo txq->frozen_expiry_remainder = 2169e705c121SKalle Valo txq->stuck_timer.expires - now; 2170e705c121SKalle Valo del_timer(&txq->stuck_timer); 2171e705c121SKalle Valo goto next_queue; 2172e705c121SKalle Valo } 2173e705c121SKalle Valo 2174e705c121SKalle Valo /* 2175e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2176e705c121SKalle Valo * remainder before it froze 2177e705c121SKalle Valo */ 2178e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2179e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2180e705c121SKalle Valo 2181e705c121SKalle Valo next_queue: 2182e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2183e705c121SKalle Valo } 2184e705c121SKalle Valo } 2185e705c121SKalle Valo 21860cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21870cd58eaaSEmmanuel Grumbach { 21880cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21890cd58eaaSEmmanuel Grumbach int i; 21900cd58eaaSEmmanuel Grumbach 21910cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2192b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 21930cd58eaaSEmmanuel Grumbach 21940cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 21950cd58eaaSEmmanuel Grumbach continue; 21960cd58eaaSEmmanuel Grumbach 21970cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 21980cd58eaaSEmmanuel Grumbach 21990cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22000cd58eaaSEmmanuel Grumbach txq->block--; 22010cd58eaaSEmmanuel Grumbach if (!txq->block) { 22020cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2203bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22040cd58eaaSEmmanuel Grumbach } 22050cd58eaaSEmmanuel Grumbach } else if (block) { 22060cd58eaaSEmmanuel Grumbach txq->block++; 22070cd58eaaSEmmanuel Grumbach } 22080cd58eaaSEmmanuel Grumbach 22090cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22100cd58eaaSEmmanuel Grumbach } 22110cd58eaaSEmmanuel Grumbach } 22120cd58eaaSEmmanuel Grumbach 2213e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2214e705c121SKalle Valo 221538398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 221638398efbSSara Sharon { 2217afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2218afb84431SEmmanuel Grumbach u32 status; 2219afb84431SEmmanuel Grumbach bool active; 2220afb84431SEmmanuel Grumbach u8 fifo; 222138398efbSSara Sharon 2222afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2223afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2224bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2225ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2226ae79785fSSara Sharon return; 2227afb84431SEmmanuel Grumbach } 2228ae79785fSSara Sharon 2229afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2230afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2231afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 223238398efbSSara Sharon 223338398efbSSara Sharon IWL_ERR(trans, 2234afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2235afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2236afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2237afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2238afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 22397b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2240afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 22417b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2242afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 224338398efbSSara Sharon } 224438398efbSSara Sharon 224592536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 224692536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 224792536c96SSara Sharon { 224892536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 224992536c96SSara Sharon 225092536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 225192536c96SSara Sharon return -EINVAL; 225292536c96SSara Sharon 225392536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 225492536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 225592536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 225692536c96SSara Sharon data->fr_bd_wid = 0; 225792536c96SSara Sharon 225892536c96SSara Sharon return 0; 225992536c96SSara Sharon } 226092536c96SSara Sharon 2261d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2262e705c121SKalle Valo { 2263e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2264e705c121SKalle Valo struct iwl_txq *txq; 2265e705c121SKalle Valo unsigned long now = jiffies; 22662ae48edcSSara Sharon bool overflow_tx; 2267e705c121SKalle Valo u8 wr_ptr; 2268e705c121SKalle Valo 22692b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2270f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2271f60c9e59SEmmanuel Grumbach return -ENODEV; 22722b3fae66SMatt Chen 2273d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2274d6d517b7SSara Sharon return -EINVAL; 2275e705c121SKalle Valo 2276d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2277d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22782ae48edcSSara Sharon 22792ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22802ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22812ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22822ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22832ae48edcSSara Sharon 22846aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2285e705c121SKalle Valo 22862ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22872ae48edcSSara Sharon overflow_tx) && 2288e705c121SKalle Valo !time_after(jiffies, 2289e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22906aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2291e705c121SKalle Valo 22922ae48edcSSara Sharon /* 22932ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22942ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 22952ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 22962ae48edcSSara Sharon */ 22972ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2298e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2299e705c121SKalle Valo wr_ptr, write_ptr)) 2300e705c121SKalle Valo return -ETIMEDOUT; 23012ae48edcSSara Sharon wr_ptr = write_ptr; 23022ae48edcSSara Sharon 2303192185d6SJohannes Berg usleep_range(1000, 2000); 23042ae48edcSSara Sharon 23052ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23062ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23072ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23082ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2309e705c121SKalle Valo } 2310e705c121SKalle Valo 2311bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2312e705c121SKalle Valo IWL_ERR(trans, 2313d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2314d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2315d6d517b7SSara Sharon return -ETIMEDOUT; 2316e705c121SKalle Valo } 2317e705c121SKalle Valo 2318d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2319d6d517b7SSara Sharon 2320d6d517b7SSara Sharon return 0; 2321d6d517b7SSara Sharon } 2322d6d517b7SSara Sharon 2323d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2324d6d517b7SSara Sharon { 2325d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2326d6d517b7SSara Sharon int cnt; 2327d6d517b7SSara Sharon int ret = 0; 2328d6d517b7SSara Sharon 2329d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2330d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2331d6d517b7SSara Sharon 2332d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2333d6d517b7SSara Sharon continue; 2334d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2335d6d517b7SSara Sharon continue; 2336d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2337d6d517b7SSara Sharon continue; 2338d6d517b7SSara Sharon 2339d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 234038398efbSSara Sharon if (ret) 2341d6d517b7SSara Sharon break; 2342d6d517b7SSara Sharon } 2343e705c121SKalle Valo 2344e705c121SKalle Valo return ret; 2345e705c121SKalle Valo } 2346e705c121SKalle Valo 2347e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2348e705c121SKalle Valo u32 mask, u32 value) 2349e705c121SKalle Valo { 2350e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2351e705c121SKalle Valo unsigned long flags; 2352e705c121SKalle Valo 2353e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2354e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2355e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2356e705c121SKalle Valo } 2357e705c121SKalle Valo 2358e705c121SKalle Valo static const char *get_csr_string(int cmd) 2359e705c121SKalle Valo { 2360e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2361e705c121SKalle Valo switch (cmd) { 2362e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2363e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2364e705c121SKalle Valo IWL_CMD(CSR_INT); 2365e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2366e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2367e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2368e705c121SKalle Valo IWL_CMD(CSR_RESET); 2369e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2370e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2371e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2372e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2373e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2374e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2375e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2376e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2377e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2378e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2379e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2380e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2381e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2382e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2383e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2384e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2385e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2386e705c121SKalle Valo default: 2387e705c121SKalle Valo return "UNKNOWN"; 2388e705c121SKalle Valo } 2389e705c121SKalle Valo #undef IWL_CMD 2390e705c121SKalle Valo } 2391e705c121SKalle Valo 2392e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2393e705c121SKalle Valo { 2394e705c121SKalle Valo int i; 2395e705c121SKalle Valo static const u32 csr_tbl[] = { 2396e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2397e705c121SKalle Valo CSR_INT_COALESCING, 2398e705c121SKalle Valo CSR_INT, 2399e705c121SKalle Valo CSR_INT_MASK, 2400e705c121SKalle Valo CSR_FH_INT_STATUS, 2401e705c121SKalle Valo CSR_GPIO_IN, 2402e705c121SKalle Valo CSR_RESET, 2403e705c121SKalle Valo CSR_GP_CNTRL, 2404e705c121SKalle Valo CSR_HW_REV, 2405e705c121SKalle Valo CSR_EEPROM_REG, 2406e705c121SKalle Valo CSR_EEPROM_GP, 2407e705c121SKalle Valo CSR_OTP_GP_REG, 2408e705c121SKalle Valo CSR_GIO_REG, 2409e705c121SKalle Valo CSR_GP_UCODE_REG, 2410e705c121SKalle Valo CSR_GP_DRIVER_REG, 2411e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2412e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2413e705c121SKalle Valo CSR_LED_REG, 2414e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2415e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2416e705c121SKalle Valo CSR_ANA_PLL_CFG, 2417e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2418e705c121SKalle Valo CSR_HW_REV_WA_REG, 2419e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2420e705c121SKalle Valo }; 2421e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2422e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2423e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2424e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2425e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2426e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2427e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2428e705c121SKalle Valo } 2429e705c121SKalle Valo } 2430e705c121SKalle Valo 2431e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2432e705c121SKalle Valo /* create and remove of files */ 2433e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2434cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2435cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2436e705c121SKalle Valo } while (0) 2437e705c121SKalle Valo 2438e705c121SKalle Valo /* file operation */ 2439e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2440e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2441e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2442e705c121SKalle Valo .open = simple_open, \ 2443e705c121SKalle Valo .llseek = generic_file_llseek, \ 2444e705c121SKalle Valo }; 2445e705c121SKalle Valo 2446e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2447e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2448e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2449e705c121SKalle Valo .open = simple_open, \ 2450e705c121SKalle Valo .llseek = generic_file_llseek, \ 2451e705c121SKalle Valo }; 2452e705c121SKalle Valo 2453e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2454e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2455e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2456e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2457e705c121SKalle Valo .open = simple_open, \ 2458e705c121SKalle Valo .llseek = generic_file_llseek, \ 2459e705c121SKalle Valo }; 2460e705c121SKalle Valo 2461e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2462e705c121SKalle Valo char __user *user_buf, 2463e705c121SKalle Valo size_t count, loff_t *ppos) 2464e705c121SKalle Valo { 2465e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2466e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2467e705c121SKalle Valo struct iwl_txq *txq; 2468e705c121SKalle Valo char *buf; 2469e705c121SKalle Valo int pos = 0; 2470e705c121SKalle Valo int cnt; 2471e705c121SKalle Valo int ret; 2472e705c121SKalle Valo size_t bufsz; 2473e705c121SKalle Valo 2474e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2475e705c121SKalle Valo 2476b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2477e705c121SKalle Valo return -EAGAIN; 2478e705c121SKalle Valo 2479e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2480e705c121SKalle Valo if (!buf) 2481e705c121SKalle Valo return -ENOMEM; 2482e705c121SKalle Valo 2483e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2484b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2485e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2486e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2487bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2488e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2489e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2490e705c121SKalle Valo txq->need_update, txq->frozen, 2491e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2492e705c121SKalle Valo } 2493e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2494e705c121SKalle Valo kfree(buf); 2495e705c121SKalle Valo return ret; 2496e705c121SKalle Valo } 2497e705c121SKalle Valo 2498e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2499e705c121SKalle Valo char __user *user_buf, 2500e705c121SKalle Valo size_t count, loff_t *ppos) 2501e705c121SKalle Valo { 2502e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2503e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 250478485054SSara Sharon char *buf; 250578485054SSara Sharon int pos = 0, i, ret; 250678485054SSara Sharon size_t bufsz = sizeof(buf); 2507e705c121SKalle Valo 250878485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 250978485054SSara Sharon 251078485054SSara Sharon if (!trans_pcie->rxq) 251178485054SSara Sharon return -EAGAIN; 251278485054SSara Sharon 251378485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 251478485054SSara Sharon if (!buf) 251578485054SSara Sharon return -ENOMEM; 251678485054SSara Sharon 251778485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 251878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 251978485054SSara Sharon 252078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 252178485054SSara Sharon i); 252278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2523e705c121SKalle Valo rxq->read); 252478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2525e705c121SKalle Valo rxq->write); 252678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2527e705c121SKalle Valo rxq->write_actual); 252878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2529e705c121SKalle Valo rxq->need_update); 253078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2531e705c121SKalle Valo rxq->free_count); 2532e705c121SKalle Valo if (rxq->rb_stts) { 25330307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25340307c839SGolan Ben Ami rxq)); 253578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 253678485054SSara Sharon "\tclosed_rb_num: %u\n", 25370307c839SGolan Ben Ami r & 0x0FFF); 2538e705c121SKalle Valo } else { 2539e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 254078485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2541e705c121SKalle Valo } 254278485054SSara Sharon } 254378485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 254478485054SSara Sharon kfree(buf); 254578485054SSara Sharon 254678485054SSara Sharon return ret; 2547e705c121SKalle Valo } 2548e705c121SKalle Valo 2549e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2550e705c121SKalle Valo char __user *user_buf, 2551e705c121SKalle Valo size_t count, loff_t *ppos) 2552e705c121SKalle Valo { 2553e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2554e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2555e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2556e705c121SKalle Valo 2557e705c121SKalle Valo int pos = 0; 2558e705c121SKalle Valo char *buf; 2559e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2560e705c121SKalle Valo ssize_t ret; 2561e705c121SKalle Valo 2562e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2563e705c121SKalle Valo if (!buf) 2564e705c121SKalle Valo return -ENOMEM; 2565e705c121SKalle Valo 2566e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2567e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2568e705c121SKalle Valo 2569e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2570e705c121SKalle Valo isr_stats->hw); 2571e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2572e705c121SKalle Valo isr_stats->sw); 2573e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2574e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2575e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2576e705c121SKalle Valo isr_stats->err_code); 2577e705c121SKalle Valo } 2578e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2579e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2580e705c121SKalle Valo isr_stats->sch); 2581e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2582e705c121SKalle Valo isr_stats->alive); 2583e705c121SKalle Valo #endif 2584e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2585e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2586e705c121SKalle Valo 2587e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2588e705c121SKalle Valo isr_stats->ctkill); 2589e705c121SKalle Valo 2590e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2591e705c121SKalle Valo isr_stats->wakeup); 2592e705c121SKalle Valo 2593e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2594e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2595e705c121SKalle Valo 2596e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2597e705c121SKalle Valo isr_stats->tx); 2598e705c121SKalle Valo 2599e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2600e705c121SKalle Valo isr_stats->unhandled); 2601e705c121SKalle Valo 2602e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2603e705c121SKalle Valo kfree(buf); 2604e705c121SKalle Valo return ret; 2605e705c121SKalle Valo } 2606e705c121SKalle Valo 2607e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2608e705c121SKalle Valo const char __user *user_buf, 2609e705c121SKalle Valo size_t count, loff_t *ppos) 2610e705c121SKalle Valo { 2611e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2612e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2613e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2614e705c121SKalle Valo u32 reset_flag; 2615078f1131SJohannes Berg int ret; 2616e705c121SKalle Valo 2617078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2618078f1131SJohannes Berg if (ret) 2619078f1131SJohannes Berg return ret; 2620e705c121SKalle Valo if (reset_flag == 0) 2621e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2622e705c121SKalle Valo 2623e705c121SKalle Valo return count; 2624e705c121SKalle Valo } 2625e705c121SKalle Valo 2626e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2627e705c121SKalle Valo const char __user *user_buf, 2628e705c121SKalle Valo size_t count, loff_t *ppos) 2629e705c121SKalle Valo { 2630e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2631e705c121SKalle Valo 2632e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2633e705c121SKalle Valo 2634e705c121SKalle Valo return count; 2635e705c121SKalle Valo } 2636e705c121SKalle Valo 2637e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2638e705c121SKalle Valo char __user *user_buf, 2639e705c121SKalle Valo size_t count, loff_t *ppos) 2640e705c121SKalle Valo { 2641e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2642e705c121SKalle Valo char *buf = NULL; 2643e705c121SKalle Valo ssize_t ret; 2644e705c121SKalle Valo 2645e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2646e705c121SKalle Valo if (ret < 0) 2647e705c121SKalle Valo return ret; 2648e705c121SKalle Valo if (!buf) 2649e705c121SKalle Valo return -EINVAL; 2650e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2651e705c121SKalle Valo kfree(buf); 2652e705c121SKalle Valo return ret; 2653e705c121SKalle Valo } 2654e705c121SKalle Valo 2655fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2656fa4de7f7SJohannes Berg char __user *user_buf, 2657fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2658fa4de7f7SJohannes Berg { 2659fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2660fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2661fa4de7f7SJohannes Berg char buf[100]; 2662fa4de7f7SJohannes Berg int pos; 2663fa4de7f7SJohannes Berg 2664fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2665fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2666fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2667fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2668fa4de7f7SJohannes Berg 2669fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2670fa4de7f7SJohannes Berg } 2671fa4de7f7SJohannes Berg 2672fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2673fa4de7f7SJohannes Berg const char __user *user_buf, 2674fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2675fa4de7f7SJohannes Berg { 2676fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2677fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2678c5bf4fa1SJohannes Berg bool new_value; 2679fa4de7f7SJohannes Berg int ret; 2680fa4de7f7SJohannes Berg 2681c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2682fa4de7f7SJohannes Berg if (ret) 2683fa4de7f7SJohannes Berg return ret; 2684c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2685fa4de7f7SJohannes Berg return count; 2686fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2687c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2688c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2689fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2690fa4de7f7SJohannes Berg 2691fa4de7f7SJohannes Berg return count; 2692fa4de7f7SJohannes Berg } 2693fa4de7f7SJohannes Berg 2694f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2695f7805b33SLior Cohen struct file *file) 2696f7805b33SLior Cohen { 2697f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2698f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2699f7805b33SLior Cohen 270091c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 270191c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2702f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2703f7805b33SLior Cohen return -ENOENT; 2704f7805b33SLior Cohen } 2705f7805b33SLior Cohen 2706f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2707f7805b33SLior Cohen return -EBUSY; 2708f7805b33SLior Cohen 2709f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2710f7805b33SLior Cohen return simple_open(inode, file); 2711f7805b33SLior Cohen } 2712f7805b33SLior Cohen 2713f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2714f7805b33SLior Cohen struct file *file) 2715f7805b33SLior Cohen { 2716f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2717f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2718f7805b33SLior Cohen 2719f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2720f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2721f7805b33SLior Cohen return 0; 2722f7805b33SLior Cohen } 2723f7805b33SLior Cohen 2724f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2725f7805b33SLior Cohen void *buf, ssize_t *size, 2726f7805b33SLior Cohen ssize_t *bytes_copied) 2727f7805b33SLior Cohen { 2728f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2729f7805b33SLior Cohen 2730f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2731f7805b33SLior Cohen if (*size > buf_size_left) 2732f7805b33SLior Cohen *size = buf_size_left; 2733f7805b33SLior Cohen 2734f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2735f7805b33SLior Cohen *bytes_copied += *size; 2736f7805b33SLior Cohen 2737f7805b33SLior Cohen if (buf_size_left == *size) 2738f7805b33SLior Cohen return true; 2739f7805b33SLior Cohen return false; 2740f7805b33SLior Cohen } 2741f7805b33SLior Cohen 2742f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2743f7805b33SLior Cohen char __user *user_buf, 2744f7805b33SLior Cohen size_t count, loff_t *ppos) 2745f7805b33SLior Cohen { 2746f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2747f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 274891c28b83SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon[0].block, *curr_buf; 2749f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2750f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2751f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2752f7805b33SLior Cohen bool b_full; 2753f7805b33SLior Cohen 275491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2755f7805b33SLior Cohen write_ptr_addr = 275691c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 275791c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2758f7805b33SLior Cohen } else { 2759f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2760f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2761f7805b33SLior Cohen } 2762f7805b33SLior Cohen 276391c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2764f7805b33SLior Cohen return 0; 2765f7805b33SLior Cohen 2766f7805b33SLior Cohen mutex_lock(&data->mutex); 2767f7805b33SLior Cohen if (data->state == 2768f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2769f7805b33SLior Cohen mutex_unlock(&data->mutex); 2770f7805b33SLior Cohen return 0; 2771f7805b33SLior Cohen } 2772f7805b33SLior Cohen 2773f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2774f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2775f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2776f7805b33SLior Cohen 2777f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2778f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2779f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2780f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2781f7805b33SLior Cohen curr_buf, &size, 2782f7805b33SLior Cohen &bytes_copied); 2783f7805b33SLior Cohen data->prev_wr_ptr += size; 2784f7805b33SLior Cohen 2785f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2786f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 278791c28b83SShahar S Matityahu size = trans->dbg.fw_mon[0].size - data->prev_wr_ptr; 2788f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2789f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2790f7805b33SLior Cohen curr_buf, &size, 2791f7805b33SLior Cohen &bytes_copied); 2792f7805b33SLior Cohen data->prev_wr_ptr += size; 2793f7805b33SLior Cohen 2794f7805b33SLior Cohen if (!b_full) { 2795f7805b33SLior Cohen size = write_ptr; 2796f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2797f7805b33SLior Cohen cpu_addr, &size, 2798f7805b33SLior Cohen &bytes_copied); 2799f7805b33SLior Cohen data->prev_wr_ptr = size; 2800f7805b33SLior Cohen data->prev_wrap_cnt++; 2801f7805b33SLior Cohen } 2802f7805b33SLior Cohen } else { 2803f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2804f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2805f7805b33SLior Cohen IWL_WARN(trans, 2806f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2807f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2808f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2809f7805b33SLior Cohen IWL_WARN(trans, 2810f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2811f7805b33SLior Cohen 2812f7805b33SLior Cohen size = write_ptr; 2813f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2814f7805b33SLior Cohen cpu_addr, &size, 2815f7805b33SLior Cohen &bytes_copied); 2816f7805b33SLior Cohen data->prev_wr_ptr = size; 2817f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2818f7805b33SLior Cohen } 2819f7805b33SLior Cohen 2820f7805b33SLior Cohen mutex_unlock(&data->mutex); 2821f7805b33SLior Cohen 2822f7805b33SLior Cohen return bytes_copied; 2823f7805b33SLior Cohen } 2824f7805b33SLior Cohen 2825e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2826e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2827e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2828e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2829e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2830fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2831e705c121SKalle Valo 2832f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2833f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2834f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2835f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2836f7805b33SLior Cohen }; 2837f7805b33SLior Cohen 2838f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2839cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2840e705c121SKalle Valo { 2841f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2842f8a1edb7SJohannes Berg 28432ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28442ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28452ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28462ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28472ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28482ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2849f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2850e705c121SKalle Valo } 2851f7805b33SLior Cohen 2852f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2853f7805b33SLior Cohen { 2854f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2855f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2856f7805b33SLior Cohen 2857f7805b33SLior Cohen mutex_lock(&data->mutex); 2858f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2859f7805b33SLior Cohen mutex_unlock(&data->mutex); 2860f7805b33SLior Cohen } 2861e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2862e705c121SKalle Valo 28636983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2864e705c121SKalle Valo { 28653cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2866e705c121SKalle Valo u32 cmdlen = 0; 2867e705c121SKalle Valo int i; 2868e705c121SKalle Valo 28693cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 28706983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2871e705c121SKalle Valo 2872e705c121SKalle Valo return cmdlen; 2873e705c121SKalle Valo } 2874e705c121SKalle Valo 2875e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2876e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2877e705c121SKalle Valo int allocated_rb_nums) 2878e705c121SKalle Valo { 2879e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2880e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 288178485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 288278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2883e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2884e705c121SKalle Valo 2885e705c121SKalle Valo spin_lock(&rxq->lock); 2886e705c121SKalle Valo 28870307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2888e705c121SKalle Valo 2889e705c121SKalle Valo for (i = rxq->read, j = 0; 2890e705c121SKalle Valo i != r && j < allocated_rb_nums; 2891e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2892e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2893e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2894e705c121SKalle Valo 2895e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2896e705c121SKalle Valo DMA_FROM_DEVICE); 2897e705c121SKalle Valo 2898e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2899e705c121SKalle Valo 2900e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2901e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2902e705c121SKalle Valo rb = (void *)(*data)->data; 2903e705c121SKalle Valo rb->index = cpu_to_le32(i); 2904e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2905e705c121SKalle Valo /* remap the page for the free benefit */ 2906e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2907e705c121SKalle Valo max_len, 2908e705c121SKalle Valo DMA_FROM_DEVICE); 2909e705c121SKalle Valo 2910e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2911e705c121SKalle Valo } 2912e705c121SKalle Valo 2913e705c121SKalle Valo spin_unlock(&rxq->lock); 2914e705c121SKalle Valo 2915e705c121SKalle Valo return rb_len; 2916e705c121SKalle Valo } 2917e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2918e705c121SKalle Valo 2919e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2920e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2921e705c121SKalle Valo { 2922e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2923e705c121SKalle Valo __le32 *val; 2924e705c121SKalle Valo int i; 2925e705c121SKalle Valo 2926e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2927e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2928e705c121SKalle Valo val = (void *)(*data)->data; 2929e705c121SKalle Valo 2930e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2931e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2932e705c121SKalle Valo 2933e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2934e705c121SKalle Valo 2935e705c121SKalle Valo return csr_len; 2936e705c121SKalle Valo } 2937e705c121SKalle Valo 2938e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2939e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2940e705c121SKalle Valo { 2941e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2942e705c121SKalle Valo unsigned long flags; 2943e705c121SKalle Valo __le32 *val; 2944e705c121SKalle Valo int i; 2945e705c121SKalle Valo 294623ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2947e705c121SKalle Valo return 0; 2948e705c121SKalle Valo 2949e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2950e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2951e705c121SKalle Valo val = (void *)(*data)->data; 2952e705c121SKalle Valo 2953723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2954723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2955723b45e2SLiad Kaufman i += sizeof(u32)) 2956e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2957723b45e2SLiad Kaufman else 2958ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2959ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2960723b45e2SLiad Kaufman i += sizeof(u32)) 2961723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2962723b45e2SLiad Kaufman i)); 2963e705c121SKalle Valo 2964e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2965e705c121SKalle Valo 2966e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2967e705c121SKalle Valo 2968e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2969e705c121SKalle Valo } 2970e705c121SKalle Valo 2971e705c121SKalle Valo static u32 2972e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2973e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2974e705c121SKalle Valo u32 monitor_len) 2975e705c121SKalle Valo { 2976e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2977e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2978e705c121SKalle Valo unsigned long flags; 2979e705c121SKalle Valo u32 i; 2980e705c121SKalle Valo 298123ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2982e705c121SKalle Valo return 0; 2983e705c121SKalle Valo 2984ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2985e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 2986ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 298714ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 2988ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2989e705c121SKalle Valo 2990e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2991e705c121SKalle Valo 2992e705c121SKalle Valo return monitor_len; 2993e705c121SKalle Valo } 2994e705c121SKalle Valo 29957a14c23dSSara Sharon static void 29967a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 29977a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 29987a14c23dSSara Sharon { 2999c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30007a14c23dSSara Sharon 3001c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3002c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3003c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3004c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3005c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 300691c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 300791c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 300891c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 300991c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30107a14c23dSSara Sharon } else { 30117a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30127a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30137a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30147a14c23dSSara Sharon } 3015c88580e1SShahar S Matityahu 3016c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30177a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30187a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30197a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30207a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3021c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3022c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3023c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3024c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3025c88580e1SShahar S Matityahu } 3026c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30277a14c23dSSara Sharon } 30287a14c23dSSara Sharon 3029e705c121SKalle Valo static u32 3030e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3031e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3032e705c121SKalle Valo u32 monitor_len) 3033e705c121SKalle Valo { 3034e705c121SKalle Valo u32 len = 0; 3035e705c121SKalle Valo 303691c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 303791c28b83SShahar S Matityahu (trans->dbg.num_blocks && 3038c88580e1SShahar S Matityahu (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 || 30391d45a700SShahar S Matityahu trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3040e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3041e705c121SKalle Valo 3042e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3043e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30447a14c23dSSara Sharon 30457a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3046e705c121SKalle Valo 3047e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 304891c28b83SShahar S Matityahu if (trans->dbg.num_blocks) { 3049e705c121SKalle Valo memcpy(fw_mon_data->data, 305091c28b83SShahar S Matityahu trans->dbg.fw_mon[0].block, 305191c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size); 3052e705c121SKalle Valo 305391c28b83SShahar S Matityahu monitor_len = trans->dbg.fw_mon[0].size; 305491c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 30557a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3056e705c121SKalle Valo /* 3057e705c121SKalle Valo * Update pointers to reflect actual values after 3058e705c121SKalle Valo * shifting 3059e705c121SKalle Valo */ 306091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3061fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3062fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 306391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3064fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3065fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3066fd527eb5SGolan Ben Ami } else { 3067e705c121SKalle Valo base = iwl_read_prph(trans, base) << 306891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3069fd527eb5SGolan Ben Ami } 3070fd527eb5SGolan Ben Ami 3071e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3072e705c121SKalle Valo monitor_len / sizeof(u32)); 307391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3074e705c121SKalle Valo monitor_len = 3075e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3076e705c121SKalle Valo fw_mon_data, 3077e705c121SKalle Valo monitor_len); 3078e705c121SKalle Valo } else { 3079e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3080e705c121SKalle Valo monitor_len = 0; 3081e705c121SKalle Valo } 3082e705c121SKalle Valo 3083e705c121SKalle Valo len += monitor_len; 3084e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3085e705c121SKalle Valo } 3086e705c121SKalle Valo 3087e705c121SKalle Valo return len; 3088e705c121SKalle Valo } 3089e705c121SKalle Valo 309093079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3091e705c121SKalle Valo { 309291c28b83SShahar S Matityahu if (trans->dbg.num_blocks) { 3093da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3094da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 309591c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size; 309691c28b83SShahar S Matityahu return trans->dbg.fw_mon[0].size; 309791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3098da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3099e705c121SKalle Valo 310091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 310191c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3102fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3103fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 310491c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3105fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3106fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3107fd527eb5SGolan Ben Ami 3108fd527eb5SGolan Ben Ami monitor_len = 3109fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 311091c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3111fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3112fd527eb5SGolan Ben Ami } else { 311391c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 311491c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3115e705c121SKalle Valo 3116e705c121SKalle Valo base = iwl_read_prph(trans, base) << 311791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3118e705c121SKalle Valo end = iwl_read_prph(trans, end) << 311991c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3120e705c121SKalle Valo 3121e705c121SKalle Valo /* Make "end" point to the actual end */ 3122fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 3123fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 312491c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 312591c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3126e705c121SKalle Valo monitor_len = end - base; 3127fd527eb5SGolan Ben Ami } 3128da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3129da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3130e705c121SKalle Valo monitor_len; 3131da752717SShahar S Matityahu return monitor_len; 3132e705c121SKalle Valo } 3133da752717SShahar S Matityahu return 0; 3134da752717SShahar S Matityahu } 3135da752717SShahar S Matityahu 3136da752717SShahar S Matityahu static struct iwl_trans_dump_data 3137da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 313879f033f6SSara Sharon u32 dump_mask) 3139da752717SShahar S Matityahu { 3140da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3141da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3142da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3143da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3144da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3145fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3146da752717SShahar S Matityahu int i, ptr; 3147da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3148da752717SShahar S Matityahu !trans->cfg->mq_rx_supported && 314979f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 315079f033f6SSara Sharon 315179f033f6SSara Sharon if (!dump_mask) 315279f033f6SSara Sharon return NULL; 3153da752717SShahar S Matityahu 3154da752717SShahar S Matityahu /* transport dump header */ 3155da752717SShahar S Matityahu len = sizeof(*dump_data); 3156da752717SShahar S Matityahu 3157da752717SShahar S Matityahu /* host commands */ 3158e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3159da752717SShahar S Matityahu len += sizeof(*data) + 31608672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 31618672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3162da752717SShahar S Matityahu 3163da752717SShahar S Matityahu /* FW monitor */ 3164fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3165da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3166e705c121SKalle Valo 3167e705c121SKalle Valo /* CSR registers */ 316879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3169e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3170e705c121SKalle Valo 3171e705c121SKalle Valo /* FH registers */ 317279f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3173723b45e2SLiad Kaufman if (trans->cfg->gen2) 3174723b45e2SLiad Kaufman len += sizeof(*data) + 3175ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3176ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3177723b45e2SLiad Kaufman else 3178723b45e2SLiad Kaufman len += sizeof(*data) + 3179520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3180520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3181520f03eaSShahar S Matityahu } 3182e705c121SKalle Valo 3183e705c121SKalle Valo if (dump_rbs) { 318478485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 318578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3186e705c121SKalle Valo /* RBs */ 31870307c839SGolan Ben Ami num_rbs = 31880307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3189e705c121SKalle Valo & 0x0FFF; 319078485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3191e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3192e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3193e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3194e705c121SKalle Valo } 3195e705c121SKalle Valo 31965538409bSLiad Kaufman /* Paged memory for gen2 HW */ 319779f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3198505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 31995538409bSLiad Kaufman len += sizeof(*data) + 32005538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3201505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32025538409bSLiad Kaufman 3203e705c121SKalle Valo dump_data = vzalloc(len); 3204e705c121SKalle Valo if (!dump_data) 3205e705c121SKalle Valo return NULL; 3206e705c121SKalle Valo 3207e705c121SKalle Valo len = 0; 3208e705c121SKalle Valo data = (void *)dump_data->data; 3209520f03eaSShahar S Matityahu 3210e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3211520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3212520f03eaSShahar S Matityahu 3213e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3214e705c121SKalle Valo txcmd = (void *)data->data; 3215e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3216bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3217bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32184ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3219e705c121SKalle Valo u32 caplen, cmdlen; 3220e705c121SKalle Valo 3221520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3222520f03eaSShahar S Matityahu cmdq->tfds + 3223520f03eaSShahar S Matityahu tfd_size * ptr); 3224e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3225e705c121SKalle Valo 3226e705c121SKalle Valo if (cmdlen) { 3227e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3228e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3229e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3230520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3231520f03eaSShahar S Matityahu caplen); 3232e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3233e705c121SKalle Valo } 3234e705c121SKalle Valo 32357b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3236e705c121SKalle Valo } 3237e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3238e705c121SKalle Valo 3239e705c121SKalle Valo data->len = cpu_to_le32(len); 3240e705c121SKalle Valo len += sizeof(*data); 3241e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3242520f03eaSShahar S Matityahu } 3243e705c121SKalle Valo 324479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3245e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 324679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3247e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3248e705c121SKalle Valo if (dump_rbs) 3249e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3250e705c121SKalle Valo 32515538409bSLiad Kaufman /* Paged memory for gen2 HW */ 325279f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3253505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 32545538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3255505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 32565538409bSLiad Kaufman 32575538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 32585538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 32595538409bSLiad Kaufman paging = (void *)data->data; 32605538409bSLiad Kaufman paging->index = cpu_to_le32(i); 32615538409bSLiad Kaufman memcpy(paging->data, 3262505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 32635538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 32645538409bSLiad Kaufman 32655538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 32665538409bSLiad Kaufman } 32675538409bSLiad Kaufman } 326879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3269e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3270e705c121SKalle Valo 3271e705c121SKalle Valo dump_data->len = len; 3272e705c121SKalle Valo 3273e705c121SKalle Valo return dump_data; 3274e705c121SKalle Valo } 3275e705c121SKalle Valo 32764cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 32774cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 32784cbb8e50SLuciano Coelho { 32794cbb8e50SLuciano Coelho return 0; 32804cbb8e50SLuciano Coelho } 32814cbb8e50SLuciano Coelho 32824cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 32834cbb8e50SLuciano Coelho { 32844cbb8e50SLuciano Coelho } 32854cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 32864cbb8e50SLuciano Coelho 3287623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3288623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3289623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3290623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3291623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3292623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3293623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3294623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3295623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3296623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3297623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3298870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3299623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3300623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3301623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3302623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3303623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3304d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 3305d1967ce6SShahar S Matityahu .sync_nmi = iwl_trans_pcie_sync_nmi 3306623e7766SSara Sharon 3307623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3308623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3309623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3310623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3311623e7766SSara Sharon #else 3312623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3313623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3314623e7766SSara Sharon 3315e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3316623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3317623e7766SSara Sharon IWL_TRANS_PM_OPS 3318e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3319e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3320e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3321e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3322e705c121SKalle Valo 3323e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3324e705c121SKalle Valo 3325e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3326e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3327e705c121SKalle Valo 3328e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3329e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3330e705c121SKalle Valo 333142db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 333242db09c1SLiad Kaufman 3333d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3334d6d517b7SSara Sharon 3335e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 33360cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3337f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3338f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3339f7805b33SLior Cohen #endif 3340623e7766SSara Sharon }; 3341e705c121SKalle Valo 3342623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3343623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3344623e7766SSara Sharon IWL_TRANS_PM_OPS 3345623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3346eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3347eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 334877c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3349e705c121SKalle Valo 3350ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3351e705c121SKalle Valo 3352ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3353623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3354623e7766SSara Sharon 3355ba7136f3SAlex Malamud .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3356ba7136f3SAlex Malamud 33576b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 33586b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3359d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 336092536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3361f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3362f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3363f7805b33SLior Cohen #endif 3364e705c121SKalle Valo }; 3365e705c121SKalle Valo 3366e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3367e705c121SKalle Valo const struct pci_device_id *ent, 3368e705c121SKalle Valo const struct iwl_cfg *cfg) 3369e705c121SKalle Valo { 3370e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3371e705c121SKalle Valo struct iwl_trans *trans; 337296a6497bSSara Sharon int ret, addr_size; 3373e705c121SKalle Valo 33745a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 33755a41a86cSSharon Dvir if (ret) 33765a41a86cSSharon Dvir return ERR_PTR(ret); 33775a41a86cSSharon Dvir 3378623e7766SSara Sharon if (cfg->gen2) 3379623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3380623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3381623e7766SSara Sharon else 3382e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 33831ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3384e705c121SKalle Valo if (!trans) 3385e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3386e705c121SKalle Valo 3387e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3388e705c121SKalle Valo 3389e705c121SKalle Valo trans_pcie->trans = trans; 3390326477e4SJohannes Berg trans_pcie->opmode_down = true; 3391e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3392e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3393e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3394e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 33956eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 33966eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 33976eb5e529SEmmanuel Grumbach ret = -ENOMEM; 33986eb5e529SEmmanuel Grumbach goto out_no_pci; 33996eb5e529SEmmanuel Grumbach } 3400c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3401e705c121SKalle Valo 3402e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3403e705c121SKalle Valo /* 3404e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3405e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3406e705c121SKalle Valo * lot of power. 3407e705c121SKalle Valo */ 3408e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3409e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3410e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3411e705c121SKalle Valo } 3412e705c121SKalle Valo 34139416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34149416560eSGolan Ben Ami 34156983ba69SSara Sharon if (cfg->use_tfh) { 34162c6262b7SSara Sharon addr_size = 64; 34173cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 34188352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 34196983ba69SSara Sharon } else { 34202c6262b7SSara Sharon addr_size = 36; 34213cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 34226983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 34236983ba69SSara Sharon } 34243cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 34253cd1980bSSara Sharon 3426e705c121SKalle Valo pci_set_master(pdev); 3427e705c121SKalle Valo 342896a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3429e705c121SKalle Valo if (!ret) 343096a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 343196a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3432e705c121SKalle Valo if (ret) { 3433e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3434e705c121SKalle Valo if (!ret) 3435e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3436e705c121SKalle Valo DMA_BIT_MASK(32)); 3437e705c121SKalle Valo /* both attempts failed: */ 3438e705c121SKalle Valo if (ret) { 3439e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34405a41a86cSSharon Dvir goto out_no_pci; 3441e705c121SKalle Valo } 3442e705c121SKalle Valo } 3443e705c121SKalle Valo 34445a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3445e705c121SKalle Valo if (ret) { 34465a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34475a41a86cSSharon Dvir goto out_no_pci; 3448e705c121SKalle Valo } 3449e705c121SKalle Valo 34505a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3451e705c121SKalle Valo if (!trans_pcie->hw_base) { 34525a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3453e705c121SKalle Valo ret = -ENODEV; 34545a41a86cSSharon Dvir goto out_no_pci; 3455e705c121SKalle Valo } 3456e705c121SKalle Valo 3457e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3458e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3459e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3460e705c121SKalle Valo 3461e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3462e705c121SKalle Valo iwl_disable_interrupts(trans); 3463e705c121SKalle Valo 3464e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 34659a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 34669a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 34679a098a89SRajat Jain ret = -EIO; 34689a098a89SRajat Jain goto out_no_pci; 34699a098a89SRajat Jain } 34709a098a89SRajat Jain 3471e705c121SKalle Valo /* 3472e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3473e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3474e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3475e705c121SKalle Valo * in the old format. 3476e705c121SKalle Valo */ 34776e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3478e705c121SKalle Valo unsigned long flags; 3479e705c121SKalle Valo 3480e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3481e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3482e705c121SKalle Valo 3483e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3484e705c121SKalle Valo if (ret) { 3485e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 34865a41a86cSSharon Dvir goto out_no_pci; 3487e705c121SKalle Valo } 3488e705c121SKalle Valo 3489e705c121SKalle Valo /* 3490e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3491e705c121SKalle Valo * id located at the AUX bus MISC address space. 3492e705c121SKalle Valo */ 3493c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 3494c96b5eecSJohannes Berg if (ret) 34955a41a86cSSharon Dvir goto out_no_pci; 3496e705c121SKalle Valo 349723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3498e705c121SKalle Valo u32 hw_step; 3499e705c121SKalle Valo 3500ea695b7cSShaul Triebitz hw_step = iwl_read_umac_prph_no_grab(trans, 3501ea695b7cSShaul Triebitz WFPM_CTRL_REG); 3502e705c121SKalle Valo hw_step |= ENABLE_WFPM; 3503ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, 3504ea695b7cSShaul Triebitz hw_step); 3505cc5470dfSShahar S Matityahu hw_step = iwl_read_prph_no_grab(trans, 3506cc5470dfSShahar S Matityahu CNVI_AUX_MISC_CHIP); 3507e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3508e705c121SKalle Valo if (hw_step == 0x3) 3509e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3510e705c121SKalle Valo (SILICON_C_STEP << 2); 3511e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3512e705c121SKalle Valo } 3513e705c121SKalle Valo } 3514e705c121SKalle Valo 351599be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 351699be6166SLuca Coelho 3517f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 35181afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 351933708052SLuca Coelho 3520ff911dcaSShaul Triebitz if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { 3521ff911dcaSShaul Triebitz if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { 3522ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; 3523ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3524ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3525ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; 3526ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3527ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { 3528d151b0a2SIhab Zhaika trans->cfg = &iwlax211_2ax_cfg_so_gf_a0; 35295bd757a6SShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 35305bd757a6SShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) { 3531d151b0a2SIhab Zhaika trans->cfg = &iwlax411_2ax_cfg_so_gf4_a0; 3532ff911dcaSShaul Triebitz } 3533085486deSIhab Zhaika } else if (cfg == &iwl_ax101_cfg_qu_hr) { 3534498d3eb5SOren Givon if ((CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3535debec2f2SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3536498d3eb5SOren Givon trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) || 3537498d3eb5SOren Givon (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3538498d3eb5SOren Givon CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR1))) { 3539debec2f2SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3540debec2f2SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 354133708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3542085486deSIhab Zhaika trans->cfg = &iwl_ax101_cfg_qu_hr; 3543b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3544b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3545b1bbc1a6SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_jf; 3546b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3547b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3548b1bbc1a6SLuca Coelho IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3549b1bbc1a6SLuca Coelho ret = -EINVAL; 3550b1bbc1a6SLuca Coelho goto out_no_pci; 3551b1bbc1a6SLuca Coelho } else { 3552b1bbc1a6SLuca Coelho IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3553b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3554b1bbc1a6SLuca Coelho ret = -EINVAL; 3555b1bbc1a6SLuca Coelho goto out_no_pci; 3556b1bbc1a6SLuca Coelho } 3557b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 35588093bb6dSLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3559b9500577SLuca Coelho trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) { 3560f6586b69STzipi Peres u32 hw_status; 3561f6586b69STzipi Peres 3562f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 356333708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 356433708052SLuca Coelho /* 356533708052SLuca Coelho * b step fw is the same for physical card and fpga 356633708052SLuca Coelho */ 356733708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 356833708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 356933708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 357033708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 357133708052SLuca Coelho } else { 357233708052SLuca Coelho /* 357333708052SLuca Coelho * a step no FPGA 357433708052SLuca Coelho */ 35752f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3576f6586b69STzipi Peres } 357733708052SLuca Coelho } 3578f6586b69STzipi Peres #endif 35791afb0ae4SHaim Dreyfuss 35802e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3581e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3582e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3583e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3584e705c121SKalle Valo 3585e705c121SKalle Valo /* Initialize the wait queue for commands */ 3586e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3587e705c121SKalle Valo 35882e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 35892388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 35902388bd7bSDan Carpenter if (ret) 35915a41a86cSSharon Dvir goto out_no_pci; 35922e5d4a8fSHaim Dreyfuss } else { 3593e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3594e705c121SKalle Valo if (ret) 35955a41a86cSSharon Dvir goto out_no_pci; 3596e705c121SKalle Valo 35975a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 35985a41a86cSSharon Dvir iwl_pcie_isr, 3599e705c121SKalle Valo iwl_pcie_irq_handler, 3600e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3601e705c121SKalle Valo if (ret) { 3602e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3603e705c121SKalle Valo goto out_free_ict; 3604e705c121SKalle Valo } 3605e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 36062e5d4a8fSHaim Dreyfuss } 3607e705c121SKalle Valo 360810a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 360910a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 361010a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 361110a54d81SLuca Coelho 3612f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3613f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3614f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3615f7805b33SLior Cohen #endif 3616f7805b33SLior Cohen 3617e705c121SKalle Valo return trans; 3618e705c121SKalle Valo 3619e705c121SKalle Valo out_free_ict: 3620e705c121SKalle Valo iwl_pcie_free_ict(trans); 3621e705c121SKalle Valo out_no_pci: 36226eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3623e705c121SKalle Valo iwl_trans_free(trans); 3624e705c121SKalle Valo return ERR_PTR(ret); 3625e705c121SKalle Valo } 3626b8a7547dSShahar S Matityahu 3627d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3628b8a7547dSShahar S Matityahu { 36291c6bca6dSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3630b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3631e4eee943SShahar S Matityahu bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 36321c6bca6dSShahar S Matityahu u32 inta_addr, sw_err_bit; 36331c6bca6dSShahar S Matityahu 36341c6bca6dSShahar S Matityahu if (trans_pcie->msix_enabled) { 36351c6bca6dSShahar S Matityahu inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 36361c6bca6dSShahar S Matityahu sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 36371c6bca6dSShahar S Matityahu } else { 36381c6bca6dSShahar S Matityahu inta_addr = CSR_INT; 36391c6bca6dSShahar S Matityahu sw_err_bit = CSR_INT_BIT_SW_ERR; 36401c6bca6dSShahar S Matityahu } 3641b8a7547dSShahar S Matityahu 3642e4eee943SShahar S Matityahu /* if the interrupts were already disabled, there is no point in 3643e4eee943SShahar S Matityahu * calling iwl_disable_interrupts 3644e4eee943SShahar S Matityahu */ 3645e4eee943SShahar S Matityahu if (interrupts_enabled) 3646b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3647e4eee943SShahar S Matityahu 3648b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3649b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 36501c6bca6dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, inta_addr); 3651b8a7547dSShahar S Matityahu 3652b8a7547dSShahar S Matityahu /* Error detected by uCode */ 36531c6bca6dSShahar S Matityahu if (inta_hw & sw_err_bit) { 3654b8a7547dSShahar S Matityahu /* Clear causes register */ 36551c6bca6dSShahar S Matityahu iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3656b8a7547dSShahar S Matityahu break; 3657b8a7547dSShahar S Matityahu } 3658b8a7547dSShahar S Matityahu 3659b8a7547dSShahar S Matityahu mdelay(1); 3660b8a7547dSShahar S Matityahu } 3661e4eee943SShahar S Matityahu 3662e4eee943SShahar S Matityahu /* enable interrupts only if there were already enabled before this 3663e4eee943SShahar S Matityahu * function to avoid a case were the driver enable interrupts before 3664e4eee943SShahar S Matityahu * proper configurations were made 3665e4eee943SShahar S Matityahu */ 3666e4eee943SShahar S Matityahu if (interrupts_enabled) 3667b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3668e4eee943SShahar S Matityahu 3669b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3670b8a7547dSShahar S Matityahu } 3671