1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/pci-aspm.h> 66e705c121SKalle Valo #include <linux/interrupt.h> 67e705c121SKalle Valo #include <linux/debugfs.h> 68e705c121SKalle Valo #include <linux/sched.h> 69e705c121SKalle Valo #include <linux/bitops.h> 70e705c121SKalle Valo #include <linux/gfp.h> 71e705c121SKalle Valo #include <linux/vmalloc.h> 72b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 7349564a80SLuca Coelho #include <linux/module.h> 74f7805b33SLior Cohen #include <linux/wait.h> 75e705c121SKalle Valo 76e705c121SKalle Valo #include "iwl-drv.h" 77e705c121SKalle Valo #include "iwl-trans.h" 78e705c121SKalle Valo #include "iwl-csr.h" 79e705c121SKalle Valo #include "iwl-prph.h" 80e705c121SKalle Valo #include "iwl-scd.h" 81e705c121SKalle Valo #include "iwl-agn-hw.h" 82d962f9b1SJohannes Berg #include "fw/error-dump.h" 83520f03eaSShahar S Matityahu #include "fw/dbg.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 914290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92a6d24fadSRajat Jain { 93c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 94c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 95c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 96a6d24fadSRajat Jain #define PREFIX_LEN 32 97a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 98a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 99a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 100a6d24fadSRajat Jain char *prefix; 101a6d24fadSRajat Jain 102a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 103a6d24fadSRajat Jain return; 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Should be a multiple of 4 */ 106a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 107c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 108c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 109c4d3f2eeSLuca Coelho 110a6d24fadSRajat Jain /* Alloc a max size buffer */ 111a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 112c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 113c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 114c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 115c4d3f2eeSLuca Coelho 116a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 117a6d24fadSRajat Jain if (!buf) 118a6d24fadSRajat Jain return; 119a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 122a6d24fadSRajat Jain 123a6d24fadSRajat Jain /* Print wifi device registers */ 124a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 125a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 126a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 128a6d24fadSRajat Jain goto err_read; 129a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 130a6d24fadSRajat Jain 131a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 132c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 133a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 134a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 135a6d24fadSRajat Jain 136a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137a6d24fadSRajat Jain if (pos) { 138a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 139a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 140a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 141a6d24fadSRajat Jain goto err_read; 142a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 143a6d24fadSRajat Jain 32, 4, buf, i, 0); 144a6d24fadSRajat Jain } 145a6d24fadSRajat Jain 146a6d24fadSRajat Jain /* Print parent device registers next */ 147a6d24fadSRajat Jain if (!pdev->bus->self) 148a6d24fadSRajat Jain goto out; 149a6d24fadSRajat Jain 150a6d24fadSRajat Jain pdev = pdev->bus->self; 151a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 152a6d24fadSRajat Jain 153a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 154a6d24fadSRajat Jain pci_name(pdev)); 155c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 156a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 157a6d24fadSRajat Jain goto err_read; 158a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 159a6d24fadSRajat Jain 160a6d24fadSRajat Jain /* Print root port AER registers */ 161a6d24fadSRajat Jain pos = 0; 162a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 163a6d24fadSRajat Jain if (pdev) 164a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 165a6d24fadSRajat Jain if (pos) { 166a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 167a6d24fadSRajat Jain pci_name(pdev)); 168a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 169a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 170a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 171a6d24fadSRajat Jain goto err_read; 172a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 173a6d24fadSRajat Jain 4, buf, i, 0); 174a6d24fadSRajat Jain } 175f3402d6dSSara Sharon goto out; 176a6d24fadSRajat Jain 177a6d24fadSRajat Jain err_read: 178a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 179a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 180a6d24fadSRajat Jain out: 181a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 182a6d24fadSRajat Jain kfree(buf); 183a6d24fadSRajat Jain } 184a6d24fadSRajat Jain 185870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 186870c2a11SGolan Ben Ami { 187870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 188a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 189a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 190870c2a11SGolan Ben Ami usleep_range(5000, 6000); 191870c2a11SGolan Ben Ami } 192870c2a11SGolan Ben Ami 193e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 194e705c121SKalle Valo { 19588964b2eSSara Sharon int i; 196e705c121SKalle Valo 19791c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.num_blocks; i++) { 19891c28b83SShahar S Matityahu dma_free_coherent(trans->dev, trans->dbg.fw_mon[i].size, 19991c28b83SShahar S Matityahu trans->dbg.fw_mon[i].block, 20091c28b83SShahar S Matityahu trans->dbg.fw_mon[i].physical); 20191c28b83SShahar S Matityahu trans->dbg.fw_mon[i].block = NULL; 20291c28b83SShahar S Matityahu trans->dbg.fw_mon[i].physical = 0; 20391c28b83SShahar S Matityahu trans->dbg.fw_mon[i].size = 0; 20491c28b83SShahar S Matityahu trans->dbg.num_blocks--; 20588964b2eSSara Sharon } 206e705c121SKalle Valo } 207e705c121SKalle Valo 20888964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20988964b2eSSara Sharon u8 max_power, u8 min_power) 210e705c121SKalle Valo { 211c5f97542SShahar S Matityahu void *cpu_addr = NULL; 21288964b2eSSara Sharon dma_addr_t phys = 0; 213e705c121SKalle Valo u32 size = 0; 214e705c121SKalle Valo u8 power; 215e705c121SKalle Valo 21688964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 217e705c121SKalle Valo size = BIT(power); 218c5f97542SShahar S Matityahu cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 219c5f97542SShahar S Matityahu GFP_KERNEL | __GFP_NOWARN | 220c5f97542SShahar S Matityahu __GFP_ZERO | __GFP_COMP); 221c5f97542SShahar S Matityahu if (!cpu_addr) 222e705c121SKalle Valo continue; 223e705c121SKalle Valo 224e705c121SKalle Valo IWL_INFO(trans, 225c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 226c5f97542SShahar S Matityahu size); 227e705c121SKalle Valo break; 228e705c121SKalle Valo } 229e705c121SKalle Valo 230c5f97542SShahar S Matityahu if (WARN_ON_ONCE(!cpu_addr)) 231e705c121SKalle Valo return; 232e705c121SKalle Valo 233e705c121SKalle Valo if (power != max_power) 234e705c121SKalle Valo IWL_ERR(trans, 235e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 236e705c121SKalle Valo (unsigned long)BIT(power - 10), 237e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 238e705c121SKalle Valo 23991c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].block = cpu_addr; 24091c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].physical = phys; 24191c28b83SShahar S Matityahu trans->dbg.fw_mon[trans->dbg.num_blocks].size = size; 24291c28b83SShahar S Matityahu trans->dbg.num_blocks++; 24388964b2eSSara Sharon } 24488964b2eSSara Sharon 24588964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24688964b2eSSara Sharon { 24788964b2eSSara Sharon if (!max_power) { 24888964b2eSSara Sharon /* default max_power is maximum */ 24988964b2eSSara Sharon max_power = 26; 25088964b2eSSara Sharon } else { 25188964b2eSSara Sharon max_power += 11; 25288964b2eSSara Sharon } 25388964b2eSSara Sharon 25488964b2eSSara Sharon if (WARN(max_power > 26, 25588964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25688964b2eSSara Sharon max_power)) 25788964b2eSSara Sharon return; 25888964b2eSSara Sharon 25988964b2eSSara Sharon /* 26088964b2eSSara Sharon * This function allocats the default fw monitor. 26188964b2eSSara Sharon * The optional additional ones will be allocated in runtime 26288964b2eSSara Sharon */ 26391c28b83SShahar S Matityahu if (trans->dbg.num_blocks) 26488964b2eSSara Sharon return; 26588964b2eSSara Sharon 26688964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 267e705c121SKalle Valo } 268e705c121SKalle Valo 269e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 270e705c121SKalle Valo { 271e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 272e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 273e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 274e705c121SKalle Valo } 275e705c121SKalle Valo 276e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 277e705c121SKalle Valo { 278e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 279e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 280e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 281e705c121SKalle Valo } 282e705c121SKalle Valo 283e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 284e705c121SKalle Valo { 285e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 286e705c121SKalle Valo return; 287e705c121SKalle Valo 288e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 289e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 290e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 291e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 292e705c121SKalle Valo else 293e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 294e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 295e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 296e705c121SKalle Valo } 297e705c121SKalle Valo 298e705c121SKalle Valo /* PCI registers */ 299e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 300e705c121SKalle Valo 301eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 302e705c121SKalle Valo { 303e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 304e705c121SKalle Valo u16 lctl; 305e705c121SKalle Valo u16 cap; 306e705c121SKalle Valo 307e705c121SKalle Valo /* 308e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 309e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 310e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 311e705c121SKalle Valo * costs negligible amount of power savings. 312e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 313e705c121SKalle Valo * power savings, even without L1. 314e705c121SKalle Valo */ 315e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 316e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 317e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 318e705c121SKalle Valo else 319e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 320e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 321e705c121SKalle Valo 322e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 323e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 324d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 325e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 326e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 327e705c121SKalle Valo } 328e705c121SKalle Valo 329e705c121SKalle Valo /* 330e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 331e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 332e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 333e705c121SKalle Valo */ 334e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 335e705c121SKalle Valo { 33652b6e168SEmmanuel Grumbach int ret; 33752b6e168SEmmanuel Grumbach 338e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 339e705c121SKalle Valo 340e705c121SKalle Valo /* 341e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 342e705c121SKalle Valo * bits already set by default after reset. 343e705c121SKalle Valo */ 344e705c121SKalle Valo 345e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3466e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 347e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 348e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 349e705c121SKalle Valo 350e705c121SKalle Valo /* 351e705c121SKalle Valo * Disable L0s without affecting L1; 352e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 353e705c121SKalle Valo */ 354e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 355e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 356e705c121SKalle Valo 357e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 358e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 359e705c121SKalle Valo 360e705c121SKalle Valo /* 361e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 362e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 363e705c121SKalle Valo */ 364e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 365e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 366e705c121SKalle Valo 367e705c121SKalle Valo iwl_pcie_apm_config(trans); 368e705c121SKalle Valo 369e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 37077d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 37177d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 372e705c121SKalle Valo 373c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 374c96b5eecSJohannes Berg if (ret) 37552b6e168SEmmanuel Grumbach return ret; 376e705c121SKalle Valo 377e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 378e705c121SKalle Valo /* 379e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 380e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 381e705c121SKalle Valo * not related to host_interrupt_operation_mode. 382e705c121SKalle Valo * 383e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 384e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 385e705c121SKalle Valo * that we wake up from L1 on time. 386e705c121SKalle Valo * 387e705c121SKalle Valo * This looks weird: read twice the same register, discard the 388e705c121SKalle Valo * value, set a bit, and yet again, read that same register 389e705c121SKalle Valo * just to discard the value. But that's the way the hardware 390e705c121SKalle Valo * seems to like it. 391e705c121SKalle Valo */ 392e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 393e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 394e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 395e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 396e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 397e705c121SKalle Valo } 398e705c121SKalle Valo 399e705c121SKalle Valo /* 400e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 401e705c121SKalle Valo * 402e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 403e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 404e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 405e705c121SKalle Valo */ 406e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 407e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 408e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 409e705c121SKalle Valo udelay(20); 410e705c121SKalle Valo 411e705c121SKalle Valo /* Disable L1-Active */ 412e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 413e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 414e705c121SKalle Valo 415e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 416e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 417e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 418e705c121SKalle Valo } 419e705c121SKalle Valo 420e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 421e705c121SKalle Valo 42252b6e168SEmmanuel Grumbach return 0; 423e705c121SKalle Valo } 424e705c121SKalle Valo 425e705c121SKalle Valo /* 426e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 427e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 428e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 429e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 430e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 431e705c121SKalle Valo */ 432e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 433e705c121SKalle Valo { 434e705c121SKalle Valo int ret; 435e705c121SKalle Valo u32 apmg_gp1_reg; 436e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 437e705c121SKalle Valo u32 dl_cfg_reg; 438e705c121SKalle Valo 439e705c121SKalle Valo /* Force XTAL ON */ 440e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 441e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 442e705c121SKalle Valo 443870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 444e705c121SKalle Valo 445c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 446c96b5eecSJohannes Berg if (WARN_ON(ret)) { 447e705c121SKalle Valo /* Release XTAL ON request */ 448e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 449e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 450e705c121SKalle Valo return; 451e705c121SKalle Valo } 452e705c121SKalle Valo 453e705c121SKalle Valo /* 454e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 455e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 456e705c121SKalle Valo */ 457e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 458e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 459e705c121SKalle Valo 460e705c121SKalle Valo /* 461e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 462e705c121SKalle Valo * caused by APMG idle state. 463e705c121SKalle Valo */ 464e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 465e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 466e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 467e705c121SKalle Valo apmg_xtal_cfg_reg | 468e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 469e705c121SKalle Valo 470870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 471e705c121SKalle Valo 472e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 473e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 474e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 475e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 476e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 477e705c121SKalle Valo 478e705c121SKalle Valo /* Clear delay line clock power up */ 479e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 480e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 481e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 482e705c121SKalle Valo 483e705c121SKalle Valo /* 484e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 485e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 486e705c121SKalle Valo */ 487e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 488e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 489e705c121SKalle Valo 490e705c121SKalle Valo /* 491e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 492e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 493e705c121SKalle Valo */ 494e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 495a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 496e705c121SKalle Valo 497e705c121SKalle Valo /* Activates XTAL resources monitor */ 498e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 499e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 500e705c121SKalle Valo 501e705c121SKalle Valo /* Release XTAL ON request */ 502e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 503e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 504e705c121SKalle Valo udelay(10); 505e705c121SKalle Valo 506e705c121SKalle Valo /* Release APMG XTAL */ 507e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 508e705c121SKalle Valo apmg_xtal_cfg_reg & 509e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 510e705c121SKalle Valo } 511e705c121SKalle Valo 512e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 513e705c121SKalle Valo { 514e8c8935eSJohannes Berg int ret; 515e705c121SKalle Valo 516e705c121SKalle Valo /* stop device's busmaster DMA activity */ 517a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 518a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 519e705c121SKalle Valo 520a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 521a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 522a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 523e705c121SKalle Valo if (ret < 0) 524e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 525e705c121SKalle Valo 526e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 527e705c121SKalle Valo } 528e705c121SKalle Valo 529e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 530e705c121SKalle Valo { 531e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 532e705c121SKalle Valo 533e705c121SKalle Valo if (op_mode_leave) { 534e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 535e705c121SKalle Valo iwl_pcie_apm_init(trans); 536e705c121SKalle Valo 537e705c121SKalle Valo /* inform ME that we are leaving */ 538e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 539e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 540e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5416e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 542e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 544e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 545e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 546e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 547e705c121SKalle Valo mdelay(1); 548e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 549e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 550e705c121SKalle Valo } 551e705c121SKalle Valo mdelay(5); 552e705c121SKalle Valo } 553e705c121SKalle Valo 554e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 555e705c121SKalle Valo 556e705c121SKalle Valo /* Stop device's DMA activity */ 557e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 558e705c121SKalle Valo 559e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 560e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 561e705c121SKalle Valo return; 562e705c121SKalle Valo } 563e705c121SKalle Valo 564870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 565e705c121SKalle Valo 566e705c121SKalle Valo /* 567e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 568e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 569e705c121SKalle Valo */ 570e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 571a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 572e705c121SKalle Valo } 573e705c121SKalle Valo 574e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 575e705c121SKalle Valo { 576e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 57752b6e168SEmmanuel Grumbach int ret; 578e705c121SKalle Valo 579e705c121SKalle Valo /* nic_init */ 580e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 58152b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 582e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 583e705c121SKalle Valo 58452b6e168SEmmanuel Grumbach if (ret) 58552b6e168SEmmanuel Grumbach return ret; 58652b6e168SEmmanuel Grumbach 587e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 588e705c121SKalle Valo 589e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 590e705c121SKalle Valo 591e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 592e705c121SKalle Valo iwl_pcie_rx_init(trans); 593e705c121SKalle Valo 594e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 595e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 596e705c121SKalle Valo return -ENOMEM; 597e705c121SKalle Valo 598e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 599e705c121SKalle Valo /* enable shadow regs in HW */ 600e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 601e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 602e705c121SKalle Valo } 603e705c121SKalle Valo 604e705c121SKalle Valo return 0; 605e705c121SKalle Valo } 606e705c121SKalle Valo 607e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 608e705c121SKalle Valo 609e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 610e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 611e705c121SKalle Valo { 612e705c121SKalle Valo int ret; 613e705c121SKalle Valo 614e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 615e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 616e705c121SKalle Valo 617e705c121SKalle Valo /* See if we got it */ 618e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 619e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 620e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 621e705c121SKalle Valo HW_READY_TIMEOUT); 622e705c121SKalle Valo 623e705c121SKalle Valo if (ret >= 0) 624e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 625e705c121SKalle Valo 626e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 627e705c121SKalle Valo return ret; 628e705c121SKalle Valo } 629e705c121SKalle Valo 630e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 631eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 632e705c121SKalle Valo { 633e705c121SKalle Valo int ret; 634e705c121SKalle Valo int t = 0; 635e705c121SKalle Valo int iter; 636e705c121SKalle Valo 637e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 638e705c121SKalle Valo 639e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 640e705c121SKalle Valo /* If the card is ready, exit 0 */ 641e705c121SKalle Valo if (ret >= 0) 642e705c121SKalle Valo return 0; 643e705c121SKalle Valo 644e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 645e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 646192185d6SJohannes Berg usleep_range(1000, 2000); 647e705c121SKalle Valo 648e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 649e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 650e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 651e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 652e705c121SKalle Valo 653e705c121SKalle Valo do { 654e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 655e705c121SKalle Valo if (ret >= 0) 656e705c121SKalle Valo return 0; 657e705c121SKalle Valo 658e705c121SKalle Valo usleep_range(200, 1000); 659e705c121SKalle Valo t += 200; 660e705c121SKalle Valo } while (t < 150000); 661e705c121SKalle Valo msleep(25); 662e705c121SKalle Valo } 663e705c121SKalle Valo 664e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 665e705c121SKalle Valo 666e705c121SKalle Valo return ret; 667e705c121SKalle Valo } 668e705c121SKalle Valo 669e705c121SKalle Valo /* 670e705c121SKalle Valo * ucode 671e705c121SKalle Valo */ 672564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 673564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 674564cdce7SSara Sharon u32 byte_cnt) 675e705c121SKalle Valo { 676bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 677e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 678e705c121SKalle Valo 679bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 680e705c121SKalle Valo dst_addr); 681e705c121SKalle Valo 682bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 683e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 684e705c121SKalle Valo 685bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 686e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 687e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 688e705c121SKalle Valo 689bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 690bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 691bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 692e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 693e705c121SKalle Valo 694bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 695e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 696e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 697e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 698564cdce7SSara Sharon } 699e705c121SKalle Valo 700564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 701564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 702564cdce7SSara Sharon u32 byte_cnt) 703564cdce7SSara Sharon { 704564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 705564cdce7SSara Sharon unsigned long flags; 706564cdce7SSara Sharon int ret; 707564cdce7SSara Sharon 708564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 709564cdce7SSara Sharon 710564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 711564cdce7SSara Sharon return -EIO; 712564cdce7SSara Sharon 713564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 714564cdce7SSara Sharon byte_cnt); 715bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 716bac842daSEmmanuel Grumbach 717e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 718e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 719e705c121SKalle Valo if (!ret) { 720e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 721fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 722e705c121SKalle Valo return -ETIMEDOUT; 723e705c121SKalle Valo } 724e705c121SKalle Valo 725e705c121SKalle Valo return 0; 726e705c121SKalle Valo } 727e705c121SKalle Valo 728e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 729e705c121SKalle Valo const struct fw_desc *section) 730e705c121SKalle Valo { 731e705c121SKalle Valo u8 *v_addr; 732e705c121SKalle Valo dma_addr_t p_addr; 733e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 734e705c121SKalle Valo int ret = 0; 735e705c121SKalle Valo 736e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 737e705c121SKalle Valo section_num); 738e705c121SKalle Valo 739e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 740e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 741e705c121SKalle Valo if (!v_addr) { 742e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 743e705c121SKalle Valo chunk_sz = PAGE_SIZE; 744e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 745e705c121SKalle Valo &p_addr, GFP_KERNEL); 746e705c121SKalle Valo if (!v_addr) 747e705c121SKalle Valo return -ENOMEM; 748e705c121SKalle Valo } 749e705c121SKalle Valo 750e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 751e705c121SKalle Valo u32 copy_size, dst_addr; 752e705c121SKalle Valo bool extended_addr = false; 753e705c121SKalle Valo 754e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 755e705c121SKalle Valo dst_addr = section->offset + offset; 756e705c121SKalle Valo 757e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 758e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 759e705c121SKalle Valo extended_addr = true; 760e705c121SKalle Valo 761e705c121SKalle Valo if (extended_addr) 762e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 763e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 764e705c121SKalle Valo 765e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 766e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 767e705c121SKalle Valo copy_size); 768e705c121SKalle Valo 769e705c121SKalle Valo if (extended_addr) 770e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 771e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 772e705c121SKalle Valo 773e705c121SKalle Valo if (ret) { 774e705c121SKalle Valo IWL_ERR(trans, 775e705c121SKalle Valo "Could not load the [%d] uCode section\n", 776e705c121SKalle Valo section_num); 777e705c121SKalle Valo break; 778e705c121SKalle Valo } 779e705c121SKalle Valo } 780e705c121SKalle Valo 781e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 782e705c121SKalle Valo return ret; 783e705c121SKalle Valo } 784e705c121SKalle Valo 785e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 786e705c121SKalle Valo const struct fw_img *image, 787e705c121SKalle Valo int cpu, 788e705c121SKalle Valo int *first_ucode_section) 789e705c121SKalle Valo { 790e705c121SKalle Valo int shift_param; 791e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 792e705c121SKalle Valo u32 val, last_read_idx = 0; 793e705c121SKalle Valo 794e705c121SKalle Valo if (cpu == 1) { 795e705c121SKalle Valo shift_param = 0; 796e705c121SKalle Valo *first_ucode_section = 0; 797e705c121SKalle Valo } else { 798e705c121SKalle Valo shift_param = 16; 799e705c121SKalle Valo (*first_ucode_section)++; 800e705c121SKalle Valo } 801e705c121SKalle Valo 802eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 803e705c121SKalle Valo last_read_idx = i; 804e705c121SKalle Valo 805e705c121SKalle Valo /* 806e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 807e705c121SKalle Valo * CPU1 to CPU2. 808e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 809e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 810e705c121SKalle Valo */ 811e705c121SKalle Valo if (!image->sec[i].data || 812e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 813e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 814e705c121SKalle Valo IWL_DEBUG_FW(trans, 815e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 816e705c121SKalle Valo i); 817e705c121SKalle Valo break; 818e705c121SKalle Valo } 819e705c121SKalle Valo 820e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 821e705c121SKalle Valo if (ret) 822e705c121SKalle Valo return ret; 823e705c121SKalle Valo 824d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 825e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 826e705c121SKalle Valo val = val | (sec_num << shift_param); 827e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 828eda50cdeSSara Sharon 829e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 830e705c121SKalle Valo } 831e705c121SKalle Valo 832e705c121SKalle Valo *first_ucode_section = last_read_idx; 833e705c121SKalle Valo 8342aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8352aabdbdcSEmmanuel Grumbach 836d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 837e705c121SKalle Valo if (cpu == 1) 838d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 839d6a2c5c7SSara Sharon 0xFFFF); 840e705c121SKalle Valo else 841d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 842d6a2c5c7SSara Sharon 0xFFFFFFFF); 843d6a2c5c7SSara Sharon } else { 844d6a2c5c7SSara Sharon if (cpu == 1) 845d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 846d6a2c5c7SSara Sharon 0xFFFF); 847d6a2c5c7SSara Sharon else 848d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 849d6a2c5c7SSara Sharon 0xFFFFFFFF); 850d6a2c5c7SSara Sharon } 851e705c121SKalle Valo 852e705c121SKalle Valo return 0; 853e705c121SKalle Valo } 854e705c121SKalle Valo 855e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 856e705c121SKalle Valo const struct fw_img *image, 857e705c121SKalle Valo int cpu, 858e705c121SKalle Valo int *first_ucode_section) 859e705c121SKalle Valo { 860e705c121SKalle Valo int i, ret = 0; 861e705c121SKalle Valo u32 last_read_idx = 0; 862e705c121SKalle Valo 8633ce4a038SKirtika Ruchandani if (cpu == 1) 864e705c121SKalle Valo *first_ucode_section = 0; 8653ce4a038SKirtika Ruchandani else 866e705c121SKalle Valo (*first_ucode_section)++; 867e705c121SKalle Valo 868eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 869e705c121SKalle Valo last_read_idx = i; 870e705c121SKalle Valo 871e705c121SKalle Valo /* 872e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 873e705c121SKalle Valo * CPU1 to CPU2. 874e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 875e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 876e705c121SKalle Valo */ 877e705c121SKalle Valo if (!image->sec[i].data || 878e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 879e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 880e705c121SKalle Valo IWL_DEBUG_FW(trans, 881e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 882e705c121SKalle Valo i); 883e705c121SKalle Valo break; 884e705c121SKalle Valo } 885e705c121SKalle Valo 886e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 887e705c121SKalle Valo if (ret) 888e705c121SKalle Valo return ret; 889e705c121SKalle Valo } 890e705c121SKalle Valo 891e705c121SKalle Valo *first_ucode_section = last_read_idx; 892e705c121SKalle Valo 893e705c121SKalle Valo return 0; 894e705c121SKalle Valo } 895e705c121SKalle Valo 896c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 897e705c121SKalle Valo { 89891c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 899e705c121SKalle Valo int i; 900e705c121SKalle Valo 90191c28b83SShahar S Matityahu if (trans->dbg.ini_valid) { 90291c28b83SShahar S Matityahu if (!trans->dbg.num_blocks) 9037a14c23dSSara Sharon return; 9047a14c23dSSara Sharon 90553032e6eSShahar S Matityahu IWL_DEBUG_FW(trans, 90653032e6eSShahar S Matityahu "WRT: applying DRAM buffer[0] destination\n"); 907ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 90891c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 9097a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 910ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 91191c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 91291c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size - 256) >> 9137a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 9147a14c23dSSara Sharon return; 9157a14c23dSSara Sharon } 9167a14c23dSSara Sharon 917e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 918e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 919e705c121SKalle Valo 920e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 921e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 922e705c121SKalle Valo else 923e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 924e705c121SKalle Valo 92591c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 926e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 927e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 928e705c121SKalle Valo 929e705c121SKalle Valo switch (dest->reg_ops[i].op) { 930e705c121SKalle Valo case CSR_ASSIGN: 931e705c121SKalle Valo iwl_write32(trans, addr, val); 932e705c121SKalle Valo break; 933e705c121SKalle Valo case CSR_SETBIT: 934e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 935e705c121SKalle Valo break; 936e705c121SKalle Valo case CSR_CLEARBIT: 937e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 938e705c121SKalle Valo break; 939e705c121SKalle Valo case PRPH_ASSIGN: 940e705c121SKalle Valo iwl_write_prph(trans, addr, val); 941e705c121SKalle Valo break; 942e705c121SKalle Valo case PRPH_SETBIT: 943e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 944e705c121SKalle Valo break; 945e705c121SKalle Valo case PRPH_CLEARBIT: 946e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 947e705c121SKalle Valo break; 948e705c121SKalle Valo case PRPH_BLOCKBIT: 949e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 950e705c121SKalle Valo IWL_ERR(trans, 951e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 952e705c121SKalle Valo val, addr); 953e705c121SKalle Valo goto monitor; 954e705c121SKalle Valo } 955e705c121SKalle Valo break; 956e705c121SKalle Valo default: 957e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 958e705c121SKalle Valo dest->reg_ops[i].op); 959e705c121SKalle Valo break; 960e705c121SKalle Valo } 961e705c121SKalle Valo } 962e705c121SKalle Valo 963e705c121SKalle Valo monitor: 96491c28b83SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && trans->dbg.fw_mon[0].size) { 965e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 96691c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 96791c28b83SShahar S Matityahu dest->base_shift); 9686e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 969e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97091c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 97191c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size - 256) >> 97262d7476dSEmmanuel Grumbach dest->end_shift); 97362d7476dSEmmanuel Grumbach else 97462d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97591c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 97691c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size) >> 97762d7476dSEmmanuel Grumbach dest->end_shift); 978e705c121SKalle Valo } 979e705c121SKalle Valo } 980e705c121SKalle Valo 981e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 982e705c121SKalle Valo const struct fw_img *image) 983e705c121SKalle Valo { 984e705c121SKalle Valo int ret = 0; 985e705c121SKalle Valo int first_ucode_section; 986e705c121SKalle Valo 987e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 988e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 989e705c121SKalle Valo 990e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 991e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 992e705c121SKalle Valo if (ret) 993e705c121SKalle Valo return ret; 994e705c121SKalle Valo 995e705c121SKalle Valo if (image->is_dual_cpus) { 996e705c121SKalle Valo /* set CPU2 header address */ 997e705c121SKalle Valo iwl_write_prph(trans, 998e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 999e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1000e705c121SKalle Valo 1001e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1002e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1003e705c121SKalle Valo &first_ucode_section); 1004e705c121SKalle Valo if (ret) 1005e705c121SKalle Valo return ret; 1006e705c121SKalle Valo } 1007e705c121SKalle Valo 1008e705c121SKalle Valo /* supported for 7000 only for the moment */ 1009e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1010e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1011e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1012e705c121SKalle Valo 101391c28b83SShahar S Matityahu if (trans->dbg.fw_mon[0].size) { 1014e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 101591c28b83SShahar S Matityahu trans->dbg.fw_mon[0].physical >> 4); 1016e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 101791c28b83SShahar S Matityahu (trans->dbg.fw_mon[0].physical + 101891c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size) >> 4); 1019e705c121SKalle Valo } 10207a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1021e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1022e705c121SKalle Valo } 1023e705c121SKalle Valo 10242aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10252aabdbdcSEmmanuel Grumbach 1026e705c121SKalle Valo /* release CPU reset */ 1027e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1028e705c121SKalle Valo 1029e705c121SKalle Valo return 0; 1030e705c121SKalle Valo } 1031e705c121SKalle Valo 1032e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1033e705c121SKalle Valo const struct fw_img *image) 1034e705c121SKalle Valo { 1035e705c121SKalle Valo int ret = 0; 1036e705c121SKalle Valo int first_ucode_section; 1037e705c121SKalle Valo 1038e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1039e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1040e705c121SKalle Valo 10417a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1042e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1043e705c121SKalle Valo 104482ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 104582ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 104682ea7966SSara Sharon 104782ea7966SSara Sharon /* 104882ea7966SSara Sharon * Set default value. On resume reading the values that were 104982ea7966SSara Sharon * zeored can provide debug data on the resume flow. 105082ea7966SSara Sharon * This is for debugging only and has no functional impact. 105182ea7966SSara Sharon */ 105282ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 105382ea7966SSara Sharon 1054e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1055e705c121SKalle Valo /* release CPU reset */ 1056e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1057e705c121SKalle Valo 1058e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1059e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1060e705c121SKalle Valo &first_ucode_section); 1061e705c121SKalle Valo if (ret) 1062e705c121SKalle Valo return ret; 1063e705c121SKalle Valo 1064e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1065e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1066e705c121SKalle Valo &first_ucode_section); 1067e705c121SKalle Valo } 1068e705c121SKalle Valo 10699ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1070727c02dfSSara Sharon { 1071326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1072727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1073326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1074326477e4SJohannes Berg bool report; 1075727c02dfSSara Sharon 1076326477e4SJohannes Berg if (hw_rfkill) { 1077326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1078326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1079326477e4SJohannes Berg } else { 1080326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1081326477e4SJohannes Berg if (trans_pcie->opmode_down) 1082326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083326477e4SJohannes Berg } 1084727c02dfSSara Sharon 1085326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1086326477e4SJohannes Berg 1087326477e4SJohannes Berg if (prev != report) 1088326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1089727c02dfSSara Sharon 1090727c02dfSSara Sharon return hw_rfkill; 1091727c02dfSSara Sharon } 1092727c02dfSSara Sharon 10937ca00409SHaim Dreyfuss struct iwl_causes_list { 10947ca00409SHaim Dreyfuss u32 cause_num; 10957ca00409SHaim Dreyfuss u32 mask_reg; 10967ca00409SHaim Dreyfuss u8 addr; 10977ca00409SHaim Dreyfuss }; 10987ca00409SHaim Dreyfuss 10997ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11007ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11017ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11027ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11037ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11047ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11057ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1106ff911dcaSShaul Triebitz {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 11077ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11087ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11097ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11107ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11117ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11127ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11137ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11147ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11157ca00409SHaim Dreyfuss }; 11167ca00409SHaim Dreyfuss 11179b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11189b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11199b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11209b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11219b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11229b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11239b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11249b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11259b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11269b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11279b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11289b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11299b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11309b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11319b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11329b58419eSGolan Ben Ami }; 11339b58419eSGolan Ben Ami 11347ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11357ca00409SHaim Dreyfuss { 11367ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11377ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11389b58419eSGolan Ben Ami int i, arr_size = 1139ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11409b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11417ca00409SHaim Dreyfuss 11427ca00409SHaim Dreyfuss /* 11437ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11447ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11457ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11467ca00409SHaim Dreyfuss */ 11479b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11489b58419eSGolan Ben Ami struct iwl_causes_list *causes = 1149ff911dcaSShaul Triebitz (trans->cfg->device_family != IWL_DEVICE_FAMILY_22560) ? 11509b58419eSGolan Ben Ami causes_list : causes_list_v2; 11519b58419eSGolan Ben Ami 11529b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11539b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11549b58419eSGolan Ben Ami causes[i].cause_num); 11557ca00409SHaim Dreyfuss } 11567ca00409SHaim Dreyfuss } 11577ca00409SHaim Dreyfuss 11587ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11597ca00409SHaim Dreyfuss { 11607ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11617ca00409SHaim Dreyfuss u32 offset = 11627ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11637ca00409SHaim Dreyfuss u32 val, idx; 11647ca00409SHaim Dreyfuss 11657ca00409SHaim Dreyfuss /* 11667ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11677ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11687ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11697ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11707ca00409SHaim Dreyfuss */ 11717ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11727ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11737ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11747ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11757ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11767ca00409SHaim Dreyfuss } 11777ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11787ca00409SHaim Dreyfuss 11797ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11807ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11817ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11827ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11837ca00409SHaim Dreyfuss 11847ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11857ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11867ca00409SHaim Dreyfuss } 11877ca00409SHaim Dreyfuss 118877c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11897ca00409SHaim Dreyfuss { 11907ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11917ca00409SHaim Dreyfuss 11927ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1193d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1194d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1195ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11967ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11977ca00409SHaim Dreyfuss return; 11987ca00409SHaim Dreyfuss } 1199d7270d61SHaim Dreyfuss /* 1200d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1201d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1202d7270d61SHaim Dreyfuss * prph. 1203d7270d61SHaim Dreyfuss */ 1204d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1205ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12067ca00409SHaim Dreyfuss 12077ca00409SHaim Dreyfuss /* 12087ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12097ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12107ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12117ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12127ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12137ca00409SHaim Dreyfuss */ 12147ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12157ca00409SHaim Dreyfuss 12167ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 121783730058SHaim Dreyfuss } 12187ca00409SHaim Dreyfuss 121983730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122083730058SHaim Dreyfuss { 122183730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122283730058SHaim Dreyfuss 122383730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122483730058SHaim Dreyfuss 122583730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 122683730058SHaim Dreyfuss return; 122783730058SHaim Dreyfuss 122883730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12297ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123083730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12317ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12327ca00409SHaim Dreyfuss } 12337ca00409SHaim Dreyfuss 1234e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1235e705c121SKalle Valo { 1236e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237e705c121SKalle Valo 1238e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1239e705c121SKalle Valo 1240e705c121SKalle Valo if (trans_pcie->is_down) 1241e705c121SKalle Valo return; 1242e705c121SKalle Valo 1243e705c121SKalle Valo trans_pcie->is_down = true; 1244e705c121SKalle Valo 1245e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1246e705c121SKalle Valo iwl_disable_interrupts(trans); 1247e705c121SKalle Valo 1248e705c121SKalle Valo /* device going down, Stop using ICT table */ 1249e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1250e705c121SKalle Valo 1251e705c121SKalle Valo /* 1252e705c121SKalle Valo * If a HW restart happens during firmware loading, 1253e705c121SKalle Valo * then the firmware loading might call this function 1254e705c121SKalle Valo * and later it might be called again due to the 1255e705c121SKalle Valo * restart. So don't process again if the device is 1256e705c121SKalle Valo * already dead. 1257e705c121SKalle Valo */ 1258e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1259a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1260a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1261e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1262e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1263e705c121SKalle Valo 1264e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1265e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1266e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1267e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1268e705c121SKalle Valo udelay(5); 1269e705c121SKalle Valo } 1270e705c121SKalle Valo } 1271e705c121SKalle Valo 1272e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1273e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1274a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1275e705c121SKalle Valo 1276e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1277e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1278e705c121SKalle Valo 1279870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1280e705c121SKalle Valo 1281e705c121SKalle Valo /* 1282f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1283f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1284f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1285f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1286f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1287f4a1f04aSGolan Ben Ami */ 1288f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1289f4a1f04aSGolan Ben Ami 1290f4a1f04aSGolan Ben Ami /* 1291e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1292e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1293e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1294e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1295e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1296e705c121SKalle Valo */ 1297e705c121SKalle Valo iwl_disable_interrupts(trans); 1298e705c121SKalle Valo 1299e705c121SKalle Valo /* clear all status bits */ 1300e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1301e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1302e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1303e705c121SKalle Valo 1304e705c121SKalle Valo /* 1305e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1306e705c121SKalle Valo * interrupt 1307e705c121SKalle Valo */ 1308e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1309e705c121SKalle Valo 1310a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1311e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1312e705c121SKalle Valo } 1313e705c121SKalle Valo 1314eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13152e5d4a8fSHaim Dreyfuss { 13162e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13172e5d4a8fSHaim Dreyfuss 13182e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13192e5d4a8fSHaim Dreyfuss int i; 13202e5d4a8fSHaim Dreyfuss 1321496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13222e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13232e5d4a8fSHaim Dreyfuss } else { 13242e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13252e5d4a8fSHaim Dreyfuss } 13262e5d4a8fSHaim Dreyfuss } 13272e5d4a8fSHaim Dreyfuss 1328a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1329a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1330a6bd005fSEmmanuel Grumbach { 1331a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1332a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1333a6bd005fSEmmanuel Grumbach int ret; 1334a6bd005fSEmmanuel Grumbach 1335a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1336a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1337a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1338a6bd005fSEmmanuel Grumbach ret = -EIO; 1339a6bd005fSEmmanuel Grumbach goto out; 1340a6bd005fSEmmanuel Grumbach } 1341a6bd005fSEmmanuel Grumbach 1342a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1343a6bd005fSEmmanuel Grumbach 1344a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1345a6bd005fSEmmanuel Grumbach 1346a6bd005fSEmmanuel Grumbach /* 1347a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1348a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1349a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1350a6bd005fSEmmanuel Grumbach */ 1351a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1352a6bd005fSEmmanuel Grumbach 1353a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13542e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1355a6bd005fSEmmanuel Grumbach 1356a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1357a6bd005fSEmmanuel Grumbach 1358a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13599ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1360a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1361a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1362a6bd005fSEmmanuel Grumbach goto out; 1363a6bd005fSEmmanuel Grumbach } 1364a6bd005fSEmmanuel Grumbach 1365a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1366a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1367a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1368a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136920aa99bbSAnton Protopopov ret = -EIO; 1370a6bd005fSEmmanuel Grumbach goto out; 1371a6bd005fSEmmanuel Grumbach } 1372a6bd005fSEmmanuel Grumbach 1373a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1374a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1375a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1376a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1377a6bd005fSEmmanuel Grumbach 1378a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1379a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1382a6bd005fSEmmanuel Grumbach if (ret) { 1383a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1384a6bd005fSEmmanuel Grumbach goto out; 1385a6bd005fSEmmanuel Grumbach } 1386a6bd005fSEmmanuel Grumbach 1387a6bd005fSEmmanuel Grumbach /* 1388a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1389a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1390a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1391a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1392a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1393a6bd005fSEmmanuel Grumbach */ 1394a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1395a6bd005fSEmmanuel Grumbach 1396a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1397a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1398a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1399a6bd005fSEmmanuel Grumbach 1400a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 14016e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1402a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1403a6bd005fSEmmanuel Grumbach else 1404a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1405a6bd005fSEmmanuel Grumbach 1406a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14079ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1408a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1409a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1410a6bd005fSEmmanuel Grumbach 1411a6bd005fSEmmanuel Grumbach out: 1412a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1413a6bd005fSEmmanuel Grumbach return ret; 1414a6bd005fSEmmanuel Grumbach } 1415a6bd005fSEmmanuel Grumbach 1416a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1417a6bd005fSEmmanuel Grumbach { 1418a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1419a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1420a6bd005fSEmmanuel Grumbach } 1421a6bd005fSEmmanuel Grumbach 1422326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1423326477e4SJohannes Berg bool was_in_rfkill) 1424326477e4SJohannes Berg { 1425326477e4SJohannes Berg bool hw_rfkill; 1426326477e4SJohannes Berg 1427326477e4SJohannes Berg /* 1428326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1429326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1430326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1431326477e4SJohannes Berg * op_mode. 1432326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1433326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1434326477e4SJohannes Berg * notification without endless recursion. Under very rare 1435326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1436326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1437326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1438326477e4SJohannes Berg */ 1439326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1440326477e4SJohannes Berg if (hw_rfkill) { 1441326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1442326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1443326477e4SJohannes Berg } else { 1444326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1445326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1446326477e4SJohannes Berg } 1447326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1448326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1449326477e4SJohannes Berg } 1450326477e4SJohannes Berg 1451e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1452e705c121SKalle Valo { 1453e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1454326477e4SJohannes Berg bool was_in_rfkill; 1455e705c121SKalle Valo 1456e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1457326477e4SJohannes Berg trans_pcie->opmode_down = true; 1458326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1459e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1460326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1461e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1462e705c121SKalle Valo } 1463e705c121SKalle Valo 1464e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1465e705c121SKalle Valo { 1466e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1467e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1468e705c121SKalle Valo 1469e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1470e705c121SKalle Valo 1471326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1472326477e4SJohannes Berg state ? "disabled" : "enabled"); 147377c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 147477c09bc8SSara Sharon if (trans->cfg->gen2) 147577c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 147677c09bc8SSara Sharon else 1477e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1478e705c121SKalle Valo } 147977c09bc8SSara Sharon } 1480e705c121SKalle Valo 148123ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 148223ae6128SMatti Gottlieb bool reset) 1483e705c121SKalle Valo { 148423ae6128SMatti Gottlieb if (!reset) { 1485e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1486e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1487e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1488e705c121SKalle Valo } 1489e705c121SKalle Valo 1490e705c121SKalle Valo iwl_disable_interrupts(trans); 1491e705c121SKalle Valo 1492e705c121SKalle Valo /* 1493e705c121SKalle Valo * in testing mode, the host stays awake and the 1494e705c121SKalle Valo * hardware won't be reset (not even partially) 1495e705c121SKalle Valo */ 1496e705c121SKalle Valo if (test) 1497e705c121SKalle Valo return; 1498e705c121SKalle Valo 1499e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1500e705c121SKalle Valo 15012e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1502e705c121SKalle Valo 1503e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1504a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1505e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1506a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1507e705c121SKalle Valo 150823ae6128SMatti Gottlieb if (reset) { 1509e705c121SKalle Valo /* 1510e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1511e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1512e705c121SKalle Valo * to execute some invalid memory upon resume 1513e705c121SKalle Valo */ 1514e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1515e705c121SKalle Valo } 1516e705c121SKalle Valo 1517e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1518e705c121SKalle Valo } 1519e705c121SKalle Valo 1520e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1521e705c121SKalle Valo enum iwl_d3_status *status, 152223ae6128SMatti Gottlieb bool test, bool reset) 1523e705c121SKalle Valo { 1524d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1525e705c121SKalle Valo u32 val; 1526e705c121SKalle Valo int ret; 1527e705c121SKalle Valo 1528e705c121SKalle Valo if (test) { 1529e705c121SKalle Valo iwl_enable_interrupts(trans); 1530e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1531e705c121SKalle Valo return 0; 1532e705c121SKalle Valo } 1533e705c121SKalle Valo 1534a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1535a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1536e705c121SKalle Valo 1537c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 1538c96b5eecSJohannes Berg if (ret) 1539e705c121SKalle Valo return ret; 1540e705c121SKalle Valo 1541f98ad635SEmmanuel Grumbach /* 1542f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1543f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1544f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1545f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1546f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1547f98ad635SEmmanuel Grumbach */ 1548f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1549f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1550f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1551f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1552f98ad635SEmmanuel Grumbach 1553e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1554e705c121SKalle Valo 155523ae6128SMatti Gottlieb if (!reset) { 1556e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1557a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1558e705c121SKalle Valo } else { 1559e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1560e705c121SKalle Valo 1561e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1562e705c121SKalle Valo if (ret) { 1563e705c121SKalle Valo IWL_ERR(trans, 1564e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1565e705c121SKalle Valo return ret; 1566e705c121SKalle Valo } 1567e705c121SKalle Valo } 1568e705c121SKalle Valo 156982ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1570ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 157182ea7966SSara Sharon 1572e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1573e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1574e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1575e705c121SKalle Valo else 1576e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1577e705c121SKalle Valo 1578e705c121SKalle Valo return 0; 1579e705c121SKalle Valo } 1580e705c121SKalle Valo 15812e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15822e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 15832e5d4a8fSHaim Dreyfuss { 15842e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1585ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15862e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15872e5d4a8fSHaim Dreyfuss 158806f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 158906f4b081SSara Sharon goto enable_msi; 159006f4b081SSara Sharon 1591ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 159206f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15932e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15942e5d4a8fSHaim Dreyfuss 159506f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15962e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 159706f4b081SSara Sharon max_irqs); 159806f4b081SSara Sharon if (num_irqs < 0) { 1599496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 160006f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 160106f4b081SSara Sharon num_irqs); 160206f4b081SSara Sharon goto enable_msi; 1603496d83caSHaim Dreyfuss } 160406f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1605496d83caSHaim Dreyfuss 16062e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 160706f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 160806f4b081SSara Sharon num_irqs); 160906f4b081SSara Sharon 1610496d83caSHaim Dreyfuss /* 161106f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 161206f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1613496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1614496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1615496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1616496d83caSHaim Dreyfuss */ 1617ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 161806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1619496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1620496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1621ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 162206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1623496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1624496d83caSHaim Dreyfuss } else { 162506f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1626496d83caSHaim Dreyfuss } 1627ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16282e5d4a8fSHaim Dreyfuss 162906f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1630496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16312e5d4a8fSHaim Dreyfuss return; 16322e5d4a8fSHaim Dreyfuss 163306f4b081SSara Sharon enable_msi: 163406f4b081SSara Sharon ret = pci_enable_msi(pdev); 163506f4b081SSara Sharon if (ret) { 163606f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16372e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16382e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16392e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16402e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16412e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16422e5d4a8fSHaim Dreyfuss } 16432e5d4a8fSHaim Dreyfuss } 16442e5d4a8fSHaim Dreyfuss } 16452e5d4a8fSHaim Dreyfuss 16467c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16477c8d91ebSHaim Dreyfuss { 16487c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16497c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16507c8d91ebSHaim Dreyfuss 16517c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16527c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16537c8d91ebSHaim Dreyfuss offset = 1 + i; 16547c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16557c8d91ebSHaim Dreyfuss /* 16567c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16577c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16587c8d91ebSHaim Dreyfuss */ 16597c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16607c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16617c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16627c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16637c8d91ebSHaim Dreyfuss if (ret) 16647c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16657c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16667c8d91ebSHaim Dreyfuss i); 16677c8d91ebSHaim Dreyfuss } 16687c8d91ebSHaim Dreyfuss } 16697c8d91ebSHaim Dreyfuss 16702e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16712e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16722e5d4a8fSHaim Dreyfuss { 1673496d83caSHaim Dreyfuss int i; 16742e5d4a8fSHaim Dreyfuss 1675496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16762e5d4a8fSHaim Dreyfuss int ret; 16775a41a86cSSharon Dvir struct msix_entry *msix_entry; 167864fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 167964fa3affSSharon Dvir 168064fa3affSSharon Dvir if (!qname) 168164fa3affSSharon Dvir return -ENOMEM; 16822e5d4a8fSHaim Dreyfuss 16835a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16845a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16855a41a86cSSharon Dvir msix_entry->vector, 16862e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1687496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16882e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16892e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16902e5d4a8fSHaim Dreyfuss IRQF_SHARED, 169164fa3affSSharon Dvir qname, 16925a41a86cSSharon Dvir msix_entry); 16932e5d4a8fSHaim Dreyfuss if (ret) { 16942e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16952e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16965a41a86cSSharon Dvir 16972e5d4a8fSHaim Dreyfuss return ret; 16982e5d4a8fSHaim Dreyfuss } 16992e5d4a8fSHaim Dreyfuss } 17007c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17012e5d4a8fSHaim Dreyfuss 17022e5d4a8fSHaim Dreyfuss return 0; 17032e5d4a8fSHaim Dreyfuss } 17042e5d4a8fSHaim Dreyfuss 170544f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 170644f61b5cSShahar S Matityahu { 170744f61b5cSShahar S Matityahu u32 hpm, wprot; 170844f61b5cSShahar S Matityahu 170944f61b5cSShahar S Matityahu switch (trans->cfg->device_family) { 171044f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 171144f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 171244f61b5cSShahar S Matityahu break; 171344f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 171444f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 171544f61b5cSShahar S Matityahu break; 171644f61b5cSShahar S Matityahu default: 171744f61b5cSShahar S Matityahu return 0; 171844f61b5cSShahar S Matityahu } 171944f61b5cSShahar S Matityahu 172044f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 172144f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 172244f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 172344f61b5cSShahar S Matityahu 172444f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 172544f61b5cSShahar S Matityahu IWL_ERR(trans, 172644f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 172744f61b5cSShahar S Matityahu return -EPERM; 172844f61b5cSShahar S Matityahu } 172944f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 173044f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 173144f61b5cSShahar S Matityahu } 173244f61b5cSShahar S Matityahu 173344f61b5cSShahar S Matityahu return 0; 173444f61b5cSShahar S Matityahu } 173544f61b5cSShahar S Matityahu 1736e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1737e705c121SKalle Valo { 1738e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1739e705c121SKalle Valo int err; 1740e705c121SKalle Valo 1741e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1742e705c121SKalle Valo 1743e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1744e705c121SKalle Valo if (err) { 1745e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1746e705c121SKalle Valo return err; 1747e705c121SKalle Valo } 1748e705c121SKalle Valo 174944f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 175044f61b5cSShahar S Matityahu if (err) 175144f61b5cSShahar S Matityahu return err; 17528954e1ebSShahar S Matityahu 1753870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1754e705c121SKalle Valo 175552b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 175652b6e168SEmmanuel Grumbach if (err) 175752b6e168SEmmanuel Grumbach return err; 1758e705c121SKalle Valo 17592e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 176083730058SHaim Dreyfuss 1761e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1762e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1763e705c121SKalle Valo 1764326477e4SJohannes Berg trans_pcie->opmode_down = false; 1765326477e4SJohannes Berg 1766e705c121SKalle Valo /* Set is_down to false here so that...*/ 1767e705c121SKalle Valo trans_pcie->is_down = false; 1768e705c121SKalle Valo 1769e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17709ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1771e705c121SKalle Valo 17724cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 17734cbb8e50SLuciano Coelho if (low_power) 17744cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 17754cbb8e50SLuciano Coelho 1776e705c121SKalle Valo return 0; 1777e705c121SKalle Valo } 1778e705c121SKalle Valo 1779e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1780e705c121SKalle Valo { 1781e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1782e705c121SKalle Valo int ret; 1783e705c121SKalle Valo 1784e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1785e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1786e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1787e705c121SKalle Valo 1788e705c121SKalle Valo return ret; 1789e705c121SKalle Valo } 1790e705c121SKalle Valo 1791e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1792e705c121SKalle Valo { 1793e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1794e705c121SKalle Valo 1795e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1796e705c121SKalle Valo 1797e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1798e705c121SKalle Valo iwl_disable_interrupts(trans); 1799e705c121SKalle Valo 1800e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1801e705c121SKalle Valo 1802e705c121SKalle Valo iwl_disable_interrupts(trans); 1803e705c121SKalle Valo 1804e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1805e705c121SKalle Valo 1806e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1807e705c121SKalle Valo 18082e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1809e705c121SKalle Valo } 1810e705c121SKalle Valo 1811e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1812e705c121SKalle Valo { 1813e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1814e705c121SKalle Valo } 1815e705c121SKalle Valo 1816e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1817e705c121SKalle Valo { 1818e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1819e705c121SKalle Valo } 1820e705c121SKalle Valo 1821e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1822e705c121SKalle Valo { 1823e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1824e705c121SKalle Valo } 1825e705c121SKalle Valo 182684fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 182784fb372cSSara Sharon { 182884fb372cSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 182984fb372cSSara Sharon return 0x00FFFFFF; 183084fb372cSSara Sharon else 183184fb372cSSara Sharon return 0x000FFFFF; 183284fb372cSSara Sharon } 183384fb372cSSara Sharon 1834e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1835e705c121SKalle Valo { 183684fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 183784fb372cSSara Sharon 1838e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 183984fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1840e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1841e705c121SKalle Valo } 1842e705c121SKalle Valo 1843e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1844e705c121SKalle Valo u32 val) 1845e705c121SKalle Valo { 184684fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 184784fb372cSSara Sharon 1848e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 184984fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1850e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1851e705c121SKalle Valo } 1852e705c121SKalle Valo 1853e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1854e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1855e705c121SKalle Valo { 1856e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1857e705c121SKalle Valo 1858e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1859e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1860e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1861e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1862e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1863e705c121SKalle Valo else 1864e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1865e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1866e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1867e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1868e705c121SKalle Valo 18696c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18706c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18716c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1872e705c121SKalle Valo 1873e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1874e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 187541837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1876e705c121SKalle Valo 187721cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 187821cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 187921cb3222SJohannes Berg 188039bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 188139bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 188239bdb17eSSharon Dvir 1883e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1884e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1885e705c121SKalle Valo * As this function may be called again in some corner cases don't 1886e705c121SKalle Valo * do anything if NAPI was already initialized. 1887e705c121SKalle Valo */ 1888bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1889e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1890e705c121SKalle Valo } 1891e705c121SKalle Valo 1892e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1893e705c121SKalle Valo { 1894e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18956eb5e529SEmmanuel Grumbach int i; 1896e705c121SKalle Valo 18972e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1898e705c121SKalle Valo 189913a3a390SSara Sharon if (trans->cfg->gen2) 190013a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 190113a3a390SSara Sharon else 1902e705c121SKalle Valo iwl_pcie_tx_free(trans); 1903e705c121SKalle Valo iwl_pcie_rx_free(trans); 1904e705c121SKalle Valo 190510a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 190610a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 190710a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 190810a54d81SLuca Coelho } 190910a54d81SLuca Coelho 19102e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19117c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19127c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19137c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19147c8d91ebSHaim Dreyfuss NULL); 19157c8d91ebSHaim Dreyfuss } 19162e5d4a8fSHaim Dreyfuss 19172e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19182e5d4a8fSHaim Dreyfuss } else { 1919e705c121SKalle Valo iwl_pcie_free_ict(trans); 19202e5d4a8fSHaim Dreyfuss } 1921e705c121SKalle Valo 1922e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1923e705c121SKalle Valo 19246eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19256eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19266eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19276eb5e529SEmmanuel Grumbach 19286eb5e529SEmmanuel Grumbach if (p->page) 19296eb5e529SEmmanuel Grumbach __free_page(p->page); 19306eb5e529SEmmanuel Grumbach } 19316eb5e529SEmmanuel Grumbach 19326eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1933a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1934e705c121SKalle Valo iwl_trans_free(trans); 1935e705c121SKalle Valo } 1936e705c121SKalle Valo 1937e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1938e705c121SKalle Valo { 1939e705c121SKalle Valo if (state) 1940e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1941e705c121SKalle Valo else 1942e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1943e705c121SKalle Valo } 1944e705c121SKalle Valo 194549564a80SLuca Coelho struct iwl_trans_pcie_removal { 194649564a80SLuca Coelho struct pci_dev *pdev; 194749564a80SLuca Coelho struct work_struct work; 194849564a80SLuca Coelho }; 194949564a80SLuca Coelho 195049564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 195149564a80SLuca Coelho { 195249564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 195349564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 195449564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1955aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 195649564a80SLuca Coelho 195749564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 195849564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 195949564a80SLuca Coelho pci_lock_rescan_remove(); 196049564a80SLuca Coelho pci_dev_put(pdev); 196149564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 196249564a80SLuca Coelho pci_unlock_rescan_remove(); 196349564a80SLuca Coelho 196449564a80SLuca Coelho kfree(removal); 196549564a80SLuca Coelho module_put(THIS_MODULE); 196649564a80SLuca Coelho } 196749564a80SLuca Coelho 196823ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1969e705c121SKalle Valo unsigned long *flags) 1970e705c121SKalle Valo { 1971e705c121SKalle Valo int ret; 1972e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1973e705c121SKalle Valo 1974e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1975e705c121SKalle Valo 1976e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1977e705c121SKalle Valo goto out; 1978e705c121SKalle Valo 1979e705c121SKalle Valo /* this bit wakes up the NIC */ 1980e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1981a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19826e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1983e705c121SKalle Valo udelay(2); 1984e705c121SKalle Valo 1985e705c121SKalle Valo /* 1986e705c121SKalle Valo * These bits say the device is running, and should keep running for 1987e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1988e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1989fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1990fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1991e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1992e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1993e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1994e705c121SKalle Valo * to keep device from sleeping. 1995e705c121SKalle Valo * 1996e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1997e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1998fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 1999fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2000fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2001e705c121SKalle Valo * 2002e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2003e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2004e705c121SKalle Valo */ 2005e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2006a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 2007a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2008e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2009e705c121SKalle Valo if (unlikely(ret < 0)) { 201049564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 201149564a80SLuca Coelho 2012e705c121SKalle Valo WARN_ONCE(1, 2013e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 201449564a80SLuca Coelho cntrl); 201549564a80SLuca Coelho 201649564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 201749564a80SLuca Coelho 201849564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 201949564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 202049564a80SLuca Coelho 2021f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 202249564a80SLuca Coelho goto err; 202349564a80SLuca Coelho 202449564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 202549564a80SLuca Coelho 202649564a80SLuca Coelho /* 202749564a80SLuca Coelho * get a module reference to avoid doing this 202849564a80SLuca Coelho * while unloading anyway and to avoid 202949564a80SLuca Coelho * scheduling a work with code that's being 203049564a80SLuca Coelho * removed. 203149564a80SLuca Coelho */ 203249564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 203349564a80SLuca Coelho IWL_ERR(trans, 203449564a80SLuca Coelho "Module is being unloaded - abort\n"); 203549564a80SLuca Coelho goto err; 203649564a80SLuca Coelho } 203749564a80SLuca Coelho 203849564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 203949564a80SLuca Coelho if (!removal) { 204049564a80SLuca Coelho module_put(THIS_MODULE); 204149564a80SLuca Coelho goto err; 204249564a80SLuca Coelho } 204349564a80SLuca Coelho /* 204449564a80SLuca Coelho * we don't need to clear this flag, because 204549564a80SLuca Coelho * the trans will be freed and reallocated. 204649564a80SLuca Coelho */ 2047f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 204849564a80SLuca Coelho 204949564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 205049564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 205149564a80SLuca Coelho pci_dev_get(removal->pdev); 205249564a80SLuca Coelho schedule_work(&removal->work); 205349564a80SLuca Coelho } else { 205449564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 205549564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 205649564a80SLuca Coelho } 205749564a80SLuca Coelho 205849564a80SLuca Coelho err: 2059e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2060e705c121SKalle Valo return false; 2061e705c121SKalle Valo } 2062e705c121SKalle Valo 2063e705c121SKalle Valo out: 2064e705c121SKalle Valo /* 2065e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2066e705c121SKalle Valo * track nic_access anyway. 2067e705c121SKalle Valo */ 2068e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2069e705c121SKalle Valo return true; 2070e705c121SKalle Valo } 2071e705c121SKalle Valo 2072e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2073e705c121SKalle Valo unsigned long *flags) 2074e705c121SKalle Valo { 2075e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2076e705c121SKalle Valo 2077e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2078e705c121SKalle Valo 2079e705c121SKalle Valo /* 2080e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2081e705c121SKalle Valo * track nic_access anyway. 2082e705c121SKalle Valo */ 2083e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2084e705c121SKalle Valo 2085e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2086e705c121SKalle Valo goto out; 2087e705c121SKalle Valo 2088e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2089a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2090e705c121SKalle Valo /* 2091e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2092e705c121SKalle Valo * any previous writes, but we need the write that clears the 2093e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2094e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2095e705c121SKalle Valo */ 2096e705c121SKalle Valo out: 2097e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2098e705c121SKalle Valo } 2099e705c121SKalle Valo 2100e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2101e705c121SKalle Valo void *buf, int dwords) 2102e705c121SKalle Valo { 2103e705c121SKalle Valo unsigned long flags; 2104e705c121SKalle Valo int offs, ret = 0; 2105e705c121SKalle Valo u32 *vals = buf; 2106e705c121SKalle Valo 210723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2108e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2109e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2110e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2111e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2112e705c121SKalle Valo } else { 2113e705c121SKalle Valo ret = -EBUSY; 2114e705c121SKalle Valo } 2115e705c121SKalle Valo return ret; 2116e705c121SKalle Valo } 2117e705c121SKalle Valo 2118e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2119e705c121SKalle Valo const void *buf, int dwords) 2120e705c121SKalle Valo { 2121e705c121SKalle Valo unsigned long flags; 2122e705c121SKalle Valo int offs, ret = 0; 2123e705c121SKalle Valo const u32 *vals = buf; 2124e705c121SKalle Valo 212523ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2126e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2127e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2128e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2129e705c121SKalle Valo vals ? vals[offs] : 0); 2130e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2131e705c121SKalle Valo } else { 2132e705c121SKalle Valo ret = -EBUSY; 2133e705c121SKalle Valo } 2134e705c121SKalle Valo return ret; 2135e705c121SKalle Valo } 2136e705c121SKalle Valo 2137e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2138e705c121SKalle Valo unsigned long txqs, 2139e705c121SKalle Valo bool freeze) 2140e705c121SKalle Valo { 2141e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2142e705c121SKalle Valo int queue; 2143e705c121SKalle Valo 2144e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2145b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2146e705c121SKalle Valo unsigned long now; 2147e705c121SKalle Valo 2148e705c121SKalle Valo spin_lock_bh(&txq->lock); 2149e705c121SKalle Valo 2150e705c121SKalle Valo now = jiffies; 2151e705c121SKalle Valo 2152e705c121SKalle Valo if (txq->frozen == freeze) 2153e705c121SKalle Valo goto next_queue; 2154e705c121SKalle Valo 2155e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2156e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2157e705c121SKalle Valo 2158e705c121SKalle Valo txq->frozen = freeze; 2159e705c121SKalle Valo 2160bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2161e705c121SKalle Valo goto next_queue; 2162e705c121SKalle Valo 2163e705c121SKalle Valo if (freeze) { 2164e705c121SKalle Valo if (unlikely(time_after(now, 2165e705c121SKalle Valo txq->stuck_timer.expires))) { 2166e705c121SKalle Valo /* 2167e705c121SKalle Valo * The timer should have fired, maybe it is 2168e705c121SKalle Valo * spinning right now on the lock. 2169e705c121SKalle Valo */ 2170e705c121SKalle Valo goto next_queue; 2171e705c121SKalle Valo } 2172e705c121SKalle Valo /* remember how long until the timer fires */ 2173e705c121SKalle Valo txq->frozen_expiry_remainder = 2174e705c121SKalle Valo txq->stuck_timer.expires - now; 2175e705c121SKalle Valo del_timer(&txq->stuck_timer); 2176e705c121SKalle Valo goto next_queue; 2177e705c121SKalle Valo } 2178e705c121SKalle Valo 2179e705c121SKalle Valo /* 2180e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2181e705c121SKalle Valo * remainder before it froze 2182e705c121SKalle Valo */ 2183e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2184e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2185e705c121SKalle Valo 2186e705c121SKalle Valo next_queue: 2187e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2188e705c121SKalle Valo } 2189e705c121SKalle Valo } 2190e705c121SKalle Valo 21910cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21920cd58eaaSEmmanuel Grumbach { 21930cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21940cd58eaaSEmmanuel Grumbach int i; 21950cd58eaaSEmmanuel Grumbach 21960cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2197b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 21980cd58eaaSEmmanuel Grumbach 21990cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 22000cd58eaaSEmmanuel Grumbach continue; 22010cd58eaaSEmmanuel Grumbach 22020cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22030cd58eaaSEmmanuel Grumbach 22040cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22050cd58eaaSEmmanuel Grumbach txq->block--; 22060cd58eaaSEmmanuel Grumbach if (!txq->block) { 22070cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2208bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22090cd58eaaSEmmanuel Grumbach } 22100cd58eaaSEmmanuel Grumbach } else if (block) { 22110cd58eaaSEmmanuel Grumbach txq->block++; 22120cd58eaaSEmmanuel Grumbach } 22130cd58eaaSEmmanuel Grumbach 22140cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22150cd58eaaSEmmanuel Grumbach } 22160cd58eaaSEmmanuel Grumbach } 22170cd58eaaSEmmanuel Grumbach 2218e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2219e705c121SKalle Valo 222038398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 222138398efbSSara Sharon { 2222afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2223afb84431SEmmanuel Grumbach u32 status; 2224afb84431SEmmanuel Grumbach bool active; 2225afb84431SEmmanuel Grumbach u8 fifo; 222638398efbSSara Sharon 2227afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2228afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2229bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2230ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2231ae79785fSSara Sharon return; 2232afb84431SEmmanuel Grumbach } 2233ae79785fSSara Sharon 2234afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2235afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2236afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 223738398efbSSara Sharon 223838398efbSSara Sharon IWL_ERR(trans, 2239afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2240afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2241afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2242afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2243afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 22447b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2245afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 22467b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2247afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 224838398efbSSara Sharon } 224938398efbSSara Sharon 225092536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 225192536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 225292536c96SSara Sharon { 225392536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 225492536c96SSara Sharon 225592536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 225692536c96SSara Sharon return -EINVAL; 225792536c96SSara Sharon 225892536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 225992536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 226092536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 226192536c96SSara Sharon data->fr_bd_wid = 0; 226292536c96SSara Sharon 226392536c96SSara Sharon return 0; 226492536c96SSara Sharon } 226592536c96SSara Sharon 2266d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2267e705c121SKalle Valo { 2268e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2269e705c121SKalle Valo struct iwl_txq *txq; 2270e705c121SKalle Valo unsigned long now = jiffies; 22712ae48edcSSara Sharon bool overflow_tx; 2272e705c121SKalle Valo u8 wr_ptr; 2273e705c121SKalle Valo 22742b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2275f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2276f60c9e59SEmmanuel Grumbach return -ENODEV; 22772b3fae66SMatt Chen 2278d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2279d6d517b7SSara Sharon return -EINVAL; 2280e705c121SKalle Valo 2281d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2282d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22832ae48edcSSara Sharon 22842ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22852ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22862ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22872ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22882ae48edcSSara Sharon 22896aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2290e705c121SKalle Valo 22912ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22922ae48edcSSara Sharon overflow_tx) && 2293e705c121SKalle Valo !time_after(jiffies, 2294e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22956aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2296e705c121SKalle Valo 22972ae48edcSSara Sharon /* 22982ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22992ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23002ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23012ae48edcSSara Sharon */ 23022ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2303e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2304e705c121SKalle Valo wr_ptr, write_ptr)) 2305e705c121SKalle Valo return -ETIMEDOUT; 23062ae48edcSSara Sharon wr_ptr = write_ptr; 23072ae48edcSSara Sharon 2308192185d6SJohannes Berg usleep_range(1000, 2000); 23092ae48edcSSara Sharon 23102ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23112ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23122ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23132ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2314e705c121SKalle Valo } 2315e705c121SKalle Valo 2316bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2317e705c121SKalle Valo IWL_ERR(trans, 2318d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2319d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2320d6d517b7SSara Sharon return -ETIMEDOUT; 2321e705c121SKalle Valo } 2322e705c121SKalle Valo 2323d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2324d6d517b7SSara Sharon 2325d6d517b7SSara Sharon return 0; 2326d6d517b7SSara Sharon } 2327d6d517b7SSara Sharon 2328d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2329d6d517b7SSara Sharon { 2330d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2331d6d517b7SSara Sharon int cnt; 2332d6d517b7SSara Sharon int ret = 0; 2333d6d517b7SSara Sharon 2334d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2335d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2336d6d517b7SSara Sharon 2337d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2338d6d517b7SSara Sharon continue; 2339d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2340d6d517b7SSara Sharon continue; 2341d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2342d6d517b7SSara Sharon continue; 2343d6d517b7SSara Sharon 2344d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 234538398efbSSara Sharon if (ret) 2346d6d517b7SSara Sharon break; 2347d6d517b7SSara Sharon } 2348e705c121SKalle Valo 2349e705c121SKalle Valo return ret; 2350e705c121SKalle Valo } 2351e705c121SKalle Valo 2352e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2353e705c121SKalle Valo u32 mask, u32 value) 2354e705c121SKalle Valo { 2355e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2356e705c121SKalle Valo unsigned long flags; 2357e705c121SKalle Valo 2358e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2359e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2360e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2361e705c121SKalle Valo } 2362e705c121SKalle Valo 2363c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2364e705c121SKalle Valo { 2365e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2366e705c121SKalle Valo 2367e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2368e705c121SKalle Valo return; 2369e705c121SKalle Valo 2370b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 23715d93f3a2SLuca Coelho 23725d93f3a2SLuca Coelho #ifdef CONFIG_PM 23735d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23745d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23755d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2376e705c121SKalle Valo } 2377e705c121SKalle Valo 2378c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2379e705c121SKalle Valo { 2380e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2381e705c121SKalle Valo 2382e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2383e705c121SKalle Valo return; 2384e705c121SKalle Valo 2385b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2386b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2387b3ff1270SLuca Coelho 23885d93f3a2SLuca Coelho #ifdef CONFIG_PM 23895d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23905d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23915d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2392e705c121SKalle Valo } 2393e705c121SKalle Valo 2394e705c121SKalle Valo static const char *get_csr_string(int cmd) 2395e705c121SKalle Valo { 2396e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2397e705c121SKalle Valo switch (cmd) { 2398e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2399e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2400e705c121SKalle Valo IWL_CMD(CSR_INT); 2401e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2402e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2403e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2404e705c121SKalle Valo IWL_CMD(CSR_RESET); 2405e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2406e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2407e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2408e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2409e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2410e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2411e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2412e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2413e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2414e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2415e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2416e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2417e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2418e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2419e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2420e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2421e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2422e705c121SKalle Valo default: 2423e705c121SKalle Valo return "UNKNOWN"; 2424e705c121SKalle Valo } 2425e705c121SKalle Valo #undef IWL_CMD 2426e705c121SKalle Valo } 2427e705c121SKalle Valo 2428e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2429e705c121SKalle Valo { 2430e705c121SKalle Valo int i; 2431e705c121SKalle Valo static const u32 csr_tbl[] = { 2432e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2433e705c121SKalle Valo CSR_INT_COALESCING, 2434e705c121SKalle Valo CSR_INT, 2435e705c121SKalle Valo CSR_INT_MASK, 2436e705c121SKalle Valo CSR_FH_INT_STATUS, 2437e705c121SKalle Valo CSR_GPIO_IN, 2438e705c121SKalle Valo CSR_RESET, 2439e705c121SKalle Valo CSR_GP_CNTRL, 2440e705c121SKalle Valo CSR_HW_REV, 2441e705c121SKalle Valo CSR_EEPROM_REG, 2442e705c121SKalle Valo CSR_EEPROM_GP, 2443e705c121SKalle Valo CSR_OTP_GP_REG, 2444e705c121SKalle Valo CSR_GIO_REG, 2445e705c121SKalle Valo CSR_GP_UCODE_REG, 2446e705c121SKalle Valo CSR_GP_DRIVER_REG, 2447e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2448e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2449e705c121SKalle Valo CSR_LED_REG, 2450e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2451e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2452e705c121SKalle Valo CSR_ANA_PLL_CFG, 2453e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2454e705c121SKalle Valo CSR_HW_REV_WA_REG, 2455e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2456e705c121SKalle Valo }; 2457e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2458e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2459e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2460e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2461e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2462e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2463e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2464e705c121SKalle Valo } 2465e705c121SKalle Valo } 2466e705c121SKalle Valo 2467e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2468e705c121SKalle Valo /* create and remove of files */ 2469e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2470cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2471cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2472e705c121SKalle Valo } while (0) 2473e705c121SKalle Valo 2474e705c121SKalle Valo /* file operation */ 2475e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2476e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2477e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2478e705c121SKalle Valo .open = simple_open, \ 2479e705c121SKalle Valo .llseek = generic_file_llseek, \ 2480e705c121SKalle Valo }; 2481e705c121SKalle Valo 2482e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2483e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2484e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2485e705c121SKalle Valo .open = simple_open, \ 2486e705c121SKalle Valo .llseek = generic_file_llseek, \ 2487e705c121SKalle Valo }; 2488e705c121SKalle Valo 2489e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2490e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2491e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2492e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2493e705c121SKalle Valo .open = simple_open, \ 2494e705c121SKalle Valo .llseek = generic_file_llseek, \ 2495e705c121SKalle Valo }; 2496e705c121SKalle Valo 2497e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2498e705c121SKalle Valo char __user *user_buf, 2499e705c121SKalle Valo size_t count, loff_t *ppos) 2500e705c121SKalle Valo { 2501e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2502e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2503e705c121SKalle Valo struct iwl_txq *txq; 2504e705c121SKalle Valo char *buf; 2505e705c121SKalle Valo int pos = 0; 2506e705c121SKalle Valo int cnt; 2507e705c121SKalle Valo int ret; 2508e705c121SKalle Valo size_t bufsz; 2509e705c121SKalle Valo 2510e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2511e705c121SKalle Valo 2512b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2513e705c121SKalle Valo return -EAGAIN; 2514e705c121SKalle Valo 2515e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2516e705c121SKalle Valo if (!buf) 2517e705c121SKalle Valo return -ENOMEM; 2518e705c121SKalle Valo 2519e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2520b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2521e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2522e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2523bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2524e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2525e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2526e705c121SKalle Valo txq->need_update, txq->frozen, 2527e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2528e705c121SKalle Valo } 2529e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2530e705c121SKalle Valo kfree(buf); 2531e705c121SKalle Valo return ret; 2532e705c121SKalle Valo } 2533e705c121SKalle Valo 2534e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2535e705c121SKalle Valo char __user *user_buf, 2536e705c121SKalle Valo size_t count, loff_t *ppos) 2537e705c121SKalle Valo { 2538e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2539e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 254078485054SSara Sharon char *buf; 254178485054SSara Sharon int pos = 0, i, ret; 254278485054SSara Sharon size_t bufsz = sizeof(buf); 2543e705c121SKalle Valo 254478485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 254578485054SSara Sharon 254678485054SSara Sharon if (!trans_pcie->rxq) 254778485054SSara Sharon return -EAGAIN; 254878485054SSara Sharon 254978485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 255078485054SSara Sharon if (!buf) 255178485054SSara Sharon return -ENOMEM; 255278485054SSara Sharon 255378485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 255478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 255578485054SSara Sharon 255678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 255778485054SSara Sharon i); 255878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2559e705c121SKalle Valo rxq->read); 256078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2561e705c121SKalle Valo rxq->write); 256278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2563e705c121SKalle Valo rxq->write_actual); 256478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2565e705c121SKalle Valo rxq->need_update); 256678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2567e705c121SKalle Valo rxq->free_count); 2568e705c121SKalle Valo if (rxq->rb_stts) { 25690307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25700307c839SGolan Ben Ami rxq)); 257178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 257278485054SSara Sharon "\tclosed_rb_num: %u\n", 25730307c839SGolan Ben Ami r & 0x0FFF); 2574e705c121SKalle Valo } else { 2575e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 257678485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2577e705c121SKalle Valo } 257878485054SSara Sharon } 257978485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 258078485054SSara Sharon kfree(buf); 258178485054SSara Sharon 258278485054SSara Sharon return ret; 2583e705c121SKalle Valo } 2584e705c121SKalle Valo 2585e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2586e705c121SKalle Valo char __user *user_buf, 2587e705c121SKalle Valo size_t count, loff_t *ppos) 2588e705c121SKalle Valo { 2589e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2590e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2591e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2592e705c121SKalle Valo 2593e705c121SKalle Valo int pos = 0; 2594e705c121SKalle Valo char *buf; 2595e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2596e705c121SKalle Valo ssize_t ret; 2597e705c121SKalle Valo 2598e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2599e705c121SKalle Valo if (!buf) 2600e705c121SKalle Valo return -ENOMEM; 2601e705c121SKalle Valo 2602e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2603e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2604e705c121SKalle Valo 2605e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2606e705c121SKalle Valo isr_stats->hw); 2607e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2608e705c121SKalle Valo isr_stats->sw); 2609e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2610e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2611e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2612e705c121SKalle Valo isr_stats->err_code); 2613e705c121SKalle Valo } 2614e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2615e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2616e705c121SKalle Valo isr_stats->sch); 2617e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2618e705c121SKalle Valo isr_stats->alive); 2619e705c121SKalle Valo #endif 2620e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2621e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2622e705c121SKalle Valo 2623e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2624e705c121SKalle Valo isr_stats->ctkill); 2625e705c121SKalle Valo 2626e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2627e705c121SKalle Valo isr_stats->wakeup); 2628e705c121SKalle Valo 2629e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2630e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2631e705c121SKalle Valo 2632e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2633e705c121SKalle Valo isr_stats->tx); 2634e705c121SKalle Valo 2635e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2636e705c121SKalle Valo isr_stats->unhandled); 2637e705c121SKalle Valo 2638e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2639e705c121SKalle Valo kfree(buf); 2640e705c121SKalle Valo return ret; 2641e705c121SKalle Valo } 2642e705c121SKalle Valo 2643e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2644e705c121SKalle Valo const char __user *user_buf, 2645e705c121SKalle Valo size_t count, loff_t *ppos) 2646e705c121SKalle Valo { 2647e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2648e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2649e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2650e705c121SKalle Valo u32 reset_flag; 2651078f1131SJohannes Berg int ret; 2652e705c121SKalle Valo 2653078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2654078f1131SJohannes Berg if (ret) 2655078f1131SJohannes Berg return ret; 2656e705c121SKalle Valo if (reset_flag == 0) 2657e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2658e705c121SKalle Valo 2659e705c121SKalle Valo return count; 2660e705c121SKalle Valo } 2661e705c121SKalle Valo 2662e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2663e705c121SKalle Valo const char __user *user_buf, 2664e705c121SKalle Valo size_t count, loff_t *ppos) 2665e705c121SKalle Valo { 2666e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2667e705c121SKalle Valo 2668e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2669e705c121SKalle Valo 2670e705c121SKalle Valo return count; 2671e705c121SKalle Valo } 2672e705c121SKalle Valo 2673e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2674e705c121SKalle Valo char __user *user_buf, 2675e705c121SKalle Valo size_t count, loff_t *ppos) 2676e705c121SKalle Valo { 2677e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2678e705c121SKalle Valo char *buf = NULL; 2679e705c121SKalle Valo ssize_t ret; 2680e705c121SKalle Valo 2681e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2682e705c121SKalle Valo if (ret < 0) 2683e705c121SKalle Valo return ret; 2684e705c121SKalle Valo if (!buf) 2685e705c121SKalle Valo return -EINVAL; 2686e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2687e705c121SKalle Valo kfree(buf); 2688e705c121SKalle Valo return ret; 2689e705c121SKalle Valo } 2690e705c121SKalle Valo 2691fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2692fa4de7f7SJohannes Berg char __user *user_buf, 2693fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2694fa4de7f7SJohannes Berg { 2695fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2696fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2697fa4de7f7SJohannes Berg char buf[100]; 2698fa4de7f7SJohannes Berg int pos; 2699fa4de7f7SJohannes Berg 2700fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2701fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2702fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2703fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2704fa4de7f7SJohannes Berg 2705fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2706fa4de7f7SJohannes Berg } 2707fa4de7f7SJohannes Berg 2708fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2709fa4de7f7SJohannes Berg const char __user *user_buf, 2710fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2711fa4de7f7SJohannes Berg { 2712fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2713fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2714c5bf4fa1SJohannes Berg bool new_value; 2715fa4de7f7SJohannes Berg int ret; 2716fa4de7f7SJohannes Berg 2717c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2718fa4de7f7SJohannes Berg if (ret) 2719fa4de7f7SJohannes Berg return ret; 2720c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2721fa4de7f7SJohannes Berg return count; 2722fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2723c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2724c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2725fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2726fa4de7f7SJohannes Berg 2727fa4de7f7SJohannes Berg return count; 2728fa4de7f7SJohannes Berg } 2729fa4de7f7SJohannes Berg 2730f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2731f7805b33SLior Cohen struct file *file) 2732f7805b33SLior Cohen { 2733f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2734f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2735f7805b33SLior Cohen 273691c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 273791c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2738f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2739f7805b33SLior Cohen return -ENOENT; 2740f7805b33SLior Cohen } 2741f7805b33SLior Cohen 2742f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2743f7805b33SLior Cohen return -EBUSY; 2744f7805b33SLior Cohen 2745f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2746f7805b33SLior Cohen return simple_open(inode, file); 2747f7805b33SLior Cohen } 2748f7805b33SLior Cohen 2749f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2750f7805b33SLior Cohen struct file *file) 2751f7805b33SLior Cohen { 2752f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2753f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2754f7805b33SLior Cohen 2755f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2756f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2757f7805b33SLior Cohen return 0; 2758f7805b33SLior Cohen } 2759f7805b33SLior Cohen 2760f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2761f7805b33SLior Cohen void *buf, ssize_t *size, 2762f7805b33SLior Cohen ssize_t *bytes_copied) 2763f7805b33SLior Cohen { 2764f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2765f7805b33SLior Cohen 2766f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2767f7805b33SLior Cohen if (*size > buf_size_left) 2768f7805b33SLior Cohen *size = buf_size_left; 2769f7805b33SLior Cohen 2770f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2771f7805b33SLior Cohen *bytes_copied += *size; 2772f7805b33SLior Cohen 2773f7805b33SLior Cohen if (buf_size_left == *size) 2774f7805b33SLior Cohen return true; 2775f7805b33SLior Cohen return false; 2776f7805b33SLior Cohen } 2777f7805b33SLior Cohen 2778f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2779f7805b33SLior Cohen char __user *user_buf, 2780f7805b33SLior Cohen size_t count, loff_t *ppos) 2781f7805b33SLior Cohen { 2782f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2783f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 278491c28b83SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon[0].block, *curr_buf; 2785f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2786f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2787f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2788f7805b33SLior Cohen bool b_full; 2789f7805b33SLior Cohen 279091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2791f7805b33SLior Cohen write_ptr_addr = 279291c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 279391c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2794f7805b33SLior Cohen } else { 2795f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2796f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2797f7805b33SLior Cohen } 2798f7805b33SLior Cohen 279991c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2800f7805b33SLior Cohen return 0; 2801f7805b33SLior Cohen 2802f7805b33SLior Cohen mutex_lock(&data->mutex); 2803f7805b33SLior Cohen if (data->state == 2804f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2805f7805b33SLior Cohen mutex_unlock(&data->mutex); 2806f7805b33SLior Cohen return 0; 2807f7805b33SLior Cohen } 2808f7805b33SLior Cohen 2809f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2810f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2811f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2812f7805b33SLior Cohen 2813f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2814f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2815f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2816f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2817f7805b33SLior Cohen curr_buf, &size, 2818f7805b33SLior Cohen &bytes_copied); 2819f7805b33SLior Cohen data->prev_wr_ptr += size; 2820f7805b33SLior Cohen 2821f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2822f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 282391c28b83SShahar S Matityahu size = trans->dbg.fw_mon[0].size - data->prev_wr_ptr; 2824f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2825f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2826f7805b33SLior Cohen curr_buf, &size, 2827f7805b33SLior Cohen &bytes_copied); 2828f7805b33SLior Cohen data->prev_wr_ptr += size; 2829f7805b33SLior Cohen 2830f7805b33SLior Cohen if (!b_full) { 2831f7805b33SLior Cohen size = write_ptr; 2832f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2833f7805b33SLior Cohen cpu_addr, &size, 2834f7805b33SLior Cohen &bytes_copied); 2835f7805b33SLior Cohen data->prev_wr_ptr = size; 2836f7805b33SLior Cohen data->prev_wrap_cnt++; 2837f7805b33SLior Cohen } 2838f7805b33SLior Cohen } else { 2839f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2840f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2841f7805b33SLior Cohen IWL_WARN(trans, 2842f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2843f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2844f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2845f7805b33SLior Cohen IWL_WARN(trans, 2846f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2847f7805b33SLior Cohen 2848f7805b33SLior Cohen size = write_ptr; 2849f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2850f7805b33SLior Cohen cpu_addr, &size, 2851f7805b33SLior Cohen &bytes_copied); 2852f7805b33SLior Cohen data->prev_wr_ptr = size; 2853f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2854f7805b33SLior Cohen } 2855f7805b33SLior Cohen 2856f7805b33SLior Cohen mutex_unlock(&data->mutex); 2857f7805b33SLior Cohen 2858f7805b33SLior Cohen return bytes_copied; 2859f7805b33SLior Cohen } 2860f7805b33SLior Cohen 2861e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2862e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2863e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2864e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2865e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2866fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2867e705c121SKalle Valo 2868f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2869f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2870f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2871f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2872f7805b33SLior Cohen }; 2873f7805b33SLior Cohen 2874f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2875cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2876e705c121SKalle Valo { 2877f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2878f8a1edb7SJohannes Berg 28792ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28802ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28812ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28822ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28832ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28842ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2885f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2886e705c121SKalle Valo } 2887f7805b33SLior Cohen 2888f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2889f7805b33SLior Cohen { 2890f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2891f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2892f7805b33SLior Cohen 2893f7805b33SLior Cohen mutex_lock(&data->mutex); 2894f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2895f7805b33SLior Cohen mutex_unlock(&data->mutex); 2896f7805b33SLior Cohen } 2897e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2898e705c121SKalle Valo 28996983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2900e705c121SKalle Valo { 29013cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2902e705c121SKalle Valo u32 cmdlen = 0; 2903e705c121SKalle Valo int i; 2904e705c121SKalle Valo 29053cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 29066983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2907e705c121SKalle Valo 2908e705c121SKalle Valo return cmdlen; 2909e705c121SKalle Valo } 2910e705c121SKalle Valo 2911e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2912e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2913e705c121SKalle Valo int allocated_rb_nums) 2914e705c121SKalle Valo { 2915e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2916e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 291778485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 291878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2919e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2920e705c121SKalle Valo 2921e705c121SKalle Valo spin_lock(&rxq->lock); 2922e705c121SKalle Valo 29230307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2924e705c121SKalle Valo 2925e705c121SKalle Valo for (i = rxq->read, j = 0; 2926e705c121SKalle Valo i != r && j < allocated_rb_nums; 2927e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2928e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2929e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2930e705c121SKalle Valo 2931e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2932e705c121SKalle Valo DMA_FROM_DEVICE); 2933e705c121SKalle Valo 2934e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2935e705c121SKalle Valo 2936e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2937e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2938e705c121SKalle Valo rb = (void *)(*data)->data; 2939e705c121SKalle Valo rb->index = cpu_to_le32(i); 2940e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2941e705c121SKalle Valo /* remap the page for the free benefit */ 2942e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2943e705c121SKalle Valo max_len, 2944e705c121SKalle Valo DMA_FROM_DEVICE); 2945e705c121SKalle Valo 2946e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2947e705c121SKalle Valo } 2948e705c121SKalle Valo 2949e705c121SKalle Valo spin_unlock(&rxq->lock); 2950e705c121SKalle Valo 2951e705c121SKalle Valo return rb_len; 2952e705c121SKalle Valo } 2953e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2954e705c121SKalle Valo 2955e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2956e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2957e705c121SKalle Valo { 2958e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2959e705c121SKalle Valo __le32 *val; 2960e705c121SKalle Valo int i; 2961e705c121SKalle Valo 2962e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2963e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2964e705c121SKalle Valo val = (void *)(*data)->data; 2965e705c121SKalle Valo 2966e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2967e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2968e705c121SKalle Valo 2969e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2970e705c121SKalle Valo 2971e705c121SKalle Valo return csr_len; 2972e705c121SKalle Valo } 2973e705c121SKalle Valo 2974e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2975e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2976e705c121SKalle Valo { 2977e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2978e705c121SKalle Valo unsigned long flags; 2979e705c121SKalle Valo __le32 *val; 2980e705c121SKalle Valo int i; 2981e705c121SKalle Valo 298223ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2983e705c121SKalle Valo return 0; 2984e705c121SKalle Valo 2985e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2986e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2987e705c121SKalle Valo val = (void *)(*data)->data; 2988e705c121SKalle Valo 2989723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2990723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2991723b45e2SLiad Kaufman i += sizeof(u32)) 2992e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2993723b45e2SLiad Kaufman else 2994ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2995ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2996723b45e2SLiad Kaufman i += sizeof(u32)) 2997723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2998723b45e2SLiad Kaufman i)); 2999e705c121SKalle Valo 3000e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3001e705c121SKalle Valo 3002e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3003e705c121SKalle Valo 3004e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3005e705c121SKalle Valo } 3006e705c121SKalle Valo 3007e705c121SKalle Valo static u32 3008e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3009e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3010e705c121SKalle Valo u32 monitor_len) 3011e705c121SKalle Valo { 3012e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3013e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3014e705c121SKalle Valo unsigned long flags; 3015e705c121SKalle Valo u32 i; 3016e705c121SKalle Valo 301723ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3018e705c121SKalle Valo return 0; 3019e705c121SKalle Valo 3020ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3021e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3022ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 302314ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3024ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3025e705c121SKalle Valo 3026e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3027e705c121SKalle Valo 3028e705c121SKalle Valo return monitor_len; 3029e705c121SKalle Valo } 3030e705c121SKalle Valo 30317a14c23dSSara Sharon static void 30327a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30337a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30347a14c23dSSara Sharon { 3035c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30367a14c23dSSara Sharon 3037c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3038c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3039c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3040c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3041c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 304291c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 304391c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 304491c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 304591c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30467a14c23dSSara Sharon } else { 30477a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30487a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30497a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30507a14c23dSSara Sharon } 3051c88580e1SShahar S Matityahu 3052c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30537a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30547a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30557a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30567a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3057c88580e1SShahar S Matityahu if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3058c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3059c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3060c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3061c88580e1SShahar S Matityahu } 3062c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30637a14c23dSSara Sharon } 30647a14c23dSSara Sharon 3065e705c121SKalle Valo static u32 3066e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3067e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3068e705c121SKalle Valo u32 monitor_len) 3069e705c121SKalle Valo { 3070e705c121SKalle Valo u32 len = 0; 3071e705c121SKalle Valo 307291c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 307391c28b83SShahar S Matityahu (trans->dbg.num_blocks && 3074c88580e1SShahar S Matityahu (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 || 30751d45a700SShahar S Matityahu trans->cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3076e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3077e705c121SKalle Valo 3078e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3079e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30807a14c23dSSara Sharon 30817a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3082e705c121SKalle Valo 3083e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 308491c28b83SShahar S Matityahu if (trans->dbg.num_blocks) { 3085e705c121SKalle Valo memcpy(fw_mon_data->data, 308691c28b83SShahar S Matityahu trans->dbg.fw_mon[0].block, 308791c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size); 3088e705c121SKalle Valo 308991c28b83SShahar S Matityahu monitor_len = trans->dbg.fw_mon[0].size; 309091c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 30917a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3092e705c121SKalle Valo /* 3093e705c121SKalle Valo * Update pointers to reflect actual values after 3094e705c121SKalle Valo * shifting 3095e705c121SKalle Valo */ 309691c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3097fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3098fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 309991c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3100fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3101fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3102fd527eb5SGolan Ben Ami } else { 3103e705c121SKalle Valo base = iwl_read_prph(trans, base) << 310491c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3105fd527eb5SGolan Ben Ami } 3106fd527eb5SGolan Ben Ami 3107e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3108e705c121SKalle Valo monitor_len / sizeof(u32)); 310991c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3110e705c121SKalle Valo monitor_len = 3111e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3112e705c121SKalle Valo fw_mon_data, 3113e705c121SKalle Valo monitor_len); 3114e705c121SKalle Valo } else { 3115e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3116e705c121SKalle Valo monitor_len = 0; 3117e705c121SKalle Valo } 3118e705c121SKalle Valo 3119e705c121SKalle Valo len += monitor_len; 3120e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3121e705c121SKalle Valo } 3122e705c121SKalle Valo 3123e705c121SKalle Valo return len; 3124e705c121SKalle Valo } 3125e705c121SKalle Valo 312693079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3127e705c121SKalle Valo { 312891c28b83SShahar S Matityahu if (trans->dbg.num_blocks) { 3129da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3130da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 313191c28b83SShahar S Matityahu trans->dbg.fw_mon[0].size; 313291c28b83SShahar S Matityahu return trans->dbg.fw_mon[0].size; 313391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3134da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3135e705c121SKalle Valo 313691c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 313791c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3138fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3139fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 314091c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3141fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3142fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3143fd527eb5SGolan Ben Ami 3144fd527eb5SGolan Ben Ami monitor_len = 3145fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 314691c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3147fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3148fd527eb5SGolan Ben Ami } else { 314991c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 315091c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3151e705c121SKalle Valo 3152e705c121SKalle Valo base = iwl_read_prph(trans, base) << 315391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3154e705c121SKalle Valo end = iwl_read_prph(trans, end) << 315591c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3156e705c121SKalle Valo 3157e705c121SKalle Valo /* Make "end" point to the actual end */ 3158fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 3159fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 316091c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 316191c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3162e705c121SKalle Valo monitor_len = end - base; 3163fd527eb5SGolan Ben Ami } 3164da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3165da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3166e705c121SKalle Valo monitor_len; 3167da752717SShahar S Matityahu return monitor_len; 3168e705c121SKalle Valo } 3169da752717SShahar S Matityahu return 0; 3170da752717SShahar S Matityahu } 3171da752717SShahar S Matityahu 3172da752717SShahar S Matityahu static struct iwl_trans_dump_data 3173da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 317479f033f6SSara Sharon u32 dump_mask) 3175da752717SShahar S Matityahu { 3176da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3177da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3178da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3179da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3180da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3181fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3182da752717SShahar S Matityahu int i, ptr; 3183da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3184da752717SShahar S Matityahu !trans->cfg->mq_rx_supported && 318579f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 318679f033f6SSara Sharon 318779f033f6SSara Sharon if (!dump_mask) 318879f033f6SSara Sharon return NULL; 3189da752717SShahar S Matityahu 3190da752717SShahar S Matityahu /* transport dump header */ 3191da752717SShahar S Matityahu len = sizeof(*dump_data); 3192da752717SShahar S Matityahu 3193da752717SShahar S Matityahu /* host commands */ 3194e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3195da752717SShahar S Matityahu len += sizeof(*data) + 31968672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 31978672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3198da752717SShahar S Matityahu 3199da752717SShahar S Matityahu /* FW monitor */ 3200fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3201da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3202e705c121SKalle Valo 3203e705c121SKalle Valo /* CSR registers */ 320479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3205e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3206e705c121SKalle Valo 3207e705c121SKalle Valo /* FH registers */ 320879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3209723b45e2SLiad Kaufman if (trans->cfg->gen2) 3210723b45e2SLiad Kaufman len += sizeof(*data) + 3211ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3212ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3213723b45e2SLiad Kaufman else 3214723b45e2SLiad Kaufman len += sizeof(*data) + 3215520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3216520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3217520f03eaSShahar S Matityahu } 3218e705c121SKalle Valo 3219e705c121SKalle Valo if (dump_rbs) { 322078485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 322178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3222e705c121SKalle Valo /* RBs */ 32230307c839SGolan Ben Ami num_rbs = 32240307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3225e705c121SKalle Valo & 0x0FFF; 322678485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3227e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3228e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3229e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3230e705c121SKalle Valo } 3231e705c121SKalle Valo 32325538409bSLiad Kaufman /* Paged memory for gen2 HW */ 323379f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3234505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32355538409bSLiad Kaufman len += sizeof(*data) + 32365538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3237505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32385538409bSLiad Kaufman 3239e705c121SKalle Valo dump_data = vzalloc(len); 3240e705c121SKalle Valo if (!dump_data) 3241e705c121SKalle Valo return NULL; 3242e705c121SKalle Valo 3243e705c121SKalle Valo len = 0; 3244e705c121SKalle Valo data = (void *)dump_data->data; 3245520f03eaSShahar S Matityahu 3246e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3247520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3248520f03eaSShahar S Matityahu 3249e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3250e705c121SKalle Valo txcmd = (void *)data->data; 3251e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3252bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3253bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32544ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3255e705c121SKalle Valo u32 caplen, cmdlen; 3256e705c121SKalle Valo 3257520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3258520f03eaSShahar S Matityahu cmdq->tfds + 3259520f03eaSShahar S Matityahu tfd_size * ptr); 3260e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3261e705c121SKalle Valo 3262e705c121SKalle Valo if (cmdlen) { 3263e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3264e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3265e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3266520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3267520f03eaSShahar S Matityahu caplen); 3268e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3269e705c121SKalle Valo } 3270e705c121SKalle Valo 32717b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3272e705c121SKalle Valo } 3273e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3274e705c121SKalle Valo 3275e705c121SKalle Valo data->len = cpu_to_le32(len); 3276e705c121SKalle Valo len += sizeof(*data); 3277e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3278520f03eaSShahar S Matityahu } 3279e705c121SKalle Valo 328079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3281e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 328279f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3283e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3284e705c121SKalle Valo if (dump_rbs) 3285e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3286e705c121SKalle Valo 32875538409bSLiad Kaufman /* Paged memory for gen2 HW */ 328879f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3289505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 32905538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3291505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 32925538409bSLiad Kaufman 32935538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 32945538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 32955538409bSLiad Kaufman paging = (void *)data->data; 32965538409bSLiad Kaufman paging->index = cpu_to_le32(i); 32975538409bSLiad Kaufman memcpy(paging->data, 3298505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 32995538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33005538409bSLiad Kaufman 33015538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33025538409bSLiad Kaufman } 33035538409bSLiad Kaufman } 330479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3305e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3306e705c121SKalle Valo 3307e705c121SKalle Valo dump_data->len = len; 3308e705c121SKalle Valo 3309e705c121SKalle Valo return dump_data; 3310e705c121SKalle Valo } 3311e705c121SKalle Valo 33124cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 33134cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 33144cbb8e50SLuciano Coelho { 3315e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3316e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 33174cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 33184cbb8e50SLuciano Coelho 33194cbb8e50SLuciano Coelho return 0; 33204cbb8e50SLuciano Coelho } 33214cbb8e50SLuciano Coelho 33224cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 33234cbb8e50SLuciano Coelho { 3324e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3325e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 33264cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 33274cbb8e50SLuciano Coelho } 33284cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 33294cbb8e50SLuciano Coelho 3330623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3331623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3332623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3333623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3334623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3335623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3336623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3337623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3338623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3339623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3340623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3341870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3342623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3343623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3344623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3345623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3346623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3347623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3348623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3349d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 3350d1967ce6SShahar S Matityahu .sync_nmi = iwl_trans_pcie_sync_nmi 3351623e7766SSara Sharon 3352623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3353623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3354623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3355623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3356623e7766SSara Sharon #else 3357623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3358623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3359623e7766SSara Sharon 3360e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3361623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3362623e7766SSara Sharon IWL_TRANS_PM_OPS 3363e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3364e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3365e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3366e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3367e705c121SKalle Valo 3368e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3369e705c121SKalle Valo 3370e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3371e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3372e705c121SKalle Valo 3373e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3374e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3375e705c121SKalle Valo 337642db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 337742db09c1SLiad Kaufman 3378d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3379d6d517b7SSara Sharon 3380e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 33810cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3382f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3383f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3384f7805b33SLior Cohen #endif 3385623e7766SSara Sharon }; 3386e705c121SKalle Valo 3387623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3388623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3389623e7766SSara Sharon IWL_TRANS_PM_OPS 3390623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3391eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3392eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 339377c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3394e705c121SKalle Valo 3395ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3396e705c121SKalle Valo 3397ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3398623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3399623e7766SSara Sharon 3400ba7136f3SAlex Malamud .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3401ba7136f3SAlex Malamud 34026b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 34036b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3404d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 340592536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3406f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3407f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3408f7805b33SLior Cohen #endif 3409e705c121SKalle Valo }; 3410e705c121SKalle Valo 3411e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3412e705c121SKalle Valo const struct pci_device_id *ent, 3413e705c121SKalle Valo const struct iwl_cfg *cfg) 3414e705c121SKalle Valo { 3415e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3416e705c121SKalle Valo struct iwl_trans *trans; 341796a6497bSSara Sharon int ret, addr_size; 3418e705c121SKalle Valo 34195a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 34205a41a86cSSharon Dvir if (ret) 34215a41a86cSSharon Dvir return ERR_PTR(ret); 34225a41a86cSSharon Dvir 3423623e7766SSara Sharon if (cfg->gen2) 3424623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3425623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3426623e7766SSara Sharon else 3427e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 34281ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3429e705c121SKalle Valo if (!trans) 3430e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3431e705c121SKalle Valo 3432e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3433e705c121SKalle Valo 3434e705c121SKalle Valo trans_pcie->trans = trans; 3435326477e4SJohannes Berg trans_pcie->opmode_down = true; 3436e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3437e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3438e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3439e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 34406eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 34416eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 34426eb5e529SEmmanuel Grumbach ret = -ENOMEM; 34436eb5e529SEmmanuel Grumbach goto out_no_pci; 34446eb5e529SEmmanuel Grumbach } 3445c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3446e705c121SKalle Valo 3447e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3448e705c121SKalle Valo /* 3449e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3450e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3451e705c121SKalle Valo * lot of power. 3452e705c121SKalle Valo */ 3453e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3454e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3455e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3456e705c121SKalle Valo } 3457e705c121SKalle Valo 34589416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34599416560eSGolan Ben Ami 34606983ba69SSara Sharon if (cfg->use_tfh) { 34612c6262b7SSara Sharon addr_size = 64; 34623cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 34638352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 34646983ba69SSara Sharon } else { 34652c6262b7SSara Sharon addr_size = 36; 34663cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 34676983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 34686983ba69SSara Sharon } 34693cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 34703cd1980bSSara Sharon 3471e705c121SKalle Valo pci_set_master(pdev); 3472e705c121SKalle Valo 347396a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3474e705c121SKalle Valo if (!ret) 347596a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 347696a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3477e705c121SKalle Valo if (ret) { 3478e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3479e705c121SKalle Valo if (!ret) 3480e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3481e705c121SKalle Valo DMA_BIT_MASK(32)); 3482e705c121SKalle Valo /* both attempts failed: */ 3483e705c121SKalle Valo if (ret) { 3484e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34855a41a86cSSharon Dvir goto out_no_pci; 3486e705c121SKalle Valo } 3487e705c121SKalle Valo } 3488e705c121SKalle Valo 34895a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3490e705c121SKalle Valo if (ret) { 34915a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34925a41a86cSSharon Dvir goto out_no_pci; 3493e705c121SKalle Valo } 3494e705c121SKalle Valo 34955a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3496e705c121SKalle Valo if (!trans_pcie->hw_base) { 34975a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3498e705c121SKalle Valo ret = -ENODEV; 34995a41a86cSSharon Dvir goto out_no_pci; 3500e705c121SKalle Valo } 3501e705c121SKalle Valo 3502e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3503e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3504e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3505e705c121SKalle Valo 3506e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3507e705c121SKalle Valo iwl_disable_interrupts(trans); 3508e705c121SKalle Valo 3509e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35109a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35119a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35129a098a89SRajat Jain ret = -EIO; 35139a098a89SRajat Jain goto out_no_pci; 35149a098a89SRajat Jain } 35159a098a89SRajat Jain 3516e705c121SKalle Valo /* 3517e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3518e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3519e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3520e705c121SKalle Valo * in the old format. 3521e705c121SKalle Valo */ 35226e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3523e705c121SKalle Valo unsigned long flags; 3524e705c121SKalle Valo 3525e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3526e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3527e705c121SKalle Valo 3528e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3529e705c121SKalle Valo if (ret) { 3530e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 35315a41a86cSSharon Dvir goto out_no_pci; 3532e705c121SKalle Valo } 3533e705c121SKalle Valo 3534e705c121SKalle Valo /* 3535e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3536e705c121SKalle Valo * id located at the AUX bus MISC address space. 3537e705c121SKalle Valo */ 3538c96b5eecSJohannes Berg ret = iwl_finish_nic_init(trans); 3539c96b5eecSJohannes Berg if (ret) 35405a41a86cSSharon Dvir goto out_no_pci; 3541e705c121SKalle Valo 354223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3543e705c121SKalle Valo u32 hw_step; 3544e705c121SKalle Valo 3545ea695b7cSShaul Triebitz hw_step = iwl_read_umac_prph_no_grab(trans, 3546ea695b7cSShaul Triebitz WFPM_CTRL_REG); 3547e705c121SKalle Valo hw_step |= ENABLE_WFPM; 3548ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, WFPM_CTRL_REG, 3549ea695b7cSShaul Triebitz hw_step); 3550cc5470dfSShahar S Matityahu hw_step = iwl_read_prph_no_grab(trans, 3551cc5470dfSShahar S Matityahu CNVI_AUX_MISC_CHIP); 3552e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3553e705c121SKalle Valo if (hw_step == 0x3) 3554e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3555e705c121SKalle Valo (SILICON_C_STEP << 2); 3556e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3557e705c121SKalle Valo } 3558e705c121SKalle Valo } 3559e705c121SKalle Valo 356099be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 356199be6166SLuca Coelho 3562f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 35631afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 356433708052SLuca Coelho 3565ff911dcaSShaul Triebitz if (cfg == &iwlax210_2ax_cfg_so_hr_a0) { 3566ff911dcaSShaul Triebitz if (trans->hw_rev == CSR_HW_REV_TYPE_TY) { 3567ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_ty_gf_a0; 3568ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3569ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3570ff911dcaSShaul Triebitz trans->cfg = &iwlax210_2ax_cfg_so_jf_a0; 3571ff911dcaSShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3572ff911dcaSShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF)) { 3573d151b0a2SIhab Zhaika trans->cfg = &iwlax211_2ax_cfg_so_gf_a0; 35745bd757a6SShaul Triebitz } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 35755bd757a6SShaul Triebitz CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_GF4)) { 3576d151b0a2SIhab Zhaika trans->cfg = &iwlax411_2ax_cfg_so_gf4_a0; 3577ff911dcaSShaul Triebitz } 3578085486deSIhab Zhaika } else if (cfg == &iwl_ax101_cfg_qu_hr) { 3579498d3eb5SOren Givon if ((CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3580debec2f2SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3581498d3eb5SOren Givon trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) || 3582498d3eb5SOren Givon (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3583498d3eb5SOren Givon CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR1))) { 3584debec2f2SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 3585debec2f2SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 358633708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3587085486deSIhab Zhaika trans->cfg = &iwl_ax101_cfg_qu_hr; 3588b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3589b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3590b1bbc1a6SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_jf; 3591b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3592b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3593b1bbc1a6SLuca Coelho IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3594b1bbc1a6SLuca Coelho ret = -EINVAL; 3595b1bbc1a6SLuca Coelho goto out_no_pci; 3596b1bbc1a6SLuca Coelho } else { 3597b1bbc1a6SLuca Coelho IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3598b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3599b1bbc1a6SLuca Coelho ret = -EINVAL; 3600b1bbc1a6SLuca Coelho goto out_no_pci; 3601b1bbc1a6SLuca Coelho } 3602b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 36038093bb6dSLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 3604b9500577SLuca Coelho trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) { 3605f6586b69STzipi Peres u32 hw_status; 3606f6586b69STzipi Peres 3607f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 360833708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 360933708052SLuca Coelho /* 361033708052SLuca Coelho * b step fw is the same for physical card and fpga 361133708052SLuca Coelho */ 361233708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 361333708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 361433708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 361533708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 361633708052SLuca Coelho } else { 361733708052SLuca Coelho /* 361833708052SLuca Coelho * a step no FPGA 361933708052SLuca Coelho */ 36202f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3621f6586b69STzipi Peres } 362233708052SLuca Coelho } 3623f6586b69STzipi Peres #endif 36241afb0ae4SHaim Dreyfuss 36252e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3626e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3627e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3628e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3629e705c121SKalle Valo 3630e705c121SKalle Valo /* Initialize the wait queue for commands */ 3631e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3632e705c121SKalle Valo 36334cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 36344cbb8e50SLuciano Coelho 36352e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36362388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36372388bd7bSDan Carpenter if (ret) 36385a41a86cSSharon Dvir goto out_no_pci; 36392e5d4a8fSHaim Dreyfuss } else { 3640e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3641e705c121SKalle Valo if (ret) 36425a41a86cSSharon Dvir goto out_no_pci; 3643e705c121SKalle Valo 36445a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36455a41a86cSSharon Dvir iwl_pcie_isr, 3646e705c121SKalle Valo iwl_pcie_irq_handler, 3647e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3648e705c121SKalle Valo if (ret) { 3649e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3650e705c121SKalle Valo goto out_free_ict; 3651e705c121SKalle Valo } 3652e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 36532e5d4a8fSHaim Dreyfuss } 3654e705c121SKalle Valo 365510a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 365610a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 365710a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 365810a54d81SLuca Coelho 3659b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3660b3ff1270SLuca Coelho 3661f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3662f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3663f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3664f7805b33SLior Cohen #endif 3665f7805b33SLior Cohen 3666e705c121SKalle Valo return trans; 3667e705c121SKalle Valo 3668e705c121SKalle Valo out_free_ict: 3669e705c121SKalle Valo iwl_pcie_free_ict(trans); 3670e705c121SKalle Valo out_no_pci: 36716eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3672e705c121SKalle Valo iwl_trans_free(trans); 3673e705c121SKalle Valo return ERR_PTR(ret); 3674e705c121SKalle Valo } 3675b8a7547dSShahar S Matityahu 3676d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3677b8a7547dSShahar S Matityahu { 36781c6bca6dSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3679b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3680e4eee943SShahar S Matityahu bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 36811c6bca6dSShahar S Matityahu u32 inta_addr, sw_err_bit; 36821c6bca6dSShahar S Matityahu 36831c6bca6dSShahar S Matityahu if (trans_pcie->msix_enabled) { 36841c6bca6dSShahar S Matityahu inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 36851c6bca6dSShahar S Matityahu sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 36861c6bca6dSShahar S Matityahu } else { 36871c6bca6dSShahar S Matityahu inta_addr = CSR_INT; 36881c6bca6dSShahar S Matityahu sw_err_bit = CSR_INT_BIT_SW_ERR; 36891c6bca6dSShahar S Matityahu } 3690b8a7547dSShahar S Matityahu 3691e4eee943SShahar S Matityahu /* if the interrupts were already disabled, there is no point in 3692e4eee943SShahar S Matityahu * calling iwl_disable_interrupts 3693e4eee943SShahar S Matityahu */ 3694e4eee943SShahar S Matityahu if (interrupts_enabled) 3695b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3696e4eee943SShahar S Matityahu 3697b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3698b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 36991c6bca6dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, inta_addr); 3700b8a7547dSShahar S Matityahu 3701b8a7547dSShahar S Matityahu /* Error detected by uCode */ 37021c6bca6dSShahar S Matityahu if (inta_hw & sw_err_bit) { 3703b8a7547dSShahar S Matityahu /* Clear causes register */ 37041c6bca6dSShahar S Matityahu iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3705b8a7547dSShahar S Matityahu break; 3706b8a7547dSShahar S Matityahu } 3707b8a7547dSShahar S Matityahu 3708b8a7547dSShahar S Matityahu mdelay(1); 3709b8a7547dSShahar S Matityahu } 3710e4eee943SShahar S Matityahu 3711e4eee943SShahar S Matityahu /* enable interrupts only if there were already enabled before this 3712e4eee943SShahar S Matityahu * function to avoid a case were the driver enable interrupts before 3713e4eee943SShahar S Matityahu * proper configurations were made 3714e4eee943SShahar S Matityahu */ 3715e4eee943SShahar S Matityahu if (interrupts_enabled) 3716b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3717e4eee943SShahar S Matityahu 3718b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3719b8a7547dSShahar S Matityahu } 3720