18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 3227f2597SJohannes Berg * Copyright (C) 2007-2015, 2018-2022 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 276d19a5ebSEmmanuel Grumbach #include "mei/iwl-mei.h" 28e705c121SKalle Valo #include "internal.h" 29e705c121SKalle Valo #include "iwl-fh.h" 306654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 31e705c121SKalle Valo 32e705c121SKalle Valo /* extended range in FW SRAM */ 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 34e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35e705c121SKalle Valo 364290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37a6d24fadSRajat Jain { 38c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 39c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 40c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 41a6d24fadSRajat Jain #define PREFIX_LEN 32 42a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 44a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 45a6d24fadSRajat Jain char *prefix; 46a6d24fadSRajat Jain 47a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 48a6d24fadSRajat Jain return; 49a6d24fadSRajat Jain 50a6d24fadSRajat Jain /* Should be a multiple of 4 */ 51a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54c4d3f2eeSLuca Coelho 55a6d24fadSRajat Jain /* Alloc a max size buffer */ 56a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60c4d3f2eeSLuca Coelho 61a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 62a6d24fadSRajat Jain if (!buf) 63a6d24fadSRajat Jain return; 64a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 65a6d24fadSRajat Jain 66a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67a6d24fadSRajat Jain 68a6d24fadSRajat Jain /* Print wifi device registers */ 69a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 71a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 73a6d24fadSRajat Jain goto err_read; 74a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75a6d24fadSRajat Jain 76a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 79a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80a6d24fadSRajat Jain 81a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82a6d24fadSRajat Jain if (pos) { 83a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 86a6d24fadSRajat Jain goto err_read; 87a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88a6d24fadSRajat Jain 32, 4, buf, i, 0); 89a6d24fadSRajat Jain } 90a6d24fadSRajat Jain 91a6d24fadSRajat Jain /* Print parent device registers next */ 92a6d24fadSRajat Jain if (!pdev->bus->self) 93a6d24fadSRajat Jain goto out; 94a6d24fadSRajat Jain 95a6d24fadSRajat Jain pdev = pdev->bus->self; 96a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97a6d24fadSRajat Jain 98a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99a6d24fadSRajat Jain pci_name(pdev)); 100c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 102a6d24fadSRajat Jain goto err_read; 103a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Print root port AER registers */ 106a6d24fadSRajat Jain pos = 0; 107a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 108a6d24fadSRajat Jain if (pdev) 109a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110a6d24fadSRajat Jain if (pos) { 111a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112a6d24fadSRajat Jain pci_name(pdev)); 113a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 116a6d24fadSRajat Jain goto err_read; 117a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118a6d24fadSRajat Jain 4, buf, i, 0); 119a6d24fadSRajat Jain } 120f3402d6dSSara Sharon goto out; 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain err_read: 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 125a6d24fadSRajat Jain out: 126a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 127a6d24fadSRajat Jain kfree(buf); 128a6d24fadSRajat Jain } 129a6d24fadSRajat Jain 13015bf5ac6SJohannes Berg static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 13115bf5ac6SJohannes Berg bool retake_ownership) 132870c2a11SGolan Ben Ami { 133870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1341b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1351b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_GP_CNTRL, 1361b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_SW_RESET); 1371b6598c3SRoee Goldfiner else 1381b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_RESET, 1391b6598c3SRoee Goldfiner CSR_RESET_REG_FLAG_SW_RESET); 140870c2a11SGolan Ben Ami usleep_range(5000, 6000); 14115bf5ac6SJohannes Berg 14215bf5ac6SJohannes Berg if (retake_ownership) 14315bf5ac6SJohannes Berg return iwl_pcie_prepare_card_hw(trans); 14415bf5ac6SJohannes Berg 14515bf5ac6SJohannes Berg return 0; 146870c2a11SGolan Ben Ami } 147870c2a11SGolan Ben Ami 148e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 149e705c121SKalle Valo { 15069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 151e705c121SKalle Valo 15269f0e505SShahar S Matityahu if (!fw_mon->size) 15369f0e505SShahar S Matityahu return; 15469f0e505SShahar S Matityahu 15569f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 15669f0e505SShahar S Matityahu fw_mon->physical); 15769f0e505SShahar S Matityahu 15869f0e505SShahar S Matityahu fw_mon->block = NULL; 15969f0e505SShahar S Matityahu fw_mon->physical = 0; 16069f0e505SShahar S Matityahu fw_mon->size = 0; 161e705c121SKalle Valo } 162e705c121SKalle Valo 16388964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 16488964b2eSSara Sharon u8 max_power, u8 min_power) 165e705c121SKalle Valo { 16669f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 16769f0e505SShahar S Matityahu void *block = NULL; 16869f0e505SShahar S Matityahu dma_addr_t physical = 0; 169e705c121SKalle Valo u32 size = 0; 170e705c121SKalle Valo u8 power; 171e705c121SKalle Valo 17269f0e505SShahar S Matityahu if (fw_mon->size) 17369f0e505SShahar S Matityahu return; 17469f0e505SShahar S Matityahu 17588964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 176e705c121SKalle Valo size = BIT(power); 17769f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1782d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 17969f0e505SShahar S Matityahu if (!block) 180e705c121SKalle Valo continue; 181e705c121SKalle Valo 182e705c121SKalle Valo IWL_INFO(trans, 183c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 184c5f97542SShahar S Matityahu size); 185e705c121SKalle Valo break; 186e705c121SKalle Valo } 187e705c121SKalle Valo 18869f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 189e705c121SKalle Valo return; 190e705c121SKalle Valo 191e705c121SKalle Valo if (power != max_power) 192e705c121SKalle Valo IWL_ERR(trans, 193e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 194e705c121SKalle Valo (unsigned long)BIT(power - 10), 195e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 196e705c121SKalle Valo 19769f0e505SShahar S Matityahu fw_mon->block = block; 19869f0e505SShahar S Matityahu fw_mon->physical = physical; 19969f0e505SShahar S Matityahu fw_mon->size = size; 20088964b2eSSara Sharon } 20188964b2eSSara Sharon 20288964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 20388964b2eSSara Sharon { 20488964b2eSSara Sharon if (!max_power) { 20588964b2eSSara Sharon /* default max_power is maximum */ 20688964b2eSSara Sharon max_power = 26; 20788964b2eSSara Sharon } else { 20888964b2eSSara Sharon max_power += 11; 20988964b2eSSara Sharon } 21088964b2eSSara Sharon 21188964b2eSSara Sharon if (WARN(max_power > 26, 21288964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 21388964b2eSSara Sharon max_power)) 21488964b2eSSara Sharon return; 21588964b2eSSara Sharon 21669f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 21788964b2eSSara Sharon return; 21888964b2eSSara Sharon 21988964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 220e705c121SKalle Valo } 221e705c121SKalle Valo 222e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 223e705c121SKalle Valo { 224e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 225e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 226e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 227e705c121SKalle Valo } 228e705c121SKalle Valo 229e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 230e705c121SKalle Valo { 231e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 232e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 233e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 234e705c121SKalle Valo } 235e705c121SKalle Valo 236e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 237e705c121SKalle Valo { 238e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 239e705c121SKalle Valo return; 240e705c121SKalle Valo 241e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 242e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 243e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 244e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 245e705c121SKalle Valo else 246e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 247e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 248e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 249e705c121SKalle Valo } 250e705c121SKalle Valo 251e705c121SKalle Valo /* PCI registers */ 252e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 253e705c121SKalle Valo 254eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 255e705c121SKalle Valo { 256e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 257e705c121SKalle Valo u16 lctl; 258e705c121SKalle Valo u16 cap; 259e705c121SKalle Valo 260e705c121SKalle Valo /* 261cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 262cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 263cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 264e705c121SKalle Valo */ 2653d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 266cc894b85SLuca Coelho 267cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 268e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 269e705c121SKalle Valo 270e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 271e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 272d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 273e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 274e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 275e705c121SKalle Valo } 276e705c121SKalle Valo 277e705c121SKalle Valo /* 278e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 279e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 280e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 281e705c121SKalle Valo */ 282e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 283e705c121SKalle Valo { 28452b6e168SEmmanuel Grumbach int ret; 28552b6e168SEmmanuel Grumbach 286e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 287e705c121SKalle Valo 288e705c121SKalle Valo /* 289e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 290e705c121SKalle Valo * bits already set by default after reset. 291e705c121SKalle Valo */ 292e705c121SKalle Valo 293e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 294286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 295e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 296e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 297e705c121SKalle Valo 298e705c121SKalle Valo /* 299e705c121SKalle Valo * Disable L0s without affecting L1; 300e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 301e705c121SKalle Valo */ 302e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 303e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 304e705c121SKalle Valo 305e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 306e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 307e705c121SKalle Valo 308e705c121SKalle Valo /* 309e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 310e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 311e705c121SKalle Valo */ 312e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 313e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 314e705c121SKalle Valo 315e705c121SKalle Valo iwl_pcie_apm_config(trans); 316e705c121SKalle Valo 317e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 318286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 31977d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 320e705c121SKalle Valo 321425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 322c96b5eecSJohannes Berg if (ret) 32352b6e168SEmmanuel Grumbach return ret; 324e705c121SKalle Valo 325e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 326e705c121SKalle Valo /* 327e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 328e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 329e705c121SKalle Valo * not related to host_interrupt_operation_mode. 330e705c121SKalle Valo * 331e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 332e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 333e705c121SKalle Valo * that we wake up from L1 on time. 334e705c121SKalle Valo * 335e705c121SKalle Valo * This looks weird: read twice the same register, discard the 336e705c121SKalle Valo * value, set a bit, and yet again, read that same register 337e705c121SKalle Valo * just to discard the value. But that's the way the hardware 338e705c121SKalle Valo * seems to like it. 339e705c121SKalle Valo */ 340e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 341e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 342e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 343e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 344e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 345e705c121SKalle Valo } 346e705c121SKalle Valo 347e705c121SKalle Valo /* 348e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 349e705c121SKalle Valo * 350e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 351e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 352e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 353e705c121SKalle Valo */ 354e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 355e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 356e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 357e705c121SKalle Valo udelay(20); 358e705c121SKalle Valo 359e705c121SKalle Valo /* Disable L1-Active */ 360e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 361e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 362e705c121SKalle Valo 363e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 364e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 365e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 366e705c121SKalle Valo } 367e705c121SKalle Valo 368e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 369e705c121SKalle Valo 37052b6e168SEmmanuel Grumbach return 0; 371e705c121SKalle Valo } 372e705c121SKalle Valo 373e705c121SKalle Valo /* 374e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 375e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 376e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 377e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 378e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 379e705c121SKalle Valo */ 380e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 381e705c121SKalle Valo { 382e705c121SKalle Valo int ret; 383e705c121SKalle Valo u32 apmg_gp1_reg; 384e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 385e705c121SKalle Valo u32 dl_cfg_reg; 386e705c121SKalle Valo 387e705c121SKalle Valo /* Force XTAL ON */ 388e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 389e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 390e705c121SKalle Valo 39115bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 392e705c121SKalle Valo 39315bf5ac6SJohannes Berg if (!ret) 394425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 39515bf5ac6SJohannes Berg 396c96b5eecSJohannes Berg if (WARN_ON(ret)) { 397e705c121SKalle Valo /* Release XTAL ON request */ 398e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 399e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 400e705c121SKalle Valo return; 401e705c121SKalle Valo } 402e705c121SKalle Valo 403e705c121SKalle Valo /* 404e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 405e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 406e705c121SKalle Valo */ 407e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 408e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 409e705c121SKalle Valo 410e705c121SKalle Valo /* 411e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 412e705c121SKalle Valo * caused by APMG idle state. 413e705c121SKalle Valo */ 414e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 415e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 417e705c121SKalle Valo apmg_xtal_cfg_reg | 418e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 419e705c121SKalle Valo 42015bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 42115bf5ac6SJohannes Berg if (ret) 42215bf5ac6SJohannes Berg IWL_ERR(trans, 42315bf5ac6SJohannes Berg "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 424e705c121SKalle Valo 425e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 426e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 427e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 428e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 429e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 430e705c121SKalle Valo 431e705c121SKalle Valo /* Clear delay line clock power up */ 432e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 433e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 434e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 435e705c121SKalle Valo 436e705c121SKalle Valo /* 437e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 438e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 439e705c121SKalle Valo */ 440e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 441e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 442e705c121SKalle Valo 443e705c121SKalle Valo /* 444e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 445e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 446e705c121SKalle Valo */ 4476dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 448e705c121SKalle Valo 449e705c121SKalle Valo /* Activates XTAL resources monitor */ 450e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 451e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 452e705c121SKalle Valo 453e705c121SKalle Valo /* Release XTAL ON request */ 454e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 455e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 456e705c121SKalle Valo udelay(10); 457e705c121SKalle Valo 458e705c121SKalle Valo /* Release APMG XTAL */ 459e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 460e705c121SKalle Valo apmg_xtal_cfg_reg & 461e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 462e705c121SKalle Valo } 463e705c121SKalle Valo 464e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 465e705c121SKalle Valo { 466e8c8935eSJohannes Berg int ret; 467e705c121SKalle Valo 468e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4699ce041f5SJohannes Berg 4709ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4719ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4729ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4739ce041f5SJohannes Berg 4749ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4759ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4769ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4779ce041f5SJohannes Berg 100); 47844b2dd40SRoee Goldfiner msleep(100); 4799ce041f5SJohannes Berg } else { 4806dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 481e705c121SKalle Valo 4826dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4836dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4846dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4859ce041f5SJohannes Berg } 4869ce041f5SJohannes Berg 487e705c121SKalle Valo if (ret < 0) 488e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 489e705c121SKalle Valo 490e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 491e705c121SKalle Valo } 492e705c121SKalle Valo 493e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 494e705c121SKalle Valo { 495e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 496e705c121SKalle Valo 497e705c121SKalle Valo if (op_mode_leave) { 498e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 499e705c121SKalle Valo iwl_pcie_apm_init(trans); 500e705c121SKalle Valo 501e705c121SKalle Valo /* inform ME that we are leaving */ 502286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 503e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 504e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 505286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 50679b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 507e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 508e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 509e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 510e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 511e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 512e705c121SKalle Valo mdelay(1); 513e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 514e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 515e705c121SKalle Valo } 516e705c121SKalle Valo mdelay(5); 517e705c121SKalle Valo } 518e705c121SKalle Valo 519e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 520e705c121SKalle Valo 521e705c121SKalle Valo /* Stop device's DMA activity */ 522e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 523e705c121SKalle Valo 524e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 525e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 526e705c121SKalle Valo return; 527e705c121SKalle Valo } 528e705c121SKalle Valo 52915bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, false); 530e705c121SKalle Valo 531e705c121SKalle Valo /* 532e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 533e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 534e705c121SKalle Valo */ 5356dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 536e705c121SKalle Valo } 537e705c121SKalle Valo 538e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 539e705c121SKalle Valo { 540e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 54152b6e168SEmmanuel Grumbach int ret; 542e705c121SKalle Valo 543e705c121SKalle Valo /* nic_init */ 54425edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 54552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 54625edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 547e705c121SKalle Valo 54852b6e168SEmmanuel Grumbach if (ret) 54952b6e168SEmmanuel Grumbach return ret; 55052b6e168SEmmanuel Grumbach 551e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 552e705c121SKalle Valo 553e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 554e705c121SKalle Valo 555e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5569cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5579cf671d6SEmmanuel Grumbach if (ret) 5589cf671d6SEmmanuel Grumbach return ret; 559e705c121SKalle Valo 560e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5619cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5629cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 563e705c121SKalle Valo return -ENOMEM; 5649cf671d6SEmmanuel Grumbach } 565e705c121SKalle Valo 566286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 567e705c121SKalle Valo /* enable shadow regs in HW */ 568e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 569e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 570e705c121SKalle Valo } 571e705c121SKalle Valo 572e705c121SKalle Valo return 0; 573e705c121SKalle Valo } 574e705c121SKalle Valo 575e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 576e705c121SKalle Valo 577e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 578e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 579e705c121SKalle Valo { 580e705c121SKalle Valo int ret; 581e705c121SKalle Valo 582e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 583e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 584e705c121SKalle Valo 585e705c121SKalle Valo /* See if we got it */ 586e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 587e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 588e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 589e705c121SKalle Valo HW_READY_TIMEOUT); 590e705c121SKalle Valo 591e705c121SKalle Valo if (ret >= 0) 592e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 593e705c121SKalle Valo 594e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 595e705c121SKalle Valo return ret; 596e705c121SKalle Valo } 597e705c121SKalle Valo 598e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 599eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 600e705c121SKalle Valo { 601e705c121SKalle Valo int ret; 602e705c121SKalle Valo int t = 0; 603e705c121SKalle Valo int iter; 604e705c121SKalle Valo 605e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 606e705c121SKalle Valo 607e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 608e705c121SKalle Valo /* If the card is ready, exit 0 */ 6096d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6106d19a5ebSEmmanuel Grumbach trans->csme_own = false; 611e705c121SKalle Valo return 0; 6126d19a5ebSEmmanuel Grumbach } 613e705c121SKalle Valo 614e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 615e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 616192185d6SJohannes Berg usleep_range(1000, 2000); 617e705c121SKalle Valo 618e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 619e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 620e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 621e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 622e705c121SKalle Valo 623e705c121SKalle Valo do { 624e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 6256d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6266d19a5ebSEmmanuel Grumbach trans->csme_own = false; 627e705c121SKalle Valo return 0; 6286d19a5ebSEmmanuel Grumbach } 6296d19a5ebSEmmanuel Grumbach 6306d19a5ebSEmmanuel Grumbach if (iwl_mei_is_connected()) { 6316d19a5ebSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 6326d19a5ebSEmmanuel Grumbach "Couldn't prepare the card but SAP is connected\n"); 6336d19a5ebSEmmanuel Grumbach trans->csme_own = true; 6346d19a5ebSEmmanuel Grumbach if (trans->trans_cfg->device_family != 6356d19a5ebSEmmanuel Grumbach IWL_DEVICE_FAMILY_9000) 6366d19a5ebSEmmanuel Grumbach IWL_ERR(trans, 6376d19a5ebSEmmanuel Grumbach "SAP not supported for this NIC family\n"); 6386d19a5ebSEmmanuel Grumbach 6396d19a5ebSEmmanuel Grumbach return -EBUSY; 6406d19a5ebSEmmanuel Grumbach } 641e705c121SKalle Valo 642e705c121SKalle Valo usleep_range(200, 1000); 643e705c121SKalle Valo t += 200; 644e705c121SKalle Valo } while (t < 150000); 645e705c121SKalle Valo msleep(25); 646e705c121SKalle Valo } 647e705c121SKalle Valo 648e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 649e705c121SKalle Valo 650e705c121SKalle Valo return ret; 651e705c121SKalle Valo } 652e705c121SKalle Valo 653e705c121SKalle Valo /* 654e705c121SKalle Valo * ucode 655e705c121SKalle Valo */ 656564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 657564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 658564cdce7SSara Sharon u32 byte_cnt) 659e705c121SKalle Valo { 660bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 661e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 662e705c121SKalle Valo 663bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 664e705c121SKalle Valo dst_addr); 665e705c121SKalle Valo 666bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 667e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 668e705c121SKalle Valo 669bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 670e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 671e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 672e705c121SKalle Valo 673bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 674bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 675bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 676e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 677e705c121SKalle Valo 678bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 679e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 680e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 681e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 682564cdce7SSara Sharon } 683e705c121SKalle Valo 684564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 685564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 686564cdce7SSara Sharon u32 byte_cnt) 687564cdce7SSara Sharon { 688564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 689564cdce7SSara Sharon int ret; 690564cdce7SSara Sharon 691564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 692564cdce7SSara Sharon 6931ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 694564cdce7SSara Sharon return -EIO; 695564cdce7SSara Sharon 696564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 697564cdce7SSara Sharon byte_cnt); 6981ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 699bac842daSEmmanuel Grumbach 700e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 701e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 702e705c121SKalle Valo if (!ret) { 703e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 704fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 705e705c121SKalle Valo return -ETIMEDOUT; 706e705c121SKalle Valo } 707e705c121SKalle Valo 708e705c121SKalle Valo return 0; 709e705c121SKalle Valo } 710e705c121SKalle Valo 711e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 712e705c121SKalle Valo const struct fw_desc *section) 713e705c121SKalle Valo { 714e705c121SKalle Valo u8 *v_addr; 715e705c121SKalle Valo dma_addr_t p_addr; 716e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 717e705c121SKalle Valo int ret = 0; 718e705c121SKalle Valo 719e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 720e705c121SKalle Valo section_num); 721e705c121SKalle Valo 722e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 723e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 724e705c121SKalle Valo if (!v_addr) { 725e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 726e705c121SKalle Valo chunk_sz = PAGE_SIZE; 727e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 728e705c121SKalle Valo &p_addr, GFP_KERNEL); 729e705c121SKalle Valo if (!v_addr) 730e705c121SKalle Valo return -ENOMEM; 731e705c121SKalle Valo } 732e705c121SKalle Valo 733e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 734e705c121SKalle Valo u32 copy_size, dst_addr; 735e705c121SKalle Valo bool extended_addr = false; 736e705c121SKalle Valo 737e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 738e705c121SKalle Valo dst_addr = section->offset + offset; 739e705c121SKalle Valo 740e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 741e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 742e705c121SKalle Valo extended_addr = true; 743e705c121SKalle Valo 744e705c121SKalle Valo if (extended_addr) 745e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 746e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 747e705c121SKalle Valo 74873c289baSBjoern A. Zeeb memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 749e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 750e705c121SKalle Valo copy_size); 751e705c121SKalle Valo 752e705c121SKalle Valo if (extended_addr) 753e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 754e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 755e705c121SKalle Valo 756e705c121SKalle Valo if (ret) { 757e705c121SKalle Valo IWL_ERR(trans, 758e705c121SKalle Valo "Could not load the [%d] uCode section\n", 759e705c121SKalle Valo section_num); 760e705c121SKalle Valo break; 761e705c121SKalle Valo } 762e705c121SKalle Valo } 763e705c121SKalle Valo 764e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 765e705c121SKalle Valo return ret; 766e705c121SKalle Valo } 767e705c121SKalle Valo 768e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 769e705c121SKalle Valo const struct fw_img *image, 770e705c121SKalle Valo int cpu, 771e705c121SKalle Valo int *first_ucode_section) 772e705c121SKalle Valo { 773e705c121SKalle Valo int shift_param; 774e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 775e705c121SKalle Valo u32 val, last_read_idx = 0; 776e705c121SKalle Valo 777e705c121SKalle Valo if (cpu == 1) { 778e705c121SKalle Valo shift_param = 0; 779e705c121SKalle Valo *first_ucode_section = 0; 780e705c121SKalle Valo } else { 781e705c121SKalle Valo shift_param = 16; 782e705c121SKalle Valo (*first_ucode_section)++; 783e705c121SKalle Valo } 784e705c121SKalle Valo 785eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 786e705c121SKalle Valo last_read_idx = i; 787e705c121SKalle Valo 788e705c121SKalle Valo /* 789e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 790e705c121SKalle Valo * CPU1 to CPU2. 791e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 792e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 793e705c121SKalle Valo */ 794e705c121SKalle Valo if (!image->sec[i].data || 795e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 796e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 797e705c121SKalle Valo IWL_DEBUG_FW(trans, 798e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 799e705c121SKalle Valo i); 800e705c121SKalle Valo break; 801e705c121SKalle Valo } 802e705c121SKalle Valo 803e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 804e705c121SKalle Valo if (ret) 805e705c121SKalle Valo return ret; 806e705c121SKalle Valo 807d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 808e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 809e705c121SKalle Valo val = val | (sec_num << shift_param); 810e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 811eda50cdeSSara Sharon 812e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 813e705c121SKalle Valo } 814e705c121SKalle Valo 815e705c121SKalle Valo *first_ucode_section = last_read_idx; 816e705c121SKalle Valo 8172aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8182aabdbdcSEmmanuel Grumbach 819286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 820e705c121SKalle Valo if (cpu == 1) 821d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 822d6a2c5c7SSara Sharon 0xFFFF); 823e705c121SKalle Valo else 824d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 825d6a2c5c7SSara Sharon 0xFFFFFFFF); 826d6a2c5c7SSara Sharon } else { 827d6a2c5c7SSara Sharon if (cpu == 1) 828d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 829d6a2c5c7SSara Sharon 0xFFFF); 830d6a2c5c7SSara Sharon else 831d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 832d6a2c5c7SSara Sharon 0xFFFFFFFF); 833d6a2c5c7SSara Sharon } 834e705c121SKalle Valo 835e705c121SKalle Valo return 0; 836e705c121SKalle Valo } 837e705c121SKalle Valo 838e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 839e705c121SKalle Valo const struct fw_img *image, 840e705c121SKalle Valo int cpu, 841e705c121SKalle Valo int *first_ucode_section) 842e705c121SKalle Valo { 843e705c121SKalle Valo int i, ret = 0; 844e705c121SKalle Valo u32 last_read_idx = 0; 845e705c121SKalle Valo 8463ce4a038SKirtika Ruchandani if (cpu == 1) 847e705c121SKalle Valo *first_ucode_section = 0; 8483ce4a038SKirtika Ruchandani else 849e705c121SKalle Valo (*first_ucode_section)++; 850e705c121SKalle Valo 851eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 852e705c121SKalle Valo last_read_idx = i; 853e705c121SKalle Valo 854e705c121SKalle Valo /* 855e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 856e705c121SKalle Valo * CPU1 to CPU2. 857e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 858e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 859e705c121SKalle Valo */ 860e705c121SKalle Valo if (!image->sec[i].data || 861e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 862e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 863e705c121SKalle Valo IWL_DEBUG_FW(trans, 864e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 865e705c121SKalle Valo i); 866e705c121SKalle Valo break; 867e705c121SKalle Valo } 868e705c121SKalle Valo 869e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 870e705c121SKalle Valo if (ret) 871e705c121SKalle Valo return ret; 872e705c121SKalle Valo } 873e705c121SKalle Valo 874e705c121SKalle Valo *first_ucode_section = last_read_idx; 875e705c121SKalle Valo 876e705c121SKalle Valo return 0; 877e705c121SKalle Valo } 878e705c121SKalle Valo 879593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 880593fae3eSShahar S Matityahu { 881593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 882593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 883593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 884593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 885593fae3eSShahar S Matityahu 886593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 887593fae3eSShahar S Matityahu return; 888593fae3eSShahar S Matityahu 889593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 890593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 891593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 892593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 893593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 894593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 895593fae3eSShahar S Matityahu 896593fae3eSShahar S Matityahu return; 897593fae3eSShahar S Matityahu } 898593fae3eSShahar S Matityahu 899593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 900593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 901593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 902593fae3eSShahar S Matityahu return; 903593fae3eSShahar S Matityahu 904593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 905593fae3eSShahar S Matityahu 906593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 907593fae3eSShahar S Matityahu alloc_id); 908593fae3eSShahar S Matityahu 909593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 910593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 911593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 912593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 913593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 914593fae3eSShahar S Matityahu } 915593fae3eSShahar S Matityahu 916c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 917e705c121SKalle Valo { 91891c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 91969f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 920e705c121SKalle Valo int i; 921e705c121SKalle Valo 922a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 923593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9247a14c23dSSara Sharon return; 9257a14c23dSSara Sharon } 9267a14c23dSSara Sharon 927e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 928e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 929e705c121SKalle Valo 930e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 931e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 932e705c121SKalle Valo else 933e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 934e705c121SKalle Valo 93591c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 936e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 937e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 938e705c121SKalle Valo 939e705c121SKalle Valo switch (dest->reg_ops[i].op) { 940e705c121SKalle Valo case CSR_ASSIGN: 941e705c121SKalle Valo iwl_write32(trans, addr, val); 942e705c121SKalle Valo break; 943e705c121SKalle Valo case CSR_SETBIT: 944e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 945e705c121SKalle Valo break; 946e705c121SKalle Valo case CSR_CLEARBIT: 947e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 948e705c121SKalle Valo break; 949e705c121SKalle Valo case PRPH_ASSIGN: 950e705c121SKalle Valo iwl_write_prph(trans, addr, val); 951e705c121SKalle Valo break; 952e705c121SKalle Valo case PRPH_SETBIT: 953e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 954e705c121SKalle Valo break; 955e705c121SKalle Valo case PRPH_CLEARBIT: 956e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 957e705c121SKalle Valo break; 958e705c121SKalle Valo case PRPH_BLOCKBIT: 959e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 960e705c121SKalle Valo IWL_ERR(trans, 961e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 962e705c121SKalle Valo val, addr); 963e705c121SKalle Valo goto monitor; 964e705c121SKalle Valo } 965e705c121SKalle Valo break; 966e705c121SKalle Valo default: 967e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 968e705c121SKalle Valo dest->reg_ops[i].op); 969e705c121SKalle Valo break; 970e705c121SKalle Valo } 971e705c121SKalle Valo } 972e705c121SKalle Valo 973e705c121SKalle Valo monitor: 97469f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 975e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 97669f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 977286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 978e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97969f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 98069f0e505SShahar S Matityahu 256) >> dest->end_shift); 98162d7476dSEmmanuel Grumbach else 98262d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98369f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 98462d7476dSEmmanuel Grumbach dest->end_shift); 985e705c121SKalle Valo } 986e705c121SKalle Valo } 987e705c121SKalle Valo 988e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 989e705c121SKalle Valo const struct fw_img *image) 990e705c121SKalle Valo { 991e705c121SKalle Valo int ret = 0; 992e705c121SKalle Valo int first_ucode_section; 993e705c121SKalle Valo 994e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 995e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 996e705c121SKalle Valo 997e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 998e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 999e705c121SKalle Valo if (ret) 1000e705c121SKalle Valo return ret; 1001e705c121SKalle Valo 1002e705c121SKalle Valo if (image->is_dual_cpus) { 1003e705c121SKalle Valo /* set CPU2 header address */ 1004e705c121SKalle Valo iwl_write_prph(trans, 1005e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1006e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1007e705c121SKalle Valo 1008e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1009e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1010e705c121SKalle Valo &first_ucode_section); 1011e705c121SKalle Valo if (ret) 1012e705c121SKalle Valo return ret; 1013e705c121SKalle Valo } 1014e705c121SKalle Valo 10159efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 1016e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1017e705c121SKalle Valo 10182aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10192aabdbdcSEmmanuel Grumbach 1020e705c121SKalle Valo /* release CPU reset */ 1021e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1022e705c121SKalle Valo 1023e705c121SKalle Valo return 0; 1024e705c121SKalle Valo } 1025e705c121SKalle Valo 1026e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1027e705c121SKalle Valo const struct fw_img *image) 1028e705c121SKalle Valo { 1029e705c121SKalle Valo int ret = 0; 1030e705c121SKalle Valo int first_ucode_section; 1031e705c121SKalle Valo 1032e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1033e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1034e705c121SKalle Valo 10357a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1036e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1037e705c121SKalle Valo 103882ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 103982ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 104082ea7966SSara Sharon 104182ea7966SSara Sharon /* 104282ea7966SSara Sharon * Set default value. On resume reading the values that were 104382ea7966SSara Sharon * zeored can provide debug data on the resume flow. 104482ea7966SSara Sharon * This is for debugging only and has no functional impact. 104582ea7966SSara Sharon */ 104682ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 104782ea7966SSara Sharon 1048e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1049e705c121SKalle Valo /* release CPU reset */ 1050e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1051e705c121SKalle Valo 1052e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1053e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1054e705c121SKalle Valo &first_ucode_section); 1055e705c121SKalle Valo if (ret) 1056e705c121SKalle Valo return ret; 1057e705c121SKalle Valo 1058e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1059e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1060e705c121SKalle Valo &first_ucode_section); 1061e705c121SKalle Valo } 1062e705c121SKalle Valo 10639ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1064727c02dfSSara Sharon { 1065326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1066727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1067326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1068326477e4SJohannes Berg bool report; 1069727c02dfSSara Sharon 1070326477e4SJohannes Berg if (hw_rfkill) { 1071326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1072326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1073326477e4SJohannes Berg } else { 1074326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1075326477e4SJohannes Berg if (trans_pcie->opmode_down) 1076326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1077326477e4SJohannes Berg } 1078727c02dfSSara Sharon 1079326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1080326477e4SJohannes Berg 1081326477e4SJohannes Berg if (prev != report) 1082326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1083727c02dfSSara Sharon 1084727c02dfSSara Sharon return hw_rfkill; 1085727c02dfSSara Sharon } 1086727c02dfSSara Sharon 10877ca00409SHaim Dreyfuss struct iwl_causes_list { 1088c1918196SJohannes Berg u16 mask_reg; 1089c1918196SJohannes Berg u8 bit; 10907ca00409SHaim Dreyfuss u8 addr; 10917ca00409SHaim Dreyfuss }; 10927ca00409SHaim Dreyfuss 10939c683731SJohannes Berg #define IWL_CAUSE(reg, mask) \ 1094c1918196SJohannes Berg { \ 1095c1918196SJohannes Berg .mask_reg = reg, \ 1096c1918196SJohannes Berg .bit = ilog2(mask), \ 1097c1918196SJohannes Berg .addr = ilog2(mask) + \ 1098c1918196SJohannes Berg ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1099c1918196SJohannes Berg (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1100c1918196SJohannes Berg 0xffff), /* causes overflow warning */ \ 1101c1918196SJohannes Berg } 1102c1918196SJohannes Berg 1103571836a0SMike Golant static const struct iwl_causes_list causes_list_common[] = { 11049c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 11059c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 11069c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 11079c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 11089c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 11099c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 11109c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 11119c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 11129c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 11139c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 11149c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 11159c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 11169c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 11179c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 11187ca00409SHaim Dreyfuss }; 11197ca00409SHaim Dreyfuss 1120571836a0SMike Golant static const struct iwl_causes_list causes_list_pre_bz[] = { 11219c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1122571836a0SMike Golant }; 11237ca00409SHaim Dreyfuss 1124571836a0SMike Golant static const struct iwl_causes_list causes_list_bz[] = { 11259c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1126571836a0SMike Golant }; 1127571836a0SMike Golant 1128571836a0SMike Golant static void iwl_pcie_map_list(struct iwl_trans *trans, 1129571836a0SMike Golant const struct iwl_causes_list *causes, 1130571836a0SMike Golant int arr_size, int val) 1131571836a0SMike Golant { 1132571836a0SMike Golant int i; 1133571836a0SMike Golant 11349b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11359b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11369b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 1137c1918196SJohannes Berg BIT(causes[i].bit)); 11387ca00409SHaim Dreyfuss } 11397ca00409SHaim Dreyfuss } 11407ca00409SHaim Dreyfuss 1141571836a0SMike Golant static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1142571836a0SMike Golant { 1143571836a0SMike Golant struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1144571836a0SMike Golant int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1145571836a0SMike Golant /* 1146571836a0SMike Golant * Access all non RX causes and map them to the default irq. 1147571836a0SMike Golant * In case we are missing at least one interrupt vector, 1148571836a0SMike Golant * the first interrupt vector will serve non-RX and FBQ causes. 1149571836a0SMike Golant */ 1150571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_common, 1151571836a0SMike Golant ARRAY_SIZE(causes_list_common), val); 1152571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1153571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_bz, 1154571836a0SMike Golant ARRAY_SIZE(causes_list_bz), val); 1155571836a0SMike Golant else 1156571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_pre_bz, 1157571836a0SMike Golant ARRAY_SIZE(causes_list_pre_bz), val); 1158571836a0SMike Golant } 1159571836a0SMike Golant 11607ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11617ca00409SHaim Dreyfuss { 11627ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11637ca00409SHaim Dreyfuss u32 offset = 11647ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11657ca00409SHaim Dreyfuss u32 val, idx; 11667ca00409SHaim Dreyfuss 11677ca00409SHaim Dreyfuss /* 11687ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11697ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11707ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11717ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11727ca00409SHaim Dreyfuss */ 11737ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11747ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11757ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11767ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11777ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11787ca00409SHaim Dreyfuss } 11797ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11807ca00409SHaim Dreyfuss 11817ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11827ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11837ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11847ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11857ca00409SHaim Dreyfuss 11867ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11877ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11887ca00409SHaim Dreyfuss } 11897ca00409SHaim Dreyfuss 119077c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11917ca00409SHaim Dreyfuss { 11927ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11937ca00409SHaim Dreyfuss 11947ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1195286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1196d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1197ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11987ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11997ca00409SHaim Dreyfuss return; 12007ca00409SHaim Dreyfuss } 1201d7270d61SHaim Dreyfuss /* 1202d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1203d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1204d7270d61SHaim Dreyfuss * prph. 1205d7270d61SHaim Dreyfuss */ 1206d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1207ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12087ca00409SHaim Dreyfuss 12097ca00409SHaim Dreyfuss /* 12107ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12117ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12127ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12137ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12147ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12157ca00409SHaim Dreyfuss */ 12167ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12177ca00409SHaim Dreyfuss 12187ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 121983730058SHaim Dreyfuss } 12207ca00409SHaim Dreyfuss 122183730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122283730058SHaim Dreyfuss { 122383730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122483730058SHaim Dreyfuss 122583730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122683730058SHaim Dreyfuss 122783730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 122883730058SHaim Dreyfuss return; 122983730058SHaim Dreyfuss 123083730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12317ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123283730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12337ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12347ca00409SHaim Dreyfuss } 12357ca00409SHaim Dreyfuss 1236bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1237e705c121SKalle Valo { 1238e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1239e705c121SKalle Valo 1240e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1241e705c121SKalle Valo 1242e705c121SKalle Valo if (trans_pcie->is_down) 1243e705c121SKalle Valo return; 1244e705c121SKalle Valo 1245e705c121SKalle Valo trans_pcie->is_down = true; 1246e705c121SKalle Valo 1247e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1248e705c121SKalle Valo iwl_disable_interrupts(trans); 1249e705c121SKalle Valo 1250e705c121SKalle Valo /* device going down, Stop using ICT table */ 1251e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1252e705c121SKalle Valo 1253e705c121SKalle Valo /* 1254e705c121SKalle Valo * If a HW restart happens during firmware loading, 1255e705c121SKalle Valo * then the firmware loading might call this function 1256e705c121SKalle Valo * and later it might be called again due to the 1257e705c121SKalle Valo * restart. So don't process again if the device is 1258e705c121SKalle Valo * already dead. 1259e705c121SKalle Valo */ 1260e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1261a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1262a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1263e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1264e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1265e705c121SKalle Valo 1266e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1267e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1268e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1269e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1270e705c121SKalle Valo udelay(5); 1271e705c121SKalle Valo } 1272e705c121SKalle Valo } 1273e705c121SKalle Valo 1274e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 12751b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 12761b6598c3SRoee Goldfiner iwl_clear_bit(trans, CSR_GP_CNTRL, 12771b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 12781b6598c3SRoee Goldfiner else 1279e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12806dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1281e705c121SKalle Valo 1282e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1283e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1284e705c121SKalle Valo 128515bf5ac6SJohannes Berg /* re-take ownership to prevent other users from stealing the device */ 128615bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, true); 1287e705c121SKalle Valo 1288e705c121SKalle Valo /* 1289f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1290f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1291f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1292f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1293f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1294f4a1f04aSGolan Ben Ami */ 1295f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1296f4a1f04aSGolan Ben Ami 1297f4a1f04aSGolan Ben Ami /* 1298e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1299e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1300e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1301e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1302e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1303e705c121SKalle Valo */ 1304e705c121SKalle Valo iwl_disable_interrupts(trans); 1305e705c121SKalle Valo 1306e705c121SKalle Valo /* clear all status bits */ 1307e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1308e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1309e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1310e705c121SKalle Valo 1311e705c121SKalle Valo /* 1312e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1313e705c121SKalle Valo * interrupt 1314e705c121SKalle Valo */ 1315e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1316e705c121SKalle Valo } 1317e705c121SKalle Valo 1318eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13192e5d4a8fSHaim Dreyfuss { 13202e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13212e5d4a8fSHaim Dreyfuss 13222e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13232e5d4a8fSHaim Dreyfuss int i; 13242e5d4a8fSHaim Dreyfuss 1325496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13262e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13272e5d4a8fSHaim Dreyfuss } else { 13282e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13292e5d4a8fSHaim Dreyfuss } 13302e5d4a8fSHaim Dreyfuss } 13312e5d4a8fSHaim Dreyfuss 1332a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1333a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1334a6bd005fSEmmanuel Grumbach { 1335a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1336a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1337a6bd005fSEmmanuel Grumbach int ret; 1338a6bd005fSEmmanuel Grumbach 1339a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1340a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1341a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1342e9848aedSJohannes Berg return -EIO; 1343a6bd005fSEmmanuel Grumbach } 1344a6bd005fSEmmanuel Grumbach 1345a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1346a6bd005fSEmmanuel Grumbach 1347a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1348a6bd005fSEmmanuel Grumbach 1349a6bd005fSEmmanuel Grumbach /* 1350a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1351a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1352a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1353a6bd005fSEmmanuel Grumbach */ 1354a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1355a6bd005fSEmmanuel Grumbach 1356a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13572e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1358a6bd005fSEmmanuel Grumbach 1359a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1360a6bd005fSEmmanuel Grumbach 1361a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13629ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1363a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1364a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1365a6bd005fSEmmanuel Grumbach goto out; 1366a6bd005fSEmmanuel Grumbach } 1367a6bd005fSEmmanuel Grumbach 1368a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1369a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1370a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1371a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 137220aa99bbSAnton Protopopov ret = -EIO; 1373a6bd005fSEmmanuel Grumbach goto out; 1374a6bd005fSEmmanuel Grumbach } 1375a6bd005fSEmmanuel Grumbach 1376a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1377a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1378a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1379a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1382a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1383a6bd005fSEmmanuel Grumbach 1384a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1385a6bd005fSEmmanuel Grumbach if (ret) { 1386a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1387a6bd005fSEmmanuel Grumbach goto out; 1388a6bd005fSEmmanuel Grumbach } 1389a6bd005fSEmmanuel Grumbach 1390a6bd005fSEmmanuel Grumbach /* 1391a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1392a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1393a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1394a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1395a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1396a6bd005fSEmmanuel Grumbach */ 1397a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1398a6bd005fSEmmanuel Grumbach 1399a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1400a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1401a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1402a6bd005fSEmmanuel Grumbach 1403a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1404286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1405a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1406a6bd005fSEmmanuel Grumbach else 1407a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1408a6bd005fSEmmanuel Grumbach 1409a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14109ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1411a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1412a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1413a6bd005fSEmmanuel Grumbach 1414a6bd005fSEmmanuel Grumbach out: 1415a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1416a6bd005fSEmmanuel Grumbach return ret; 1417a6bd005fSEmmanuel Grumbach } 1418a6bd005fSEmmanuel Grumbach 1419a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1420a6bd005fSEmmanuel Grumbach { 1421a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1422a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1423a6bd005fSEmmanuel Grumbach } 1424a6bd005fSEmmanuel Grumbach 1425326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1426326477e4SJohannes Berg bool was_in_rfkill) 1427326477e4SJohannes Berg { 1428326477e4SJohannes Berg bool hw_rfkill; 1429326477e4SJohannes Berg 1430326477e4SJohannes Berg /* 1431326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1432326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1433326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1434326477e4SJohannes Berg * op_mode. 1435326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1436326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1437326477e4SJohannes Berg * notification without endless recursion. Under very rare 1438326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1439326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1440326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1441326477e4SJohannes Berg */ 1442326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1443326477e4SJohannes Berg if (hw_rfkill) { 1444326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1445326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1446326477e4SJohannes Berg } else { 1447326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1448326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1449326477e4SJohannes Berg } 1450326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1451326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1452326477e4SJohannes Berg } 1453326477e4SJohannes Berg 1454bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1455e705c121SKalle Valo { 1456e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1457326477e4SJohannes Berg bool was_in_rfkill; 1458e705c121SKalle Valo 1459d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1460d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1461d0129315SMordechay Goodstein NULL); 1462d0129315SMordechay Goodstein 1463e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1464326477e4SJohannes Berg trans_pcie->opmode_down = true; 1465326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1466bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1467326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1468e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1469e705c121SKalle Valo } 1470e705c121SKalle Valo 1471e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1472e705c121SKalle Valo { 1473e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1474e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1475e705c121SKalle Valo 1476e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1477e705c121SKalle Valo 1478326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1479326477e4SJohannes Berg state ? "disabled" : "enabled"); 148077c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1481286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1482bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 148377c09bc8SSara Sharon else 1484bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1485e705c121SKalle Valo } 148677c09bc8SSara Sharon } 1487e705c121SKalle Valo 1488e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1489e5f3f215SHaim Dreyfuss bool test, bool reset) 1490e705c121SKalle Valo { 1491e705c121SKalle Valo iwl_disable_interrupts(trans); 1492e705c121SKalle Valo 1493e705c121SKalle Valo /* 1494e705c121SKalle Valo * in testing mode, the host stays awake and the 1495e705c121SKalle Valo * hardware won't be reset (not even partially) 1496e705c121SKalle Valo */ 1497e705c121SKalle Valo if (test) 1498e705c121SKalle Valo return; 1499e705c121SKalle Valo 1500e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1501e705c121SKalle Valo 15022e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1503e705c121SKalle Valo 1504e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15056dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 15066dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1507e705c121SKalle Valo 150823ae6128SMatti Gottlieb if (reset) { 1509e705c121SKalle Valo /* 1510e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1511e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1512e705c121SKalle Valo * to execute some invalid memory upon resume 1513e705c121SKalle Valo */ 1514e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1515e705c121SKalle Valo } 1516e705c121SKalle Valo 1517e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1518e705c121SKalle Valo } 1519e705c121SKalle Valo 1520af08571dSHaim Dreyfuss static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1521af08571dSHaim Dreyfuss { 1522af08571dSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1523af08571dSHaim Dreyfuss int ret; 1524af08571dSHaim Dreyfuss 1525af08571dSHaim Dreyfuss if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 1526af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1527af08571dSHaim Dreyfuss suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1528af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1529af08571dSHaim Dreyfuss } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1530af08571dSHaim Dreyfuss iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1531af08571dSHaim Dreyfuss suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1532af08571dSHaim Dreyfuss CSR_IPC_SLEEP_CONTROL_RESUME); 1533af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1534af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SLEEP_CTRL); 1535af08571dSHaim Dreyfuss } else { 1536af08571dSHaim Dreyfuss return 0; 1537af08571dSHaim Dreyfuss } 1538af08571dSHaim Dreyfuss 1539af08571dSHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1540af08571dSHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1541af08571dSHaim Dreyfuss 1542af08571dSHaim Dreyfuss /* Invalidate it toward next suspend or resume */ 1543af08571dSHaim Dreyfuss trans_pcie->sx_complete = false; 1544af08571dSHaim Dreyfuss 1545af08571dSHaim Dreyfuss if (!ret) { 1546af08571dSHaim Dreyfuss IWL_ERR(trans, "Timeout %s D3\n", 1547af08571dSHaim Dreyfuss suspend ? "entering" : "exiting"); 1548af08571dSHaim Dreyfuss return -ETIMEDOUT; 1549af08571dSHaim Dreyfuss } 1550af08571dSHaim Dreyfuss 1551af08571dSHaim Dreyfuss return 0; 1552af08571dSHaim Dreyfuss } 1553af08571dSHaim Dreyfuss 1554e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1555e5f3f215SHaim Dreyfuss bool reset) 1556e5f3f215SHaim Dreyfuss { 1557e5f3f215SHaim Dreyfuss int ret; 1558e5f3f215SHaim Dreyfuss 1559771db3a1SHaim Dreyfuss if (!reset) 1560e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1561e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1562e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1563e5f3f215SHaim Dreyfuss 1564af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, true); 1565af08571dSHaim Dreyfuss if (ret) 1566af08571dSHaim Dreyfuss return ret; 1567e5f3f215SHaim Dreyfuss 1568e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1569e5f3f215SHaim Dreyfuss 1570e5f3f215SHaim Dreyfuss return 0; 1571e5f3f215SHaim Dreyfuss } 1572e5f3f215SHaim Dreyfuss 1573e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1574e705c121SKalle Valo enum iwl_d3_status *status, 157523ae6128SMatti Gottlieb bool test, bool reset) 1576e705c121SKalle Valo { 1577d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1578e705c121SKalle Valo u32 val; 1579e705c121SKalle Valo int ret; 1580e705c121SKalle Valo 1581e705c121SKalle Valo if (test) { 1582e705c121SKalle Valo iwl_enable_interrupts(trans); 1583e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1584af08571dSHaim Dreyfuss ret = 0; 1585e5f3f215SHaim Dreyfuss goto out; 1586e705c121SKalle Valo } 1587e705c121SKalle Valo 1588a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15896dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1590e705c121SKalle Valo 1591425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 1592c96b5eecSJohannes Berg if (ret) 1593e705c121SKalle Valo return ret; 1594e705c121SKalle Valo 1595f98ad635SEmmanuel Grumbach /* 1596f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1597f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1598f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1599f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1600f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1601f98ad635SEmmanuel Grumbach */ 1602f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1603f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1604f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1605f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1606f98ad635SEmmanuel Grumbach 1607e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1608e705c121SKalle Valo 160923ae6128SMatti Gottlieb if (!reset) { 1610e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 16116dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1612e705c121SKalle Valo } else { 1613e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1614e705c121SKalle Valo 1615e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1616e705c121SKalle Valo if (ret) { 1617e705c121SKalle Valo IWL_ERR(trans, 1618e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1619e705c121SKalle Valo return ret; 1620e705c121SKalle Valo } 1621e705c121SKalle Valo } 1622e705c121SKalle Valo 162382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1624ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 162582ea7966SSara Sharon 1626e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1627e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1628e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1629e705c121SKalle Valo else 1630e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1631e705c121SKalle Valo 1632e5f3f215SHaim Dreyfuss out: 1633af08571dSHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE) 1634af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, false); 1635e5f3f215SHaim Dreyfuss 1636af08571dSHaim Dreyfuss return ret; 1637e705c121SKalle Valo } 1638e705c121SKalle Valo 16390c18714aSLuca Coelho static void 16400c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16410c18714aSLuca Coelho struct iwl_trans *trans, 16420c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16432e5d4a8fSHaim Dreyfuss { 16442e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1645ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16462e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16470cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 16482e5d4a8fSHaim Dreyfuss 16490c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 165006f4b081SSara Sharon goto enable_msi; 165106f4b081SSara Sharon 16520cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 16530cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 16540cd38f4dSMordechay Goodstein 16550cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 165606f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16572e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16582e5d4a8fSHaim Dreyfuss 165906f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16602e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 166106f4b081SSara Sharon max_irqs); 166206f4b081SSara Sharon if (num_irqs < 0) { 1663496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 166406f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 166506f4b081SSara Sharon num_irqs); 166606f4b081SSara Sharon goto enable_msi; 1667496d83caSHaim Dreyfuss } 166806f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1669496d83caSHaim Dreyfuss 16702e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 167106f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 167206f4b081SSara Sharon num_irqs); 167306f4b081SSara Sharon 1674496d83caSHaim Dreyfuss /* 167506f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 167606f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1677496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1678496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1679496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1680496d83caSHaim Dreyfuss */ 1681ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 168206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1683496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1684496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1685ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 168606f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1687496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1688496d83caSHaim Dreyfuss } else { 168906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1690496d83caSHaim Dreyfuss } 16919d401222SMordechay Goodstein 16929d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16939d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16949d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16959d401222SMordechay Goodstein 1696ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16972e5d4a8fSHaim Dreyfuss 169806f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1699496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 17002e5d4a8fSHaim Dreyfuss return; 17012e5d4a8fSHaim Dreyfuss 170206f4b081SSara Sharon enable_msi: 170306f4b081SSara Sharon ret = pci_enable_msi(pdev); 170406f4b081SSara Sharon if (ret) { 170506f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 17062e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 17072e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 17082e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 17092e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 17102e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 17112e5d4a8fSHaim Dreyfuss } 17122e5d4a8fSHaim Dreyfuss } 17132e5d4a8fSHaim Dreyfuss } 17142e5d4a8fSHaim Dreyfuss 17157c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 17167c8d91ebSHaim Dreyfuss { 17177c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 17187c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17197c8d91ebSHaim Dreyfuss 17207c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 17217c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 17227c8d91ebSHaim Dreyfuss offset = 1 + i; 17237c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 17247c8d91ebSHaim Dreyfuss /* 17257c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 17267c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17277c8d91ebSHaim Dreyfuss */ 17287c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17297c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17307c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17317c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17327c8d91ebSHaim Dreyfuss if (ret) 17337c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17347c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 173557e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 17367c8d91ebSHaim Dreyfuss } 17377c8d91ebSHaim Dreyfuss } 17387c8d91ebSHaim Dreyfuss 17392e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17402e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17412e5d4a8fSHaim Dreyfuss { 1742496d83caSHaim Dreyfuss int i; 17432e5d4a8fSHaim Dreyfuss 1744496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17452e5d4a8fSHaim Dreyfuss int ret; 17465a41a86cSSharon Dvir struct msix_entry *msix_entry; 174764fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 174864fa3affSSharon Dvir 174964fa3affSSharon Dvir if (!qname) 175064fa3affSSharon Dvir return -ENOMEM; 17512e5d4a8fSHaim Dreyfuss 17525a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17535a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17545a41a86cSSharon Dvir msix_entry->vector, 17552e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1756496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17572e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17582e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17592e5d4a8fSHaim Dreyfuss IRQF_SHARED, 176064fa3affSSharon Dvir qname, 17615a41a86cSSharon Dvir msix_entry); 17622e5d4a8fSHaim Dreyfuss if (ret) { 17632e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17642e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17655a41a86cSSharon Dvir 17662e5d4a8fSHaim Dreyfuss return ret; 17672e5d4a8fSHaim Dreyfuss } 17682e5d4a8fSHaim Dreyfuss } 17697c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17702e5d4a8fSHaim Dreyfuss 17712e5d4a8fSHaim Dreyfuss return 0; 17722e5d4a8fSHaim Dreyfuss } 17732e5d4a8fSHaim Dreyfuss 177444f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 177544f61b5cSShahar S Matityahu { 177644f61b5cSShahar S Matityahu u32 hpm, wprot; 177744f61b5cSShahar S Matityahu 1778286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 177944f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 178044f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 178144f61b5cSShahar S Matityahu break; 178244f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 178344f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 178444f61b5cSShahar S Matityahu break; 178544f61b5cSShahar S Matityahu default: 178644f61b5cSShahar S Matityahu return 0; 178744f61b5cSShahar S Matityahu } 178844f61b5cSShahar S Matityahu 178944f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 179044f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 179144f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 179244f61b5cSShahar S Matityahu 179344f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 179444f61b5cSShahar S Matityahu IWL_ERR(trans, 179544f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 179644f61b5cSShahar S Matityahu return -EPERM; 179744f61b5cSShahar S Matityahu } 179844f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 179944f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 180044f61b5cSShahar S Matityahu } 180144f61b5cSShahar S Matityahu 180244f61b5cSShahar S Matityahu return 0; 180344f61b5cSShahar S Matityahu } 180444f61b5cSShahar S Matityahu 18050df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 18060df36b90SLuca Coelho { 18070df36b90SLuca Coelho int ret; 18080df36b90SLuca Coelho 1809425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 18100df36b90SLuca Coelho if (ret < 0) 18110df36b90SLuca Coelho return ret; 18120df36b90SLuca Coelho 18130df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18140df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18150df36b90SLuca Coelho udelay(20); 18160df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18170df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 18180df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 18190df36b90SLuca Coelho udelay(20); 18200df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 18210df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18220df36b90SLuca Coelho 182315bf5ac6SJohannes Berg return iwl_trans_pcie_sw_reset(trans, true); 18240df36b90SLuca Coelho } 18250df36b90SLuca Coelho 1826bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1827e705c121SKalle Valo { 1828e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1829e705c121SKalle Valo int err; 1830e705c121SKalle Valo 1831e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1832e705c121SKalle Valo 1833e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1834e705c121SKalle Valo if (err) { 1835e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1836e705c121SKalle Valo return err; 1837e705c121SKalle Valo } 1838e705c121SKalle Valo 183944f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 184044f61b5cSShahar S Matityahu if (err) 184144f61b5cSShahar S Matityahu return err; 18428954e1ebSShahar S Matityahu 184315bf5ac6SJohannes Berg err = iwl_trans_pcie_sw_reset(trans, true); 184415bf5ac6SJohannes Berg if (err) 184515bf5ac6SJohannes Berg return err; 1846e705c121SKalle Valo 18470df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18487897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18490df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18500df36b90SLuca Coelho if (err) 18510df36b90SLuca Coelho return err; 18520df36b90SLuca Coelho } 18530df36b90SLuca Coelho 185452b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 185552b6e168SEmmanuel Grumbach if (err) 185652b6e168SEmmanuel Grumbach return err; 1857e705c121SKalle Valo 18582e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 185983730058SHaim Dreyfuss 1860e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1861e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1862e705c121SKalle Valo 1863326477e4SJohannes Berg trans_pcie->opmode_down = false; 1864326477e4SJohannes Berg 1865e705c121SKalle Valo /* Set is_down to false here so that...*/ 1866e705c121SKalle Valo trans_pcie->is_down = false; 1867e705c121SKalle Valo 1868e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18699ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1870e705c121SKalle Valo 1871e705c121SKalle Valo return 0; 1872e705c121SKalle Valo } 1873e705c121SKalle Valo 1874bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1875e705c121SKalle Valo { 1876e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1877e705c121SKalle Valo int ret; 1878e705c121SKalle Valo 1879e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1880bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1881e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1882e705c121SKalle Valo 1883e705c121SKalle Valo return ret; 1884e705c121SKalle Valo } 1885e705c121SKalle Valo 1886e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1887e705c121SKalle Valo { 1888e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1889e705c121SKalle Valo 1890e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1891e705c121SKalle Valo 1892e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1893e705c121SKalle Valo iwl_disable_interrupts(trans); 1894e705c121SKalle Valo 1895e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1896e705c121SKalle Valo 1897e705c121SKalle Valo iwl_disable_interrupts(trans); 1898e705c121SKalle Valo 1899e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1900e705c121SKalle Valo 1901e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1902e705c121SKalle Valo 19032e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1904e705c121SKalle Valo } 1905e705c121SKalle Valo 1906e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1907e705c121SKalle Valo { 1908e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1909e705c121SKalle Valo } 1910e705c121SKalle Valo 1911e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1912e705c121SKalle Valo { 1913e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1914e705c121SKalle Valo } 1915e705c121SKalle Valo 1916e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1917e705c121SKalle Valo { 1918e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1919e705c121SKalle Valo } 1920e705c121SKalle Valo 192184fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 192284fb372cSSara Sharon { 19233681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 192484fb372cSSara Sharon return 0x00FFFFFF; 192584fb372cSSara Sharon else 192684fb372cSSara Sharon return 0x000FFFFF; 192784fb372cSSara Sharon } 192884fb372cSSara Sharon 1929e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1930e705c121SKalle Valo { 193184fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 193284fb372cSSara Sharon 1933e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 193484fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1935e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1936e705c121SKalle Valo } 1937e705c121SKalle Valo 1938e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1939e705c121SKalle Valo u32 val) 1940e705c121SKalle Valo { 194184fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 194284fb372cSSara Sharon 1943e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 194484fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1945e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1946e705c121SKalle Valo } 1947e705c121SKalle Valo 1948e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1949e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1950e705c121SKalle Valo { 1951e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1952e705c121SKalle Valo 19536ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 19546ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 19556ac57200SJohannes Berg 19564f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 19574f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 19584f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 195922852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 196022852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1961227f2597SJohannes Berg trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 196222852fadSMordechay Goodstein 1963e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1964e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1965e705c121SKalle Valo else 1966e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1967e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1968e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1969e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1970e705c121SKalle Valo 19716c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19726c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19736c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 197480084e35SJohannes Berg trans_pcie->rx_buf_bytes = 197580084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1976cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1977cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1978cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1979e705c121SKalle Valo 19808e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1981e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1982e705c121SKalle Valo 198339bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 198439bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 198539bdb17eSSharon Dvir 1986e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1987e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1988e705c121SKalle Valo * As this function may be called again in some corner cases don't 1989e705c121SKalle Valo * do anything if NAPI was already initialized. 1990e705c121SKalle Valo */ 1991bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1992e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1993906d4eb8SJohannes Berg 1994906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1995e705c121SKalle Valo } 1996e705c121SKalle Valo 1997e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1998e705c121SKalle Valo { 1999e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20006eb5e529SEmmanuel Grumbach int i; 2001e705c121SKalle Valo 20022e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 2003e705c121SKalle Valo 2004286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 20050cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 200613a3a390SSara Sharon else 2007e705c121SKalle Valo iwl_pcie_tx_free(trans); 2008e705c121SKalle Valo iwl_pcie_rx_free(trans); 2009e705c121SKalle Valo 201010a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 201110a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 201210a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 201310a54d81SLuca Coelho } 201410a54d81SLuca Coelho 20152e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 20167c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 20177c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 20187c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 20197c8d91ebSHaim Dreyfuss NULL); 20207c8d91ebSHaim Dreyfuss } 20212e5d4a8fSHaim Dreyfuss 20222e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 20232e5d4a8fSHaim Dreyfuss } else { 2024e705c121SKalle Valo iwl_pcie_free_ict(trans); 20252e5d4a8fSHaim Dreyfuss } 2026e705c121SKalle Valo 2027e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 2028e705c121SKalle Valo 202969725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 203069725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 203169725928SLuca Coelho trans_pcie->pnvm_dram.block, 203269725928SLuca Coelho trans_pcie->pnvm_dram.physical); 203369725928SLuca Coelho 20349dad325fSLuca Coelho if (trans_pcie->reduce_power_dram.size) 20359dad325fSLuca Coelho dma_free_coherent(trans->dev, 20369dad325fSLuca Coelho trans_pcie->reduce_power_dram.size, 20379dad325fSLuca Coelho trans_pcie->reduce_power_dram.block, 20389dad325fSLuca Coelho trans_pcie->reduce_power_dram.physical); 20399dad325fSLuca Coelho 2040a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2041e705c121SKalle Valo iwl_trans_free(trans); 2042e705c121SKalle Valo } 2043e705c121SKalle Valo 2044e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2045e705c121SKalle Valo { 2046e705c121SKalle Valo if (state) 2047e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2048e705c121SKalle Valo else 2049e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2050e705c121SKalle Valo } 2051e705c121SKalle Valo 205249564a80SLuca Coelho struct iwl_trans_pcie_removal { 205349564a80SLuca Coelho struct pci_dev *pdev; 205449564a80SLuca Coelho struct work_struct work; 2055*b8133439SAvraham Stern bool rescan; 205649564a80SLuca Coelho }; 205749564a80SLuca Coelho 205849564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 205949564a80SLuca Coelho { 206049564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 206149564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 206249564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2063aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2064*b8133439SAvraham Stern struct pci_bus *bus = pdev->bus; 206549564a80SLuca Coelho 206649564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 206749564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 206849564a80SLuca Coelho pci_lock_rescan_remove(); 206949564a80SLuca Coelho pci_dev_put(pdev); 207049564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 2071*b8133439SAvraham Stern if (removal->rescan) 2072*b8133439SAvraham Stern pci_rescan_bus(bus->parent); 207349564a80SLuca Coelho pci_unlock_rescan_remove(); 207449564a80SLuca Coelho 207549564a80SLuca Coelho kfree(removal); 207649564a80SLuca Coelho module_put(THIS_MODULE); 207749564a80SLuca Coelho } 207849564a80SLuca Coelho 2079*b8133439SAvraham Stern void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2080*b8133439SAvraham Stern { 2081*b8133439SAvraham Stern struct iwl_trans_pcie_removal *removal; 2082*b8133439SAvraham Stern 2083*b8133439SAvraham Stern if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2084*b8133439SAvraham Stern return; 2085*b8133439SAvraham Stern 2086*b8133439SAvraham Stern IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2087*b8133439SAvraham Stern 2088*b8133439SAvraham Stern /* 2089*b8133439SAvraham Stern * get a module reference to avoid doing this 2090*b8133439SAvraham Stern * while unloading anyway and to avoid 2091*b8133439SAvraham Stern * scheduling a work with code that's being 2092*b8133439SAvraham Stern * removed. 2093*b8133439SAvraham Stern */ 2094*b8133439SAvraham Stern if (!try_module_get(THIS_MODULE)) { 2095*b8133439SAvraham Stern IWL_ERR(trans, 2096*b8133439SAvraham Stern "Module is being unloaded - abort\n"); 2097*b8133439SAvraham Stern return; 2098*b8133439SAvraham Stern } 2099*b8133439SAvraham Stern 2100*b8133439SAvraham Stern removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2101*b8133439SAvraham Stern if (!removal) { 2102*b8133439SAvraham Stern module_put(THIS_MODULE); 2103*b8133439SAvraham Stern return; 2104*b8133439SAvraham Stern } 2105*b8133439SAvraham Stern /* 2106*b8133439SAvraham Stern * we don't need to clear this flag, because 2107*b8133439SAvraham Stern * the trans will be freed and reallocated. 2108*b8133439SAvraham Stern */ 2109*b8133439SAvraham Stern set_bit(STATUS_TRANS_DEAD, &trans->status); 2110*b8133439SAvraham Stern 2111*b8133439SAvraham Stern removal->pdev = to_pci_dev(trans->dev); 2112*b8133439SAvraham Stern removal->rescan = rescan; 2113*b8133439SAvraham Stern INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2114*b8133439SAvraham Stern pci_dev_get(removal->pdev); 2115*b8133439SAvraham Stern schedule_work(&removal->work); 2116*b8133439SAvraham Stern } 2117*b8133439SAvraham Stern EXPORT_SYMBOL(iwl_trans_pcie_remove); 2118*b8133439SAvraham Stern 2119c544d89bSJohannes Berg /* 2120c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2121c544d89bSJohannes Berg * already disabled. 2122c544d89bSJohannes Berg */ 2123c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2124e705c121SKalle Valo { 2125e705c121SKalle Valo int ret; 2126e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21279ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 21289ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 21299ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 21309ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2131e705c121SKalle Valo 2132c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2133e705c121SKalle Valo 2134e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2135e705c121SKalle Valo goto out; 2136e705c121SKalle Valo 21379ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 21389ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 21399ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21409ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21419ce041f5SJohannes Berg } 21429ce041f5SJohannes Berg 2143e705c121SKalle Valo /* this bit wakes up the NIC */ 21449ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2145286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2146e705c121SKalle Valo udelay(2); 2147e705c121SKalle Valo 2148e705c121SKalle Valo /* 2149e705c121SKalle Valo * These bits say the device is running, and should keep running for 2150e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2151e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2152fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2153fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2154e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2155e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2156e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2157e705c121SKalle Valo * to keep device from sleeping. 2158e705c121SKalle Valo * 2159e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2160e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2161fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2162fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2163fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2164e705c121SKalle Valo * 2165e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2166e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2167e705c121SKalle Valo */ 21689ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2169e705c121SKalle Valo if (unlikely(ret < 0)) { 217049564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 217149564a80SLuca Coelho 2172e705c121SKalle Valo WARN_ONCE(1, 2173e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 217449564a80SLuca Coelho cntrl); 217549564a80SLuca Coelho 217649564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 217749564a80SLuca Coelho 2178*b8133439SAvraham Stern if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2179*b8133439SAvraham Stern iwl_trans_pcie_remove(trans, false); 2180*b8133439SAvraham Stern else 218149564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 218249564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 218349564a80SLuca Coelho 2184c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2185e705c121SKalle Valo return false; 2186e705c121SKalle Valo } 2187e705c121SKalle Valo 2188e705c121SKalle Valo out: 2189e705c121SKalle Valo /* 2190e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2191e705c121SKalle Valo * track nic_access anyway. 2192e705c121SKalle Valo */ 2193e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2194e705c121SKalle Valo return true; 2195e705c121SKalle Valo } 2196e705c121SKalle Valo 2197c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2198c544d89bSJohannes Berg { 2199c544d89bSJohannes Berg bool ret; 2200c544d89bSJohannes Berg 2201c544d89bSJohannes Berg local_bh_disable(); 2202c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2203c544d89bSJohannes Berg if (ret) { 2204c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2205c544d89bSJohannes Berg return ret; 2206c544d89bSJohannes Berg } 2207c544d89bSJohannes Berg local_bh_enable(); 2208c544d89bSJohannes Berg return false; 2209c544d89bSJohannes Berg } 2210c544d89bSJohannes Berg 22111ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2212e705c121SKalle Valo { 2213e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2214e705c121SKalle Valo 2215e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2216e705c121SKalle Valo 2217e705c121SKalle Valo /* 2218e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2219e705c121SKalle Valo * track nic_access anyway. 2220e705c121SKalle Valo */ 2221e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2222e705c121SKalle Valo 2223e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2224e705c121SKalle Valo goto out; 22251b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 22261b6598c3SRoee Goldfiner __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22271b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 22281b6598c3SRoee Goldfiner else 2229e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22306dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2231e705c121SKalle Valo /* 2232e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2233e705c121SKalle Valo * any previous writes, but we need the write that clears the 2234e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2235e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2236e705c121SKalle Valo */ 2237e705c121SKalle Valo out: 2238874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2239e705c121SKalle Valo } 2240e705c121SKalle Valo 2241e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2242e705c121SKalle Valo void *buf, int dwords) 2243e705c121SKalle Valo { 224404516706SJohannes Berg int offs = 0; 2245e705c121SKalle Valo u32 *vals = buf; 2246e705c121SKalle Valo 224704516706SJohannes Berg while (offs < dwords) { 224804516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 224967013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 22503d372c4eSJohannes Berg bool resched = false; 225104516706SJohannes Berg 22521ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 225304516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 225404516706SJohannes Berg addr + 4 * offs); 225504516706SJohannes Berg 225604516706SJohannes Berg while (offs < dwords) { 225704516706SJohannes Berg vals[offs] = iwl_read32(trans, 225804516706SJohannes Berg HBUS_TARG_MEM_RDAT); 225904516706SJohannes Berg offs++; 226004516706SJohannes Berg 22613d372c4eSJohannes Berg if (time_after(jiffies, end)) { 22623d372c4eSJohannes Berg resched = true; 226304516706SJohannes Berg break; 226404516706SJohannes Berg } 22653d372c4eSJohannes Berg } 22661ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 22673d372c4eSJohannes Berg 22683d372c4eSJohannes Berg if (resched) 22693d372c4eSJohannes Berg cond_resched(); 2270e705c121SKalle Valo } else { 227104516706SJohannes Berg return -EBUSY; 2272e705c121SKalle Valo } 227304516706SJohannes Berg } 227404516706SJohannes Berg 227504516706SJohannes Berg return 0; 2276e705c121SKalle Valo } 2277e705c121SKalle Valo 2278e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2279e705c121SKalle Valo const void *buf, int dwords) 2280e705c121SKalle Valo { 2281e705c121SKalle Valo int offs, ret = 0; 2282e705c121SKalle Valo const u32 *vals = buf; 2283e705c121SKalle Valo 22841ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2285e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2286e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2287e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2288e705c121SKalle Valo vals ? vals[offs] : 0); 22891ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2290e705c121SKalle Valo } else { 2291e705c121SKalle Valo ret = -EBUSY; 2292e705c121SKalle Valo } 2293e705c121SKalle Valo return ret; 2294e705c121SKalle Valo } 2295e705c121SKalle Valo 22967f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22977f1fe1d4SLuca Coelho u32 *val) 22987f1fe1d4SLuca Coelho { 22997f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 23007f1fe1d4SLuca Coelho ofs, val); 23017f1fe1d4SLuca Coelho } 23027f1fe1d4SLuca Coelho 23030cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 23040cd58eaaSEmmanuel Grumbach { 23050cd58eaaSEmmanuel Grumbach int i; 23060cd58eaaSEmmanuel Grumbach 2307286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 23084f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 23090cd58eaaSEmmanuel Grumbach 23104f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 23110cd58eaaSEmmanuel Grumbach continue; 23120cd58eaaSEmmanuel Grumbach 23130cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 23140cd58eaaSEmmanuel Grumbach 23150cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 23160cd58eaaSEmmanuel Grumbach txq->block--; 23170cd58eaaSEmmanuel Grumbach if (!txq->block) { 23180cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2319bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 23200cd58eaaSEmmanuel Grumbach } 23210cd58eaaSEmmanuel Grumbach } else if (block) { 23220cd58eaaSEmmanuel Grumbach txq->block++; 23230cd58eaaSEmmanuel Grumbach } 23240cd58eaaSEmmanuel Grumbach 23250cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 23260cd58eaaSEmmanuel Grumbach } 23270cd58eaaSEmmanuel Grumbach } 23280cd58eaaSEmmanuel Grumbach 2329e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2330e705c121SKalle Valo 233192536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 233292536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 233392536c96SSara Sharon { 233492536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 233592536c96SSara Sharon 233692536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 233792536c96SSara Sharon return -EINVAL; 233892536c96SSara Sharon 233992536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 234092536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 234192536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 234292536c96SSara Sharon data->fr_bd_wid = 0; 234392536c96SSara Sharon 234492536c96SSara Sharon return 0; 234592536c96SSara Sharon } 234692536c96SSara Sharon 2347d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2348e705c121SKalle Valo { 2349e705c121SKalle Valo struct iwl_txq *txq; 2350e705c121SKalle Valo unsigned long now = jiffies; 23512ae48edcSSara Sharon bool overflow_tx; 2352e705c121SKalle Valo u8 wr_ptr; 2353e705c121SKalle Valo 23542b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2355f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2356f60c9e59SEmmanuel Grumbach return -ENODEV; 23572b3fae66SMatt Chen 23584f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2359d6d517b7SSara Sharon return -EINVAL; 2360e705c121SKalle Valo 2361d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 23624f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 23632ae48edcSSara Sharon 23642ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23652ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23662ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23672ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23682ae48edcSSara Sharon 23696aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2370e705c121SKalle Valo 23712ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23722ae48edcSSara Sharon overflow_tx) && 2373e705c121SKalle Valo !time_after(jiffies, 2374e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23756aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2376e705c121SKalle Valo 23772ae48edcSSara Sharon /* 23782ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23792ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23802ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23812ae48edcSSara Sharon */ 23822ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2383e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2384e705c121SKalle Valo wr_ptr, write_ptr)) 2385e705c121SKalle Valo return -ETIMEDOUT; 23862ae48edcSSara Sharon wr_ptr = write_ptr; 23872ae48edcSSara Sharon 2388192185d6SJohannes Berg usleep_range(1000, 2000); 23892ae48edcSSara Sharon 23902ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23912ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23922ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23932ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2394e705c121SKalle Valo } 2395e705c121SKalle Valo 2396bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2397e705c121SKalle Valo IWL_ERR(trans, 2398d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 23990cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2400d6d517b7SSara Sharon return -ETIMEDOUT; 2401e705c121SKalle Valo } 2402e705c121SKalle Valo 2403d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2404d6d517b7SSara Sharon 2405d6d517b7SSara Sharon return 0; 2406d6d517b7SSara Sharon } 2407d6d517b7SSara Sharon 2408d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2409d6d517b7SSara Sharon { 2410d6d517b7SSara Sharon int cnt; 2411d6d517b7SSara Sharon int ret = 0; 2412d6d517b7SSara Sharon 2413d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 241479b6c8feSLuca Coelho for (cnt = 0; 2415286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 241679b6c8feSLuca Coelho cnt++) { 2417d6d517b7SSara Sharon 24184f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2419d6d517b7SSara Sharon continue; 24204f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2421d6d517b7SSara Sharon continue; 2422d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2423d6d517b7SSara Sharon continue; 2424d6d517b7SSara Sharon 2425d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 242638398efbSSara Sharon if (ret) 2427d6d517b7SSara Sharon break; 2428d6d517b7SSara Sharon } 2429e705c121SKalle Valo 2430e705c121SKalle Valo return ret; 2431e705c121SKalle Valo } 2432e705c121SKalle Valo 2433e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2434e705c121SKalle Valo u32 mask, u32 value) 2435e705c121SKalle Valo { 2436e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2437e705c121SKalle Valo 2438874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2439e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2440874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2441e705c121SKalle Valo } 2442e705c121SKalle Valo 2443e705c121SKalle Valo static const char *get_csr_string(int cmd) 2444e705c121SKalle Valo { 2445e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2446e705c121SKalle Valo switch (cmd) { 2447e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2448e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2449e705c121SKalle Valo IWL_CMD(CSR_INT); 2450e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2451e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2452e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2453e705c121SKalle Valo IWL_CMD(CSR_RESET); 2454e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2455e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2456e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2457e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2458e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2459e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2460e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2461e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2462e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2463e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2464e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2465e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2466e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2467e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2468e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2469e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2470e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2471e705c121SKalle Valo default: 2472e705c121SKalle Valo return "UNKNOWN"; 2473e705c121SKalle Valo } 2474e705c121SKalle Valo #undef IWL_CMD 2475e705c121SKalle Valo } 2476e705c121SKalle Valo 2477e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2478e705c121SKalle Valo { 2479e705c121SKalle Valo int i; 2480e705c121SKalle Valo static const u32 csr_tbl[] = { 2481e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2482e705c121SKalle Valo CSR_INT_COALESCING, 2483e705c121SKalle Valo CSR_INT, 2484e705c121SKalle Valo CSR_INT_MASK, 2485e705c121SKalle Valo CSR_FH_INT_STATUS, 2486e705c121SKalle Valo CSR_GPIO_IN, 2487e705c121SKalle Valo CSR_RESET, 2488e705c121SKalle Valo CSR_GP_CNTRL, 2489e705c121SKalle Valo CSR_HW_REV, 2490e705c121SKalle Valo CSR_EEPROM_REG, 2491e705c121SKalle Valo CSR_EEPROM_GP, 2492e705c121SKalle Valo CSR_OTP_GP_REG, 2493e705c121SKalle Valo CSR_GIO_REG, 2494e705c121SKalle Valo CSR_GP_UCODE_REG, 2495e705c121SKalle Valo CSR_GP_DRIVER_REG, 2496e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2497e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2498e705c121SKalle Valo CSR_LED_REG, 2499e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2500e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2501e705c121SKalle Valo CSR_ANA_PLL_CFG, 2502e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2503e705c121SKalle Valo CSR_HW_REV_WA_REG, 2504e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2505e705c121SKalle Valo }; 2506e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2507e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2508e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2509e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2510e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2511e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2512e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2513e705c121SKalle Valo } 2514e705c121SKalle Valo } 2515e705c121SKalle Valo 2516e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2517e705c121SKalle Valo /* create and remove of files */ 2518e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2519cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2520cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2521e705c121SKalle Valo } while (0) 2522e705c121SKalle Valo 2523e705c121SKalle Valo /* file operation */ 2524e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2525e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2526e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2527e705c121SKalle Valo .open = simple_open, \ 2528e705c121SKalle Valo .llseek = generic_file_llseek, \ 2529e705c121SKalle Valo }; 2530e705c121SKalle Valo 2531e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2532e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2533e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2534e705c121SKalle Valo .open = simple_open, \ 2535e705c121SKalle Valo .llseek = generic_file_llseek, \ 2536e705c121SKalle Valo }; 2537e705c121SKalle Valo 2538e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2539e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2540e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2541e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2542e705c121SKalle Valo .open = simple_open, \ 2543e705c121SKalle Valo .llseek = generic_file_llseek, \ 2544e705c121SKalle Valo }; 2545e705c121SKalle Valo 2546df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2547df67a1beSJohannes Berg struct iwl_trans *trans; 2548df67a1beSJohannes Berg }; 2549df67a1beSJohannes Berg 2550df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2551df67a1beSJohannes Berg loff_t pos; 2552df67a1beSJohannes Berg }; 2553df67a1beSJohannes Berg 2554df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2555e705c121SKalle Valo { 2556df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2557df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2558df67a1beSJohannes Berg 2559df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2560df67a1beSJohannes Berg return NULL; 2561df67a1beSJohannes Berg 2562df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2563df67a1beSJohannes Berg if (!state) 2564df67a1beSJohannes Berg return NULL; 2565df67a1beSJohannes Berg state->pos = *pos; 2566df67a1beSJohannes Berg return state; 2567df67a1beSJohannes Berg } 2568df67a1beSJohannes Berg 2569df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2570df67a1beSJohannes Berg void *v, loff_t *pos) 2571df67a1beSJohannes Berg { 2572df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2573df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2574df67a1beSJohannes Berg 2575df67a1beSJohannes Berg *pos = ++state->pos; 2576df67a1beSJohannes Berg 2577df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2578df67a1beSJohannes Berg return NULL; 2579df67a1beSJohannes Berg 2580df67a1beSJohannes Berg return state; 2581df67a1beSJohannes Berg } 2582df67a1beSJohannes Berg 2583df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2584df67a1beSJohannes Berg { 2585df67a1beSJohannes Berg kfree(v); 2586df67a1beSJohannes Berg } 2587df67a1beSJohannes Berg 2588df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2589df67a1beSJohannes Berg { 2590df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2591df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2592df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 25934f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2594e705c121SKalle Valo 2595df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2596df67a1beSJohannes Berg (unsigned int)state->pos, 25974f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 25984f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2599df67a1beSJohannes Berg if (txq) 2600df67a1beSJohannes Berg seq_printf(seq, 260195a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2602df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 260395a9e44fSJohannes Berg txq->need_update, txq->frozen, 260495a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2605df67a1beSJohannes Berg else 2606df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2607e705c121SKalle Valo 26084f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2609df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2610df67a1beSJohannes Berg seq_puts(seq, "\n"); 2611e705c121SKalle Valo 2612df67a1beSJohannes Berg return 0; 2613df67a1beSJohannes Berg } 2614df67a1beSJohannes Berg 2615df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2616df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2617df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2618df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2619df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2620df67a1beSJohannes Berg }; 2621df67a1beSJohannes Berg 2622df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2623df67a1beSJohannes Berg { 2624df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2625df67a1beSJohannes Berg 2626df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2627df67a1beSJohannes Berg sizeof(*priv)); 2628df67a1beSJohannes Berg 2629df67a1beSJohannes Berg if (!priv) 2630e705c121SKalle Valo return -ENOMEM; 2631e705c121SKalle Valo 2632df67a1beSJohannes Berg priv->trans = inode->i_private; 2633df67a1beSJohannes Berg return 0; 2634e705c121SKalle Valo } 2635e705c121SKalle Valo 2636e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2637e705c121SKalle Valo char __user *user_buf, 2638e705c121SKalle Valo size_t count, loff_t *ppos) 2639e705c121SKalle Valo { 2640e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2641e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 264278485054SSara Sharon char *buf; 264378485054SSara Sharon int pos = 0, i, ret; 2644eb3dc36eSColin Ian King size_t bufsz; 2645e705c121SKalle Valo 264678485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 264778485054SSara Sharon 264878485054SSara Sharon if (!trans_pcie->rxq) 264978485054SSara Sharon return -EAGAIN; 265078485054SSara Sharon 265178485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 265278485054SSara Sharon if (!buf) 265378485054SSara Sharon return -ENOMEM; 265478485054SSara Sharon 265578485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 265678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 265778485054SSara Sharon 265878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 265978485054SSara Sharon i); 266078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2661e705c121SKalle Valo rxq->read); 266278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2663e705c121SKalle Valo rxq->write); 266478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2665e705c121SKalle Valo rxq->write_actual); 266678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2667e705c121SKalle Valo rxq->need_update); 266878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2669e705c121SKalle Valo rxq->free_count); 2670e705c121SKalle Valo if (rxq->rb_stts) { 26710307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26720307c839SGolan Ben Ami rxq)); 267378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 267478485054SSara Sharon "\tclosed_rb_num: %u\n", 26750307c839SGolan Ben Ami r & 0x0FFF); 2676e705c121SKalle Valo } else { 2677e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 267878485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2679e705c121SKalle Valo } 268078485054SSara Sharon } 268178485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 268278485054SSara Sharon kfree(buf); 268378485054SSara Sharon 268478485054SSara Sharon return ret; 2685e705c121SKalle Valo } 2686e705c121SKalle Valo 2687e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2688e705c121SKalle Valo char __user *user_buf, 2689e705c121SKalle Valo size_t count, loff_t *ppos) 2690e705c121SKalle Valo { 2691e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2692e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2693e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2694e705c121SKalle Valo 2695e705c121SKalle Valo int pos = 0; 2696e705c121SKalle Valo char *buf; 2697e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2698e705c121SKalle Valo ssize_t ret; 2699e705c121SKalle Valo 2700e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2701e705c121SKalle Valo if (!buf) 2702e705c121SKalle Valo return -ENOMEM; 2703e705c121SKalle Valo 2704e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2705e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2706e705c121SKalle Valo 2707e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2708e705c121SKalle Valo isr_stats->hw); 2709e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2710e705c121SKalle Valo isr_stats->sw); 2711e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2712e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2713e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2714e705c121SKalle Valo isr_stats->err_code); 2715e705c121SKalle Valo } 2716e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2717e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2718e705c121SKalle Valo isr_stats->sch); 2719e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2720e705c121SKalle Valo isr_stats->alive); 2721e705c121SKalle Valo #endif 2722e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2723e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2724e705c121SKalle Valo 2725e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2726e705c121SKalle Valo isr_stats->ctkill); 2727e705c121SKalle Valo 2728e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2729e705c121SKalle Valo isr_stats->wakeup); 2730e705c121SKalle Valo 2731e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2732e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2733e705c121SKalle Valo 2734e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2735e705c121SKalle Valo isr_stats->tx); 2736e705c121SKalle Valo 2737e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2738e705c121SKalle Valo isr_stats->unhandled); 2739e705c121SKalle Valo 2740e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2741e705c121SKalle Valo kfree(buf); 2742e705c121SKalle Valo return ret; 2743e705c121SKalle Valo } 2744e705c121SKalle Valo 2745e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2746e705c121SKalle Valo const char __user *user_buf, 2747e705c121SKalle Valo size_t count, loff_t *ppos) 2748e705c121SKalle Valo { 2749e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2750e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2751e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2752e705c121SKalle Valo u32 reset_flag; 2753078f1131SJohannes Berg int ret; 2754e705c121SKalle Valo 2755078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2756078f1131SJohannes Berg if (ret) 2757078f1131SJohannes Berg return ret; 2758e705c121SKalle Valo if (reset_flag == 0) 2759e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2760e705c121SKalle Valo 2761e705c121SKalle Valo return count; 2762e705c121SKalle Valo } 2763e705c121SKalle Valo 2764e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2765e705c121SKalle Valo const char __user *user_buf, 2766e705c121SKalle Valo size_t count, loff_t *ppos) 2767e705c121SKalle Valo { 2768e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2769e705c121SKalle Valo 2770e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2771e705c121SKalle Valo 2772e705c121SKalle Valo return count; 2773e705c121SKalle Valo } 2774e705c121SKalle Valo 2775e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2776e705c121SKalle Valo char __user *user_buf, 2777e705c121SKalle Valo size_t count, loff_t *ppos) 2778e705c121SKalle Valo { 2779e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2780e705c121SKalle Valo char *buf = NULL; 2781e705c121SKalle Valo ssize_t ret; 2782e705c121SKalle Valo 2783e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2784e705c121SKalle Valo if (ret < 0) 2785e705c121SKalle Valo return ret; 2786e705c121SKalle Valo if (!buf) 2787e705c121SKalle Valo return -EINVAL; 2788e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2789e705c121SKalle Valo kfree(buf); 2790e705c121SKalle Valo return ret; 2791e705c121SKalle Valo } 2792e705c121SKalle Valo 2793fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2794fa4de7f7SJohannes Berg char __user *user_buf, 2795fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2796fa4de7f7SJohannes Berg { 2797fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2798fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2799fa4de7f7SJohannes Berg char buf[100]; 2800fa4de7f7SJohannes Berg int pos; 2801fa4de7f7SJohannes Berg 2802fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2803fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2804fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2805fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2806fa4de7f7SJohannes Berg 2807fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2808fa4de7f7SJohannes Berg } 2809fa4de7f7SJohannes Berg 2810fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2811fa4de7f7SJohannes Berg const char __user *user_buf, 2812fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2813fa4de7f7SJohannes Berg { 2814fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2815fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2816c5bf4fa1SJohannes Berg bool new_value; 2817fa4de7f7SJohannes Berg int ret; 2818fa4de7f7SJohannes Berg 2819c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2820fa4de7f7SJohannes Berg if (ret) 2821fa4de7f7SJohannes Berg return ret; 2822c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2823fa4de7f7SJohannes Berg return count; 2824fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2825c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2826c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2827fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2828fa4de7f7SJohannes Berg 2829fa4de7f7SJohannes Berg return count; 2830fa4de7f7SJohannes Berg } 2831fa4de7f7SJohannes Berg 2832f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2833f7805b33SLior Cohen struct file *file) 2834f7805b33SLior Cohen { 2835f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2836f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2837f7805b33SLior Cohen 283891c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 283991c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2840f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2841f7805b33SLior Cohen return -ENOENT; 2842f7805b33SLior Cohen } 2843f7805b33SLior Cohen 2844f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2845f7805b33SLior Cohen return -EBUSY; 2846f7805b33SLior Cohen 2847f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2848f7805b33SLior Cohen return simple_open(inode, file); 2849f7805b33SLior Cohen } 2850f7805b33SLior Cohen 2851f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2852f7805b33SLior Cohen struct file *file) 2853f7805b33SLior Cohen { 2854f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2855f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2856f7805b33SLior Cohen 2857f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2858f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2859f7805b33SLior Cohen return 0; 2860f7805b33SLior Cohen } 2861f7805b33SLior Cohen 2862f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2863f7805b33SLior Cohen void *buf, ssize_t *size, 2864f7805b33SLior Cohen ssize_t *bytes_copied) 2865f7805b33SLior Cohen { 2866f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2867f7805b33SLior Cohen 2868f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2869f7805b33SLior Cohen if (*size > buf_size_left) 2870f7805b33SLior Cohen *size = buf_size_left; 2871f7805b33SLior Cohen 2872f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2873f7805b33SLior Cohen *bytes_copied += *size; 2874f7805b33SLior Cohen 2875f7805b33SLior Cohen if (buf_size_left == *size) 2876f7805b33SLior Cohen return true; 2877f7805b33SLior Cohen return false; 2878f7805b33SLior Cohen } 2879f7805b33SLior Cohen 2880f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2881f7805b33SLior Cohen char __user *user_buf, 2882f7805b33SLior Cohen size_t count, loff_t *ppos) 2883f7805b33SLior Cohen { 2884f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2885f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 28863827cb59SJohannes Berg u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2887f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2888f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2889f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2890f7805b33SLior Cohen bool b_full; 2891f7805b33SLior Cohen 289291c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2893f7805b33SLior Cohen write_ptr_addr = 289491c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 289591c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2896f7805b33SLior Cohen } else { 2897f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2898f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2899f7805b33SLior Cohen } 2900f7805b33SLior Cohen 290191c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2902f7805b33SLior Cohen return 0; 2903f7805b33SLior Cohen 2904f7805b33SLior Cohen mutex_lock(&data->mutex); 2905f7805b33SLior Cohen if (data->state == 2906f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2907f7805b33SLior Cohen mutex_unlock(&data->mutex); 2908f7805b33SLior Cohen return 0; 2909f7805b33SLior Cohen } 2910f7805b33SLior Cohen 2911f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2912f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2913f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2914f7805b33SLior Cohen 2915f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2916f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2917f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2918f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2919f7805b33SLior Cohen curr_buf, &size, 2920f7805b33SLior Cohen &bytes_copied); 2921f7805b33SLior Cohen data->prev_wr_ptr += size; 2922f7805b33SLior Cohen 2923f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2924f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 292569f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2926f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2927f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2928f7805b33SLior Cohen curr_buf, &size, 2929f7805b33SLior Cohen &bytes_copied); 2930f7805b33SLior Cohen data->prev_wr_ptr += size; 2931f7805b33SLior Cohen 2932f7805b33SLior Cohen if (!b_full) { 2933f7805b33SLior Cohen size = write_ptr; 2934f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2935f7805b33SLior Cohen cpu_addr, &size, 2936f7805b33SLior Cohen &bytes_copied); 2937f7805b33SLior Cohen data->prev_wr_ptr = size; 2938f7805b33SLior Cohen data->prev_wrap_cnt++; 2939f7805b33SLior Cohen } 2940f7805b33SLior Cohen } else { 2941f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2942f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2943f7805b33SLior Cohen IWL_WARN(trans, 2944f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2945f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2946f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2947f7805b33SLior Cohen IWL_WARN(trans, 2948f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2949f7805b33SLior Cohen 2950f7805b33SLior Cohen size = write_ptr; 2951f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2952f7805b33SLior Cohen cpu_addr, &size, 2953f7805b33SLior Cohen &bytes_copied); 2954f7805b33SLior Cohen data->prev_wr_ptr = size; 2955f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2956f7805b33SLior Cohen } 2957f7805b33SLior Cohen 2958f7805b33SLior Cohen mutex_unlock(&data->mutex); 2959f7805b33SLior Cohen 2960f7805b33SLior Cohen return bytes_copied; 2961f7805b33SLior Cohen } 2962f7805b33SLior Cohen 2963aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 2964aa899e68SJohannes Berg char __user *user_buf, 2965aa899e68SJohannes Berg size_t count, loff_t *ppos) 2966aa899e68SJohannes Berg { 2967aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 2968aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2969aa899e68SJohannes Berg 2970aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 2971aa899e68SJohannes Berg return -ENODEV; 2972aa899e68SJohannes Berg 2973aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 2974aa899e68SJohannes Berg trans_pcie->rf_name, 2975aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 2976aa899e68SJohannes Berg } 2977aa899e68SJohannes Berg 2978e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2979e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2980e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2981e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2982fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2983aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 2984aa899e68SJohannes Berg 2985df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2986df67a1beSJohannes Berg .owner = THIS_MODULE, 2987df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2988df67a1beSJohannes Berg .read = seq_read, 2989df67a1beSJohannes Berg .llseek = seq_lseek, 2990df67a1beSJohannes Berg .release = seq_release_private, 2991df67a1beSJohannes Berg }; 2992e705c121SKalle Valo 2993f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2994f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2995f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2996f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2997f7805b33SLior Cohen }; 2998f7805b33SLior Cohen 2999f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 3000cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3001e705c121SKalle Valo { 3002f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 3003f8a1edb7SJohannes Berg 30042ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 30052ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 30062ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 30072ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 30082ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 30092ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3010f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3011aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 3012e705c121SKalle Valo } 3013f7805b33SLior Cohen 3014f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3015f7805b33SLior Cohen { 3016f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3017f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 3018f7805b33SLior Cohen 3019f7805b33SLior Cohen mutex_lock(&data->mutex); 3020f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3021f7805b33SLior Cohen mutex_unlock(&data->mutex); 3022f7805b33SLior Cohen } 3023e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3024e705c121SKalle Valo 30256983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3026e705c121SKalle Valo { 3027e705c121SKalle Valo u32 cmdlen = 0; 3028e705c121SKalle Valo int i; 3029e705c121SKalle Valo 3030885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 30310179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3032e705c121SKalle Valo 3033e705c121SKalle Valo return cmdlen; 3034e705c121SKalle Valo } 3035e705c121SKalle Valo 3036e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3037e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3038e705c121SKalle Valo int allocated_rb_nums) 3039e705c121SKalle Valo { 3040e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 304180084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 304278485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 304378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3044e705c121SKalle Valo u32 i, r, j, rb_len = 0; 3045e705c121SKalle Valo 3046e705c121SKalle Valo spin_lock(&rxq->lock); 3047e705c121SKalle Valo 30480307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3049e705c121SKalle Valo 3050e705c121SKalle Valo for (i = rxq->read, j = 0; 3051e705c121SKalle Valo i != r && j < allocated_rb_nums; 3052e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3053e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3054e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3055e705c121SKalle Valo 305659a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 305759a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 3058e705c121SKalle Valo 3059e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3060e705c121SKalle Valo 3061e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3062e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3063e705c121SKalle Valo rb = (void *)(*data)->data; 3064e705c121SKalle Valo rb->index = cpu_to_le32(i); 3065e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3066e705c121SKalle Valo 3067e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3068e705c121SKalle Valo } 3069e705c121SKalle Valo 3070e705c121SKalle Valo spin_unlock(&rxq->lock); 3071e705c121SKalle Valo 3072e705c121SKalle Valo return rb_len; 3073e705c121SKalle Valo } 3074e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3075e705c121SKalle Valo 3076e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3077e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3078e705c121SKalle Valo { 3079e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3080e705c121SKalle Valo __le32 *val; 3081e705c121SKalle Valo int i; 3082e705c121SKalle Valo 3083e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3084e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3085e705c121SKalle Valo val = (void *)(*data)->data; 3086e705c121SKalle Valo 3087e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3088e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3089e705c121SKalle Valo 3090e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3091e705c121SKalle Valo 3092e705c121SKalle Valo return csr_len; 3093e705c121SKalle Valo } 3094e705c121SKalle Valo 3095e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3096e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3097e705c121SKalle Valo { 3098e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3099e705c121SKalle Valo __le32 *val; 3100e705c121SKalle Valo int i; 3101e705c121SKalle Valo 31021ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3103e705c121SKalle Valo return 0; 3104e705c121SKalle Valo 3105e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3106e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3107e705c121SKalle Valo val = (void *)(*data)->data; 3108e705c121SKalle Valo 3109286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3110723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3111723b45e2SLiad Kaufman i += sizeof(u32)) 3112e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3113723b45e2SLiad Kaufman else 3114ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3115ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3116723b45e2SLiad Kaufman i += sizeof(u32)) 3117723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3118723b45e2SLiad Kaufman i)); 3119e705c121SKalle Valo 31201ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3121e705c121SKalle Valo 3122e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3123e705c121SKalle Valo 3124e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3125e705c121SKalle Valo } 3126e705c121SKalle Valo 3127e705c121SKalle Valo static u32 3128e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3129e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3130e705c121SKalle Valo u32 monitor_len) 3131e705c121SKalle Valo { 3132e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3133e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3134e705c121SKalle Valo u32 i; 3135e705c121SKalle Valo 31361ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3137e705c121SKalle Valo return 0; 3138e705c121SKalle Valo 3139ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3140e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3141ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 314214ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3143ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3144e705c121SKalle Valo 31451ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3146e705c121SKalle Valo 3147e705c121SKalle Valo return monitor_len; 3148e705c121SKalle Valo } 3149e705c121SKalle Valo 31507a14c23dSSara Sharon static void 31517a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31527a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31537a14c23dSSara Sharon { 3154c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 31557a14c23dSSara Sharon 3156286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3157c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3158c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3159c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3160c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 316191c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 316291c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 316391c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 316491c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 31657a14c23dSSara Sharon } else { 31667a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 31677a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31687a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31697a14c23dSSara Sharon } 3170c88580e1SShahar S Matityahu 3171c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31727a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31737a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31747a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31757a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3176286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3177c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3178c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3179c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3180cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3181cc598782SRotem Saado write_ptr_val >>= 2; 3182c88580e1SShahar S Matityahu } 3183c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31847a14c23dSSara Sharon } 31857a14c23dSSara Sharon 3186e705c121SKalle Valo static u32 3187e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3188e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3189e705c121SKalle Valo u32 monitor_len) 3190e705c121SKalle Valo { 319169f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3192e705c121SKalle Valo u32 len = 0; 3193e705c121SKalle Valo 319491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 319569f0e505SShahar S Matityahu (fw_mon->size && 3196286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3197286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3198e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3199e705c121SKalle Valo 3200e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3201e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 32027a14c23dSSara Sharon 32037a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3204e705c121SKalle Valo 3205e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 320669f0e505SShahar S Matityahu if (fw_mon->size) { 320769f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 320869f0e505SShahar S Matityahu monitor_len = fw_mon->size; 320991c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 32107a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3211e705c121SKalle Valo /* 3212e705c121SKalle Valo * Update pointers to reflect actual values after 3213e705c121SKalle Valo * shifting 3214e705c121SKalle Valo */ 321591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3216fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3217fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 321891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3219fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3220fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3221fd527eb5SGolan Ben Ami } else { 3222e705c121SKalle Valo base = iwl_read_prph(trans, base) << 322391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3224fd527eb5SGolan Ben Ami } 3225fd527eb5SGolan Ben Ami 3226e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3227e705c121SKalle Valo monitor_len / sizeof(u32)); 322891c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3229e705c121SKalle Valo monitor_len = 3230e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3231e705c121SKalle Valo fw_mon_data, 3232e705c121SKalle Valo monitor_len); 3233e705c121SKalle Valo } else { 3234e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3235e705c121SKalle Valo monitor_len = 0; 3236e705c121SKalle Valo } 3237e705c121SKalle Valo 3238e705c121SKalle Valo len += monitor_len; 3239e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3240e705c121SKalle Valo } 3241e705c121SKalle Valo 3242e705c121SKalle Valo return len; 3243e705c121SKalle Valo } 3244e705c121SKalle Valo 324593079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3246e705c121SKalle Valo { 324769f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3248da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3249da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 325069f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 325169f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 325291c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3253da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3254e705c121SKalle Valo 325591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 325691c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3257fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3258fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 325991c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3260fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3261fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3262fd527eb5SGolan Ben Ami 3263fd527eb5SGolan Ben Ami monitor_len = 3264fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 326591c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3266fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3267fd527eb5SGolan Ben Ami } else { 326891c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 326991c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3270e705c121SKalle Valo 3271e705c121SKalle Valo base = iwl_read_prph(trans, base) << 327291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3273e705c121SKalle Valo end = iwl_read_prph(trans, end) << 327491c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3275e705c121SKalle Valo 3276e705c121SKalle Valo /* Make "end" point to the actual end */ 3277286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3278fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 327991c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 328091c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3281e705c121SKalle Valo monitor_len = end - base; 3282fd527eb5SGolan Ben Ami } 3283da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3284da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3285e705c121SKalle Valo monitor_len; 3286da752717SShahar S Matityahu return monitor_len; 3287e705c121SKalle Valo } 3288da752717SShahar S Matityahu return 0; 3289da752717SShahar S Matityahu } 3290da752717SShahar S Matityahu 3291fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3292fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3293fdb70083SJohannes Berg u32 dump_mask, 3294fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3295fdb70083SJohannes Berg void *sanitize_ctx) 3296da752717SShahar S Matityahu { 3297da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3298da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 32994f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3300da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3301da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3302fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3303da752717SShahar S Matityahu int i, ptr; 3304da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3305286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 330679f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 330779f033f6SSara Sharon 330879f033f6SSara Sharon if (!dump_mask) 330979f033f6SSara Sharon return NULL; 3310da752717SShahar S Matityahu 3311da752717SShahar S Matityahu /* transport dump header */ 3312da752717SShahar S Matityahu len = sizeof(*dump_data); 3313da752717SShahar S Matityahu 3314da752717SShahar S Matityahu /* host commands */ 3315e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3316da752717SShahar S Matityahu len += sizeof(*data) + 33178672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 33188672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3319da752717SShahar S Matityahu 3320da752717SShahar S Matityahu /* FW monitor */ 3321fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3322da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3323e705c121SKalle Valo 3324e705c121SKalle Valo /* CSR registers */ 332579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3326e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3327e705c121SKalle Valo 3328e705c121SKalle Valo /* FH registers */ 332979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3330286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3331723b45e2SLiad Kaufman len += sizeof(*data) + 3332ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3333ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3334723b45e2SLiad Kaufman else 3335723b45e2SLiad Kaufman len += sizeof(*data) + 3336520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3337520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3338520f03eaSShahar S Matityahu } 3339e705c121SKalle Valo 3340e705c121SKalle Valo if (dump_rbs) { 334178485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 334278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3343e705c121SKalle Valo /* RBs */ 33440307c839SGolan Ben Ami num_rbs = 33450307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3346e705c121SKalle Valo & 0x0FFF; 334778485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3348e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3349e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3350e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3351e705c121SKalle Valo } 3352e705c121SKalle Valo 33535538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3354286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3355505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 33565538409bSLiad Kaufman len += sizeof(*data) + 33575538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3358505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 33595538409bSLiad Kaufman 3360e705c121SKalle Valo dump_data = vzalloc(len); 3361e705c121SKalle Valo if (!dump_data) 3362e705c121SKalle Valo return NULL; 3363e705c121SKalle Valo 3364e705c121SKalle Valo len = 0; 3365e705c121SKalle Valo data = (void *)dump_data->data; 3366520f03eaSShahar S Matityahu 3367e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3368885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3369520f03eaSShahar S Matityahu 3370e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3371e705c121SKalle Valo txcmd = (void *)data->data; 3372e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3373bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3374bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33750cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 337608326a97SJohannes Berg u8 tfdidx; 3377e705c121SKalle Valo u32 caplen, cmdlen; 3378e705c121SKalle Valo 337908326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 338008326a97SJohannes Berg tfdidx = idx; 338108326a97SJohannes Berg else 338208326a97SJohannes Berg tfdidx = ptr; 338308326a97SJohannes Berg 3384520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 338508326a97SJohannes Berg (u8 *)cmdq->tfds + 338608326a97SJohannes Berg tfd_size * tfdidx); 3387e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3388e705c121SKalle Valo 3389e705c121SKalle Valo if (cmdlen) { 3390e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3391e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3392e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3393520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3394520f03eaSShahar S Matityahu caplen); 3395fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3396fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3397fdb70083SJohannes Berg txcmd->data, 3398fdb70083SJohannes Berg caplen); 3399e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3400e705c121SKalle Valo } 3401e705c121SKalle Valo 34020cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3403e705c121SKalle Valo } 3404e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3405e705c121SKalle Valo 3406e705c121SKalle Valo data->len = cpu_to_le32(len); 3407e705c121SKalle Valo len += sizeof(*data); 3408e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3409520f03eaSShahar S Matityahu } 3410e705c121SKalle Valo 341179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3412e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 341379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3414e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3415e705c121SKalle Valo if (dump_rbs) 3416e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3417e705c121SKalle Valo 34185538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3419286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 342079b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3421505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 34225538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3423505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 34245538409bSLiad Kaufman 34255538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 34265538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 34275538409bSLiad Kaufman paging = (void *)data->data; 34285538409bSLiad Kaufman paging->index = cpu_to_le32(i); 34295538409bSLiad Kaufman memcpy(paging->data, 3430505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 34315538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 34325538409bSLiad Kaufman 34335538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 34345538409bSLiad Kaufman } 34355538409bSLiad Kaufman } 343679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3437e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3438e705c121SKalle Valo 3439e705c121SKalle Valo dump_data->len = len; 3440e705c121SKalle Valo 3441e705c121SKalle Valo return dump_data; 3442e705c121SKalle Valo } 3443e705c121SKalle Valo 34443161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 34454cbb8e50SLuciano Coelho { 34463161a34dSMordechay Goodstein if (enable) 34473161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 34483161a34dSMordechay Goodstein else 34493161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 34504cbb8e50SLuciano Coelho } 34514cbb8e50SLuciano Coelho 34523161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 34534cbb8e50SLuciano Coelho { 34543161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 34553161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 34563161a34dSMordechay Goodstein 34573161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 34583161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3459571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3460571836a0SMike Golant sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3461571836a0SMike Golant else 34623161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 34633161a34dSMordechay Goodstein } else { 34643161a34dSMordechay Goodstein inta_addr = CSR_INT; 34653161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 34664cbb8e50SLuciano Coelho } 34673161a34dSMordechay Goodstein 34683161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 34693161a34dSMordechay Goodstein } 34704cbb8e50SLuciano Coelho 3471623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3472623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3473623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3474623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3475623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3476623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3477623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3478623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3479623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 34807f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3481623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3482623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3483870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3484623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3485623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3486623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3487623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3488623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3489d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 34903161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 3491c0941aceSMukesh Sisodiya .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3492c0941aceSMukesh Sisodiya .imr_dma_data = iwl_trans_pcie_copy_imr \ 3493623e7766SSara Sharon 3494e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3495623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3496e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3497e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3498e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3499e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3500e705c121SKalle Valo 350113f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3502e705c121SKalle Valo 3503e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3504a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3505e705c121SKalle Valo 3506e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3507e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3508e705c121SKalle Valo 350942db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 351042db09c1SLiad Kaufman 3511d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3512d6d517b7SSara Sharon 3513a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 35140cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3515f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3516f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3517f7805b33SLior Cohen #endif 3518623e7766SSara Sharon }; 3519e705c121SKalle Valo 3520623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3521623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3522623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3523eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3524eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 352577c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3526e705c121SKalle Valo 352713f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3528e705c121SKalle Valo 35290cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3530a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3531623e7766SSara Sharon 3532a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3533ba7136f3SAlex Malamud 35340cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 35350cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3536d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 353792536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 35386654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 35399dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3540f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3541f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3542f7805b33SLior Cohen #endif 3543e705c121SKalle Valo }; 3544e705c121SKalle Valo 3545e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3546e705c121SKalle Valo const struct pci_device_id *ent, 35477e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3548e705c121SKalle Valo { 3549e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3550e705c121SKalle Valo struct iwl_trans *trans; 3551fda1bd0dSMordechay Goodstein int ret, addr_size; 3552a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3553f00c3f9eSJohannes Berg void __iomem * const *table; 3554a89c72ffSJohannes Berg 3555fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3556a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3557e705c121SKalle Valo 35585a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 35595a41a86cSSharon Dvir if (ret) 35605a41a86cSSharon Dvir return ERR_PTR(ret); 35615a41a86cSSharon Dvir 3562a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3563fda1bd0dSMordechay Goodstein cfg_trans); 3564e705c121SKalle Valo if (!trans) 3565e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3566e705c121SKalle Valo 3567e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3568e705c121SKalle Valo 3569e705c121SKalle Valo trans_pcie->trans = trans; 3570326477e4SJohannes Berg trans_pcie->opmode_down = true; 3571e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3572e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3573cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3574e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3575e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3576906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3577c0941aceSMukesh Sisodiya init_waitqueue_head(&trans_pcie->imr_waitq); 35788188a18eSJohannes Berg 35798188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35808188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35818188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35828188a18eSJohannes Berg ret = -ENOMEM; 35838188a18eSJohannes Berg goto out_free_trans; 35848188a18eSJohannes Berg } 35858188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35868188a18eSJohannes Berg 3587c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3588e705c121SKalle Valo 35897e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3590e705c121SKalle Valo /* 3591e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3592e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3593e705c121SKalle Valo * lot of power. 3594e705c121SKalle Valo */ 3595e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3596e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3597e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3598e705c121SKalle Valo } 3599e705c121SKalle Valo 36009416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 36019416560eSGolan Ben Ami 3602e705c121SKalle Valo pci_set_master(pdev); 3603e705c121SKalle Valo 3604885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3605ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3606e705c121SKalle Valo if (ret) { 3607ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3608e705c121SKalle Valo /* both attempts failed: */ 3609e705c121SKalle Valo if (ret) { 3610e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 36115a41a86cSSharon Dvir goto out_no_pci; 3612e705c121SKalle Valo } 3613e705c121SKalle Valo } 3614e705c121SKalle Valo 36155a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3616e705c121SKalle Valo if (ret) { 36175a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 36185a41a86cSSharon Dvir goto out_no_pci; 3619e705c121SKalle Valo } 3620e705c121SKalle Valo 3621f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3622f00c3f9eSJohannes Berg if (!table) { 36235a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3624f00c3f9eSJohannes Berg ret = -ENOMEM; 3625f00c3f9eSJohannes Berg goto out_no_pci; 3626f00c3f9eSJohannes Berg } 3627f00c3f9eSJohannes Berg 3628f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3629f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3630f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3631e705c121SKalle Valo ret = -ENODEV; 36325a41a86cSSharon Dvir goto out_no_pci; 3633e705c121SKalle Valo } 3634e705c121SKalle Valo 3635e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3636e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3637e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3638e705c121SKalle Valo 3639e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3640e705c121SKalle Valo iwl_disable_interrupts(trans); 3641e705c121SKalle Valo 3642e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 36439a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 36449a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 36459a098a89SRajat Jain ret = -EIO; 36469a098a89SRajat Jain goto out_no_pci; 36479a098a89SRajat Jain } 36489a098a89SRajat Jain 3649e705c121SKalle Valo /* 3650e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3651e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3652e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3653e705c121SKalle Valo * in the old format. 3654e705c121SKalle Valo */ 36554adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 365655c6d8f8SMike Golant trans->hw_rev_step = trans->hw_rev & 0xF; 365755c6d8f8SMike Golant else 365855c6d8f8SMike Golant trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3659e705c121SKalle Valo 366099be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 366199be6166SLuca Coelho 36627e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3663e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3664e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3665e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3666e705c121SKalle Valo 3667e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3668e5f3f215SHaim Dreyfuss 3669c239feecSJohannes Berg 36702e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36712388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36722388bd7bSDan Carpenter if (ret) 36735a41a86cSSharon Dvir goto out_no_pci; 36742e5d4a8fSHaim Dreyfuss } else { 3675e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3676e705c121SKalle Valo if (ret) 36775a41a86cSSharon Dvir goto out_no_pci; 3678e705c121SKalle Valo 36795a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36805a41a86cSSharon Dvir iwl_pcie_isr, 3681e705c121SKalle Valo iwl_pcie_irq_handler, 3682e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3683e705c121SKalle Valo if (ret) { 3684e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3685e705c121SKalle Valo goto out_free_ict; 3686e705c121SKalle Valo } 36872e5d4a8fSHaim Dreyfuss } 3688e705c121SKalle Valo 3689f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3690f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3691f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3692f7805b33SLior Cohen #endif 3693f7805b33SLior Cohen 3694a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3695a9248de4SShahar S Matityahu 3696e705c121SKalle Valo return trans; 3697e705c121SKalle Valo 3698e705c121SKalle Valo out_free_ict: 3699e705c121SKalle Valo iwl_pcie_free_ict(trans); 3700e705c121SKalle Valo out_no_pci: 37018188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 37028188a18eSJohannes Berg out_free_trans: 3703e705c121SKalle Valo iwl_trans_free(trans); 3704e705c121SKalle Valo return ERR_PTR(ret); 3705e705c121SKalle Valo } 3706c0941aceSMukesh Sisodiya 3707c0941aceSMukesh Sisodiya void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3708c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3709c0941aceSMukesh Sisodiya { 3710c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_UREG_CHICK, 3711c0941aceSMukesh Sisodiya iwl_read_prph(trans, IMR_UREG_CHICK) | 3712c0941aceSMukesh Sisodiya IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3713c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3714c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3715c0941aceSMukesh Sisodiya (u32)(src_addr & 0xFFFFFFFF)); 3716c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3717c0941aceSMukesh Sisodiya iwl_get_dma_hi_addr(src_addr)); 3718c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3719c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3720c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3721c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3722c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3723c0941aceSMukesh Sisodiya } 3724c0941aceSMukesh Sisodiya 3725c0941aceSMukesh Sisodiya int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3726c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3727c0941aceSMukesh Sisodiya { 3728c0941aceSMukesh Sisodiya struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3729c0941aceSMukesh Sisodiya int ret = -1; 3730c0941aceSMukesh Sisodiya 3731c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_REQUESTED; 3732c0941aceSMukesh Sisodiya iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3733c0941aceSMukesh Sisodiya ret = wait_event_timeout(trans_pcie->imr_waitq, 3734c0941aceSMukesh Sisodiya trans_pcie->imr_status != 3735c0941aceSMukesh Sisodiya IMR_D2S_REQUESTED, 5 * HZ); 3736c0941aceSMukesh Sisodiya if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3737c0941aceSMukesh Sisodiya IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3738c0941aceSMukesh Sisodiya iwl_trans_pcie_dump_regs(trans); 3739c0941aceSMukesh Sisodiya return -ETIMEDOUT; 3740c0941aceSMukesh Sisodiya } 3741c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_IDLE; 3742c0941aceSMukesh Sisodiya return 0; 3743c0941aceSMukesh Sisodiya } 3744