18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 276d19a5ebSEmmanuel Grumbach #include "mei/iwl-mei.h" 28e705c121SKalle Valo #include "internal.h" 29e705c121SKalle Valo #include "iwl-fh.h" 306654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 31e705c121SKalle Valo 32e705c121SKalle Valo /* extended range in FW SRAM */ 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 34e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35e705c121SKalle Valo 364290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37a6d24fadSRajat Jain { 38c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 39c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 40c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 41a6d24fadSRajat Jain #define PREFIX_LEN 32 42a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 44a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 45a6d24fadSRajat Jain char *prefix; 46a6d24fadSRajat Jain 47a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 48a6d24fadSRajat Jain return; 49a6d24fadSRajat Jain 50a6d24fadSRajat Jain /* Should be a multiple of 4 */ 51a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54c4d3f2eeSLuca Coelho 55a6d24fadSRajat Jain /* Alloc a max size buffer */ 56a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60c4d3f2eeSLuca Coelho 61a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 62a6d24fadSRajat Jain if (!buf) 63a6d24fadSRajat Jain return; 64a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 65a6d24fadSRajat Jain 66a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67a6d24fadSRajat Jain 68a6d24fadSRajat Jain /* Print wifi device registers */ 69a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 71a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 73a6d24fadSRajat Jain goto err_read; 74a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75a6d24fadSRajat Jain 76a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 79a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80a6d24fadSRajat Jain 81a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82a6d24fadSRajat Jain if (pos) { 83a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 86a6d24fadSRajat Jain goto err_read; 87a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88a6d24fadSRajat Jain 32, 4, buf, i, 0); 89a6d24fadSRajat Jain } 90a6d24fadSRajat Jain 91a6d24fadSRajat Jain /* Print parent device registers next */ 92a6d24fadSRajat Jain if (!pdev->bus->self) 93a6d24fadSRajat Jain goto out; 94a6d24fadSRajat Jain 95a6d24fadSRajat Jain pdev = pdev->bus->self; 96a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97a6d24fadSRajat Jain 98a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99a6d24fadSRajat Jain pci_name(pdev)); 100c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 102a6d24fadSRajat Jain goto err_read; 103a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Print root port AER registers */ 106a6d24fadSRajat Jain pos = 0; 107a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 108a6d24fadSRajat Jain if (pdev) 109a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110a6d24fadSRajat Jain if (pos) { 111a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112a6d24fadSRajat Jain pci_name(pdev)); 113a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 116a6d24fadSRajat Jain goto err_read; 117a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118a6d24fadSRajat Jain 4, buf, i, 0); 119a6d24fadSRajat Jain } 120f3402d6dSSara Sharon goto out; 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain err_read: 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 125a6d24fadSRajat Jain out: 126a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 127a6d24fadSRajat Jain kfree(buf); 128a6d24fadSRajat Jain } 129a6d24fadSRajat Jain 130870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 131870c2a11SGolan Ben Ami { 132870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1331b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1341b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_GP_CNTRL, 1351b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_SW_RESET); 1361b6598c3SRoee Goldfiner else 1371b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_RESET, 1381b6598c3SRoee Goldfiner CSR_RESET_REG_FLAG_SW_RESET); 139870c2a11SGolan Ben Ami usleep_range(5000, 6000); 140870c2a11SGolan Ben Ami } 141870c2a11SGolan Ben Ami 142e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 143e705c121SKalle Valo { 14469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 145e705c121SKalle Valo 14669f0e505SShahar S Matityahu if (!fw_mon->size) 14769f0e505SShahar S Matityahu return; 14869f0e505SShahar S Matityahu 14969f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 15069f0e505SShahar S Matityahu fw_mon->physical); 15169f0e505SShahar S Matityahu 15269f0e505SShahar S Matityahu fw_mon->block = NULL; 15369f0e505SShahar S Matityahu fw_mon->physical = 0; 15469f0e505SShahar S Matityahu fw_mon->size = 0; 155e705c121SKalle Valo } 156e705c121SKalle Valo 15788964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 15888964b2eSSara Sharon u8 max_power, u8 min_power) 159e705c121SKalle Valo { 16069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 16169f0e505SShahar S Matityahu void *block = NULL; 16269f0e505SShahar S Matityahu dma_addr_t physical = 0; 163e705c121SKalle Valo u32 size = 0; 164e705c121SKalle Valo u8 power; 165e705c121SKalle Valo 16669f0e505SShahar S Matityahu if (fw_mon->size) 16769f0e505SShahar S Matityahu return; 16869f0e505SShahar S Matityahu 16988964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 170e705c121SKalle Valo size = BIT(power); 17169f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1722d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 17369f0e505SShahar S Matityahu if (!block) 174e705c121SKalle Valo continue; 175e705c121SKalle Valo 176e705c121SKalle Valo IWL_INFO(trans, 177c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 178c5f97542SShahar S Matityahu size); 179e705c121SKalle Valo break; 180e705c121SKalle Valo } 181e705c121SKalle Valo 18269f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 183e705c121SKalle Valo return; 184e705c121SKalle Valo 185e705c121SKalle Valo if (power != max_power) 186e705c121SKalle Valo IWL_ERR(trans, 187e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 188e705c121SKalle Valo (unsigned long)BIT(power - 10), 189e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 190e705c121SKalle Valo 19169f0e505SShahar S Matityahu fw_mon->block = block; 19269f0e505SShahar S Matityahu fw_mon->physical = physical; 19369f0e505SShahar S Matityahu fw_mon->size = size; 19488964b2eSSara Sharon } 19588964b2eSSara Sharon 19688964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 19788964b2eSSara Sharon { 19888964b2eSSara Sharon if (!max_power) { 19988964b2eSSara Sharon /* default max_power is maximum */ 20088964b2eSSara Sharon max_power = 26; 20188964b2eSSara Sharon } else { 20288964b2eSSara Sharon max_power += 11; 20388964b2eSSara Sharon } 20488964b2eSSara Sharon 20588964b2eSSara Sharon if (WARN(max_power > 26, 20688964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 20788964b2eSSara Sharon max_power)) 20888964b2eSSara Sharon return; 20988964b2eSSara Sharon 21069f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 21188964b2eSSara Sharon return; 21288964b2eSSara Sharon 21388964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 214e705c121SKalle Valo } 215e705c121SKalle Valo 216e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 217e705c121SKalle Valo { 218e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 219e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 220e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 221e705c121SKalle Valo } 222e705c121SKalle Valo 223e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 224e705c121SKalle Valo { 225e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 226e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 227e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 228e705c121SKalle Valo } 229e705c121SKalle Valo 230e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 231e705c121SKalle Valo { 232e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 233e705c121SKalle Valo return; 234e705c121SKalle Valo 235e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 236e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 237e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 238e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 239e705c121SKalle Valo else 240e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 241e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 242e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 243e705c121SKalle Valo } 244e705c121SKalle Valo 245e705c121SKalle Valo /* PCI registers */ 246e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 247e705c121SKalle Valo 248eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 249e705c121SKalle Valo { 250e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251e705c121SKalle Valo u16 lctl; 252e705c121SKalle Valo u16 cap; 253e705c121SKalle Valo 254e705c121SKalle Valo /* 255cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 256cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 257cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 258e705c121SKalle Valo */ 2593d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 260cc894b85SLuca Coelho 261cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 262e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 263e705c121SKalle Valo 264e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 265e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 266d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 267e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 268e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 269e705c121SKalle Valo } 270e705c121SKalle Valo 271e705c121SKalle Valo /* 272e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 273e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 274e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 275e705c121SKalle Valo */ 276e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 277e705c121SKalle Valo { 27852b6e168SEmmanuel Grumbach int ret; 27952b6e168SEmmanuel Grumbach 280e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 281e705c121SKalle Valo 282e705c121SKalle Valo /* 283e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 284e705c121SKalle Valo * bits already set by default after reset. 285e705c121SKalle Valo */ 286e705c121SKalle Valo 287e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 288286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 289e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 290e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 291e705c121SKalle Valo 292e705c121SKalle Valo /* 293e705c121SKalle Valo * Disable L0s without affecting L1; 294e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 295e705c121SKalle Valo */ 296e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 297e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 298e705c121SKalle Valo 299e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 300e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 301e705c121SKalle Valo 302e705c121SKalle Valo /* 303e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 304e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 305e705c121SKalle Valo */ 306e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 307e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 308e705c121SKalle Valo 309e705c121SKalle Valo iwl_pcie_apm_config(trans); 310e705c121SKalle Valo 311e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 312286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 31377d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 314e705c121SKalle Valo 315425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 316c96b5eecSJohannes Berg if (ret) 31752b6e168SEmmanuel Grumbach return ret; 318e705c121SKalle Valo 319e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 320e705c121SKalle Valo /* 321e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 322e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 323e705c121SKalle Valo * not related to host_interrupt_operation_mode. 324e705c121SKalle Valo * 325e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 326e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 327e705c121SKalle Valo * that we wake up from L1 on time. 328e705c121SKalle Valo * 329e705c121SKalle Valo * This looks weird: read twice the same register, discard the 330e705c121SKalle Valo * value, set a bit, and yet again, read that same register 331e705c121SKalle Valo * just to discard the value. But that's the way the hardware 332e705c121SKalle Valo * seems to like it. 333e705c121SKalle Valo */ 334e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 335e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 336e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 337e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 338e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 339e705c121SKalle Valo } 340e705c121SKalle Valo 341e705c121SKalle Valo /* 342e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 343e705c121SKalle Valo * 344e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 345e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 346e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 347e705c121SKalle Valo */ 348e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 349e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 350e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 351e705c121SKalle Valo udelay(20); 352e705c121SKalle Valo 353e705c121SKalle Valo /* Disable L1-Active */ 354e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 355e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 356e705c121SKalle Valo 357e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 358e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 359e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 360e705c121SKalle Valo } 361e705c121SKalle Valo 362e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 363e705c121SKalle Valo 36452b6e168SEmmanuel Grumbach return 0; 365e705c121SKalle Valo } 366e705c121SKalle Valo 367e705c121SKalle Valo /* 368e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 369e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 370e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 371e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 372e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 373e705c121SKalle Valo */ 374e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 375e705c121SKalle Valo { 376e705c121SKalle Valo int ret; 377e705c121SKalle Valo u32 apmg_gp1_reg; 378e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 379e705c121SKalle Valo u32 dl_cfg_reg; 380e705c121SKalle Valo 381e705c121SKalle Valo /* Force XTAL ON */ 382e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 383e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 384e705c121SKalle Valo 385870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 386e705c121SKalle Valo 387425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 388c96b5eecSJohannes Berg if (WARN_ON(ret)) { 389e705c121SKalle Valo /* Release XTAL ON request */ 390e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 391e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 392e705c121SKalle Valo return; 393e705c121SKalle Valo } 394e705c121SKalle Valo 395e705c121SKalle Valo /* 396e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 397e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 398e705c121SKalle Valo */ 399e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 400e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 401e705c121SKalle Valo 402e705c121SKalle Valo /* 403e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 404e705c121SKalle Valo * caused by APMG idle state. 405e705c121SKalle Valo */ 406e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 407e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 408e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 409e705c121SKalle Valo apmg_xtal_cfg_reg | 410e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 411e705c121SKalle Valo 412870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 415e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 417e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 418e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 419e705c121SKalle Valo 420e705c121SKalle Valo /* Clear delay line clock power up */ 421e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 422e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 423e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 424e705c121SKalle Valo 425e705c121SKalle Valo /* 426e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 427e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 428e705c121SKalle Valo */ 429e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 430e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 431e705c121SKalle Valo 432e705c121SKalle Valo /* 433e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 434e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 435e705c121SKalle Valo */ 4366dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 437e705c121SKalle Valo 438e705c121SKalle Valo /* Activates XTAL resources monitor */ 439e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 440e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 441e705c121SKalle Valo 442e705c121SKalle Valo /* Release XTAL ON request */ 443e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 444e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 445e705c121SKalle Valo udelay(10); 446e705c121SKalle Valo 447e705c121SKalle Valo /* Release APMG XTAL */ 448e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 449e705c121SKalle Valo apmg_xtal_cfg_reg & 450e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 451e705c121SKalle Valo } 452e705c121SKalle Valo 453e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 454e705c121SKalle Valo { 455e8c8935eSJohannes Berg int ret; 456e705c121SKalle Valo 457e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4589ce041f5SJohannes Berg 4599ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4609ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4619ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4629ce041f5SJohannes Berg 4639ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4649ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4659ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4669ce041f5SJohannes Berg 100); 46744b2dd40SRoee Goldfiner msleep(100); 4689ce041f5SJohannes Berg } else { 4696dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 470e705c121SKalle Valo 4716dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4726dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4736dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4749ce041f5SJohannes Berg } 4759ce041f5SJohannes Berg 476e705c121SKalle Valo if (ret < 0) 477e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 478e705c121SKalle Valo 479e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 480e705c121SKalle Valo } 481e705c121SKalle Valo 482e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 483e705c121SKalle Valo { 484e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 485e705c121SKalle Valo 486e705c121SKalle Valo if (op_mode_leave) { 487e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 488e705c121SKalle Valo iwl_pcie_apm_init(trans); 489e705c121SKalle Valo 490e705c121SKalle Valo /* inform ME that we are leaving */ 491286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 492e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 493e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 494286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 49579b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 496e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 497e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 498e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 499e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 500e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 501e705c121SKalle Valo mdelay(1); 502e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 503e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 504e705c121SKalle Valo } 505e705c121SKalle Valo mdelay(5); 506e705c121SKalle Valo } 507e705c121SKalle Valo 508e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 509e705c121SKalle Valo 510e705c121SKalle Valo /* Stop device's DMA activity */ 511e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 512e705c121SKalle Valo 513e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 514e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 515e705c121SKalle Valo return; 516e705c121SKalle Valo } 517e705c121SKalle Valo 518870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 519e705c121SKalle Valo 520e705c121SKalle Valo /* 521e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 522e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 523e705c121SKalle Valo */ 5246dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 525e705c121SKalle Valo } 526e705c121SKalle Valo 527e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 528e705c121SKalle Valo { 529e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 53052b6e168SEmmanuel Grumbach int ret; 531e705c121SKalle Valo 532e705c121SKalle Valo /* nic_init */ 53325edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 53452b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 53525edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 536e705c121SKalle Valo 53752b6e168SEmmanuel Grumbach if (ret) 53852b6e168SEmmanuel Grumbach return ret; 53952b6e168SEmmanuel Grumbach 540e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 541e705c121SKalle Valo 542e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 543e705c121SKalle Valo 544e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5459cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5469cf671d6SEmmanuel Grumbach if (ret) 5479cf671d6SEmmanuel Grumbach return ret; 548e705c121SKalle Valo 549e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5509cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5519cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 552e705c121SKalle Valo return -ENOMEM; 5539cf671d6SEmmanuel Grumbach } 554e705c121SKalle Valo 555286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 556e705c121SKalle Valo /* enable shadow regs in HW */ 557e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 558e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 559e705c121SKalle Valo } 560e705c121SKalle Valo 561e705c121SKalle Valo return 0; 562e705c121SKalle Valo } 563e705c121SKalle Valo 564e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 565e705c121SKalle Valo 566e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 567e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 568e705c121SKalle Valo { 569e705c121SKalle Valo int ret; 570e705c121SKalle Valo 571e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 572e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 573e705c121SKalle Valo 574e705c121SKalle Valo /* See if we got it */ 575e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 576e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 577e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 578e705c121SKalle Valo HW_READY_TIMEOUT); 579e705c121SKalle Valo 580e705c121SKalle Valo if (ret >= 0) 581e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 582e705c121SKalle Valo 583e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 584e705c121SKalle Valo return ret; 585e705c121SKalle Valo } 586e705c121SKalle Valo 587e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 588eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 589e705c121SKalle Valo { 590e705c121SKalle Valo int ret; 591e705c121SKalle Valo int t = 0; 592e705c121SKalle Valo int iter; 593e705c121SKalle Valo 594e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 595e705c121SKalle Valo 596e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 597e705c121SKalle Valo /* If the card is ready, exit 0 */ 5986d19a5ebSEmmanuel Grumbach if (ret >= 0) { 5996d19a5ebSEmmanuel Grumbach trans->csme_own = false; 600e705c121SKalle Valo return 0; 6016d19a5ebSEmmanuel Grumbach } 602e705c121SKalle Valo 603e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 604e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 605192185d6SJohannes Berg usleep_range(1000, 2000); 606e705c121SKalle Valo 607e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 608e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 609e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 610e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 611e705c121SKalle Valo 612e705c121SKalle Valo do { 613e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 6146d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6156d19a5ebSEmmanuel Grumbach trans->csme_own = false; 616e705c121SKalle Valo return 0; 6176d19a5ebSEmmanuel Grumbach } 6186d19a5ebSEmmanuel Grumbach 6196d19a5ebSEmmanuel Grumbach if (iwl_mei_is_connected()) { 6206d19a5ebSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 6216d19a5ebSEmmanuel Grumbach "Couldn't prepare the card but SAP is connected\n"); 6226d19a5ebSEmmanuel Grumbach trans->csme_own = true; 6236d19a5ebSEmmanuel Grumbach if (trans->trans_cfg->device_family != 6246d19a5ebSEmmanuel Grumbach IWL_DEVICE_FAMILY_9000) 6256d19a5ebSEmmanuel Grumbach IWL_ERR(trans, 6266d19a5ebSEmmanuel Grumbach "SAP not supported for this NIC family\n"); 6276d19a5ebSEmmanuel Grumbach 6286d19a5ebSEmmanuel Grumbach return -EBUSY; 6296d19a5ebSEmmanuel Grumbach } 630e705c121SKalle Valo 631e705c121SKalle Valo usleep_range(200, 1000); 632e705c121SKalle Valo t += 200; 633e705c121SKalle Valo } while (t < 150000); 634e705c121SKalle Valo msleep(25); 635e705c121SKalle Valo } 636e705c121SKalle Valo 637e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 638e705c121SKalle Valo 639e705c121SKalle Valo return ret; 640e705c121SKalle Valo } 641e705c121SKalle Valo 642e705c121SKalle Valo /* 643e705c121SKalle Valo * ucode 644e705c121SKalle Valo */ 645564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 646564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 647564cdce7SSara Sharon u32 byte_cnt) 648e705c121SKalle Valo { 649bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 650e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 651e705c121SKalle Valo 652bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 653e705c121SKalle Valo dst_addr); 654e705c121SKalle Valo 655bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 656e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 657e705c121SKalle Valo 658bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 659e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 660e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 661e705c121SKalle Valo 662bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 663bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 664bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 665e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 666e705c121SKalle Valo 667bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 668e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 669e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 670e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 671564cdce7SSara Sharon } 672e705c121SKalle Valo 673564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 674564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 675564cdce7SSara Sharon u32 byte_cnt) 676564cdce7SSara Sharon { 677564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 678564cdce7SSara Sharon int ret; 679564cdce7SSara Sharon 680564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 681564cdce7SSara Sharon 6821ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 683564cdce7SSara Sharon return -EIO; 684564cdce7SSara Sharon 685564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 686564cdce7SSara Sharon byte_cnt); 6871ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 688bac842daSEmmanuel Grumbach 689e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 690e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 691e705c121SKalle Valo if (!ret) { 692e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 693fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 694e705c121SKalle Valo return -ETIMEDOUT; 695e705c121SKalle Valo } 696e705c121SKalle Valo 697e705c121SKalle Valo return 0; 698e705c121SKalle Valo } 699e705c121SKalle Valo 700e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 701e705c121SKalle Valo const struct fw_desc *section) 702e705c121SKalle Valo { 703e705c121SKalle Valo u8 *v_addr; 704e705c121SKalle Valo dma_addr_t p_addr; 705e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 706e705c121SKalle Valo int ret = 0; 707e705c121SKalle Valo 708e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 709e705c121SKalle Valo section_num); 710e705c121SKalle Valo 711e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 712e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 713e705c121SKalle Valo if (!v_addr) { 714e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 715e705c121SKalle Valo chunk_sz = PAGE_SIZE; 716e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 717e705c121SKalle Valo &p_addr, GFP_KERNEL); 718e705c121SKalle Valo if (!v_addr) 719e705c121SKalle Valo return -ENOMEM; 720e705c121SKalle Valo } 721e705c121SKalle Valo 722e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 723e705c121SKalle Valo u32 copy_size, dst_addr; 724e705c121SKalle Valo bool extended_addr = false; 725e705c121SKalle Valo 726e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 727e705c121SKalle Valo dst_addr = section->offset + offset; 728e705c121SKalle Valo 729e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 730e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 731e705c121SKalle Valo extended_addr = true; 732e705c121SKalle Valo 733e705c121SKalle Valo if (extended_addr) 734e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 735e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 736e705c121SKalle Valo 737e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 738e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 739e705c121SKalle Valo copy_size); 740e705c121SKalle Valo 741e705c121SKalle Valo if (extended_addr) 742e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 743e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 744e705c121SKalle Valo 745e705c121SKalle Valo if (ret) { 746e705c121SKalle Valo IWL_ERR(trans, 747e705c121SKalle Valo "Could not load the [%d] uCode section\n", 748e705c121SKalle Valo section_num); 749e705c121SKalle Valo break; 750e705c121SKalle Valo } 751e705c121SKalle Valo } 752e705c121SKalle Valo 753e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 754e705c121SKalle Valo return ret; 755e705c121SKalle Valo } 756e705c121SKalle Valo 757e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 758e705c121SKalle Valo const struct fw_img *image, 759e705c121SKalle Valo int cpu, 760e705c121SKalle Valo int *first_ucode_section) 761e705c121SKalle Valo { 762e705c121SKalle Valo int shift_param; 763e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 764e705c121SKalle Valo u32 val, last_read_idx = 0; 765e705c121SKalle Valo 766e705c121SKalle Valo if (cpu == 1) { 767e705c121SKalle Valo shift_param = 0; 768e705c121SKalle Valo *first_ucode_section = 0; 769e705c121SKalle Valo } else { 770e705c121SKalle Valo shift_param = 16; 771e705c121SKalle Valo (*first_ucode_section)++; 772e705c121SKalle Valo } 773e705c121SKalle Valo 774eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 775e705c121SKalle Valo last_read_idx = i; 776e705c121SKalle Valo 777e705c121SKalle Valo /* 778e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 779e705c121SKalle Valo * CPU1 to CPU2. 780e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 781e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 782e705c121SKalle Valo */ 783e705c121SKalle Valo if (!image->sec[i].data || 784e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 785e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 786e705c121SKalle Valo IWL_DEBUG_FW(trans, 787e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 788e705c121SKalle Valo i); 789e705c121SKalle Valo break; 790e705c121SKalle Valo } 791e705c121SKalle Valo 792e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 793e705c121SKalle Valo if (ret) 794e705c121SKalle Valo return ret; 795e705c121SKalle Valo 796d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 797e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 798e705c121SKalle Valo val = val | (sec_num << shift_param); 799e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 800eda50cdeSSara Sharon 801e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 802e705c121SKalle Valo } 803e705c121SKalle Valo 804e705c121SKalle Valo *first_ucode_section = last_read_idx; 805e705c121SKalle Valo 8062aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8072aabdbdcSEmmanuel Grumbach 808286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 809e705c121SKalle Valo if (cpu == 1) 810d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 811d6a2c5c7SSara Sharon 0xFFFF); 812e705c121SKalle Valo else 813d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 814d6a2c5c7SSara Sharon 0xFFFFFFFF); 815d6a2c5c7SSara Sharon } else { 816d6a2c5c7SSara Sharon if (cpu == 1) 817d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 818d6a2c5c7SSara Sharon 0xFFFF); 819d6a2c5c7SSara Sharon else 820d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 821d6a2c5c7SSara Sharon 0xFFFFFFFF); 822d6a2c5c7SSara Sharon } 823e705c121SKalle Valo 824e705c121SKalle Valo return 0; 825e705c121SKalle Valo } 826e705c121SKalle Valo 827e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 828e705c121SKalle Valo const struct fw_img *image, 829e705c121SKalle Valo int cpu, 830e705c121SKalle Valo int *first_ucode_section) 831e705c121SKalle Valo { 832e705c121SKalle Valo int i, ret = 0; 833e705c121SKalle Valo u32 last_read_idx = 0; 834e705c121SKalle Valo 8353ce4a038SKirtika Ruchandani if (cpu == 1) 836e705c121SKalle Valo *first_ucode_section = 0; 8373ce4a038SKirtika Ruchandani else 838e705c121SKalle Valo (*first_ucode_section)++; 839e705c121SKalle Valo 840eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 841e705c121SKalle Valo last_read_idx = i; 842e705c121SKalle Valo 843e705c121SKalle Valo /* 844e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 845e705c121SKalle Valo * CPU1 to CPU2. 846e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 847e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 848e705c121SKalle Valo */ 849e705c121SKalle Valo if (!image->sec[i].data || 850e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 851e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 852e705c121SKalle Valo IWL_DEBUG_FW(trans, 853e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 854e705c121SKalle Valo i); 855e705c121SKalle Valo break; 856e705c121SKalle Valo } 857e705c121SKalle Valo 858e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 859e705c121SKalle Valo if (ret) 860e705c121SKalle Valo return ret; 861e705c121SKalle Valo } 862e705c121SKalle Valo 863e705c121SKalle Valo *first_ucode_section = last_read_idx; 864e705c121SKalle Valo 865e705c121SKalle Valo return 0; 866e705c121SKalle Valo } 867e705c121SKalle Valo 868593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 869593fae3eSShahar S Matityahu { 870593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 871593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 872593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 873593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 874593fae3eSShahar S Matityahu 875593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 876593fae3eSShahar S Matityahu return; 877593fae3eSShahar S Matityahu 878593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 879593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 880593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 881593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 882593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 883593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 884593fae3eSShahar S Matityahu 885593fae3eSShahar S Matityahu return; 886593fae3eSShahar S Matityahu } 887593fae3eSShahar S Matityahu 888593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 889593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 890593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 891593fae3eSShahar S Matityahu return; 892593fae3eSShahar S Matityahu 893593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 894593fae3eSShahar S Matityahu 895593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 896593fae3eSShahar S Matityahu alloc_id); 897593fae3eSShahar S Matityahu 898593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 899593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 900593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 901593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 902593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 903593fae3eSShahar S Matityahu } 904593fae3eSShahar S Matityahu 905c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 906e705c121SKalle Valo { 90791c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 90869f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 909e705c121SKalle Valo int i; 910e705c121SKalle Valo 911a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 912593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9137a14c23dSSara Sharon return; 9147a14c23dSSara Sharon } 9157a14c23dSSara Sharon 916e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 917e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 918e705c121SKalle Valo 919e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 920e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 921e705c121SKalle Valo else 922e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 923e705c121SKalle Valo 92491c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 925e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 926e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 927e705c121SKalle Valo 928e705c121SKalle Valo switch (dest->reg_ops[i].op) { 929e705c121SKalle Valo case CSR_ASSIGN: 930e705c121SKalle Valo iwl_write32(trans, addr, val); 931e705c121SKalle Valo break; 932e705c121SKalle Valo case CSR_SETBIT: 933e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 934e705c121SKalle Valo break; 935e705c121SKalle Valo case CSR_CLEARBIT: 936e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 937e705c121SKalle Valo break; 938e705c121SKalle Valo case PRPH_ASSIGN: 939e705c121SKalle Valo iwl_write_prph(trans, addr, val); 940e705c121SKalle Valo break; 941e705c121SKalle Valo case PRPH_SETBIT: 942e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 943e705c121SKalle Valo break; 944e705c121SKalle Valo case PRPH_CLEARBIT: 945e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 946e705c121SKalle Valo break; 947e705c121SKalle Valo case PRPH_BLOCKBIT: 948e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 949e705c121SKalle Valo IWL_ERR(trans, 950e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 951e705c121SKalle Valo val, addr); 952e705c121SKalle Valo goto monitor; 953e705c121SKalle Valo } 954e705c121SKalle Valo break; 955e705c121SKalle Valo default: 956e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 957e705c121SKalle Valo dest->reg_ops[i].op); 958e705c121SKalle Valo break; 959e705c121SKalle Valo } 960e705c121SKalle Valo } 961e705c121SKalle Valo 962e705c121SKalle Valo monitor: 96369f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 964e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 96569f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 966286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 967e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 96869f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 96969f0e505SShahar S Matityahu 256) >> dest->end_shift); 97062d7476dSEmmanuel Grumbach else 97162d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97269f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 97362d7476dSEmmanuel Grumbach dest->end_shift); 974e705c121SKalle Valo } 975e705c121SKalle Valo } 976e705c121SKalle Valo 977e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 978e705c121SKalle Valo const struct fw_img *image) 979e705c121SKalle Valo { 980e705c121SKalle Valo int ret = 0; 981e705c121SKalle Valo int first_ucode_section; 982e705c121SKalle Valo 983e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 984e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 985e705c121SKalle Valo 986e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 987e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 988e705c121SKalle Valo if (ret) 989e705c121SKalle Valo return ret; 990e705c121SKalle Valo 991e705c121SKalle Valo if (image->is_dual_cpus) { 992e705c121SKalle Valo /* set CPU2 header address */ 993e705c121SKalle Valo iwl_write_prph(trans, 994e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 995e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 996e705c121SKalle Valo 997e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 998e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 999e705c121SKalle Valo &first_ucode_section); 1000e705c121SKalle Valo if (ret) 1001e705c121SKalle Valo return ret; 1002e705c121SKalle Valo } 1003e705c121SKalle Valo 10049efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 1005e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1006e705c121SKalle Valo 10072aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10082aabdbdcSEmmanuel Grumbach 1009e705c121SKalle Valo /* release CPU reset */ 1010e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1011e705c121SKalle Valo 1012e705c121SKalle Valo return 0; 1013e705c121SKalle Valo } 1014e705c121SKalle Valo 1015e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1016e705c121SKalle Valo const struct fw_img *image) 1017e705c121SKalle Valo { 1018e705c121SKalle Valo int ret = 0; 1019e705c121SKalle Valo int first_ucode_section; 1020e705c121SKalle Valo 1021e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1022e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1023e705c121SKalle Valo 10247a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1025e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1026e705c121SKalle Valo 102782ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 102882ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 102982ea7966SSara Sharon 103082ea7966SSara Sharon /* 103182ea7966SSara Sharon * Set default value. On resume reading the values that were 103282ea7966SSara Sharon * zeored can provide debug data on the resume flow. 103382ea7966SSara Sharon * This is for debugging only and has no functional impact. 103482ea7966SSara Sharon */ 103582ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 103682ea7966SSara Sharon 1037e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1038e705c121SKalle Valo /* release CPU reset */ 1039e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1040e705c121SKalle Valo 1041e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1042e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1043e705c121SKalle Valo &first_ucode_section); 1044e705c121SKalle Valo if (ret) 1045e705c121SKalle Valo return ret; 1046e705c121SKalle Valo 1047e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1048e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1049e705c121SKalle Valo &first_ucode_section); 1050e705c121SKalle Valo } 1051e705c121SKalle Valo 10529ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1053727c02dfSSara Sharon { 1054326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1055727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1056326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1057326477e4SJohannes Berg bool report; 1058727c02dfSSara Sharon 1059326477e4SJohannes Berg if (hw_rfkill) { 1060326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1061326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1062326477e4SJohannes Berg } else { 1063326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1064326477e4SJohannes Berg if (trans_pcie->opmode_down) 1065326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1066326477e4SJohannes Berg } 1067727c02dfSSara Sharon 1068326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1069326477e4SJohannes Berg 1070326477e4SJohannes Berg if (prev != report) 1071326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1072727c02dfSSara Sharon 1073727c02dfSSara Sharon return hw_rfkill; 1074727c02dfSSara Sharon } 1075727c02dfSSara Sharon 10767ca00409SHaim Dreyfuss struct iwl_causes_list { 10777ca00409SHaim Dreyfuss u32 cause_num; 10787ca00409SHaim Dreyfuss u32 mask_reg; 10797ca00409SHaim Dreyfuss u8 addr; 10807ca00409SHaim Dreyfuss }; 10817ca00409SHaim Dreyfuss 1082571836a0SMike Golant static const struct iwl_causes_list causes_list_common[] = { 10837ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10847ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10857ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10867ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10877ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10887ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1089906d4eb8SJohannes Berg {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10907ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10917ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 10927ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 10937ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 10947ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 10957ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 10967ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 10977ca00409SHaim Dreyfuss }; 10987ca00409SHaim Dreyfuss 1099571836a0SMike Golant static const struct iwl_causes_list causes_list_pre_bz[] = { 1100571836a0SMike Golant {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1101571836a0SMike Golant }; 11027ca00409SHaim Dreyfuss 1103571836a0SMike Golant static const struct iwl_causes_list causes_list_bz[] = { 1104571836a0SMike Golant {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1105571836a0SMike Golant }; 1106571836a0SMike Golant 1107571836a0SMike Golant static void iwl_pcie_map_list(struct iwl_trans *trans, 1108571836a0SMike Golant const struct iwl_causes_list *causes, 1109571836a0SMike Golant int arr_size, int val) 1110571836a0SMike Golant { 1111571836a0SMike Golant int i; 1112571836a0SMike Golant 11139b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11149b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11159b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11169b58419eSGolan Ben Ami causes[i].cause_num); 11177ca00409SHaim Dreyfuss } 11187ca00409SHaim Dreyfuss } 11197ca00409SHaim Dreyfuss 1120571836a0SMike Golant static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1121571836a0SMike Golant { 1122571836a0SMike Golant struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1123571836a0SMike Golant int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1124571836a0SMike Golant /* 1125571836a0SMike Golant * Access all non RX causes and map them to the default irq. 1126571836a0SMike Golant * In case we are missing at least one interrupt vector, 1127571836a0SMike Golant * the first interrupt vector will serve non-RX and FBQ causes. 1128571836a0SMike Golant */ 1129571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_common, 1130571836a0SMike Golant ARRAY_SIZE(causes_list_common), val); 1131571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1132571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_bz, 1133571836a0SMike Golant ARRAY_SIZE(causes_list_bz), val); 1134571836a0SMike Golant else 1135571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_pre_bz, 1136571836a0SMike Golant ARRAY_SIZE(causes_list_pre_bz), val); 1137571836a0SMike Golant } 1138571836a0SMike Golant 11397ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11407ca00409SHaim Dreyfuss { 11417ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11427ca00409SHaim Dreyfuss u32 offset = 11437ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11447ca00409SHaim Dreyfuss u32 val, idx; 11457ca00409SHaim Dreyfuss 11467ca00409SHaim Dreyfuss /* 11477ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11487ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11497ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11507ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11517ca00409SHaim Dreyfuss */ 11527ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11537ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11547ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11557ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11567ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11577ca00409SHaim Dreyfuss } 11587ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11597ca00409SHaim Dreyfuss 11607ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11617ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11627ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11637ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11647ca00409SHaim Dreyfuss 11657ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11667ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11677ca00409SHaim Dreyfuss } 11687ca00409SHaim Dreyfuss 116977c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11707ca00409SHaim Dreyfuss { 11717ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11727ca00409SHaim Dreyfuss 11737ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1174286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1175d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1176ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11777ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11787ca00409SHaim Dreyfuss return; 11797ca00409SHaim Dreyfuss } 1180d7270d61SHaim Dreyfuss /* 1181d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1182d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1183d7270d61SHaim Dreyfuss * prph. 1184d7270d61SHaim Dreyfuss */ 1185d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1186ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11877ca00409SHaim Dreyfuss 11887ca00409SHaim Dreyfuss /* 11897ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11907ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11917ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11927ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11937ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11947ca00409SHaim Dreyfuss */ 11957ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 11967ca00409SHaim Dreyfuss 11977ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 119883730058SHaim Dreyfuss } 11997ca00409SHaim Dreyfuss 120083730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 120183730058SHaim Dreyfuss { 120283730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 120383730058SHaim Dreyfuss 120483730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 120583730058SHaim Dreyfuss 120683730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 120783730058SHaim Dreyfuss return; 120883730058SHaim Dreyfuss 120983730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12107ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 121183730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12127ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12137ca00409SHaim Dreyfuss } 12147ca00409SHaim Dreyfuss 1215bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1216e705c121SKalle Valo { 1217e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1218e705c121SKalle Valo 1219e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1220e705c121SKalle Valo 1221e705c121SKalle Valo if (trans_pcie->is_down) 1222e705c121SKalle Valo return; 1223e705c121SKalle Valo 1224e705c121SKalle Valo trans_pcie->is_down = true; 1225e705c121SKalle Valo 1226e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1227e705c121SKalle Valo iwl_disable_interrupts(trans); 1228e705c121SKalle Valo 1229e705c121SKalle Valo /* device going down, Stop using ICT table */ 1230e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1231e705c121SKalle Valo 1232e705c121SKalle Valo /* 1233e705c121SKalle Valo * If a HW restart happens during firmware loading, 1234e705c121SKalle Valo * then the firmware loading might call this function 1235e705c121SKalle Valo * and later it might be called again due to the 1236e705c121SKalle Valo * restart. So don't process again if the device is 1237e705c121SKalle Valo * already dead. 1238e705c121SKalle Valo */ 1239e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1240a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1241a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1242e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1243e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1244e705c121SKalle Valo 1245e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1246e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1247e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1248e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1249e705c121SKalle Valo udelay(5); 1250e705c121SKalle Valo } 1251e705c121SKalle Valo } 1252e705c121SKalle Valo 1253e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 12541b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 12551b6598c3SRoee Goldfiner iwl_clear_bit(trans, CSR_GP_CNTRL, 12561b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 12571b6598c3SRoee Goldfiner else 1258e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12596dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1260e705c121SKalle Valo 1261e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1262e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1263e705c121SKalle Valo 1264870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1265e705c121SKalle Valo 1266e705c121SKalle Valo /* 1267f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1268f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1269f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1270f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1271f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1272f4a1f04aSGolan Ben Ami */ 1273f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1274f4a1f04aSGolan Ben Ami 1275f4a1f04aSGolan Ben Ami /* 1276e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1277e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1278e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1279e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1280e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1281e705c121SKalle Valo */ 1282e705c121SKalle Valo iwl_disable_interrupts(trans); 1283e705c121SKalle Valo 1284e705c121SKalle Valo /* clear all status bits */ 1285e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1286e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1287e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1288e705c121SKalle Valo 1289e705c121SKalle Valo /* 1290e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1291e705c121SKalle Valo * interrupt 1292e705c121SKalle Valo */ 1293e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1294e705c121SKalle Valo 1295a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1296e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1297e705c121SKalle Valo } 1298e705c121SKalle Valo 1299eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13002e5d4a8fSHaim Dreyfuss { 13012e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13022e5d4a8fSHaim Dreyfuss 13032e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13042e5d4a8fSHaim Dreyfuss int i; 13052e5d4a8fSHaim Dreyfuss 1306496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13072e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13082e5d4a8fSHaim Dreyfuss } else { 13092e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13102e5d4a8fSHaim Dreyfuss } 13112e5d4a8fSHaim Dreyfuss } 13122e5d4a8fSHaim Dreyfuss 1313a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1314a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1315a6bd005fSEmmanuel Grumbach { 1316a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1317a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1318a6bd005fSEmmanuel Grumbach int ret; 1319a6bd005fSEmmanuel Grumbach 1320a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1321a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1322a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1323a6bd005fSEmmanuel Grumbach ret = -EIO; 1324a6bd005fSEmmanuel Grumbach goto out; 1325a6bd005fSEmmanuel Grumbach } 1326a6bd005fSEmmanuel Grumbach 1327a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1328a6bd005fSEmmanuel Grumbach 1329a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1330a6bd005fSEmmanuel Grumbach 1331a6bd005fSEmmanuel Grumbach /* 1332a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1333a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1334a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1335a6bd005fSEmmanuel Grumbach */ 1336a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1337a6bd005fSEmmanuel Grumbach 1338a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13392e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1340a6bd005fSEmmanuel Grumbach 1341a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1342a6bd005fSEmmanuel Grumbach 1343a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13449ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1345a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1346a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1347a6bd005fSEmmanuel Grumbach goto out; 1348a6bd005fSEmmanuel Grumbach } 1349a6bd005fSEmmanuel Grumbach 1350a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1351a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1352a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1353a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 135420aa99bbSAnton Protopopov ret = -EIO; 1355a6bd005fSEmmanuel Grumbach goto out; 1356a6bd005fSEmmanuel Grumbach } 1357a6bd005fSEmmanuel Grumbach 1358a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1359a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1360a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1361a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1362a6bd005fSEmmanuel Grumbach 1363a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1364a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1365a6bd005fSEmmanuel Grumbach 1366a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1367a6bd005fSEmmanuel Grumbach if (ret) { 1368a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1369a6bd005fSEmmanuel Grumbach goto out; 1370a6bd005fSEmmanuel Grumbach } 1371a6bd005fSEmmanuel Grumbach 1372a6bd005fSEmmanuel Grumbach /* 1373a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1374a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1375a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1376a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1377a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1378a6bd005fSEmmanuel Grumbach */ 1379a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1382a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1383a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1384a6bd005fSEmmanuel Grumbach 1385a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1386286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1387a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1388a6bd005fSEmmanuel Grumbach else 1389a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1390a6bd005fSEmmanuel Grumbach 1391a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13929ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1393a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1394a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1395a6bd005fSEmmanuel Grumbach 1396a6bd005fSEmmanuel Grumbach out: 1397a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1398a6bd005fSEmmanuel Grumbach return ret; 1399a6bd005fSEmmanuel Grumbach } 1400a6bd005fSEmmanuel Grumbach 1401a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1402a6bd005fSEmmanuel Grumbach { 1403a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1404a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1405a6bd005fSEmmanuel Grumbach } 1406a6bd005fSEmmanuel Grumbach 1407326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1408326477e4SJohannes Berg bool was_in_rfkill) 1409326477e4SJohannes Berg { 1410326477e4SJohannes Berg bool hw_rfkill; 1411326477e4SJohannes Berg 1412326477e4SJohannes Berg /* 1413326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1414326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1415326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1416326477e4SJohannes Berg * op_mode. 1417326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1418326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1419326477e4SJohannes Berg * notification without endless recursion. Under very rare 1420326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1421326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1422326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1423326477e4SJohannes Berg */ 1424326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1425326477e4SJohannes Berg if (hw_rfkill) { 1426326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1427326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1428326477e4SJohannes Berg } else { 1429326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1430326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1431326477e4SJohannes Berg } 1432326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1433326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1434326477e4SJohannes Berg } 1435326477e4SJohannes Berg 1436bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1437e705c121SKalle Valo { 1438e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1439326477e4SJohannes Berg bool was_in_rfkill; 1440e705c121SKalle Valo 1441d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1442d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1443d0129315SMordechay Goodstein NULL); 1444d0129315SMordechay Goodstein 1445e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1446326477e4SJohannes Berg trans_pcie->opmode_down = true; 1447326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1448bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1449326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1450e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1451e705c121SKalle Valo } 1452e705c121SKalle Valo 1453e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1454e705c121SKalle Valo { 1455e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1456e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1457e705c121SKalle Valo 1458e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1459e705c121SKalle Valo 1460326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1461326477e4SJohannes Berg state ? "disabled" : "enabled"); 146277c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1463286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1464bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 146577c09bc8SSara Sharon else 1466bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1467e705c121SKalle Valo } 146877c09bc8SSara Sharon } 1469e705c121SKalle Valo 1470e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1471e5f3f215SHaim Dreyfuss bool test, bool reset) 1472e705c121SKalle Valo { 1473e705c121SKalle Valo iwl_disable_interrupts(trans); 1474e705c121SKalle Valo 1475e705c121SKalle Valo /* 1476e705c121SKalle Valo * in testing mode, the host stays awake and the 1477e705c121SKalle Valo * hardware won't be reset (not even partially) 1478e705c121SKalle Valo */ 1479e705c121SKalle Valo if (test) 1480e705c121SKalle Valo return; 1481e705c121SKalle Valo 1482e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1483e705c121SKalle Valo 14842e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1485e705c121SKalle Valo 1486e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14876dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14886dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1489e705c121SKalle Valo 149023ae6128SMatti Gottlieb if (reset) { 1491e705c121SKalle Valo /* 1492e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1493e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1494e705c121SKalle Valo * to execute some invalid memory upon resume 1495e705c121SKalle Valo */ 1496e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1497e705c121SKalle Valo } 1498e705c121SKalle Valo 1499e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1500e705c121SKalle Valo } 1501e705c121SKalle Valo 1502*af08571dSHaim Dreyfuss static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1503*af08571dSHaim Dreyfuss { 1504*af08571dSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1505*af08571dSHaim Dreyfuss int ret; 1506*af08571dSHaim Dreyfuss 1507*af08571dSHaim Dreyfuss if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 1508*af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1509*af08571dSHaim Dreyfuss suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1510*af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1511*af08571dSHaim Dreyfuss } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1512*af08571dSHaim Dreyfuss iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1513*af08571dSHaim Dreyfuss suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1514*af08571dSHaim Dreyfuss CSR_IPC_SLEEP_CONTROL_RESUME); 1515*af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1516*af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SLEEP_CTRL); 1517*af08571dSHaim Dreyfuss } else { 1518*af08571dSHaim Dreyfuss return 0; 1519*af08571dSHaim Dreyfuss } 1520*af08571dSHaim Dreyfuss 1521*af08571dSHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1522*af08571dSHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1523*af08571dSHaim Dreyfuss 1524*af08571dSHaim Dreyfuss /* Invalidate it toward next suspend or resume */ 1525*af08571dSHaim Dreyfuss trans_pcie->sx_complete = false; 1526*af08571dSHaim Dreyfuss 1527*af08571dSHaim Dreyfuss if (!ret) { 1528*af08571dSHaim Dreyfuss IWL_ERR(trans, "Timeout %s D3\n", 1529*af08571dSHaim Dreyfuss suspend ? "entering" : "exiting"); 1530*af08571dSHaim Dreyfuss return -ETIMEDOUT; 1531*af08571dSHaim Dreyfuss } 1532*af08571dSHaim Dreyfuss 1533*af08571dSHaim Dreyfuss return 0; 1534*af08571dSHaim Dreyfuss } 1535*af08571dSHaim Dreyfuss 1536e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1537e5f3f215SHaim Dreyfuss bool reset) 1538e5f3f215SHaim Dreyfuss { 1539e5f3f215SHaim Dreyfuss int ret; 1540e5f3f215SHaim Dreyfuss 1541771db3a1SHaim Dreyfuss if (!reset) 1542e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1543e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1544e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1545e5f3f215SHaim Dreyfuss 1546*af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, true); 1547*af08571dSHaim Dreyfuss if (ret) 1548*af08571dSHaim Dreyfuss return ret; 1549e5f3f215SHaim Dreyfuss 1550e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1551e5f3f215SHaim Dreyfuss 1552e5f3f215SHaim Dreyfuss return 0; 1553e5f3f215SHaim Dreyfuss } 1554e5f3f215SHaim Dreyfuss 1555e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1556e705c121SKalle Valo enum iwl_d3_status *status, 155723ae6128SMatti Gottlieb bool test, bool reset) 1558e705c121SKalle Valo { 1559d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1560e705c121SKalle Valo u32 val; 1561e705c121SKalle Valo int ret; 1562e705c121SKalle Valo 1563e705c121SKalle Valo if (test) { 1564e705c121SKalle Valo iwl_enable_interrupts(trans); 1565e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1566*af08571dSHaim Dreyfuss ret = 0; 1567e5f3f215SHaim Dreyfuss goto out; 1568e705c121SKalle Valo } 1569e705c121SKalle Valo 1570a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15716dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1572e705c121SKalle Valo 1573425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 1574c96b5eecSJohannes Berg if (ret) 1575e705c121SKalle Valo return ret; 1576e705c121SKalle Valo 1577f98ad635SEmmanuel Grumbach /* 1578f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1579f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1580f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1581f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1582f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1583f98ad635SEmmanuel Grumbach */ 1584f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1585f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1586f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1587f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1588f98ad635SEmmanuel Grumbach 1589e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1590e705c121SKalle Valo 159123ae6128SMatti Gottlieb if (!reset) { 1592e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15936dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1594e705c121SKalle Valo } else { 1595e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1596e705c121SKalle Valo 1597e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1598e705c121SKalle Valo if (ret) { 1599e705c121SKalle Valo IWL_ERR(trans, 1600e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1601e705c121SKalle Valo return ret; 1602e705c121SKalle Valo } 1603e705c121SKalle Valo } 1604e705c121SKalle Valo 160582ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1606ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 160782ea7966SSara Sharon 1608e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1609e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1610e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1611e705c121SKalle Valo else 1612e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1613e705c121SKalle Valo 1614e5f3f215SHaim Dreyfuss out: 1615*af08571dSHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE) 1616*af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, false); 1617e5f3f215SHaim Dreyfuss 1618*af08571dSHaim Dreyfuss return ret; 1619e705c121SKalle Valo } 1620e705c121SKalle Valo 16210c18714aSLuca Coelho static void 16220c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16230c18714aSLuca Coelho struct iwl_trans *trans, 16240c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16252e5d4a8fSHaim Dreyfuss { 16262e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1627ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16282e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16290cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 16302e5d4a8fSHaim Dreyfuss 16310c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 163206f4b081SSara Sharon goto enable_msi; 163306f4b081SSara Sharon 16340cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 16350cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 16360cd38f4dSMordechay Goodstein 16370cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 163806f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16392e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16402e5d4a8fSHaim Dreyfuss 164106f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16422e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 164306f4b081SSara Sharon max_irqs); 164406f4b081SSara Sharon if (num_irqs < 0) { 1645496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164606f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 164706f4b081SSara Sharon num_irqs); 164806f4b081SSara Sharon goto enable_msi; 1649496d83caSHaim Dreyfuss } 165006f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1651496d83caSHaim Dreyfuss 16522e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 165306f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 165406f4b081SSara Sharon num_irqs); 165506f4b081SSara Sharon 1656496d83caSHaim Dreyfuss /* 165706f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 165806f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1659496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1660496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1661496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1662496d83caSHaim Dreyfuss */ 1663ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 166406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1665496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1666496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1667ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 166806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1669496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1670496d83caSHaim Dreyfuss } else { 167106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1672496d83caSHaim Dreyfuss } 16739d401222SMordechay Goodstein 16749d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16759d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16769d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16779d401222SMordechay Goodstein 1678ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16792e5d4a8fSHaim Dreyfuss 168006f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1681496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16822e5d4a8fSHaim Dreyfuss return; 16832e5d4a8fSHaim Dreyfuss 168406f4b081SSara Sharon enable_msi: 168506f4b081SSara Sharon ret = pci_enable_msi(pdev); 168606f4b081SSara Sharon if (ret) { 168706f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16882e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16892e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16902e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16912e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16922e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16932e5d4a8fSHaim Dreyfuss } 16942e5d4a8fSHaim Dreyfuss } 16952e5d4a8fSHaim Dreyfuss } 16962e5d4a8fSHaim Dreyfuss 16977c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16987c8d91ebSHaim Dreyfuss { 16997c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 17007c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17017c8d91ebSHaim Dreyfuss 17027c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 17037c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 17047c8d91ebSHaim Dreyfuss offset = 1 + i; 17057c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 17067c8d91ebSHaim Dreyfuss /* 17077c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 17087c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17097c8d91ebSHaim Dreyfuss */ 17107c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17117c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17127c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17137c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17147c8d91ebSHaim Dreyfuss if (ret) 17157c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17167c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 171757e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 17187c8d91ebSHaim Dreyfuss } 17197c8d91ebSHaim Dreyfuss } 17207c8d91ebSHaim Dreyfuss 17212e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17222e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17232e5d4a8fSHaim Dreyfuss { 1724496d83caSHaim Dreyfuss int i; 17252e5d4a8fSHaim Dreyfuss 1726496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17272e5d4a8fSHaim Dreyfuss int ret; 17285a41a86cSSharon Dvir struct msix_entry *msix_entry; 172964fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 173064fa3affSSharon Dvir 173164fa3affSSharon Dvir if (!qname) 173264fa3affSSharon Dvir return -ENOMEM; 17332e5d4a8fSHaim Dreyfuss 17345a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17355a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17365a41a86cSSharon Dvir msix_entry->vector, 17372e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1738496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17392e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17402e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17412e5d4a8fSHaim Dreyfuss IRQF_SHARED, 174264fa3affSSharon Dvir qname, 17435a41a86cSSharon Dvir msix_entry); 17442e5d4a8fSHaim Dreyfuss if (ret) { 17452e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17462e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17475a41a86cSSharon Dvir 17482e5d4a8fSHaim Dreyfuss return ret; 17492e5d4a8fSHaim Dreyfuss } 17502e5d4a8fSHaim Dreyfuss } 17517c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17522e5d4a8fSHaim Dreyfuss 17532e5d4a8fSHaim Dreyfuss return 0; 17542e5d4a8fSHaim Dreyfuss } 17552e5d4a8fSHaim Dreyfuss 175644f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 175744f61b5cSShahar S Matityahu { 175844f61b5cSShahar S Matityahu u32 hpm, wprot; 175944f61b5cSShahar S Matityahu 1760286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 176144f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 176244f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 176344f61b5cSShahar S Matityahu break; 176444f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 176544f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 176644f61b5cSShahar S Matityahu break; 176744f61b5cSShahar S Matityahu default: 176844f61b5cSShahar S Matityahu return 0; 176944f61b5cSShahar S Matityahu } 177044f61b5cSShahar S Matityahu 177144f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 177244f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 177344f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 177444f61b5cSShahar S Matityahu 177544f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 177644f61b5cSShahar S Matityahu IWL_ERR(trans, 177744f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 177844f61b5cSShahar S Matityahu return -EPERM; 177944f61b5cSShahar S Matityahu } 178044f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 178144f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 178244f61b5cSShahar S Matityahu } 178344f61b5cSShahar S Matityahu 178444f61b5cSShahar S Matityahu return 0; 178544f61b5cSShahar S Matityahu } 178644f61b5cSShahar S Matityahu 17870df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17880df36b90SLuca Coelho { 17890df36b90SLuca Coelho int ret; 17900df36b90SLuca Coelho 1791425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 17920df36b90SLuca Coelho if (ret < 0) 17930df36b90SLuca Coelho return ret; 17940df36b90SLuca Coelho 17950df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17960df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17970df36b90SLuca Coelho udelay(20); 17980df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17990df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 18000df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 18010df36b90SLuca Coelho udelay(20); 18020df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 18030df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18040df36b90SLuca Coelho 18050df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 18060df36b90SLuca Coelho 18070df36b90SLuca Coelho return 0; 18080df36b90SLuca Coelho } 18090df36b90SLuca Coelho 1810bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1811e705c121SKalle Valo { 1812e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1813e705c121SKalle Valo int err; 1814e705c121SKalle Valo 1815e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1816e705c121SKalle Valo 1817e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1818e705c121SKalle Valo if (err) { 1819e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1820e705c121SKalle Valo return err; 1821e705c121SKalle Valo } 1822e705c121SKalle Valo 182344f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 182444f61b5cSShahar S Matityahu if (err) 182544f61b5cSShahar S Matityahu return err; 18268954e1ebSShahar S Matityahu 1827870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1828e705c121SKalle Valo 18290df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18307897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18310df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18320df36b90SLuca Coelho if (err) 18330df36b90SLuca Coelho return err; 18340df36b90SLuca Coelho } 18350df36b90SLuca Coelho 183652b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 183752b6e168SEmmanuel Grumbach if (err) 183852b6e168SEmmanuel Grumbach return err; 1839e705c121SKalle Valo 18402e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 184183730058SHaim Dreyfuss 1842e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1843e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1844e705c121SKalle Valo 1845326477e4SJohannes Berg trans_pcie->opmode_down = false; 1846326477e4SJohannes Berg 1847e705c121SKalle Valo /* Set is_down to false here so that...*/ 1848e705c121SKalle Valo trans_pcie->is_down = false; 1849e705c121SKalle Valo 1850e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18519ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1852e705c121SKalle Valo 1853e705c121SKalle Valo return 0; 1854e705c121SKalle Valo } 1855e705c121SKalle Valo 1856bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1857e705c121SKalle Valo { 1858e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1859e705c121SKalle Valo int ret; 1860e705c121SKalle Valo 1861e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1862bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1863e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1864e705c121SKalle Valo 1865e705c121SKalle Valo return ret; 1866e705c121SKalle Valo } 1867e705c121SKalle Valo 1868e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1869e705c121SKalle Valo { 1870e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1871e705c121SKalle Valo 1872e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1873e705c121SKalle Valo 1874e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1875e705c121SKalle Valo iwl_disable_interrupts(trans); 1876e705c121SKalle Valo 1877e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1878e705c121SKalle Valo 1879e705c121SKalle Valo iwl_disable_interrupts(trans); 1880e705c121SKalle Valo 1881e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1882e705c121SKalle Valo 1883e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1884e705c121SKalle Valo 18852e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 1888e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1889e705c121SKalle Valo { 1890e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1891e705c121SKalle Valo } 1892e705c121SKalle Valo 1893e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1894e705c121SKalle Valo { 1895e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1896e705c121SKalle Valo } 1897e705c121SKalle Valo 1898e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1899e705c121SKalle Valo { 1900e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1901e705c121SKalle Valo } 1902e705c121SKalle Valo 190384fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 190484fb372cSSara Sharon { 19053681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 190684fb372cSSara Sharon return 0x00FFFFFF; 190784fb372cSSara Sharon else 190884fb372cSSara Sharon return 0x000FFFFF; 190984fb372cSSara Sharon } 191084fb372cSSara Sharon 1911e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1912e705c121SKalle Valo { 191384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 191484fb372cSSara Sharon 1915e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 191684fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1917e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 1920e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1921e705c121SKalle Valo u32 val) 1922e705c121SKalle Valo { 192384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 192484fb372cSSara Sharon 1925e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 192684fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1927e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1928e705c121SKalle Valo } 1929e705c121SKalle Valo 1930e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1931e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1932e705c121SKalle Valo { 1933e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1934e705c121SKalle Valo 19356ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 19366ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 19376ac57200SJohannes Berg 19384f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 19394f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 19404f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 194122852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 194222852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 194322852fadSMordechay Goodstein 1944e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1945e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1946e705c121SKalle Valo else 1947e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1948e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1949e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1950e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1951e705c121SKalle Valo 19526c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19536c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19546c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 195580084e35SJohannes Berg trans_pcie->rx_buf_bytes = 195680084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1957cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1958cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1959cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1960e705c121SKalle Valo 19618e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1962e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1963e705c121SKalle Valo 196439bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 196539bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 196639bdb17eSSharon Dvir 1967e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1968e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1969e705c121SKalle Valo * As this function may be called again in some corner cases don't 1970e705c121SKalle Valo * do anything if NAPI was already initialized. 1971e705c121SKalle Valo */ 1972bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1973e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1974906d4eb8SJohannes Berg 1975906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1976e705c121SKalle Valo } 1977e705c121SKalle Valo 1978e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1979e705c121SKalle Valo { 1980e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19816eb5e529SEmmanuel Grumbach int i; 1982e705c121SKalle Valo 19832e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1984e705c121SKalle Valo 1985286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 19860cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 198713a3a390SSara Sharon else 1988e705c121SKalle Valo iwl_pcie_tx_free(trans); 1989e705c121SKalle Valo iwl_pcie_rx_free(trans); 1990e705c121SKalle Valo 199110a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 199210a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 199310a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 199410a54d81SLuca Coelho } 199510a54d81SLuca Coelho 19962e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19977c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19987c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19997c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 20007c8d91ebSHaim Dreyfuss NULL); 20017c8d91ebSHaim Dreyfuss } 20022e5d4a8fSHaim Dreyfuss 20032e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 20042e5d4a8fSHaim Dreyfuss } else { 2005e705c121SKalle Valo iwl_pcie_free_ict(trans); 20062e5d4a8fSHaim Dreyfuss } 2007e705c121SKalle Valo 2008e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 2009e705c121SKalle Valo 201069725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 201169725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 201269725928SLuca Coelho trans_pcie->pnvm_dram.block, 201369725928SLuca Coelho trans_pcie->pnvm_dram.physical); 201469725928SLuca Coelho 20159dad325fSLuca Coelho if (trans_pcie->reduce_power_dram.size) 20169dad325fSLuca Coelho dma_free_coherent(trans->dev, 20179dad325fSLuca Coelho trans_pcie->reduce_power_dram.size, 20189dad325fSLuca Coelho trans_pcie->reduce_power_dram.block, 20199dad325fSLuca Coelho trans_pcie->reduce_power_dram.physical); 20209dad325fSLuca Coelho 2021a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2022e705c121SKalle Valo iwl_trans_free(trans); 2023e705c121SKalle Valo } 2024e705c121SKalle Valo 2025e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2026e705c121SKalle Valo { 2027e705c121SKalle Valo if (state) 2028e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2029e705c121SKalle Valo else 2030e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2031e705c121SKalle Valo } 2032e705c121SKalle Valo 203349564a80SLuca Coelho struct iwl_trans_pcie_removal { 203449564a80SLuca Coelho struct pci_dev *pdev; 203549564a80SLuca Coelho struct work_struct work; 203649564a80SLuca Coelho }; 203749564a80SLuca Coelho 203849564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 203949564a80SLuca Coelho { 204049564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 204149564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 204249564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2043aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 204449564a80SLuca Coelho 204549564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 204649564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 204749564a80SLuca Coelho pci_lock_rescan_remove(); 204849564a80SLuca Coelho pci_dev_put(pdev); 204949564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 205049564a80SLuca Coelho pci_unlock_rescan_remove(); 205149564a80SLuca Coelho 205249564a80SLuca Coelho kfree(removal); 205349564a80SLuca Coelho module_put(THIS_MODULE); 205449564a80SLuca Coelho } 205549564a80SLuca Coelho 2056c544d89bSJohannes Berg /* 2057c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2058c544d89bSJohannes Berg * already disabled. 2059c544d89bSJohannes Berg */ 2060c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2061e705c121SKalle Valo { 2062e705c121SKalle Valo int ret; 2063e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20649ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 20659ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 20669ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 20679ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2068e705c121SKalle Valo 2069c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2070e705c121SKalle Valo 2071e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2072e705c121SKalle Valo goto out; 2073e705c121SKalle Valo 20749ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 20759ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 20769ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20779ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20789ce041f5SJohannes Berg } 20799ce041f5SJohannes Berg 2080e705c121SKalle Valo /* this bit wakes up the NIC */ 20819ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2082286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2083e705c121SKalle Valo udelay(2); 2084e705c121SKalle Valo 2085e705c121SKalle Valo /* 2086e705c121SKalle Valo * These bits say the device is running, and should keep running for 2087e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2088e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2089fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2090fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2091e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2092e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2093e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2094e705c121SKalle Valo * to keep device from sleeping. 2095e705c121SKalle Valo * 2096e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2097e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2098fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2099fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2100fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2101e705c121SKalle Valo * 2102e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2103e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2104e705c121SKalle Valo */ 21059ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2106e705c121SKalle Valo if (unlikely(ret < 0)) { 210749564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 210849564a80SLuca Coelho 2109e705c121SKalle Valo WARN_ONCE(1, 2110e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 211149564a80SLuca Coelho cntrl); 211249564a80SLuca Coelho 211349564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 211449564a80SLuca Coelho 211549564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 211649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 211749564a80SLuca Coelho 2118f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 211949564a80SLuca Coelho goto err; 212049564a80SLuca Coelho 212149564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 212249564a80SLuca Coelho 212349564a80SLuca Coelho /* 212449564a80SLuca Coelho * get a module reference to avoid doing this 212549564a80SLuca Coelho * while unloading anyway and to avoid 212649564a80SLuca Coelho * scheduling a work with code that's being 212749564a80SLuca Coelho * removed. 212849564a80SLuca Coelho */ 212949564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 213049564a80SLuca Coelho IWL_ERR(trans, 213149564a80SLuca Coelho "Module is being unloaded - abort\n"); 213249564a80SLuca Coelho goto err; 213349564a80SLuca Coelho } 213449564a80SLuca Coelho 213549564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 213649564a80SLuca Coelho if (!removal) { 213749564a80SLuca Coelho module_put(THIS_MODULE); 213849564a80SLuca Coelho goto err; 213949564a80SLuca Coelho } 214049564a80SLuca Coelho /* 214149564a80SLuca Coelho * we don't need to clear this flag, because 214249564a80SLuca Coelho * the trans will be freed and reallocated. 214349564a80SLuca Coelho */ 2144f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 214549564a80SLuca Coelho 214649564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 214749564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 214849564a80SLuca Coelho pci_dev_get(removal->pdev); 214949564a80SLuca Coelho schedule_work(&removal->work); 215049564a80SLuca Coelho } else { 215149564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 215249564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 215349564a80SLuca Coelho } 215449564a80SLuca Coelho 215549564a80SLuca Coelho err: 2156c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2157e705c121SKalle Valo return false; 2158e705c121SKalle Valo } 2159e705c121SKalle Valo 2160e705c121SKalle Valo out: 2161e705c121SKalle Valo /* 2162e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2163e705c121SKalle Valo * track nic_access anyway. 2164e705c121SKalle Valo */ 2165e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2166e705c121SKalle Valo return true; 2167e705c121SKalle Valo } 2168e705c121SKalle Valo 2169c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2170c544d89bSJohannes Berg { 2171c544d89bSJohannes Berg bool ret; 2172c544d89bSJohannes Berg 2173c544d89bSJohannes Berg local_bh_disable(); 2174c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2175c544d89bSJohannes Berg if (ret) { 2176c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2177c544d89bSJohannes Berg return ret; 2178c544d89bSJohannes Berg } 2179c544d89bSJohannes Berg local_bh_enable(); 2180c544d89bSJohannes Berg return false; 2181c544d89bSJohannes Berg } 2182c544d89bSJohannes Berg 21831ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2184e705c121SKalle Valo { 2185e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2186e705c121SKalle Valo 2187e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2188e705c121SKalle Valo 2189e705c121SKalle Valo /* 2190e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2191e705c121SKalle Valo * track nic_access anyway. 2192e705c121SKalle Valo */ 2193e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2194e705c121SKalle Valo 2195e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2196e705c121SKalle Valo goto out; 21971b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 21981b6598c3SRoee Goldfiner __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21991b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 22001b6598c3SRoee Goldfiner else 2201e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22026dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2203e705c121SKalle Valo /* 2204e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2205e705c121SKalle Valo * any previous writes, but we need the write that clears the 2206e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2207e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2208e705c121SKalle Valo */ 2209e705c121SKalle Valo out: 2210874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2211e705c121SKalle Valo } 2212e705c121SKalle Valo 2213e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2214e705c121SKalle Valo void *buf, int dwords) 2215e705c121SKalle Valo { 221604516706SJohannes Berg int offs = 0; 2217e705c121SKalle Valo u32 *vals = buf; 2218e705c121SKalle Valo 221904516706SJohannes Berg while (offs < dwords) { 222004516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 222167013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 22223d372c4eSJohannes Berg bool resched = false; 222304516706SJohannes Berg 22241ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 222504516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 222604516706SJohannes Berg addr + 4 * offs); 222704516706SJohannes Berg 222804516706SJohannes Berg while (offs < dwords) { 222904516706SJohannes Berg vals[offs] = iwl_read32(trans, 223004516706SJohannes Berg HBUS_TARG_MEM_RDAT); 223104516706SJohannes Berg offs++; 223204516706SJohannes Berg 22333d372c4eSJohannes Berg if (time_after(jiffies, end)) { 22343d372c4eSJohannes Berg resched = true; 223504516706SJohannes Berg break; 223604516706SJohannes Berg } 22373d372c4eSJohannes Berg } 22381ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 22393d372c4eSJohannes Berg 22403d372c4eSJohannes Berg if (resched) 22413d372c4eSJohannes Berg cond_resched(); 2242e705c121SKalle Valo } else { 224304516706SJohannes Berg return -EBUSY; 2244e705c121SKalle Valo } 224504516706SJohannes Berg } 224604516706SJohannes Berg 224704516706SJohannes Berg return 0; 2248e705c121SKalle Valo } 2249e705c121SKalle Valo 2250e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2251e705c121SKalle Valo const void *buf, int dwords) 2252e705c121SKalle Valo { 2253e705c121SKalle Valo int offs, ret = 0; 2254e705c121SKalle Valo const u32 *vals = buf; 2255e705c121SKalle Valo 22561ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2257e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2258e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2259e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2260e705c121SKalle Valo vals ? vals[offs] : 0); 22611ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2262e705c121SKalle Valo } else { 2263e705c121SKalle Valo ret = -EBUSY; 2264e705c121SKalle Valo } 2265e705c121SKalle Valo return ret; 2266e705c121SKalle Valo } 2267e705c121SKalle Valo 22687f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22697f1fe1d4SLuca Coelho u32 *val) 22707f1fe1d4SLuca Coelho { 22717f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 22727f1fe1d4SLuca Coelho ofs, val); 22737f1fe1d4SLuca Coelho } 22747f1fe1d4SLuca Coelho 22750cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22760cd58eaaSEmmanuel Grumbach { 22770cd58eaaSEmmanuel Grumbach int i; 22780cd58eaaSEmmanuel Grumbach 2279286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 22804f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 22810cd58eaaSEmmanuel Grumbach 22824f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 22830cd58eaaSEmmanuel Grumbach continue; 22840cd58eaaSEmmanuel Grumbach 22850cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22860cd58eaaSEmmanuel Grumbach 22870cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22880cd58eaaSEmmanuel Grumbach txq->block--; 22890cd58eaaSEmmanuel Grumbach if (!txq->block) { 22900cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2291bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22920cd58eaaSEmmanuel Grumbach } 22930cd58eaaSEmmanuel Grumbach } else if (block) { 22940cd58eaaSEmmanuel Grumbach txq->block++; 22950cd58eaaSEmmanuel Grumbach } 22960cd58eaaSEmmanuel Grumbach 22970cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22980cd58eaaSEmmanuel Grumbach } 22990cd58eaaSEmmanuel Grumbach } 23000cd58eaaSEmmanuel Grumbach 2301e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2302e705c121SKalle Valo 230392536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 230492536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 230592536c96SSara Sharon { 230692536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 230792536c96SSara Sharon 230892536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 230992536c96SSara Sharon return -EINVAL; 231092536c96SSara Sharon 231192536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 231292536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 231392536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 231492536c96SSara Sharon data->fr_bd_wid = 0; 231592536c96SSara Sharon 231692536c96SSara Sharon return 0; 231792536c96SSara Sharon } 231892536c96SSara Sharon 2319d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2320e705c121SKalle Valo { 2321e705c121SKalle Valo struct iwl_txq *txq; 2322e705c121SKalle Valo unsigned long now = jiffies; 23232ae48edcSSara Sharon bool overflow_tx; 2324e705c121SKalle Valo u8 wr_ptr; 2325e705c121SKalle Valo 23262b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2327f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2328f60c9e59SEmmanuel Grumbach return -ENODEV; 23292b3fae66SMatt Chen 23304f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2331d6d517b7SSara Sharon return -EINVAL; 2332e705c121SKalle Valo 2333d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 23344f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 23352ae48edcSSara Sharon 23362ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23372ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23382ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23392ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23402ae48edcSSara Sharon 23416aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2342e705c121SKalle Valo 23432ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23442ae48edcSSara Sharon overflow_tx) && 2345e705c121SKalle Valo !time_after(jiffies, 2346e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23476aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2348e705c121SKalle Valo 23492ae48edcSSara Sharon /* 23502ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23512ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23522ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23532ae48edcSSara Sharon */ 23542ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2355e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2356e705c121SKalle Valo wr_ptr, write_ptr)) 2357e705c121SKalle Valo return -ETIMEDOUT; 23582ae48edcSSara Sharon wr_ptr = write_ptr; 23592ae48edcSSara Sharon 2360192185d6SJohannes Berg usleep_range(1000, 2000); 23612ae48edcSSara Sharon 23622ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23632ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23642ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23652ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2366e705c121SKalle Valo } 2367e705c121SKalle Valo 2368bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2369e705c121SKalle Valo IWL_ERR(trans, 2370d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 23710cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2372d6d517b7SSara Sharon return -ETIMEDOUT; 2373e705c121SKalle Valo } 2374e705c121SKalle Valo 2375d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2376d6d517b7SSara Sharon 2377d6d517b7SSara Sharon return 0; 2378d6d517b7SSara Sharon } 2379d6d517b7SSara Sharon 2380d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2381d6d517b7SSara Sharon { 2382d6d517b7SSara Sharon int cnt; 2383d6d517b7SSara Sharon int ret = 0; 2384d6d517b7SSara Sharon 2385d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 238679b6c8feSLuca Coelho for (cnt = 0; 2387286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 238879b6c8feSLuca Coelho cnt++) { 2389d6d517b7SSara Sharon 23904f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2391d6d517b7SSara Sharon continue; 23924f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2393d6d517b7SSara Sharon continue; 2394d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2395d6d517b7SSara Sharon continue; 2396d6d517b7SSara Sharon 2397d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 239838398efbSSara Sharon if (ret) 2399d6d517b7SSara Sharon break; 2400d6d517b7SSara Sharon } 2401e705c121SKalle Valo 2402e705c121SKalle Valo return ret; 2403e705c121SKalle Valo } 2404e705c121SKalle Valo 2405e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2406e705c121SKalle Valo u32 mask, u32 value) 2407e705c121SKalle Valo { 2408e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2409e705c121SKalle Valo 2410874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2411e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2412874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2413e705c121SKalle Valo } 2414e705c121SKalle Valo 2415e705c121SKalle Valo static const char *get_csr_string(int cmd) 2416e705c121SKalle Valo { 2417e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2418e705c121SKalle Valo switch (cmd) { 2419e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2420e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2421e705c121SKalle Valo IWL_CMD(CSR_INT); 2422e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2423e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2424e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2425e705c121SKalle Valo IWL_CMD(CSR_RESET); 2426e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2427e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2428e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2429e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2430e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2431e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2432e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2433e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2434e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2435e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2436e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2437e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2438e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2439e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2440e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2441e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2442e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2443e705c121SKalle Valo default: 2444e705c121SKalle Valo return "UNKNOWN"; 2445e705c121SKalle Valo } 2446e705c121SKalle Valo #undef IWL_CMD 2447e705c121SKalle Valo } 2448e705c121SKalle Valo 2449e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2450e705c121SKalle Valo { 2451e705c121SKalle Valo int i; 2452e705c121SKalle Valo static const u32 csr_tbl[] = { 2453e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2454e705c121SKalle Valo CSR_INT_COALESCING, 2455e705c121SKalle Valo CSR_INT, 2456e705c121SKalle Valo CSR_INT_MASK, 2457e705c121SKalle Valo CSR_FH_INT_STATUS, 2458e705c121SKalle Valo CSR_GPIO_IN, 2459e705c121SKalle Valo CSR_RESET, 2460e705c121SKalle Valo CSR_GP_CNTRL, 2461e705c121SKalle Valo CSR_HW_REV, 2462e705c121SKalle Valo CSR_EEPROM_REG, 2463e705c121SKalle Valo CSR_EEPROM_GP, 2464e705c121SKalle Valo CSR_OTP_GP_REG, 2465e705c121SKalle Valo CSR_GIO_REG, 2466e705c121SKalle Valo CSR_GP_UCODE_REG, 2467e705c121SKalle Valo CSR_GP_DRIVER_REG, 2468e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2469e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2470e705c121SKalle Valo CSR_LED_REG, 2471e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2472e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2473e705c121SKalle Valo CSR_ANA_PLL_CFG, 2474e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2475e705c121SKalle Valo CSR_HW_REV_WA_REG, 2476e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2477e705c121SKalle Valo }; 2478e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2479e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2480e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2481e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2482e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2483e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2484e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2485e705c121SKalle Valo } 2486e705c121SKalle Valo } 2487e705c121SKalle Valo 2488e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2489e705c121SKalle Valo /* create and remove of files */ 2490e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2491cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2492cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2493e705c121SKalle Valo } while (0) 2494e705c121SKalle Valo 2495e705c121SKalle Valo /* file operation */ 2496e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2497e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2498e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2499e705c121SKalle Valo .open = simple_open, \ 2500e705c121SKalle Valo .llseek = generic_file_llseek, \ 2501e705c121SKalle Valo }; 2502e705c121SKalle Valo 2503e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2504e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2505e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2506e705c121SKalle Valo .open = simple_open, \ 2507e705c121SKalle Valo .llseek = generic_file_llseek, \ 2508e705c121SKalle Valo }; 2509e705c121SKalle Valo 2510e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2511e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2512e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2513e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2514e705c121SKalle Valo .open = simple_open, \ 2515e705c121SKalle Valo .llseek = generic_file_llseek, \ 2516e705c121SKalle Valo }; 2517e705c121SKalle Valo 2518df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2519df67a1beSJohannes Berg struct iwl_trans *trans; 2520df67a1beSJohannes Berg }; 2521df67a1beSJohannes Berg 2522df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2523df67a1beSJohannes Berg loff_t pos; 2524df67a1beSJohannes Berg }; 2525df67a1beSJohannes Berg 2526df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2527e705c121SKalle Valo { 2528df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2529df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2530df67a1beSJohannes Berg 2531df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2532df67a1beSJohannes Berg return NULL; 2533df67a1beSJohannes Berg 2534df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2535df67a1beSJohannes Berg if (!state) 2536df67a1beSJohannes Berg return NULL; 2537df67a1beSJohannes Berg state->pos = *pos; 2538df67a1beSJohannes Berg return state; 2539df67a1beSJohannes Berg } 2540df67a1beSJohannes Berg 2541df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2542df67a1beSJohannes Berg void *v, loff_t *pos) 2543df67a1beSJohannes Berg { 2544df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2545df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2546df67a1beSJohannes Berg 2547df67a1beSJohannes Berg *pos = ++state->pos; 2548df67a1beSJohannes Berg 2549df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2550df67a1beSJohannes Berg return NULL; 2551df67a1beSJohannes Berg 2552df67a1beSJohannes Berg return state; 2553df67a1beSJohannes Berg } 2554df67a1beSJohannes Berg 2555df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2556df67a1beSJohannes Berg { 2557df67a1beSJohannes Berg kfree(v); 2558df67a1beSJohannes Berg } 2559df67a1beSJohannes Berg 2560df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2561df67a1beSJohannes Berg { 2562df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2563df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2564df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 25654f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2566e705c121SKalle Valo 2567df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2568df67a1beSJohannes Berg (unsigned int)state->pos, 25694f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 25704f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2571df67a1beSJohannes Berg if (txq) 2572df67a1beSJohannes Berg seq_printf(seq, 257395a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2574df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 257595a9e44fSJohannes Berg txq->need_update, txq->frozen, 257695a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2577df67a1beSJohannes Berg else 2578df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2579e705c121SKalle Valo 25804f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2581df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2582df67a1beSJohannes Berg seq_puts(seq, "\n"); 2583e705c121SKalle Valo 2584df67a1beSJohannes Berg return 0; 2585df67a1beSJohannes Berg } 2586df67a1beSJohannes Berg 2587df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2588df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2589df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2590df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2591df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2592df67a1beSJohannes Berg }; 2593df67a1beSJohannes Berg 2594df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2595df67a1beSJohannes Berg { 2596df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2597df67a1beSJohannes Berg 2598df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2599df67a1beSJohannes Berg sizeof(*priv)); 2600df67a1beSJohannes Berg 2601df67a1beSJohannes Berg if (!priv) 2602e705c121SKalle Valo return -ENOMEM; 2603e705c121SKalle Valo 2604df67a1beSJohannes Berg priv->trans = inode->i_private; 2605df67a1beSJohannes Berg return 0; 2606e705c121SKalle Valo } 2607e705c121SKalle Valo 2608e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2609e705c121SKalle Valo char __user *user_buf, 2610e705c121SKalle Valo size_t count, loff_t *ppos) 2611e705c121SKalle Valo { 2612e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2613e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 261478485054SSara Sharon char *buf; 261578485054SSara Sharon int pos = 0, i, ret; 2616eb3dc36eSColin Ian King size_t bufsz; 2617e705c121SKalle Valo 261878485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 261978485054SSara Sharon 262078485054SSara Sharon if (!trans_pcie->rxq) 262178485054SSara Sharon return -EAGAIN; 262278485054SSara Sharon 262378485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 262478485054SSara Sharon if (!buf) 262578485054SSara Sharon return -ENOMEM; 262678485054SSara Sharon 262778485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 262878485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 262978485054SSara Sharon 263078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 263178485054SSara Sharon i); 263278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2633e705c121SKalle Valo rxq->read); 263478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2635e705c121SKalle Valo rxq->write); 263678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2637e705c121SKalle Valo rxq->write_actual); 263878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2639e705c121SKalle Valo rxq->need_update); 264078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2641e705c121SKalle Valo rxq->free_count); 2642e705c121SKalle Valo if (rxq->rb_stts) { 26430307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26440307c839SGolan Ben Ami rxq)); 264578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 264678485054SSara Sharon "\tclosed_rb_num: %u\n", 26470307c839SGolan Ben Ami r & 0x0FFF); 2648e705c121SKalle Valo } else { 2649e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 265078485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2651e705c121SKalle Valo } 265278485054SSara Sharon } 265378485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 265478485054SSara Sharon kfree(buf); 265578485054SSara Sharon 265678485054SSara Sharon return ret; 2657e705c121SKalle Valo } 2658e705c121SKalle Valo 2659e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2660e705c121SKalle Valo char __user *user_buf, 2661e705c121SKalle Valo size_t count, loff_t *ppos) 2662e705c121SKalle Valo { 2663e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2664e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2665e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2666e705c121SKalle Valo 2667e705c121SKalle Valo int pos = 0; 2668e705c121SKalle Valo char *buf; 2669e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2670e705c121SKalle Valo ssize_t ret; 2671e705c121SKalle Valo 2672e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2673e705c121SKalle Valo if (!buf) 2674e705c121SKalle Valo return -ENOMEM; 2675e705c121SKalle Valo 2676e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2677e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2678e705c121SKalle Valo 2679e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2680e705c121SKalle Valo isr_stats->hw); 2681e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2682e705c121SKalle Valo isr_stats->sw); 2683e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2684e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2685e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2686e705c121SKalle Valo isr_stats->err_code); 2687e705c121SKalle Valo } 2688e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2689e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2690e705c121SKalle Valo isr_stats->sch); 2691e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2692e705c121SKalle Valo isr_stats->alive); 2693e705c121SKalle Valo #endif 2694e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2695e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2696e705c121SKalle Valo 2697e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2698e705c121SKalle Valo isr_stats->ctkill); 2699e705c121SKalle Valo 2700e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2701e705c121SKalle Valo isr_stats->wakeup); 2702e705c121SKalle Valo 2703e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2704e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2705e705c121SKalle Valo 2706e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2707e705c121SKalle Valo isr_stats->tx); 2708e705c121SKalle Valo 2709e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2710e705c121SKalle Valo isr_stats->unhandled); 2711e705c121SKalle Valo 2712e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2713e705c121SKalle Valo kfree(buf); 2714e705c121SKalle Valo return ret; 2715e705c121SKalle Valo } 2716e705c121SKalle Valo 2717e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2718e705c121SKalle Valo const char __user *user_buf, 2719e705c121SKalle Valo size_t count, loff_t *ppos) 2720e705c121SKalle Valo { 2721e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2722e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2723e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2724e705c121SKalle Valo u32 reset_flag; 2725078f1131SJohannes Berg int ret; 2726e705c121SKalle Valo 2727078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2728078f1131SJohannes Berg if (ret) 2729078f1131SJohannes Berg return ret; 2730e705c121SKalle Valo if (reset_flag == 0) 2731e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2732e705c121SKalle Valo 2733e705c121SKalle Valo return count; 2734e705c121SKalle Valo } 2735e705c121SKalle Valo 2736e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2737e705c121SKalle Valo const char __user *user_buf, 2738e705c121SKalle Valo size_t count, loff_t *ppos) 2739e705c121SKalle Valo { 2740e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2741e705c121SKalle Valo 2742e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2743e705c121SKalle Valo 2744e705c121SKalle Valo return count; 2745e705c121SKalle Valo } 2746e705c121SKalle Valo 2747e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2748e705c121SKalle Valo char __user *user_buf, 2749e705c121SKalle Valo size_t count, loff_t *ppos) 2750e705c121SKalle Valo { 2751e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2752e705c121SKalle Valo char *buf = NULL; 2753e705c121SKalle Valo ssize_t ret; 2754e705c121SKalle Valo 2755e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2756e705c121SKalle Valo if (ret < 0) 2757e705c121SKalle Valo return ret; 2758e705c121SKalle Valo if (!buf) 2759e705c121SKalle Valo return -EINVAL; 2760e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2761e705c121SKalle Valo kfree(buf); 2762e705c121SKalle Valo return ret; 2763e705c121SKalle Valo } 2764e705c121SKalle Valo 2765fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2766fa4de7f7SJohannes Berg char __user *user_buf, 2767fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2768fa4de7f7SJohannes Berg { 2769fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2770fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2771fa4de7f7SJohannes Berg char buf[100]; 2772fa4de7f7SJohannes Berg int pos; 2773fa4de7f7SJohannes Berg 2774fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2775fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2776fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2777fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2778fa4de7f7SJohannes Berg 2779fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2780fa4de7f7SJohannes Berg } 2781fa4de7f7SJohannes Berg 2782fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2783fa4de7f7SJohannes Berg const char __user *user_buf, 2784fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2785fa4de7f7SJohannes Berg { 2786fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2787fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2788c5bf4fa1SJohannes Berg bool new_value; 2789fa4de7f7SJohannes Berg int ret; 2790fa4de7f7SJohannes Berg 2791c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2792fa4de7f7SJohannes Berg if (ret) 2793fa4de7f7SJohannes Berg return ret; 2794c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2795fa4de7f7SJohannes Berg return count; 2796fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2797c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2798c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2799fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2800fa4de7f7SJohannes Berg 2801fa4de7f7SJohannes Berg return count; 2802fa4de7f7SJohannes Berg } 2803fa4de7f7SJohannes Berg 2804f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2805f7805b33SLior Cohen struct file *file) 2806f7805b33SLior Cohen { 2807f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2808f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2809f7805b33SLior Cohen 281091c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 281191c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2812f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2813f7805b33SLior Cohen return -ENOENT; 2814f7805b33SLior Cohen } 2815f7805b33SLior Cohen 2816f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2817f7805b33SLior Cohen return -EBUSY; 2818f7805b33SLior Cohen 2819f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2820f7805b33SLior Cohen return simple_open(inode, file); 2821f7805b33SLior Cohen } 2822f7805b33SLior Cohen 2823f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2824f7805b33SLior Cohen struct file *file) 2825f7805b33SLior Cohen { 2826f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2827f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2828f7805b33SLior Cohen 2829f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2830f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2831f7805b33SLior Cohen return 0; 2832f7805b33SLior Cohen } 2833f7805b33SLior Cohen 2834f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2835f7805b33SLior Cohen void *buf, ssize_t *size, 2836f7805b33SLior Cohen ssize_t *bytes_copied) 2837f7805b33SLior Cohen { 2838f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2839f7805b33SLior Cohen 2840f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2841f7805b33SLior Cohen if (*size > buf_size_left) 2842f7805b33SLior Cohen *size = buf_size_left; 2843f7805b33SLior Cohen 2844f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2845f7805b33SLior Cohen *bytes_copied += *size; 2846f7805b33SLior Cohen 2847f7805b33SLior Cohen if (buf_size_left == *size) 2848f7805b33SLior Cohen return true; 2849f7805b33SLior Cohen return false; 2850f7805b33SLior Cohen } 2851f7805b33SLior Cohen 2852f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2853f7805b33SLior Cohen char __user *user_buf, 2854f7805b33SLior Cohen size_t count, loff_t *ppos) 2855f7805b33SLior Cohen { 2856f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2857f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 285869f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2859f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2860f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2861f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2862f7805b33SLior Cohen bool b_full; 2863f7805b33SLior Cohen 286491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2865f7805b33SLior Cohen write_ptr_addr = 286691c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 286791c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2868f7805b33SLior Cohen } else { 2869f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2870f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2871f7805b33SLior Cohen } 2872f7805b33SLior Cohen 287391c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2874f7805b33SLior Cohen return 0; 2875f7805b33SLior Cohen 2876f7805b33SLior Cohen mutex_lock(&data->mutex); 2877f7805b33SLior Cohen if (data->state == 2878f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2879f7805b33SLior Cohen mutex_unlock(&data->mutex); 2880f7805b33SLior Cohen return 0; 2881f7805b33SLior Cohen } 2882f7805b33SLior Cohen 2883f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2884f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2885f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2886f7805b33SLior Cohen 2887f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2888f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2889f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2890f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2891f7805b33SLior Cohen curr_buf, &size, 2892f7805b33SLior Cohen &bytes_copied); 2893f7805b33SLior Cohen data->prev_wr_ptr += size; 2894f7805b33SLior Cohen 2895f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2896f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 289769f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2898f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2899f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2900f7805b33SLior Cohen curr_buf, &size, 2901f7805b33SLior Cohen &bytes_copied); 2902f7805b33SLior Cohen data->prev_wr_ptr += size; 2903f7805b33SLior Cohen 2904f7805b33SLior Cohen if (!b_full) { 2905f7805b33SLior Cohen size = write_ptr; 2906f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2907f7805b33SLior Cohen cpu_addr, &size, 2908f7805b33SLior Cohen &bytes_copied); 2909f7805b33SLior Cohen data->prev_wr_ptr = size; 2910f7805b33SLior Cohen data->prev_wrap_cnt++; 2911f7805b33SLior Cohen } 2912f7805b33SLior Cohen } else { 2913f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2914f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2915f7805b33SLior Cohen IWL_WARN(trans, 2916f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2917f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2918f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2919f7805b33SLior Cohen IWL_WARN(trans, 2920f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2921f7805b33SLior Cohen 2922f7805b33SLior Cohen size = write_ptr; 2923f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2924f7805b33SLior Cohen cpu_addr, &size, 2925f7805b33SLior Cohen &bytes_copied); 2926f7805b33SLior Cohen data->prev_wr_ptr = size; 2927f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2928f7805b33SLior Cohen } 2929f7805b33SLior Cohen 2930f7805b33SLior Cohen mutex_unlock(&data->mutex); 2931f7805b33SLior Cohen 2932f7805b33SLior Cohen return bytes_copied; 2933f7805b33SLior Cohen } 2934f7805b33SLior Cohen 2935aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 2936aa899e68SJohannes Berg char __user *user_buf, 2937aa899e68SJohannes Berg size_t count, loff_t *ppos) 2938aa899e68SJohannes Berg { 2939aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 2940aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2941aa899e68SJohannes Berg 2942aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 2943aa899e68SJohannes Berg return -ENODEV; 2944aa899e68SJohannes Berg 2945aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 2946aa899e68SJohannes Berg trans_pcie->rf_name, 2947aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 2948aa899e68SJohannes Berg } 2949aa899e68SJohannes Berg 2950e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2951e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2952e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2953e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2954fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2955aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 2956aa899e68SJohannes Berg 2957df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2958df67a1beSJohannes Berg .owner = THIS_MODULE, 2959df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2960df67a1beSJohannes Berg .read = seq_read, 2961df67a1beSJohannes Berg .llseek = seq_lseek, 2962df67a1beSJohannes Berg .release = seq_release_private, 2963df67a1beSJohannes Berg }; 2964e705c121SKalle Valo 2965f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2966f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2967f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2968f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2969f7805b33SLior Cohen }; 2970f7805b33SLior Cohen 2971f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2972cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2973e705c121SKalle Valo { 2974f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2975f8a1edb7SJohannes Berg 29762ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 29772ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 29782ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 29792ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 29802ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 29812ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2982f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2983aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 2984e705c121SKalle Valo } 2985f7805b33SLior Cohen 2986f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2987f7805b33SLior Cohen { 2988f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2989f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2990f7805b33SLior Cohen 2991f7805b33SLior Cohen mutex_lock(&data->mutex); 2992f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2993f7805b33SLior Cohen mutex_unlock(&data->mutex); 2994f7805b33SLior Cohen } 2995e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2996e705c121SKalle Valo 29976983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2998e705c121SKalle Valo { 2999e705c121SKalle Valo u32 cmdlen = 0; 3000e705c121SKalle Valo int i; 3001e705c121SKalle Valo 3002885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 30030179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3004e705c121SKalle Valo 3005e705c121SKalle Valo return cmdlen; 3006e705c121SKalle Valo } 3007e705c121SKalle Valo 3008e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3009e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3010e705c121SKalle Valo int allocated_rb_nums) 3011e705c121SKalle Valo { 3012e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301380084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 301478485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 301578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3016e705c121SKalle Valo u32 i, r, j, rb_len = 0; 3017e705c121SKalle Valo 3018e705c121SKalle Valo spin_lock(&rxq->lock); 3019e705c121SKalle Valo 30200307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3021e705c121SKalle Valo 3022e705c121SKalle Valo for (i = rxq->read, j = 0; 3023e705c121SKalle Valo i != r && j < allocated_rb_nums; 3024e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3025e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3026e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3027e705c121SKalle Valo 302859a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 302959a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 3030e705c121SKalle Valo 3031e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3032e705c121SKalle Valo 3033e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3034e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3035e705c121SKalle Valo rb = (void *)(*data)->data; 3036e705c121SKalle Valo rb->index = cpu_to_le32(i); 3037e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3038e705c121SKalle Valo 3039e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3040e705c121SKalle Valo } 3041e705c121SKalle Valo 3042e705c121SKalle Valo spin_unlock(&rxq->lock); 3043e705c121SKalle Valo 3044e705c121SKalle Valo return rb_len; 3045e705c121SKalle Valo } 3046e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3047e705c121SKalle Valo 3048e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3049e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3050e705c121SKalle Valo { 3051e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3052e705c121SKalle Valo __le32 *val; 3053e705c121SKalle Valo int i; 3054e705c121SKalle Valo 3055e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3056e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3057e705c121SKalle Valo val = (void *)(*data)->data; 3058e705c121SKalle Valo 3059e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3060e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3061e705c121SKalle Valo 3062e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3063e705c121SKalle Valo 3064e705c121SKalle Valo return csr_len; 3065e705c121SKalle Valo } 3066e705c121SKalle Valo 3067e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3068e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3069e705c121SKalle Valo { 3070e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3071e705c121SKalle Valo __le32 *val; 3072e705c121SKalle Valo int i; 3073e705c121SKalle Valo 30741ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3075e705c121SKalle Valo return 0; 3076e705c121SKalle Valo 3077e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3078e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3079e705c121SKalle Valo val = (void *)(*data)->data; 3080e705c121SKalle Valo 3081286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3082723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3083723b45e2SLiad Kaufman i += sizeof(u32)) 3084e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3085723b45e2SLiad Kaufman else 3086ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3087ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3088723b45e2SLiad Kaufman i += sizeof(u32)) 3089723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3090723b45e2SLiad Kaufman i)); 3091e705c121SKalle Valo 30921ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3093e705c121SKalle Valo 3094e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3095e705c121SKalle Valo 3096e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3097e705c121SKalle Valo } 3098e705c121SKalle Valo 3099e705c121SKalle Valo static u32 3100e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3101e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3102e705c121SKalle Valo u32 monitor_len) 3103e705c121SKalle Valo { 3104e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3105e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3106e705c121SKalle Valo u32 i; 3107e705c121SKalle Valo 31081ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3109e705c121SKalle Valo return 0; 3110e705c121SKalle Valo 3111ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3112e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3113ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 311414ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3115ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3116e705c121SKalle Valo 31171ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3118e705c121SKalle Valo 3119e705c121SKalle Valo return monitor_len; 3120e705c121SKalle Valo } 3121e705c121SKalle Valo 31227a14c23dSSara Sharon static void 31237a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31247a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31257a14c23dSSara Sharon { 3126c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 31277a14c23dSSara Sharon 3128286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3129c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3130c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3131c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3132c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 313391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 313491c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 313591c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 313691c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 31377a14c23dSSara Sharon } else { 31387a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 31397a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31407a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31417a14c23dSSara Sharon } 3142c88580e1SShahar S Matityahu 3143c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31447a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31457a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31467a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31477a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3148286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3149c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3150c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3151c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3152cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3153cc598782SRotem Saado write_ptr_val >>= 2; 3154c88580e1SShahar S Matityahu } 3155c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31567a14c23dSSara Sharon } 31577a14c23dSSara Sharon 3158e705c121SKalle Valo static u32 3159e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3160e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3161e705c121SKalle Valo u32 monitor_len) 3162e705c121SKalle Valo { 316369f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3164e705c121SKalle Valo u32 len = 0; 3165e705c121SKalle Valo 316691c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 316769f0e505SShahar S Matityahu (fw_mon->size && 3168286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3169286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3170e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3171e705c121SKalle Valo 3172e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3173e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 31747a14c23dSSara Sharon 31757a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3176e705c121SKalle Valo 3177e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 317869f0e505SShahar S Matityahu if (fw_mon->size) { 317969f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 318069f0e505SShahar S Matityahu monitor_len = fw_mon->size; 318191c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 31827a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3183e705c121SKalle Valo /* 3184e705c121SKalle Valo * Update pointers to reflect actual values after 3185e705c121SKalle Valo * shifting 3186e705c121SKalle Valo */ 318791c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3188fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3189fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 319091c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3191fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3192fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3193fd527eb5SGolan Ben Ami } else { 3194e705c121SKalle Valo base = iwl_read_prph(trans, base) << 319591c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3196fd527eb5SGolan Ben Ami } 3197fd527eb5SGolan Ben Ami 3198e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3199e705c121SKalle Valo monitor_len / sizeof(u32)); 320091c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3201e705c121SKalle Valo monitor_len = 3202e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3203e705c121SKalle Valo fw_mon_data, 3204e705c121SKalle Valo monitor_len); 3205e705c121SKalle Valo } else { 3206e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3207e705c121SKalle Valo monitor_len = 0; 3208e705c121SKalle Valo } 3209e705c121SKalle Valo 3210e705c121SKalle Valo len += monitor_len; 3211e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3212e705c121SKalle Valo } 3213e705c121SKalle Valo 3214e705c121SKalle Valo return len; 3215e705c121SKalle Valo } 3216e705c121SKalle Valo 321793079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3218e705c121SKalle Valo { 321969f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3220da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3221da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 322269f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 322369f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 322491c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3225da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3226e705c121SKalle Valo 322791c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 322891c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3229fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3230fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 323191c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3232fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3233fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3234fd527eb5SGolan Ben Ami 3235fd527eb5SGolan Ben Ami monitor_len = 3236fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 323791c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3238fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3239fd527eb5SGolan Ben Ami } else { 324091c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 324191c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3242e705c121SKalle Valo 3243e705c121SKalle Valo base = iwl_read_prph(trans, base) << 324491c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3245e705c121SKalle Valo end = iwl_read_prph(trans, end) << 324691c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3247e705c121SKalle Valo 3248e705c121SKalle Valo /* Make "end" point to the actual end */ 3249286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3250fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 325191c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 325291c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3253e705c121SKalle Valo monitor_len = end - base; 3254fd527eb5SGolan Ben Ami } 3255da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3256da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3257e705c121SKalle Valo monitor_len; 3258da752717SShahar S Matityahu return monitor_len; 3259e705c121SKalle Valo } 3260da752717SShahar S Matityahu return 0; 3261da752717SShahar S Matityahu } 3262da752717SShahar S Matityahu 3263fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3264fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3265fdb70083SJohannes Berg u32 dump_mask, 3266fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3267fdb70083SJohannes Berg void *sanitize_ctx) 3268da752717SShahar S Matityahu { 3269da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3270da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 32714f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3272da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3273da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3274fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3275da752717SShahar S Matityahu int i, ptr; 3276da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3277286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 327879f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 327979f033f6SSara Sharon 328079f033f6SSara Sharon if (!dump_mask) 328179f033f6SSara Sharon return NULL; 3282da752717SShahar S Matityahu 3283da752717SShahar S Matityahu /* transport dump header */ 3284da752717SShahar S Matityahu len = sizeof(*dump_data); 3285da752717SShahar S Matityahu 3286da752717SShahar S Matityahu /* host commands */ 3287e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3288da752717SShahar S Matityahu len += sizeof(*data) + 32898672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 32908672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3291da752717SShahar S Matityahu 3292da752717SShahar S Matityahu /* FW monitor */ 3293fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3294da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3295e705c121SKalle Valo 3296e705c121SKalle Valo /* CSR registers */ 329779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3298e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3299e705c121SKalle Valo 3300e705c121SKalle Valo /* FH registers */ 330179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3302286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3303723b45e2SLiad Kaufman len += sizeof(*data) + 3304ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3305ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3306723b45e2SLiad Kaufman else 3307723b45e2SLiad Kaufman len += sizeof(*data) + 3308520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3309520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3310520f03eaSShahar S Matityahu } 3311e705c121SKalle Valo 3312e705c121SKalle Valo if (dump_rbs) { 331378485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 331478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3315e705c121SKalle Valo /* RBs */ 33160307c839SGolan Ben Ami num_rbs = 33170307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3318e705c121SKalle Valo & 0x0FFF; 331978485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3320e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3321e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3322e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3323e705c121SKalle Valo } 3324e705c121SKalle Valo 33255538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3326286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3327505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 33285538409bSLiad Kaufman len += sizeof(*data) + 33295538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3330505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 33315538409bSLiad Kaufman 3332e705c121SKalle Valo dump_data = vzalloc(len); 3333e705c121SKalle Valo if (!dump_data) 3334e705c121SKalle Valo return NULL; 3335e705c121SKalle Valo 3336e705c121SKalle Valo len = 0; 3337e705c121SKalle Valo data = (void *)dump_data->data; 3338520f03eaSShahar S Matityahu 3339e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3340885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3341520f03eaSShahar S Matityahu 3342e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3343e705c121SKalle Valo txcmd = (void *)data->data; 3344e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3345bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3346bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33470cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 334808326a97SJohannes Berg u8 tfdidx; 3349e705c121SKalle Valo u32 caplen, cmdlen; 3350e705c121SKalle Valo 335108326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 335208326a97SJohannes Berg tfdidx = idx; 335308326a97SJohannes Berg else 335408326a97SJohannes Berg tfdidx = ptr; 335508326a97SJohannes Berg 3356520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 335708326a97SJohannes Berg (u8 *)cmdq->tfds + 335808326a97SJohannes Berg tfd_size * tfdidx); 3359e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3360e705c121SKalle Valo 3361e705c121SKalle Valo if (cmdlen) { 3362e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3363e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3364e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3365520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3366520f03eaSShahar S Matityahu caplen); 3367fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3368fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3369fdb70083SJohannes Berg txcmd->data, 3370fdb70083SJohannes Berg caplen); 3371e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3372e705c121SKalle Valo } 3373e705c121SKalle Valo 33740cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3375e705c121SKalle Valo } 3376e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3377e705c121SKalle Valo 3378e705c121SKalle Valo data->len = cpu_to_le32(len); 3379e705c121SKalle Valo len += sizeof(*data); 3380e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3381520f03eaSShahar S Matityahu } 3382e705c121SKalle Valo 338379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3384e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 338579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3386e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3387e705c121SKalle Valo if (dump_rbs) 3388e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3389e705c121SKalle Valo 33905538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3391286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 339279b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3393505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 33945538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3395505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 33965538409bSLiad Kaufman 33975538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 33985538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 33995538409bSLiad Kaufman paging = (void *)data->data; 34005538409bSLiad Kaufman paging->index = cpu_to_le32(i); 34015538409bSLiad Kaufman memcpy(paging->data, 3402505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 34035538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 34045538409bSLiad Kaufman 34055538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 34065538409bSLiad Kaufman } 34075538409bSLiad Kaufman } 340879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3409e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3410e705c121SKalle Valo 3411e705c121SKalle Valo dump_data->len = len; 3412e705c121SKalle Valo 3413e705c121SKalle Valo return dump_data; 3414e705c121SKalle Valo } 3415e705c121SKalle Valo 34163161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 34174cbb8e50SLuciano Coelho { 34183161a34dSMordechay Goodstein if (enable) 34193161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 34203161a34dSMordechay Goodstein else 34213161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 34224cbb8e50SLuciano Coelho } 34234cbb8e50SLuciano Coelho 34243161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 34254cbb8e50SLuciano Coelho { 34263161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 34273161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 34283161a34dSMordechay Goodstein 34293161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 34303161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3431571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3432571836a0SMike Golant sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3433571836a0SMike Golant else 34343161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 34353161a34dSMordechay Goodstein } else { 34363161a34dSMordechay Goodstein inta_addr = CSR_INT; 34373161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 34384cbb8e50SLuciano Coelho } 34393161a34dSMordechay Goodstein 34403161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 34413161a34dSMordechay Goodstein } 34424cbb8e50SLuciano Coelho 3443623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3444623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3445623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3446623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3447623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3448623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3449623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3450623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3451623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 34527f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3453623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3454623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3455870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3456623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3457623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3458623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3459623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3460623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3461d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 34623161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 34633161a34dSMordechay Goodstein .sync_nmi = iwl_trans_pcie_sync_nmi \ 3464623e7766SSara Sharon 3465e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3466623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3467e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3468e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3469e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3470e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3471e705c121SKalle Valo 347213f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3473e705c121SKalle Valo 3474e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3475a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3476e705c121SKalle Valo 3477e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3478e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3479e705c121SKalle Valo 348042db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 348142db09c1SLiad Kaufman 3482d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3483d6d517b7SSara Sharon 3484a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 34850cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3486f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3487f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3488f7805b33SLior Cohen #endif 3489623e7766SSara Sharon }; 3490e705c121SKalle Valo 3491623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3492623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3493623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3494eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3495eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 349677c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3497e705c121SKalle Valo 349813f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3499e705c121SKalle Valo 35000cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3501a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3502623e7766SSara Sharon 3503a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3504ba7136f3SAlex Malamud 35050cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 35060cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3507d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 350892536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 35096654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 35109dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3511f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3512f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3513f7805b33SLior Cohen #endif 3514e705c121SKalle Valo }; 3515e705c121SKalle Valo 3516e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3517e705c121SKalle Valo const struct pci_device_id *ent, 35187e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3519e705c121SKalle Valo { 3520e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3521e705c121SKalle Valo struct iwl_trans *trans; 3522fda1bd0dSMordechay Goodstein int ret, addr_size; 3523a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3524f00c3f9eSJohannes Berg void __iomem * const *table; 3525a89c72ffSJohannes Berg 3526fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3527a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3528e705c121SKalle Valo 35295a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 35305a41a86cSSharon Dvir if (ret) 35315a41a86cSSharon Dvir return ERR_PTR(ret); 35325a41a86cSSharon Dvir 3533a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3534fda1bd0dSMordechay Goodstein cfg_trans); 3535e705c121SKalle Valo if (!trans) 3536e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3537e705c121SKalle Valo 3538e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3539e705c121SKalle Valo 3540e705c121SKalle Valo trans_pcie->trans = trans; 3541326477e4SJohannes Berg trans_pcie->opmode_down = true; 3542e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3543e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3544cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3545e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3546e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3547906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 35488188a18eSJohannes Berg 35498188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35508188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35518188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35528188a18eSJohannes Berg ret = -ENOMEM; 35538188a18eSJohannes Berg goto out_free_trans; 35548188a18eSJohannes Berg } 35558188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35568188a18eSJohannes Berg 3557c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3558e705c121SKalle Valo 35597e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3560e705c121SKalle Valo /* 3561e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3562e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3563e705c121SKalle Valo * lot of power. 3564e705c121SKalle Valo */ 3565e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3566e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3567e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3568e705c121SKalle Valo } 3569e705c121SKalle Valo 35709416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 35719416560eSGolan Ben Ami 3572e705c121SKalle Valo pci_set_master(pdev); 3573e705c121SKalle Valo 3574885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3575ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3576e705c121SKalle Valo if (ret) { 3577ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3578e705c121SKalle Valo /* both attempts failed: */ 3579e705c121SKalle Valo if (ret) { 3580e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 35815a41a86cSSharon Dvir goto out_no_pci; 3582e705c121SKalle Valo } 3583e705c121SKalle Valo } 3584e705c121SKalle Valo 35855a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3586e705c121SKalle Valo if (ret) { 35875a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 35885a41a86cSSharon Dvir goto out_no_pci; 3589e705c121SKalle Valo } 3590e705c121SKalle Valo 3591f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3592f00c3f9eSJohannes Berg if (!table) { 35935a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3594f00c3f9eSJohannes Berg ret = -ENOMEM; 3595f00c3f9eSJohannes Berg goto out_no_pci; 3596f00c3f9eSJohannes Berg } 3597f00c3f9eSJohannes Berg 3598f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3599f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3600f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3601e705c121SKalle Valo ret = -ENODEV; 36025a41a86cSSharon Dvir goto out_no_pci; 3603e705c121SKalle Valo } 3604e705c121SKalle Valo 3605e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3606e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3607e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3608e705c121SKalle Valo 3609e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3610e705c121SKalle Valo iwl_disable_interrupts(trans); 3611e705c121SKalle Valo 3612e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 36139a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 36149a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 36159a098a89SRajat Jain ret = -EIO; 36169a098a89SRajat Jain goto out_no_pci; 36179a098a89SRajat Jain } 36189a098a89SRajat Jain 3619e705c121SKalle Valo /* 3620e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3621e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3622e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3623e705c121SKalle Valo * in the old format. 3624e705c121SKalle Valo */ 36254adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 362655c6d8f8SMike Golant trans->hw_rev_step = trans->hw_rev & 0xF; 362755c6d8f8SMike Golant else 362855c6d8f8SMike Golant trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3629e705c121SKalle Valo 363099be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 363199be6166SLuca Coelho 36327e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3633e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3634e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3635e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3636e705c121SKalle Valo 3637e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3638e5f3f215SHaim Dreyfuss 3639c239feecSJohannes Berg 36402e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36412388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36422388bd7bSDan Carpenter if (ret) 36435a41a86cSSharon Dvir goto out_no_pci; 36442e5d4a8fSHaim Dreyfuss } else { 3645e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3646e705c121SKalle Valo if (ret) 36475a41a86cSSharon Dvir goto out_no_pci; 3648e705c121SKalle Valo 36495a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36505a41a86cSSharon Dvir iwl_pcie_isr, 3651e705c121SKalle Valo iwl_pcie_irq_handler, 3652e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3653e705c121SKalle Valo if (ret) { 3654e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3655e705c121SKalle Valo goto out_free_ict; 3656e705c121SKalle Valo } 36572e5d4a8fSHaim Dreyfuss } 3658e705c121SKalle Valo 3659f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3660f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3661f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3662f7805b33SLior Cohen #endif 3663f7805b33SLior Cohen 3664a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3665a9248de4SShahar S Matityahu 3666e705c121SKalle Valo return trans; 3667e705c121SKalle Valo 3668e705c121SKalle Valo out_free_ict: 3669e705c121SKalle Valo iwl_pcie_free_ict(trans); 3670e705c121SKalle Valo out_no_pci: 36718188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 36728188a18eSJohannes Berg out_free_trans: 3673e705c121SKalle Valo iwl_trans_free(trans); 3674e705c121SKalle Valo return ERR_PTR(ret); 3675e705c121SKalle Valo } 3676