1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/pci-aspm.h> 66e705c121SKalle Valo #include <linux/interrupt.h> 67e705c121SKalle Valo #include <linux/debugfs.h> 68e705c121SKalle Valo #include <linux/sched.h> 69e705c121SKalle Valo #include <linux/bitops.h> 70e705c121SKalle Valo #include <linux/gfp.h> 71e705c121SKalle Valo #include <linux/vmalloc.h> 72b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 7349564a80SLuca Coelho #include <linux/module.h> 74f7805b33SLior Cohen #include <linux/wait.h> 75e705c121SKalle Valo 76e705c121SKalle Valo #include "iwl-drv.h" 77e705c121SKalle Valo #include "iwl-trans.h" 78e705c121SKalle Valo #include "iwl-csr.h" 79e705c121SKalle Valo #include "iwl-prph.h" 80e705c121SKalle Valo #include "iwl-scd.h" 81e705c121SKalle Valo #include "iwl-agn-hw.h" 82d962f9b1SJohannes Berg #include "fw/error-dump.h" 83520f03eaSShahar S Matityahu #include "fw/dbg.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 914290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92a6d24fadSRajat Jain { 93a6d24fadSRajat Jain #define PCI_DUMP_SIZE 64 94a6d24fadSRajat Jain #define PREFIX_LEN 32 95a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 97a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 98a6d24fadSRajat Jain char *prefix; 99a6d24fadSRajat Jain 100a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 101a6d24fadSRajat Jain return; 102a6d24fadSRajat Jain 103a6d24fadSRajat Jain /* Should be a multiple of 4 */ 104a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105a6d24fadSRajat Jain /* Alloc a max size buffer */ 106a6d24fadSRajat Jain if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108a6d24fadSRajat Jain else 109a6d24fadSRajat Jain alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 111a6d24fadSRajat Jain if (!buf) 112a6d24fadSRajat Jain return; 113a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 114a6d24fadSRajat Jain 115a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116a6d24fadSRajat Jain 117a6d24fadSRajat Jain /* Print wifi device registers */ 118a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 120a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 122a6d24fadSRajat Jain goto err_read; 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain 125a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 128a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129a6d24fadSRajat Jain 130a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131a6d24fadSRajat Jain if (pos) { 132a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 135a6d24fadSRajat Jain goto err_read; 136a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137a6d24fadSRajat Jain 32, 4, buf, i, 0); 138a6d24fadSRajat Jain } 139a6d24fadSRajat Jain 140a6d24fadSRajat Jain /* Print parent device registers next */ 141a6d24fadSRajat Jain if (!pdev->bus->self) 142a6d24fadSRajat Jain goto out; 143a6d24fadSRajat Jain 144a6d24fadSRajat Jain pdev = pdev->bus->self; 145a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146a6d24fadSRajat Jain 147a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148a6d24fadSRajat Jain pci_name(pdev)); 149a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 151a6d24fadSRajat Jain goto err_read; 152a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153a6d24fadSRajat Jain 154a6d24fadSRajat Jain /* Print root port AER registers */ 155a6d24fadSRajat Jain pos = 0; 156a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 157a6d24fadSRajat Jain if (pdev) 158a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159a6d24fadSRajat Jain if (pos) { 160a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161a6d24fadSRajat Jain pci_name(pdev)); 162a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 165a6d24fadSRajat Jain goto err_read; 166a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167a6d24fadSRajat Jain 4, buf, i, 0); 168a6d24fadSRajat Jain } 169f3402d6dSSara Sharon goto out; 170a6d24fadSRajat Jain 171a6d24fadSRajat Jain err_read: 172a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 174a6d24fadSRajat Jain out: 175a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 176a6d24fadSRajat Jain kfree(buf); 177a6d24fadSRajat Jain } 178a6d24fadSRajat Jain 179870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 180870c2a11SGolan Ben Ami { 181870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 182a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 183a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 184870c2a11SGolan Ben Ami usleep_range(5000, 6000); 185870c2a11SGolan Ben Ami } 186870c2a11SGolan Ben Ami 187e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 188e705c121SKalle Valo { 18988964b2eSSara Sharon int i; 190e705c121SKalle Valo 19188964b2eSSara Sharon for (i = 0; i < trans->num_blocks; i++) { 19288964b2eSSara Sharon dma_free_coherent(trans->dev, trans->fw_mon[i].size, 19388964b2eSSara Sharon trans->fw_mon[i].block, 19488964b2eSSara Sharon trans->fw_mon[i].physical); 19588964b2eSSara Sharon trans->fw_mon[i].block = NULL; 19688964b2eSSara Sharon trans->fw_mon[i].physical = 0; 19788964b2eSSara Sharon trans->fw_mon[i].size = 0; 19888964b2eSSara Sharon trans->num_blocks--; 19988964b2eSSara Sharon } 200e705c121SKalle Valo } 201e705c121SKalle Valo 20288964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20388964b2eSSara Sharon u8 max_power, u8 min_power) 204e705c121SKalle Valo { 205c5f97542SShahar S Matityahu void *cpu_addr = NULL; 20688964b2eSSara Sharon dma_addr_t phys = 0; 207e705c121SKalle Valo u32 size = 0; 208e705c121SKalle Valo u8 power; 209e705c121SKalle Valo 21088964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 211e705c121SKalle Valo size = BIT(power); 212c5f97542SShahar S Matityahu cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 213c5f97542SShahar S Matityahu GFP_KERNEL | __GFP_NOWARN | 214c5f97542SShahar S Matityahu __GFP_ZERO | __GFP_COMP); 215c5f97542SShahar S Matityahu if (!cpu_addr) 216e705c121SKalle Valo continue; 217e705c121SKalle Valo 218e705c121SKalle Valo IWL_INFO(trans, 219c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 220c5f97542SShahar S Matityahu size); 221e705c121SKalle Valo break; 222e705c121SKalle Valo } 223e705c121SKalle Valo 224c5f97542SShahar S Matityahu if (WARN_ON_ONCE(!cpu_addr)) 225e705c121SKalle Valo return; 226e705c121SKalle Valo 227e705c121SKalle Valo if (power != max_power) 228e705c121SKalle Valo IWL_ERR(trans, 229e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 230e705c121SKalle Valo (unsigned long)BIT(power - 10), 231e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 232e705c121SKalle Valo 23388964b2eSSara Sharon trans->fw_mon[trans->num_blocks].block = cpu_addr; 23488964b2eSSara Sharon trans->fw_mon[trans->num_blocks].physical = phys; 23588964b2eSSara Sharon trans->fw_mon[trans->num_blocks].size = size; 23688964b2eSSara Sharon trans->num_blocks++; 23788964b2eSSara Sharon } 23888964b2eSSara Sharon 23988964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24088964b2eSSara Sharon { 24188964b2eSSara Sharon if (!max_power) { 24288964b2eSSara Sharon /* default max_power is maximum */ 24388964b2eSSara Sharon max_power = 26; 24488964b2eSSara Sharon } else { 24588964b2eSSara Sharon max_power += 11; 24688964b2eSSara Sharon } 24788964b2eSSara Sharon 24888964b2eSSara Sharon if (WARN(max_power > 26, 24988964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25088964b2eSSara Sharon max_power)) 25188964b2eSSara Sharon return; 25288964b2eSSara Sharon 25388964b2eSSara Sharon /* 25488964b2eSSara Sharon * This function allocats the default fw monitor. 25588964b2eSSara Sharon * The optional additional ones will be allocated in runtime 25688964b2eSSara Sharon */ 25788964b2eSSara Sharon if (trans->num_blocks) 25888964b2eSSara Sharon return; 25988964b2eSSara Sharon 26088964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 261e705c121SKalle Valo } 262e705c121SKalle Valo 263e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 264e705c121SKalle Valo { 265e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 266e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 267e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 268e705c121SKalle Valo } 269e705c121SKalle Valo 270e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 271e705c121SKalle Valo { 272e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 273e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 275e705c121SKalle Valo } 276e705c121SKalle Valo 277e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 278e705c121SKalle Valo { 279e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 280e705c121SKalle Valo return; 281e705c121SKalle Valo 282e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 283e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 284e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 285e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 286e705c121SKalle Valo else 287e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 288e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 289e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo /* PCI registers */ 293e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 294e705c121SKalle Valo 295eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 296e705c121SKalle Valo { 297e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 298e705c121SKalle Valo u16 lctl; 299e705c121SKalle Valo u16 cap; 300e705c121SKalle Valo 301e705c121SKalle Valo /* 302e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 303e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 304e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 305e705c121SKalle Valo * costs negligible amount of power savings. 306e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 307e705c121SKalle Valo * power savings, even without L1. 308e705c121SKalle Valo */ 309e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 310e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 311e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 312e705c121SKalle Valo else 313e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 314e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 315e705c121SKalle Valo 316e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 317e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 318d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 319e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 320e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 321e705c121SKalle Valo } 322e705c121SKalle Valo 323e705c121SKalle Valo /* 324e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 325e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 326e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 327e705c121SKalle Valo */ 328e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 329e705c121SKalle Valo { 33052b6e168SEmmanuel Grumbach int ret; 33152b6e168SEmmanuel Grumbach 332e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 333e705c121SKalle Valo 334e705c121SKalle Valo /* 335e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 336e705c121SKalle Valo * bits already set by default after reset. 337e705c121SKalle Valo */ 338e705c121SKalle Valo 339e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3406e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 341e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 342e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 343e705c121SKalle Valo 344e705c121SKalle Valo /* 345e705c121SKalle Valo * Disable L0s without affecting L1; 346e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 347e705c121SKalle Valo */ 348e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 349e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 350e705c121SKalle Valo 351e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 352e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 353e705c121SKalle Valo 354e705c121SKalle Valo /* 355e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 356e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 357e705c121SKalle Valo */ 358e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 359e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 360e705c121SKalle Valo 361e705c121SKalle Valo iwl_pcie_apm_config(trans); 362e705c121SKalle Valo 363e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 36477d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 36577d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 366e705c121SKalle Valo 367e705c121SKalle Valo /* 368e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 369e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 370e705c121SKalle Valo */ 371a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 372a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 373e705c121SKalle Valo 374e705c121SKalle Valo /* 375e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 376e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 377e705c121SKalle Valo * and accesses to uCode SRAM. 378e705c121SKalle Valo */ 379e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 380a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 381a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 382a8cbb46fSGolan Ben Ami 25000); 383e705c121SKalle Valo if (ret < 0) { 38452b6e168SEmmanuel Grumbach IWL_ERR(trans, "Failed to init the card\n"); 38552b6e168SEmmanuel Grumbach return ret; 386e705c121SKalle Valo } 387e705c121SKalle Valo 388e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 389e705c121SKalle Valo /* 390e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 391e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 392e705c121SKalle Valo * not related to host_interrupt_operation_mode. 393e705c121SKalle Valo * 394e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 395e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 396e705c121SKalle Valo * that we wake up from L1 on time. 397e705c121SKalle Valo * 398e705c121SKalle Valo * This looks weird: read twice the same register, discard the 399e705c121SKalle Valo * value, set a bit, and yet again, read that same register 400e705c121SKalle Valo * just to discard the value. But that's the way the hardware 401e705c121SKalle Valo * seems to like it. 402e705c121SKalle Valo */ 403e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 404e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 405e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 406e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 407e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 408e705c121SKalle Valo } 409e705c121SKalle Valo 410e705c121SKalle Valo /* 411e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 412e705c121SKalle Valo * 413e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 414e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 415e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 416e705c121SKalle Valo */ 417e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 418e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 419e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 420e705c121SKalle Valo udelay(20); 421e705c121SKalle Valo 422e705c121SKalle Valo /* Disable L1-Active */ 423e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 424e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 425e705c121SKalle Valo 426e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 427e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 428e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 429e705c121SKalle Valo } 430e705c121SKalle Valo 431e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 432e705c121SKalle Valo 43352b6e168SEmmanuel Grumbach return 0; 434e705c121SKalle Valo } 435e705c121SKalle Valo 436e705c121SKalle Valo /* 437e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 438e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 439e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 440e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 441e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 442e705c121SKalle Valo */ 443e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 444e705c121SKalle Valo { 445e705c121SKalle Valo int ret; 446e705c121SKalle Valo u32 apmg_gp1_reg; 447e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 448e705c121SKalle Valo u32 dl_cfg_reg; 449e705c121SKalle Valo 450e705c121SKalle Valo /* Force XTAL ON */ 451e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 452e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 453e705c121SKalle Valo 454870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 455e705c121SKalle Valo 456e705c121SKalle Valo /* 457e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 458e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 459e705c121SKalle Valo */ 460a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 461a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 462e705c121SKalle Valo 463e705c121SKalle Valo /* 464e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 465e705c121SKalle Valo * device-internal resources is possible. 466e705c121SKalle Valo */ 467e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 468a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 469a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 470e705c121SKalle Valo 25000); 471e705c121SKalle Valo if (WARN_ON(ret < 0)) { 472e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 473e705c121SKalle Valo /* Release XTAL ON request */ 474e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 475e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 476e705c121SKalle Valo return; 477e705c121SKalle Valo } 478e705c121SKalle Valo 479e705c121SKalle Valo /* 480e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 481e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 482e705c121SKalle Valo */ 483e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 484e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 485e705c121SKalle Valo 486e705c121SKalle Valo /* 487e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 488e705c121SKalle Valo * caused by APMG idle state. 489e705c121SKalle Valo */ 490e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 491e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 492e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 493e705c121SKalle Valo apmg_xtal_cfg_reg | 494e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 495e705c121SKalle Valo 496870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 497e705c121SKalle Valo 498e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 499e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 500e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 501e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 502e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 503e705c121SKalle Valo 504e705c121SKalle Valo /* Clear delay line clock power up */ 505e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 506e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 507e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 508e705c121SKalle Valo 509e705c121SKalle Valo /* 510e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 511e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 512e705c121SKalle Valo */ 513e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 514e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 515e705c121SKalle Valo 516e705c121SKalle Valo /* 517e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 518e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 519e705c121SKalle Valo */ 520e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 521a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 522e705c121SKalle Valo 523e705c121SKalle Valo /* Activates XTAL resources monitor */ 524e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 525e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 526e705c121SKalle Valo 527e705c121SKalle Valo /* Release XTAL ON request */ 528e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 529e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 530e705c121SKalle Valo udelay(10); 531e705c121SKalle Valo 532e705c121SKalle Valo /* Release APMG XTAL */ 533e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 534e705c121SKalle Valo apmg_xtal_cfg_reg & 535e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 536e705c121SKalle Valo } 537e705c121SKalle Valo 538e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 539e705c121SKalle Valo { 540e8c8935eSJohannes Berg int ret; 541e705c121SKalle Valo 542e705c121SKalle Valo /* stop device's busmaster DMA activity */ 543a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 544a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 545e705c121SKalle Valo 546a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 547a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 548a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 549e705c121SKalle Valo if (ret < 0) 550e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 551e705c121SKalle Valo 552e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 553e705c121SKalle Valo } 554e705c121SKalle Valo 555e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 556e705c121SKalle Valo { 557e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 558e705c121SKalle Valo 559e705c121SKalle Valo if (op_mode_leave) { 560e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 561e705c121SKalle Valo iwl_pcie_apm_init(trans); 562e705c121SKalle Valo 563e705c121SKalle Valo /* inform ME that we are leaving */ 564e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 565e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 566e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5676e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 568e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 569e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 570e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 571e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 572e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 573e705c121SKalle Valo mdelay(1); 574e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 575e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 576e705c121SKalle Valo } 577e705c121SKalle Valo mdelay(5); 578e705c121SKalle Valo } 579e705c121SKalle Valo 580e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 581e705c121SKalle Valo 582e705c121SKalle Valo /* Stop device's DMA activity */ 583e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 584e705c121SKalle Valo 585e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 586e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 587e705c121SKalle Valo return; 588e705c121SKalle Valo } 589e705c121SKalle Valo 590870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 591e705c121SKalle Valo 592e705c121SKalle Valo /* 593e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 594e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 595e705c121SKalle Valo */ 596e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 597a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 598e705c121SKalle Valo } 599e705c121SKalle Valo 600e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 601e705c121SKalle Valo { 602e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 60352b6e168SEmmanuel Grumbach int ret; 604e705c121SKalle Valo 605e705c121SKalle Valo /* nic_init */ 606e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 60752b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 608e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 609e705c121SKalle Valo 61052b6e168SEmmanuel Grumbach if (ret) 61152b6e168SEmmanuel Grumbach return ret; 61252b6e168SEmmanuel Grumbach 613e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 614e705c121SKalle Valo 615e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 616e705c121SKalle Valo 617e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 618e705c121SKalle Valo iwl_pcie_rx_init(trans); 619e705c121SKalle Valo 620e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 621e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 622e705c121SKalle Valo return -ENOMEM; 623e705c121SKalle Valo 624e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 625e705c121SKalle Valo /* enable shadow regs in HW */ 626e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 627e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 628e705c121SKalle Valo } 629e705c121SKalle Valo 630e705c121SKalle Valo return 0; 631e705c121SKalle Valo } 632e705c121SKalle Valo 633e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 634e705c121SKalle Valo 635e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 636e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 637e705c121SKalle Valo { 638e705c121SKalle Valo int ret; 639e705c121SKalle Valo 640e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 641e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 642e705c121SKalle Valo 643e705c121SKalle Valo /* See if we got it */ 644e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 645e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 646e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 647e705c121SKalle Valo HW_READY_TIMEOUT); 648e705c121SKalle Valo 649e705c121SKalle Valo if (ret >= 0) 650e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 651e705c121SKalle Valo 652e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 653e705c121SKalle Valo return ret; 654e705c121SKalle Valo } 655e705c121SKalle Valo 656e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 657eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 658e705c121SKalle Valo { 659e705c121SKalle Valo int ret; 660e705c121SKalle Valo int t = 0; 661e705c121SKalle Valo int iter; 662e705c121SKalle Valo 663e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 664e705c121SKalle Valo 665e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 666e705c121SKalle Valo /* If the card is ready, exit 0 */ 667e705c121SKalle Valo if (ret >= 0) 668e705c121SKalle Valo return 0; 669e705c121SKalle Valo 670e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 671e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 672192185d6SJohannes Berg usleep_range(1000, 2000); 673e705c121SKalle Valo 674e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 675e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 676e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 677e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 678e705c121SKalle Valo 679e705c121SKalle Valo do { 680e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 681e705c121SKalle Valo if (ret >= 0) 682e705c121SKalle Valo return 0; 683e705c121SKalle Valo 684e705c121SKalle Valo usleep_range(200, 1000); 685e705c121SKalle Valo t += 200; 686e705c121SKalle Valo } while (t < 150000); 687e705c121SKalle Valo msleep(25); 688e705c121SKalle Valo } 689e705c121SKalle Valo 690e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 691e705c121SKalle Valo 692e705c121SKalle Valo return ret; 693e705c121SKalle Valo } 694e705c121SKalle Valo 695e705c121SKalle Valo /* 696e705c121SKalle Valo * ucode 697e705c121SKalle Valo */ 698564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 699564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 700564cdce7SSara Sharon u32 byte_cnt) 701e705c121SKalle Valo { 702bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 703e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 704e705c121SKalle Valo 705bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 706e705c121SKalle Valo dst_addr); 707e705c121SKalle Valo 708bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 709e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 710e705c121SKalle Valo 711bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 712e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 713e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 714e705c121SKalle Valo 715bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 716bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 717bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 718e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 719e705c121SKalle Valo 720bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 721e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 722e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 723e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 724564cdce7SSara Sharon } 725e705c121SKalle Valo 726564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 727564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 728564cdce7SSara Sharon u32 byte_cnt) 729564cdce7SSara Sharon { 730564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 731564cdce7SSara Sharon unsigned long flags; 732564cdce7SSara Sharon int ret; 733564cdce7SSara Sharon 734564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 735564cdce7SSara Sharon 736564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 737564cdce7SSara Sharon return -EIO; 738564cdce7SSara Sharon 739564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 740564cdce7SSara Sharon byte_cnt); 741bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 742bac842daSEmmanuel Grumbach 743e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 744e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 745e705c121SKalle Valo if (!ret) { 746e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 747fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 748e705c121SKalle Valo return -ETIMEDOUT; 749e705c121SKalle Valo } 750e705c121SKalle Valo 751e705c121SKalle Valo return 0; 752e705c121SKalle Valo } 753e705c121SKalle Valo 754e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 755e705c121SKalle Valo const struct fw_desc *section) 756e705c121SKalle Valo { 757e705c121SKalle Valo u8 *v_addr; 758e705c121SKalle Valo dma_addr_t p_addr; 759e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 760e705c121SKalle Valo int ret = 0; 761e705c121SKalle Valo 762e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 763e705c121SKalle Valo section_num); 764e705c121SKalle Valo 765e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 766e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 767e705c121SKalle Valo if (!v_addr) { 768e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 769e705c121SKalle Valo chunk_sz = PAGE_SIZE; 770e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 771e705c121SKalle Valo &p_addr, GFP_KERNEL); 772e705c121SKalle Valo if (!v_addr) 773e705c121SKalle Valo return -ENOMEM; 774e705c121SKalle Valo } 775e705c121SKalle Valo 776e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 777e705c121SKalle Valo u32 copy_size, dst_addr; 778e705c121SKalle Valo bool extended_addr = false; 779e705c121SKalle Valo 780e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 781e705c121SKalle Valo dst_addr = section->offset + offset; 782e705c121SKalle Valo 783e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 784e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 785e705c121SKalle Valo extended_addr = true; 786e705c121SKalle Valo 787e705c121SKalle Valo if (extended_addr) 788e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 789e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 790e705c121SKalle Valo 791e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 792e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 793e705c121SKalle Valo copy_size); 794e705c121SKalle Valo 795e705c121SKalle Valo if (extended_addr) 796e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 797e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 798e705c121SKalle Valo 799e705c121SKalle Valo if (ret) { 800e705c121SKalle Valo IWL_ERR(trans, 801e705c121SKalle Valo "Could not load the [%d] uCode section\n", 802e705c121SKalle Valo section_num); 803e705c121SKalle Valo break; 804e705c121SKalle Valo } 805e705c121SKalle Valo } 806e705c121SKalle Valo 807e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 808e705c121SKalle Valo return ret; 809e705c121SKalle Valo } 810e705c121SKalle Valo 811e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 812e705c121SKalle Valo const struct fw_img *image, 813e705c121SKalle Valo int cpu, 814e705c121SKalle Valo int *first_ucode_section) 815e705c121SKalle Valo { 816e705c121SKalle Valo int shift_param; 817e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 818e705c121SKalle Valo u32 val, last_read_idx = 0; 819e705c121SKalle Valo 820e705c121SKalle Valo if (cpu == 1) { 821e705c121SKalle Valo shift_param = 0; 822e705c121SKalle Valo *first_ucode_section = 0; 823e705c121SKalle Valo } else { 824e705c121SKalle Valo shift_param = 16; 825e705c121SKalle Valo (*first_ucode_section)++; 826e705c121SKalle Valo } 827e705c121SKalle Valo 828eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 829e705c121SKalle Valo last_read_idx = i; 830e705c121SKalle Valo 831e705c121SKalle Valo /* 832e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 833e705c121SKalle Valo * CPU1 to CPU2. 834e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 835e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 836e705c121SKalle Valo */ 837e705c121SKalle Valo if (!image->sec[i].data || 838e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 839e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 840e705c121SKalle Valo IWL_DEBUG_FW(trans, 841e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 842e705c121SKalle Valo i); 843e705c121SKalle Valo break; 844e705c121SKalle Valo } 845e705c121SKalle Valo 846e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 847e705c121SKalle Valo if (ret) 848e705c121SKalle Valo return ret; 849e705c121SKalle Valo 850d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 851e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 852e705c121SKalle Valo val = val | (sec_num << shift_param); 853e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 854eda50cdeSSara Sharon 855e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 856e705c121SKalle Valo } 857e705c121SKalle Valo 858e705c121SKalle Valo *first_ucode_section = last_read_idx; 859e705c121SKalle Valo 8602aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8612aabdbdcSEmmanuel Grumbach 862d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 863e705c121SKalle Valo if (cpu == 1) 864d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 865d6a2c5c7SSara Sharon 0xFFFF); 866e705c121SKalle Valo else 867d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 868d6a2c5c7SSara Sharon 0xFFFFFFFF); 869d6a2c5c7SSara Sharon } else { 870d6a2c5c7SSara Sharon if (cpu == 1) 871d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 872d6a2c5c7SSara Sharon 0xFFFF); 873d6a2c5c7SSara Sharon else 874d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 875d6a2c5c7SSara Sharon 0xFFFFFFFF); 876d6a2c5c7SSara Sharon } 877e705c121SKalle Valo 878e705c121SKalle Valo return 0; 879e705c121SKalle Valo } 880e705c121SKalle Valo 881e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 882e705c121SKalle Valo const struct fw_img *image, 883e705c121SKalle Valo int cpu, 884e705c121SKalle Valo int *first_ucode_section) 885e705c121SKalle Valo { 886e705c121SKalle Valo int i, ret = 0; 887e705c121SKalle Valo u32 last_read_idx = 0; 888e705c121SKalle Valo 8893ce4a038SKirtika Ruchandani if (cpu == 1) 890e705c121SKalle Valo *first_ucode_section = 0; 8913ce4a038SKirtika Ruchandani else 892e705c121SKalle Valo (*first_ucode_section)++; 893e705c121SKalle Valo 894eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 895e705c121SKalle Valo last_read_idx = i; 896e705c121SKalle Valo 897e705c121SKalle Valo /* 898e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 899e705c121SKalle Valo * CPU1 to CPU2. 900e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 901e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 902e705c121SKalle Valo */ 903e705c121SKalle Valo if (!image->sec[i].data || 904e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 905e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 906e705c121SKalle Valo IWL_DEBUG_FW(trans, 907e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 908e705c121SKalle Valo i); 909e705c121SKalle Valo break; 910e705c121SKalle Valo } 911e705c121SKalle Valo 912e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 913e705c121SKalle Valo if (ret) 914e705c121SKalle Valo return ret; 915e705c121SKalle Valo } 916e705c121SKalle Valo 917e705c121SKalle Valo *first_ucode_section = last_read_idx; 918e705c121SKalle Valo 919e705c121SKalle Valo return 0; 920e705c121SKalle Valo } 921e705c121SKalle Valo 922c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 923e705c121SKalle Valo { 924fd527eb5SGolan Ben Ami const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 925e705c121SKalle Valo int i; 926e705c121SKalle Valo 9277a14c23dSSara Sharon if (trans->ini_valid) { 9287a14c23dSSara Sharon if (!trans->num_blocks) 9297a14c23dSSara Sharon return; 9307a14c23dSSara Sharon 9317a14c23dSSara Sharon iwl_write_prph(trans, MON_BUFF_BASE_ADDR_VER2, 9327a14c23dSSara Sharon trans->fw_mon[0].physical >> 9337a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 9347a14c23dSSara Sharon iwl_write_prph(trans, MON_BUFF_END_ADDR_VER2, 9357a14c23dSSara Sharon (trans->fw_mon[0].physical + 9367a14c23dSSara Sharon trans->fw_mon[0].size - 256) >> 9377a14c23dSSara Sharon MON_BUFF_SHIFT_VER2); 9387a14c23dSSara Sharon return; 9397a14c23dSSara Sharon } 9407a14c23dSSara Sharon 941e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 942e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 943e705c121SKalle Valo 944e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 945e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 946e705c121SKalle Valo else 947e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 948e705c121SKalle Valo 94917b809c9SSara Sharon for (i = 0; i < trans->dbg_n_dest_reg; i++) { 950e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 951e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 952e705c121SKalle Valo 953e705c121SKalle Valo switch (dest->reg_ops[i].op) { 954e705c121SKalle Valo case CSR_ASSIGN: 955e705c121SKalle Valo iwl_write32(trans, addr, val); 956e705c121SKalle Valo break; 957e705c121SKalle Valo case CSR_SETBIT: 958e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 959e705c121SKalle Valo break; 960e705c121SKalle Valo case CSR_CLEARBIT: 961e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 962e705c121SKalle Valo break; 963e705c121SKalle Valo case PRPH_ASSIGN: 964e705c121SKalle Valo iwl_write_prph(trans, addr, val); 965e705c121SKalle Valo break; 966e705c121SKalle Valo case PRPH_SETBIT: 967e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 968e705c121SKalle Valo break; 969e705c121SKalle Valo case PRPH_CLEARBIT: 970e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 971e705c121SKalle Valo break; 972e705c121SKalle Valo case PRPH_BLOCKBIT: 973e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 974e705c121SKalle Valo IWL_ERR(trans, 975e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 976e705c121SKalle Valo val, addr); 977e705c121SKalle Valo goto monitor; 978e705c121SKalle Valo } 979e705c121SKalle Valo break; 980e705c121SKalle Valo default: 981e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 982e705c121SKalle Valo dest->reg_ops[i].op); 983e705c121SKalle Valo break; 984e705c121SKalle Valo } 985e705c121SKalle Valo } 986e705c121SKalle Valo 987e705c121SKalle Valo monitor: 98888964b2eSSara Sharon if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { 989e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 99088964b2eSSara Sharon trans->fw_mon[0].physical >> dest->base_shift); 9916e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 992e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99388964b2eSSara Sharon (trans->fw_mon[0].physical + 99488964b2eSSara Sharon trans->fw_mon[0].size - 256) >> 99562d7476dSEmmanuel Grumbach dest->end_shift); 99662d7476dSEmmanuel Grumbach else 99762d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99888964b2eSSara Sharon (trans->fw_mon[0].physical + 99988964b2eSSara Sharon trans->fw_mon[0].size) >> 100062d7476dSEmmanuel Grumbach dest->end_shift); 1001e705c121SKalle Valo } 1002e705c121SKalle Valo } 1003e705c121SKalle Valo 1004e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1005e705c121SKalle Valo const struct fw_img *image) 1006e705c121SKalle Valo { 1007e705c121SKalle Valo int ret = 0; 1008e705c121SKalle Valo int first_ucode_section; 1009e705c121SKalle Valo 1010e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1011e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1012e705c121SKalle Valo 1013e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1014e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1015e705c121SKalle Valo if (ret) 1016e705c121SKalle Valo return ret; 1017e705c121SKalle Valo 1018e705c121SKalle Valo if (image->is_dual_cpus) { 1019e705c121SKalle Valo /* set CPU2 header address */ 1020e705c121SKalle Valo iwl_write_prph(trans, 1021e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1022e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1023e705c121SKalle Valo 1024e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1025e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1026e705c121SKalle Valo &first_ucode_section); 1027e705c121SKalle Valo if (ret) 1028e705c121SKalle Valo return ret; 1029e705c121SKalle Valo } 1030e705c121SKalle Valo 1031e705c121SKalle Valo /* supported for 7000 only for the moment */ 1032e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1033e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1034e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1035e705c121SKalle Valo 103688964b2eSSara Sharon if (trans->fw_mon[0].size) { 1037e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 103888964b2eSSara Sharon trans->fw_mon[0].physical >> 4); 1039e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 104088964b2eSSara Sharon (trans->fw_mon[0].physical + 104188964b2eSSara Sharon trans->fw_mon[0].size) >> 4); 1042e705c121SKalle Valo } 10437a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1044e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1045e705c121SKalle Valo } 1046e705c121SKalle Valo 10472aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10482aabdbdcSEmmanuel Grumbach 1049e705c121SKalle Valo /* release CPU reset */ 1050e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1051e705c121SKalle Valo 1052e705c121SKalle Valo return 0; 1053e705c121SKalle Valo } 1054e705c121SKalle Valo 1055e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1056e705c121SKalle Valo const struct fw_img *image) 1057e705c121SKalle Valo { 1058e705c121SKalle Valo int ret = 0; 1059e705c121SKalle Valo int first_ucode_section; 1060e705c121SKalle Valo 1061e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1062e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1063e705c121SKalle Valo 10647a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1065e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1066e705c121SKalle Valo 106782ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 106882ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 106982ea7966SSara Sharon 107082ea7966SSara Sharon /* 107182ea7966SSara Sharon * Set default value. On resume reading the values that were 107282ea7966SSara Sharon * zeored can provide debug data on the resume flow. 107382ea7966SSara Sharon * This is for debugging only and has no functional impact. 107482ea7966SSara Sharon */ 107582ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 107682ea7966SSara Sharon 1077e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1078e705c121SKalle Valo /* release CPU reset */ 1079e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1080e705c121SKalle Valo 1081e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1082e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1083e705c121SKalle Valo &first_ucode_section); 1084e705c121SKalle Valo if (ret) 1085e705c121SKalle Valo return ret; 1086e705c121SKalle Valo 1087e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1088e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1089e705c121SKalle Valo &first_ucode_section); 1090e705c121SKalle Valo } 1091e705c121SKalle Valo 10929ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1093727c02dfSSara Sharon { 1094326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1095727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1096326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1097326477e4SJohannes Berg bool report; 1098727c02dfSSara Sharon 1099326477e4SJohannes Berg if (hw_rfkill) { 1100326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1101326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1102326477e4SJohannes Berg } else { 1103326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1104326477e4SJohannes Berg if (trans_pcie->opmode_down) 1105326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1106326477e4SJohannes Berg } 1107727c02dfSSara Sharon 1108326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1109326477e4SJohannes Berg 1110326477e4SJohannes Berg if (prev != report) 1111326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1112727c02dfSSara Sharon 1113727c02dfSSara Sharon return hw_rfkill; 1114727c02dfSSara Sharon } 1115727c02dfSSara Sharon 11167ca00409SHaim Dreyfuss struct iwl_causes_list { 11177ca00409SHaim Dreyfuss u32 cause_num; 11187ca00409SHaim Dreyfuss u32 mask_reg; 11197ca00409SHaim Dreyfuss u8 addr; 11207ca00409SHaim Dreyfuss }; 11217ca00409SHaim Dreyfuss 11227ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11237ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11247ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11257ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11267ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11277ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11287ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11297ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11307ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11317ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11327ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11337ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11347ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11357ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11367ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11377ca00409SHaim Dreyfuss }; 11387ca00409SHaim Dreyfuss 11399b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11409b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11419b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11429b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11439b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11449b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11459b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11469b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11479b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11489b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11499b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11509b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11519b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11529b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11539b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11549b58419eSGolan Ben Ami }; 11559b58419eSGolan Ben Ami 11567ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11577ca00409SHaim Dreyfuss { 11587ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11597ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11609b58419eSGolan Ben Ami int i, arr_size = 11619b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11629b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11637ca00409SHaim Dreyfuss 11647ca00409SHaim Dreyfuss /* 11657ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11667ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11677ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11687ca00409SHaim Dreyfuss */ 11699b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11709b58419eSGolan Ben Ami struct iwl_causes_list *causes = 11719b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11729b58419eSGolan Ben Ami causes_list : causes_list_v2; 11739b58419eSGolan Ben Ami 11749b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11759b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11769b58419eSGolan Ben Ami causes[i].cause_num); 11777ca00409SHaim Dreyfuss } 11787ca00409SHaim Dreyfuss } 11797ca00409SHaim Dreyfuss 11807ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11817ca00409SHaim Dreyfuss { 11827ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11837ca00409SHaim Dreyfuss u32 offset = 11847ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11857ca00409SHaim Dreyfuss u32 val, idx; 11867ca00409SHaim Dreyfuss 11877ca00409SHaim Dreyfuss /* 11887ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11897ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11907ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11917ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11927ca00409SHaim Dreyfuss */ 11937ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11947ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11957ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11967ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11977ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11987ca00409SHaim Dreyfuss } 11997ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 12007ca00409SHaim Dreyfuss 12017ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 12027ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 12037ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 12047ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 12057ca00409SHaim Dreyfuss 12067ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 12077ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 12087ca00409SHaim Dreyfuss } 12097ca00409SHaim Dreyfuss 121077c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 12117ca00409SHaim Dreyfuss { 12127ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 12137ca00409SHaim Dreyfuss 12147ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1215d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1216d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12177ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, 12187ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 12197ca00409SHaim Dreyfuss return; 12207ca00409SHaim Dreyfuss } 1221d7270d61SHaim Dreyfuss /* 1222d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1223d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1224d7270d61SHaim Dreyfuss * prph. 1225d7270d61SHaim Dreyfuss */ 1226d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12277ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12287ca00409SHaim Dreyfuss 12297ca00409SHaim Dreyfuss /* 12307ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12317ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12327ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12337ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12347ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12357ca00409SHaim Dreyfuss */ 12367ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12377ca00409SHaim Dreyfuss 12387ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 123983730058SHaim Dreyfuss } 12407ca00409SHaim Dreyfuss 124183730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 124283730058SHaim Dreyfuss { 124383730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 124483730058SHaim Dreyfuss 124583730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 124683730058SHaim Dreyfuss 124783730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 124883730058SHaim Dreyfuss return; 124983730058SHaim Dreyfuss 125083730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12517ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 125283730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12537ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12547ca00409SHaim Dreyfuss } 12557ca00409SHaim Dreyfuss 1256e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1257e705c121SKalle Valo { 1258e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1259e705c121SKalle Valo 1260e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1261e705c121SKalle Valo 1262e705c121SKalle Valo if (trans_pcie->is_down) 1263e705c121SKalle Valo return; 1264e705c121SKalle Valo 1265e705c121SKalle Valo trans_pcie->is_down = true; 1266e705c121SKalle Valo 12670232d2cdSSara Sharon /* Stop dbgc before stopping device */ 12685cfe79c8SSara Sharon _iwl_fw_dbg_stop_recording(trans, NULL); 12690232d2cdSSara Sharon 1270e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1271e705c121SKalle Valo iwl_disable_interrupts(trans); 1272e705c121SKalle Valo 1273e705c121SKalle Valo /* device going down, Stop using ICT table */ 1274e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1275e705c121SKalle Valo 1276e705c121SKalle Valo /* 1277e705c121SKalle Valo * If a HW restart happens during firmware loading, 1278e705c121SKalle Valo * then the firmware loading might call this function 1279e705c121SKalle Valo * and later it might be called again due to the 1280e705c121SKalle Valo * restart. So don't process again if the device is 1281e705c121SKalle Valo * already dead. 1282e705c121SKalle Valo */ 1283e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1284a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1285a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1286e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1287e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1288e705c121SKalle Valo 1289e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1290e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1291e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1292e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1293e705c121SKalle Valo udelay(5); 1294e705c121SKalle Valo } 1295e705c121SKalle Valo } 1296e705c121SKalle Valo 1297e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1298e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1299a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1300e705c121SKalle Valo 1301e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1302e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1303e705c121SKalle Valo 1304870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1305e705c121SKalle Valo 1306e705c121SKalle Valo /* 1307f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1308f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1309f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1310f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1311f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1312f4a1f04aSGolan Ben Ami */ 1313f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1314f4a1f04aSGolan Ben Ami 1315f4a1f04aSGolan Ben Ami /* 1316e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1317e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1318e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1319e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1320e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1321e705c121SKalle Valo */ 1322e705c121SKalle Valo iwl_disable_interrupts(trans); 1323e705c121SKalle Valo 1324e705c121SKalle Valo /* clear all status bits */ 1325e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1326e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1327e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1328e705c121SKalle Valo 1329e705c121SKalle Valo /* 1330e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1331e705c121SKalle Valo * interrupt 1332e705c121SKalle Valo */ 1333e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1334e705c121SKalle Valo 1335a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1336e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1337e705c121SKalle Valo } 1338e705c121SKalle Valo 1339eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13402e5d4a8fSHaim Dreyfuss { 13412e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13422e5d4a8fSHaim Dreyfuss 13432e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13442e5d4a8fSHaim Dreyfuss int i; 13452e5d4a8fSHaim Dreyfuss 1346496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13472e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13482e5d4a8fSHaim Dreyfuss } else { 13492e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13502e5d4a8fSHaim Dreyfuss } 13512e5d4a8fSHaim Dreyfuss } 13522e5d4a8fSHaim Dreyfuss 1353a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1354a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1355a6bd005fSEmmanuel Grumbach { 1356a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1357a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1358a6bd005fSEmmanuel Grumbach int ret; 1359a6bd005fSEmmanuel Grumbach 1360a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1361a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1362a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1363a6bd005fSEmmanuel Grumbach ret = -EIO; 1364a6bd005fSEmmanuel Grumbach goto out; 1365a6bd005fSEmmanuel Grumbach } 1366a6bd005fSEmmanuel Grumbach 1367a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1368a6bd005fSEmmanuel Grumbach 1369a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1370a6bd005fSEmmanuel Grumbach 1371a6bd005fSEmmanuel Grumbach /* 1372a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1373a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1374a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1375a6bd005fSEmmanuel Grumbach */ 1376a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1377a6bd005fSEmmanuel Grumbach 1378a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13792e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1382a6bd005fSEmmanuel Grumbach 1383a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13849ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1385a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1386a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1387a6bd005fSEmmanuel Grumbach goto out; 1388a6bd005fSEmmanuel Grumbach } 1389a6bd005fSEmmanuel Grumbach 1390a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1391a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1392a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1393a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 139420aa99bbSAnton Protopopov ret = -EIO; 1395a6bd005fSEmmanuel Grumbach goto out; 1396a6bd005fSEmmanuel Grumbach } 1397a6bd005fSEmmanuel Grumbach 1398a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1399a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1400a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1401a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1402a6bd005fSEmmanuel Grumbach 1403a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1404a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1405a6bd005fSEmmanuel Grumbach 1406a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1407a6bd005fSEmmanuel Grumbach if (ret) { 1408a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1409a6bd005fSEmmanuel Grumbach goto out; 1410a6bd005fSEmmanuel Grumbach } 1411a6bd005fSEmmanuel Grumbach 1412a6bd005fSEmmanuel Grumbach /* 1413a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1414a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1415a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1416a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1417a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1418a6bd005fSEmmanuel Grumbach */ 1419a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1420a6bd005fSEmmanuel Grumbach 1421a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1422a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1423a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1424a6bd005fSEmmanuel Grumbach 1425a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 14266e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1427a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1428a6bd005fSEmmanuel Grumbach else 1429a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1430a6bd005fSEmmanuel Grumbach 1431a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14329ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1433a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1434a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1435a6bd005fSEmmanuel Grumbach 1436a6bd005fSEmmanuel Grumbach out: 1437a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1438a6bd005fSEmmanuel Grumbach return ret; 1439a6bd005fSEmmanuel Grumbach } 1440a6bd005fSEmmanuel Grumbach 1441a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1442a6bd005fSEmmanuel Grumbach { 1443a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1444a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1445a6bd005fSEmmanuel Grumbach } 1446a6bd005fSEmmanuel Grumbach 1447326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1448326477e4SJohannes Berg bool was_in_rfkill) 1449326477e4SJohannes Berg { 1450326477e4SJohannes Berg bool hw_rfkill; 1451326477e4SJohannes Berg 1452326477e4SJohannes Berg /* 1453326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1454326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1455326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1456326477e4SJohannes Berg * op_mode. 1457326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1458326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1459326477e4SJohannes Berg * notification without endless recursion. Under very rare 1460326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1461326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1462326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1463326477e4SJohannes Berg */ 1464326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1465326477e4SJohannes Berg if (hw_rfkill) { 1466326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1467326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1468326477e4SJohannes Berg } else { 1469326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1470326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1471326477e4SJohannes Berg } 1472326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1473326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1474326477e4SJohannes Berg } 1475326477e4SJohannes Berg 1476e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1477e705c121SKalle Valo { 1478e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1479326477e4SJohannes Berg bool was_in_rfkill; 1480e705c121SKalle Valo 1481e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1482326477e4SJohannes Berg trans_pcie->opmode_down = true; 1483326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1484e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1485326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1486e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1487e705c121SKalle Valo } 1488e705c121SKalle Valo 1489e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1490e705c121SKalle Valo { 1491e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1492e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1493e705c121SKalle Valo 1494e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1495e705c121SKalle Valo 1496326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1497326477e4SJohannes Berg state ? "disabled" : "enabled"); 149877c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 149977c09bc8SSara Sharon if (trans->cfg->gen2) 150077c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 150177c09bc8SSara Sharon else 1502e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1503e705c121SKalle Valo } 150477c09bc8SSara Sharon } 1505e705c121SKalle Valo 150623ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 150723ae6128SMatti Gottlieb bool reset) 1508e705c121SKalle Valo { 150923ae6128SMatti Gottlieb if (!reset) { 1510e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1511e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1512e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1513e705c121SKalle Valo } 1514e705c121SKalle Valo 1515e705c121SKalle Valo iwl_disable_interrupts(trans); 1516e705c121SKalle Valo 1517e705c121SKalle Valo /* 1518e705c121SKalle Valo * in testing mode, the host stays awake and the 1519e705c121SKalle Valo * hardware won't be reset (not even partially) 1520e705c121SKalle Valo */ 1521e705c121SKalle Valo if (test) 1522e705c121SKalle Valo return; 1523e705c121SKalle Valo 1524e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1525e705c121SKalle Valo 15262e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1527e705c121SKalle Valo 1528e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1529a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1530e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1531a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1532e705c121SKalle Valo 15331316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, false); 15341316d595SSara Sharon 153523ae6128SMatti Gottlieb if (reset) { 1536e705c121SKalle Valo /* 1537e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1538e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1539e705c121SKalle Valo * to execute some invalid memory upon resume 1540e705c121SKalle Valo */ 1541e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1542e705c121SKalle Valo } 1543e705c121SKalle Valo 1544e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1545e705c121SKalle Valo } 1546e705c121SKalle Valo 1547e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1548e705c121SKalle Valo enum iwl_d3_status *status, 154923ae6128SMatti Gottlieb bool test, bool reset) 1550e705c121SKalle Valo { 1551d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1552e705c121SKalle Valo u32 val; 1553e705c121SKalle Valo int ret; 1554e705c121SKalle Valo 1555e705c121SKalle Valo if (test) { 1556e705c121SKalle Valo iwl_enable_interrupts(trans); 1557e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1558e705c121SKalle Valo return 0; 1559e705c121SKalle Valo } 1560e705c121SKalle Valo 15611316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 15621316d595SSara Sharon 1563a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1564a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1565a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1566a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1567e705c121SKalle Valo 15686e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1569e705c121SKalle Valo udelay(2); 1570e705c121SKalle Valo 1571e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1572a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1573a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1574e705c121SKalle Valo 25000); 1575e705c121SKalle Valo if (ret < 0) { 1576e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1577e705c121SKalle Valo return ret; 1578e705c121SKalle Valo } 1579e705c121SKalle Valo 1580f98ad635SEmmanuel Grumbach /* 1581f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1582f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1583f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1584f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1585f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1586f98ad635SEmmanuel Grumbach */ 1587f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1588f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1589f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1590f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1591f98ad635SEmmanuel Grumbach 1592e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1593e705c121SKalle Valo 159423ae6128SMatti Gottlieb if (!reset) { 1595e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1596a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1597e705c121SKalle Valo } else { 1598e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1599e705c121SKalle Valo 1600e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1601e705c121SKalle Valo if (ret) { 1602e705c121SKalle Valo IWL_ERR(trans, 1603e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1604e705c121SKalle Valo return ret; 1605e705c121SKalle Valo } 1606e705c121SKalle Valo } 1607e705c121SKalle Valo 160882ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 160982ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 161082ea7966SSara Sharon 1611e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1612e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1613e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1614e705c121SKalle Valo else 1615e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1616e705c121SKalle Valo 1617e705c121SKalle Valo return 0; 1618e705c121SKalle Valo } 1619e705c121SKalle Valo 16202e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16212e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 16222e5d4a8fSHaim Dreyfuss { 16232e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1624ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16252e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16262e5d4a8fSHaim Dreyfuss 162706f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 162806f4b081SSara Sharon goto enable_msi; 162906f4b081SSara Sharon 1630ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 163106f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16322e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16332e5d4a8fSHaim Dreyfuss 163406f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16352e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 163606f4b081SSara Sharon max_irqs); 163706f4b081SSara Sharon if (num_irqs < 0) { 1638496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 163906f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 164006f4b081SSara Sharon num_irqs); 164106f4b081SSara Sharon goto enable_msi; 1642496d83caSHaim Dreyfuss } 164306f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1644496d83caSHaim Dreyfuss 16452e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164606f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 164706f4b081SSara Sharon num_irqs); 164806f4b081SSara Sharon 1649496d83caSHaim Dreyfuss /* 165006f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 165106f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1652496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1653496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1654496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1655496d83caSHaim Dreyfuss */ 1656ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 165706f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1658496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1659496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1660ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 166106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1662496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1663496d83caSHaim Dreyfuss } else { 166406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1665496d83caSHaim Dreyfuss } 1666ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16672e5d4a8fSHaim Dreyfuss 166806f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1669496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16702e5d4a8fSHaim Dreyfuss return; 16712e5d4a8fSHaim Dreyfuss 167206f4b081SSara Sharon enable_msi: 167306f4b081SSara Sharon ret = pci_enable_msi(pdev); 167406f4b081SSara Sharon if (ret) { 167506f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16762e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16772e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16782e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16792e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16802e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16812e5d4a8fSHaim Dreyfuss } 16822e5d4a8fSHaim Dreyfuss } 16832e5d4a8fSHaim Dreyfuss } 16842e5d4a8fSHaim Dreyfuss 16857c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16867c8d91ebSHaim Dreyfuss { 16877c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16887c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16897c8d91ebSHaim Dreyfuss 16907c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16917c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16927c8d91ebSHaim Dreyfuss offset = 1 + i; 16937c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16947c8d91ebSHaim Dreyfuss /* 16957c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16967c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16977c8d91ebSHaim Dreyfuss */ 16987c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16997c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17007c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17017c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17027c8d91ebSHaim Dreyfuss if (ret) 17037c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17047c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 17057c8d91ebSHaim Dreyfuss i); 17067c8d91ebSHaim Dreyfuss } 17077c8d91ebSHaim Dreyfuss } 17087c8d91ebSHaim Dreyfuss 17092e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17102e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17112e5d4a8fSHaim Dreyfuss { 1712496d83caSHaim Dreyfuss int i; 17132e5d4a8fSHaim Dreyfuss 1714496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17152e5d4a8fSHaim Dreyfuss int ret; 17165a41a86cSSharon Dvir struct msix_entry *msix_entry; 171764fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 171864fa3affSSharon Dvir 171964fa3affSSharon Dvir if (!qname) 172064fa3affSSharon Dvir return -ENOMEM; 17212e5d4a8fSHaim Dreyfuss 17225a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17235a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17245a41a86cSSharon Dvir msix_entry->vector, 17252e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1726496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17272e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17282e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17292e5d4a8fSHaim Dreyfuss IRQF_SHARED, 173064fa3affSSharon Dvir qname, 17315a41a86cSSharon Dvir msix_entry); 17322e5d4a8fSHaim Dreyfuss if (ret) { 17332e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17342e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17355a41a86cSSharon Dvir 17362e5d4a8fSHaim Dreyfuss return ret; 17372e5d4a8fSHaim Dreyfuss } 17382e5d4a8fSHaim Dreyfuss } 17397c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17402e5d4a8fSHaim Dreyfuss 17412e5d4a8fSHaim Dreyfuss return 0; 17422e5d4a8fSHaim Dreyfuss } 17432e5d4a8fSHaim Dreyfuss 1744e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1745e705c121SKalle Valo { 1746e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17478954e1ebSShahar S Matityahu u32 hpm; 1748e705c121SKalle Valo int err; 1749e705c121SKalle Valo 1750e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1751e705c121SKalle Valo 1752e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1753e705c121SKalle Valo if (err) { 1754e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1755e705c121SKalle Valo return err; 1756e705c121SKalle Valo } 1757e705c121SKalle Valo 17588954e1ebSShahar S Matityahu hpm = iwl_trans_read_prph(trans, HPM_DEBUG); 17598954e1ebSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 17608954e1ebSShahar S Matityahu if (iwl_trans_read_prph(trans, PREG_PRPH_WPROT_0) & 17618954e1ebSShahar S Matityahu PREG_WFPM_ACCESS) { 17628954e1ebSShahar S Matityahu IWL_ERR(trans, 17638954e1ebSShahar S Matityahu "Error, can not clear persistence bit\n"); 17648954e1ebSShahar S Matityahu return -EPERM; 17658954e1ebSShahar S Matityahu } 17668954e1ebSShahar S Matityahu iwl_trans_write_prph(trans, HPM_DEBUG, hpm & ~PERSISTENCE_BIT); 17678954e1ebSShahar S Matityahu } 17688954e1ebSShahar S Matityahu 1769870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1770e705c121SKalle Valo 177152b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 177252b6e168SEmmanuel Grumbach if (err) 177352b6e168SEmmanuel Grumbach return err; 1774e705c121SKalle Valo 17752e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 177683730058SHaim Dreyfuss 1777e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1778e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1779e705c121SKalle Valo 1780326477e4SJohannes Berg trans_pcie->opmode_down = false; 1781326477e4SJohannes Berg 1782e705c121SKalle Valo /* Set is_down to false here so that...*/ 1783e705c121SKalle Valo trans_pcie->is_down = false; 1784e705c121SKalle Valo 1785e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17869ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1787e705c121SKalle Valo 17884cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 17894cbb8e50SLuciano Coelho if (low_power) 17904cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 17914cbb8e50SLuciano Coelho 1792e705c121SKalle Valo return 0; 1793e705c121SKalle Valo } 1794e705c121SKalle Valo 1795e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1796e705c121SKalle Valo { 1797e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1798e705c121SKalle Valo int ret; 1799e705c121SKalle Valo 1800e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1801e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1802e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1803e705c121SKalle Valo 1804e705c121SKalle Valo return ret; 1805e705c121SKalle Valo } 1806e705c121SKalle Valo 1807e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1808e705c121SKalle Valo { 1809e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1810e705c121SKalle Valo 1811e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1812e705c121SKalle Valo 1813e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1814e705c121SKalle Valo iwl_disable_interrupts(trans); 1815e705c121SKalle Valo 1816e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1817e705c121SKalle Valo 1818e705c121SKalle Valo iwl_disable_interrupts(trans); 1819e705c121SKalle Valo 1820e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1821e705c121SKalle Valo 1822e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1823e705c121SKalle Valo 18242e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1825e705c121SKalle Valo } 1826e705c121SKalle Valo 1827e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1828e705c121SKalle Valo { 1829e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1830e705c121SKalle Valo } 1831e705c121SKalle Valo 1832e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1833e705c121SKalle Valo { 1834e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1835e705c121SKalle Valo } 1836e705c121SKalle Valo 1837e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1838e705c121SKalle Valo { 1839e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1840e705c121SKalle Valo } 1841e705c121SKalle Valo 184284fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 184384fb372cSSara Sharon { 184484fb372cSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 184584fb372cSSara Sharon return 0x00FFFFFF; 184684fb372cSSara Sharon else 184784fb372cSSara Sharon return 0x000FFFFF; 184884fb372cSSara Sharon } 184984fb372cSSara Sharon 1850e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1851e705c121SKalle Valo { 185284fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 185384fb372cSSara Sharon 1854e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 185584fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1856e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1857e705c121SKalle Valo } 1858e705c121SKalle Valo 1859e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1860e705c121SKalle Valo u32 val) 1861e705c121SKalle Valo { 186284fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 186384fb372cSSara Sharon 1864e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 186584fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1866e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1867e705c121SKalle Valo } 1868e705c121SKalle Valo 1869e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1870e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1871e705c121SKalle Valo { 1872e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1873e705c121SKalle Valo 1874e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1875e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1876e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1877e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1878e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1879e705c121SKalle Valo else 1880e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1881e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1882e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1883e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1884e705c121SKalle Valo 18856c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18866c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18876c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1888e705c121SKalle Valo 1889e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1890e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 189141837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1892e705c121SKalle Valo 189321cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 189421cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 189521cb3222SJohannes Berg 189639bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 189739bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 189839bdb17eSSharon Dvir 1899e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1900e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1901e705c121SKalle Valo * As this function may be called again in some corner cases don't 1902e705c121SKalle Valo * do anything if NAPI was already initialized. 1903e705c121SKalle Valo */ 1904bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1905e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1906e705c121SKalle Valo } 1907e705c121SKalle Valo 1908e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1909e705c121SKalle Valo { 1910e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19116eb5e529SEmmanuel Grumbach int i; 1912e705c121SKalle Valo 19132e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1914e705c121SKalle Valo 191513a3a390SSara Sharon if (trans->cfg->gen2) 191613a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 191713a3a390SSara Sharon else 1918e705c121SKalle Valo iwl_pcie_tx_free(trans); 1919e705c121SKalle Valo iwl_pcie_rx_free(trans); 1920e705c121SKalle Valo 192110a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 192210a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 192310a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 192410a54d81SLuca Coelho } 192510a54d81SLuca Coelho 19262e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19277c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19287c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19297c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19307c8d91ebSHaim Dreyfuss NULL); 19317c8d91ebSHaim Dreyfuss } 19322e5d4a8fSHaim Dreyfuss 19332e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19342e5d4a8fSHaim Dreyfuss } else { 1935e705c121SKalle Valo iwl_pcie_free_ict(trans); 19362e5d4a8fSHaim Dreyfuss } 1937e705c121SKalle Valo 1938e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1939e705c121SKalle Valo 19406eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19416eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19426eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19436eb5e529SEmmanuel Grumbach 19446eb5e529SEmmanuel Grumbach if (p->page) 19456eb5e529SEmmanuel Grumbach __free_page(p->page); 19466eb5e529SEmmanuel Grumbach } 19476eb5e529SEmmanuel Grumbach 19486eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1949a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1950e705c121SKalle Valo iwl_trans_free(trans); 1951e705c121SKalle Valo } 1952e705c121SKalle Valo 1953e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1954e705c121SKalle Valo { 1955e705c121SKalle Valo if (state) 1956e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1957e705c121SKalle Valo else 1958e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1959e705c121SKalle Valo } 1960e705c121SKalle Valo 196149564a80SLuca Coelho struct iwl_trans_pcie_removal { 196249564a80SLuca Coelho struct pci_dev *pdev; 196349564a80SLuca Coelho struct work_struct work; 196449564a80SLuca Coelho }; 196549564a80SLuca Coelho 196649564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 196749564a80SLuca Coelho { 196849564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 196949564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 197049564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1971aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 197249564a80SLuca Coelho 197349564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 197449564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 197549564a80SLuca Coelho pci_lock_rescan_remove(); 197649564a80SLuca Coelho pci_dev_put(pdev); 197749564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 197849564a80SLuca Coelho pci_unlock_rescan_remove(); 197949564a80SLuca Coelho 198049564a80SLuca Coelho kfree(removal); 198149564a80SLuca Coelho module_put(THIS_MODULE); 198249564a80SLuca Coelho } 198349564a80SLuca Coelho 198423ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1985e705c121SKalle Valo unsigned long *flags) 1986e705c121SKalle Valo { 1987e705c121SKalle Valo int ret; 1988e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1989e705c121SKalle Valo 1990e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1991e705c121SKalle Valo 1992e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1993e705c121SKalle Valo goto out; 1994e705c121SKalle Valo 1995e705c121SKalle Valo /* this bit wakes up the NIC */ 1996e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1997a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19986e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1999e705c121SKalle Valo udelay(2); 2000e705c121SKalle Valo 2001e705c121SKalle Valo /* 2002e705c121SKalle Valo * These bits say the device is running, and should keep running for 2003e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2004e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2005fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2006fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2007e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2008e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2009e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2010e705c121SKalle Valo * to keep device from sleeping. 2011e705c121SKalle Valo * 2012e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2013e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2014fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2015fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2016fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2017e705c121SKalle Valo * 2018e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2019e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2020e705c121SKalle Valo */ 2021e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2022a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 2023a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2024e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2025e705c121SKalle Valo if (unlikely(ret < 0)) { 202649564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 202749564a80SLuca Coelho 2028e705c121SKalle Valo WARN_ONCE(1, 2029e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 203049564a80SLuca Coelho cntrl); 203149564a80SLuca Coelho 203249564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 203349564a80SLuca Coelho 203449564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 203549564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 203649564a80SLuca Coelho 2037f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 203849564a80SLuca Coelho goto err; 203949564a80SLuca Coelho 204049564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 204149564a80SLuca Coelho 204249564a80SLuca Coelho /* 204349564a80SLuca Coelho * get a module reference to avoid doing this 204449564a80SLuca Coelho * while unloading anyway and to avoid 204549564a80SLuca Coelho * scheduling a work with code that's being 204649564a80SLuca Coelho * removed. 204749564a80SLuca Coelho */ 204849564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 204949564a80SLuca Coelho IWL_ERR(trans, 205049564a80SLuca Coelho "Module is being unloaded - abort\n"); 205149564a80SLuca Coelho goto err; 205249564a80SLuca Coelho } 205349564a80SLuca Coelho 205449564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 205549564a80SLuca Coelho if (!removal) { 205649564a80SLuca Coelho module_put(THIS_MODULE); 205749564a80SLuca Coelho goto err; 205849564a80SLuca Coelho } 205949564a80SLuca Coelho /* 206049564a80SLuca Coelho * we don't need to clear this flag, because 206149564a80SLuca Coelho * the trans will be freed and reallocated. 206249564a80SLuca Coelho */ 2063f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 206449564a80SLuca Coelho 206549564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 206649564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 206749564a80SLuca Coelho pci_dev_get(removal->pdev); 206849564a80SLuca Coelho schedule_work(&removal->work); 206949564a80SLuca Coelho } else { 207049564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 207149564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 207249564a80SLuca Coelho } 207349564a80SLuca Coelho 207449564a80SLuca Coelho err: 2075e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2076e705c121SKalle Valo return false; 2077e705c121SKalle Valo } 2078e705c121SKalle Valo 2079e705c121SKalle Valo out: 2080e705c121SKalle Valo /* 2081e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2082e705c121SKalle Valo * track nic_access anyway. 2083e705c121SKalle Valo */ 2084e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2085e705c121SKalle Valo return true; 2086e705c121SKalle Valo } 2087e705c121SKalle Valo 2088e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2089e705c121SKalle Valo unsigned long *flags) 2090e705c121SKalle Valo { 2091e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2092e705c121SKalle Valo 2093e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2094e705c121SKalle Valo 2095e705c121SKalle Valo /* 2096e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2097e705c121SKalle Valo * track nic_access anyway. 2098e705c121SKalle Valo */ 2099e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2100e705c121SKalle Valo 2101e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2102e705c121SKalle Valo goto out; 2103e705c121SKalle Valo 2104e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2105a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2106e705c121SKalle Valo /* 2107e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2108e705c121SKalle Valo * any previous writes, but we need the write that clears the 2109e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2110e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2111e705c121SKalle Valo */ 2112e705c121SKalle Valo mmiowb(); 2113e705c121SKalle Valo out: 2114e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2115e705c121SKalle Valo } 2116e705c121SKalle Valo 2117e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2118e705c121SKalle Valo void *buf, int dwords) 2119e705c121SKalle Valo { 2120e705c121SKalle Valo unsigned long flags; 2121e705c121SKalle Valo int offs, ret = 0; 2122e705c121SKalle Valo u32 *vals = buf; 2123e705c121SKalle Valo 212423ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2125e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2126e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2127e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2128e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2129e705c121SKalle Valo } else { 2130e705c121SKalle Valo ret = -EBUSY; 2131e705c121SKalle Valo } 2132e705c121SKalle Valo return ret; 2133e705c121SKalle Valo } 2134e705c121SKalle Valo 2135e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2136e705c121SKalle Valo const void *buf, int dwords) 2137e705c121SKalle Valo { 2138e705c121SKalle Valo unsigned long flags; 2139e705c121SKalle Valo int offs, ret = 0; 2140e705c121SKalle Valo const u32 *vals = buf; 2141e705c121SKalle Valo 214223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2143e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2144e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2145e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2146e705c121SKalle Valo vals ? vals[offs] : 0); 2147e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2148e705c121SKalle Valo } else { 2149e705c121SKalle Valo ret = -EBUSY; 2150e705c121SKalle Valo } 2151e705c121SKalle Valo return ret; 2152e705c121SKalle Valo } 2153e705c121SKalle Valo 2154e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2155e705c121SKalle Valo unsigned long txqs, 2156e705c121SKalle Valo bool freeze) 2157e705c121SKalle Valo { 2158e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2159e705c121SKalle Valo int queue; 2160e705c121SKalle Valo 2161e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2162b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2163e705c121SKalle Valo unsigned long now; 2164e705c121SKalle Valo 2165e705c121SKalle Valo spin_lock_bh(&txq->lock); 2166e705c121SKalle Valo 2167e705c121SKalle Valo now = jiffies; 2168e705c121SKalle Valo 2169e705c121SKalle Valo if (txq->frozen == freeze) 2170e705c121SKalle Valo goto next_queue; 2171e705c121SKalle Valo 2172e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2173e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2174e705c121SKalle Valo 2175e705c121SKalle Valo txq->frozen = freeze; 2176e705c121SKalle Valo 2177bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2178e705c121SKalle Valo goto next_queue; 2179e705c121SKalle Valo 2180e705c121SKalle Valo if (freeze) { 2181e705c121SKalle Valo if (unlikely(time_after(now, 2182e705c121SKalle Valo txq->stuck_timer.expires))) { 2183e705c121SKalle Valo /* 2184e705c121SKalle Valo * The timer should have fired, maybe it is 2185e705c121SKalle Valo * spinning right now on the lock. 2186e705c121SKalle Valo */ 2187e705c121SKalle Valo goto next_queue; 2188e705c121SKalle Valo } 2189e705c121SKalle Valo /* remember how long until the timer fires */ 2190e705c121SKalle Valo txq->frozen_expiry_remainder = 2191e705c121SKalle Valo txq->stuck_timer.expires - now; 2192e705c121SKalle Valo del_timer(&txq->stuck_timer); 2193e705c121SKalle Valo goto next_queue; 2194e705c121SKalle Valo } 2195e705c121SKalle Valo 2196e705c121SKalle Valo /* 2197e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2198e705c121SKalle Valo * remainder before it froze 2199e705c121SKalle Valo */ 2200e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2201e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2202e705c121SKalle Valo 2203e705c121SKalle Valo next_queue: 2204e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2205e705c121SKalle Valo } 2206e705c121SKalle Valo } 2207e705c121SKalle Valo 22080cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22090cd58eaaSEmmanuel Grumbach { 22100cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22110cd58eaaSEmmanuel Grumbach int i; 22120cd58eaaSEmmanuel Grumbach 22130cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2214b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 22150cd58eaaSEmmanuel Grumbach 22160cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 22170cd58eaaSEmmanuel Grumbach continue; 22180cd58eaaSEmmanuel Grumbach 22190cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22200cd58eaaSEmmanuel Grumbach 22210cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22220cd58eaaSEmmanuel Grumbach txq->block--; 22230cd58eaaSEmmanuel Grumbach if (!txq->block) { 22240cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2225bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22260cd58eaaSEmmanuel Grumbach } 22270cd58eaaSEmmanuel Grumbach } else if (block) { 22280cd58eaaSEmmanuel Grumbach txq->block++; 22290cd58eaaSEmmanuel Grumbach } 22300cd58eaaSEmmanuel Grumbach 22310cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22320cd58eaaSEmmanuel Grumbach } 22330cd58eaaSEmmanuel Grumbach } 22340cd58eaaSEmmanuel Grumbach 2235e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2236e705c121SKalle Valo 223738398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 223838398efbSSara Sharon { 2239afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2240afb84431SEmmanuel Grumbach u32 status; 2241afb84431SEmmanuel Grumbach bool active; 2242afb84431SEmmanuel Grumbach u8 fifo; 224338398efbSSara Sharon 2244afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2245afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2246bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2247ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2248ae79785fSSara Sharon return; 2249afb84431SEmmanuel Grumbach } 2250ae79785fSSara Sharon 2251afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2252afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2253afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 225438398efbSSara Sharon 225538398efbSSara Sharon IWL_ERR(trans, 2256afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2257afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2258afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2259afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2260afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 22617b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2262afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 22637b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2264afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 226538398efbSSara Sharon } 226638398efbSSara Sharon 226792536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 226892536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 226992536c96SSara Sharon { 227092536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 227192536c96SSara Sharon 227292536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 227392536c96SSara Sharon return -EINVAL; 227492536c96SSara Sharon 227592536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 227692536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 227792536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 227892536c96SSara Sharon data->fr_bd_wid = 0; 227992536c96SSara Sharon 228092536c96SSara Sharon return 0; 228192536c96SSara Sharon } 228292536c96SSara Sharon 2283d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2284e705c121SKalle Valo { 2285e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2286e705c121SKalle Valo struct iwl_txq *txq; 2287e705c121SKalle Valo unsigned long now = jiffies; 2288e705c121SKalle Valo u8 wr_ptr; 2289e705c121SKalle Valo 22902b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2291f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2292f60c9e59SEmmanuel Grumbach return -ENODEV; 22932b3fae66SMatt Chen 2294d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2295d6d517b7SSara Sharon return -EINVAL; 2296e705c121SKalle Valo 2297d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2298d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22996aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2300e705c121SKalle Valo 23016aa7de05SMark Rutland while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2302e705c121SKalle Valo !time_after(jiffies, 2303e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23046aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2305e705c121SKalle Valo 2306e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 2307e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2308e705c121SKalle Valo wr_ptr, write_ptr)) 2309e705c121SKalle Valo return -ETIMEDOUT; 2310192185d6SJohannes Berg usleep_range(1000, 2000); 2311e705c121SKalle Valo } 2312e705c121SKalle Valo 2313bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2314e705c121SKalle Valo IWL_ERR(trans, 2315d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2316d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2317d6d517b7SSara Sharon return -ETIMEDOUT; 2318e705c121SKalle Valo } 2319e705c121SKalle Valo 2320d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2321d6d517b7SSara Sharon 2322d6d517b7SSara Sharon return 0; 2323d6d517b7SSara Sharon } 2324d6d517b7SSara Sharon 2325d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2326d6d517b7SSara Sharon { 2327d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2328d6d517b7SSara Sharon int cnt; 2329d6d517b7SSara Sharon int ret = 0; 2330d6d517b7SSara Sharon 2331d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2332d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2333d6d517b7SSara Sharon 2334d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2335d6d517b7SSara Sharon continue; 2336d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2337d6d517b7SSara Sharon continue; 2338d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2339d6d517b7SSara Sharon continue; 2340d6d517b7SSara Sharon 2341d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 234238398efbSSara Sharon if (ret) 2343d6d517b7SSara Sharon break; 2344d6d517b7SSara Sharon } 2345e705c121SKalle Valo 2346e705c121SKalle Valo return ret; 2347e705c121SKalle Valo } 2348e705c121SKalle Valo 2349e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2350e705c121SKalle Valo u32 mask, u32 value) 2351e705c121SKalle Valo { 2352e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2353e705c121SKalle Valo unsigned long flags; 2354e705c121SKalle Valo 2355e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2356e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2357e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2358e705c121SKalle Valo } 2359e705c121SKalle Valo 2360c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2361e705c121SKalle Valo { 2362e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2363e705c121SKalle Valo 2364e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2365e705c121SKalle Valo return; 2366e705c121SKalle Valo 2367b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 23685d93f3a2SLuca Coelho 23695d93f3a2SLuca Coelho #ifdef CONFIG_PM 23705d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23715d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23725d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2373e705c121SKalle Valo } 2374e705c121SKalle Valo 2375c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2376e705c121SKalle Valo { 2377e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2378e705c121SKalle Valo 2379e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2380e705c121SKalle Valo return; 2381e705c121SKalle Valo 2382b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2383b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2384b3ff1270SLuca Coelho 23855d93f3a2SLuca Coelho #ifdef CONFIG_PM 23865d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23875d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23885d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2389e705c121SKalle Valo } 2390e705c121SKalle Valo 2391e705c121SKalle Valo static const char *get_csr_string(int cmd) 2392e705c121SKalle Valo { 2393e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2394e705c121SKalle Valo switch (cmd) { 2395e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2396e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2397e705c121SKalle Valo IWL_CMD(CSR_INT); 2398e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2399e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2400e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2401e705c121SKalle Valo IWL_CMD(CSR_RESET); 2402e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2403e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2404e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2405e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2406e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2407e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2408e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2409e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2410e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2411e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2412e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2413e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2414e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2415e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2416e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2417e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2418e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2419e705c121SKalle Valo default: 2420e705c121SKalle Valo return "UNKNOWN"; 2421e705c121SKalle Valo } 2422e705c121SKalle Valo #undef IWL_CMD 2423e705c121SKalle Valo } 2424e705c121SKalle Valo 2425e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2426e705c121SKalle Valo { 2427e705c121SKalle Valo int i; 2428e705c121SKalle Valo static const u32 csr_tbl[] = { 2429e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2430e705c121SKalle Valo CSR_INT_COALESCING, 2431e705c121SKalle Valo CSR_INT, 2432e705c121SKalle Valo CSR_INT_MASK, 2433e705c121SKalle Valo CSR_FH_INT_STATUS, 2434e705c121SKalle Valo CSR_GPIO_IN, 2435e705c121SKalle Valo CSR_RESET, 2436e705c121SKalle Valo CSR_GP_CNTRL, 2437e705c121SKalle Valo CSR_HW_REV, 2438e705c121SKalle Valo CSR_EEPROM_REG, 2439e705c121SKalle Valo CSR_EEPROM_GP, 2440e705c121SKalle Valo CSR_OTP_GP_REG, 2441e705c121SKalle Valo CSR_GIO_REG, 2442e705c121SKalle Valo CSR_GP_UCODE_REG, 2443e705c121SKalle Valo CSR_GP_DRIVER_REG, 2444e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2445e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2446e705c121SKalle Valo CSR_LED_REG, 2447e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2448e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2449e705c121SKalle Valo CSR_ANA_PLL_CFG, 2450e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2451e705c121SKalle Valo CSR_HW_REV_WA_REG, 2452e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2453e705c121SKalle Valo }; 2454e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2455e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2456e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2457e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2458e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2459e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2460e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2461e705c121SKalle Valo } 2462e705c121SKalle Valo } 2463e705c121SKalle Valo 2464e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2465e705c121SKalle Valo /* create and remove of files */ 2466e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2467e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 2468e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 2469e705c121SKalle Valo goto err; \ 2470e705c121SKalle Valo } while (0) 2471e705c121SKalle Valo 2472e705c121SKalle Valo /* file operation */ 2473e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2474e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2475e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2476e705c121SKalle Valo .open = simple_open, \ 2477e705c121SKalle Valo .llseek = generic_file_llseek, \ 2478e705c121SKalle Valo }; 2479e705c121SKalle Valo 2480e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2481e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2482e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2483e705c121SKalle Valo .open = simple_open, \ 2484e705c121SKalle Valo .llseek = generic_file_llseek, \ 2485e705c121SKalle Valo }; 2486e705c121SKalle Valo 2487e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2488e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2489e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2490e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2491e705c121SKalle Valo .open = simple_open, \ 2492e705c121SKalle Valo .llseek = generic_file_llseek, \ 2493e705c121SKalle Valo }; 2494e705c121SKalle Valo 2495e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2496e705c121SKalle Valo char __user *user_buf, 2497e705c121SKalle Valo size_t count, loff_t *ppos) 2498e705c121SKalle Valo { 2499e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2500e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2501e705c121SKalle Valo struct iwl_txq *txq; 2502e705c121SKalle Valo char *buf; 2503e705c121SKalle Valo int pos = 0; 2504e705c121SKalle Valo int cnt; 2505e705c121SKalle Valo int ret; 2506e705c121SKalle Valo size_t bufsz; 2507e705c121SKalle Valo 2508e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2509e705c121SKalle Valo 2510b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2511e705c121SKalle Valo return -EAGAIN; 2512e705c121SKalle Valo 2513e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2514e705c121SKalle Valo if (!buf) 2515e705c121SKalle Valo return -ENOMEM; 2516e705c121SKalle Valo 2517e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2518b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2519e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2520e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2521bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2522e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2523e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2524e705c121SKalle Valo txq->need_update, txq->frozen, 2525e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2526e705c121SKalle Valo } 2527e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2528e705c121SKalle Valo kfree(buf); 2529e705c121SKalle Valo return ret; 2530e705c121SKalle Valo } 2531e705c121SKalle Valo 2532e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2533e705c121SKalle Valo char __user *user_buf, 2534e705c121SKalle Valo size_t count, loff_t *ppos) 2535e705c121SKalle Valo { 2536e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2537e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 253878485054SSara Sharon char *buf; 253978485054SSara Sharon int pos = 0, i, ret; 254078485054SSara Sharon size_t bufsz = sizeof(buf); 2541e705c121SKalle Valo 254278485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 254378485054SSara Sharon 254478485054SSara Sharon if (!trans_pcie->rxq) 254578485054SSara Sharon return -EAGAIN; 254678485054SSara Sharon 254778485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 254878485054SSara Sharon if (!buf) 254978485054SSara Sharon return -ENOMEM; 255078485054SSara Sharon 255178485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 255278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 255378485054SSara Sharon 255478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 255578485054SSara Sharon i); 255678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2557e705c121SKalle Valo rxq->read); 255878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2559e705c121SKalle Valo rxq->write); 256078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2561e705c121SKalle Valo rxq->write_actual); 256278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2563e705c121SKalle Valo rxq->need_update); 256478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2565e705c121SKalle Valo rxq->free_count); 2566e705c121SKalle Valo if (rxq->rb_stts) { 25670307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25680307c839SGolan Ben Ami rxq)); 256978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 257078485054SSara Sharon "\tclosed_rb_num: %u\n", 25710307c839SGolan Ben Ami r & 0x0FFF); 2572e705c121SKalle Valo } else { 2573e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 257478485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2575e705c121SKalle Valo } 257678485054SSara Sharon } 257778485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 257878485054SSara Sharon kfree(buf); 257978485054SSara Sharon 258078485054SSara Sharon return ret; 2581e705c121SKalle Valo } 2582e705c121SKalle Valo 2583e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2584e705c121SKalle Valo char __user *user_buf, 2585e705c121SKalle Valo size_t count, loff_t *ppos) 2586e705c121SKalle Valo { 2587e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2588e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2589e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2590e705c121SKalle Valo 2591e705c121SKalle Valo int pos = 0; 2592e705c121SKalle Valo char *buf; 2593e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2594e705c121SKalle Valo ssize_t ret; 2595e705c121SKalle Valo 2596e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2597e705c121SKalle Valo if (!buf) 2598e705c121SKalle Valo return -ENOMEM; 2599e705c121SKalle Valo 2600e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2601e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2602e705c121SKalle Valo 2603e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2604e705c121SKalle Valo isr_stats->hw); 2605e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2606e705c121SKalle Valo isr_stats->sw); 2607e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2608e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2609e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2610e705c121SKalle Valo isr_stats->err_code); 2611e705c121SKalle Valo } 2612e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2613e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2614e705c121SKalle Valo isr_stats->sch); 2615e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2616e705c121SKalle Valo isr_stats->alive); 2617e705c121SKalle Valo #endif 2618e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2619e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2620e705c121SKalle Valo 2621e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2622e705c121SKalle Valo isr_stats->ctkill); 2623e705c121SKalle Valo 2624e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2625e705c121SKalle Valo isr_stats->wakeup); 2626e705c121SKalle Valo 2627e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2628e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2629e705c121SKalle Valo 2630e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2631e705c121SKalle Valo isr_stats->tx); 2632e705c121SKalle Valo 2633e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2634e705c121SKalle Valo isr_stats->unhandled); 2635e705c121SKalle Valo 2636e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2637e705c121SKalle Valo kfree(buf); 2638e705c121SKalle Valo return ret; 2639e705c121SKalle Valo } 2640e705c121SKalle Valo 2641e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2642e705c121SKalle Valo const char __user *user_buf, 2643e705c121SKalle Valo size_t count, loff_t *ppos) 2644e705c121SKalle Valo { 2645e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2646e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2647e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2648e705c121SKalle Valo u32 reset_flag; 2649078f1131SJohannes Berg int ret; 2650e705c121SKalle Valo 2651078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2652078f1131SJohannes Berg if (ret) 2653078f1131SJohannes Berg return ret; 2654e705c121SKalle Valo if (reset_flag == 0) 2655e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2656e705c121SKalle Valo 2657e705c121SKalle Valo return count; 2658e705c121SKalle Valo } 2659e705c121SKalle Valo 2660e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2661e705c121SKalle Valo const char __user *user_buf, 2662e705c121SKalle Valo size_t count, loff_t *ppos) 2663e705c121SKalle Valo { 2664e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2665e705c121SKalle Valo 2666e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2667e705c121SKalle Valo 2668e705c121SKalle Valo return count; 2669e705c121SKalle Valo } 2670e705c121SKalle Valo 2671e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2672e705c121SKalle Valo char __user *user_buf, 2673e705c121SKalle Valo size_t count, loff_t *ppos) 2674e705c121SKalle Valo { 2675e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2676e705c121SKalle Valo char *buf = NULL; 2677e705c121SKalle Valo ssize_t ret; 2678e705c121SKalle Valo 2679e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2680e705c121SKalle Valo if (ret < 0) 2681e705c121SKalle Valo return ret; 2682e705c121SKalle Valo if (!buf) 2683e705c121SKalle Valo return -EINVAL; 2684e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2685e705c121SKalle Valo kfree(buf); 2686e705c121SKalle Valo return ret; 2687e705c121SKalle Valo } 2688e705c121SKalle Valo 2689fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2690fa4de7f7SJohannes Berg char __user *user_buf, 2691fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2692fa4de7f7SJohannes Berg { 2693fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2694fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2695fa4de7f7SJohannes Berg char buf[100]; 2696fa4de7f7SJohannes Berg int pos; 2697fa4de7f7SJohannes Berg 2698fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2699fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2700fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2701fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2702fa4de7f7SJohannes Berg 2703fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2704fa4de7f7SJohannes Berg } 2705fa4de7f7SJohannes Berg 2706fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2707fa4de7f7SJohannes Berg const char __user *user_buf, 2708fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2709fa4de7f7SJohannes Berg { 2710fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2711fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2712fa4de7f7SJohannes Berg bool old = trans_pcie->debug_rfkill; 2713fa4de7f7SJohannes Berg int ret; 2714fa4de7f7SJohannes Berg 2715fa4de7f7SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2716fa4de7f7SJohannes Berg if (ret) 2717fa4de7f7SJohannes Berg return ret; 2718fa4de7f7SJohannes Berg if (old == trans_pcie->debug_rfkill) 2719fa4de7f7SJohannes Berg return count; 2720fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2721fa4de7f7SJohannes Berg old, trans_pcie->debug_rfkill); 2722fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2723fa4de7f7SJohannes Berg 2724fa4de7f7SJohannes Berg return count; 2725fa4de7f7SJohannes Berg } 2726fa4de7f7SJohannes Berg 2727f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2728f7805b33SLior Cohen struct file *file) 2729f7805b33SLior Cohen { 2730f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2731f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2732f7805b33SLior Cohen 2733f7805b33SLior Cohen if (!trans->dbg_dest_tlv || 2734f7805b33SLior Cohen trans->dbg_dest_tlv->monitor_mode != EXTERNAL_MODE) { 2735f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2736f7805b33SLior Cohen return -ENOENT; 2737f7805b33SLior Cohen } 2738f7805b33SLior Cohen 2739f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2740f7805b33SLior Cohen return -EBUSY; 2741f7805b33SLior Cohen 2742f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2743f7805b33SLior Cohen return simple_open(inode, file); 2744f7805b33SLior Cohen } 2745f7805b33SLior Cohen 2746f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2747f7805b33SLior Cohen struct file *file) 2748f7805b33SLior Cohen { 2749f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2750f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2751f7805b33SLior Cohen 2752f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2753f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2754f7805b33SLior Cohen return 0; 2755f7805b33SLior Cohen } 2756f7805b33SLior Cohen 2757f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2758f7805b33SLior Cohen void *buf, ssize_t *size, 2759f7805b33SLior Cohen ssize_t *bytes_copied) 2760f7805b33SLior Cohen { 2761f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2762f7805b33SLior Cohen 2763f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2764f7805b33SLior Cohen if (*size > buf_size_left) 2765f7805b33SLior Cohen *size = buf_size_left; 2766f7805b33SLior Cohen 2767f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2768f7805b33SLior Cohen *bytes_copied += *size; 2769f7805b33SLior Cohen 2770f7805b33SLior Cohen if (buf_size_left == *size) 2771f7805b33SLior Cohen return true; 2772f7805b33SLior Cohen return false; 2773f7805b33SLior Cohen } 2774f7805b33SLior Cohen 2775f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2776f7805b33SLior Cohen char __user *user_buf, 2777f7805b33SLior Cohen size_t count, loff_t *ppos) 2778f7805b33SLior Cohen { 2779f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2780f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2781f7805b33SLior Cohen void *cpu_addr = (void *)trans->fw_mon[0].block, *curr_buf; 2782f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2783f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2784f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2785f7805b33SLior Cohen bool b_full; 2786f7805b33SLior Cohen 2787f7805b33SLior Cohen if (trans->dbg_dest_tlv) { 2788f7805b33SLior Cohen write_ptr_addr = 2789f7805b33SLior Cohen le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2790f7805b33SLior Cohen wrap_cnt_addr = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2791f7805b33SLior Cohen } else { 2792f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2793f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2794f7805b33SLior Cohen } 2795f7805b33SLior Cohen 2796f7805b33SLior Cohen if (unlikely(!trans->dbg_rec_on)) 2797f7805b33SLior Cohen return 0; 2798f7805b33SLior Cohen 2799f7805b33SLior Cohen mutex_lock(&data->mutex); 2800f7805b33SLior Cohen if (data->state == 2801f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2802f7805b33SLior Cohen mutex_unlock(&data->mutex); 2803f7805b33SLior Cohen return 0; 2804f7805b33SLior Cohen } 2805f7805b33SLior Cohen 2806f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2807f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2808f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2809f7805b33SLior Cohen 2810f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2811f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2812f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2813f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2814f7805b33SLior Cohen curr_buf, &size, 2815f7805b33SLior Cohen &bytes_copied); 2816f7805b33SLior Cohen data->prev_wr_ptr += size; 2817f7805b33SLior Cohen 2818f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2819f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 2820f7805b33SLior Cohen size = trans->fw_mon[0].size - data->prev_wr_ptr; 2821f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2822f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2823f7805b33SLior Cohen curr_buf, &size, 2824f7805b33SLior Cohen &bytes_copied); 2825f7805b33SLior Cohen data->prev_wr_ptr += size; 2826f7805b33SLior Cohen 2827f7805b33SLior Cohen if (!b_full) { 2828f7805b33SLior Cohen size = write_ptr; 2829f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2830f7805b33SLior Cohen cpu_addr, &size, 2831f7805b33SLior Cohen &bytes_copied); 2832f7805b33SLior Cohen data->prev_wr_ptr = size; 2833f7805b33SLior Cohen data->prev_wrap_cnt++; 2834f7805b33SLior Cohen } 2835f7805b33SLior Cohen } else { 2836f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2837f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2838f7805b33SLior Cohen IWL_WARN(trans, 2839f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2840f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2841f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2842f7805b33SLior Cohen IWL_WARN(trans, 2843f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2844f7805b33SLior Cohen 2845f7805b33SLior Cohen size = write_ptr; 2846f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2847f7805b33SLior Cohen cpu_addr, &size, 2848f7805b33SLior Cohen &bytes_copied); 2849f7805b33SLior Cohen data->prev_wr_ptr = size; 2850f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2851f7805b33SLior Cohen } 2852f7805b33SLior Cohen 2853f7805b33SLior Cohen mutex_unlock(&data->mutex); 2854f7805b33SLior Cohen 2855f7805b33SLior Cohen return bytes_copied; 2856f7805b33SLior Cohen } 2857f7805b33SLior Cohen 2858e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2859e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2860e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2861e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2862e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2863fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2864e705c121SKalle Valo 2865f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2866f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2867f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2868f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2869f7805b33SLior Cohen }; 2870f7805b33SLior Cohen 2871f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2872f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2873e705c121SKalle Valo { 2874f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2875f8a1edb7SJohannes Berg 28762ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28772ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28782ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28792ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28802ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28812ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2882f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2883e705c121SKalle Valo return 0; 2884e705c121SKalle Valo 2885e705c121SKalle Valo err: 2886e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2887e705c121SKalle Valo return -ENOMEM; 2888e705c121SKalle Valo } 2889f7805b33SLior Cohen 2890f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2891f7805b33SLior Cohen { 2892f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2893f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2894f7805b33SLior Cohen 2895f7805b33SLior Cohen mutex_lock(&data->mutex); 2896f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2897f7805b33SLior Cohen mutex_unlock(&data->mutex); 2898f7805b33SLior Cohen } 2899e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2900e705c121SKalle Valo 29016983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2902e705c121SKalle Valo { 29033cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2904e705c121SKalle Valo u32 cmdlen = 0; 2905e705c121SKalle Valo int i; 2906e705c121SKalle Valo 29073cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 29086983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2909e705c121SKalle Valo 2910e705c121SKalle Valo return cmdlen; 2911e705c121SKalle Valo } 2912e705c121SKalle Valo 2913e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2914e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2915e705c121SKalle Valo int allocated_rb_nums) 2916e705c121SKalle Valo { 2917e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2918e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 291978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 292078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2921e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2922e705c121SKalle Valo 2923e705c121SKalle Valo spin_lock(&rxq->lock); 2924e705c121SKalle Valo 29250307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2926e705c121SKalle Valo 2927e705c121SKalle Valo for (i = rxq->read, j = 0; 2928e705c121SKalle Valo i != r && j < allocated_rb_nums; 2929e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2930e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2931e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2932e705c121SKalle Valo 2933e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2934e705c121SKalle Valo DMA_FROM_DEVICE); 2935e705c121SKalle Valo 2936e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2937e705c121SKalle Valo 2938e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2939e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2940e705c121SKalle Valo rb = (void *)(*data)->data; 2941e705c121SKalle Valo rb->index = cpu_to_le32(i); 2942e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2943e705c121SKalle Valo /* remap the page for the free benefit */ 2944e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2945e705c121SKalle Valo max_len, 2946e705c121SKalle Valo DMA_FROM_DEVICE); 2947e705c121SKalle Valo 2948e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2949e705c121SKalle Valo } 2950e705c121SKalle Valo 2951e705c121SKalle Valo spin_unlock(&rxq->lock); 2952e705c121SKalle Valo 2953e705c121SKalle Valo return rb_len; 2954e705c121SKalle Valo } 2955e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2956e705c121SKalle Valo 2957e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2958e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2959e705c121SKalle Valo { 2960e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2961e705c121SKalle Valo __le32 *val; 2962e705c121SKalle Valo int i; 2963e705c121SKalle Valo 2964e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2965e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2966e705c121SKalle Valo val = (void *)(*data)->data; 2967e705c121SKalle Valo 2968e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2969e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2970e705c121SKalle Valo 2971e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2972e705c121SKalle Valo 2973e705c121SKalle Valo return csr_len; 2974e705c121SKalle Valo } 2975e705c121SKalle Valo 2976e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2977e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2978e705c121SKalle Valo { 2979e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2980e705c121SKalle Valo unsigned long flags; 2981e705c121SKalle Valo __le32 *val; 2982e705c121SKalle Valo int i; 2983e705c121SKalle Valo 298423ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2985e705c121SKalle Valo return 0; 2986e705c121SKalle Valo 2987e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2988e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2989e705c121SKalle Valo val = (void *)(*data)->data; 2990e705c121SKalle Valo 2991723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2992723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2993723b45e2SLiad Kaufman i += sizeof(u32)) 2994e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2995723b45e2SLiad Kaufman else 2996723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2997723b45e2SLiad Kaufman i += sizeof(u32)) 2998723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2999723b45e2SLiad Kaufman i)); 3000e705c121SKalle Valo 3001e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3002e705c121SKalle Valo 3003e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3004e705c121SKalle Valo 3005e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3006e705c121SKalle Valo } 3007e705c121SKalle Valo 3008e705c121SKalle Valo static u32 3009e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3010e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3011e705c121SKalle Valo u32 monitor_len) 3012e705c121SKalle Valo { 3013e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3014e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3015e705c121SKalle Valo unsigned long flags; 3016e705c121SKalle Valo u32 i; 3017e705c121SKalle Valo 301823ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3019e705c121SKalle Valo return 0; 3020e705c121SKalle Valo 302114ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3022e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 302314ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 302414ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 302514ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3026e705c121SKalle Valo 3027e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3028e705c121SKalle Valo 3029e705c121SKalle Valo return monitor_len; 3030e705c121SKalle Valo } 3031e705c121SKalle Valo 30327a14c23dSSara Sharon static void 30337a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30347a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30357a14c23dSSara Sharon { 30367a14c23dSSara Sharon u32 base, write_ptr, wrap_cnt; 30377a14c23dSSara Sharon 30387a14c23dSSara Sharon /* If there was a dest TLV - use the values from there */ 30397a14c23dSSara Sharon if (trans->ini_valid) { 30407a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR_VER2; 30417a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR_VER2; 30427a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT_VER2; 30437a14c23dSSara Sharon } else if (trans->dbg_dest_tlv) { 30447a14c23dSSara Sharon write_ptr = le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 30457a14c23dSSara Sharon wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 30467a14c23dSSara Sharon base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 30477a14c23dSSara Sharon } else { 30487a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30497a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30507a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30517a14c23dSSara Sharon } 30527a14c23dSSara Sharon fw_mon_data->fw_mon_wr_ptr = 30537a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, write_ptr)); 30547a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30557a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30567a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30577a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 30587a14c23dSSara Sharon } 30597a14c23dSSara Sharon 3060e705c121SKalle Valo static u32 3061e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3062e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3063e705c121SKalle Valo u32 monitor_len) 3064e705c121SKalle Valo { 3065e705c121SKalle Valo u32 len = 0; 3066e705c121SKalle Valo 306788964b2eSSara Sharon if ((trans->num_blocks && 3068e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 30697a14c23dSSara Sharon (trans->dbg_dest_tlv && !trans->ini_valid) || 30707a14c23dSSara Sharon (trans->ini_valid && trans->num_blocks)) { 3071e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3072e705c121SKalle Valo 3073e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3074e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30757a14c23dSSara Sharon 30767a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3077e705c121SKalle Valo 3078e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 307988964b2eSSara Sharon if (trans->num_blocks) { 3080e705c121SKalle Valo memcpy(fw_mon_data->data, 308188964b2eSSara Sharon trans->fw_mon[0].block, 308288964b2eSSara Sharon trans->fw_mon[0].size); 3083e705c121SKalle Valo 308488964b2eSSara Sharon monitor_len = trans->fw_mon[0].size; 3085e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 30867a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3087e705c121SKalle Valo /* 3088e705c121SKalle Valo * Update pointers to reflect actual values after 3089e705c121SKalle Valo * shifting 3090e705c121SKalle Valo */ 3091fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version) { 3092fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3093fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 3094fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 3095fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3096fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3097fd527eb5SGolan Ben Ami } else { 3098e705c121SKalle Valo base = iwl_read_prph(trans, base) << 3099e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 3100fd527eb5SGolan Ben Ami } 3101fd527eb5SGolan Ben Ami 3102e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3103e705c121SKalle Valo monitor_len / sizeof(u32)); 3104e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 3105e705c121SKalle Valo monitor_len = 3106e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3107e705c121SKalle Valo fw_mon_data, 3108e705c121SKalle Valo monitor_len); 3109e705c121SKalle Valo } else { 3110e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3111e705c121SKalle Valo monitor_len = 0; 3112e705c121SKalle Valo } 3113e705c121SKalle Valo 3114e705c121SKalle Valo len += monitor_len; 3115e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3116e705c121SKalle Valo } 3117e705c121SKalle Valo 3118e705c121SKalle Valo return len; 3119e705c121SKalle Valo } 3120e705c121SKalle Valo 3121da752717SShahar S Matityahu static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, int *len) 3122e705c121SKalle Valo { 312388964b2eSSara Sharon if (trans->num_blocks) { 3124da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3125da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 312688964b2eSSara Sharon trans->fw_mon[0].size; 312788964b2eSSara Sharon return trans->fw_mon[0].size; 3128e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 3129da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3130e705c121SKalle Valo 3131fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version == 1) { 3132fd527eb5SGolan Ben Ami cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3133fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3134fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3135fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 3136fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3137fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3138fd527eb5SGolan Ben Ami 3139fd527eb5SGolan Ben Ami monitor_len = 3140fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3141fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->end_shift; 3142fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3143fd527eb5SGolan Ben Ami } else { 3144e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 3145e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 3146e705c121SKalle Valo 3147e705c121SKalle Valo base = iwl_read_prph(trans, base) << 3148e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 3149e705c121SKalle Valo end = iwl_read_prph(trans, end) << 3150e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 3151e705c121SKalle Valo 3152e705c121SKalle Valo /* Make "end" point to the actual end */ 3153fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 3154fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 3155e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 3156e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 3157e705c121SKalle Valo monitor_len = end - base; 3158fd527eb5SGolan Ben Ami } 3159da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3160da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3161e705c121SKalle Valo monitor_len; 3162da752717SShahar S Matityahu return monitor_len; 3163e705c121SKalle Valo } 3164da752717SShahar S Matityahu return 0; 3165da752717SShahar S Matityahu } 3166da752717SShahar S Matityahu 3167da752717SShahar S Matityahu static struct iwl_trans_dump_data 3168da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 316979f033f6SSara Sharon u32 dump_mask) 3170da752717SShahar S Matityahu { 3171da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3172da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3173da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3174da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3175da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3176da752717SShahar S Matityahu u32 len, num_rbs = 0; 3177da752717SShahar S Matityahu u32 monitor_len; 3178da752717SShahar S Matityahu int i, ptr; 3179da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3180da752717SShahar S Matityahu !trans->cfg->mq_rx_supported && 318179f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 318279f033f6SSara Sharon 318379f033f6SSara Sharon if (!dump_mask) 318479f033f6SSara Sharon return NULL; 3185da752717SShahar S Matityahu 3186da752717SShahar S Matityahu /* transport dump header */ 3187da752717SShahar S Matityahu len = sizeof(*dump_data); 3188da752717SShahar S Matityahu 3189da752717SShahar S Matityahu /* host commands */ 3190da752717SShahar S Matityahu len += sizeof(*data) + 3191da752717SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 3192da752717SShahar S Matityahu 3193da752717SShahar S Matityahu /* FW monitor */ 3194da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3195e705c121SKalle Valo 319679f033f6SSara Sharon if (dump_mask == BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) { 3197e705c121SKalle Valo dump_data = vzalloc(len); 3198e705c121SKalle Valo if (!dump_data) 3199e705c121SKalle Valo return NULL; 3200e705c121SKalle Valo 3201e705c121SKalle Valo data = (void *)dump_data->data; 3202e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3203e705c121SKalle Valo dump_data->len = len; 3204e705c121SKalle Valo 3205e705c121SKalle Valo return dump_data; 3206e705c121SKalle Valo } 3207e705c121SKalle Valo 3208e705c121SKalle Valo /* CSR registers */ 320979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3210e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3211e705c121SKalle Valo 3212e705c121SKalle Valo /* FH registers */ 321379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3214723b45e2SLiad Kaufman if (trans->cfg->gen2) 3215723b45e2SLiad Kaufman len += sizeof(*data) + 3216520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND_GEN2 - 3217520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND_GEN2); 3218723b45e2SLiad Kaufman else 3219723b45e2SLiad Kaufman len += sizeof(*data) + 3220520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3221520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3222520f03eaSShahar S Matityahu } 3223e705c121SKalle Valo 3224e705c121SKalle Valo if (dump_rbs) { 322578485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 322678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3227e705c121SKalle Valo /* RBs */ 32280307c839SGolan Ben Ami num_rbs = 32290307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3230e705c121SKalle Valo & 0x0FFF; 323178485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3232e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3233e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3234e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3235e705c121SKalle Valo } 3236e705c121SKalle Valo 32375538409bSLiad Kaufman /* Paged memory for gen2 HW */ 323879f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 32395538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 32405538409bSLiad Kaufman len += sizeof(*data) + 32415538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 32425538409bSLiad Kaufman trans_pcie->init_dram.paging[i].size; 32435538409bSLiad Kaufman 3244e705c121SKalle Valo dump_data = vzalloc(len); 3245e705c121SKalle Valo if (!dump_data) 3246e705c121SKalle Valo return NULL; 3247e705c121SKalle Valo 3248e705c121SKalle Valo len = 0; 3249e705c121SKalle Valo data = (void *)dump_data->data; 3250520f03eaSShahar S Matityahu 325179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { 3252520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3253520f03eaSShahar S Matityahu 3254e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3255e705c121SKalle Valo txcmd = (void *)data->data; 3256e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3257bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3258bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32594ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3260e705c121SKalle Valo u32 caplen, cmdlen; 3261e705c121SKalle Valo 3262520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3263520f03eaSShahar S Matityahu cmdq->tfds + 3264520f03eaSShahar S Matityahu tfd_size * ptr); 3265e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3266e705c121SKalle Valo 3267e705c121SKalle Valo if (cmdlen) { 3268e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3269e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3270e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3271520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3272520f03eaSShahar S Matityahu caplen); 3273e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3274e705c121SKalle Valo } 3275e705c121SKalle Valo 32767b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3277e705c121SKalle Valo } 3278e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3279e705c121SKalle Valo 3280e705c121SKalle Valo data->len = cpu_to_le32(len); 3281e705c121SKalle Valo len += sizeof(*data); 3282e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3283520f03eaSShahar S Matityahu } 3284e705c121SKalle Valo 328579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3286e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 328779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3288e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3289e705c121SKalle Valo if (dump_rbs) 3290e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3291e705c121SKalle Valo 32925538409bSLiad Kaufman /* Paged memory for gen2 HW */ 329379f033f6SSara Sharon if (trans->cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 32945538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 32955538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 32965538409bSLiad Kaufman dma_addr_t addr = 32975538409bSLiad Kaufman trans_pcie->init_dram.paging[i].physical; 32985538409bSLiad Kaufman u32 page_len = trans_pcie->init_dram.paging[i].size; 32995538409bSLiad Kaufman 33005538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 33015538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 33025538409bSLiad Kaufman paging = (void *)data->data; 33035538409bSLiad Kaufman paging->index = cpu_to_le32(i); 33045538409bSLiad Kaufman dma_sync_single_for_cpu(trans->dev, addr, page_len, 33055538409bSLiad Kaufman DMA_BIDIRECTIONAL); 33065538409bSLiad Kaufman memcpy(paging->data, 33075538409bSLiad Kaufman trans_pcie->init_dram.paging[i].block, page_len); 33085538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33095538409bSLiad Kaufman 33105538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33115538409bSLiad Kaufman } 33125538409bSLiad Kaufman } 331379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3314e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3315e705c121SKalle Valo 3316e705c121SKalle Valo dump_data->len = len; 3317e705c121SKalle Valo 3318e705c121SKalle Valo return dump_data; 3319e705c121SKalle Valo } 3320e705c121SKalle Valo 33214cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 33224cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 33234cbb8e50SLuciano Coelho { 3324e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3325e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 33264cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 33274cbb8e50SLuciano Coelho 33284cbb8e50SLuciano Coelho return 0; 33294cbb8e50SLuciano Coelho } 33304cbb8e50SLuciano Coelho 33314cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 33324cbb8e50SLuciano Coelho { 3333e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3334e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 33354cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 33364cbb8e50SLuciano Coelho } 33374cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 33384cbb8e50SLuciano Coelho 3339623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3340623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3341623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3342623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3343623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3344623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3345623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3346623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3347623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3348623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3349623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3350870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3351623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3352623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3353623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3354623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3355623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3356623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3357623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3358623e7766SSara Sharon .d3_resume = iwl_trans_pcie_d3_resume 3359623e7766SSara Sharon 3360623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3361623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3362623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3363623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3364623e7766SSara Sharon #else 3365623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3366623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3367623e7766SSara Sharon 3368e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3369623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3370623e7766SSara Sharon IWL_TRANS_PM_OPS 3371e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3372e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3373e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3374e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3375e705c121SKalle Valo 3376e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3377e705c121SKalle Valo 3378e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3379e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3380e705c121SKalle Valo 3381e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3382e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3383e705c121SKalle Valo 338442db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 338542db09c1SLiad Kaufman 3386d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3387d6d517b7SSara Sharon 3388e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 33890cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3390f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3391f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3392f7805b33SLior Cohen #endif 3393623e7766SSara Sharon }; 3394e705c121SKalle Valo 3395623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3396623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3397623e7766SSara Sharon IWL_TRANS_PM_OPS 3398623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3399eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3400eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 340177c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3402e705c121SKalle Valo 3403ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3404e705c121SKalle Valo 3405ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3406623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3407623e7766SSara Sharon 34086b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 34096b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3410d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 341192536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3412f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3413f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3414f7805b33SLior Cohen #endif 3415e705c121SKalle Valo }; 3416e705c121SKalle Valo 3417e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3418e705c121SKalle Valo const struct pci_device_id *ent, 3419e705c121SKalle Valo const struct iwl_cfg *cfg) 3420e705c121SKalle Valo { 3421e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3422e705c121SKalle Valo struct iwl_trans *trans; 342396a6497bSSara Sharon int ret, addr_size; 3424e705c121SKalle Valo 34255a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 34265a41a86cSSharon Dvir if (ret) 34275a41a86cSSharon Dvir return ERR_PTR(ret); 34285a41a86cSSharon Dvir 3429623e7766SSara Sharon if (cfg->gen2) 3430623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3431623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3432623e7766SSara Sharon else 3433e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 34341ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3435e705c121SKalle Valo if (!trans) 3436e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3437e705c121SKalle Valo 3438e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3439e705c121SKalle Valo 3440e705c121SKalle Valo trans_pcie->trans = trans; 3441326477e4SJohannes Berg trans_pcie->opmode_down = true; 3442e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3443e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3444e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3445e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 34466eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 34476eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 34486eb5e529SEmmanuel Grumbach ret = -ENOMEM; 34496eb5e529SEmmanuel Grumbach goto out_no_pci; 34506eb5e529SEmmanuel Grumbach } 3451e705c121SKalle Valo 3452e705c121SKalle Valo 3453e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3454e705c121SKalle Valo /* 3455e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3456e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3457e705c121SKalle Valo * lot of power. 3458e705c121SKalle Valo */ 3459e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3460e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3461e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3462e705c121SKalle Valo } 3463e705c121SKalle Valo 34649416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34659416560eSGolan Ben Ami 34666983ba69SSara Sharon if (cfg->use_tfh) { 34672c6262b7SSara Sharon addr_size = 64; 34683cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 34698352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 34706983ba69SSara Sharon } else { 34712c6262b7SSara Sharon addr_size = 36; 34723cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 34736983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 34746983ba69SSara Sharon } 34753cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 34763cd1980bSSara Sharon 3477e705c121SKalle Valo pci_set_master(pdev); 3478e705c121SKalle Valo 347996a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3480e705c121SKalle Valo if (!ret) 348196a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 348296a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3483e705c121SKalle Valo if (ret) { 3484e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3485e705c121SKalle Valo if (!ret) 3486e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3487e705c121SKalle Valo DMA_BIT_MASK(32)); 3488e705c121SKalle Valo /* both attempts failed: */ 3489e705c121SKalle Valo if (ret) { 3490e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34915a41a86cSSharon Dvir goto out_no_pci; 3492e705c121SKalle Valo } 3493e705c121SKalle Valo } 3494e705c121SKalle Valo 34955a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3496e705c121SKalle Valo if (ret) { 34975a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34985a41a86cSSharon Dvir goto out_no_pci; 3499e705c121SKalle Valo } 3500e705c121SKalle Valo 35015a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3502e705c121SKalle Valo if (!trans_pcie->hw_base) { 35035a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3504e705c121SKalle Valo ret = -ENODEV; 35055a41a86cSSharon Dvir goto out_no_pci; 3506e705c121SKalle Valo } 3507e705c121SKalle Valo 3508e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3509e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3510e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3511e705c121SKalle Valo 3512e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3513e705c121SKalle Valo iwl_disable_interrupts(trans); 3514e705c121SKalle Valo 3515e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35169a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35179a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35189a098a89SRajat Jain ret = -EIO; 35199a098a89SRajat Jain goto out_no_pci; 35209a098a89SRajat Jain } 35219a098a89SRajat Jain 3522e705c121SKalle Valo /* 3523e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3524e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3525e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3526e705c121SKalle Valo * in the old format. 3527e705c121SKalle Valo */ 35286e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3529e705c121SKalle Valo unsigned long flags; 3530e705c121SKalle Valo 3531e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3532e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3533e705c121SKalle Valo 3534e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3535e705c121SKalle Valo if (ret) { 3536e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 35375a41a86cSSharon Dvir goto out_no_pci; 3538e705c121SKalle Valo } 3539e705c121SKalle Valo 3540e705c121SKalle Valo /* 3541e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3542e705c121SKalle Valo * id located at the AUX bus MISC address space. 3543e705c121SKalle Valo */ 3544e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 3545a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 3546e705c121SKalle Valo udelay(2); 3547e705c121SKalle Valo 3548e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3549a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3550a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3551e705c121SKalle Valo 25000); 3552e705c121SKalle Valo if (ret < 0) { 3553e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 35545a41a86cSSharon Dvir goto out_no_pci; 3555e705c121SKalle Valo } 3556e705c121SKalle Valo 355723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3558e705c121SKalle Valo u32 hw_step; 3559e705c121SKalle Valo 356014ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3561e705c121SKalle Valo hw_step |= ENABLE_WFPM; 356214ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 356314ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3564e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3565e705c121SKalle Valo if (hw_step == 0x3) 3566e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3567e705c121SKalle Valo (SILICON_C_STEP << 2); 3568e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3569e705c121SKalle Valo } 3570e705c121SKalle Valo } 3571e705c121SKalle Valo 357299be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 357399be6166SLuca Coelho 3574c00ee467SJohannes Berg /* 3575c00ee467SJohannes Berg * 9000-series integrated A-step has a problem with suspend/resume 3576c00ee467SJohannes Berg * and sometimes even causes the whole platform to get stuck. This 3577c00ee467SJohannes Berg * workaround makes the hardware not go into the problematic state. 3578c00ee467SJohannes Berg */ 3579c00ee467SJohannes Berg if (trans->cfg->integrated && 3580c00ee467SJohannes Berg trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3581c00ee467SJohannes Berg CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3582c00ee467SJohannes Berg iwl_set_bit(trans, CSR_HOST_CHICKEN, 3583c00ee467SJohannes Berg CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3584c00ee467SJohannes Berg 3585f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 35861afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 358733708052SLuca Coelho 3588a98e2802SIhab Zhaika if (cfg == &iwl22560_2ax_cfg_hr) { 358933708052SLuca Coelho if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 359033708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3591a98e2802SIhab Zhaika trans->cfg = &iwl22560_2ax_cfg_hr; 3592b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3593b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) { 3594b1bbc1a6SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_jf; 3595b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 3596b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) { 3597b1bbc1a6SLuca Coelho IWL_ERR(trans, "RF ID HRCDB is not supported\n"); 3598b1bbc1a6SLuca Coelho ret = -EINVAL; 3599b1bbc1a6SLuca Coelho goto out_no_pci; 3600b1bbc1a6SLuca Coelho } else { 3601b1bbc1a6SLuca Coelho IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n", 3602b1bbc1a6SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id)); 3603b1bbc1a6SLuca Coelho ret = -EINVAL; 3604b1bbc1a6SLuca Coelho goto out_no_pci; 3605b1bbc1a6SLuca Coelho } 3606b1bbc1a6SLuca Coelho } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 36078093bb6dSLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) && 360899be6166SLuca Coelho (trans->cfg != &iwl22260_2ax_cfg || 360999be6166SLuca Coelho trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) { 3610f6586b69STzipi Peres u32 hw_status; 3611f6586b69STzipi Peres 3612f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 361333708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 361433708052SLuca Coelho /* 361533708052SLuca Coelho * b step fw is the same for physical card and fpga 361633708052SLuca Coelho */ 361733708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 361833708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 361933708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 362033708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 362133708052SLuca Coelho } else { 362233708052SLuca Coelho /* 362333708052SLuca Coelho * a step no FPGA 362433708052SLuca Coelho */ 36252f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3626f6586b69STzipi Peres } 362733708052SLuca Coelho } 3628f6586b69STzipi Peres #endif 36291afb0ae4SHaim Dreyfuss 36302e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3631e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3632e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3633e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3634e705c121SKalle Valo 3635e705c121SKalle Valo /* Initialize the wait queue for commands */ 3636e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3637e705c121SKalle Valo 36384cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 36394cbb8e50SLuciano Coelho 36402e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36412388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36422388bd7bSDan Carpenter if (ret) 36435a41a86cSSharon Dvir goto out_no_pci; 36442e5d4a8fSHaim Dreyfuss } else { 3645e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3646e705c121SKalle Valo if (ret) 36475a41a86cSSharon Dvir goto out_no_pci; 3648e705c121SKalle Valo 36495a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36505a41a86cSSharon Dvir iwl_pcie_isr, 3651e705c121SKalle Valo iwl_pcie_irq_handler, 3652e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3653e705c121SKalle Valo if (ret) { 3654e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3655e705c121SKalle Valo goto out_free_ict; 3656e705c121SKalle Valo } 3657e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 36582e5d4a8fSHaim Dreyfuss } 3659e705c121SKalle Valo 366010a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 366110a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 366210a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 366310a54d81SLuca Coelho 3664b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3665b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3666b3ff1270SLuca Coelho #else 3667b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3668b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3669b3ff1270SLuca Coelho 3670f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3671f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3672f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3673f7805b33SLior Cohen #endif 3674f7805b33SLior Cohen 3675e705c121SKalle Valo return trans; 3676e705c121SKalle Valo 3677e705c121SKalle Valo out_free_ict: 3678e705c121SKalle Valo iwl_pcie_free_ict(trans); 3679e705c121SKalle Valo out_no_pci: 36806eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3681e705c121SKalle Valo iwl_trans_free(trans); 3682e705c121SKalle Valo return ERR_PTR(ret); 3683e705c121SKalle Valo } 3684