1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * You should have received a copy of the GNU General Public License 23e705c121SKalle Valo * along with this program; if not, write to the Free Software 24e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 25e705c121SKalle Valo * USA 26e705c121SKalle Valo * 27e705c121SKalle Valo * The full GNU General Public License is included in this distribution 28e705c121SKalle Valo * in the file called COPYING. 29e705c121SKalle Valo * 30e705c121SKalle Valo * Contact Information: 31cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 32e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 33e705c121SKalle Valo * 34e705c121SKalle Valo * BSD LICENSE 35e705c121SKalle Valo * 36e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 37e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 38afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 39a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 40e705c121SKalle Valo * All rights reserved. 41e705c121SKalle Valo * 42e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 43e705c121SKalle Valo * modification, are permitted provided that the following conditions 44e705c121SKalle Valo * are met: 45e705c121SKalle Valo * 46e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 47e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 48e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 49e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 50e705c121SKalle Valo * the documentation and/or other materials provided with the 51e705c121SKalle Valo * distribution. 52e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 53e705c121SKalle Valo * contributors may be used to endorse or promote products derived 54e705c121SKalle Valo * from this software without specific prior written permission. 55e705c121SKalle Valo * 56e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 57e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 58e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 59e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 60e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 61e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 62e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 66e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67e705c121SKalle Valo * 68e705c121SKalle Valo *****************************************************************************/ 69e705c121SKalle Valo #include <linux/pci.h> 70e705c121SKalle Valo #include <linux/pci-aspm.h> 71e705c121SKalle Valo #include <linux/interrupt.h> 72e705c121SKalle Valo #include <linux/debugfs.h> 73e705c121SKalle Valo #include <linux/sched.h> 74e705c121SKalle Valo #include <linux/bitops.h> 75e705c121SKalle Valo #include <linux/gfp.h> 76e705c121SKalle Valo #include <linux/vmalloc.h> 77b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 7849564a80SLuca Coelho #include <linux/module.h> 79e705c121SKalle Valo 80e705c121SKalle Valo #include "iwl-drv.h" 81e705c121SKalle Valo #include "iwl-trans.h" 82e705c121SKalle Valo #include "iwl-csr.h" 83e705c121SKalle Valo #include "iwl-prph.h" 84e705c121SKalle Valo #include "iwl-scd.h" 85e705c121SKalle Valo #include "iwl-agn-hw.h" 86d962f9b1SJohannes Berg #include "fw/error-dump.h" 87e705c121SKalle Valo #include "internal.h" 88e705c121SKalle Valo #include "iwl-fh.h" 89e705c121SKalle Valo 90e705c121SKalle Valo /* extended range in FW SRAM */ 91e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 92e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 93e705c121SKalle Valo 94fb12777aSKirtika Ruchandani static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 95a6d24fadSRajat Jain { 96a6d24fadSRajat Jain #define PCI_DUMP_SIZE 64 97a6d24fadSRajat Jain #define PREFIX_LEN 32 98a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 99a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 100a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 101a6d24fadSRajat Jain char *prefix; 102a6d24fadSRajat Jain 103a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 104a6d24fadSRajat Jain return; 105a6d24fadSRajat Jain 106a6d24fadSRajat Jain /* Should be a multiple of 4 */ 107a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 108a6d24fadSRajat Jain /* Alloc a max size buffer */ 109a6d24fadSRajat Jain if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 110a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 111a6d24fadSRajat Jain else 112a6d24fadSRajat Jain alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 113a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 114a6d24fadSRajat Jain if (!buf) 115a6d24fadSRajat Jain return; 116a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 117a6d24fadSRajat Jain 118a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 119a6d24fadSRajat Jain 120a6d24fadSRajat Jain /* Print wifi device registers */ 121a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 122a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 123a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 124a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 125a6d24fadSRajat Jain goto err_read; 126a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 127a6d24fadSRajat Jain 128a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 129a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 130a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 131a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 132a6d24fadSRajat Jain 133a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 134a6d24fadSRajat Jain if (pos) { 135a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 136a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 137a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 138a6d24fadSRajat Jain goto err_read; 139a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 140a6d24fadSRajat Jain 32, 4, buf, i, 0); 141a6d24fadSRajat Jain } 142a6d24fadSRajat Jain 143a6d24fadSRajat Jain /* Print parent device registers next */ 144a6d24fadSRajat Jain if (!pdev->bus->self) 145a6d24fadSRajat Jain goto out; 146a6d24fadSRajat Jain 147a6d24fadSRajat Jain pdev = pdev->bus->self; 148a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 149a6d24fadSRajat Jain 150a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 151a6d24fadSRajat Jain pci_name(pdev)); 152a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 153a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 154a6d24fadSRajat Jain goto err_read; 155a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 156a6d24fadSRajat Jain 157a6d24fadSRajat Jain /* Print root port AER registers */ 158a6d24fadSRajat Jain pos = 0; 159a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 160a6d24fadSRajat Jain if (pdev) 161a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 162a6d24fadSRajat Jain if (pos) { 163a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 164a6d24fadSRajat Jain pci_name(pdev)); 165a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 166a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 167a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 168a6d24fadSRajat Jain goto err_read; 169a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 170a6d24fadSRajat Jain 4, buf, i, 0); 171a6d24fadSRajat Jain } 172f3402d6dSSara Sharon goto out; 173a6d24fadSRajat Jain 174a6d24fadSRajat Jain err_read: 175a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 176a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 177a6d24fadSRajat Jain out: 178a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 179a6d24fadSRajat Jain kfree(buf); 180a6d24fadSRajat Jain } 181a6d24fadSRajat Jain 182870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 183870c2a11SGolan Ben Ami { 184870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 185a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 186a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 187870c2a11SGolan Ben Ami usleep_range(5000, 6000); 188870c2a11SGolan Ben Ami } 189870c2a11SGolan Ben Ami 190e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 191e705c121SKalle Valo { 192e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 193e705c121SKalle Valo 194e705c121SKalle Valo if (!trans_pcie->fw_mon_page) 195e705c121SKalle Valo return; 196e705c121SKalle Valo 197e705c121SKalle Valo dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 198e705c121SKalle Valo trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 199e705c121SKalle Valo __free_pages(trans_pcie->fw_mon_page, 200e705c121SKalle Valo get_order(trans_pcie->fw_mon_size)); 201e705c121SKalle Valo trans_pcie->fw_mon_page = NULL; 202e705c121SKalle Valo trans_pcie->fw_mon_phys = 0; 203e705c121SKalle Valo trans_pcie->fw_mon_size = 0; 204e705c121SKalle Valo } 205e705c121SKalle Valo 2069f358c17SGolan Ben Ami void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 207e705c121SKalle Valo { 208e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 209e705c121SKalle Valo struct page *page = NULL; 210e705c121SKalle Valo dma_addr_t phys; 211e705c121SKalle Valo u32 size = 0; 212e705c121SKalle Valo u8 power; 213e705c121SKalle Valo 214e705c121SKalle Valo if (!max_power) { 215e705c121SKalle Valo /* default max_power is maximum */ 216e705c121SKalle Valo max_power = 26; 217e705c121SKalle Valo } else { 218e705c121SKalle Valo max_power += 11; 219e705c121SKalle Valo } 220e705c121SKalle Valo 221e705c121SKalle Valo if (WARN(max_power > 26, 222e705c121SKalle Valo "External buffer size for monitor is too big %d, check the FW TLV\n", 223e705c121SKalle Valo max_power)) 224e705c121SKalle Valo return; 225e705c121SKalle Valo 226e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 227e705c121SKalle Valo dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 228e705c121SKalle Valo trans_pcie->fw_mon_size, 229e705c121SKalle Valo DMA_FROM_DEVICE); 230e705c121SKalle Valo return; 231e705c121SKalle Valo } 232e705c121SKalle Valo 233e705c121SKalle Valo phys = 0; 234e705c121SKalle Valo for (power = max_power; power >= 11; power--) { 235e705c121SKalle Valo int order; 236e705c121SKalle Valo 237e705c121SKalle Valo size = BIT(power); 238e705c121SKalle Valo order = get_order(size); 239e705c121SKalle Valo page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 240e705c121SKalle Valo order); 241e705c121SKalle Valo if (!page) 242e705c121SKalle Valo continue; 243e705c121SKalle Valo 244e705c121SKalle Valo phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 245e705c121SKalle Valo DMA_FROM_DEVICE); 246e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys)) { 247e705c121SKalle Valo __free_pages(page, order); 248e705c121SKalle Valo page = NULL; 249e705c121SKalle Valo continue; 250e705c121SKalle Valo } 251e705c121SKalle Valo IWL_INFO(trans, 252e705c121SKalle Valo "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 253e705c121SKalle Valo size, order); 254e705c121SKalle Valo break; 255e705c121SKalle Valo } 256e705c121SKalle Valo 257e705c121SKalle Valo if (WARN_ON_ONCE(!page)) 258e705c121SKalle Valo return; 259e705c121SKalle Valo 260e705c121SKalle Valo if (power != max_power) 261e705c121SKalle Valo IWL_ERR(trans, 262e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 263e705c121SKalle Valo (unsigned long)BIT(power - 10), 264e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 265e705c121SKalle Valo 266e705c121SKalle Valo trans_pcie->fw_mon_page = page; 267e705c121SKalle Valo trans_pcie->fw_mon_phys = phys; 268e705c121SKalle Valo trans_pcie->fw_mon_size = size; 269e705c121SKalle Valo } 270e705c121SKalle Valo 271e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 272e705c121SKalle Valo { 273e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 274e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 275e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 276e705c121SKalle Valo } 277e705c121SKalle Valo 278e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 279e705c121SKalle Valo { 280e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 281e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 282e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 283e705c121SKalle Valo } 284e705c121SKalle Valo 285e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 286e705c121SKalle Valo { 287e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 288e705c121SKalle Valo return; 289e705c121SKalle Valo 290e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 291e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 292e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 293e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 294e705c121SKalle Valo else 295e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 296e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 297e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 298e705c121SKalle Valo } 299e705c121SKalle Valo 300e705c121SKalle Valo /* PCI registers */ 301e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 302e705c121SKalle Valo 303eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 304e705c121SKalle Valo { 305e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 306e705c121SKalle Valo u16 lctl; 307e705c121SKalle Valo u16 cap; 308e705c121SKalle Valo 309e705c121SKalle Valo /* 310e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 311e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 312e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 313e705c121SKalle Valo * costs negligible amount of power savings. 314e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 315e705c121SKalle Valo * power savings, even without L1. 316e705c121SKalle Valo */ 317e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 318e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 319e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 320e705c121SKalle Valo else 321e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 322e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 323e705c121SKalle Valo 324e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 325e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 326d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 327e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 328e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 329e705c121SKalle Valo } 330e705c121SKalle Valo 331e705c121SKalle Valo /* 332e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 333e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 334e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 335e705c121SKalle Valo */ 336e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 337e705c121SKalle Valo { 33852b6e168SEmmanuel Grumbach int ret; 33952b6e168SEmmanuel Grumbach 340e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 341e705c121SKalle Valo 342e705c121SKalle Valo /* 343e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 344e705c121SKalle Valo * bits already set by default after reset. 345e705c121SKalle Valo */ 346e705c121SKalle Valo 347e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3486e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 349e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 350e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 351e705c121SKalle Valo 352e705c121SKalle Valo /* 353e705c121SKalle Valo * Disable L0s without affecting L1; 354e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 355e705c121SKalle Valo */ 356e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 357e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 358e705c121SKalle Valo 359e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 360e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 361e705c121SKalle Valo 362e705c121SKalle Valo /* 363e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 364e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 365e705c121SKalle Valo */ 366e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 367e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 368e705c121SKalle Valo 369e705c121SKalle Valo iwl_pcie_apm_config(trans); 370e705c121SKalle Valo 371e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 37277d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 37377d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 374e705c121SKalle Valo 375e705c121SKalle Valo /* 376e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 377e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 378e705c121SKalle Valo */ 379a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 380a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 381e705c121SKalle Valo 382e705c121SKalle Valo /* 383e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 384e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 385e705c121SKalle Valo * and accesses to uCode SRAM. 386e705c121SKalle Valo */ 387e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 388a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 389a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 390a8cbb46fSGolan Ben Ami 25000); 391e705c121SKalle Valo if (ret < 0) { 39252b6e168SEmmanuel Grumbach IWL_ERR(trans, "Failed to init the card\n"); 39352b6e168SEmmanuel Grumbach return ret; 394e705c121SKalle Valo } 395e705c121SKalle Valo 396e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 397e705c121SKalle Valo /* 398e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 399e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 400e705c121SKalle Valo * not related to host_interrupt_operation_mode. 401e705c121SKalle Valo * 402e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 403e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 404e705c121SKalle Valo * that we wake up from L1 on time. 405e705c121SKalle Valo * 406e705c121SKalle Valo * This looks weird: read twice the same register, discard the 407e705c121SKalle Valo * value, set a bit, and yet again, read that same register 408e705c121SKalle Valo * just to discard the value. But that's the way the hardware 409e705c121SKalle Valo * seems to like it. 410e705c121SKalle Valo */ 411e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 412e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 413e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 414e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 415e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 416e705c121SKalle Valo } 417e705c121SKalle Valo 418e705c121SKalle Valo /* 419e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 420e705c121SKalle Valo * 421e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 422e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 423e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 424e705c121SKalle Valo */ 425e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 426e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 427e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 428e705c121SKalle Valo udelay(20); 429e705c121SKalle Valo 430e705c121SKalle Valo /* Disable L1-Active */ 431e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 432e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 433e705c121SKalle Valo 434e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 435e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 436e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 437e705c121SKalle Valo } 438e705c121SKalle Valo 439e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 440e705c121SKalle Valo 44152b6e168SEmmanuel Grumbach return 0; 442e705c121SKalle Valo } 443e705c121SKalle Valo 444e705c121SKalle Valo /* 445e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 446e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 447e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 448e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 449e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 450e705c121SKalle Valo */ 451e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 452e705c121SKalle Valo { 453e705c121SKalle Valo int ret; 454e705c121SKalle Valo u32 apmg_gp1_reg; 455e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 456e705c121SKalle Valo u32 dl_cfg_reg; 457e705c121SKalle Valo 458e705c121SKalle Valo /* Force XTAL ON */ 459e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 460e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 461e705c121SKalle Valo 462870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 463e705c121SKalle Valo 464e705c121SKalle Valo /* 465e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 466e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 467e705c121SKalle Valo */ 468a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 469a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 470e705c121SKalle Valo 471e705c121SKalle Valo /* 472e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 473e705c121SKalle Valo * device-internal resources is possible. 474e705c121SKalle Valo */ 475e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 476a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 477a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 478e705c121SKalle Valo 25000); 479e705c121SKalle Valo if (WARN_ON(ret < 0)) { 480e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 481e705c121SKalle Valo /* Release XTAL ON request */ 482e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 483e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 484e705c121SKalle Valo return; 485e705c121SKalle Valo } 486e705c121SKalle Valo 487e705c121SKalle Valo /* 488e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 489e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 490e705c121SKalle Valo */ 491e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 492e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 493e705c121SKalle Valo 494e705c121SKalle Valo /* 495e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 496e705c121SKalle Valo * caused by APMG idle state. 497e705c121SKalle Valo */ 498e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 499e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 500e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 501e705c121SKalle Valo apmg_xtal_cfg_reg | 502e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 503e705c121SKalle Valo 504870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 505e705c121SKalle Valo 506e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 507e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 508e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 509e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 510e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 511e705c121SKalle Valo 512e705c121SKalle Valo /* Clear delay line clock power up */ 513e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 514e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 515e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 516e705c121SKalle Valo 517e705c121SKalle Valo /* 518e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 519e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 520e705c121SKalle Valo */ 521e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 522e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 523e705c121SKalle Valo 524e705c121SKalle Valo /* 525e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 526e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 527e705c121SKalle Valo */ 528e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 529a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 530e705c121SKalle Valo 531e705c121SKalle Valo /* Activates XTAL resources monitor */ 532e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 533e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 534e705c121SKalle Valo 535e705c121SKalle Valo /* Release XTAL ON request */ 536e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 537e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 538e705c121SKalle Valo udelay(10); 539e705c121SKalle Valo 540e705c121SKalle Valo /* Release APMG XTAL */ 541e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 542e705c121SKalle Valo apmg_xtal_cfg_reg & 543e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 544e705c121SKalle Valo } 545e705c121SKalle Valo 546e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 547e705c121SKalle Valo { 548e8c8935eSJohannes Berg int ret; 549e705c121SKalle Valo 550e705c121SKalle Valo /* stop device's busmaster DMA activity */ 551a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 552a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 553e705c121SKalle Valo 554a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 555a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 556a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 557e705c121SKalle Valo if (ret < 0) 558e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 559e705c121SKalle Valo 560e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 561e705c121SKalle Valo } 562e705c121SKalle Valo 563e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 564e705c121SKalle Valo { 565e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 566e705c121SKalle Valo 567e705c121SKalle Valo if (op_mode_leave) { 568e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 569e705c121SKalle Valo iwl_pcie_apm_init(trans); 570e705c121SKalle Valo 571e705c121SKalle Valo /* inform ME that we are leaving */ 572e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 573e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 574e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5756e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 576e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 577e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 578e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 579e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 580e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 581e705c121SKalle Valo mdelay(1); 582e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 583e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 584e705c121SKalle Valo } 585e705c121SKalle Valo mdelay(5); 586e705c121SKalle Valo } 587e705c121SKalle Valo 588e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 589e705c121SKalle Valo 590e705c121SKalle Valo /* Stop device's DMA activity */ 591e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 592e705c121SKalle Valo 593e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 594e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 595e705c121SKalle Valo return; 596e705c121SKalle Valo } 597e705c121SKalle Valo 598870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 599e705c121SKalle Valo 600e705c121SKalle Valo /* 601e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 602e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 603e705c121SKalle Valo */ 604e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 605a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 606e705c121SKalle Valo } 607e705c121SKalle Valo 608e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 609e705c121SKalle Valo { 610e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 61152b6e168SEmmanuel Grumbach int ret; 612e705c121SKalle Valo 613e705c121SKalle Valo /* nic_init */ 614e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 61552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 616e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 617e705c121SKalle Valo 61852b6e168SEmmanuel Grumbach if (ret) 61952b6e168SEmmanuel Grumbach return ret; 62052b6e168SEmmanuel Grumbach 621e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 622e705c121SKalle Valo 623e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 624e705c121SKalle Valo 625e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 626e705c121SKalle Valo iwl_pcie_rx_init(trans); 627e705c121SKalle Valo 628e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 629e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 630e705c121SKalle Valo return -ENOMEM; 631e705c121SKalle Valo 632e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 633e705c121SKalle Valo /* enable shadow regs in HW */ 634e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 635e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 636e705c121SKalle Valo } 637e705c121SKalle Valo 638e705c121SKalle Valo return 0; 639e705c121SKalle Valo } 640e705c121SKalle Valo 641e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 642e705c121SKalle Valo 643e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 644e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 645e705c121SKalle Valo { 646e705c121SKalle Valo int ret; 647e705c121SKalle Valo 648e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 649e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 650e705c121SKalle Valo 651e705c121SKalle Valo /* See if we got it */ 652e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 653e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 654e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 655e705c121SKalle Valo HW_READY_TIMEOUT); 656e705c121SKalle Valo 657e705c121SKalle Valo if (ret >= 0) 658e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 659e705c121SKalle Valo 660e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 661e705c121SKalle Valo return ret; 662e705c121SKalle Valo } 663e705c121SKalle Valo 664e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 665eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 666e705c121SKalle Valo { 667e705c121SKalle Valo int ret; 668e705c121SKalle Valo int t = 0; 669e705c121SKalle Valo int iter; 670e705c121SKalle Valo 671e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 672e705c121SKalle Valo 673e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 674e705c121SKalle Valo /* If the card is ready, exit 0 */ 675e705c121SKalle Valo if (ret >= 0) 676e705c121SKalle Valo return 0; 677e705c121SKalle Valo 678e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 679e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 680192185d6SJohannes Berg usleep_range(1000, 2000); 681e705c121SKalle Valo 682e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 683e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 684e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 685e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 686e705c121SKalle Valo 687e705c121SKalle Valo do { 688e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 689e705c121SKalle Valo if (ret >= 0) 690e705c121SKalle Valo return 0; 691e705c121SKalle Valo 692e705c121SKalle Valo usleep_range(200, 1000); 693e705c121SKalle Valo t += 200; 694e705c121SKalle Valo } while (t < 150000); 695e705c121SKalle Valo msleep(25); 696e705c121SKalle Valo } 697e705c121SKalle Valo 698e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 699e705c121SKalle Valo 700e705c121SKalle Valo return ret; 701e705c121SKalle Valo } 702e705c121SKalle Valo 703e705c121SKalle Valo /* 704e705c121SKalle Valo * ucode 705e705c121SKalle Valo */ 706564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 707564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 708564cdce7SSara Sharon u32 byte_cnt) 709e705c121SKalle Valo { 710bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 711e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 712e705c121SKalle Valo 713bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 714e705c121SKalle Valo dst_addr); 715e705c121SKalle Valo 716bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 717e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 718e705c121SKalle Valo 719bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 720e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 721e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 722e705c121SKalle Valo 723bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 724bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 725bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 726e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 727e705c121SKalle Valo 728bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 729e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 730e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 731e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 732564cdce7SSara Sharon } 733e705c121SKalle Valo 734564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 735564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 736564cdce7SSara Sharon u32 byte_cnt) 737564cdce7SSara Sharon { 738564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 739564cdce7SSara Sharon unsigned long flags; 740564cdce7SSara Sharon int ret; 741564cdce7SSara Sharon 742564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 743564cdce7SSara Sharon 744564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 745564cdce7SSara Sharon return -EIO; 746564cdce7SSara Sharon 747564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 748564cdce7SSara Sharon byte_cnt); 749bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 750bac842daSEmmanuel Grumbach 751e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 752e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 753e705c121SKalle Valo if (!ret) { 754e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 755fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 756e705c121SKalle Valo return -ETIMEDOUT; 757e705c121SKalle Valo } 758e705c121SKalle Valo 759e705c121SKalle Valo return 0; 760e705c121SKalle Valo } 761e705c121SKalle Valo 762e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 763e705c121SKalle Valo const struct fw_desc *section) 764e705c121SKalle Valo { 765e705c121SKalle Valo u8 *v_addr; 766e705c121SKalle Valo dma_addr_t p_addr; 767e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 768e705c121SKalle Valo int ret = 0; 769e705c121SKalle Valo 770e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 771e705c121SKalle Valo section_num); 772e705c121SKalle Valo 773e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 774e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 775e705c121SKalle Valo if (!v_addr) { 776e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 777e705c121SKalle Valo chunk_sz = PAGE_SIZE; 778e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 779e705c121SKalle Valo &p_addr, GFP_KERNEL); 780e705c121SKalle Valo if (!v_addr) 781e705c121SKalle Valo return -ENOMEM; 782e705c121SKalle Valo } 783e705c121SKalle Valo 784e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 785e705c121SKalle Valo u32 copy_size, dst_addr; 786e705c121SKalle Valo bool extended_addr = false; 787e705c121SKalle Valo 788e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 789e705c121SKalle Valo dst_addr = section->offset + offset; 790e705c121SKalle Valo 791e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 792e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 793e705c121SKalle Valo extended_addr = true; 794e705c121SKalle Valo 795e705c121SKalle Valo if (extended_addr) 796e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 797e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 798e705c121SKalle Valo 799e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 800e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 801e705c121SKalle Valo copy_size); 802e705c121SKalle Valo 803e705c121SKalle Valo if (extended_addr) 804e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 805e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 806e705c121SKalle Valo 807e705c121SKalle Valo if (ret) { 808e705c121SKalle Valo IWL_ERR(trans, 809e705c121SKalle Valo "Could not load the [%d] uCode section\n", 810e705c121SKalle Valo section_num); 811e705c121SKalle Valo break; 812e705c121SKalle Valo } 813e705c121SKalle Valo } 814e705c121SKalle Valo 815e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 816e705c121SKalle Valo return ret; 817e705c121SKalle Valo } 818e705c121SKalle Valo 819e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 820e705c121SKalle Valo const struct fw_img *image, 821e705c121SKalle Valo int cpu, 822e705c121SKalle Valo int *first_ucode_section) 823e705c121SKalle Valo { 824e705c121SKalle Valo int shift_param; 825e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 826e705c121SKalle Valo u32 val, last_read_idx = 0; 827e705c121SKalle Valo 828e705c121SKalle Valo if (cpu == 1) { 829e705c121SKalle Valo shift_param = 0; 830e705c121SKalle Valo *first_ucode_section = 0; 831e705c121SKalle Valo } else { 832e705c121SKalle Valo shift_param = 16; 833e705c121SKalle Valo (*first_ucode_section)++; 834e705c121SKalle Valo } 835e705c121SKalle Valo 836eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 837e705c121SKalle Valo last_read_idx = i; 838e705c121SKalle Valo 839e705c121SKalle Valo /* 840e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 841e705c121SKalle Valo * CPU1 to CPU2. 842e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 843e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 844e705c121SKalle Valo */ 845e705c121SKalle Valo if (!image->sec[i].data || 846e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 847e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 848e705c121SKalle Valo IWL_DEBUG_FW(trans, 849e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 850e705c121SKalle Valo i); 851e705c121SKalle Valo break; 852e705c121SKalle Valo } 853e705c121SKalle Valo 854e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 855e705c121SKalle Valo if (ret) 856e705c121SKalle Valo return ret; 857e705c121SKalle Valo 858d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 859e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 860e705c121SKalle Valo val = val | (sec_num << shift_param); 861e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 862eda50cdeSSara Sharon 863e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 864e705c121SKalle Valo } 865e705c121SKalle Valo 866e705c121SKalle Valo *first_ucode_section = last_read_idx; 867e705c121SKalle Valo 8682aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8692aabdbdcSEmmanuel Grumbach 870d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 871e705c121SKalle Valo if (cpu == 1) 872d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 873d6a2c5c7SSara Sharon 0xFFFF); 874e705c121SKalle Valo else 875d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 876d6a2c5c7SSara Sharon 0xFFFFFFFF); 877d6a2c5c7SSara Sharon } else { 878d6a2c5c7SSara Sharon if (cpu == 1) 879d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 880d6a2c5c7SSara Sharon 0xFFFF); 881d6a2c5c7SSara Sharon else 882d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 883d6a2c5c7SSara Sharon 0xFFFFFFFF); 884d6a2c5c7SSara Sharon } 885e705c121SKalle Valo 886e705c121SKalle Valo return 0; 887e705c121SKalle Valo } 888e705c121SKalle Valo 889e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 890e705c121SKalle Valo const struct fw_img *image, 891e705c121SKalle Valo int cpu, 892e705c121SKalle Valo int *first_ucode_section) 893e705c121SKalle Valo { 894e705c121SKalle Valo int i, ret = 0; 895e705c121SKalle Valo u32 last_read_idx = 0; 896e705c121SKalle Valo 8973ce4a038SKirtika Ruchandani if (cpu == 1) 898e705c121SKalle Valo *first_ucode_section = 0; 8993ce4a038SKirtika Ruchandani else 900e705c121SKalle Valo (*first_ucode_section)++; 901e705c121SKalle Valo 902eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 903e705c121SKalle Valo last_read_idx = i; 904e705c121SKalle Valo 905e705c121SKalle Valo /* 906e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 907e705c121SKalle Valo * CPU1 to CPU2. 908e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 909e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 910e705c121SKalle Valo */ 911e705c121SKalle Valo if (!image->sec[i].data || 912e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 913e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 914e705c121SKalle Valo IWL_DEBUG_FW(trans, 915e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 916e705c121SKalle Valo i); 917e705c121SKalle Valo break; 918e705c121SKalle Valo } 919e705c121SKalle Valo 920e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 921e705c121SKalle Valo if (ret) 922e705c121SKalle Valo return ret; 923e705c121SKalle Valo } 924e705c121SKalle Valo 925e705c121SKalle Valo *first_ucode_section = last_read_idx; 926e705c121SKalle Valo 927e705c121SKalle Valo return 0; 928e705c121SKalle Valo } 929e705c121SKalle Valo 930c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 931e705c121SKalle Valo { 932e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 933fd527eb5SGolan Ben Ami const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 934e705c121SKalle Valo int i; 935e705c121SKalle Valo 936e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 937e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 938e705c121SKalle Valo 939e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 940e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 941e705c121SKalle Valo else 942e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 943e705c121SKalle Valo 944e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 945e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 946e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 947e705c121SKalle Valo 948e705c121SKalle Valo switch (dest->reg_ops[i].op) { 949e705c121SKalle Valo case CSR_ASSIGN: 950e705c121SKalle Valo iwl_write32(trans, addr, val); 951e705c121SKalle Valo break; 952e705c121SKalle Valo case CSR_SETBIT: 953e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 954e705c121SKalle Valo break; 955e705c121SKalle Valo case CSR_CLEARBIT: 956e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 957e705c121SKalle Valo break; 958e705c121SKalle Valo case PRPH_ASSIGN: 959e705c121SKalle Valo iwl_write_prph(trans, addr, val); 960e705c121SKalle Valo break; 961e705c121SKalle Valo case PRPH_SETBIT: 962e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 963e705c121SKalle Valo break; 964e705c121SKalle Valo case PRPH_CLEARBIT: 965e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 966e705c121SKalle Valo break; 967e705c121SKalle Valo case PRPH_BLOCKBIT: 968e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 969e705c121SKalle Valo IWL_ERR(trans, 970e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 971e705c121SKalle Valo val, addr); 972e705c121SKalle Valo goto monitor; 973e705c121SKalle Valo } 974e705c121SKalle Valo break; 975e705c121SKalle Valo default: 976e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 977e705c121SKalle Valo dest->reg_ops[i].op); 978e705c121SKalle Valo break; 979e705c121SKalle Valo } 980e705c121SKalle Valo } 981e705c121SKalle Valo 982e705c121SKalle Valo monitor: 983e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 984e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 985e705c121SKalle Valo trans_pcie->fw_mon_phys >> dest->base_shift); 9866e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 987e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 988e705c121SKalle Valo (trans_pcie->fw_mon_phys + 98962d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size - 256) >> 99062d7476dSEmmanuel Grumbach dest->end_shift); 99162d7476dSEmmanuel Grumbach else 99262d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99362d7476dSEmmanuel Grumbach (trans_pcie->fw_mon_phys + 99462d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size) >> 99562d7476dSEmmanuel Grumbach dest->end_shift); 996e705c121SKalle Valo } 997e705c121SKalle Valo } 998e705c121SKalle Valo 999e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1000e705c121SKalle Valo const struct fw_img *image) 1001e705c121SKalle Valo { 1002e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1003e705c121SKalle Valo int ret = 0; 1004e705c121SKalle Valo int first_ucode_section; 1005e705c121SKalle Valo 1006e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1007e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1010e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1011e705c121SKalle Valo if (ret) 1012e705c121SKalle Valo return ret; 1013e705c121SKalle Valo 1014e705c121SKalle Valo if (image->is_dual_cpus) { 1015e705c121SKalle Valo /* set CPU2 header address */ 1016e705c121SKalle Valo iwl_write_prph(trans, 1017e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1018e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1019e705c121SKalle Valo 1020e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1021e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1022e705c121SKalle Valo &first_ucode_section); 1023e705c121SKalle Valo if (ret) 1024e705c121SKalle Valo return ret; 1025e705c121SKalle Valo } 1026e705c121SKalle Valo 1027e705c121SKalle Valo /* supported for 7000 only for the moment */ 1028e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1029e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1030e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1031e705c121SKalle Valo 1032e705c121SKalle Valo if (trans_pcie->fw_mon_size) { 1033e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1034e705c121SKalle Valo trans_pcie->fw_mon_phys >> 4); 1035e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 1036e705c121SKalle Valo (trans_pcie->fw_mon_phys + 1037e705c121SKalle Valo trans_pcie->fw_mon_size) >> 4); 1038e705c121SKalle Valo } 1039e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 1040e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1041e705c121SKalle Valo } 1042e705c121SKalle Valo 10432aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10442aabdbdcSEmmanuel Grumbach 1045e705c121SKalle Valo /* release CPU reset */ 1046e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1047e705c121SKalle Valo 1048e705c121SKalle Valo return 0; 1049e705c121SKalle Valo } 1050e705c121SKalle Valo 1051e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1052e705c121SKalle Valo const struct fw_img *image) 1053e705c121SKalle Valo { 1054e705c121SKalle Valo int ret = 0; 1055e705c121SKalle Valo int first_ucode_section; 1056e705c121SKalle Valo 1057e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1058e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1059e705c121SKalle Valo 1060e705c121SKalle Valo if (trans->dbg_dest_tlv) 1061e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1062e705c121SKalle Valo 106382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 106482ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 106582ea7966SSara Sharon 106682ea7966SSara Sharon /* 106782ea7966SSara Sharon * Set default value. On resume reading the values that were 106882ea7966SSara Sharon * zeored can provide debug data on the resume flow. 106982ea7966SSara Sharon * This is for debugging only and has no functional impact. 107082ea7966SSara Sharon */ 107182ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 107282ea7966SSara Sharon 1073e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1074e705c121SKalle Valo /* release CPU reset */ 1075e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1076e705c121SKalle Valo 1077e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1078e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1079e705c121SKalle Valo &first_ucode_section); 1080e705c121SKalle Valo if (ret) 1081e705c121SKalle Valo return ret; 1082e705c121SKalle Valo 1083e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1084e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1085e705c121SKalle Valo &first_ucode_section); 1086e705c121SKalle Valo } 1087e705c121SKalle Valo 10889ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1089727c02dfSSara Sharon { 1090326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1091727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1092326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1093326477e4SJohannes Berg bool report; 1094727c02dfSSara Sharon 1095326477e4SJohannes Berg if (hw_rfkill) { 1096326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1097326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1098326477e4SJohannes Berg } else { 1099326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1100326477e4SJohannes Berg if (trans_pcie->opmode_down) 1101326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1102326477e4SJohannes Berg } 1103727c02dfSSara Sharon 1104326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1105326477e4SJohannes Berg 1106326477e4SJohannes Berg if (prev != report) 1107326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1108727c02dfSSara Sharon 1109727c02dfSSara Sharon return hw_rfkill; 1110727c02dfSSara Sharon } 1111727c02dfSSara Sharon 11127ca00409SHaim Dreyfuss struct iwl_causes_list { 11137ca00409SHaim Dreyfuss u32 cause_num; 11147ca00409SHaim Dreyfuss u32 mask_reg; 11157ca00409SHaim Dreyfuss u8 addr; 11167ca00409SHaim Dreyfuss }; 11177ca00409SHaim Dreyfuss 11187ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11197ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11207ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11217ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11227ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11237ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11247ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11257ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11267ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11277ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11287ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11297ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11307ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11317ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11327ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11337ca00409SHaim Dreyfuss }; 11347ca00409SHaim Dreyfuss 11359b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11369b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11379b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11389b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11399b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11409b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11419b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11429b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11439b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11449b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11459b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11469b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11479b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11489b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11499b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11509b58419eSGolan Ben Ami }; 11519b58419eSGolan Ben Ami 11527ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11537ca00409SHaim Dreyfuss { 11547ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11557ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11569b58419eSGolan Ben Ami int i, arr_size = 11579b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11589b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11597ca00409SHaim Dreyfuss 11607ca00409SHaim Dreyfuss /* 11617ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11627ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11637ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11647ca00409SHaim Dreyfuss */ 11659b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11669b58419eSGolan Ben Ami struct iwl_causes_list *causes = 11679b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11689b58419eSGolan Ben Ami causes_list : causes_list_v2; 11699b58419eSGolan Ben Ami 11709b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11719b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11729b58419eSGolan Ben Ami causes[i].cause_num); 11737ca00409SHaim Dreyfuss } 11747ca00409SHaim Dreyfuss } 11757ca00409SHaim Dreyfuss 11767ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11777ca00409SHaim Dreyfuss { 11787ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11797ca00409SHaim Dreyfuss u32 offset = 11807ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11817ca00409SHaim Dreyfuss u32 val, idx; 11827ca00409SHaim Dreyfuss 11837ca00409SHaim Dreyfuss /* 11847ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11857ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11867ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11877ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11887ca00409SHaim Dreyfuss */ 11897ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11907ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11917ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11927ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11937ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11947ca00409SHaim Dreyfuss } 11957ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11967ca00409SHaim Dreyfuss 11977ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11987ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11997ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 12007ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 12017ca00409SHaim Dreyfuss 12027ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 12037ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 12047ca00409SHaim Dreyfuss } 12057ca00409SHaim Dreyfuss 120677c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 12077ca00409SHaim Dreyfuss { 12087ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 12097ca00409SHaim Dreyfuss 12107ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1211d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1212d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12137ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, 12147ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 12157ca00409SHaim Dreyfuss return; 12167ca00409SHaim Dreyfuss } 1217d7270d61SHaim Dreyfuss /* 1218d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1219d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1220d7270d61SHaim Dreyfuss * prph. 1221d7270d61SHaim Dreyfuss */ 1222d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12237ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12247ca00409SHaim Dreyfuss 12257ca00409SHaim Dreyfuss /* 12267ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12277ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12287ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12297ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12307ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12317ca00409SHaim Dreyfuss */ 12327ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12337ca00409SHaim Dreyfuss 12347ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 123583730058SHaim Dreyfuss } 12367ca00409SHaim Dreyfuss 123783730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 123883730058SHaim Dreyfuss { 123983730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 124083730058SHaim Dreyfuss 124183730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 124283730058SHaim Dreyfuss 124383730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 124483730058SHaim Dreyfuss return; 124583730058SHaim Dreyfuss 124683730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12477ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 124883730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12497ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12507ca00409SHaim Dreyfuss } 12517ca00409SHaim Dreyfuss 1252e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1253e705c121SKalle Valo { 1254e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1255e705c121SKalle Valo 1256e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1257e705c121SKalle Valo 1258e705c121SKalle Valo if (trans_pcie->is_down) 1259e705c121SKalle Valo return; 1260e705c121SKalle Valo 1261e705c121SKalle Valo trans_pcie->is_down = true; 1262e705c121SKalle Valo 12630232d2cdSSara Sharon /* Stop dbgc before stopping device */ 12640232d2cdSSara Sharon if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 12650232d2cdSSara Sharon iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 12660232d2cdSSara Sharon } else { 12670232d2cdSSara Sharon iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); 12680232d2cdSSara Sharon udelay(100); 12690232d2cdSSara Sharon iwl_write_prph(trans, DBGC_OUT_CTRL, 0); 12700232d2cdSSara Sharon } 12710232d2cdSSara Sharon 1272e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1273e705c121SKalle Valo iwl_disable_interrupts(trans); 1274e705c121SKalle Valo 1275e705c121SKalle Valo /* device going down, Stop using ICT table */ 1276e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1277e705c121SKalle Valo 1278e705c121SKalle Valo /* 1279e705c121SKalle Valo * If a HW restart happens during firmware loading, 1280e705c121SKalle Valo * then the firmware loading might call this function 1281e705c121SKalle Valo * and later it might be called again due to the 1282e705c121SKalle Valo * restart. So don't process again if the device is 1283e705c121SKalle Valo * already dead. 1284e705c121SKalle Valo */ 1285e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1286a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1287a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1288e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1289e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1290e705c121SKalle Valo 1291e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1292e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1293e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1294e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1295e705c121SKalle Valo udelay(5); 1296e705c121SKalle Valo } 1297e705c121SKalle Valo } 1298e705c121SKalle Valo 1299e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1300e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1301a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1302e705c121SKalle Valo 1303e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1304e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1305e705c121SKalle Valo 1306870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1307e705c121SKalle Valo 1308e705c121SKalle Valo /* 1309f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1310f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1311f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1312f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1313f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1314f4a1f04aSGolan Ben Ami */ 1315f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1316f4a1f04aSGolan Ben Ami 1317f4a1f04aSGolan Ben Ami /* 1318e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1319e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1320e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1321e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1322e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1323e705c121SKalle Valo */ 1324e705c121SKalle Valo iwl_disable_interrupts(trans); 1325e705c121SKalle Valo 1326e705c121SKalle Valo /* clear all status bits */ 1327e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1328e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1329e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1330e705c121SKalle Valo 1331e705c121SKalle Valo /* 1332e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1333e705c121SKalle Valo * interrupt 1334e705c121SKalle Valo */ 1335e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1336e705c121SKalle Valo 1337a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1338e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1339e705c121SKalle Valo } 1340e705c121SKalle Valo 1341eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13422e5d4a8fSHaim Dreyfuss { 13432e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13442e5d4a8fSHaim Dreyfuss 13452e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13462e5d4a8fSHaim Dreyfuss int i; 13472e5d4a8fSHaim Dreyfuss 1348496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13492e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13502e5d4a8fSHaim Dreyfuss } else { 13512e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13522e5d4a8fSHaim Dreyfuss } 13532e5d4a8fSHaim Dreyfuss } 13542e5d4a8fSHaim Dreyfuss 1355a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1356a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1357a6bd005fSEmmanuel Grumbach { 1358a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1359a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1360a6bd005fSEmmanuel Grumbach int ret; 1361a6bd005fSEmmanuel Grumbach 1362a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1363a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1364a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1365a6bd005fSEmmanuel Grumbach ret = -EIO; 1366a6bd005fSEmmanuel Grumbach goto out; 1367a6bd005fSEmmanuel Grumbach } 1368a6bd005fSEmmanuel Grumbach 1369a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1370a6bd005fSEmmanuel Grumbach 1371a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1372a6bd005fSEmmanuel Grumbach 1373a6bd005fSEmmanuel Grumbach /* 1374a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1375a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1376a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1377a6bd005fSEmmanuel Grumbach */ 1378a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1379a6bd005fSEmmanuel Grumbach 1380a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13812e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1382a6bd005fSEmmanuel Grumbach 1383a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1384a6bd005fSEmmanuel Grumbach 1385a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13869ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1387a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1388a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1389a6bd005fSEmmanuel Grumbach goto out; 1390a6bd005fSEmmanuel Grumbach } 1391a6bd005fSEmmanuel Grumbach 1392a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1393a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1394a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1395a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 139620aa99bbSAnton Protopopov ret = -EIO; 1397a6bd005fSEmmanuel Grumbach goto out; 1398a6bd005fSEmmanuel Grumbach } 1399a6bd005fSEmmanuel Grumbach 1400a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1401a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1402a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1403a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1404a6bd005fSEmmanuel Grumbach 1405a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1406a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1407a6bd005fSEmmanuel Grumbach 1408a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1409a6bd005fSEmmanuel Grumbach if (ret) { 1410a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1411a6bd005fSEmmanuel Grumbach goto out; 1412a6bd005fSEmmanuel Grumbach } 1413a6bd005fSEmmanuel Grumbach 1414a6bd005fSEmmanuel Grumbach /* 1415a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1416a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1417a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1418a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1419a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1420a6bd005fSEmmanuel Grumbach */ 1421a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1422a6bd005fSEmmanuel Grumbach 1423a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1424a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1425a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1426a6bd005fSEmmanuel Grumbach 1427a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 14286e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1429a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1430a6bd005fSEmmanuel Grumbach else 1431a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1432a6bd005fSEmmanuel Grumbach 1433a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14349ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1435a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1436a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1437a6bd005fSEmmanuel Grumbach 1438a6bd005fSEmmanuel Grumbach out: 1439a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1440a6bd005fSEmmanuel Grumbach return ret; 1441a6bd005fSEmmanuel Grumbach } 1442a6bd005fSEmmanuel Grumbach 1443a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1444a6bd005fSEmmanuel Grumbach { 1445a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1446a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1447a6bd005fSEmmanuel Grumbach } 1448a6bd005fSEmmanuel Grumbach 1449326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1450326477e4SJohannes Berg bool was_in_rfkill) 1451326477e4SJohannes Berg { 1452326477e4SJohannes Berg bool hw_rfkill; 1453326477e4SJohannes Berg 1454326477e4SJohannes Berg /* 1455326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1456326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1457326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1458326477e4SJohannes Berg * op_mode. 1459326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1460326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1461326477e4SJohannes Berg * notification without endless recursion. Under very rare 1462326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1463326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1464326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1465326477e4SJohannes Berg */ 1466326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1467326477e4SJohannes Berg if (hw_rfkill) { 1468326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1469326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1470326477e4SJohannes Berg } else { 1471326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1472326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1473326477e4SJohannes Berg } 1474326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1475326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1476326477e4SJohannes Berg } 1477326477e4SJohannes Berg 1478e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1479e705c121SKalle Valo { 1480e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1481326477e4SJohannes Berg bool was_in_rfkill; 1482e705c121SKalle Valo 1483e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1484326477e4SJohannes Berg trans_pcie->opmode_down = true; 1485326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1486e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1487326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1488e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1489e705c121SKalle Valo } 1490e705c121SKalle Valo 1491e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1492e705c121SKalle Valo { 1493e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1494e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1495e705c121SKalle Valo 1496e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1497e705c121SKalle Valo 1498326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1499326477e4SJohannes Berg state ? "disabled" : "enabled"); 150077c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 150177c09bc8SSara Sharon if (trans->cfg->gen2) 150277c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 150377c09bc8SSara Sharon else 1504e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1505e705c121SKalle Valo } 150677c09bc8SSara Sharon } 1507e705c121SKalle Valo 150823ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 150923ae6128SMatti Gottlieb bool reset) 1510e705c121SKalle Valo { 151123ae6128SMatti Gottlieb if (!reset) { 1512e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1513e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1514e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1515e705c121SKalle Valo } 1516e705c121SKalle Valo 1517e705c121SKalle Valo iwl_disable_interrupts(trans); 1518e705c121SKalle Valo 1519e705c121SKalle Valo /* 1520e705c121SKalle Valo * in testing mode, the host stays awake and the 1521e705c121SKalle Valo * hardware won't be reset (not even partially) 1522e705c121SKalle Valo */ 1523e705c121SKalle Valo if (test) 1524e705c121SKalle Valo return; 1525e705c121SKalle Valo 1526e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1527e705c121SKalle Valo 15282e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1529e705c121SKalle Valo 1530e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1531a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1532e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1533a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1534e705c121SKalle Valo 15351316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, false); 15361316d595SSara Sharon 153723ae6128SMatti Gottlieb if (reset) { 1538e705c121SKalle Valo /* 1539e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1540e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1541e705c121SKalle Valo * to execute some invalid memory upon resume 1542e705c121SKalle Valo */ 1543e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1544e705c121SKalle Valo } 1545e705c121SKalle Valo 1546e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1547e705c121SKalle Valo } 1548e705c121SKalle Valo 1549e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1550e705c121SKalle Valo enum iwl_d3_status *status, 155123ae6128SMatti Gottlieb bool test, bool reset) 1552e705c121SKalle Valo { 1553d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1554e705c121SKalle Valo u32 val; 1555e705c121SKalle Valo int ret; 1556e705c121SKalle Valo 1557e705c121SKalle Valo if (test) { 1558e705c121SKalle Valo iwl_enable_interrupts(trans); 1559e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1560e705c121SKalle Valo return 0; 1561e705c121SKalle Valo } 1562e705c121SKalle Valo 15631316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 15641316d595SSara Sharon 1565e705c121SKalle Valo /* 1566d7270d61SHaim Dreyfuss * Reconfigure IVAR table in case of MSIX or reset ict table in 1567d7270d61SHaim Dreyfuss * MSI mode since HW reset erased it. 1568d7270d61SHaim Dreyfuss * Also enables interrupts - none will happen as 1569d7270d61SHaim Dreyfuss * the device doesn't know we're waking it up, only when 1570d7270d61SHaim Dreyfuss * the opmode actually tells it after this call. 1571e705c121SKalle Valo */ 1572d7270d61SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 1573d7270d61SHaim Dreyfuss if (!trans_pcie->msix_enabled) 1574e705c121SKalle Valo iwl_pcie_reset_ict(trans); 157518dcb9a9SSara Sharon iwl_enable_interrupts(trans); 1576e705c121SKalle Valo 1577a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1578a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1579a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1580a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1581e705c121SKalle Valo 15826e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1583e705c121SKalle Valo udelay(2); 1584e705c121SKalle Valo 1585e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1586a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1587a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1588e705c121SKalle Valo 25000); 1589e705c121SKalle Valo if (ret < 0) { 1590e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1591e705c121SKalle Valo return ret; 1592e705c121SKalle Valo } 1593e705c121SKalle Valo 1594e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1595e705c121SKalle Valo 159623ae6128SMatti Gottlieb if (!reset) { 1597e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1598a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1599e705c121SKalle Valo } else { 1600e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1601e705c121SKalle Valo 1602e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1603e705c121SKalle Valo if (ret) { 1604e705c121SKalle Valo IWL_ERR(trans, 1605e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1606e705c121SKalle Valo return ret; 1607e705c121SKalle Valo } 1608e705c121SKalle Valo } 1609e705c121SKalle Valo 161082ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 161182ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 161282ea7966SSara Sharon 1613e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1614e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1615e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1616e705c121SKalle Valo else 1617e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1618e705c121SKalle Valo 1619e705c121SKalle Valo return 0; 1620e705c121SKalle Valo } 1621e705c121SKalle Valo 16222e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16232e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 16242e5d4a8fSHaim Dreyfuss { 16252e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1626ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16272e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16282e5d4a8fSHaim Dreyfuss 162906f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 163006f4b081SSara Sharon goto enable_msi; 163106f4b081SSara Sharon 1632ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 163306f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16342e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16352e5d4a8fSHaim Dreyfuss 163606f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16372e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 163806f4b081SSara Sharon max_irqs); 163906f4b081SSara Sharon if (num_irqs < 0) { 1640496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164106f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 164206f4b081SSara Sharon num_irqs); 164306f4b081SSara Sharon goto enable_msi; 1644496d83caSHaim Dreyfuss } 164506f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1646496d83caSHaim Dreyfuss 16472e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164806f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 164906f4b081SSara Sharon num_irqs); 165006f4b081SSara Sharon 1651496d83caSHaim Dreyfuss /* 165206f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 165306f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1654496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1655496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1656496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1657496d83caSHaim Dreyfuss */ 1658ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 165906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1660496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1661496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1662ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 166306f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1664496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1665496d83caSHaim Dreyfuss } else { 166606f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1667496d83caSHaim Dreyfuss } 1668ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16692e5d4a8fSHaim Dreyfuss 167006f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1671496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16722e5d4a8fSHaim Dreyfuss return; 16732e5d4a8fSHaim Dreyfuss 167406f4b081SSara Sharon enable_msi: 167506f4b081SSara Sharon ret = pci_enable_msi(pdev); 167606f4b081SSara Sharon if (ret) { 167706f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16782e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16792e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16802e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16812e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16822e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16832e5d4a8fSHaim Dreyfuss } 16842e5d4a8fSHaim Dreyfuss } 16852e5d4a8fSHaim Dreyfuss } 16862e5d4a8fSHaim Dreyfuss 16877c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16887c8d91ebSHaim Dreyfuss { 16897c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16907c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16917c8d91ebSHaim Dreyfuss 16927c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16937c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16947c8d91ebSHaim Dreyfuss offset = 1 + i; 16957c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16967c8d91ebSHaim Dreyfuss /* 16977c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16987c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16997c8d91ebSHaim Dreyfuss */ 17007c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17017c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17027c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17037c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17047c8d91ebSHaim Dreyfuss if (ret) 17057c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17067c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 17077c8d91ebSHaim Dreyfuss i); 17087c8d91ebSHaim Dreyfuss } 17097c8d91ebSHaim Dreyfuss } 17107c8d91ebSHaim Dreyfuss 171164fa3affSSharon Dvir static const char *queue_name(struct device *dev, 171264fa3affSSharon Dvir struct iwl_trans_pcie *trans_p, int i) 171364fa3affSSharon Dvir { 171464fa3affSSharon Dvir if (trans_p->shared_vec_mask) { 171564fa3affSSharon Dvir int vec = trans_p->shared_vec_mask & 171664fa3affSSharon Dvir IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 171764fa3affSSharon Dvir 171864fa3affSSharon Dvir if (i == 0) 171964fa3affSSharon Dvir return DRV_NAME ": shared IRQ"; 172064fa3affSSharon Dvir 172164fa3affSSharon Dvir return devm_kasprintf(dev, GFP_KERNEL, 172264fa3affSSharon Dvir DRV_NAME ": queue %d", i + vec); 172364fa3affSSharon Dvir } 172464fa3affSSharon Dvir if (i == 0) 172564fa3affSSharon Dvir return DRV_NAME ": default queue"; 172664fa3affSSharon Dvir 172764fa3affSSharon Dvir if (i == trans_p->alloc_vecs - 1) 172864fa3affSSharon Dvir return DRV_NAME ": exception"; 172964fa3affSSharon Dvir 173064fa3affSSharon Dvir return devm_kasprintf(dev, GFP_KERNEL, 173164fa3affSSharon Dvir DRV_NAME ": queue %d", i); 173264fa3affSSharon Dvir } 173364fa3affSSharon Dvir 17342e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17352e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17362e5d4a8fSHaim Dreyfuss { 1737496d83caSHaim Dreyfuss int i; 17382e5d4a8fSHaim Dreyfuss 1739496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17402e5d4a8fSHaim Dreyfuss int ret; 17415a41a86cSSharon Dvir struct msix_entry *msix_entry; 174264fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 174364fa3affSSharon Dvir 174464fa3affSSharon Dvir if (!qname) 174564fa3affSSharon Dvir return -ENOMEM; 17462e5d4a8fSHaim Dreyfuss 17475a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17485a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17495a41a86cSSharon Dvir msix_entry->vector, 17502e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1751496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17522e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17532e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17542e5d4a8fSHaim Dreyfuss IRQF_SHARED, 175564fa3affSSharon Dvir qname, 17565a41a86cSSharon Dvir msix_entry); 17572e5d4a8fSHaim Dreyfuss if (ret) { 17582e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17592e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17605a41a86cSSharon Dvir 17612e5d4a8fSHaim Dreyfuss return ret; 17622e5d4a8fSHaim Dreyfuss } 17632e5d4a8fSHaim Dreyfuss } 17647c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17652e5d4a8fSHaim Dreyfuss 17662e5d4a8fSHaim Dreyfuss return 0; 17672e5d4a8fSHaim Dreyfuss } 17682e5d4a8fSHaim Dreyfuss 1769e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1770e705c121SKalle Valo { 1771e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1772e705c121SKalle Valo int err; 1773e705c121SKalle Valo 1774e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1775e705c121SKalle Valo 1776e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1777e705c121SKalle Valo if (err) { 1778e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1779e705c121SKalle Valo return err; 1780e705c121SKalle Valo } 1781e705c121SKalle Valo 1782870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1783e705c121SKalle Valo 178452b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 178552b6e168SEmmanuel Grumbach if (err) 178652b6e168SEmmanuel Grumbach return err; 1787e705c121SKalle Valo 17882e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 178983730058SHaim Dreyfuss 1790e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1791e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1792e705c121SKalle Valo 1793326477e4SJohannes Berg trans_pcie->opmode_down = false; 1794326477e4SJohannes Berg 1795e705c121SKalle Valo /* Set is_down to false here so that...*/ 1796e705c121SKalle Valo trans_pcie->is_down = false; 1797e705c121SKalle Valo 1798e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17999ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1800e705c121SKalle Valo 18014cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 18024cbb8e50SLuciano Coelho if (low_power) 18034cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 18044cbb8e50SLuciano Coelho 1805e705c121SKalle Valo return 0; 1806e705c121SKalle Valo } 1807e705c121SKalle Valo 1808e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1809e705c121SKalle Valo { 1810e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1811e705c121SKalle Valo int ret; 1812e705c121SKalle Valo 1813e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1814e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1815e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1816e705c121SKalle Valo 1817e705c121SKalle Valo return ret; 1818e705c121SKalle Valo } 1819e705c121SKalle Valo 1820e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1821e705c121SKalle Valo { 1822e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1823e705c121SKalle Valo 1824e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1825e705c121SKalle Valo 1826e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1827e705c121SKalle Valo iwl_disable_interrupts(trans); 1828e705c121SKalle Valo 1829e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1830e705c121SKalle Valo 1831e705c121SKalle Valo iwl_disable_interrupts(trans); 1832e705c121SKalle Valo 1833e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1834e705c121SKalle Valo 1835e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1836e705c121SKalle Valo 18372e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1838e705c121SKalle Valo } 1839e705c121SKalle Valo 1840e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1841e705c121SKalle Valo { 1842e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1843e705c121SKalle Valo } 1844e705c121SKalle Valo 1845e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1846e705c121SKalle Valo { 1847e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1848e705c121SKalle Valo } 1849e705c121SKalle Valo 1850e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1851e705c121SKalle Valo { 1852e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1853e705c121SKalle Valo } 1854e705c121SKalle Valo 1855e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1856e705c121SKalle Valo { 1857e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1858e705c121SKalle Valo ((reg & 0x000FFFFF) | (3 << 24))); 1859e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1860e705c121SKalle Valo } 1861e705c121SKalle Valo 1862e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1863e705c121SKalle Valo u32 val) 1864e705c121SKalle Valo { 1865e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1866e705c121SKalle Valo ((addr & 0x000FFFFF) | (3 << 24))); 1867e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1868e705c121SKalle Valo } 1869e705c121SKalle Valo 1870e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1871e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1872e705c121SKalle Valo { 1873e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1874e705c121SKalle Valo 1875e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1876e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1877e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1878e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1879e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1880e705c121SKalle Valo else 1881e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1882e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1883e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1884e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1885e705c121SKalle Valo 18866c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18876c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18886c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1889e705c121SKalle Valo 1890e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1891e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 189241837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1893e705c121SKalle Valo 189421cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 189521cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 189621cb3222SJohannes Berg 189739bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 189839bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 189939bdb17eSSharon Dvir 1900e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1901e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1902e705c121SKalle Valo * As this function may be called again in some corner cases don't 1903e705c121SKalle Valo * do anything if NAPI was already initialized. 1904e705c121SKalle Valo */ 1905bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1906e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1907e705c121SKalle Valo } 1908e705c121SKalle Valo 1909e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1910e705c121SKalle Valo { 1911e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19126eb5e529SEmmanuel Grumbach int i; 1913e705c121SKalle Valo 19142e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1915e705c121SKalle Valo 191613a3a390SSara Sharon if (trans->cfg->gen2) 191713a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 191813a3a390SSara Sharon else 1919e705c121SKalle Valo iwl_pcie_tx_free(trans); 1920e705c121SKalle Valo iwl_pcie_rx_free(trans); 1921e705c121SKalle Valo 192210a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 192310a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 192410a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 192510a54d81SLuca Coelho } 192610a54d81SLuca Coelho 19272e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19287c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19297c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19307c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19317c8d91ebSHaim Dreyfuss NULL); 19327c8d91ebSHaim Dreyfuss } 19332e5d4a8fSHaim Dreyfuss 19342e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19352e5d4a8fSHaim Dreyfuss } else { 1936e705c121SKalle Valo iwl_pcie_free_ict(trans); 19372e5d4a8fSHaim Dreyfuss } 1938e705c121SKalle Valo 1939e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1940e705c121SKalle Valo 19416eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19426eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19436eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19446eb5e529SEmmanuel Grumbach 19456eb5e529SEmmanuel Grumbach if (p->page) 19466eb5e529SEmmanuel Grumbach __free_page(p->page); 19476eb5e529SEmmanuel Grumbach } 19486eb5e529SEmmanuel Grumbach 19496eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1950a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1951e705c121SKalle Valo iwl_trans_free(trans); 1952e705c121SKalle Valo } 1953e705c121SKalle Valo 1954e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1955e705c121SKalle Valo { 1956e705c121SKalle Valo if (state) 1957e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1958e705c121SKalle Valo else 1959e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1960e705c121SKalle Valo } 1961e705c121SKalle Valo 196249564a80SLuca Coelho struct iwl_trans_pcie_removal { 196349564a80SLuca Coelho struct pci_dev *pdev; 196449564a80SLuca Coelho struct work_struct work; 196549564a80SLuca Coelho }; 196649564a80SLuca Coelho 196749564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 196849564a80SLuca Coelho { 196949564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 197049564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 197149564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 197249564a80SLuca Coelho char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 197349564a80SLuca Coelho 197449564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 197549564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 197649564a80SLuca Coelho pci_lock_rescan_remove(); 197749564a80SLuca Coelho pci_dev_put(pdev); 197849564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 197949564a80SLuca Coelho pci_unlock_rescan_remove(); 198049564a80SLuca Coelho 198149564a80SLuca Coelho kfree(removal); 198249564a80SLuca Coelho module_put(THIS_MODULE); 198349564a80SLuca Coelho } 198449564a80SLuca Coelho 198523ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1986e705c121SKalle Valo unsigned long *flags) 1987e705c121SKalle Valo { 1988e705c121SKalle Valo int ret; 1989e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1990e705c121SKalle Valo 1991e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1992e705c121SKalle Valo 1993e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1994e705c121SKalle Valo goto out; 1995e705c121SKalle Valo 1996e705c121SKalle Valo /* this bit wakes up the NIC */ 1997e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1998a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19996e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2000e705c121SKalle Valo udelay(2); 2001e705c121SKalle Valo 2002e705c121SKalle Valo /* 2003e705c121SKalle Valo * These bits say the device is running, and should keep running for 2004e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2005e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2006fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2007fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2008e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2009e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2010e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2011e705c121SKalle Valo * to keep device from sleeping. 2012e705c121SKalle Valo * 2013e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2014e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2015fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2016fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2017fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2018e705c121SKalle Valo * 2019e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2020e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2021e705c121SKalle Valo */ 2022e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2023a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 2024a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 2025e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2026e705c121SKalle Valo if (unlikely(ret < 0)) { 202749564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 202849564a80SLuca Coelho 2029e705c121SKalle Valo WARN_ONCE(1, 2030e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 203149564a80SLuca Coelho cntrl); 203249564a80SLuca Coelho 203349564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 203449564a80SLuca Coelho 203549564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 203649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 203749564a80SLuca Coelho 203849564a80SLuca Coelho if (trans_pcie->scheduled_for_removal) 203949564a80SLuca Coelho goto err; 204049564a80SLuca Coelho 204149564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 204249564a80SLuca Coelho 204349564a80SLuca Coelho /* 204449564a80SLuca Coelho * get a module reference to avoid doing this 204549564a80SLuca Coelho * while unloading anyway and to avoid 204649564a80SLuca Coelho * scheduling a work with code that's being 204749564a80SLuca Coelho * removed. 204849564a80SLuca Coelho */ 204949564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 205049564a80SLuca Coelho IWL_ERR(trans, 205149564a80SLuca Coelho "Module is being unloaded - abort\n"); 205249564a80SLuca Coelho goto err; 205349564a80SLuca Coelho } 205449564a80SLuca Coelho 205549564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 205649564a80SLuca Coelho if (!removal) { 205749564a80SLuca Coelho module_put(THIS_MODULE); 205849564a80SLuca Coelho goto err; 205949564a80SLuca Coelho } 206049564a80SLuca Coelho /* 206149564a80SLuca Coelho * we don't need to clear this flag, because 206249564a80SLuca Coelho * the trans will be freed and reallocated. 206349564a80SLuca Coelho */ 206449564a80SLuca Coelho trans_pcie->scheduled_for_removal = true; 206549564a80SLuca Coelho 206649564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 206749564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 206849564a80SLuca Coelho pci_dev_get(removal->pdev); 206949564a80SLuca Coelho schedule_work(&removal->work); 207049564a80SLuca Coelho } else { 207149564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 207249564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 207349564a80SLuca Coelho } 207449564a80SLuca Coelho 207549564a80SLuca Coelho err: 2076e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2077e705c121SKalle Valo return false; 2078e705c121SKalle Valo } 2079e705c121SKalle Valo 2080e705c121SKalle Valo out: 2081e705c121SKalle Valo /* 2082e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2083e705c121SKalle Valo * track nic_access anyway. 2084e705c121SKalle Valo */ 2085e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2086e705c121SKalle Valo return true; 2087e705c121SKalle Valo } 2088e705c121SKalle Valo 2089e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2090e705c121SKalle Valo unsigned long *flags) 2091e705c121SKalle Valo { 2092e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2093e705c121SKalle Valo 2094e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2095e705c121SKalle Valo 2096e705c121SKalle Valo /* 2097e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2098e705c121SKalle Valo * track nic_access anyway. 2099e705c121SKalle Valo */ 2100e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2101e705c121SKalle Valo 2102e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2103e705c121SKalle Valo goto out; 2104e705c121SKalle Valo 2105e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2106a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2107e705c121SKalle Valo /* 2108e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2109e705c121SKalle Valo * any previous writes, but we need the write that clears the 2110e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2111e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2112e705c121SKalle Valo */ 2113e705c121SKalle Valo mmiowb(); 2114e705c121SKalle Valo out: 2115e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2116e705c121SKalle Valo } 2117e705c121SKalle Valo 2118e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2119e705c121SKalle Valo void *buf, int dwords) 2120e705c121SKalle Valo { 2121e705c121SKalle Valo unsigned long flags; 2122e705c121SKalle Valo int offs, ret = 0; 2123e705c121SKalle Valo u32 *vals = buf; 2124e705c121SKalle Valo 212523ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2126e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2127e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2128e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2129e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2130e705c121SKalle Valo } else { 2131e705c121SKalle Valo ret = -EBUSY; 2132e705c121SKalle Valo } 2133e705c121SKalle Valo return ret; 2134e705c121SKalle Valo } 2135e705c121SKalle Valo 2136e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2137e705c121SKalle Valo const void *buf, int dwords) 2138e705c121SKalle Valo { 2139e705c121SKalle Valo unsigned long flags; 2140e705c121SKalle Valo int offs, ret = 0; 2141e705c121SKalle Valo const u32 *vals = buf; 2142e705c121SKalle Valo 214323ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2144e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2145e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2146e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2147e705c121SKalle Valo vals ? vals[offs] : 0); 2148e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2149e705c121SKalle Valo } else { 2150e705c121SKalle Valo ret = -EBUSY; 2151e705c121SKalle Valo } 2152e705c121SKalle Valo return ret; 2153e705c121SKalle Valo } 2154e705c121SKalle Valo 2155e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2156e705c121SKalle Valo unsigned long txqs, 2157e705c121SKalle Valo bool freeze) 2158e705c121SKalle Valo { 2159e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2160e705c121SKalle Valo int queue; 2161e705c121SKalle Valo 2162e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2163b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2164e705c121SKalle Valo unsigned long now; 2165e705c121SKalle Valo 2166e705c121SKalle Valo spin_lock_bh(&txq->lock); 2167e705c121SKalle Valo 2168e705c121SKalle Valo now = jiffies; 2169e705c121SKalle Valo 2170e705c121SKalle Valo if (txq->frozen == freeze) 2171e705c121SKalle Valo goto next_queue; 2172e705c121SKalle Valo 2173e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2174e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2175e705c121SKalle Valo 2176e705c121SKalle Valo txq->frozen = freeze; 2177e705c121SKalle Valo 2178bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2179e705c121SKalle Valo goto next_queue; 2180e705c121SKalle Valo 2181e705c121SKalle Valo if (freeze) { 2182e705c121SKalle Valo if (unlikely(time_after(now, 2183e705c121SKalle Valo txq->stuck_timer.expires))) { 2184e705c121SKalle Valo /* 2185e705c121SKalle Valo * The timer should have fired, maybe it is 2186e705c121SKalle Valo * spinning right now on the lock. 2187e705c121SKalle Valo */ 2188e705c121SKalle Valo goto next_queue; 2189e705c121SKalle Valo } 2190e705c121SKalle Valo /* remember how long until the timer fires */ 2191e705c121SKalle Valo txq->frozen_expiry_remainder = 2192e705c121SKalle Valo txq->stuck_timer.expires - now; 2193e705c121SKalle Valo del_timer(&txq->stuck_timer); 2194e705c121SKalle Valo goto next_queue; 2195e705c121SKalle Valo } 2196e705c121SKalle Valo 2197e705c121SKalle Valo /* 2198e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2199e705c121SKalle Valo * remainder before it froze 2200e705c121SKalle Valo */ 2201e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2202e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2203e705c121SKalle Valo 2204e705c121SKalle Valo next_queue: 2205e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2206e705c121SKalle Valo } 2207e705c121SKalle Valo } 2208e705c121SKalle Valo 22090cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22100cd58eaaSEmmanuel Grumbach { 22110cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22120cd58eaaSEmmanuel Grumbach int i; 22130cd58eaaSEmmanuel Grumbach 22140cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2215b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 22160cd58eaaSEmmanuel Grumbach 22170cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 22180cd58eaaSEmmanuel Grumbach continue; 22190cd58eaaSEmmanuel Grumbach 22200cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22210cd58eaaSEmmanuel Grumbach 22220cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22230cd58eaaSEmmanuel Grumbach txq->block--; 22240cd58eaaSEmmanuel Grumbach if (!txq->block) { 22250cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2226bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22270cd58eaaSEmmanuel Grumbach } 22280cd58eaaSEmmanuel Grumbach } else if (block) { 22290cd58eaaSEmmanuel Grumbach txq->block++; 22300cd58eaaSEmmanuel Grumbach } 22310cd58eaaSEmmanuel Grumbach 22320cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22330cd58eaaSEmmanuel Grumbach } 22340cd58eaaSEmmanuel Grumbach } 22350cd58eaaSEmmanuel Grumbach 2236e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2237e705c121SKalle Valo 223838398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 223938398efbSSara Sharon { 2240afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2241afb84431SEmmanuel Grumbach u32 status; 2242afb84431SEmmanuel Grumbach bool active; 2243afb84431SEmmanuel Grumbach u8 fifo; 224438398efbSSara Sharon 2245afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2246afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2247bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2248ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2249ae79785fSSara Sharon return; 2250afb84431SEmmanuel Grumbach } 2251ae79785fSSara Sharon 2252afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2253afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2254afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 225538398efbSSara Sharon 225638398efbSSara Sharon IWL_ERR(trans, 2257afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2258afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2259afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2260afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2261afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 226238398efbSSara Sharon (TFD_QUEUE_SIZE_MAX - 1), 2263afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2264afb84431SEmmanuel Grumbach (TFD_QUEUE_SIZE_MAX - 1), 2265afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 226638398efbSSara Sharon } 226738398efbSSara Sharon 2268d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2269e705c121SKalle Valo { 2270e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2271e705c121SKalle Valo struct iwl_txq *txq; 2272e705c121SKalle Valo unsigned long now = jiffies; 2273e705c121SKalle Valo u8 wr_ptr; 2274e705c121SKalle Valo 2275d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2276d6d517b7SSara Sharon return -EINVAL; 2277e705c121SKalle Valo 2278d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2279d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22806aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2281e705c121SKalle Valo 22826aa7de05SMark Rutland while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2283e705c121SKalle Valo !time_after(jiffies, 2284e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22856aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2286e705c121SKalle Valo 2287e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 2288e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2289e705c121SKalle Valo wr_ptr, write_ptr)) 2290e705c121SKalle Valo return -ETIMEDOUT; 2291192185d6SJohannes Berg usleep_range(1000, 2000); 2292e705c121SKalle Valo } 2293e705c121SKalle Valo 2294bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2295e705c121SKalle Valo IWL_ERR(trans, 2296d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2297d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2298d6d517b7SSara Sharon return -ETIMEDOUT; 2299e705c121SKalle Valo } 2300e705c121SKalle Valo 2301d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2302d6d517b7SSara Sharon 2303d6d517b7SSara Sharon return 0; 2304d6d517b7SSara Sharon } 2305d6d517b7SSara Sharon 2306d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2307d6d517b7SSara Sharon { 2308d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2309d6d517b7SSara Sharon int cnt; 2310d6d517b7SSara Sharon int ret = 0; 2311d6d517b7SSara Sharon 2312d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2313d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2314d6d517b7SSara Sharon 2315d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2316d6d517b7SSara Sharon continue; 2317d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2318d6d517b7SSara Sharon continue; 2319d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2320d6d517b7SSara Sharon continue; 2321d6d517b7SSara Sharon 2322d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 232338398efbSSara Sharon if (ret) 2324d6d517b7SSara Sharon break; 2325d6d517b7SSara Sharon } 2326e705c121SKalle Valo 2327e705c121SKalle Valo return ret; 2328e705c121SKalle Valo } 2329e705c121SKalle Valo 2330e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2331e705c121SKalle Valo u32 mask, u32 value) 2332e705c121SKalle Valo { 2333e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2334e705c121SKalle Valo unsigned long flags; 2335e705c121SKalle Valo 2336e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2337e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2338e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2339e705c121SKalle Valo } 2340e705c121SKalle Valo 2341c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2342e705c121SKalle Valo { 2343e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2344e705c121SKalle Valo 2345e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2346e705c121SKalle Valo return; 2347e705c121SKalle Valo 2348b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 23495d93f3a2SLuca Coelho 23505d93f3a2SLuca Coelho #ifdef CONFIG_PM 23515d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23525d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23535d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2354e705c121SKalle Valo } 2355e705c121SKalle Valo 2356c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2357e705c121SKalle Valo { 2358e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2359e705c121SKalle Valo 2360e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2361e705c121SKalle Valo return; 2362e705c121SKalle Valo 2363b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2364b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2365b3ff1270SLuca Coelho 23665d93f3a2SLuca Coelho #ifdef CONFIG_PM 23675d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23685d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23695d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2370e705c121SKalle Valo } 2371e705c121SKalle Valo 2372e705c121SKalle Valo static const char *get_csr_string(int cmd) 2373e705c121SKalle Valo { 2374e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2375e705c121SKalle Valo switch (cmd) { 2376e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2377e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2378e705c121SKalle Valo IWL_CMD(CSR_INT); 2379e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2380e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2381e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2382e705c121SKalle Valo IWL_CMD(CSR_RESET); 2383e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2384e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2385e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2386e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2387e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2388e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2389e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2390e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2391e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2392e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2393e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2394e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2395e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2396e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2397e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2398e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2399e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2400e705c121SKalle Valo default: 2401e705c121SKalle Valo return "UNKNOWN"; 2402e705c121SKalle Valo } 2403e705c121SKalle Valo #undef IWL_CMD 2404e705c121SKalle Valo } 2405e705c121SKalle Valo 2406e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2407e705c121SKalle Valo { 2408e705c121SKalle Valo int i; 2409e705c121SKalle Valo static const u32 csr_tbl[] = { 2410e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2411e705c121SKalle Valo CSR_INT_COALESCING, 2412e705c121SKalle Valo CSR_INT, 2413e705c121SKalle Valo CSR_INT_MASK, 2414e705c121SKalle Valo CSR_FH_INT_STATUS, 2415e705c121SKalle Valo CSR_GPIO_IN, 2416e705c121SKalle Valo CSR_RESET, 2417e705c121SKalle Valo CSR_GP_CNTRL, 2418e705c121SKalle Valo CSR_HW_REV, 2419e705c121SKalle Valo CSR_EEPROM_REG, 2420e705c121SKalle Valo CSR_EEPROM_GP, 2421e705c121SKalle Valo CSR_OTP_GP_REG, 2422e705c121SKalle Valo CSR_GIO_REG, 2423e705c121SKalle Valo CSR_GP_UCODE_REG, 2424e705c121SKalle Valo CSR_GP_DRIVER_REG, 2425e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2426e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2427e705c121SKalle Valo CSR_LED_REG, 2428e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2429e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2430e705c121SKalle Valo CSR_ANA_PLL_CFG, 2431e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2432e705c121SKalle Valo CSR_HW_REV_WA_REG, 2433e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2434e705c121SKalle Valo }; 2435e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2436e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2437e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2438e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2439e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2440e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2441e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2442e705c121SKalle Valo } 2443e705c121SKalle Valo } 2444e705c121SKalle Valo 2445e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2446e705c121SKalle Valo /* create and remove of files */ 2447e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2448e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 2449e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 2450e705c121SKalle Valo goto err; \ 2451e705c121SKalle Valo } while (0) 2452e705c121SKalle Valo 2453e705c121SKalle Valo /* file operation */ 2454e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2455e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2456e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2457e705c121SKalle Valo .open = simple_open, \ 2458e705c121SKalle Valo .llseek = generic_file_llseek, \ 2459e705c121SKalle Valo }; 2460e705c121SKalle Valo 2461e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2462e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2463e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2464e705c121SKalle Valo .open = simple_open, \ 2465e705c121SKalle Valo .llseek = generic_file_llseek, \ 2466e705c121SKalle Valo }; 2467e705c121SKalle Valo 2468e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2469e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2470e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2471e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2472e705c121SKalle Valo .open = simple_open, \ 2473e705c121SKalle Valo .llseek = generic_file_llseek, \ 2474e705c121SKalle Valo }; 2475e705c121SKalle Valo 2476e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2477e705c121SKalle Valo char __user *user_buf, 2478e705c121SKalle Valo size_t count, loff_t *ppos) 2479e705c121SKalle Valo { 2480e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2481e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2482e705c121SKalle Valo struct iwl_txq *txq; 2483e705c121SKalle Valo char *buf; 2484e705c121SKalle Valo int pos = 0; 2485e705c121SKalle Valo int cnt; 2486e705c121SKalle Valo int ret; 2487e705c121SKalle Valo size_t bufsz; 2488e705c121SKalle Valo 2489e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2490e705c121SKalle Valo 2491b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2492e705c121SKalle Valo return -EAGAIN; 2493e705c121SKalle Valo 2494e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2495e705c121SKalle Valo if (!buf) 2496e705c121SKalle Valo return -ENOMEM; 2497e705c121SKalle Valo 2498e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2499b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2500e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2501e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2502bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2503e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2504e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2505e705c121SKalle Valo txq->need_update, txq->frozen, 2506e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2507e705c121SKalle Valo } 2508e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2509e705c121SKalle Valo kfree(buf); 2510e705c121SKalle Valo return ret; 2511e705c121SKalle Valo } 2512e705c121SKalle Valo 2513e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2514e705c121SKalle Valo char __user *user_buf, 2515e705c121SKalle Valo size_t count, loff_t *ppos) 2516e705c121SKalle Valo { 2517e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2518e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251978485054SSara Sharon char *buf; 252078485054SSara Sharon int pos = 0, i, ret; 252178485054SSara Sharon size_t bufsz = sizeof(buf); 2522e705c121SKalle Valo 252378485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 252478485054SSara Sharon 252578485054SSara Sharon if (!trans_pcie->rxq) 252678485054SSara Sharon return -EAGAIN; 252778485054SSara Sharon 252878485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 252978485054SSara Sharon if (!buf) 253078485054SSara Sharon return -ENOMEM; 253178485054SSara Sharon 253278485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 253378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 253478485054SSara Sharon 253578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 253678485054SSara Sharon i); 253778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2538e705c121SKalle Valo rxq->read); 253978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2540e705c121SKalle Valo rxq->write); 254178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2542e705c121SKalle Valo rxq->write_actual); 254378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2544e705c121SKalle Valo rxq->need_update); 254578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2546e705c121SKalle Valo rxq->free_count); 2547e705c121SKalle Valo if (rxq->rb_stts) { 254878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 254978485054SSara Sharon "\tclosed_rb_num: %u\n", 255078485054SSara Sharon le16_to_cpu(rxq->rb_stts->closed_rb_num) & 255178485054SSara Sharon 0x0FFF); 2552e705c121SKalle Valo } else { 2553e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 255478485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2555e705c121SKalle Valo } 255678485054SSara Sharon } 255778485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 255878485054SSara Sharon kfree(buf); 255978485054SSara Sharon 256078485054SSara Sharon return ret; 2561e705c121SKalle Valo } 2562e705c121SKalle Valo 2563e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2564e705c121SKalle Valo char __user *user_buf, 2565e705c121SKalle Valo size_t count, loff_t *ppos) 2566e705c121SKalle Valo { 2567e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2568e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2569e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2570e705c121SKalle Valo 2571e705c121SKalle Valo int pos = 0; 2572e705c121SKalle Valo char *buf; 2573e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2574e705c121SKalle Valo ssize_t ret; 2575e705c121SKalle Valo 2576e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2577e705c121SKalle Valo if (!buf) 2578e705c121SKalle Valo return -ENOMEM; 2579e705c121SKalle Valo 2580e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2581e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2582e705c121SKalle Valo 2583e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2584e705c121SKalle Valo isr_stats->hw); 2585e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2586e705c121SKalle Valo isr_stats->sw); 2587e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2588e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2589e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2590e705c121SKalle Valo isr_stats->err_code); 2591e705c121SKalle Valo } 2592e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2593e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2594e705c121SKalle Valo isr_stats->sch); 2595e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2596e705c121SKalle Valo isr_stats->alive); 2597e705c121SKalle Valo #endif 2598e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2599e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2600e705c121SKalle Valo 2601e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2602e705c121SKalle Valo isr_stats->ctkill); 2603e705c121SKalle Valo 2604e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2605e705c121SKalle Valo isr_stats->wakeup); 2606e705c121SKalle Valo 2607e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2608e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2609e705c121SKalle Valo 2610e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2611e705c121SKalle Valo isr_stats->tx); 2612e705c121SKalle Valo 2613e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2614e705c121SKalle Valo isr_stats->unhandled); 2615e705c121SKalle Valo 2616e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2617e705c121SKalle Valo kfree(buf); 2618e705c121SKalle Valo return ret; 2619e705c121SKalle Valo } 2620e705c121SKalle Valo 2621e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2622e705c121SKalle Valo const char __user *user_buf, 2623e705c121SKalle Valo size_t count, loff_t *ppos) 2624e705c121SKalle Valo { 2625e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2626e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2627e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2628e705c121SKalle Valo u32 reset_flag; 2629078f1131SJohannes Berg int ret; 2630e705c121SKalle Valo 2631078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2632078f1131SJohannes Berg if (ret) 2633078f1131SJohannes Berg return ret; 2634e705c121SKalle Valo if (reset_flag == 0) 2635e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2636e705c121SKalle Valo 2637e705c121SKalle Valo return count; 2638e705c121SKalle Valo } 2639e705c121SKalle Valo 2640e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2641e705c121SKalle Valo const char __user *user_buf, 2642e705c121SKalle Valo size_t count, loff_t *ppos) 2643e705c121SKalle Valo { 2644e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2645e705c121SKalle Valo 2646e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2647e705c121SKalle Valo 2648e705c121SKalle Valo return count; 2649e705c121SKalle Valo } 2650e705c121SKalle Valo 2651e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2652e705c121SKalle Valo char __user *user_buf, 2653e705c121SKalle Valo size_t count, loff_t *ppos) 2654e705c121SKalle Valo { 2655e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2656e705c121SKalle Valo char *buf = NULL; 2657e705c121SKalle Valo ssize_t ret; 2658e705c121SKalle Valo 2659e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2660e705c121SKalle Valo if (ret < 0) 2661e705c121SKalle Valo return ret; 2662e705c121SKalle Valo if (!buf) 2663e705c121SKalle Valo return -EINVAL; 2664e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2665e705c121SKalle Valo kfree(buf); 2666e705c121SKalle Valo return ret; 2667e705c121SKalle Valo } 2668e705c121SKalle Valo 2669fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2670fa4de7f7SJohannes Berg char __user *user_buf, 2671fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2672fa4de7f7SJohannes Berg { 2673fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2674fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2675fa4de7f7SJohannes Berg char buf[100]; 2676fa4de7f7SJohannes Berg int pos; 2677fa4de7f7SJohannes Berg 2678fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2679fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2680fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2681fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2682fa4de7f7SJohannes Berg 2683fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2684fa4de7f7SJohannes Berg } 2685fa4de7f7SJohannes Berg 2686fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2687fa4de7f7SJohannes Berg const char __user *user_buf, 2688fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2689fa4de7f7SJohannes Berg { 2690fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2691fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2692fa4de7f7SJohannes Berg bool old = trans_pcie->debug_rfkill; 2693fa4de7f7SJohannes Berg int ret; 2694fa4de7f7SJohannes Berg 2695fa4de7f7SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2696fa4de7f7SJohannes Berg if (ret) 2697fa4de7f7SJohannes Berg return ret; 2698fa4de7f7SJohannes Berg if (old == trans_pcie->debug_rfkill) 2699fa4de7f7SJohannes Berg return count; 2700fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2701fa4de7f7SJohannes Berg old, trans_pcie->debug_rfkill); 2702fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2703fa4de7f7SJohannes Berg 2704fa4de7f7SJohannes Berg return count; 2705fa4de7f7SJohannes Berg } 2706fa4de7f7SJohannes Berg 2707e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2708e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2709e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2710e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2711e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2712fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2713e705c121SKalle Valo 2714f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2715f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2716e705c121SKalle Valo { 2717f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2718f8a1edb7SJohannes Berg 27192ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 27202ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 27212ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 27222ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 27232ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 27242ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2725e705c121SKalle Valo return 0; 2726e705c121SKalle Valo 2727e705c121SKalle Valo err: 2728e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2729e705c121SKalle Valo return -ENOMEM; 2730e705c121SKalle Valo } 2731e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2732e705c121SKalle Valo 27336983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2734e705c121SKalle Valo { 27353cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2736e705c121SKalle Valo u32 cmdlen = 0; 2737e705c121SKalle Valo int i; 2738e705c121SKalle Valo 27393cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 27406983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2741e705c121SKalle Valo 2742e705c121SKalle Valo return cmdlen; 2743e705c121SKalle Valo } 2744e705c121SKalle Valo 2745e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2746e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2747e705c121SKalle Valo int allocated_rb_nums) 2748e705c121SKalle Valo { 2749e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2750e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 275178485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 275278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2753e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2754e705c121SKalle Valo 2755e705c121SKalle Valo spin_lock(&rxq->lock); 2756e705c121SKalle Valo 27576aa7de05SMark Rutland r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2758e705c121SKalle Valo 2759e705c121SKalle Valo for (i = rxq->read, j = 0; 2760e705c121SKalle Valo i != r && j < allocated_rb_nums; 2761e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2762e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2763e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2764e705c121SKalle Valo 2765e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2766e705c121SKalle Valo DMA_FROM_DEVICE); 2767e705c121SKalle Valo 2768e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2769e705c121SKalle Valo 2770e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2771e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2772e705c121SKalle Valo rb = (void *)(*data)->data; 2773e705c121SKalle Valo rb->index = cpu_to_le32(i); 2774e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2775e705c121SKalle Valo /* remap the page for the free benefit */ 2776e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2777e705c121SKalle Valo max_len, 2778e705c121SKalle Valo DMA_FROM_DEVICE); 2779e705c121SKalle Valo 2780e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2781e705c121SKalle Valo } 2782e705c121SKalle Valo 2783e705c121SKalle Valo spin_unlock(&rxq->lock); 2784e705c121SKalle Valo 2785e705c121SKalle Valo return rb_len; 2786e705c121SKalle Valo } 2787e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2788e705c121SKalle Valo 2789e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2790e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2791e705c121SKalle Valo { 2792e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2793e705c121SKalle Valo __le32 *val; 2794e705c121SKalle Valo int i; 2795e705c121SKalle Valo 2796e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2797e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2798e705c121SKalle Valo val = (void *)(*data)->data; 2799e705c121SKalle Valo 2800e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2801e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2802e705c121SKalle Valo 2803e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2804e705c121SKalle Valo 2805e705c121SKalle Valo return csr_len; 2806e705c121SKalle Valo } 2807e705c121SKalle Valo 2808e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2809e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2810e705c121SKalle Valo { 2811e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2812e705c121SKalle Valo unsigned long flags; 2813e705c121SKalle Valo __le32 *val; 2814e705c121SKalle Valo int i; 2815e705c121SKalle Valo 281623ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2817e705c121SKalle Valo return 0; 2818e705c121SKalle Valo 2819e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2820e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2821e705c121SKalle Valo val = (void *)(*data)->data; 2822e705c121SKalle Valo 2823723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2824723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2825723b45e2SLiad Kaufman i += sizeof(u32)) 2826e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2827723b45e2SLiad Kaufman else 2828723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2829723b45e2SLiad Kaufman i += sizeof(u32)) 2830723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2831723b45e2SLiad Kaufman i)); 2832e705c121SKalle Valo 2833e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2834e705c121SKalle Valo 2835e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2836e705c121SKalle Valo 2837e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2838e705c121SKalle Valo } 2839e705c121SKalle Valo 2840e705c121SKalle Valo static u32 2841e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2842e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2843e705c121SKalle Valo u32 monitor_len) 2844e705c121SKalle Valo { 2845e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2846e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2847e705c121SKalle Valo unsigned long flags; 2848e705c121SKalle Valo u32 i; 2849e705c121SKalle Valo 285023ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2851e705c121SKalle Valo return 0; 2852e705c121SKalle Valo 285314ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2854e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 285514ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 285614ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 285714ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2858e705c121SKalle Valo 2859e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2860e705c121SKalle Valo 2861e705c121SKalle Valo return monitor_len; 2862e705c121SKalle Valo } 2863e705c121SKalle Valo 2864e705c121SKalle Valo static u32 2865e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2866e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2867e705c121SKalle Valo u32 monitor_len) 2868e705c121SKalle Valo { 2869e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2870e705c121SKalle Valo u32 len = 0; 2871e705c121SKalle Valo 2872e705c121SKalle Valo if ((trans_pcie->fw_mon_page && 2873e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2874e705c121SKalle Valo trans->dbg_dest_tlv) { 2875e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2876e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2877e705c121SKalle Valo 2878e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2879e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2880e705c121SKalle Valo write_ptr = 2881e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2882e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2883e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2884e705c121SKalle Valo } else { 2885e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2886e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2887e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2888e705c121SKalle Valo } 2889e705c121SKalle Valo 2890e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2891e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2892e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2893e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2894e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2895e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2896e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2897e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2898e705c121SKalle Valo 2899e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 2900e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2901e705c121SKalle Valo /* 2902e705c121SKalle Valo * The firmware is now asserted, it won't write anything 2903e705c121SKalle Valo * to the buffer. CPU can take ownership to fetch the 2904e705c121SKalle Valo * data. The buffer will be handed back to the device 2905e705c121SKalle Valo * before the firmware will be restarted. 2906e705c121SKalle Valo */ 2907e705c121SKalle Valo dma_sync_single_for_cpu(trans->dev, 2908e705c121SKalle Valo trans_pcie->fw_mon_phys, 2909e705c121SKalle Valo trans_pcie->fw_mon_size, 2910e705c121SKalle Valo DMA_FROM_DEVICE); 2911e705c121SKalle Valo memcpy(fw_mon_data->data, 2912e705c121SKalle Valo page_address(trans_pcie->fw_mon_page), 2913e705c121SKalle Valo trans_pcie->fw_mon_size); 2914e705c121SKalle Valo 2915e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2916e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2917e705c121SKalle Valo /* 2918e705c121SKalle Valo * Update pointers to reflect actual values after 2919e705c121SKalle Valo * shifting 2920e705c121SKalle Valo */ 2921fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version) { 2922fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 2923fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 2924fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 2925fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 2926fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 2927fd527eb5SGolan Ben Ami } else { 2928e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2929e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2930fd527eb5SGolan Ben Ami } 2931fd527eb5SGolan Ben Ami 2932e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2933e705c121SKalle Valo monitor_len / sizeof(u32)); 2934e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2935e705c121SKalle Valo monitor_len = 2936e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2937e705c121SKalle Valo fw_mon_data, 2938e705c121SKalle Valo monitor_len); 2939e705c121SKalle Valo } else { 2940e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2941e705c121SKalle Valo monitor_len = 0; 2942e705c121SKalle Valo } 2943e705c121SKalle Valo 2944e705c121SKalle Valo len += monitor_len; 2945e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2946e705c121SKalle Valo } 2947e705c121SKalle Valo 2948e705c121SKalle Valo return len; 2949e705c121SKalle Valo } 2950e705c121SKalle Valo 2951e705c121SKalle Valo static struct iwl_trans_dump_data 2952e705c121SKalle Valo *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2953a80c7a69SEmmanuel Grumbach const struct iwl_fw_dbg_trigger_tlv *trigger) 2954e705c121SKalle Valo { 2955e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2956e705c121SKalle Valo struct iwl_fw_error_dump_data *data; 2957b2a3b1c1SSara Sharon struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2958e705c121SKalle Valo struct iwl_fw_error_dump_txcmd *txcmd; 2959e705c121SKalle Valo struct iwl_trans_dump_data *dump_data; 2960514c3069SLuca Coelho u32 len, num_rbs = 0; 2961e705c121SKalle Valo u32 monitor_len; 2962e705c121SKalle Valo int i, ptr; 296396a6497bSSara Sharon bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 296496a6497bSSara Sharon !trans->cfg->mq_rx_supported; 2965e705c121SKalle Valo 2966e705c121SKalle Valo /* transport dump header */ 2967e705c121SKalle Valo len = sizeof(*dump_data); 2968e705c121SKalle Valo 2969e705c121SKalle Valo /* host commands */ 2970e705c121SKalle Valo len += sizeof(*data) + 2971bb98ecd4SSara Sharon cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2972e705c121SKalle Valo 2973e705c121SKalle Valo /* FW monitor */ 2974e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2975e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2976e705c121SKalle Valo trans_pcie->fw_mon_size; 2977e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2978e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2979fd527eb5SGolan Ben Ami u32 base, end, cfg_reg; 2980e705c121SKalle Valo 2981fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version == 1) { 2982fd527eb5SGolan Ben Ami cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2983fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 2984fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 2985fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 2986fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 2987fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 2988fd527eb5SGolan Ben Ami 2989fd527eb5SGolan Ben Ami monitor_len = 2990fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 2991fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->end_shift; 2992fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 2993fd527eb5SGolan Ben Ami } else { 2994e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2995e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2996e705c121SKalle Valo 2997e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2998e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2999e705c121SKalle Valo end = iwl_read_prph(trans, end) << 3000e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 3001e705c121SKalle Valo 3002e705c121SKalle Valo /* Make "end" point to the actual end */ 3003fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 3004fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 3005e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 3006e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 3007e705c121SKalle Valo monitor_len = end - base; 3008fd527eb5SGolan Ben Ami } 3009e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 3010e705c121SKalle Valo monitor_len; 3011e705c121SKalle Valo } else { 3012e705c121SKalle Valo monitor_len = 0; 3013e705c121SKalle Valo } 3014e705c121SKalle Valo 3015e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 3016e705c121SKalle Valo dump_data = vzalloc(len); 3017e705c121SKalle Valo if (!dump_data) 3018e705c121SKalle Valo return NULL; 3019e705c121SKalle Valo 3020e705c121SKalle Valo data = (void *)dump_data->data; 3021e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3022e705c121SKalle Valo dump_data->len = len; 3023e705c121SKalle Valo 3024e705c121SKalle Valo return dump_data; 3025e705c121SKalle Valo } 3026e705c121SKalle Valo 3027e705c121SKalle Valo /* CSR registers */ 3028e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3029e705c121SKalle Valo 3030e705c121SKalle Valo /* FH registers */ 3031723b45e2SLiad Kaufman if (trans->cfg->gen2) 3032723b45e2SLiad Kaufman len += sizeof(*data) + 3033723b45e2SLiad Kaufman (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2); 3034723b45e2SLiad Kaufman else 3035723b45e2SLiad Kaufman len += sizeof(*data) + 3036723b45e2SLiad Kaufman (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 3037e705c121SKalle Valo 3038e705c121SKalle Valo if (dump_rbs) { 303978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 304078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3041e705c121SKalle Valo /* RBs */ 30426aa7de05SMark Rutland num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) 3043e705c121SKalle Valo & 0x0FFF; 304478485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3045e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3046e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3047e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3048e705c121SKalle Valo } 3049e705c121SKalle Valo 30505538409bSLiad Kaufman /* Paged memory for gen2 HW */ 30515538409bSLiad Kaufman if (trans->cfg->gen2) 30525538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 30535538409bSLiad Kaufman len += sizeof(*data) + 30545538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 30555538409bSLiad Kaufman trans_pcie->init_dram.paging[i].size; 30565538409bSLiad Kaufman 3057e705c121SKalle Valo dump_data = vzalloc(len); 3058e705c121SKalle Valo if (!dump_data) 3059e705c121SKalle Valo return NULL; 3060e705c121SKalle Valo 3061e705c121SKalle Valo len = 0; 3062e705c121SKalle Valo data = (void *)dump_data->data; 3063e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3064e705c121SKalle Valo txcmd = (void *)data->data; 3065e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3066bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3067bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 30684ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3069e705c121SKalle Valo u32 caplen, cmdlen; 3070e705c121SKalle Valo 30716983ba69SSara Sharon cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 30726983ba69SSara Sharon trans_pcie->tfd_size * ptr); 3073e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3074e705c121SKalle Valo 3075e705c121SKalle Valo if (cmdlen) { 3076e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3077e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3078e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3079e705c121SKalle Valo memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 3080e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3081e705c121SKalle Valo } 3082e705c121SKalle Valo 3083e705c121SKalle Valo ptr = iwl_queue_dec_wrap(ptr); 3084e705c121SKalle Valo } 3085e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3086e705c121SKalle Valo 3087e705c121SKalle Valo data->len = cpu_to_le32(len); 3088e705c121SKalle Valo len += sizeof(*data); 3089e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3090e705c121SKalle Valo 3091e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 3092e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3093e705c121SKalle Valo if (dump_rbs) 3094e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3095e705c121SKalle Valo 30965538409bSLiad Kaufman /* Paged memory for gen2 HW */ 30975538409bSLiad Kaufman if (trans->cfg->gen2) { 30985538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 30995538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 31005538409bSLiad Kaufman dma_addr_t addr = 31015538409bSLiad Kaufman trans_pcie->init_dram.paging[i].physical; 31025538409bSLiad Kaufman u32 page_len = trans_pcie->init_dram.paging[i].size; 31035538409bSLiad Kaufman 31045538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 31055538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 31065538409bSLiad Kaufman paging = (void *)data->data; 31075538409bSLiad Kaufman paging->index = cpu_to_le32(i); 31085538409bSLiad Kaufman dma_sync_single_for_cpu(trans->dev, addr, page_len, 31095538409bSLiad Kaufman DMA_BIDIRECTIONAL); 31105538409bSLiad Kaufman memcpy(paging->data, 31115538409bSLiad Kaufman trans_pcie->init_dram.paging[i].block, page_len); 31125538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 31135538409bSLiad Kaufman 31145538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 31155538409bSLiad Kaufman } 31165538409bSLiad Kaufman } 31175538409bSLiad Kaufman 3118e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3119e705c121SKalle Valo 3120e705c121SKalle Valo dump_data->len = len; 3121e705c121SKalle Valo 3122e705c121SKalle Valo return dump_data; 3123e705c121SKalle Valo } 3124e705c121SKalle Valo 31254cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 31264cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 31274cbb8e50SLuciano Coelho { 3128e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3129e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 31304cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 31314cbb8e50SLuciano Coelho 31324cbb8e50SLuciano Coelho return 0; 31334cbb8e50SLuciano Coelho } 31344cbb8e50SLuciano Coelho 31354cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 31364cbb8e50SLuciano Coelho { 3137e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3138e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 31394cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 31404cbb8e50SLuciano Coelho } 31414cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 31424cbb8e50SLuciano Coelho 3143623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3144623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3145623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3146623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3147623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3148623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3149623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3150623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3151623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3152623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3153623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3154870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3155623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3156623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3157623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3158623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3159623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3160623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3161fb12777aSKirtika Ruchandani .dump_regs = iwl_trans_pcie_dump_regs, \ 3162623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3163623e7766SSara Sharon .d3_resume = iwl_trans_pcie_d3_resume 3164623e7766SSara Sharon 3165623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3166623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3167623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3168623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3169623e7766SSara Sharon #else 3170623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3171623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3172623e7766SSara Sharon 3173e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3174623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3175623e7766SSara Sharon IWL_TRANS_PM_OPS 3176e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3177e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3178e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3179e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3180e705c121SKalle Valo 3181e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3182e705c121SKalle Valo 3183e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3184e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3185e705c121SKalle Valo 3186e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3187e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3188e705c121SKalle Valo 318942db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 319042db09c1SLiad Kaufman 3191d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3192d6d517b7SSara Sharon 3193e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 31940cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3195623e7766SSara Sharon }; 3196e705c121SKalle Valo 3197623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3198623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3199623e7766SSara Sharon IWL_TRANS_PM_OPS 3200623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3201eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3202eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 320377c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3204e705c121SKalle Valo 3205ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3206e705c121SKalle Valo 3207ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3208623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3209623e7766SSara Sharon 32106b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 32116b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3212d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3213e705c121SKalle Valo }; 3214e705c121SKalle Valo 3215e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3216e705c121SKalle Valo const struct pci_device_id *ent, 3217e705c121SKalle Valo const struct iwl_cfg *cfg) 3218e705c121SKalle Valo { 3219e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3220e705c121SKalle Valo struct iwl_trans *trans; 322196a6497bSSara Sharon int ret, addr_size; 3222e705c121SKalle Valo 32235a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 32245a41a86cSSharon Dvir if (ret) 32255a41a86cSSharon Dvir return ERR_PTR(ret); 32265a41a86cSSharon Dvir 3227623e7766SSara Sharon if (cfg->gen2) 3228623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3229623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3230623e7766SSara Sharon else 3231e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 32321ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3233e705c121SKalle Valo if (!trans) 3234e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3235e705c121SKalle Valo 3236e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3237e705c121SKalle Valo 3238e705c121SKalle Valo trans_pcie->trans = trans; 3239326477e4SJohannes Berg trans_pcie->opmode_down = true; 3240e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3241e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3242e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3243e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 32446eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 32456eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 32466eb5e529SEmmanuel Grumbach ret = -ENOMEM; 32476eb5e529SEmmanuel Grumbach goto out_no_pci; 32486eb5e529SEmmanuel Grumbach } 3249e705c121SKalle Valo 3250e705c121SKalle Valo 3251e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3252e705c121SKalle Valo /* 3253e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3254e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3255e705c121SKalle Valo * lot of power. 3256e705c121SKalle Valo */ 3257e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3258e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3259e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3260e705c121SKalle Valo } 3261e705c121SKalle Valo 32626983ba69SSara Sharon if (cfg->use_tfh) { 32632c6262b7SSara Sharon addr_size = 64; 32643cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 32658352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 32666983ba69SSara Sharon } else { 32672c6262b7SSara Sharon addr_size = 36; 32683cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 32696983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 32706983ba69SSara Sharon } 32713cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 32723cd1980bSSara Sharon 3273e705c121SKalle Valo pci_set_master(pdev); 3274e705c121SKalle Valo 327596a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3276e705c121SKalle Valo if (!ret) 327796a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 327896a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3279e705c121SKalle Valo if (ret) { 3280e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3281e705c121SKalle Valo if (!ret) 3282e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3283e705c121SKalle Valo DMA_BIT_MASK(32)); 3284e705c121SKalle Valo /* both attempts failed: */ 3285e705c121SKalle Valo if (ret) { 3286e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 32875a41a86cSSharon Dvir goto out_no_pci; 3288e705c121SKalle Valo } 3289e705c121SKalle Valo } 3290e705c121SKalle Valo 32915a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3292e705c121SKalle Valo if (ret) { 32935a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 32945a41a86cSSharon Dvir goto out_no_pci; 3295e705c121SKalle Valo } 3296e705c121SKalle Valo 32975a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3298e705c121SKalle Valo if (!trans_pcie->hw_base) { 32995a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3300e705c121SKalle Valo ret = -ENODEV; 33015a41a86cSSharon Dvir goto out_no_pci; 3302e705c121SKalle Valo } 3303e705c121SKalle Valo 3304e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3305e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3306e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3307e705c121SKalle Valo 3308e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3309e705c121SKalle Valo iwl_disable_interrupts(trans); 3310e705c121SKalle Valo 3311e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3312e705c121SKalle Valo /* 3313e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3314e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3315e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3316e705c121SKalle Valo * in the old format. 3317e705c121SKalle Valo */ 33186e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3319e705c121SKalle Valo unsigned long flags; 3320e705c121SKalle Valo 3321e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3322e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3323e705c121SKalle Valo 3324e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3325e705c121SKalle Valo if (ret) { 3326e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 33275a41a86cSSharon Dvir goto out_no_pci; 3328e705c121SKalle Valo } 3329e705c121SKalle Valo 3330e705c121SKalle Valo /* 3331e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3332e705c121SKalle Valo * id located at the AUX bus MISC address space. 3333e705c121SKalle Valo */ 3334e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 3335a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 3336e705c121SKalle Valo udelay(2); 3337e705c121SKalle Valo 3338e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3339a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3340a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3341e705c121SKalle Valo 25000); 3342e705c121SKalle Valo if (ret < 0) { 3343e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 33445a41a86cSSharon Dvir goto out_no_pci; 3345e705c121SKalle Valo } 3346e705c121SKalle Valo 334723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3348e705c121SKalle Valo u32 hw_step; 3349e705c121SKalle Valo 335014ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3351e705c121SKalle Valo hw_step |= ENABLE_WFPM; 335214ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 335314ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3354e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3355e705c121SKalle Valo if (hw_step == 0x3) 3356e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3357e705c121SKalle Valo (SILICON_C_STEP << 2); 3358e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3359e705c121SKalle Valo } 3360e705c121SKalle Valo } 3361e705c121SKalle Valo 3362c00ee467SJohannes Berg /* 3363c00ee467SJohannes Berg * 9000-series integrated A-step has a problem with suspend/resume 3364c00ee467SJohannes Berg * and sometimes even causes the whole platform to get stuck. This 3365c00ee467SJohannes Berg * workaround makes the hardware not go into the problematic state. 3366c00ee467SJohannes Berg */ 3367c00ee467SJohannes Berg if (trans->cfg->integrated && 3368c00ee467SJohannes Berg trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3369c00ee467SJohannes Berg CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3370c00ee467SJohannes Berg iwl_set_bit(trans, CSR_HOST_CHICKEN, 3371c00ee467SJohannes Berg CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3372c00ee467SJohannes Berg 3373f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 33741afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 337533708052SLuca Coelho 337633708052SLuca Coelho if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 337733708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3378f6586b69STzipi Peres u32 hw_status; 3379f6586b69STzipi Peres 3380f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 338133708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 338233708052SLuca Coelho /* 338333708052SLuca Coelho * b step fw is the same for physical card and fpga 338433708052SLuca Coelho */ 338533708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 338633708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 338733708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 338833708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 338933708052SLuca Coelho } else { 339033708052SLuca Coelho /* 339133708052SLuca Coelho * a step no FPGA 339233708052SLuca Coelho */ 33932f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3394f6586b69STzipi Peres } 339533708052SLuca Coelho } 3396f6586b69STzipi Peres #endif 33971afb0ae4SHaim Dreyfuss 33982e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3399e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3400e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3401e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3402e705c121SKalle Valo 3403e705c121SKalle Valo /* Initialize the wait queue for commands */ 3404e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3405e705c121SKalle Valo 34064cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 34074cbb8e50SLuciano Coelho 34082e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 34092388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 34102388bd7bSDan Carpenter if (ret) 34115a41a86cSSharon Dvir goto out_no_pci; 34122e5d4a8fSHaim Dreyfuss } else { 3413e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3414e705c121SKalle Valo if (ret) 34155a41a86cSSharon Dvir goto out_no_pci; 3416e705c121SKalle Valo 34175a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 34185a41a86cSSharon Dvir iwl_pcie_isr, 3419e705c121SKalle Valo iwl_pcie_irq_handler, 3420e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3421e705c121SKalle Valo if (ret) { 3422e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3423e705c121SKalle Valo goto out_free_ict; 3424e705c121SKalle Valo } 3425e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 34262e5d4a8fSHaim Dreyfuss } 3427e705c121SKalle Valo 342810a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 342910a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 343010a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 343110a54d81SLuca Coelho 3432b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3433b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3434b3ff1270SLuca Coelho #else 3435b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3436b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3437b3ff1270SLuca Coelho 3438e705c121SKalle Valo return trans; 3439e705c121SKalle Valo 3440e705c121SKalle Valo out_free_ict: 3441e705c121SKalle Valo iwl_pcie_free_ict(trans); 3442e705c121SKalle Valo out_no_pci: 34436eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3444e705c121SKalle Valo iwl_trans_free(trans); 3445e705c121SKalle Valo return ERR_PTR(ret); 3446e705c121SKalle Valo } 3447