1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/interrupt.h> 66e705c121SKalle Valo #include <linux/debugfs.h> 67e705c121SKalle Valo #include <linux/sched.h> 68e705c121SKalle Valo #include <linux/bitops.h> 69e705c121SKalle Valo #include <linux/gfp.h> 70e705c121SKalle Valo #include <linux/vmalloc.h> 7149564a80SLuca Coelho #include <linux/module.h> 72f7805b33SLior Cohen #include <linux/wait.h> 73df67a1beSJohannes Berg #include <linux/seq_file.h> 74e705c121SKalle Valo 75e705c121SKalle Valo #include "iwl-drv.h" 76e705c121SKalle Valo #include "iwl-trans.h" 77e705c121SKalle Valo #include "iwl-csr.h" 78e705c121SKalle Valo #include "iwl-prph.h" 79e705c121SKalle Valo #include "iwl-scd.h" 80e705c121SKalle Valo #include "iwl-agn-hw.h" 81d962f9b1SJohannes Berg #include "fw/error-dump.h" 82520f03eaSShahar S Matityahu #include "fw/dbg.h" 83a89c72ffSJohannes Berg #include "fw/api/tx.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 914290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92a6d24fadSRajat Jain { 93c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 94c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 95c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 96a6d24fadSRajat Jain #define PREFIX_LEN 32 97a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 98a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 99a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 100a6d24fadSRajat Jain char *prefix; 101a6d24fadSRajat Jain 102a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 103a6d24fadSRajat Jain return; 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Should be a multiple of 4 */ 106a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 107c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 108c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 109c4d3f2eeSLuca Coelho 110a6d24fadSRajat Jain /* Alloc a max size buffer */ 111a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 112c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 113c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 114c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 115c4d3f2eeSLuca Coelho 116a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 117a6d24fadSRajat Jain if (!buf) 118a6d24fadSRajat Jain return; 119a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 122a6d24fadSRajat Jain 123a6d24fadSRajat Jain /* Print wifi device registers */ 124a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 125a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 126a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 128a6d24fadSRajat Jain goto err_read; 129a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 130a6d24fadSRajat Jain 131a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 132c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 133a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 134a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 135a6d24fadSRajat Jain 136a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 137a6d24fadSRajat Jain if (pos) { 138a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 139a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 140a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 141a6d24fadSRajat Jain goto err_read; 142a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 143a6d24fadSRajat Jain 32, 4, buf, i, 0); 144a6d24fadSRajat Jain } 145a6d24fadSRajat Jain 146a6d24fadSRajat Jain /* Print parent device registers next */ 147a6d24fadSRajat Jain if (!pdev->bus->self) 148a6d24fadSRajat Jain goto out; 149a6d24fadSRajat Jain 150a6d24fadSRajat Jain pdev = pdev->bus->self; 151a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 152a6d24fadSRajat Jain 153a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 154a6d24fadSRajat Jain pci_name(pdev)); 155c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 156a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 157a6d24fadSRajat Jain goto err_read; 158a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 159a6d24fadSRajat Jain 160a6d24fadSRajat Jain /* Print root port AER registers */ 161a6d24fadSRajat Jain pos = 0; 162a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 163a6d24fadSRajat Jain if (pdev) 164a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 165a6d24fadSRajat Jain if (pos) { 166a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 167a6d24fadSRajat Jain pci_name(pdev)); 168a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 169a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 170a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 171a6d24fadSRajat Jain goto err_read; 172a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 173a6d24fadSRajat Jain 4, buf, i, 0); 174a6d24fadSRajat Jain } 175f3402d6dSSara Sharon goto out; 176a6d24fadSRajat Jain 177a6d24fadSRajat Jain err_read: 178a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 179a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 180a6d24fadSRajat Jain out: 181a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 182a6d24fadSRajat Jain kfree(buf); 183a6d24fadSRajat Jain } 184a6d24fadSRajat Jain 185870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 186870c2a11SGolan Ben Ami { 187870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1886dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 189870c2a11SGolan Ben Ami usleep_range(5000, 6000); 190870c2a11SGolan Ben Ami } 191870c2a11SGolan Ben Ami 192e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 193e705c121SKalle Valo { 19469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 195e705c121SKalle Valo 19669f0e505SShahar S Matityahu if (!fw_mon->size) 19769f0e505SShahar S Matityahu return; 19869f0e505SShahar S Matityahu 19969f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 20069f0e505SShahar S Matityahu fw_mon->physical); 20169f0e505SShahar S Matityahu 20269f0e505SShahar S Matityahu fw_mon->block = NULL; 20369f0e505SShahar S Matityahu fw_mon->physical = 0; 20469f0e505SShahar S Matityahu fw_mon->size = 0; 205e705c121SKalle Valo } 206e705c121SKalle Valo 20788964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20888964b2eSSara Sharon u8 max_power, u8 min_power) 209e705c121SKalle Valo { 21069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 21169f0e505SShahar S Matityahu void *block = NULL; 21269f0e505SShahar S Matityahu dma_addr_t physical = 0; 213e705c121SKalle Valo u32 size = 0; 214e705c121SKalle Valo u8 power; 215e705c121SKalle Valo 21669f0e505SShahar S Matityahu if (fw_mon->size) 21769f0e505SShahar S Matityahu return; 21869f0e505SShahar S Matityahu 21988964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 220e705c121SKalle Valo size = BIT(power); 22169f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 2222d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 22369f0e505SShahar S Matityahu if (!block) 224e705c121SKalle Valo continue; 225e705c121SKalle Valo 226e705c121SKalle Valo IWL_INFO(trans, 227c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 228c5f97542SShahar S Matityahu size); 229e705c121SKalle Valo break; 230e705c121SKalle Valo } 231e705c121SKalle Valo 23269f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 233e705c121SKalle Valo return; 234e705c121SKalle Valo 235e705c121SKalle Valo if (power != max_power) 236e705c121SKalle Valo IWL_ERR(trans, 237e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 238e705c121SKalle Valo (unsigned long)BIT(power - 10), 239e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 240e705c121SKalle Valo 24169f0e505SShahar S Matityahu fw_mon->block = block; 24269f0e505SShahar S Matityahu fw_mon->physical = physical; 24369f0e505SShahar S Matityahu fw_mon->size = size; 24488964b2eSSara Sharon } 24588964b2eSSara Sharon 24688964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24788964b2eSSara Sharon { 24888964b2eSSara Sharon if (!max_power) { 24988964b2eSSara Sharon /* default max_power is maximum */ 25088964b2eSSara Sharon max_power = 26; 25188964b2eSSara Sharon } else { 25288964b2eSSara Sharon max_power += 11; 25388964b2eSSara Sharon } 25488964b2eSSara Sharon 25588964b2eSSara Sharon if (WARN(max_power > 26, 25688964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25788964b2eSSara Sharon max_power)) 25888964b2eSSara Sharon return; 25988964b2eSSara Sharon 26069f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 26188964b2eSSara Sharon return; 26288964b2eSSara Sharon 26388964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 264e705c121SKalle Valo } 265e705c121SKalle Valo 266e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 267e705c121SKalle Valo { 268e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 269e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 270e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 271e705c121SKalle Valo } 272e705c121SKalle Valo 273e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 274e705c121SKalle Valo { 275e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 276e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 277e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 278e705c121SKalle Valo } 279e705c121SKalle Valo 280e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 281e705c121SKalle Valo { 282e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 283e705c121SKalle Valo return; 284e705c121SKalle Valo 285e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 286e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 287e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 288e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 289e705c121SKalle Valo else 290e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 291e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 292e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 293e705c121SKalle Valo } 294e705c121SKalle Valo 295e705c121SKalle Valo /* PCI registers */ 296e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 297e705c121SKalle Valo 298eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 299e705c121SKalle Valo { 300e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301e705c121SKalle Valo u16 lctl; 302e705c121SKalle Valo u16 cap; 303e705c121SKalle Valo 304e705c121SKalle Valo /* 305cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 306cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 307cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 308e705c121SKalle Valo */ 3093d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 310cc894b85SLuca Coelho 311cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 312e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 313e705c121SKalle Valo 314e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 315e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 316d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 317e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 318e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 319e705c121SKalle Valo } 320e705c121SKalle Valo 321e705c121SKalle Valo /* 322e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 323e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 324e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 325e705c121SKalle Valo */ 326e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 327e705c121SKalle Valo { 32852b6e168SEmmanuel Grumbach int ret; 32952b6e168SEmmanuel Grumbach 330e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 331e705c121SKalle Valo 332e705c121SKalle Valo /* 333e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 334e705c121SKalle Valo * bits already set by default after reset. 335e705c121SKalle Valo */ 336e705c121SKalle Valo 337e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 338286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 339e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 340e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 341e705c121SKalle Valo 342e705c121SKalle Valo /* 343e705c121SKalle Valo * Disable L0s without affecting L1; 344e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 345e705c121SKalle Valo */ 346e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 347e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 348e705c121SKalle Valo 349e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 350e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 351e705c121SKalle Valo 352e705c121SKalle Valo /* 353e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 354e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 355e705c121SKalle Valo */ 356e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 357e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 358e705c121SKalle Valo 359e705c121SKalle Valo iwl_pcie_apm_config(trans); 360e705c121SKalle Valo 361e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 362286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 36377d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 364e705c121SKalle Valo 3657d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 366c96b5eecSJohannes Berg if (ret) 36752b6e168SEmmanuel Grumbach return ret; 368e705c121SKalle Valo 369e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 370e705c121SKalle Valo /* 371e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 372e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 373e705c121SKalle Valo * not related to host_interrupt_operation_mode. 374e705c121SKalle Valo * 375e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 376e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 377e705c121SKalle Valo * that we wake up from L1 on time. 378e705c121SKalle Valo * 379e705c121SKalle Valo * This looks weird: read twice the same register, discard the 380e705c121SKalle Valo * value, set a bit, and yet again, read that same register 381e705c121SKalle Valo * just to discard the value. But that's the way the hardware 382e705c121SKalle Valo * seems to like it. 383e705c121SKalle Valo */ 384e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 385e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 386e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 387e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 388e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 389e705c121SKalle Valo } 390e705c121SKalle Valo 391e705c121SKalle Valo /* 392e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 393e705c121SKalle Valo * 394e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 395e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 396e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 397e705c121SKalle Valo */ 398e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 399e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 400e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 401e705c121SKalle Valo udelay(20); 402e705c121SKalle Valo 403e705c121SKalle Valo /* Disable L1-Active */ 404e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 405e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 406e705c121SKalle Valo 407e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 408e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 409e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 410e705c121SKalle Valo } 411e705c121SKalle Valo 412e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 413e705c121SKalle Valo 41452b6e168SEmmanuel Grumbach return 0; 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo /* 418e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 419e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 420e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 421e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 422e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 423e705c121SKalle Valo */ 424e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 425e705c121SKalle Valo { 426e705c121SKalle Valo int ret; 427e705c121SKalle Valo u32 apmg_gp1_reg; 428e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 429e705c121SKalle Valo u32 dl_cfg_reg; 430e705c121SKalle Valo 431e705c121SKalle Valo /* Force XTAL ON */ 432e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 433e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 434e705c121SKalle Valo 435870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 436e705c121SKalle Valo 4377d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 438c96b5eecSJohannes Berg if (WARN_ON(ret)) { 439e705c121SKalle Valo /* Release XTAL ON request */ 440e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 441e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 442e705c121SKalle Valo return; 443e705c121SKalle Valo } 444e705c121SKalle Valo 445e705c121SKalle Valo /* 446e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 447e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 448e705c121SKalle Valo */ 449e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 450e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 451e705c121SKalle Valo 452e705c121SKalle Valo /* 453e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 454e705c121SKalle Valo * caused by APMG idle state. 455e705c121SKalle Valo */ 456e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 457e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 458e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 459e705c121SKalle Valo apmg_xtal_cfg_reg | 460e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 461e705c121SKalle Valo 462870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 463e705c121SKalle Valo 464e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 465e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 466e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 467e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 468e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 469e705c121SKalle Valo 470e705c121SKalle Valo /* Clear delay line clock power up */ 471e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 472e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 473e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 474e705c121SKalle Valo 475e705c121SKalle Valo /* 476e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 477e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 478e705c121SKalle Valo */ 479e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 480e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 481e705c121SKalle Valo 482e705c121SKalle Valo /* 483e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 484e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 485e705c121SKalle Valo */ 4866dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 487e705c121SKalle Valo 488e705c121SKalle Valo /* Activates XTAL resources monitor */ 489e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 490e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 491e705c121SKalle Valo 492e705c121SKalle Valo /* Release XTAL ON request */ 493e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 494e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 495e705c121SKalle Valo udelay(10); 496e705c121SKalle Valo 497e705c121SKalle Valo /* Release APMG XTAL */ 498e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 499e705c121SKalle Valo apmg_xtal_cfg_reg & 500e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 501e705c121SKalle Valo } 502e705c121SKalle Valo 503e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 504e705c121SKalle Valo { 505e8c8935eSJohannes Berg int ret; 506e705c121SKalle Valo 507e705c121SKalle Valo /* stop device's busmaster DMA activity */ 5086dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 509e705c121SKalle Valo 5106dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 5116dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 5126dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 513e705c121SKalle Valo if (ret < 0) 514e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 515e705c121SKalle Valo 516e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 517e705c121SKalle Valo } 518e705c121SKalle Valo 519e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 520e705c121SKalle Valo { 521e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 522e705c121SKalle Valo 523e705c121SKalle Valo if (op_mode_leave) { 524e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 525e705c121SKalle Valo iwl_pcie_apm_init(trans); 526e705c121SKalle Valo 527e705c121SKalle Valo /* inform ME that we are leaving */ 528286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 529e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 530e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 531286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 53279b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 533e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 534e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 535e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 536e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 537e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 538e705c121SKalle Valo mdelay(1); 539e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 540e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 541e705c121SKalle Valo } 542e705c121SKalle Valo mdelay(5); 543e705c121SKalle Valo } 544e705c121SKalle Valo 545e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 546e705c121SKalle Valo 547e705c121SKalle Valo /* Stop device's DMA activity */ 548e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 549e705c121SKalle Valo 550e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 551e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 552e705c121SKalle Valo return; 553e705c121SKalle Valo } 554e705c121SKalle Valo 555870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 556e705c121SKalle Valo 557e705c121SKalle Valo /* 558e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 559e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 560e705c121SKalle Valo */ 5616dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 562e705c121SKalle Valo } 563e705c121SKalle Valo 564e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 565e705c121SKalle Valo { 566e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 56752b6e168SEmmanuel Grumbach int ret; 568e705c121SKalle Valo 569e705c121SKalle Valo /* nic_init */ 570e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 57152b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 572e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 573e705c121SKalle Valo 57452b6e168SEmmanuel Grumbach if (ret) 57552b6e168SEmmanuel Grumbach return ret; 57652b6e168SEmmanuel Grumbach 577e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 578e705c121SKalle Valo 579e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 580e705c121SKalle Valo 581e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 582e705c121SKalle Valo iwl_pcie_rx_init(trans); 583e705c121SKalle Valo 584e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 585e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 586e705c121SKalle Valo return -ENOMEM; 587e705c121SKalle Valo 588286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 589e705c121SKalle Valo /* enable shadow regs in HW */ 590e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 591e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 592e705c121SKalle Valo } 593e705c121SKalle Valo 594e705c121SKalle Valo return 0; 595e705c121SKalle Valo } 596e705c121SKalle Valo 597e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 598e705c121SKalle Valo 599e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 600e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 601e705c121SKalle Valo { 602e705c121SKalle Valo int ret; 603e705c121SKalle Valo 604e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 605e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 606e705c121SKalle Valo 607e705c121SKalle Valo /* See if we got it */ 608e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 609e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 610e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 611e705c121SKalle Valo HW_READY_TIMEOUT); 612e705c121SKalle Valo 613e705c121SKalle Valo if (ret >= 0) 614e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 615e705c121SKalle Valo 616e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 617e705c121SKalle Valo return ret; 618e705c121SKalle Valo } 619e705c121SKalle Valo 620e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 621eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 622e705c121SKalle Valo { 623e705c121SKalle Valo int ret; 624e705c121SKalle Valo int t = 0; 625e705c121SKalle Valo int iter; 626e705c121SKalle Valo 627e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 628e705c121SKalle Valo 629e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 630e705c121SKalle Valo /* If the card is ready, exit 0 */ 631e705c121SKalle Valo if (ret >= 0) 632e705c121SKalle Valo return 0; 633e705c121SKalle Valo 634e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 635e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 636192185d6SJohannes Berg usleep_range(1000, 2000); 637e705c121SKalle Valo 638e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 639e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 640e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 641e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 642e705c121SKalle Valo 643e705c121SKalle Valo do { 644e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 645e705c121SKalle Valo if (ret >= 0) 646e705c121SKalle Valo return 0; 647e705c121SKalle Valo 648e705c121SKalle Valo usleep_range(200, 1000); 649e705c121SKalle Valo t += 200; 650e705c121SKalle Valo } while (t < 150000); 651e705c121SKalle Valo msleep(25); 652e705c121SKalle Valo } 653e705c121SKalle Valo 654e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 655e705c121SKalle Valo 656e705c121SKalle Valo return ret; 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo /* 660e705c121SKalle Valo * ucode 661e705c121SKalle Valo */ 662564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 663564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 664564cdce7SSara Sharon u32 byte_cnt) 665e705c121SKalle Valo { 666bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 667e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 668e705c121SKalle Valo 669bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 670e705c121SKalle Valo dst_addr); 671e705c121SKalle Valo 672bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 673e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 674e705c121SKalle Valo 675bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 676e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 677e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 678e705c121SKalle Valo 679bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 680bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 681bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 682e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 683e705c121SKalle Valo 684bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 685e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 686e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 687e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 688564cdce7SSara Sharon } 689e705c121SKalle Valo 690564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 691564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 692564cdce7SSara Sharon u32 byte_cnt) 693564cdce7SSara Sharon { 694564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 695564cdce7SSara Sharon unsigned long flags; 696564cdce7SSara Sharon int ret; 697564cdce7SSara Sharon 698564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 699564cdce7SSara Sharon 700564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 701564cdce7SSara Sharon return -EIO; 702564cdce7SSara Sharon 703564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 704564cdce7SSara Sharon byte_cnt); 705bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 706bac842daSEmmanuel Grumbach 707e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 708e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 709e705c121SKalle Valo if (!ret) { 710e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 711fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 712e705c121SKalle Valo return -ETIMEDOUT; 713e705c121SKalle Valo } 714e705c121SKalle Valo 715e705c121SKalle Valo return 0; 716e705c121SKalle Valo } 717e705c121SKalle Valo 718e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 719e705c121SKalle Valo const struct fw_desc *section) 720e705c121SKalle Valo { 721e705c121SKalle Valo u8 *v_addr; 722e705c121SKalle Valo dma_addr_t p_addr; 723e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 724e705c121SKalle Valo int ret = 0; 725e705c121SKalle Valo 726e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 727e705c121SKalle Valo section_num); 728e705c121SKalle Valo 729e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 730e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 731e705c121SKalle Valo if (!v_addr) { 732e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 733e705c121SKalle Valo chunk_sz = PAGE_SIZE; 734e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 735e705c121SKalle Valo &p_addr, GFP_KERNEL); 736e705c121SKalle Valo if (!v_addr) 737e705c121SKalle Valo return -ENOMEM; 738e705c121SKalle Valo } 739e705c121SKalle Valo 740e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 741e705c121SKalle Valo u32 copy_size, dst_addr; 742e705c121SKalle Valo bool extended_addr = false; 743e705c121SKalle Valo 744e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 745e705c121SKalle Valo dst_addr = section->offset + offset; 746e705c121SKalle Valo 747e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 748e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 749e705c121SKalle Valo extended_addr = true; 750e705c121SKalle Valo 751e705c121SKalle Valo if (extended_addr) 752e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 753e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 754e705c121SKalle Valo 755e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 756e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 757e705c121SKalle Valo copy_size); 758e705c121SKalle Valo 759e705c121SKalle Valo if (extended_addr) 760e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 761e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 762e705c121SKalle Valo 763e705c121SKalle Valo if (ret) { 764e705c121SKalle Valo IWL_ERR(trans, 765e705c121SKalle Valo "Could not load the [%d] uCode section\n", 766e705c121SKalle Valo section_num); 767e705c121SKalle Valo break; 768e705c121SKalle Valo } 769e705c121SKalle Valo } 770e705c121SKalle Valo 771e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 772e705c121SKalle Valo return ret; 773e705c121SKalle Valo } 774e705c121SKalle Valo 775e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 776e705c121SKalle Valo const struct fw_img *image, 777e705c121SKalle Valo int cpu, 778e705c121SKalle Valo int *first_ucode_section) 779e705c121SKalle Valo { 780e705c121SKalle Valo int shift_param; 781e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 782e705c121SKalle Valo u32 val, last_read_idx = 0; 783e705c121SKalle Valo 784e705c121SKalle Valo if (cpu == 1) { 785e705c121SKalle Valo shift_param = 0; 786e705c121SKalle Valo *first_ucode_section = 0; 787e705c121SKalle Valo } else { 788e705c121SKalle Valo shift_param = 16; 789e705c121SKalle Valo (*first_ucode_section)++; 790e705c121SKalle Valo } 791e705c121SKalle Valo 792eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 793e705c121SKalle Valo last_read_idx = i; 794e705c121SKalle Valo 795e705c121SKalle Valo /* 796e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 797e705c121SKalle Valo * CPU1 to CPU2. 798e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 799e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 800e705c121SKalle Valo */ 801e705c121SKalle Valo if (!image->sec[i].data || 802e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 803e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 804e705c121SKalle Valo IWL_DEBUG_FW(trans, 805e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 806e705c121SKalle Valo i); 807e705c121SKalle Valo break; 808e705c121SKalle Valo } 809e705c121SKalle Valo 810e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 811e705c121SKalle Valo if (ret) 812e705c121SKalle Valo return ret; 813e705c121SKalle Valo 814d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 815e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 816e705c121SKalle Valo val = val | (sec_num << shift_param); 817e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 818eda50cdeSSara Sharon 819e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 820e705c121SKalle Valo } 821e705c121SKalle Valo 822e705c121SKalle Valo *first_ucode_section = last_read_idx; 823e705c121SKalle Valo 8242aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8252aabdbdcSEmmanuel Grumbach 826286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 827e705c121SKalle Valo if (cpu == 1) 828d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 829d6a2c5c7SSara Sharon 0xFFFF); 830e705c121SKalle Valo else 831d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 832d6a2c5c7SSara Sharon 0xFFFFFFFF); 833d6a2c5c7SSara Sharon } else { 834d6a2c5c7SSara Sharon if (cpu == 1) 835d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 836d6a2c5c7SSara Sharon 0xFFFF); 837d6a2c5c7SSara Sharon else 838d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 839d6a2c5c7SSara Sharon 0xFFFFFFFF); 840d6a2c5c7SSara Sharon } 841e705c121SKalle Valo 842e705c121SKalle Valo return 0; 843e705c121SKalle Valo } 844e705c121SKalle Valo 845e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 846e705c121SKalle Valo const struct fw_img *image, 847e705c121SKalle Valo int cpu, 848e705c121SKalle Valo int *first_ucode_section) 849e705c121SKalle Valo { 850e705c121SKalle Valo int i, ret = 0; 851e705c121SKalle Valo u32 last_read_idx = 0; 852e705c121SKalle Valo 8533ce4a038SKirtika Ruchandani if (cpu == 1) 854e705c121SKalle Valo *first_ucode_section = 0; 8553ce4a038SKirtika Ruchandani else 856e705c121SKalle Valo (*first_ucode_section)++; 857e705c121SKalle Valo 858eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 859e705c121SKalle Valo last_read_idx = i; 860e705c121SKalle Valo 861e705c121SKalle Valo /* 862e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 863e705c121SKalle Valo * CPU1 to CPU2. 864e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 865e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 866e705c121SKalle Valo */ 867e705c121SKalle Valo if (!image->sec[i].data || 868e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 869e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 870e705c121SKalle Valo IWL_DEBUG_FW(trans, 871e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 872e705c121SKalle Valo i); 873e705c121SKalle Valo break; 874e705c121SKalle Valo } 875e705c121SKalle Valo 876e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 877e705c121SKalle Valo if (ret) 878e705c121SKalle Valo return ret; 879e705c121SKalle Valo } 880e705c121SKalle Valo 881e705c121SKalle Valo *first_ucode_section = last_read_idx; 882e705c121SKalle Valo 883e705c121SKalle Valo return 0; 884e705c121SKalle Valo } 885e705c121SKalle Valo 886593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 887593fae3eSShahar S Matityahu { 888593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 889593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 890593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 891593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 892593fae3eSShahar S Matityahu 893593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 894593fae3eSShahar S Matityahu return; 895593fae3eSShahar S Matityahu 896593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 897593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 898593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 899593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 900593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 901593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 902593fae3eSShahar S Matityahu 903593fae3eSShahar S Matityahu return; 904593fae3eSShahar S Matityahu } 905593fae3eSShahar S Matityahu 906593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 907593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 908593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 909593fae3eSShahar S Matityahu return; 910593fae3eSShahar S Matityahu 911593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 912593fae3eSShahar S Matityahu 913593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 914593fae3eSShahar S Matityahu alloc_id); 915593fae3eSShahar S Matityahu 916593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 917593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 918593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 919593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 920593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 921593fae3eSShahar S Matityahu } 922593fae3eSShahar S Matityahu 923c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 924e705c121SKalle Valo { 92591c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 92669f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 927e705c121SKalle Valo int i; 928e705c121SKalle Valo 929a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 930593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9317a14c23dSSara Sharon return; 9327a14c23dSSara Sharon } 9337a14c23dSSara Sharon 934e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 935e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 936e705c121SKalle Valo 937e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 938e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 939e705c121SKalle Valo else 940e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 941e705c121SKalle Valo 94291c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 943e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 944e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 945e705c121SKalle Valo 946e705c121SKalle Valo switch (dest->reg_ops[i].op) { 947e705c121SKalle Valo case CSR_ASSIGN: 948e705c121SKalle Valo iwl_write32(trans, addr, val); 949e705c121SKalle Valo break; 950e705c121SKalle Valo case CSR_SETBIT: 951e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 952e705c121SKalle Valo break; 953e705c121SKalle Valo case CSR_CLEARBIT: 954e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 955e705c121SKalle Valo break; 956e705c121SKalle Valo case PRPH_ASSIGN: 957e705c121SKalle Valo iwl_write_prph(trans, addr, val); 958e705c121SKalle Valo break; 959e705c121SKalle Valo case PRPH_SETBIT: 960e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 961e705c121SKalle Valo break; 962e705c121SKalle Valo case PRPH_CLEARBIT: 963e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 964e705c121SKalle Valo break; 965e705c121SKalle Valo case PRPH_BLOCKBIT: 966e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 967e705c121SKalle Valo IWL_ERR(trans, 968e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 969e705c121SKalle Valo val, addr); 970e705c121SKalle Valo goto monitor; 971e705c121SKalle Valo } 972e705c121SKalle Valo break; 973e705c121SKalle Valo default: 974e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 975e705c121SKalle Valo dest->reg_ops[i].op); 976e705c121SKalle Valo break; 977e705c121SKalle Valo } 978e705c121SKalle Valo } 979e705c121SKalle Valo 980e705c121SKalle Valo monitor: 98169f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 982e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 98369f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 984286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 985e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98669f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 98769f0e505SShahar S Matityahu 256) >> dest->end_shift); 98862d7476dSEmmanuel Grumbach else 98962d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99069f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 99162d7476dSEmmanuel Grumbach dest->end_shift); 992e705c121SKalle Valo } 993e705c121SKalle Valo } 994e705c121SKalle Valo 995e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 996e705c121SKalle Valo const struct fw_img *image) 997e705c121SKalle Valo { 998e705c121SKalle Valo int ret = 0; 999e705c121SKalle Valo int first_ucode_section; 1000e705c121SKalle Valo 1001e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1002e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1003e705c121SKalle Valo 1004e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1005e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1006e705c121SKalle Valo if (ret) 1007e705c121SKalle Valo return ret; 1008e705c121SKalle Valo 1009e705c121SKalle Valo if (image->is_dual_cpus) { 1010e705c121SKalle Valo /* set CPU2 header address */ 1011e705c121SKalle Valo iwl_write_prph(trans, 1012e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1013e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1014e705c121SKalle Valo 1015e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1016e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1017e705c121SKalle Valo &first_ucode_section); 1018e705c121SKalle Valo if (ret) 1019e705c121SKalle Valo return ret; 1020e705c121SKalle Valo } 1021e705c121SKalle Valo 1022e705c121SKalle Valo /* supported for 7000 only for the moment */ 1023e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1024286ca8ebSLuca Coelho trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 102569f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 1026e705c121SKalle Valo 102769f0e505SShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 102869f0e505SShahar S Matityahu if (fw_mon->size) { 1029e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 103069f0e505SShahar S Matityahu fw_mon->physical >> 4); 1031e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 103269f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 4); 1033e705c121SKalle Valo } 10347a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1035e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1036e705c121SKalle Valo } 1037e705c121SKalle Valo 10382aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10392aabdbdcSEmmanuel Grumbach 1040e705c121SKalle Valo /* release CPU reset */ 1041e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1042e705c121SKalle Valo 1043e705c121SKalle Valo return 0; 1044e705c121SKalle Valo } 1045e705c121SKalle Valo 1046e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1047e705c121SKalle Valo const struct fw_img *image) 1048e705c121SKalle Valo { 1049e705c121SKalle Valo int ret = 0; 1050e705c121SKalle Valo int first_ucode_section; 1051e705c121SKalle Valo 1052e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1053e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1054e705c121SKalle Valo 10557a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1056e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1057e705c121SKalle Valo 105882ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 105982ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 106082ea7966SSara Sharon 106182ea7966SSara Sharon /* 106282ea7966SSara Sharon * Set default value. On resume reading the values that were 106382ea7966SSara Sharon * zeored can provide debug data on the resume flow. 106482ea7966SSara Sharon * This is for debugging only and has no functional impact. 106582ea7966SSara Sharon */ 106682ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 106782ea7966SSara Sharon 1068e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1069e705c121SKalle Valo /* release CPU reset */ 1070e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1071e705c121SKalle Valo 1072e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1073e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1074e705c121SKalle Valo &first_ucode_section); 1075e705c121SKalle Valo if (ret) 1076e705c121SKalle Valo return ret; 1077e705c121SKalle Valo 1078e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1079e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1080e705c121SKalle Valo &first_ucode_section); 1081e705c121SKalle Valo } 1082e705c121SKalle Valo 10839ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1084727c02dfSSara Sharon { 1085326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1086727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1087326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1088326477e4SJohannes Berg bool report; 1089727c02dfSSara Sharon 1090326477e4SJohannes Berg if (hw_rfkill) { 1091326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1092326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1093326477e4SJohannes Berg } else { 1094326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1095326477e4SJohannes Berg if (trans_pcie->opmode_down) 1096326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1097326477e4SJohannes Berg } 1098727c02dfSSara Sharon 1099326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1100326477e4SJohannes Berg 1101326477e4SJohannes Berg if (prev != report) 1102326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1103727c02dfSSara Sharon 1104727c02dfSSara Sharon return hw_rfkill; 1105727c02dfSSara Sharon } 1106727c02dfSSara Sharon 11077ca00409SHaim Dreyfuss struct iwl_causes_list { 11087ca00409SHaim Dreyfuss u32 cause_num; 11097ca00409SHaim Dreyfuss u32 mask_reg; 11107ca00409SHaim Dreyfuss u8 addr; 11117ca00409SHaim Dreyfuss }; 11127ca00409SHaim Dreyfuss 11137ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11147ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11157ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11167ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11177ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11187ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11197ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1120ff911dcaSShaul Triebitz {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 11217ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11227ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11237ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11247ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11257ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11267ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11277ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11287ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11297ca00409SHaim Dreyfuss }; 11307ca00409SHaim Dreyfuss 11317ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11327ca00409SHaim Dreyfuss { 11337ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11347ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11353681021fSJohannes Berg int i, arr_size = ARRAY_SIZE(causes_list); 11363681021fSJohannes Berg struct iwl_causes_list *causes = causes_list; 11377ca00409SHaim Dreyfuss 11387ca00409SHaim Dreyfuss /* 11397ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11407ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11417ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11427ca00409SHaim Dreyfuss */ 11439b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11449b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11459b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11469b58419eSGolan Ben Ami causes[i].cause_num); 11477ca00409SHaim Dreyfuss } 11487ca00409SHaim Dreyfuss } 11497ca00409SHaim Dreyfuss 11507ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11517ca00409SHaim Dreyfuss { 11527ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11537ca00409SHaim Dreyfuss u32 offset = 11547ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11557ca00409SHaim Dreyfuss u32 val, idx; 11567ca00409SHaim Dreyfuss 11577ca00409SHaim Dreyfuss /* 11587ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11597ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11607ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11617ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11627ca00409SHaim Dreyfuss */ 11637ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11647ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11657ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11667ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11677ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11687ca00409SHaim Dreyfuss } 11697ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11707ca00409SHaim Dreyfuss 11717ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11727ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11737ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11747ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11757ca00409SHaim Dreyfuss 11767ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11777ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11787ca00409SHaim Dreyfuss } 11797ca00409SHaim Dreyfuss 118077c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11817ca00409SHaim Dreyfuss { 11827ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11837ca00409SHaim Dreyfuss 11847ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1185286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1186d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1187ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11887ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11897ca00409SHaim Dreyfuss return; 11907ca00409SHaim Dreyfuss } 1191d7270d61SHaim Dreyfuss /* 1192d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1193d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1194d7270d61SHaim Dreyfuss * prph. 1195d7270d61SHaim Dreyfuss */ 1196d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1197ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11987ca00409SHaim Dreyfuss 11997ca00409SHaim Dreyfuss /* 12007ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12017ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12027ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12037ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12047ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12057ca00409SHaim Dreyfuss */ 12067ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12077ca00409SHaim Dreyfuss 12087ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 120983730058SHaim Dreyfuss } 12107ca00409SHaim Dreyfuss 121183730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 121283730058SHaim Dreyfuss { 121383730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 121483730058SHaim Dreyfuss 121583730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 121683730058SHaim Dreyfuss 121783730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 121883730058SHaim Dreyfuss return; 121983730058SHaim Dreyfuss 122083730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12217ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 122283730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12237ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12247ca00409SHaim Dreyfuss } 12257ca00409SHaim Dreyfuss 1226bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1227e705c121SKalle Valo { 1228e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1229e705c121SKalle Valo 1230e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1231e705c121SKalle Valo 1232e705c121SKalle Valo if (trans_pcie->is_down) 1233e705c121SKalle Valo return; 1234e705c121SKalle Valo 1235e705c121SKalle Valo trans_pcie->is_down = true; 1236e705c121SKalle Valo 1237e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1238e705c121SKalle Valo iwl_disable_interrupts(trans); 1239e705c121SKalle Valo 1240e705c121SKalle Valo /* device going down, Stop using ICT table */ 1241e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1242e705c121SKalle Valo 1243e705c121SKalle Valo /* 1244e705c121SKalle Valo * If a HW restart happens during firmware loading, 1245e705c121SKalle Valo * then the firmware loading might call this function 1246e705c121SKalle Valo * and later it might be called again due to the 1247e705c121SKalle Valo * restart. So don't process again if the device is 1248e705c121SKalle Valo * already dead. 1249e705c121SKalle Valo */ 1250e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1251a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1252a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1253e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1254e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1255e705c121SKalle Valo 1256e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1257e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1258e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1259e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1260e705c121SKalle Valo udelay(5); 1261e705c121SKalle Valo } 1262e705c121SKalle Valo } 1263e705c121SKalle Valo 1264e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1265e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12666dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1267e705c121SKalle Valo 1268e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1269e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1270e705c121SKalle Valo 1271870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1272e705c121SKalle Valo 1273e705c121SKalle Valo /* 1274f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1275f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1276f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1277f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1278f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1279f4a1f04aSGolan Ben Ami */ 1280f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1281f4a1f04aSGolan Ben Ami 1282f4a1f04aSGolan Ben Ami /* 1283e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1284e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1285e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1286e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1287e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1288e705c121SKalle Valo */ 1289e705c121SKalle Valo iwl_disable_interrupts(trans); 1290e705c121SKalle Valo 1291e705c121SKalle Valo /* clear all status bits */ 1292e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1293e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1294e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1295e705c121SKalle Valo 1296e705c121SKalle Valo /* 1297e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1298e705c121SKalle Valo * interrupt 1299e705c121SKalle Valo */ 1300e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1301e705c121SKalle Valo 1302a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1303e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1304e705c121SKalle Valo } 1305e705c121SKalle Valo 1306eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13072e5d4a8fSHaim Dreyfuss { 13082e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13092e5d4a8fSHaim Dreyfuss 13102e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13112e5d4a8fSHaim Dreyfuss int i; 13122e5d4a8fSHaim Dreyfuss 1313496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13142e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13152e5d4a8fSHaim Dreyfuss } else { 13162e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13172e5d4a8fSHaim Dreyfuss } 13182e5d4a8fSHaim Dreyfuss } 13192e5d4a8fSHaim Dreyfuss 1320a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1321a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1322a6bd005fSEmmanuel Grumbach { 1323a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1324a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1325a6bd005fSEmmanuel Grumbach int ret; 1326a6bd005fSEmmanuel Grumbach 1327a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1328a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1329a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1330a6bd005fSEmmanuel Grumbach ret = -EIO; 1331a6bd005fSEmmanuel Grumbach goto out; 1332a6bd005fSEmmanuel Grumbach } 1333a6bd005fSEmmanuel Grumbach 1334a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1335a6bd005fSEmmanuel Grumbach 1336a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1337a6bd005fSEmmanuel Grumbach 1338a6bd005fSEmmanuel Grumbach /* 1339a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1340a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1341a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1342a6bd005fSEmmanuel Grumbach */ 1343a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1344a6bd005fSEmmanuel Grumbach 1345a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13462e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1347a6bd005fSEmmanuel Grumbach 1348a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1349a6bd005fSEmmanuel Grumbach 1350a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13519ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1352a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1353a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1354a6bd005fSEmmanuel Grumbach goto out; 1355a6bd005fSEmmanuel Grumbach } 1356a6bd005fSEmmanuel Grumbach 1357a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1358a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1359a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1360a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136120aa99bbSAnton Protopopov ret = -EIO; 1362a6bd005fSEmmanuel Grumbach goto out; 1363a6bd005fSEmmanuel Grumbach } 1364a6bd005fSEmmanuel Grumbach 1365a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1366a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1367a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1368a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1369a6bd005fSEmmanuel Grumbach 1370a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1371a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1372a6bd005fSEmmanuel Grumbach 1373a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1374a6bd005fSEmmanuel Grumbach if (ret) { 1375a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1376a6bd005fSEmmanuel Grumbach goto out; 1377a6bd005fSEmmanuel Grumbach } 1378a6bd005fSEmmanuel Grumbach 1379a6bd005fSEmmanuel Grumbach /* 1380a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1381a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1382a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1383a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1384a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1385a6bd005fSEmmanuel Grumbach */ 1386a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1387a6bd005fSEmmanuel Grumbach 1388a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1389a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1390a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1391a6bd005fSEmmanuel Grumbach 1392a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1393286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1394a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1395a6bd005fSEmmanuel Grumbach else 1396a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1397a6bd005fSEmmanuel Grumbach 1398a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13999ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1400a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1401a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1402a6bd005fSEmmanuel Grumbach 1403a6bd005fSEmmanuel Grumbach out: 1404a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1405a6bd005fSEmmanuel Grumbach return ret; 1406a6bd005fSEmmanuel Grumbach } 1407a6bd005fSEmmanuel Grumbach 1408a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1409a6bd005fSEmmanuel Grumbach { 1410a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1411a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1412a6bd005fSEmmanuel Grumbach } 1413a6bd005fSEmmanuel Grumbach 1414326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1415326477e4SJohannes Berg bool was_in_rfkill) 1416326477e4SJohannes Berg { 1417326477e4SJohannes Berg bool hw_rfkill; 1418326477e4SJohannes Berg 1419326477e4SJohannes Berg /* 1420326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1421326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1422326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1423326477e4SJohannes Berg * op_mode. 1424326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1425326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1426326477e4SJohannes Berg * notification without endless recursion. Under very rare 1427326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1428326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1429326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1430326477e4SJohannes Berg */ 1431326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1432326477e4SJohannes Berg if (hw_rfkill) { 1433326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1434326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1435326477e4SJohannes Berg } else { 1436326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1437326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1438326477e4SJohannes Berg } 1439326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1440326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1441326477e4SJohannes Berg } 1442326477e4SJohannes Berg 1443bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1444e705c121SKalle Valo { 1445e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1446326477e4SJohannes Berg bool was_in_rfkill; 1447e705c121SKalle Valo 1448e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1449326477e4SJohannes Berg trans_pcie->opmode_down = true; 1450326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1451bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1452326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1453e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1454e705c121SKalle Valo } 1455e705c121SKalle Valo 1456e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1457e705c121SKalle Valo { 1458e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1459e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1460e705c121SKalle Valo 1461e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1462e705c121SKalle Valo 1463326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1464326477e4SJohannes Berg state ? "disabled" : "enabled"); 146577c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1466286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1467bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 146877c09bc8SSara Sharon else 1469bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1470e705c121SKalle Valo } 147177c09bc8SSara Sharon } 1472e705c121SKalle Valo 1473e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1474e5f3f215SHaim Dreyfuss bool test, bool reset) 1475e705c121SKalle Valo { 1476e705c121SKalle Valo iwl_disable_interrupts(trans); 1477e705c121SKalle Valo 1478e705c121SKalle Valo /* 1479e705c121SKalle Valo * in testing mode, the host stays awake and the 1480e705c121SKalle Valo * hardware won't be reset (not even partially) 1481e705c121SKalle Valo */ 1482e705c121SKalle Valo if (test) 1483e705c121SKalle Valo return; 1484e705c121SKalle Valo 1485e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1486e705c121SKalle Valo 14872e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1488e705c121SKalle Valo 1489e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14906dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14916dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1492e705c121SKalle Valo 149323ae6128SMatti Gottlieb if (reset) { 1494e705c121SKalle Valo /* 1495e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1496e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1497e705c121SKalle Valo * to execute some invalid memory upon resume 1498e705c121SKalle Valo */ 1499e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1500e705c121SKalle Valo } 1501e705c121SKalle Valo 1502e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1503e705c121SKalle Valo } 1504e705c121SKalle Valo 1505e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1506e5f3f215SHaim Dreyfuss bool reset) 1507e5f3f215SHaim Dreyfuss { 1508e5f3f215SHaim Dreyfuss int ret; 1509e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1510e5f3f215SHaim Dreyfuss 1511e5f3f215SHaim Dreyfuss /* 1512e5f3f215SHaim Dreyfuss * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW. 1513e5f3f215SHaim Dreyfuss */ 1514e5f3f215SHaim Dreyfuss if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 1515e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1516e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1517e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1518e5f3f215SHaim Dreyfuss } 1519e5f3f215SHaim Dreyfuss 1520e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1521e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1522e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1523e5f3f215SHaim Dreyfuss 1524e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1525e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1526e5f3f215SHaim Dreyfuss /* 1527e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1528e5f3f215SHaim Dreyfuss */ 1529e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1530e5f3f215SHaim Dreyfuss 1531e5f3f215SHaim Dreyfuss if (!ret) { 1532e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1533e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1534e5f3f215SHaim Dreyfuss } 1535e5f3f215SHaim Dreyfuss } 1536e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1537e5f3f215SHaim Dreyfuss 1538e5f3f215SHaim Dreyfuss return 0; 1539e5f3f215SHaim Dreyfuss } 1540e5f3f215SHaim Dreyfuss 1541e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1542e705c121SKalle Valo enum iwl_d3_status *status, 154323ae6128SMatti Gottlieb bool test, bool reset) 1544e705c121SKalle Valo { 1545d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1546e705c121SKalle Valo u32 val; 1547e705c121SKalle Valo int ret; 1548e705c121SKalle Valo 1549e705c121SKalle Valo if (test) { 1550e705c121SKalle Valo iwl_enable_interrupts(trans); 1551e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1552e5f3f215SHaim Dreyfuss goto out; 1553e705c121SKalle Valo } 1554e705c121SKalle Valo 1555a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15566dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1557e705c121SKalle Valo 15587d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1559c96b5eecSJohannes Berg if (ret) 1560e705c121SKalle Valo return ret; 1561e705c121SKalle Valo 1562f98ad635SEmmanuel Grumbach /* 1563f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1564f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1565f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1566f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1567f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1568f98ad635SEmmanuel Grumbach */ 1569f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1570f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1571f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1572f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1573f98ad635SEmmanuel Grumbach 1574e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1575e705c121SKalle Valo 157623ae6128SMatti Gottlieb if (!reset) { 1577e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15786dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1579e705c121SKalle Valo } else { 1580e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1581e705c121SKalle Valo 1582e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1583e705c121SKalle Valo if (ret) { 1584e705c121SKalle Valo IWL_ERR(trans, 1585e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1586e705c121SKalle Valo return ret; 1587e705c121SKalle Valo } 1588e705c121SKalle Valo } 1589e705c121SKalle Valo 159082ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1591ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 159282ea7966SSara Sharon 1593e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1594e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1595e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1596e705c121SKalle Valo else 1597e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1598e705c121SKalle Valo 1599e5f3f215SHaim Dreyfuss out: 1600e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1601e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1602e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1603e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1604e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1605e5f3f215SHaim Dreyfuss 1606e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1607e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1608e5f3f215SHaim Dreyfuss /* 1609e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1610e5f3f215SHaim Dreyfuss */ 1611e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1612e5f3f215SHaim Dreyfuss 1613e5f3f215SHaim Dreyfuss if (!ret) { 1614e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1615e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1616e5f3f215SHaim Dreyfuss } 1617e5f3f215SHaim Dreyfuss } 1618e705c121SKalle Valo return 0; 1619e705c121SKalle Valo } 1620e705c121SKalle Valo 16210c18714aSLuca Coelho static void 16220c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16230c18714aSLuca Coelho struct iwl_trans *trans, 16240c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16252e5d4a8fSHaim Dreyfuss { 16262e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1627ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16282e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16292e5d4a8fSHaim Dreyfuss 16300c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 163106f4b081SSara Sharon goto enable_msi; 163206f4b081SSara Sharon 1633ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 163406f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16352e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16362e5d4a8fSHaim Dreyfuss 163706f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16382e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 163906f4b081SSara Sharon max_irqs); 164006f4b081SSara Sharon if (num_irqs < 0) { 1641496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164206f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 164306f4b081SSara Sharon num_irqs); 164406f4b081SSara Sharon goto enable_msi; 1645496d83caSHaim Dreyfuss } 164606f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1647496d83caSHaim Dreyfuss 16482e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 164906f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 165006f4b081SSara Sharon num_irqs); 165106f4b081SSara Sharon 1652496d83caSHaim Dreyfuss /* 165306f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 165406f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1655496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1656496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1657496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1658496d83caSHaim Dreyfuss */ 1659ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 166006f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1661496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1662496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1663ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 166406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1665496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1666496d83caSHaim Dreyfuss } else { 166706f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1668496d83caSHaim Dreyfuss } 1669ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16702e5d4a8fSHaim Dreyfuss 167106f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1672496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16732e5d4a8fSHaim Dreyfuss return; 16742e5d4a8fSHaim Dreyfuss 167506f4b081SSara Sharon enable_msi: 167606f4b081SSara Sharon ret = pci_enable_msi(pdev); 167706f4b081SSara Sharon if (ret) { 167806f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16792e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16802e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16812e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16822e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16832e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16842e5d4a8fSHaim Dreyfuss } 16852e5d4a8fSHaim Dreyfuss } 16862e5d4a8fSHaim Dreyfuss } 16872e5d4a8fSHaim Dreyfuss 16887c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16897c8d91ebSHaim Dreyfuss { 16907c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16917c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16927c8d91ebSHaim Dreyfuss 16937c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16947c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16957c8d91ebSHaim Dreyfuss offset = 1 + i; 16967c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16977c8d91ebSHaim Dreyfuss /* 16987c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16997c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17007c8d91ebSHaim Dreyfuss */ 17017c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17027c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17037c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17047c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17057c8d91ebSHaim Dreyfuss if (ret) 17067c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17077c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 17087c8d91ebSHaim Dreyfuss i); 17097c8d91ebSHaim Dreyfuss } 17107c8d91ebSHaim Dreyfuss } 17117c8d91ebSHaim Dreyfuss 17122e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17132e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17142e5d4a8fSHaim Dreyfuss { 1715496d83caSHaim Dreyfuss int i; 17162e5d4a8fSHaim Dreyfuss 1717496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17182e5d4a8fSHaim Dreyfuss int ret; 17195a41a86cSSharon Dvir struct msix_entry *msix_entry; 172064fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 172164fa3affSSharon Dvir 172264fa3affSSharon Dvir if (!qname) 172364fa3affSSharon Dvir return -ENOMEM; 17242e5d4a8fSHaim Dreyfuss 17255a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17265a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17275a41a86cSSharon Dvir msix_entry->vector, 17282e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1729496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17302e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17312e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17322e5d4a8fSHaim Dreyfuss IRQF_SHARED, 173364fa3affSSharon Dvir qname, 17345a41a86cSSharon Dvir msix_entry); 17352e5d4a8fSHaim Dreyfuss if (ret) { 17362e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17372e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17385a41a86cSSharon Dvir 17392e5d4a8fSHaim Dreyfuss return ret; 17402e5d4a8fSHaim Dreyfuss } 17412e5d4a8fSHaim Dreyfuss } 17427c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17432e5d4a8fSHaim Dreyfuss 17442e5d4a8fSHaim Dreyfuss return 0; 17452e5d4a8fSHaim Dreyfuss } 17462e5d4a8fSHaim Dreyfuss 174744f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 174844f61b5cSShahar S Matityahu { 174944f61b5cSShahar S Matityahu u32 hpm, wprot; 175044f61b5cSShahar S Matityahu 1751286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 175244f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 175344f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 175444f61b5cSShahar S Matityahu break; 175544f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 175644f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 175744f61b5cSShahar S Matityahu break; 175844f61b5cSShahar S Matityahu default: 175944f61b5cSShahar S Matityahu return 0; 176044f61b5cSShahar S Matityahu } 176144f61b5cSShahar S Matityahu 176244f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 176344f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 176444f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 176544f61b5cSShahar S Matityahu 176644f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 176744f61b5cSShahar S Matityahu IWL_ERR(trans, 176844f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 176944f61b5cSShahar S Matityahu return -EPERM; 177044f61b5cSShahar S Matityahu } 177144f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 177244f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 177344f61b5cSShahar S Matityahu } 177444f61b5cSShahar S Matityahu 177544f61b5cSShahar S Matityahu return 0; 177644f61b5cSShahar S Matityahu } 177744f61b5cSShahar S Matityahu 17780df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17790df36b90SLuca Coelho { 17800df36b90SLuca Coelho int ret; 17810df36b90SLuca Coelho 17820df36b90SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 17830df36b90SLuca Coelho if (ret < 0) 17840df36b90SLuca Coelho return ret; 17850df36b90SLuca Coelho 17860df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17870df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17880df36b90SLuca Coelho udelay(20); 17890df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17900df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 17910df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 17920df36b90SLuca Coelho udelay(20); 17930df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 17940df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17950df36b90SLuca Coelho 17960df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 17970df36b90SLuca Coelho 17980df36b90SLuca Coelho return 0; 17990df36b90SLuca Coelho } 18000df36b90SLuca Coelho 1801bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1802e705c121SKalle Valo { 1803e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1804e705c121SKalle Valo int err; 1805e705c121SKalle Valo 1806e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1807e705c121SKalle Valo 1808e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1809e705c121SKalle Valo if (err) { 1810e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1811e705c121SKalle Valo return err; 1812e705c121SKalle Valo } 1813e705c121SKalle Valo 181444f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 181544f61b5cSShahar S Matityahu if (err) 181644f61b5cSShahar S Matityahu return err; 18178954e1ebSShahar S Matityahu 1818870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1819e705c121SKalle Valo 18200df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18217897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18220df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18230df36b90SLuca Coelho if (err) 18240df36b90SLuca Coelho return err; 18250df36b90SLuca Coelho } 18260df36b90SLuca Coelho 182752b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 182852b6e168SEmmanuel Grumbach if (err) 182952b6e168SEmmanuel Grumbach return err; 1830e705c121SKalle Valo 18312e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 183283730058SHaim Dreyfuss 1833e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1834e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1835e705c121SKalle Valo 1836326477e4SJohannes Berg trans_pcie->opmode_down = false; 1837326477e4SJohannes Berg 1838e705c121SKalle Valo /* Set is_down to false here so that...*/ 1839e705c121SKalle Valo trans_pcie->is_down = false; 1840e705c121SKalle Valo 1841e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18429ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1843e705c121SKalle Valo 1844e705c121SKalle Valo return 0; 1845e705c121SKalle Valo } 1846e705c121SKalle Valo 1847bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1848e705c121SKalle Valo { 1849e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1850e705c121SKalle Valo int ret; 1851e705c121SKalle Valo 1852e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1853bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1854e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1855e705c121SKalle Valo 1856e705c121SKalle Valo return ret; 1857e705c121SKalle Valo } 1858e705c121SKalle Valo 1859e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1860e705c121SKalle Valo { 1861e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1862e705c121SKalle Valo 1863e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1864e705c121SKalle Valo 1865e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1866e705c121SKalle Valo iwl_disable_interrupts(trans); 1867e705c121SKalle Valo 1868e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1869e705c121SKalle Valo 1870e705c121SKalle Valo iwl_disable_interrupts(trans); 1871e705c121SKalle Valo 1872e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1873e705c121SKalle Valo 1874e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1875e705c121SKalle Valo 18762e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1877e705c121SKalle Valo } 1878e705c121SKalle Valo 1879e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1880e705c121SKalle Valo { 1881e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1882e705c121SKalle Valo } 1883e705c121SKalle Valo 1884e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1885e705c121SKalle Valo { 1886e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1887e705c121SKalle Valo } 1888e705c121SKalle Valo 1889e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1890e705c121SKalle Valo { 1891e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1892e705c121SKalle Valo } 1893e705c121SKalle Valo 189484fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 189584fb372cSSara Sharon { 18963681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 189784fb372cSSara Sharon return 0x00FFFFFF; 189884fb372cSSara Sharon else 189984fb372cSSara Sharon return 0x000FFFFF; 190084fb372cSSara Sharon } 190184fb372cSSara Sharon 1902e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1903e705c121SKalle Valo { 190484fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 190584fb372cSSara Sharon 1906e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 190784fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1908e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1909e705c121SKalle Valo } 1910e705c121SKalle Valo 1911e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1912e705c121SKalle Valo u32 val) 1913e705c121SKalle Valo { 191484fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 191584fb372cSSara Sharon 1916e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 191784fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1918e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1919e705c121SKalle Valo } 1920e705c121SKalle Valo 1921e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1922e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1923e705c121SKalle Valo { 1924e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1925e705c121SKalle Valo 1926e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1927e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1928e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1929e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1930e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1931e705c121SKalle Valo else 1932e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1933e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1934e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1935e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1936e705c121SKalle Valo 19376c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19386c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19396c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 194080084e35SJohannes Berg trans_pcie->rx_buf_bytes = 194180084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1942cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1943cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1944cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1945e705c121SKalle Valo 1946e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1947e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 194841837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1949e705c121SKalle Valo 195021cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 195121cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 195221cb3222SJohannes Berg 195339bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 195439bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 195539bdb17eSSharon Dvir 1956e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1957e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1958e705c121SKalle Valo * As this function may be called again in some corner cases don't 1959e705c121SKalle Valo * do anything if NAPI was already initialized. 1960e705c121SKalle Valo */ 1961bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1962e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1963e705c121SKalle Valo } 1964e705c121SKalle Valo 1965e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1966e705c121SKalle Valo { 1967e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19686eb5e529SEmmanuel Grumbach int i; 1969e705c121SKalle Valo 19702e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1971e705c121SKalle Valo 1972286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 197313a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 197413a3a390SSara Sharon else 1975e705c121SKalle Valo iwl_pcie_tx_free(trans); 1976e705c121SKalle Valo iwl_pcie_rx_free(trans); 1977e705c121SKalle Valo 197810a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 197910a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 198010a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 198110a54d81SLuca Coelho } 198210a54d81SLuca Coelho 19832e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19847c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19857c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19867c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19877c8d91ebSHaim Dreyfuss NULL); 19887c8d91ebSHaim Dreyfuss } 19892e5d4a8fSHaim Dreyfuss 19902e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19912e5d4a8fSHaim Dreyfuss } else { 1992e705c121SKalle Valo iwl_pcie_free_ict(trans); 19932e5d4a8fSHaim Dreyfuss } 1994e705c121SKalle Valo 1995e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1996e705c121SKalle Valo 19976eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19986eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19996eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 20006eb5e529SEmmanuel Grumbach 20016eb5e529SEmmanuel Grumbach if (p->page) 20026eb5e529SEmmanuel Grumbach __free_page(p->page); 20036eb5e529SEmmanuel Grumbach } 20046eb5e529SEmmanuel Grumbach 20056eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 2006a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2007e705c121SKalle Valo iwl_trans_free(trans); 2008e705c121SKalle Valo } 2009e705c121SKalle Valo 2010e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2011e705c121SKalle Valo { 2012e705c121SKalle Valo if (state) 2013e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2014e705c121SKalle Valo else 2015e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2016e705c121SKalle Valo } 2017e705c121SKalle Valo 201849564a80SLuca Coelho struct iwl_trans_pcie_removal { 201949564a80SLuca Coelho struct pci_dev *pdev; 202049564a80SLuca Coelho struct work_struct work; 202149564a80SLuca Coelho }; 202249564a80SLuca Coelho 202349564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 202449564a80SLuca Coelho { 202549564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 202649564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 202749564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2028aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 202949564a80SLuca Coelho 203049564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 203149564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 203249564a80SLuca Coelho pci_lock_rescan_remove(); 203349564a80SLuca Coelho pci_dev_put(pdev); 203449564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 203549564a80SLuca Coelho pci_unlock_rescan_remove(); 203649564a80SLuca Coelho 203749564a80SLuca Coelho kfree(removal); 203849564a80SLuca Coelho module_put(THIS_MODULE); 203949564a80SLuca Coelho } 204049564a80SLuca Coelho 204123ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 2042e705c121SKalle Valo unsigned long *flags) 2043e705c121SKalle Valo { 2044e705c121SKalle Valo int ret; 2045e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2046e705c121SKalle Valo 2047e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 2048e705c121SKalle Valo 2049e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2050e705c121SKalle Valo goto out; 2051e705c121SKalle Valo 2052e705c121SKalle Valo /* this bit wakes up the NIC */ 2053e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 20546dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2055286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2056e705c121SKalle Valo udelay(2); 2057e705c121SKalle Valo 2058e705c121SKalle Valo /* 2059e705c121SKalle Valo * These bits say the device is running, and should keep running for 2060e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2061e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2062fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2063fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2064e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2065e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2066e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2067e705c121SKalle Valo * to keep device from sleeping. 2068e705c121SKalle Valo * 2069e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2070e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2071fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2072fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2073fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2074e705c121SKalle Valo * 2075e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2076e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2077e705c121SKalle Valo */ 2078e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 20796dece0e9SLuca Coelho CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 20806dece0e9SLuca Coelho (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2081e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2082e705c121SKalle Valo if (unlikely(ret < 0)) { 208349564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 208449564a80SLuca Coelho 2085e705c121SKalle Valo WARN_ONCE(1, 2086e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 208749564a80SLuca Coelho cntrl); 208849564a80SLuca Coelho 208949564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 209049564a80SLuca Coelho 209149564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 209249564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 209349564a80SLuca Coelho 2094f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 209549564a80SLuca Coelho goto err; 209649564a80SLuca Coelho 209749564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 209849564a80SLuca Coelho 209949564a80SLuca Coelho /* 210049564a80SLuca Coelho * get a module reference to avoid doing this 210149564a80SLuca Coelho * while unloading anyway and to avoid 210249564a80SLuca Coelho * scheduling a work with code that's being 210349564a80SLuca Coelho * removed. 210449564a80SLuca Coelho */ 210549564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 210649564a80SLuca Coelho IWL_ERR(trans, 210749564a80SLuca Coelho "Module is being unloaded - abort\n"); 210849564a80SLuca Coelho goto err; 210949564a80SLuca Coelho } 211049564a80SLuca Coelho 211149564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 211249564a80SLuca Coelho if (!removal) { 211349564a80SLuca Coelho module_put(THIS_MODULE); 211449564a80SLuca Coelho goto err; 211549564a80SLuca Coelho } 211649564a80SLuca Coelho /* 211749564a80SLuca Coelho * we don't need to clear this flag, because 211849564a80SLuca Coelho * the trans will be freed and reallocated. 211949564a80SLuca Coelho */ 2120f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 212149564a80SLuca Coelho 212249564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 212349564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 212449564a80SLuca Coelho pci_dev_get(removal->pdev); 212549564a80SLuca Coelho schedule_work(&removal->work); 212649564a80SLuca Coelho } else { 212749564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 212849564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 212949564a80SLuca Coelho } 213049564a80SLuca Coelho 213149564a80SLuca Coelho err: 2132e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2133e705c121SKalle Valo return false; 2134e705c121SKalle Valo } 2135e705c121SKalle Valo 2136e705c121SKalle Valo out: 2137e705c121SKalle Valo /* 2138e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2139e705c121SKalle Valo * track nic_access anyway. 2140e705c121SKalle Valo */ 2141e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2142e705c121SKalle Valo return true; 2143e705c121SKalle Valo } 2144e705c121SKalle Valo 2145e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2146e705c121SKalle Valo unsigned long *flags) 2147e705c121SKalle Valo { 2148e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2149e705c121SKalle Valo 2150e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2151e705c121SKalle Valo 2152e705c121SKalle Valo /* 2153e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2154e705c121SKalle Valo * track nic_access anyway. 2155e705c121SKalle Valo */ 2156e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2157e705c121SKalle Valo 2158e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2159e705c121SKalle Valo goto out; 2160e705c121SKalle Valo 2161e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21626dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2163e705c121SKalle Valo /* 2164e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2165e705c121SKalle Valo * any previous writes, but we need the write that clears the 2166e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2167e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2168e705c121SKalle Valo */ 2169e705c121SKalle Valo out: 2170e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2171e705c121SKalle Valo } 2172e705c121SKalle Valo 2173e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2174e705c121SKalle Valo void *buf, int dwords) 2175e705c121SKalle Valo { 2176e705c121SKalle Valo unsigned long flags; 2177e705c121SKalle Valo int offs, ret = 0; 2178e705c121SKalle Valo u32 *vals = buf; 2179e705c121SKalle Valo 218023ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2181e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2182e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2183e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2184e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2185e705c121SKalle Valo } else { 2186e705c121SKalle Valo ret = -EBUSY; 2187e705c121SKalle Valo } 2188e705c121SKalle Valo return ret; 2189e705c121SKalle Valo } 2190e705c121SKalle Valo 2191e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2192e705c121SKalle Valo const void *buf, int dwords) 2193e705c121SKalle Valo { 2194e705c121SKalle Valo unsigned long flags; 2195e705c121SKalle Valo int offs, ret = 0; 2196e705c121SKalle Valo const u32 *vals = buf; 2197e705c121SKalle Valo 219823ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2199e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2200e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2201e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2202e705c121SKalle Valo vals ? vals[offs] : 0); 2203e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2204e705c121SKalle Valo } else { 2205e705c121SKalle Valo ret = -EBUSY; 2206e705c121SKalle Valo } 2207e705c121SKalle Valo return ret; 2208e705c121SKalle Valo } 2209e705c121SKalle Valo 22107f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22117f1fe1d4SLuca Coelho u32 *val) 22127f1fe1d4SLuca Coelho { 22137f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 22147f1fe1d4SLuca Coelho ofs, val); 22157f1fe1d4SLuca Coelho } 22167f1fe1d4SLuca Coelho 2217e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2218e705c121SKalle Valo unsigned long txqs, 2219e705c121SKalle Valo bool freeze) 2220e705c121SKalle Valo { 2221e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2222e705c121SKalle Valo int queue; 2223e705c121SKalle Valo 2224e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2225b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2226e705c121SKalle Valo unsigned long now; 2227e705c121SKalle Valo 2228e705c121SKalle Valo spin_lock_bh(&txq->lock); 2229e705c121SKalle Valo 2230e705c121SKalle Valo now = jiffies; 2231e705c121SKalle Valo 2232e705c121SKalle Valo if (txq->frozen == freeze) 2233e705c121SKalle Valo goto next_queue; 2234e705c121SKalle Valo 2235e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2236e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2237e705c121SKalle Valo 2238e705c121SKalle Valo txq->frozen = freeze; 2239e705c121SKalle Valo 2240bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2241e705c121SKalle Valo goto next_queue; 2242e705c121SKalle Valo 2243e705c121SKalle Valo if (freeze) { 2244e705c121SKalle Valo if (unlikely(time_after(now, 2245e705c121SKalle Valo txq->stuck_timer.expires))) { 2246e705c121SKalle Valo /* 2247e705c121SKalle Valo * The timer should have fired, maybe it is 2248e705c121SKalle Valo * spinning right now on the lock. 2249e705c121SKalle Valo */ 2250e705c121SKalle Valo goto next_queue; 2251e705c121SKalle Valo } 2252e705c121SKalle Valo /* remember how long until the timer fires */ 2253e705c121SKalle Valo txq->frozen_expiry_remainder = 2254e705c121SKalle Valo txq->stuck_timer.expires - now; 2255e705c121SKalle Valo del_timer(&txq->stuck_timer); 2256e705c121SKalle Valo goto next_queue; 2257e705c121SKalle Valo } 2258e705c121SKalle Valo 2259e705c121SKalle Valo /* 2260e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2261e705c121SKalle Valo * remainder before it froze 2262e705c121SKalle Valo */ 2263e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2264e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2265e705c121SKalle Valo 2266e705c121SKalle Valo next_queue: 2267e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2268e705c121SKalle Valo } 2269e705c121SKalle Valo } 2270e705c121SKalle Valo 22710cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22720cd58eaaSEmmanuel Grumbach { 22730cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22740cd58eaaSEmmanuel Grumbach int i; 22750cd58eaaSEmmanuel Grumbach 2276286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2277b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 22780cd58eaaSEmmanuel Grumbach 22790cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 22800cd58eaaSEmmanuel Grumbach continue; 22810cd58eaaSEmmanuel Grumbach 22820cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22830cd58eaaSEmmanuel Grumbach 22840cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22850cd58eaaSEmmanuel Grumbach txq->block--; 22860cd58eaaSEmmanuel Grumbach if (!txq->block) { 22870cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2288bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22890cd58eaaSEmmanuel Grumbach } 22900cd58eaaSEmmanuel Grumbach } else if (block) { 22910cd58eaaSEmmanuel Grumbach txq->block++; 22920cd58eaaSEmmanuel Grumbach } 22930cd58eaaSEmmanuel Grumbach 22940cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22950cd58eaaSEmmanuel Grumbach } 22960cd58eaaSEmmanuel Grumbach } 22970cd58eaaSEmmanuel Grumbach 2298e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2299e705c121SKalle Valo 230038398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 230138398efbSSara Sharon { 2302afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2303afb84431SEmmanuel Grumbach u32 status; 2304afb84431SEmmanuel Grumbach bool active; 2305afb84431SEmmanuel Grumbach u8 fifo; 230638398efbSSara Sharon 2307286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 2308afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2309bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2310ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2311ae79785fSSara Sharon return; 2312afb84431SEmmanuel Grumbach } 2313ae79785fSSara Sharon 2314afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2315afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2316afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 231738398efbSSara Sharon 231838398efbSSara Sharon IWL_ERR(trans, 2319afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2320afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2321afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2322afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2323afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2324286ca8ebSLuca Coelho (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2325afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2326286ca8ebSLuca Coelho (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2327afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 232838398efbSSara Sharon } 232938398efbSSara Sharon 233092536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 233192536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 233292536c96SSara Sharon { 233392536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 233492536c96SSara Sharon 233592536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 233692536c96SSara Sharon return -EINVAL; 233792536c96SSara Sharon 233892536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 233992536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 234092536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 234192536c96SSara Sharon data->fr_bd_wid = 0; 234292536c96SSara Sharon 234392536c96SSara Sharon return 0; 234492536c96SSara Sharon } 234592536c96SSara Sharon 2346d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2347e705c121SKalle Valo { 2348e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2349e705c121SKalle Valo struct iwl_txq *txq; 2350e705c121SKalle Valo unsigned long now = jiffies; 23512ae48edcSSara Sharon bool overflow_tx; 2352e705c121SKalle Valo u8 wr_ptr; 2353e705c121SKalle Valo 23542b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2355f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2356f60c9e59SEmmanuel Grumbach return -ENODEV; 23572b3fae66SMatt Chen 2358d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2359d6d517b7SSara Sharon return -EINVAL; 2360e705c121SKalle Valo 2361d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2362d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 23632ae48edcSSara Sharon 23642ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23652ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23662ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23672ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23682ae48edcSSara Sharon 23696aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2370e705c121SKalle Valo 23712ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23722ae48edcSSara Sharon overflow_tx) && 2373e705c121SKalle Valo !time_after(jiffies, 2374e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23756aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2376e705c121SKalle Valo 23772ae48edcSSara Sharon /* 23782ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23792ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23802ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23812ae48edcSSara Sharon */ 23822ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2383e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2384e705c121SKalle Valo wr_ptr, write_ptr)) 2385e705c121SKalle Valo return -ETIMEDOUT; 23862ae48edcSSara Sharon wr_ptr = write_ptr; 23872ae48edcSSara Sharon 2388192185d6SJohannes Berg usleep_range(1000, 2000); 23892ae48edcSSara Sharon 23902ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23912ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23922ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23932ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2394e705c121SKalle Valo } 2395e705c121SKalle Valo 2396bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2397e705c121SKalle Valo IWL_ERR(trans, 2398d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2399d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2400d6d517b7SSara Sharon return -ETIMEDOUT; 2401e705c121SKalle Valo } 2402e705c121SKalle Valo 2403d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2404d6d517b7SSara Sharon 2405d6d517b7SSara Sharon return 0; 2406d6d517b7SSara Sharon } 2407d6d517b7SSara Sharon 2408d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2409d6d517b7SSara Sharon { 2410d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2411d6d517b7SSara Sharon int cnt; 2412d6d517b7SSara Sharon int ret = 0; 2413d6d517b7SSara Sharon 2414d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 241579b6c8feSLuca Coelho for (cnt = 0; 2416286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 241779b6c8feSLuca Coelho cnt++) { 2418d6d517b7SSara Sharon 2419d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2420d6d517b7SSara Sharon continue; 2421d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2422d6d517b7SSara Sharon continue; 2423d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2424d6d517b7SSara Sharon continue; 2425d6d517b7SSara Sharon 2426d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 242738398efbSSara Sharon if (ret) 2428d6d517b7SSara Sharon break; 2429d6d517b7SSara Sharon } 2430e705c121SKalle Valo 2431e705c121SKalle Valo return ret; 2432e705c121SKalle Valo } 2433e705c121SKalle Valo 2434e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2435e705c121SKalle Valo u32 mask, u32 value) 2436e705c121SKalle Valo { 2437e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2438e705c121SKalle Valo unsigned long flags; 2439e705c121SKalle Valo 2440e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2441e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2442e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2443e705c121SKalle Valo } 2444e705c121SKalle Valo 2445e705c121SKalle Valo static const char *get_csr_string(int cmd) 2446e705c121SKalle Valo { 2447e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2448e705c121SKalle Valo switch (cmd) { 2449e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2450e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2451e705c121SKalle Valo IWL_CMD(CSR_INT); 2452e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2453e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2454e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2455e705c121SKalle Valo IWL_CMD(CSR_RESET); 2456e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2457e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2458e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2459e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2460e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2461e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2462e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2463e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2464e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2465e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2466e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2467e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2468e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2469e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2470e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2471e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2472e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2473e705c121SKalle Valo default: 2474e705c121SKalle Valo return "UNKNOWN"; 2475e705c121SKalle Valo } 2476e705c121SKalle Valo #undef IWL_CMD 2477e705c121SKalle Valo } 2478e705c121SKalle Valo 2479e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2480e705c121SKalle Valo { 2481e705c121SKalle Valo int i; 2482e705c121SKalle Valo static const u32 csr_tbl[] = { 2483e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2484e705c121SKalle Valo CSR_INT_COALESCING, 2485e705c121SKalle Valo CSR_INT, 2486e705c121SKalle Valo CSR_INT_MASK, 2487e705c121SKalle Valo CSR_FH_INT_STATUS, 2488e705c121SKalle Valo CSR_GPIO_IN, 2489e705c121SKalle Valo CSR_RESET, 2490e705c121SKalle Valo CSR_GP_CNTRL, 2491e705c121SKalle Valo CSR_HW_REV, 2492e705c121SKalle Valo CSR_EEPROM_REG, 2493e705c121SKalle Valo CSR_EEPROM_GP, 2494e705c121SKalle Valo CSR_OTP_GP_REG, 2495e705c121SKalle Valo CSR_GIO_REG, 2496e705c121SKalle Valo CSR_GP_UCODE_REG, 2497e705c121SKalle Valo CSR_GP_DRIVER_REG, 2498e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2499e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2500e705c121SKalle Valo CSR_LED_REG, 2501e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2502e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2503e705c121SKalle Valo CSR_ANA_PLL_CFG, 2504e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2505e705c121SKalle Valo CSR_HW_REV_WA_REG, 2506e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2507e705c121SKalle Valo }; 2508e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2509e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2510e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2511e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2512e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2513e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2514e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2515e705c121SKalle Valo } 2516e705c121SKalle Valo } 2517e705c121SKalle Valo 2518e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2519e705c121SKalle Valo /* create and remove of files */ 2520e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2521cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2522cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2523e705c121SKalle Valo } while (0) 2524e705c121SKalle Valo 2525e705c121SKalle Valo /* file operation */ 2526e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2527e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2528e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2529e705c121SKalle Valo .open = simple_open, \ 2530e705c121SKalle Valo .llseek = generic_file_llseek, \ 2531e705c121SKalle Valo }; 2532e705c121SKalle Valo 2533e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2534e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2535e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2536e705c121SKalle Valo .open = simple_open, \ 2537e705c121SKalle Valo .llseek = generic_file_llseek, \ 2538e705c121SKalle Valo }; 2539e705c121SKalle Valo 2540e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2541e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2542e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2543e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2544e705c121SKalle Valo .open = simple_open, \ 2545e705c121SKalle Valo .llseek = generic_file_llseek, \ 2546e705c121SKalle Valo }; 2547e705c121SKalle Valo 2548df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2549df67a1beSJohannes Berg struct iwl_trans *trans; 2550df67a1beSJohannes Berg }; 2551df67a1beSJohannes Berg 2552df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2553df67a1beSJohannes Berg loff_t pos; 2554df67a1beSJohannes Berg }; 2555df67a1beSJohannes Berg 2556df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2557e705c121SKalle Valo { 2558df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2559df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2560df67a1beSJohannes Berg 2561df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2562df67a1beSJohannes Berg return NULL; 2563df67a1beSJohannes Berg 2564df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2565df67a1beSJohannes Berg if (!state) 2566df67a1beSJohannes Berg return NULL; 2567df67a1beSJohannes Berg state->pos = *pos; 2568df67a1beSJohannes Berg return state; 2569df67a1beSJohannes Berg } 2570df67a1beSJohannes Berg 2571df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2572df67a1beSJohannes Berg void *v, loff_t *pos) 2573df67a1beSJohannes Berg { 2574df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2575df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2576df67a1beSJohannes Berg 2577df67a1beSJohannes Berg *pos = ++state->pos; 2578df67a1beSJohannes Berg 2579df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2580df67a1beSJohannes Berg return NULL; 2581df67a1beSJohannes Berg 2582df67a1beSJohannes Berg return state; 2583df67a1beSJohannes Berg } 2584df67a1beSJohannes Berg 2585df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2586df67a1beSJohannes Berg { 2587df67a1beSJohannes Berg kfree(v); 2588df67a1beSJohannes Berg } 2589df67a1beSJohannes Berg 2590df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2591df67a1beSJohannes Berg { 2592df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2593df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2594df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 2595e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2596df67a1beSJohannes Berg struct iwl_txq *txq = trans_pcie->txq[state->pos]; 2597e705c121SKalle Valo 2598df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2599df67a1beSJohannes Berg (unsigned int)state->pos, 2600df67a1beSJohannes Berg !!test_bit(state->pos, trans_pcie->queue_used), 2601df67a1beSJohannes Berg !!test_bit(state->pos, trans_pcie->queue_stopped)); 2602df67a1beSJohannes Berg if (txq) 2603df67a1beSJohannes Berg seq_printf(seq, 260495a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2605df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 260695a9e44fSJohannes Berg txq->need_update, txq->frozen, 260795a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2608df67a1beSJohannes Berg else 2609df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2610e705c121SKalle Valo 2611df67a1beSJohannes Berg if (state->pos == trans_pcie->cmd_queue) 2612df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2613df67a1beSJohannes Berg seq_puts(seq, "\n"); 2614e705c121SKalle Valo 2615df67a1beSJohannes Berg return 0; 2616df67a1beSJohannes Berg } 2617df67a1beSJohannes Berg 2618df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2619df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2620df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2621df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2622df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2623df67a1beSJohannes Berg }; 2624df67a1beSJohannes Berg 2625df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2626df67a1beSJohannes Berg { 2627df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2628df67a1beSJohannes Berg 2629df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2630df67a1beSJohannes Berg sizeof(*priv)); 2631df67a1beSJohannes Berg 2632df67a1beSJohannes Berg if (!priv) 2633e705c121SKalle Valo return -ENOMEM; 2634e705c121SKalle Valo 2635df67a1beSJohannes Berg priv->trans = inode->i_private; 2636df67a1beSJohannes Berg return 0; 2637e705c121SKalle Valo } 2638e705c121SKalle Valo 2639e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2640e705c121SKalle Valo char __user *user_buf, 2641e705c121SKalle Valo size_t count, loff_t *ppos) 2642e705c121SKalle Valo { 2643e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2644e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 264578485054SSara Sharon char *buf; 264678485054SSara Sharon int pos = 0, i, ret; 2647eb3dc36eSColin Ian King size_t bufsz; 2648e705c121SKalle Valo 264978485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 265078485054SSara Sharon 265178485054SSara Sharon if (!trans_pcie->rxq) 265278485054SSara Sharon return -EAGAIN; 265378485054SSara Sharon 265478485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 265578485054SSara Sharon if (!buf) 265678485054SSara Sharon return -ENOMEM; 265778485054SSara Sharon 265878485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 265978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 266078485054SSara Sharon 266178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 266278485054SSara Sharon i); 266378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2664e705c121SKalle Valo rxq->read); 266578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2666e705c121SKalle Valo rxq->write); 266778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2668e705c121SKalle Valo rxq->write_actual); 266978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2670e705c121SKalle Valo rxq->need_update); 267178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2672e705c121SKalle Valo rxq->free_count); 2673e705c121SKalle Valo if (rxq->rb_stts) { 26740307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26750307c839SGolan Ben Ami rxq)); 267678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 267778485054SSara Sharon "\tclosed_rb_num: %u\n", 26780307c839SGolan Ben Ami r & 0x0FFF); 2679e705c121SKalle Valo } else { 2680e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 268178485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2682e705c121SKalle Valo } 268378485054SSara Sharon } 268478485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 268578485054SSara Sharon kfree(buf); 268678485054SSara Sharon 268778485054SSara Sharon return ret; 2688e705c121SKalle Valo } 2689e705c121SKalle Valo 2690e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2691e705c121SKalle Valo char __user *user_buf, 2692e705c121SKalle Valo size_t count, loff_t *ppos) 2693e705c121SKalle Valo { 2694e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2695e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2696e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2697e705c121SKalle Valo 2698e705c121SKalle Valo int pos = 0; 2699e705c121SKalle Valo char *buf; 2700e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2701e705c121SKalle Valo ssize_t ret; 2702e705c121SKalle Valo 2703e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2704e705c121SKalle Valo if (!buf) 2705e705c121SKalle Valo return -ENOMEM; 2706e705c121SKalle Valo 2707e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2708e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2709e705c121SKalle Valo 2710e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2711e705c121SKalle Valo isr_stats->hw); 2712e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2713e705c121SKalle Valo isr_stats->sw); 2714e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2715e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2716e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2717e705c121SKalle Valo isr_stats->err_code); 2718e705c121SKalle Valo } 2719e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2720e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2721e705c121SKalle Valo isr_stats->sch); 2722e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2723e705c121SKalle Valo isr_stats->alive); 2724e705c121SKalle Valo #endif 2725e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2726e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2727e705c121SKalle Valo 2728e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2729e705c121SKalle Valo isr_stats->ctkill); 2730e705c121SKalle Valo 2731e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2732e705c121SKalle Valo isr_stats->wakeup); 2733e705c121SKalle Valo 2734e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2735e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2736e705c121SKalle Valo 2737e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2738e705c121SKalle Valo isr_stats->tx); 2739e705c121SKalle Valo 2740e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2741e705c121SKalle Valo isr_stats->unhandled); 2742e705c121SKalle Valo 2743e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2744e705c121SKalle Valo kfree(buf); 2745e705c121SKalle Valo return ret; 2746e705c121SKalle Valo } 2747e705c121SKalle Valo 2748e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2749e705c121SKalle Valo const char __user *user_buf, 2750e705c121SKalle Valo size_t count, loff_t *ppos) 2751e705c121SKalle Valo { 2752e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2753e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2754e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2755e705c121SKalle Valo u32 reset_flag; 2756078f1131SJohannes Berg int ret; 2757e705c121SKalle Valo 2758078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2759078f1131SJohannes Berg if (ret) 2760078f1131SJohannes Berg return ret; 2761e705c121SKalle Valo if (reset_flag == 0) 2762e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2763e705c121SKalle Valo 2764e705c121SKalle Valo return count; 2765e705c121SKalle Valo } 2766e705c121SKalle Valo 2767e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2768e705c121SKalle Valo const char __user *user_buf, 2769e705c121SKalle Valo size_t count, loff_t *ppos) 2770e705c121SKalle Valo { 2771e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2772e705c121SKalle Valo 2773e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2774e705c121SKalle Valo 2775e705c121SKalle Valo return count; 2776e705c121SKalle Valo } 2777e705c121SKalle Valo 2778e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2779e705c121SKalle Valo char __user *user_buf, 2780e705c121SKalle Valo size_t count, loff_t *ppos) 2781e705c121SKalle Valo { 2782e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2783e705c121SKalle Valo char *buf = NULL; 2784e705c121SKalle Valo ssize_t ret; 2785e705c121SKalle Valo 2786e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2787e705c121SKalle Valo if (ret < 0) 2788e705c121SKalle Valo return ret; 2789e705c121SKalle Valo if (!buf) 2790e705c121SKalle Valo return -EINVAL; 2791e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2792e705c121SKalle Valo kfree(buf); 2793e705c121SKalle Valo return ret; 2794e705c121SKalle Valo } 2795e705c121SKalle Valo 2796fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2797fa4de7f7SJohannes Berg char __user *user_buf, 2798fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2799fa4de7f7SJohannes Berg { 2800fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2801fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2802fa4de7f7SJohannes Berg char buf[100]; 2803fa4de7f7SJohannes Berg int pos; 2804fa4de7f7SJohannes Berg 2805fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2806fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2807fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2808fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2809fa4de7f7SJohannes Berg 2810fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2811fa4de7f7SJohannes Berg } 2812fa4de7f7SJohannes Berg 2813fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2814fa4de7f7SJohannes Berg const char __user *user_buf, 2815fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2816fa4de7f7SJohannes Berg { 2817fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2818fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2819c5bf4fa1SJohannes Berg bool new_value; 2820fa4de7f7SJohannes Berg int ret; 2821fa4de7f7SJohannes Berg 2822c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2823fa4de7f7SJohannes Berg if (ret) 2824fa4de7f7SJohannes Berg return ret; 2825c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2826fa4de7f7SJohannes Berg return count; 2827fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2828c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2829c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2830fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2831fa4de7f7SJohannes Berg 2832fa4de7f7SJohannes Berg return count; 2833fa4de7f7SJohannes Berg } 2834fa4de7f7SJohannes Berg 2835f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2836f7805b33SLior Cohen struct file *file) 2837f7805b33SLior Cohen { 2838f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2839f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2840f7805b33SLior Cohen 284191c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 284291c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2843f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2844f7805b33SLior Cohen return -ENOENT; 2845f7805b33SLior Cohen } 2846f7805b33SLior Cohen 2847f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2848f7805b33SLior Cohen return -EBUSY; 2849f7805b33SLior Cohen 2850f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2851f7805b33SLior Cohen return simple_open(inode, file); 2852f7805b33SLior Cohen } 2853f7805b33SLior Cohen 2854f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2855f7805b33SLior Cohen struct file *file) 2856f7805b33SLior Cohen { 2857f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2858f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2859f7805b33SLior Cohen 2860f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2861f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2862f7805b33SLior Cohen return 0; 2863f7805b33SLior Cohen } 2864f7805b33SLior Cohen 2865f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2866f7805b33SLior Cohen void *buf, ssize_t *size, 2867f7805b33SLior Cohen ssize_t *bytes_copied) 2868f7805b33SLior Cohen { 2869f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2870f7805b33SLior Cohen 2871f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2872f7805b33SLior Cohen if (*size > buf_size_left) 2873f7805b33SLior Cohen *size = buf_size_left; 2874f7805b33SLior Cohen 2875f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2876f7805b33SLior Cohen *bytes_copied += *size; 2877f7805b33SLior Cohen 2878f7805b33SLior Cohen if (buf_size_left == *size) 2879f7805b33SLior Cohen return true; 2880f7805b33SLior Cohen return false; 2881f7805b33SLior Cohen } 2882f7805b33SLior Cohen 2883f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2884f7805b33SLior Cohen char __user *user_buf, 2885f7805b33SLior Cohen size_t count, loff_t *ppos) 2886f7805b33SLior Cohen { 2887f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2888f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 288969f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2890f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2891f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2892f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2893f7805b33SLior Cohen bool b_full; 2894f7805b33SLior Cohen 289591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2896f7805b33SLior Cohen write_ptr_addr = 289791c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 289891c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2899f7805b33SLior Cohen } else { 2900f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2901f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2902f7805b33SLior Cohen } 2903f7805b33SLior Cohen 290491c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2905f7805b33SLior Cohen return 0; 2906f7805b33SLior Cohen 2907f7805b33SLior Cohen mutex_lock(&data->mutex); 2908f7805b33SLior Cohen if (data->state == 2909f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2910f7805b33SLior Cohen mutex_unlock(&data->mutex); 2911f7805b33SLior Cohen return 0; 2912f7805b33SLior Cohen } 2913f7805b33SLior Cohen 2914f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2915f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2916f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2917f7805b33SLior Cohen 2918f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2919f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2920f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2921f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2922f7805b33SLior Cohen curr_buf, &size, 2923f7805b33SLior Cohen &bytes_copied); 2924f7805b33SLior Cohen data->prev_wr_ptr += size; 2925f7805b33SLior Cohen 2926f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2927f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 292869f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2929f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2930f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2931f7805b33SLior Cohen curr_buf, &size, 2932f7805b33SLior Cohen &bytes_copied); 2933f7805b33SLior Cohen data->prev_wr_ptr += size; 2934f7805b33SLior Cohen 2935f7805b33SLior Cohen if (!b_full) { 2936f7805b33SLior Cohen size = write_ptr; 2937f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2938f7805b33SLior Cohen cpu_addr, &size, 2939f7805b33SLior Cohen &bytes_copied); 2940f7805b33SLior Cohen data->prev_wr_ptr = size; 2941f7805b33SLior Cohen data->prev_wrap_cnt++; 2942f7805b33SLior Cohen } 2943f7805b33SLior Cohen } else { 2944f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2945f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2946f7805b33SLior Cohen IWL_WARN(trans, 2947f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2948f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2949f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2950f7805b33SLior Cohen IWL_WARN(trans, 2951f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2952f7805b33SLior Cohen 2953f7805b33SLior Cohen size = write_ptr; 2954f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2955f7805b33SLior Cohen cpu_addr, &size, 2956f7805b33SLior Cohen &bytes_copied); 2957f7805b33SLior Cohen data->prev_wr_ptr = size; 2958f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2959f7805b33SLior Cohen } 2960f7805b33SLior Cohen 2961f7805b33SLior Cohen mutex_unlock(&data->mutex); 2962f7805b33SLior Cohen 2963f7805b33SLior Cohen return bytes_copied; 2964f7805b33SLior Cohen } 2965f7805b33SLior Cohen 2966e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2967e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2968e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2969e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2970fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2971df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2972df67a1beSJohannes Berg .owner = THIS_MODULE, 2973df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2974df67a1beSJohannes Berg .read = seq_read, 2975df67a1beSJohannes Berg .llseek = seq_lseek, 2976df67a1beSJohannes Berg .release = seq_release_private, 2977df67a1beSJohannes Berg }; 2978e705c121SKalle Valo 2979f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2980f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2981f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2982f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2983f7805b33SLior Cohen }; 2984f7805b33SLior Cohen 2985f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2986cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2987e705c121SKalle Valo { 2988f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2989f8a1edb7SJohannes Berg 29902ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 29912ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 29922ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 29932ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 29942ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 29952ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2996f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2997e705c121SKalle Valo } 2998f7805b33SLior Cohen 2999f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3000f7805b33SLior Cohen { 3001f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3002f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 3003f7805b33SLior Cohen 3004f7805b33SLior Cohen mutex_lock(&data->mutex); 3005f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3006f7805b33SLior Cohen mutex_unlock(&data->mutex); 3007f7805b33SLior Cohen } 3008e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3009e705c121SKalle Valo 30106983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3011e705c121SKalle Valo { 30123cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3013e705c121SKalle Valo u32 cmdlen = 0; 3014e705c121SKalle Valo int i; 3015e705c121SKalle Valo 30163cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 30176983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 3018e705c121SKalle Valo 3019e705c121SKalle Valo return cmdlen; 3020e705c121SKalle Valo } 3021e705c121SKalle Valo 3022e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3023e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3024e705c121SKalle Valo int allocated_rb_nums) 3025e705c121SKalle Valo { 3026e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 302780084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 302878485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 302978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3030e705c121SKalle Valo u32 i, r, j, rb_len = 0; 3031e705c121SKalle Valo 3032e705c121SKalle Valo spin_lock(&rxq->lock); 3033e705c121SKalle Valo 30340307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3035e705c121SKalle Valo 3036e705c121SKalle Valo for (i = rxq->read, j = 0; 3037e705c121SKalle Valo i != r && j < allocated_rb_nums; 3038e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3039e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3040e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3041e705c121SKalle Valo 3042e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 3043e705c121SKalle Valo DMA_FROM_DEVICE); 3044e705c121SKalle Valo 3045e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3046e705c121SKalle Valo 3047e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3048e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3049e705c121SKalle Valo rb = (void *)(*data)->data; 3050e705c121SKalle Valo rb->index = cpu_to_le32(i); 3051e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3052e705c121SKalle Valo /* remap the page for the free benefit */ 3053cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, rxb->page, 3054cfdc20efSJohannes Berg rxb->offset, max_len, 3055e705c121SKalle Valo DMA_FROM_DEVICE); 3056e705c121SKalle Valo 3057e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3058e705c121SKalle Valo } 3059e705c121SKalle Valo 3060e705c121SKalle Valo spin_unlock(&rxq->lock); 3061e705c121SKalle Valo 3062e705c121SKalle Valo return rb_len; 3063e705c121SKalle Valo } 3064e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3065e705c121SKalle Valo 3066e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3067e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3068e705c121SKalle Valo { 3069e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3070e705c121SKalle Valo __le32 *val; 3071e705c121SKalle Valo int i; 3072e705c121SKalle Valo 3073e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3074e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3075e705c121SKalle Valo val = (void *)(*data)->data; 3076e705c121SKalle Valo 3077e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3078e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3079e705c121SKalle Valo 3080e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3081e705c121SKalle Valo 3082e705c121SKalle Valo return csr_len; 3083e705c121SKalle Valo } 3084e705c121SKalle Valo 3085e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3086e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3087e705c121SKalle Valo { 3088e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3089e705c121SKalle Valo unsigned long flags; 3090e705c121SKalle Valo __le32 *val; 3091e705c121SKalle Valo int i; 3092e705c121SKalle Valo 309323ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3094e705c121SKalle Valo return 0; 3095e705c121SKalle Valo 3096e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3097e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3098e705c121SKalle Valo val = (void *)(*data)->data; 3099e705c121SKalle Valo 3100286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3101723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3102723b45e2SLiad Kaufman i += sizeof(u32)) 3103e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3104723b45e2SLiad Kaufman else 3105ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3106ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3107723b45e2SLiad Kaufman i += sizeof(u32)) 3108723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3109723b45e2SLiad Kaufman i)); 3110e705c121SKalle Valo 3111e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3112e705c121SKalle Valo 3113e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3114e705c121SKalle Valo 3115e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3116e705c121SKalle Valo } 3117e705c121SKalle Valo 3118e705c121SKalle Valo static u32 3119e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3120e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3121e705c121SKalle Valo u32 monitor_len) 3122e705c121SKalle Valo { 3123e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3124e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3125e705c121SKalle Valo unsigned long flags; 3126e705c121SKalle Valo u32 i; 3127e705c121SKalle Valo 312823ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3129e705c121SKalle Valo return 0; 3130e705c121SKalle Valo 3131ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3132e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3133ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 313414ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3135ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3136e705c121SKalle Valo 3137e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3138e705c121SKalle Valo 3139e705c121SKalle Valo return monitor_len; 3140e705c121SKalle Valo } 3141e705c121SKalle Valo 31427a14c23dSSara Sharon static void 31437a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31447a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31457a14c23dSSara Sharon { 3146c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 31477a14c23dSSara Sharon 3148286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3149c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3150c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3151c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3152c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 315391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 315491c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 315591c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 315691c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 31577a14c23dSSara Sharon } else { 31587a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 31597a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31607a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31617a14c23dSSara Sharon } 3162c88580e1SShahar S Matityahu 3163c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31647a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31657a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31667a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31677a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3168286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3169c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3170c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3171c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3172c88580e1SShahar S Matityahu } 3173c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31747a14c23dSSara Sharon } 31757a14c23dSSara Sharon 3176e705c121SKalle Valo static u32 3177e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3178e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3179e705c121SKalle Valo u32 monitor_len) 3180e705c121SKalle Valo { 318169f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3182e705c121SKalle Valo u32 len = 0; 3183e705c121SKalle Valo 318491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 318569f0e505SShahar S Matityahu (fw_mon->size && 3186286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3187286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3188e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3189e705c121SKalle Valo 3190e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3191e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 31927a14c23dSSara Sharon 31937a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3194e705c121SKalle Valo 3195e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 319669f0e505SShahar S Matityahu if (fw_mon->size) { 319769f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 319869f0e505SShahar S Matityahu monitor_len = fw_mon->size; 319991c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 32007a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3201e705c121SKalle Valo /* 3202e705c121SKalle Valo * Update pointers to reflect actual values after 3203e705c121SKalle Valo * shifting 3204e705c121SKalle Valo */ 320591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3206fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3207fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 320891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3209fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3210fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3211fd527eb5SGolan Ben Ami } else { 3212e705c121SKalle Valo base = iwl_read_prph(trans, base) << 321391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3214fd527eb5SGolan Ben Ami } 3215fd527eb5SGolan Ben Ami 3216e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3217e705c121SKalle Valo monitor_len / sizeof(u32)); 321891c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3219e705c121SKalle Valo monitor_len = 3220e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3221e705c121SKalle Valo fw_mon_data, 3222e705c121SKalle Valo monitor_len); 3223e705c121SKalle Valo } else { 3224e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3225e705c121SKalle Valo monitor_len = 0; 3226e705c121SKalle Valo } 3227e705c121SKalle Valo 3228e705c121SKalle Valo len += monitor_len; 3229e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3230e705c121SKalle Valo } 3231e705c121SKalle Valo 3232e705c121SKalle Valo return len; 3233e705c121SKalle Valo } 3234e705c121SKalle Valo 323593079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3236e705c121SKalle Valo { 323769f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3238da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3239da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 324069f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 324169f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 324291c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3243da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3244e705c121SKalle Valo 324591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 324691c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3247fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3248fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 324991c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3250fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3251fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3252fd527eb5SGolan Ben Ami 3253fd527eb5SGolan Ben Ami monitor_len = 3254fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 325591c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3256fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3257fd527eb5SGolan Ben Ami } else { 325891c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 325991c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3260e705c121SKalle Valo 3261e705c121SKalle Valo base = iwl_read_prph(trans, base) << 326291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3263e705c121SKalle Valo end = iwl_read_prph(trans, end) << 326491c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3265e705c121SKalle Valo 3266e705c121SKalle Valo /* Make "end" point to the actual end */ 3267286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3268fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 326991c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 327091c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3271e705c121SKalle Valo monitor_len = end - base; 3272fd527eb5SGolan Ben Ami } 3273da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3274da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3275e705c121SKalle Valo monitor_len; 3276da752717SShahar S Matityahu return monitor_len; 3277e705c121SKalle Valo } 3278da752717SShahar S Matityahu return 0; 3279da752717SShahar S Matityahu } 3280da752717SShahar S Matityahu 3281da752717SShahar S Matityahu static struct iwl_trans_dump_data 3282da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 328379f033f6SSara Sharon u32 dump_mask) 3284da752717SShahar S Matityahu { 3285da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3286da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3287da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3288da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3289da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3290fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3291da752717SShahar S Matityahu int i, ptr; 3292da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3293286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 329479f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 329579f033f6SSara Sharon 329679f033f6SSara Sharon if (!dump_mask) 329779f033f6SSara Sharon return NULL; 3298da752717SShahar S Matityahu 3299da752717SShahar S Matityahu /* transport dump header */ 3300da752717SShahar S Matityahu len = sizeof(*dump_data); 3301da752717SShahar S Matityahu 3302da752717SShahar S Matityahu /* host commands */ 3303e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3304da752717SShahar S Matityahu len += sizeof(*data) + 33058672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 33068672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3307da752717SShahar S Matityahu 3308da752717SShahar S Matityahu /* FW monitor */ 3309fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3310da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3311e705c121SKalle Valo 3312e705c121SKalle Valo /* CSR registers */ 331379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3314e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3315e705c121SKalle Valo 3316e705c121SKalle Valo /* FH registers */ 331779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3318286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3319723b45e2SLiad Kaufman len += sizeof(*data) + 3320ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3321ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3322723b45e2SLiad Kaufman else 3323723b45e2SLiad Kaufman len += sizeof(*data) + 3324520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3325520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3326520f03eaSShahar S Matityahu } 3327e705c121SKalle Valo 3328e705c121SKalle Valo if (dump_rbs) { 332978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 333078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3331e705c121SKalle Valo /* RBs */ 33320307c839SGolan Ben Ami num_rbs = 33330307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3334e705c121SKalle Valo & 0x0FFF; 333578485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3336e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3337e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3338e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3339e705c121SKalle Valo } 3340e705c121SKalle Valo 33415538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3342286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3343505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 33445538409bSLiad Kaufman len += sizeof(*data) + 33455538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3346505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 33475538409bSLiad Kaufman 3348e705c121SKalle Valo dump_data = vzalloc(len); 3349e705c121SKalle Valo if (!dump_data) 3350e705c121SKalle Valo return NULL; 3351e705c121SKalle Valo 3352e705c121SKalle Valo len = 0; 3353e705c121SKalle Valo data = (void *)dump_data->data; 3354520f03eaSShahar S Matityahu 3355e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3356520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3357520f03eaSShahar S Matityahu 3358e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3359e705c121SKalle Valo txcmd = (void *)data->data; 3360e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3361bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3362bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33634ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 336408326a97SJohannes Berg u8 tfdidx; 3365e705c121SKalle Valo u32 caplen, cmdlen; 3366e705c121SKalle Valo 336708326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 336808326a97SJohannes Berg tfdidx = idx; 336908326a97SJohannes Berg else 337008326a97SJohannes Berg tfdidx = ptr; 337108326a97SJohannes Berg 3372520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 337308326a97SJohannes Berg (u8 *)cmdq->tfds + 337408326a97SJohannes Berg tfd_size * tfdidx); 3375e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3376e705c121SKalle Valo 3377e705c121SKalle Valo if (cmdlen) { 3378e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3379e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3380e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3381520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3382520f03eaSShahar S Matityahu caplen); 3383e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3384e705c121SKalle Valo } 3385e705c121SKalle Valo 33867b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3387e705c121SKalle Valo } 3388e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3389e705c121SKalle Valo 3390e705c121SKalle Valo data->len = cpu_to_le32(len); 3391e705c121SKalle Valo len += sizeof(*data); 3392e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3393520f03eaSShahar S Matityahu } 3394e705c121SKalle Valo 339579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3396e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 339779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3398e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3399e705c121SKalle Valo if (dump_rbs) 3400e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3401e705c121SKalle Valo 34025538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3403286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 340479b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3405505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 34065538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3407505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 34085538409bSLiad Kaufman 34095538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 34105538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 34115538409bSLiad Kaufman paging = (void *)data->data; 34125538409bSLiad Kaufman paging->index = cpu_to_le32(i); 34135538409bSLiad Kaufman memcpy(paging->data, 3414505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 34155538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 34165538409bSLiad Kaufman 34175538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 34185538409bSLiad Kaufman } 34195538409bSLiad Kaufman } 342079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3421e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3422e705c121SKalle Valo 3423e705c121SKalle Valo dump_data->len = len; 3424e705c121SKalle Valo 3425e705c121SKalle Valo return dump_data; 3426e705c121SKalle Valo } 3427e705c121SKalle Valo 34284cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 34294cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 34304cbb8e50SLuciano Coelho { 34314cbb8e50SLuciano Coelho return 0; 34324cbb8e50SLuciano Coelho } 34334cbb8e50SLuciano Coelho 34344cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 34354cbb8e50SLuciano Coelho { 34364cbb8e50SLuciano Coelho } 34374cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 34384cbb8e50SLuciano Coelho 3439623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3440623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3441623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3442623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3443623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3444623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3445623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3446623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3447623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 34487f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3449623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3450623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3451870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3452623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3453623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3454623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3455623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3456623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3457d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 3458d1967ce6SShahar S Matityahu .sync_nmi = iwl_trans_pcie_sync_nmi 3459623e7766SSara Sharon 3460623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3461623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3462623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3463623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3464623e7766SSara Sharon #else 3465623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3466623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3467623e7766SSara Sharon 3468e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3469623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3470623e7766SSara Sharon IWL_TRANS_PM_OPS 3471e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3472e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3473e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3474e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3475e705c121SKalle Valo 3476e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3477e705c121SKalle Valo 3478e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3479e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3480e705c121SKalle Valo 3481e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3482e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3483e705c121SKalle Valo 348442db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 348542db09c1SLiad Kaufman 3486d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3487d6d517b7SSara Sharon 3488e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 34890cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3490f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3491f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3492f7805b33SLior Cohen #endif 3493623e7766SSara Sharon }; 3494e705c121SKalle Valo 3495623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3496623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3497623e7766SSara Sharon IWL_TRANS_PM_OPS 3498623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3499eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3500eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 350177c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3502e705c121SKalle Valo 3503ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3504e705c121SKalle Valo 3505ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3506623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3507623e7766SSara Sharon 3508ba7136f3SAlex Malamud .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3509ba7136f3SAlex Malamud 35106b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 35116b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3512d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 351392536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3514f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3515f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3516f7805b33SLior Cohen #endif 3517e705c121SKalle Valo }; 3518e705c121SKalle Valo 3519e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3520e705c121SKalle Valo const struct pci_device_id *ent, 35217e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3522e705c121SKalle Valo { 3523e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3524e705c121SKalle Valo struct iwl_trans *trans; 3525a89c72ffSJohannes Berg int ret, addr_size, txcmd_size, txcmd_align; 3526a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3527a89c72ffSJohannes Berg 3528a89c72ffSJohannes Berg if (!cfg_trans->gen2) { 3529a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3530a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd); 3531a89c72ffSJohannes Berg txcmd_align = sizeof(void *); 3532a89c72ffSJohannes Berg } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) { 3533a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd_gen2); 3534a89c72ffSJohannes Berg txcmd_align = 64; 3535a89c72ffSJohannes Berg } else { 3536a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd_gen3); 3537a89c72ffSJohannes Berg txcmd_align = 128; 3538a89c72ffSJohannes Berg } 3539a89c72ffSJohannes Berg 3540a89c72ffSJohannes Berg txcmd_size += sizeof(struct iwl_cmd_header); 3541a89c72ffSJohannes Berg txcmd_size += 36; /* biggest possible 802.11 header */ 3542a89c72ffSJohannes Berg 3543a89c72ffSJohannes Berg /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */ 3544a89c72ffSJohannes Berg if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align)) 3545a89c72ffSJohannes Berg return ERR_PTR(-EINVAL); 3546e705c121SKalle Valo 35475a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 35485a41a86cSSharon Dvir if (ret) 35495a41a86cSSharon Dvir return ERR_PTR(ret); 35505a41a86cSSharon Dvir 3551a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3552a89c72ffSJohannes Berg txcmd_size, txcmd_align); 3553e705c121SKalle Valo if (!trans) 3554e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3555e705c121SKalle Valo 3556e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3557e705c121SKalle Valo 3558e705c121SKalle Valo trans_pcie->trans = trans; 3559326477e4SJohannes Berg trans_pcie->opmode_down = true; 3560e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3561e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3562cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3563e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3564e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 35658188a18eSJohannes Berg 35668188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35678188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35688188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35698188a18eSJohannes Berg ret = -ENOMEM; 35708188a18eSJohannes Berg goto out_free_trans; 35718188a18eSJohannes Berg } 35728188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35738188a18eSJohannes Berg 35746eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 35756eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 35766eb5e529SEmmanuel Grumbach ret = -ENOMEM; 35776eb5e529SEmmanuel Grumbach goto out_no_pci; 35786eb5e529SEmmanuel Grumbach } 3579c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3580e705c121SKalle Valo 35817e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3582e705c121SKalle Valo /* 3583e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3584e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3585e705c121SKalle Valo * lot of power. 3586e705c121SKalle Valo */ 3587e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3588e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3589e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3590e705c121SKalle Valo } 3591e705c121SKalle Valo 35929416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 35939416560eSGolan Ben Ami 35947e8258c0SLuca Coelho if (cfg_trans->use_tfh) { 35952c6262b7SSara Sharon addr_size = 64; 35963cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 35978352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 35986983ba69SSara Sharon } else { 35992c6262b7SSara Sharon addr_size = 36; 36003cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 36016983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 36026983ba69SSara Sharon } 36033cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 36043cd1980bSSara Sharon 3605e705c121SKalle Valo pci_set_master(pdev); 3606e705c121SKalle Valo 360796a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3608e705c121SKalle Valo if (!ret) 360996a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 361096a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3611e705c121SKalle Valo if (ret) { 3612e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3613e705c121SKalle Valo if (!ret) 3614e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3615e705c121SKalle Valo DMA_BIT_MASK(32)); 3616e705c121SKalle Valo /* both attempts failed: */ 3617e705c121SKalle Valo if (ret) { 3618e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 36195a41a86cSSharon Dvir goto out_no_pci; 3620e705c121SKalle Valo } 3621e705c121SKalle Valo } 3622e705c121SKalle Valo 36235a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3624e705c121SKalle Valo if (ret) { 36255a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 36265a41a86cSSharon Dvir goto out_no_pci; 3627e705c121SKalle Valo } 3628e705c121SKalle Valo 36295a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3630e705c121SKalle Valo if (!trans_pcie->hw_base) { 36315a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3632e705c121SKalle Valo ret = -ENODEV; 36335a41a86cSSharon Dvir goto out_no_pci; 3634e705c121SKalle Valo } 3635e705c121SKalle Valo 3636e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3637e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3638e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3639e705c121SKalle Valo 3640e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3641e705c121SKalle Valo iwl_disable_interrupts(trans); 3642e705c121SKalle Valo 3643e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 36449a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 36459a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 36469a098a89SRajat Jain ret = -EIO; 36479a098a89SRajat Jain goto out_no_pci; 36489a098a89SRajat Jain } 36499a098a89SRajat Jain 3650e705c121SKalle Valo /* 3651e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3652e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3653e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3654e705c121SKalle Valo * in the old format. 3655e705c121SKalle Valo */ 36567e8258c0SLuca Coelho if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) { 3657e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3658e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3659e705c121SKalle Valo 3660e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3661e705c121SKalle Valo if (ret) { 3662e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 36635a41a86cSSharon Dvir goto out_no_pci; 3664e705c121SKalle Valo } 3665e705c121SKalle Valo 3666e705c121SKalle Valo /* 3667e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3668e705c121SKalle Valo * id located at the AUX bus MISC address space. 3669e705c121SKalle Valo */ 36707e8258c0SLuca Coelho ret = iwl_finish_nic_init(trans, cfg_trans); 3671c96b5eecSJohannes Berg if (ret) 36725a41a86cSSharon Dvir goto out_no_pci; 3673e705c121SKalle Valo 3674e705c121SKalle Valo } 3675e705c121SKalle Valo 367699be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 367799be6166SLuca Coelho 36787e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3679e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3680e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3681e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3682e705c121SKalle Valo 3683e705c121SKalle Valo /* Initialize the wait queue for commands */ 3684e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3685e705c121SKalle Valo 3686e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3687e5f3f215SHaim Dreyfuss 36882e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36892388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36902388bd7bSDan Carpenter if (ret) 36915a41a86cSSharon Dvir goto out_no_pci; 36922e5d4a8fSHaim Dreyfuss } else { 3693e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3694e705c121SKalle Valo if (ret) 36955a41a86cSSharon Dvir goto out_no_pci; 3696e705c121SKalle Valo 36975a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36985a41a86cSSharon Dvir iwl_pcie_isr, 3699e705c121SKalle Valo iwl_pcie_irq_handler, 3700e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3701e705c121SKalle Valo if (ret) { 3702e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3703e705c121SKalle Valo goto out_free_ict; 3704e705c121SKalle Valo } 3705e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 37062e5d4a8fSHaim Dreyfuss } 3707e705c121SKalle Valo 3708f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3709f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3710f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3711f7805b33SLior Cohen #endif 3712f7805b33SLior Cohen 3713a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3714a9248de4SShahar S Matityahu 3715e705c121SKalle Valo return trans; 3716e705c121SKalle Valo 3717e705c121SKalle Valo out_free_ict: 3718e705c121SKalle Valo iwl_pcie_free_ict(trans); 3719e705c121SKalle Valo out_no_pci: 37206eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 37218188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 37228188a18eSJohannes Berg out_free_trans: 3723e705c121SKalle Valo iwl_trans_free(trans); 3724e705c121SKalle Valo return ERR_PTR(ret); 3725e705c121SKalle Valo } 3726b8a7547dSShahar S Matityahu 3727d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3728b8a7547dSShahar S Matityahu { 37291c6bca6dSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3730b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3731e4eee943SShahar S Matityahu bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 37321c6bca6dSShahar S Matityahu u32 inta_addr, sw_err_bit; 37331c6bca6dSShahar S Matityahu 37341c6bca6dSShahar S Matityahu if (trans_pcie->msix_enabled) { 37351c6bca6dSShahar S Matityahu inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 37361c6bca6dSShahar S Matityahu sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 37371c6bca6dSShahar S Matityahu } else { 37381c6bca6dSShahar S Matityahu inta_addr = CSR_INT; 37391c6bca6dSShahar S Matityahu sw_err_bit = CSR_INT_BIT_SW_ERR; 37401c6bca6dSShahar S Matityahu } 3741b8a7547dSShahar S Matityahu 3742e4eee943SShahar S Matityahu /* if the interrupts were already disabled, there is no point in 3743e4eee943SShahar S Matityahu * calling iwl_disable_interrupts 3744e4eee943SShahar S Matityahu */ 3745e4eee943SShahar S Matityahu if (interrupts_enabled) 3746b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3747e4eee943SShahar S Matityahu 3748b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3749b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 37501c6bca6dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, inta_addr); 3751b8a7547dSShahar S Matityahu 3752b8a7547dSShahar S Matityahu /* Error detected by uCode */ 37531c6bca6dSShahar S Matityahu if (inta_hw & sw_err_bit) { 3754b8a7547dSShahar S Matityahu /* Clear causes register */ 37551c6bca6dSShahar S Matityahu iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3756b8a7547dSShahar S Matityahu break; 3757b8a7547dSShahar S Matityahu } 3758b8a7547dSShahar S Matityahu 3759b8a7547dSShahar S Matityahu mdelay(1); 3760b8a7547dSShahar S Matityahu } 3761e4eee943SShahar S Matityahu 3762e4eee943SShahar S Matityahu /* enable interrupts only if there were already enabled before this 3763e4eee943SShahar S Matityahu * function to avoid a case were the driver enable interrupts before 3764e4eee943SShahar S Matityahu * proper configurations were made 3765e4eee943SShahar S Matityahu */ 3766e4eee943SShahar S Matityahu if (interrupts_enabled) 3767b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3768e4eee943SShahar S Matityahu 3769b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3770b8a7547dSShahar S Matityahu } 3771