18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 27e705c121SKalle Valo #include "internal.h" 28e705c121SKalle Valo #include "iwl-fh.h" 296654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 30e705c121SKalle Valo 31e705c121SKalle Valo /* extended range in FW SRAM */ 32e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 34e705c121SKalle Valo 354290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 36a6d24fadSRajat Jain { 37c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 38c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 39c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 40a6d24fadSRajat Jain #define PREFIX_LEN 32 41a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 42a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 43a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 44a6d24fadSRajat Jain char *prefix; 45a6d24fadSRajat Jain 46a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 47a6d24fadSRajat Jain return; 48a6d24fadSRajat Jain 49a6d24fadSRajat Jain /* Should be a multiple of 4 */ 50a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 51c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho 54a6d24fadSRajat Jain /* Alloc a max size buffer */ 55a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 56c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho 60a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 61a6d24fadSRajat Jain if (!buf) 62a6d24fadSRajat Jain return; 63a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 64a6d24fadSRajat Jain 65a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 66a6d24fadSRajat Jain 67a6d24fadSRajat Jain /* Print wifi device registers */ 68a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 69a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 70a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 71a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 72a6d24fadSRajat Jain goto err_read; 73a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 74a6d24fadSRajat Jain 75a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 76c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 77a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 78a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79a6d24fadSRajat Jain 80a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 81a6d24fadSRajat Jain if (pos) { 82a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 83a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 84a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 85a6d24fadSRajat Jain goto err_read; 86a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 87a6d24fadSRajat Jain 32, 4, buf, i, 0); 88a6d24fadSRajat Jain } 89a6d24fadSRajat Jain 90a6d24fadSRajat Jain /* Print parent device registers next */ 91a6d24fadSRajat Jain if (!pdev->bus->self) 92a6d24fadSRajat Jain goto out; 93a6d24fadSRajat Jain 94a6d24fadSRajat Jain pdev = pdev->bus->self; 95a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 96a6d24fadSRajat Jain 97a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 98a6d24fadSRajat Jain pci_name(pdev)); 99c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 100a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 101a6d24fadSRajat Jain goto err_read; 102a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Print root port AER registers */ 105a6d24fadSRajat Jain pos = 0; 106a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 107a6d24fadSRajat Jain if (pdev) 108a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 109a6d24fadSRajat Jain if (pos) { 110a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 111a6d24fadSRajat Jain pci_name(pdev)); 112a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 113a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 114a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 115a6d24fadSRajat Jain goto err_read; 116a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 117a6d24fadSRajat Jain 4, buf, i, 0); 118a6d24fadSRajat Jain } 119f3402d6dSSara Sharon goto out; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain err_read: 122a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 123a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 124a6d24fadSRajat Jain out: 125a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 126a6d24fadSRajat Jain kfree(buf); 127a6d24fadSRajat Jain } 128a6d24fadSRajat Jain 129870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 130870c2a11SGolan Ben Ami { 131870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1326dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 133870c2a11SGolan Ben Ami usleep_range(5000, 6000); 134870c2a11SGolan Ben Ami } 135870c2a11SGolan Ben Ami 136e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 137e705c121SKalle Valo { 13869f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 139e705c121SKalle Valo 14069f0e505SShahar S Matityahu if (!fw_mon->size) 14169f0e505SShahar S Matityahu return; 14269f0e505SShahar S Matityahu 14369f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 14469f0e505SShahar S Matityahu fw_mon->physical); 14569f0e505SShahar S Matityahu 14669f0e505SShahar S Matityahu fw_mon->block = NULL; 14769f0e505SShahar S Matityahu fw_mon->physical = 0; 14869f0e505SShahar S Matityahu fw_mon->size = 0; 149e705c121SKalle Valo } 150e705c121SKalle Valo 15188964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 15288964b2eSSara Sharon u8 max_power, u8 min_power) 153e705c121SKalle Valo { 15469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 15569f0e505SShahar S Matityahu void *block = NULL; 15669f0e505SShahar S Matityahu dma_addr_t physical = 0; 157e705c121SKalle Valo u32 size = 0; 158e705c121SKalle Valo u8 power; 159e705c121SKalle Valo 16069f0e505SShahar S Matityahu if (fw_mon->size) 16169f0e505SShahar S Matityahu return; 16269f0e505SShahar S Matityahu 16388964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 164e705c121SKalle Valo size = BIT(power); 16569f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1662d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 16769f0e505SShahar S Matityahu if (!block) 168e705c121SKalle Valo continue; 169e705c121SKalle Valo 170e705c121SKalle Valo IWL_INFO(trans, 171c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 172c5f97542SShahar S Matityahu size); 173e705c121SKalle Valo break; 174e705c121SKalle Valo } 175e705c121SKalle Valo 17669f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 177e705c121SKalle Valo return; 178e705c121SKalle Valo 179e705c121SKalle Valo if (power != max_power) 180e705c121SKalle Valo IWL_ERR(trans, 181e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 182e705c121SKalle Valo (unsigned long)BIT(power - 10), 183e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 184e705c121SKalle Valo 18569f0e505SShahar S Matityahu fw_mon->block = block; 18669f0e505SShahar S Matityahu fw_mon->physical = physical; 18769f0e505SShahar S Matityahu fw_mon->size = size; 18888964b2eSSara Sharon } 18988964b2eSSara Sharon 19088964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 19188964b2eSSara Sharon { 19288964b2eSSara Sharon if (!max_power) { 19388964b2eSSara Sharon /* default max_power is maximum */ 19488964b2eSSara Sharon max_power = 26; 19588964b2eSSara Sharon } else { 19688964b2eSSara Sharon max_power += 11; 19788964b2eSSara Sharon } 19888964b2eSSara Sharon 19988964b2eSSara Sharon if (WARN(max_power > 26, 20088964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 20188964b2eSSara Sharon max_power)) 20288964b2eSSara Sharon return; 20388964b2eSSara Sharon 20469f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 20588964b2eSSara Sharon return; 20688964b2eSSara Sharon 20788964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 208e705c121SKalle Valo } 209e705c121SKalle Valo 210e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 211e705c121SKalle Valo { 212e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 213e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 214e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 215e705c121SKalle Valo } 216e705c121SKalle Valo 217e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 218e705c121SKalle Valo { 219e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 220e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 221e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 222e705c121SKalle Valo } 223e705c121SKalle Valo 224e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 225e705c121SKalle Valo { 226e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 227e705c121SKalle Valo return; 228e705c121SKalle Valo 229e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 230e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 231e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 232e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 233e705c121SKalle Valo else 234e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 235e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 236e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 237e705c121SKalle Valo } 238e705c121SKalle Valo 239e705c121SKalle Valo /* PCI registers */ 240e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 241e705c121SKalle Valo 242eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 243e705c121SKalle Valo { 244e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 245e705c121SKalle Valo u16 lctl; 246e705c121SKalle Valo u16 cap; 247e705c121SKalle Valo 248e705c121SKalle Valo /* 249cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 250cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 251cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 252e705c121SKalle Valo */ 2533d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 254cc894b85SLuca Coelho 255cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 256e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 257e705c121SKalle Valo 258e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 259e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 260d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 261e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 262e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 263e705c121SKalle Valo } 264e705c121SKalle Valo 265e705c121SKalle Valo /* 266e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 267e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 268e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 269e705c121SKalle Valo */ 270e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 271e705c121SKalle Valo { 27252b6e168SEmmanuel Grumbach int ret; 27352b6e168SEmmanuel Grumbach 274e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 275e705c121SKalle Valo 276e705c121SKalle Valo /* 277e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 278e705c121SKalle Valo * bits already set by default after reset. 279e705c121SKalle Valo */ 280e705c121SKalle Valo 281e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 282286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 283e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 284e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 285e705c121SKalle Valo 286e705c121SKalle Valo /* 287e705c121SKalle Valo * Disable L0s without affecting L1; 288e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 289e705c121SKalle Valo */ 290e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 291e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 292e705c121SKalle Valo 293e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 294e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 295e705c121SKalle Valo 296e705c121SKalle Valo /* 297e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 298e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 299e705c121SKalle Valo */ 300e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 301e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 302e705c121SKalle Valo 303e705c121SKalle Valo iwl_pcie_apm_config(trans); 304e705c121SKalle Valo 305e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 306286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 30777d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 308e705c121SKalle Valo 3097d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 310c96b5eecSJohannes Berg if (ret) 31152b6e168SEmmanuel Grumbach return ret; 312e705c121SKalle Valo 313e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 314e705c121SKalle Valo /* 315e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 316e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 317e705c121SKalle Valo * not related to host_interrupt_operation_mode. 318e705c121SKalle Valo * 319e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 320e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 321e705c121SKalle Valo * that we wake up from L1 on time. 322e705c121SKalle Valo * 323e705c121SKalle Valo * This looks weird: read twice the same register, discard the 324e705c121SKalle Valo * value, set a bit, and yet again, read that same register 325e705c121SKalle Valo * just to discard the value. But that's the way the hardware 326e705c121SKalle Valo * seems to like it. 327e705c121SKalle Valo */ 328e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 329e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 330e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 331e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 332e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo /* 336e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 337e705c121SKalle Valo * 338e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 339e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 340e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 341e705c121SKalle Valo */ 342e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 343e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 344e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 345e705c121SKalle Valo udelay(20); 346e705c121SKalle Valo 347e705c121SKalle Valo /* Disable L1-Active */ 348e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 349e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 350e705c121SKalle Valo 351e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 352e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 353e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 354e705c121SKalle Valo } 355e705c121SKalle Valo 356e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 357e705c121SKalle Valo 35852b6e168SEmmanuel Grumbach return 0; 359e705c121SKalle Valo } 360e705c121SKalle Valo 361e705c121SKalle Valo /* 362e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 363e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 364e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 365e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 366e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 367e705c121SKalle Valo */ 368e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 369e705c121SKalle Valo { 370e705c121SKalle Valo int ret; 371e705c121SKalle Valo u32 apmg_gp1_reg; 372e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 373e705c121SKalle Valo u32 dl_cfg_reg; 374e705c121SKalle Valo 375e705c121SKalle Valo /* Force XTAL ON */ 376e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 377e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 378e705c121SKalle Valo 379870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 380e705c121SKalle Valo 3817d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 382c96b5eecSJohannes Berg if (WARN_ON(ret)) { 383e705c121SKalle Valo /* Release XTAL ON request */ 384e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 385e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo /* 390e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 391e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 392e705c121SKalle Valo */ 393e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 394e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 395e705c121SKalle Valo 396e705c121SKalle Valo /* 397e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 398e705c121SKalle Valo * caused by APMG idle state. 399e705c121SKalle Valo */ 400e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 401e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 402e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 403e705c121SKalle Valo apmg_xtal_cfg_reg | 404e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 405e705c121SKalle Valo 406870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 407e705c121SKalle Valo 408e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 409e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 410e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 411e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 412e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Clear delay line clock power up */ 415e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 417e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 418e705c121SKalle Valo 419e705c121SKalle Valo /* 420e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 421e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 422e705c121SKalle Valo */ 423e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 424e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 425e705c121SKalle Valo 426e705c121SKalle Valo /* 427e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 428e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 429e705c121SKalle Valo */ 4306dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 431e705c121SKalle Valo 432e705c121SKalle Valo /* Activates XTAL resources monitor */ 433e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 434e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 435e705c121SKalle Valo 436e705c121SKalle Valo /* Release XTAL ON request */ 437e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 438e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 439e705c121SKalle Valo udelay(10); 440e705c121SKalle Valo 441e705c121SKalle Valo /* Release APMG XTAL */ 442e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 443e705c121SKalle Valo apmg_xtal_cfg_reg & 444e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 445e705c121SKalle Valo } 446e705c121SKalle Valo 447e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 448e705c121SKalle Valo { 449e8c8935eSJohannes Berg int ret; 450e705c121SKalle Valo 451e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4526dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 453e705c121SKalle Valo 4546dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4556dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4566dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 457e705c121SKalle Valo if (ret < 0) 458e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 459e705c121SKalle Valo 460e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 461e705c121SKalle Valo } 462e705c121SKalle Valo 463e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 464e705c121SKalle Valo { 465e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 466e705c121SKalle Valo 467e705c121SKalle Valo if (op_mode_leave) { 468e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 469e705c121SKalle Valo iwl_pcie_apm_init(trans); 470e705c121SKalle Valo 471e705c121SKalle Valo /* inform ME that we are leaving */ 472286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 473e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 474e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 475286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 47679b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 477e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 478e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 479e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 480e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 481e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 482e705c121SKalle Valo mdelay(1); 483e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 484e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 485e705c121SKalle Valo } 486e705c121SKalle Valo mdelay(5); 487e705c121SKalle Valo } 488e705c121SKalle Valo 489e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 490e705c121SKalle Valo 491e705c121SKalle Valo /* Stop device's DMA activity */ 492e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 493e705c121SKalle Valo 494e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 495e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 496e705c121SKalle Valo return; 497e705c121SKalle Valo } 498e705c121SKalle Valo 499870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 500e705c121SKalle Valo 501e705c121SKalle Valo /* 502e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 503e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 504e705c121SKalle Valo */ 5056dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 506e705c121SKalle Valo } 507e705c121SKalle Valo 508e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 509e705c121SKalle Valo { 510e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 51152b6e168SEmmanuel Grumbach int ret; 512e705c121SKalle Valo 513e705c121SKalle Valo /* nic_init */ 514e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 51552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 516e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 517e705c121SKalle Valo 51852b6e168SEmmanuel Grumbach if (ret) 51952b6e168SEmmanuel Grumbach return ret; 52052b6e168SEmmanuel Grumbach 521e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 522e705c121SKalle Valo 523e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 524e705c121SKalle Valo 525e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 526e705c121SKalle Valo iwl_pcie_rx_init(trans); 527e705c121SKalle Valo 528e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 529e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 530e705c121SKalle Valo return -ENOMEM; 531e705c121SKalle Valo 532286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 533e705c121SKalle Valo /* enable shadow regs in HW */ 534e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 535e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 536e705c121SKalle Valo } 537e705c121SKalle Valo 538e705c121SKalle Valo return 0; 539e705c121SKalle Valo } 540e705c121SKalle Valo 541e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 542e705c121SKalle Valo 543e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 544e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 545e705c121SKalle Valo { 546e705c121SKalle Valo int ret; 547e705c121SKalle Valo 548e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 549e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 550e705c121SKalle Valo 551e705c121SKalle Valo /* See if we got it */ 552e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 553e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 554e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 555e705c121SKalle Valo HW_READY_TIMEOUT); 556e705c121SKalle Valo 557e705c121SKalle Valo if (ret >= 0) 558e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 559e705c121SKalle Valo 560e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 561e705c121SKalle Valo return ret; 562e705c121SKalle Valo } 563e705c121SKalle Valo 564e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 565eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 566e705c121SKalle Valo { 567e705c121SKalle Valo int ret; 568e705c121SKalle Valo int t = 0; 569e705c121SKalle Valo int iter; 570e705c121SKalle Valo 571e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 572e705c121SKalle Valo 573e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 574e705c121SKalle Valo /* If the card is ready, exit 0 */ 575e705c121SKalle Valo if (ret >= 0) 576e705c121SKalle Valo return 0; 577e705c121SKalle Valo 578e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 579e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 580192185d6SJohannes Berg usleep_range(1000, 2000); 581e705c121SKalle Valo 582e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 583e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 584e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 585e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 586e705c121SKalle Valo 587e705c121SKalle Valo do { 588e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 589e705c121SKalle Valo if (ret >= 0) 590e705c121SKalle Valo return 0; 591e705c121SKalle Valo 592e705c121SKalle Valo usleep_range(200, 1000); 593e705c121SKalle Valo t += 200; 594e705c121SKalle Valo } while (t < 150000); 595e705c121SKalle Valo msleep(25); 596e705c121SKalle Valo } 597e705c121SKalle Valo 598e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 599e705c121SKalle Valo 600e705c121SKalle Valo return ret; 601e705c121SKalle Valo } 602e705c121SKalle Valo 603e705c121SKalle Valo /* 604e705c121SKalle Valo * ucode 605e705c121SKalle Valo */ 606564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 607564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 608564cdce7SSara Sharon u32 byte_cnt) 609e705c121SKalle Valo { 610bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 611e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 612e705c121SKalle Valo 613bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 614e705c121SKalle Valo dst_addr); 615e705c121SKalle Valo 616bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 617e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 618e705c121SKalle Valo 619bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 620e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 621e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 622e705c121SKalle Valo 623bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 624bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 625bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 626e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 627e705c121SKalle Valo 628bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 629e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 630e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 631e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 632564cdce7SSara Sharon } 633e705c121SKalle Valo 634564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 635564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 636564cdce7SSara Sharon u32 byte_cnt) 637564cdce7SSara Sharon { 638564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 639564cdce7SSara Sharon unsigned long flags; 640564cdce7SSara Sharon int ret; 641564cdce7SSara Sharon 642564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 643564cdce7SSara Sharon 644564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 645564cdce7SSara Sharon return -EIO; 646564cdce7SSara Sharon 647564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 648564cdce7SSara Sharon byte_cnt); 649bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 650bac842daSEmmanuel Grumbach 651e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 652e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 653e705c121SKalle Valo if (!ret) { 654e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 655fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 656e705c121SKalle Valo return -ETIMEDOUT; 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo return 0; 660e705c121SKalle Valo } 661e705c121SKalle Valo 662e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 663e705c121SKalle Valo const struct fw_desc *section) 664e705c121SKalle Valo { 665e705c121SKalle Valo u8 *v_addr; 666e705c121SKalle Valo dma_addr_t p_addr; 667e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 668e705c121SKalle Valo int ret = 0; 669e705c121SKalle Valo 670e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 671e705c121SKalle Valo section_num); 672e705c121SKalle Valo 673e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 674e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 675e705c121SKalle Valo if (!v_addr) { 676e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 677e705c121SKalle Valo chunk_sz = PAGE_SIZE; 678e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 679e705c121SKalle Valo &p_addr, GFP_KERNEL); 680e705c121SKalle Valo if (!v_addr) 681e705c121SKalle Valo return -ENOMEM; 682e705c121SKalle Valo } 683e705c121SKalle Valo 684e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 685e705c121SKalle Valo u32 copy_size, dst_addr; 686e705c121SKalle Valo bool extended_addr = false; 687e705c121SKalle Valo 688e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 689e705c121SKalle Valo dst_addr = section->offset + offset; 690e705c121SKalle Valo 691e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 692e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 693e705c121SKalle Valo extended_addr = true; 694e705c121SKalle Valo 695e705c121SKalle Valo if (extended_addr) 696e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 697e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 698e705c121SKalle Valo 699e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 700e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 701e705c121SKalle Valo copy_size); 702e705c121SKalle Valo 703e705c121SKalle Valo if (extended_addr) 704e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 705e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 706e705c121SKalle Valo 707e705c121SKalle Valo if (ret) { 708e705c121SKalle Valo IWL_ERR(trans, 709e705c121SKalle Valo "Could not load the [%d] uCode section\n", 710e705c121SKalle Valo section_num); 711e705c121SKalle Valo break; 712e705c121SKalle Valo } 713e705c121SKalle Valo } 714e705c121SKalle Valo 715e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 716e705c121SKalle Valo return ret; 717e705c121SKalle Valo } 718e705c121SKalle Valo 719e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 720e705c121SKalle Valo const struct fw_img *image, 721e705c121SKalle Valo int cpu, 722e705c121SKalle Valo int *first_ucode_section) 723e705c121SKalle Valo { 724e705c121SKalle Valo int shift_param; 725e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 726e705c121SKalle Valo u32 val, last_read_idx = 0; 727e705c121SKalle Valo 728e705c121SKalle Valo if (cpu == 1) { 729e705c121SKalle Valo shift_param = 0; 730e705c121SKalle Valo *first_ucode_section = 0; 731e705c121SKalle Valo } else { 732e705c121SKalle Valo shift_param = 16; 733e705c121SKalle Valo (*first_ucode_section)++; 734e705c121SKalle Valo } 735e705c121SKalle Valo 736eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 737e705c121SKalle Valo last_read_idx = i; 738e705c121SKalle Valo 739e705c121SKalle Valo /* 740e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 741e705c121SKalle Valo * CPU1 to CPU2. 742e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 743e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 744e705c121SKalle Valo */ 745e705c121SKalle Valo if (!image->sec[i].data || 746e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 747e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 748e705c121SKalle Valo IWL_DEBUG_FW(trans, 749e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 750e705c121SKalle Valo i); 751e705c121SKalle Valo break; 752e705c121SKalle Valo } 753e705c121SKalle Valo 754e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 755e705c121SKalle Valo if (ret) 756e705c121SKalle Valo return ret; 757e705c121SKalle Valo 758d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 759e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 760e705c121SKalle Valo val = val | (sec_num << shift_param); 761e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 762eda50cdeSSara Sharon 763e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 764e705c121SKalle Valo } 765e705c121SKalle Valo 766e705c121SKalle Valo *first_ucode_section = last_read_idx; 767e705c121SKalle Valo 7682aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 7692aabdbdcSEmmanuel Grumbach 770286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 771e705c121SKalle Valo if (cpu == 1) 772d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 773d6a2c5c7SSara Sharon 0xFFFF); 774e705c121SKalle Valo else 775d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 776d6a2c5c7SSara Sharon 0xFFFFFFFF); 777d6a2c5c7SSara Sharon } else { 778d6a2c5c7SSara Sharon if (cpu == 1) 779d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 780d6a2c5c7SSara Sharon 0xFFFF); 781d6a2c5c7SSara Sharon else 782d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 783d6a2c5c7SSara Sharon 0xFFFFFFFF); 784d6a2c5c7SSara Sharon } 785e705c121SKalle Valo 786e705c121SKalle Valo return 0; 787e705c121SKalle Valo } 788e705c121SKalle Valo 789e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 790e705c121SKalle Valo const struct fw_img *image, 791e705c121SKalle Valo int cpu, 792e705c121SKalle Valo int *first_ucode_section) 793e705c121SKalle Valo { 794e705c121SKalle Valo int i, ret = 0; 795e705c121SKalle Valo u32 last_read_idx = 0; 796e705c121SKalle Valo 7973ce4a038SKirtika Ruchandani if (cpu == 1) 798e705c121SKalle Valo *first_ucode_section = 0; 7993ce4a038SKirtika Ruchandani else 800e705c121SKalle Valo (*first_ucode_section)++; 801e705c121SKalle Valo 802eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 803e705c121SKalle Valo last_read_idx = i; 804e705c121SKalle Valo 805e705c121SKalle Valo /* 806e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 807e705c121SKalle Valo * CPU1 to CPU2. 808e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 809e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 810e705c121SKalle Valo */ 811e705c121SKalle Valo if (!image->sec[i].data || 812e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 813e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 814e705c121SKalle Valo IWL_DEBUG_FW(trans, 815e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 816e705c121SKalle Valo i); 817e705c121SKalle Valo break; 818e705c121SKalle Valo } 819e705c121SKalle Valo 820e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 821e705c121SKalle Valo if (ret) 822e705c121SKalle Valo return ret; 823e705c121SKalle Valo } 824e705c121SKalle Valo 825e705c121SKalle Valo *first_ucode_section = last_read_idx; 826e705c121SKalle Valo 827e705c121SKalle Valo return 0; 828e705c121SKalle Valo } 829e705c121SKalle Valo 830593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 831593fae3eSShahar S Matityahu { 832593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 833593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 834593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 835593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 836593fae3eSShahar S Matityahu 837593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 838593fae3eSShahar S Matityahu return; 839593fae3eSShahar S Matityahu 840593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 841593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 842593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 843593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 844593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 845593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 846593fae3eSShahar S Matityahu 847593fae3eSShahar S Matityahu return; 848593fae3eSShahar S Matityahu } 849593fae3eSShahar S Matityahu 850593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 851593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 852593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 853593fae3eSShahar S Matityahu return; 854593fae3eSShahar S Matityahu 855593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 856593fae3eSShahar S Matityahu 857593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 858593fae3eSShahar S Matityahu alloc_id); 859593fae3eSShahar S Matityahu 860593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 861593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 862593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 863593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 864593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 865593fae3eSShahar S Matityahu } 866593fae3eSShahar S Matityahu 867c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 868e705c121SKalle Valo { 86991c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 87069f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 871e705c121SKalle Valo int i; 872e705c121SKalle Valo 873a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 874593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 8757a14c23dSSara Sharon return; 8767a14c23dSSara Sharon } 8777a14c23dSSara Sharon 878e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 879e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 880e705c121SKalle Valo 881e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 882e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 883e705c121SKalle Valo else 884e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 885e705c121SKalle Valo 88691c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 887e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 888e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 889e705c121SKalle Valo 890e705c121SKalle Valo switch (dest->reg_ops[i].op) { 891e705c121SKalle Valo case CSR_ASSIGN: 892e705c121SKalle Valo iwl_write32(trans, addr, val); 893e705c121SKalle Valo break; 894e705c121SKalle Valo case CSR_SETBIT: 895e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 896e705c121SKalle Valo break; 897e705c121SKalle Valo case CSR_CLEARBIT: 898e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 899e705c121SKalle Valo break; 900e705c121SKalle Valo case PRPH_ASSIGN: 901e705c121SKalle Valo iwl_write_prph(trans, addr, val); 902e705c121SKalle Valo break; 903e705c121SKalle Valo case PRPH_SETBIT: 904e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 905e705c121SKalle Valo break; 906e705c121SKalle Valo case PRPH_CLEARBIT: 907e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 908e705c121SKalle Valo break; 909e705c121SKalle Valo case PRPH_BLOCKBIT: 910e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 911e705c121SKalle Valo IWL_ERR(trans, 912e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 913e705c121SKalle Valo val, addr); 914e705c121SKalle Valo goto monitor; 915e705c121SKalle Valo } 916e705c121SKalle Valo break; 917e705c121SKalle Valo default: 918e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 919e705c121SKalle Valo dest->reg_ops[i].op); 920e705c121SKalle Valo break; 921e705c121SKalle Valo } 922e705c121SKalle Valo } 923e705c121SKalle Valo 924e705c121SKalle Valo monitor: 92569f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 926e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 92769f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 928286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 929e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93069f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 93169f0e505SShahar S Matityahu 256) >> dest->end_shift); 93262d7476dSEmmanuel Grumbach else 93362d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93469f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 93562d7476dSEmmanuel Grumbach dest->end_shift); 936e705c121SKalle Valo } 937e705c121SKalle Valo } 938e705c121SKalle Valo 939e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 940e705c121SKalle Valo const struct fw_img *image) 941e705c121SKalle Valo { 942e705c121SKalle Valo int ret = 0; 943e705c121SKalle Valo int first_ucode_section; 944e705c121SKalle Valo 945e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 946e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 947e705c121SKalle Valo 948e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 949e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 950e705c121SKalle Valo if (ret) 951e705c121SKalle Valo return ret; 952e705c121SKalle Valo 953e705c121SKalle Valo if (image->is_dual_cpus) { 954e705c121SKalle Valo /* set CPU2 header address */ 955e705c121SKalle Valo iwl_write_prph(trans, 956e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 957e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 958e705c121SKalle Valo 959e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 960e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 961e705c121SKalle Valo &first_ucode_section); 962e705c121SKalle Valo if (ret) 963e705c121SKalle Valo return ret; 964e705c121SKalle Valo } 965e705c121SKalle Valo 9669efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 967e705c121SKalle Valo iwl_pcie_apply_destination(trans); 968e705c121SKalle Valo 9692aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 9702aabdbdcSEmmanuel Grumbach 971e705c121SKalle Valo /* release CPU reset */ 972e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 973e705c121SKalle Valo 974e705c121SKalle Valo return 0; 975e705c121SKalle Valo } 976e705c121SKalle Valo 977e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 978e705c121SKalle Valo const struct fw_img *image) 979e705c121SKalle Valo { 980e705c121SKalle Valo int ret = 0; 981e705c121SKalle Valo int first_ucode_section; 982e705c121SKalle Valo 983e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 984e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 985e705c121SKalle Valo 9867a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 987e705c121SKalle Valo iwl_pcie_apply_destination(trans); 988e705c121SKalle Valo 98982ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 99082ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 99182ea7966SSara Sharon 99282ea7966SSara Sharon /* 99382ea7966SSara Sharon * Set default value. On resume reading the values that were 99482ea7966SSara Sharon * zeored can provide debug data on the resume flow. 99582ea7966SSara Sharon * This is for debugging only and has no functional impact. 99682ea7966SSara Sharon */ 99782ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 99882ea7966SSara Sharon 999e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1000e705c121SKalle Valo /* release CPU reset */ 1001e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1002e705c121SKalle Valo 1003e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1004e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1005e705c121SKalle Valo &first_ucode_section); 1006e705c121SKalle Valo if (ret) 1007e705c121SKalle Valo return ret; 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1010e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1011e705c121SKalle Valo &first_ucode_section); 1012e705c121SKalle Valo } 1013e705c121SKalle Valo 10149ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1015727c02dfSSara Sharon { 1016326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1017727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1018326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1019326477e4SJohannes Berg bool report; 1020727c02dfSSara Sharon 1021326477e4SJohannes Berg if (hw_rfkill) { 1022326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1023326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1024326477e4SJohannes Berg } else { 1025326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1026326477e4SJohannes Berg if (trans_pcie->opmode_down) 1027326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1028326477e4SJohannes Berg } 1029727c02dfSSara Sharon 1030326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1031326477e4SJohannes Berg 1032326477e4SJohannes Berg if (prev != report) 1033326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1034727c02dfSSara Sharon 1035727c02dfSSara Sharon return hw_rfkill; 1036727c02dfSSara Sharon } 1037727c02dfSSara Sharon 10387ca00409SHaim Dreyfuss struct iwl_causes_list { 10397ca00409SHaim Dreyfuss u32 cause_num; 10407ca00409SHaim Dreyfuss u32 mask_reg; 10417ca00409SHaim Dreyfuss u8 addr; 10427ca00409SHaim Dreyfuss }; 10437ca00409SHaim Dreyfuss 10447ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 10457ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10467ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10477ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10487ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10497ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10507ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1051*906d4eb8SJohannes Berg {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10527ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10537ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 10547ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 10557ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 10567ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 10577ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 10587ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 10597ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 10607ca00409SHaim Dreyfuss }; 10617ca00409SHaim Dreyfuss 10627ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 10637ca00409SHaim Dreyfuss { 10647ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10657ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 10663681021fSJohannes Berg int i, arr_size = ARRAY_SIZE(causes_list); 10673681021fSJohannes Berg struct iwl_causes_list *causes = causes_list; 10687ca00409SHaim Dreyfuss 10697ca00409SHaim Dreyfuss /* 10707ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 10717ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 10727ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 10737ca00409SHaim Dreyfuss */ 10749b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 10759b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 10769b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 10779b58419eSGolan Ben Ami causes[i].cause_num); 10787ca00409SHaim Dreyfuss } 10797ca00409SHaim Dreyfuss } 10807ca00409SHaim Dreyfuss 10817ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 10827ca00409SHaim Dreyfuss { 10837ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 10847ca00409SHaim Dreyfuss u32 offset = 10857ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 10867ca00409SHaim Dreyfuss u32 val, idx; 10877ca00409SHaim Dreyfuss 10887ca00409SHaim Dreyfuss /* 10897ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 10907ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 10917ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 10927ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 10937ca00409SHaim Dreyfuss */ 10947ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 10957ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 10967ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 10977ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 10987ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 10997ca00409SHaim Dreyfuss } 11007ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11017ca00409SHaim Dreyfuss 11027ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11037ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11047ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11057ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11067ca00409SHaim Dreyfuss 11077ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11087ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11097ca00409SHaim Dreyfuss } 11107ca00409SHaim Dreyfuss 111177c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11127ca00409SHaim Dreyfuss { 11137ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11147ca00409SHaim Dreyfuss 11157ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1116286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1117d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1118ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11197ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11207ca00409SHaim Dreyfuss return; 11217ca00409SHaim Dreyfuss } 1122d7270d61SHaim Dreyfuss /* 1123d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1124d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1125d7270d61SHaim Dreyfuss * prph. 1126d7270d61SHaim Dreyfuss */ 1127d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1128ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11297ca00409SHaim Dreyfuss 11307ca00409SHaim Dreyfuss /* 11317ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11327ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11337ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11347ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11357ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11367ca00409SHaim Dreyfuss */ 11377ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 11387ca00409SHaim Dreyfuss 11397ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 114083730058SHaim Dreyfuss } 11417ca00409SHaim Dreyfuss 114283730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 114383730058SHaim Dreyfuss { 114483730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 114583730058SHaim Dreyfuss 114683730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 114783730058SHaim Dreyfuss 114883730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 114983730058SHaim Dreyfuss return; 115083730058SHaim Dreyfuss 115183730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 11527ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 115383730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 11547ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 11557ca00409SHaim Dreyfuss } 11567ca00409SHaim Dreyfuss 1157bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1158e705c121SKalle Valo { 1159e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1160e705c121SKalle Valo 1161e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1162e705c121SKalle Valo 1163e705c121SKalle Valo if (trans_pcie->is_down) 1164e705c121SKalle Valo return; 1165e705c121SKalle Valo 1166e705c121SKalle Valo trans_pcie->is_down = true; 1167e705c121SKalle Valo 1168e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1169e705c121SKalle Valo iwl_disable_interrupts(trans); 1170e705c121SKalle Valo 1171e705c121SKalle Valo /* device going down, Stop using ICT table */ 1172e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1173e705c121SKalle Valo 1174e705c121SKalle Valo /* 1175e705c121SKalle Valo * If a HW restart happens during firmware loading, 1176e705c121SKalle Valo * then the firmware loading might call this function 1177e705c121SKalle Valo * and later it might be called again due to the 1178e705c121SKalle Valo * restart. So don't process again if the device is 1179e705c121SKalle Valo * already dead. 1180e705c121SKalle Valo */ 1181e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1182a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1183a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1184e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1185e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1186e705c121SKalle Valo 1187e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1188e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1189e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1190e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1191e705c121SKalle Valo udelay(5); 1192e705c121SKalle Valo } 1193e705c121SKalle Valo } 1194e705c121SKalle Valo 1195e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1196e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 11976dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1198e705c121SKalle Valo 1199e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1200e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1201e705c121SKalle Valo 1202870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1203e705c121SKalle Valo 1204e705c121SKalle Valo /* 1205f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1206f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1207f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1208f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1209f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1210f4a1f04aSGolan Ben Ami */ 1211f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1212f4a1f04aSGolan Ben Ami 1213f4a1f04aSGolan Ben Ami /* 1214e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1215e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1216e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1217e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1218e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1219e705c121SKalle Valo */ 1220e705c121SKalle Valo iwl_disable_interrupts(trans); 1221e705c121SKalle Valo 1222e705c121SKalle Valo /* clear all status bits */ 1223e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1224e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1225e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1226e705c121SKalle Valo 1227e705c121SKalle Valo /* 1228e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1229e705c121SKalle Valo * interrupt 1230e705c121SKalle Valo */ 1231e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1232e705c121SKalle Valo 1233a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1234e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1235e705c121SKalle Valo } 1236e705c121SKalle Valo 1237eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 12382e5d4a8fSHaim Dreyfuss { 12392e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12402e5d4a8fSHaim Dreyfuss 12412e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 12422e5d4a8fSHaim Dreyfuss int i; 12432e5d4a8fSHaim Dreyfuss 1244496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 12452e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 12462e5d4a8fSHaim Dreyfuss } else { 12472e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 12482e5d4a8fSHaim Dreyfuss } 12492e5d4a8fSHaim Dreyfuss } 12502e5d4a8fSHaim Dreyfuss 1251a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1252a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1253a6bd005fSEmmanuel Grumbach { 1254a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1255a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1256a6bd005fSEmmanuel Grumbach int ret; 1257a6bd005fSEmmanuel Grumbach 1258a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1259a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1260a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1261a6bd005fSEmmanuel Grumbach ret = -EIO; 1262a6bd005fSEmmanuel Grumbach goto out; 1263a6bd005fSEmmanuel Grumbach } 1264a6bd005fSEmmanuel Grumbach 1265a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1266a6bd005fSEmmanuel Grumbach 1267a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1268a6bd005fSEmmanuel Grumbach 1269a6bd005fSEmmanuel Grumbach /* 1270a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1271a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1272a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1273a6bd005fSEmmanuel Grumbach */ 1274a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1275a6bd005fSEmmanuel Grumbach 1276a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 12772e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1278a6bd005fSEmmanuel Grumbach 1279a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1280a6bd005fSEmmanuel Grumbach 1281a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 12829ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1283a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1284a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1285a6bd005fSEmmanuel Grumbach goto out; 1286a6bd005fSEmmanuel Grumbach } 1287a6bd005fSEmmanuel Grumbach 1288a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1289a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1290a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1291a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 129220aa99bbSAnton Protopopov ret = -EIO; 1293a6bd005fSEmmanuel Grumbach goto out; 1294a6bd005fSEmmanuel Grumbach } 1295a6bd005fSEmmanuel Grumbach 1296a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1297a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1298a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1299a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1300a6bd005fSEmmanuel Grumbach 1301a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1302a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1303a6bd005fSEmmanuel Grumbach 1304a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1305a6bd005fSEmmanuel Grumbach if (ret) { 1306a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1307a6bd005fSEmmanuel Grumbach goto out; 1308a6bd005fSEmmanuel Grumbach } 1309a6bd005fSEmmanuel Grumbach 1310a6bd005fSEmmanuel Grumbach /* 1311a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1312a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1313a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1314a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1315a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1316a6bd005fSEmmanuel Grumbach */ 1317a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1318a6bd005fSEmmanuel Grumbach 1319a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1320a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1321a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1322a6bd005fSEmmanuel Grumbach 1323a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1324286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1325a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1326a6bd005fSEmmanuel Grumbach else 1327a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1328a6bd005fSEmmanuel Grumbach 1329a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13309ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1331a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1332a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1333a6bd005fSEmmanuel Grumbach 1334a6bd005fSEmmanuel Grumbach out: 1335a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1336a6bd005fSEmmanuel Grumbach return ret; 1337a6bd005fSEmmanuel Grumbach } 1338a6bd005fSEmmanuel Grumbach 1339a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1340a6bd005fSEmmanuel Grumbach { 1341a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1342a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1343a6bd005fSEmmanuel Grumbach } 1344a6bd005fSEmmanuel Grumbach 1345326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1346326477e4SJohannes Berg bool was_in_rfkill) 1347326477e4SJohannes Berg { 1348326477e4SJohannes Berg bool hw_rfkill; 1349326477e4SJohannes Berg 1350326477e4SJohannes Berg /* 1351326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1352326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1353326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1354326477e4SJohannes Berg * op_mode. 1355326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1356326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1357326477e4SJohannes Berg * notification without endless recursion. Under very rare 1358326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1359326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1360326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1361326477e4SJohannes Berg */ 1362326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1363326477e4SJohannes Berg if (hw_rfkill) { 1364326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1365326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1366326477e4SJohannes Berg } else { 1367326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1368326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1369326477e4SJohannes Berg } 1370326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1371326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1372326477e4SJohannes Berg } 1373326477e4SJohannes Berg 1374bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1375e705c121SKalle Valo { 1376e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1377326477e4SJohannes Berg bool was_in_rfkill; 1378e705c121SKalle Valo 1379e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1380326477e4SJohannes Berg trans_pcie->opmode_down = true; 1381326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1382bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1383326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1384e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1385e705c121SKalle Valo } 1386e705c121SKalle Valo 1387e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1388e705c121SKalle Valo { 1389e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1390e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1391e705c121SKalle Valo 1392e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1393e705c121SKalle Valo 1394326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1395326477e4SJohannes Berg state ? "disabled" : "enabled"); 139677c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1397286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1398bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 139977c09bc8SSara Sharon else 1400bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1401e705c121SKalle Valo } 140277c09bc8SSara Sharon } 1403e705c121SKalle Valo 1404e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1405e5f3f215SHaim Dreyfuss bool test, bool reset) 1406e705c121SKalle Valo { 1407e705c121SKalle Valo iwl_disable_interrupts(trans); 1408e705c121SKalle Valo 1409e705c121SKalle Valo /* 1410e705c121SKalle Valo * in testing mode, the host stays awake and the 1411e705c121SKalle Valo * hardware won't be reset (not even partially) 1412e705c121SKalle Valo */ 1413e705c121SKalle Valo if (test) 1414e705c121SKalle Valo return; 1415e705c121SKalle Valo 1416e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1417e705c121SKalle Valo 14182e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1419e705c121SKalle Valo 1420e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14216dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14226dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1423e705c121SKalle Valo 142423ae6128SMatti Gottlieb if (reset) { 1425e705c121SKalle Valo /* 1426e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1427e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1428e705c121SKalle Valo * to execute some invalid memory upon resume 1429e705c121SKalle Valo */ 1430e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1431e705c121SKalle Valo } 1432e705c121SKalle Valo 1433e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1434e705c121SKalle Valo } 1435e705c121SKalle Valo 1436e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1437e5f3f215SHaim Dreyfuss bool reset) 1438e5f3f215SHaim Dreyfuss { 1439e5f3f215SHaim Dreyfuss int ret; 1440e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1441e5f3f215SHaim Dreyfuss 1442771db3a1SHaim Dreyfuss if (!reset) 1443e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1444e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1445e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1446e5f3f215SHaim Dreyfuss 1447e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1448e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1449e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1450e5f3f215SHaim Dreyfuss 1451e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1452e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1453e5f3f215SHaim Dreyfuss /* 1454e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1455e5f3f215SHaim Dreyfuss */ 1456e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1457e5f3f215SHaim Dreyfuss 1458e5f3f215SHaim Dreyfuss if (!ret) { 1459e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1460e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1461e5f3f215SHaim Dreyfuss } 1462e5f3f215SHaim Dreyfuss } 1463e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1464e5f3f215SHaim Dreyfuss 1465e5f3f215SHaim Dreyfuss return 0; 1466e5f3f215SHaim Dreyfuss } 1467e5f3f215SHaim Dreyfuss 1468e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1469e705c121SKalle Valo enum iwl_d3_status *status, 147023ae6128SMatti Gottlieb bool test, bool reset) 1471e705c121SKalle Valo { 1472d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1473e705c121SKalle Valo u32 val; 1474e705c121SKalle Valo int ret; 1475e705c121SKalle Valo 1476e705c121SKalle Valo if (test) { 1477e705c121SKalle Valo iwl_enable_interrupts(trans); 1478e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1479e5f3f215SHaim Dreyfuss goto out; 1480e705c121SKalle Valo } 1481e705c121SKalle Valo 1482a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 14836dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1484e705c121SKalle Valo 14857d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1486c96b5eecSJohannes Berg if (ret) 1487e705c121SKalle Valo return ret; 1488e705c121SKalle Valo 1489f98ad635SEmmanuel Grumbach /* 1490f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1491f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1492f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1493f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1494f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1495f98ad635SEmmanuel Grumbach */ 1496f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1497f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1498f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1499f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1500f98ad635SEmmanuel Grumbach 1501e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1502e705c121SKalle Valo 150323ae6128SMatti Gottlieb if (!reset) { 1504e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15056dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1506e705c121SKalle Valo } else { 1507e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1508e705c121SKalle Valo 1509e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1510e705c121SKalle Valo if (ret) { 1511e705c121SKalle Valo IWL_ERR(trans, 1512e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1513e705c121SKalle Valo return ret; 1514e705c121SKalle Valo } 1515e705c121SKalle Valo } 1516e705c121SKalle Valo 151782ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1518ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 151982ea7966SSara Sharon 1520e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1521e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1522e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1523e705c121SKalle Valo else 1524e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1525e705c121SKalle Valo 1526e5f3f215SHaim Dreyfuss out: 1527e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1528e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1529e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1530e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1531e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1532e5f3f215SHaim Dreyfuss 1533e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1534e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1535e5f3f215SHaim Dreyfuss /* 1536e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1537e5f3f215SHaim Dreyfuss */ 1538e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1539e5f3f215SHaim Dreyfuss 1540e5f3f215SHaim Dreyfuss if (!ret) { 1541e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1542e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1543e5f3f215SHaim Dreyfuss } 1544e5f3f215SHaim Dreyfuss } 1545e705c121SKalle Valo return 0; 1546e705c121SKalle Valo } 1547e705c121SKalle Valo 15480c18714aSLuca Coelho static void 15490c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15500c18714aSLuca Coelho struct iwl_trans *trans, 15510c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 15522e5d4a8fSHaim Dreyfuss { 15532e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1554ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 15552e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15560cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 15572e5d4a8fSHaim Dreyfuss 15580c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 155906f4b081SSara Sharon goto enable_msi; 156006f4b081SSara Sharon 15610cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 15620cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 15630cd38f4dSMordechay Goodstein 15640cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 156506f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 15662e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 15672e5d4a8fSHaim Dreyfuss 156806f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 15692e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 157006f4b081SSara Sharon max_irqs); 157106f4b081SSara Sharon if (num_irqs < 0) { 1572496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 157306f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 157406f4b081SSara Sharon num_irqs); 157506f4b081SSara Sharon goto enable_msi; 1576496d83caSHaim Dreyfuss } 157706f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1578496d83caSHaim Dreyfuss 15792e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 158006f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 158106f4b081SSara Sharon num_irqs); 158206f4b081SSara Sharon 1583496d83caSHaim Dreyfuss /* 158406f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 158506f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1586496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1587496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1588496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1589496d83caSHaim Dreyfuss */ 1590ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 159106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1592496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1593496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1594ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 159506f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1596496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1597496d83caSHaim Dreyfuss } else { 159806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1599496d83caSHaim Dreyfuss } 1600ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16012e5d4a8fSHaim Dreyfuss 160206f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1603496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16042e5d4a8fSHaim Dreyfuss return; 16052e5d4a8fSHaim Dreyfuss 160606f4b081SSara Sharon enable_msi: 160706f4b081SSara Sharon ret = pci_enable_msi(pdev); 160806f4b081SSara Sharon if (ret) { 160906f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16102e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16112e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16122e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16132e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16142e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16152e5d4a8fSHaim Dreyfuss } 16162e5d4a8fSHaim Dreyfuss } 16172e5d4a8fSHaim Dreyfuss } 16182e5d4a8fSHaim Dreyfuss 16197c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16207c8d91ebSHaim Dreyfuss { 16217c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16227c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16237c8d91ebSHaim Dreyfuss 16247c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16257c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16267c8d91ebSHaim Dreyfuss offset = 1 + i; 16277c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16287c8d91ebSHaim Dreyfuss /* 16297c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16307c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16317c8d91ebSHaim Dreyfuss */ 16327c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16337c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16347c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16357c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16367c8d91ebSHaim Dreyfuss if (ret) 16377c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16387c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16397c8d91ebSHaim Dreyfuss i); 16407c8d91ebSHaim Dreyfuss } 16417c8d91ebSHaim Dreyfuss } 16427c8d91ebSHaim Dreyfuss 16432e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16442e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16452e5d4a8fSHaim Dreyfuss { 1646496d83caSHaim Dreyfuss int i; 16472e5d4a8fSHaim Dreyfuss 1648496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 16492e5d4a8fSHaim Dreyfuss int ret; 16505a41a86cSSharon Dvir struct msix_entry *msix_entry; 165164fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 165264fa3affSSharon Dvir 165364fa3affSSharon Dvir if (!qname) 165464fa3affSSharon Dvir return -ENOMEM; 16552e5d4a8fSHaim Dreyfuss 16565a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 16575a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 16585a41a86cSSharon Dvir msix_entry->vector, 16592e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1660496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 16612e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 16622e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 16632e5d4a8fSHaim Dreyfuss IRQF_SHARED, 166464fa3affSSharon Dvir qname, 16655a41a86cSSharon Dvir msix_entry); 16662e5d4a8fSHaim Dreyfuss if (ret) { 16672e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16682e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 16695a41a86cSSharon Dvir 16702e5d4a8fSHaim Dreyfuss return ret; 16712e5d4a8fSHaim Dreyfuss } 16722e5d4a8fSHaim Dreyfuss } 16737c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 16742e5d4a8fSHaim Dreyfuss 16752e5d4a8fSHaim Dreyfuss return 0; 16762e5d4a8fSHaim Dreyfuss } 16772e5d4a8fSHaim Dreyfuss 167844f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 167944f61b5cSShahar S Matityahu { 168044f61b5cSShahar S Matityahu u32 hpm, wprot; 168144f61b5cSShahar S Matityahu 1682286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 168344f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 168444f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 168544f61b5cSShahar S Matityahu break; 168644f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 168744f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 168844f61b5cSShahar S Matityahu break; 168944f61b5cSShahar S Matityahu default: 169044f61b5cSShahar S Matityahu return 0; 169144f61b5cSShahar S Matityahu } 169244f61b5cSShahar S Matityahu 169344f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 169444f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 169544f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 169644f61b5cSShahar S Matityahu 169744f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 169844f61b5cSShahar S Matityahu IWL_ERR(trans, 169944f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 170044f61b5cSShahar S Matityahu return -EPERM; 170144f61b5cSShahar S Matityahu } 170244f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 170344f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 170444f61b5cSShahar S Matityahu } 170544f61b5cSShahar S Matityahu 170644f61b5cSShahar S Matityahu return 0; 170744f61b5cSShahar S Matityahu } 170844f61b5cSShahar S Matityahu 17090df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17100df36b90SLuca Coelho { 17110df36b90SLuca Coelho int ret; 17120df36b90SLuca Coelho 17130df36b90SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 17140df36b90SLuca Coelho if (ret < 0) 17150df36b90SLuca Coelho return ret; 17160df36b90SLuca Coelho 17170df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17180df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17190df36b90SLuca Coelho udelay(20); 17200df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17210df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 17220df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 17230df36b90SLuca Coelho udelay(20); 17240df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 17250df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17260df36b90SLuca Coelho 17270df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 17280df36b90SLuca Coelho 17290df36b90SLuca Coelho return 0; 17300df36b90SLuca Coelho } 17310df36b90SLuca Coelho 1732bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1733e705c121SKalle Valo { 1734e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1735e705c121SKalle Valo int err; 1736e705c121SKalle Valo 1737e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1738e705c121SKalle Valo 1739e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1740e705c121SKalle Valo if (err) { 1741e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1742e705c121SKalle Valo return err; 1743e705c121SKalle Valo } 1744e705c121SKalle Valo 174544f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 174644f61b5cSShahar S Matityahu if (err) 174744f61b5cSShahar S Matityahu return err; 17488954e1ebSShahar S Matityahu 1749870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1750e705c121SKalle Valo 17510df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 17527897dfa2SLuca Coelho trans->trans_cfg->integrated) { 17530df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 17540df36b90SLuca Coelho if (err) 17550df36b90SLuca Coelho return err; 17560df36b90SLuca Coelho } 17570df36b90SLuca Coelho 175852b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 175952b6e168SEmmanuel Grumbach if (err) 176052b6e168SEmmanuel Grumbach return err; 1761e705c121SKalle Valo 17622e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 176383730058SHaim Dreyfuss 1764e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1765e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1766e705c121SKalle Valo 1767326477e4SJohannes Berg trans_pcie->opmode_down = false; 1768326477e4SJohannes Berg 1769e705c121SKalle Valo /* Set is_down to false here so that...*/ 1770e705c121SKalle Valo trans_pcie->is_down = false; 1771e705c121SKalle Valo 1772e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17739ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1774e705c121SKalle Valo 1775e705c121SKalle Valo return 0; 1776e705c121SKalle Valo } 1777e705c121SKalle Valo 1778bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1779e705c121SKalle Valo { 1780e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1781e705c121SKalle Valo int ret; 1782e705c121SKalle Valo 1783e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1784bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1785e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1786e705c121SKalle Valo 1787e705c121SKalle Valo return ret; 1788e705c121SKalle Valo } 1789e705c121SKalle Valo 1790e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1791e705c121SKalle Valo { 1792e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1793e705c121SKalle Valo 1794e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1795e705c121SKalle Valo 1796e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1797e705c121SKalle Valo iwl_disable_interrupts(trans); 1798e705c121SKalle Valo 1799e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1800e705c121SKalle Valo 1801e705c121SKalle Valo iwl_disable_interrupts(trans); 1802e705c121SKalle Valo 1803e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1804e705c121SKalle Valo 1805e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1806e705c121SKalle Valo 18072e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1808e705c121SKalle Valo } 1809e705c121SKalle Valo 1810e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1811e705c121SKalle Valo { 1812e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 1815e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1816e705c121SKalle Valo { 1817e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1818e705c121SKalle Valo } 1819e705c121SKalle Valo 1820e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1821e705c121SKalle Valo { 1822e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1823e705c121SKalle Valo } 1824e705c121SKalle Valo 182584fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 182684fb372cSSara Sharon { 18273681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 182884fb372cSSara Sharon return 0x00FFFFFF; 182984fb372cSSara Sharon else 183084fb372cSSara Sharon return 0x000FFFFF; 183184fb372cSSara Sharon } 183284fb372cSSara Sharon 1833e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1834e705c121SKalle Valo { 183584fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 183684fb372cSSara Sharon 1837e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 183884fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1839e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1840e705c121SKalle Valo } 1841e705c121SKalle Valo 1842e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1843e705c121SKalle Valo u32 val) 1844e705c121SKalle Valo { 184584fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 184684fb372cSSara Sharon 1847e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 184884fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1849e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1850e705c121SKalle Valo } 1851e705c121SKalle Valo 1852e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1853e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1854e705c121SKalle Valo { 1855e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1856e705c121SKalle Valo 18574f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 18584f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 18594f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 186022852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 186122852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 186222852fadSMordechay Goodstein 1863e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1864e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1865e705c121SKalle Valo else 1866e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1867e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1868e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1869e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1870e705c121SKalle Valo 18716c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18726c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18736c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 187480084e35SJohannes Berg trans_pcie->rx_buf_bytes = 187580084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1876cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1877cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1878cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1879e705c121SKalle Valo 18808e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1881e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1882e705c121SKalle Valo 188339bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 188439bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 188539bdb17eSSharon Dvir 1886e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1887e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1888e705c121SKalle Valo * As this function may be called again in some corner cases don't 1889e705c121SKalle Valo * do anything if NAPI was already initialized. 1890e705c121SKalle Valo */ 1891bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1892e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1893*906d4eb8SJohannes Berg 1894*906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1895e705c121SKalle Valo } 1896e705c121SKalle Valo 1897e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1898e705c121SKalle Valo { 1899e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19006eb5e529SEmmanuel Grumbach int i; 1901e705c121SKalle Valo 19022e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1903e705c121SKalle Valo 1904286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 19050cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 190613a3a390SSara Sharon else 1907e705c121SKalle Valo iwl_pcie_tx_free(trans); 1908e705c121SKalle Valo iwl_pcie_rx_free(trans); 1909e705c121SKalle Valo 191010a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 191110a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 191210a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 191310a54d81SLuca Coelho } 191410a54d81SLuca Coelho 19152e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19167c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19177c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19187c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19197c8d91ebSHaim Dreyfuss NULL); 19207c8d91ebSHaim Dreyfuss } 19212e5d4a8fSHaim Dreyfuss 19222e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19232e5d4a8fSHaim Dreyfuss } else { 1924e705c121SKalle Valo iwl_pcie_free_ict(trans); 19252e5d4a8fSHaim Dreyfuss } 1926e705c121SKalle Valo 1927e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1928e705c121SKalle Valo 192969725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 193069725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 193169725928SLuca Coelho trans_pcie->pnvm_dram.block, 193269725928SLuca Coelho trans_pcie->pnvm_dram.physical); 193369725928SLuca Coelho 1934a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1935e705c121SKalle Valo iwl_trans_free(trans); 1936e705c121SKalle Valo } 1937e705c121SKalle Valo 1938e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1939e705c121SKalle Valo { 1940e705c121SKalle Valo if (state) 1941e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1942e705c121SKalle Valo else 1943e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1944e705c121SKalle Valo } 1945e705c121SKalle Valo 194649564a80SLuca Coelho struct iwl_trans_pcie_removal { 194749564a80SLuca Coelho struct pci_dev *pdev; 194849564a80SLuca Coelho struct work_struct work; 194949564a80SLuca Coelho }; 195049564a80SLuca Coelho 195149564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 195249564a80SLuca Coelho { 195349564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 195449564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 195549564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 1956aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 195749564a80SLuca Coelho 195849564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 195949564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 196049564a80SLuca Coelho pci_lock_rescan_remove(); 196149564a80SLuca Coelho pci_dev_put(pdev); 196249564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 196349564a80SLuca Coelho pci_unlock_rescan_remove(); 196449564a80SLuca Coelho 196549564a80SLuca Coelho kfree(removal); 196649564a80SLuca Coelho module_put(THIS_MODULE); 196749564a80SLuca Coelho } 196849564a80SLuca Coelho 196923ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1970e705c121SKalle Valo unsigned long *flags) 1971e705c121SKalle Valo { 1972e705c121SKalle Valo int ret; 1973e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1974e705c121SKalle Valo 1975e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1976e705c121SKalle Valo 1977e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1978e705c121SKalle Valo goto out; 1979e705c121SKalle Valo 1980e705c121SKalle Valo /* this bit wakes up the NIC */ 1981e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 19826dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1983286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1984e705c121SKalle Valo udelay(2); 1985e705c121SKalle Valo 1986e705c121SKalle Valo /* 1987e705c121SKalle Valo * These bits say the device is running, and should keep running for 1988e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1989e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1990fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1991fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1992e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1993e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1994e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1995e705c121SKalle Valo * to keep device from sleeping. 1996e705c121SKalle Valo * 1997e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1998e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1999fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2000fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2001fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2002e705c121SKalle Valo * 2003e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2004e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2005e705c121SKalle Valo */ 2006e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 20076dece0e9SLuca Coelho CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 20086dece0e9SLuca Coelho (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2009e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2010e705c121SKalle Valo if (unlikely(ret < 0)) { 201149564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 201249564a80SLuca Coelho 2013e705c121SKalle Valo WARN_ONCE(1, 2014e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 201549564a80SLuca Coelho cntrl); 201649564a80SLuca Coelho 201749564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 201849564a80SLuca Coelho 201949564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 202049564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 202149564a80SLuca Coelho 2022f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 202349564a80SLuca Coelho goto err; 202449564a80SLuca Coelho 202549564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 202649564a80SLuca Coelho 202749564a80SLuca Coelho /* 202849564a80SLuca Coelho * get a module reference to avoid doing this 202949564a80SLuca Coelho * while unloading anyway and to avoid 203049564a80SLuca Coelho * scheduling a work with code that's being 203149564a80SLuca Coelho * removed. 203249564a80SLuca Coelho */ 203349564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 203449564a80SLuca Coelho IWL_ERR(trans, 203549564a80SLuca Coelho "Module is being unloaded - abort\n"); 203649564a80SLuca Coelho goto err; 203749564a80SLuca Coelho } 203849564a80SLuca Coelho 203949564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 204049564a80SLuca Coelho if (!removal) { 204149564a80SLuca Coelho module_put(THIS_MODULE); 204249564a80SLuca Coelho goto err; 204349564a80SLuca Coelho } 204449564a80SLuca Coelho /* 204549564a80SLuca Coelho * we don't need to clear this flag, because 204649564a80SLuca Coelho * the trans will be freed and reallocated. 204749564a80SLuca Coelho */ 2048f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 204949564a80SLuca Coelho 205049564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 205149564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 205249564a80SLuca Coelho pci_dev_get(removal->pdev); 205349564a80SLuca Coelho schedule_work(&removal->work); 205449564a80SLuca Coelho } else { 205549564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 205649564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 205749564a80SLuca Coelho } 205849564a80SLuca Coelho 205949564a80SLuca Coelho err: 2060e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2061e705c121SKalle Valo return false; 2062e705c121SKalle Valo } 2063e705c121SKalle Valo 2064e705c121SKalle Valo out: 2065e705c121SKalle Valo /* 2066e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2067e705c121SKalle Valo * track nic_access anyway. 2068e705c121SKalle Valo */ 2069e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2070e705c121SKalle Valo return true; 2071e705c121SKalle Valo } 2072e705c121SKalle Valo 2073e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2074e705c121SKalle Valo unsigned long *flags) 2075e705c121SKalle Valo { 2076e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2077e705c121SKalle Valo 2078e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2079e705c121SKalle Valo 2080e705c121SKalle Valo /* 2081e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2082e705c121SKalle Valo * track nic_access anyway. 2083e705c121SKalle Valo */ 2084e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2085e705c121SKalle Valo 2086e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2087e705c121SKalle Valo goto out; 2088e705c121SKalle Valo 2089e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 20906dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2091e705c121SKalle Valo /* 2092e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2093e705c121SKalle Valo * any previous writes, but we need the write that clears the 2094e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2095e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2096e705c121SKalle Valo */ 2097e705c121SKalle Valo out: 2098e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2099e705c121SKalle Valo } 2100e705c121SKalle Valo 2101e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2102e705c121SKalle Valo void *buf, int dwords) 2103e705c121SKalle Valo { 2104e705c121SKalle Valo unsigned long flags; 210504516706SJohannes Berg int offs = 0; 2106e705c121SKalle Valo u32 *vals = buf; 2107e705c121SKalle Valo 210804516706SJohannes Berg while (offs < dwords) { 210904516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 211004516706SJohannes Berg ktime_t timeout = ktime_add_us(ktime_get(), 500 * USEC_PER_MSEC); 211104516706SJohannes Berg 211223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 211304516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 211404516706SJohannes Berg addr + 4 * offs); 211504516706SJohannes Berg 211604516706SJohannes Berg while (offs < dwords) { 211704516706SJohannes Berg vals[offs] = iwl_read32(trans, 211804516706SJohannes Berg HBUS_TARG_MEM_RDAT); 211904516706SJohannes Berg offs++; 212004516706SJohannes Berg 212104516706SJohannes Berg /* calling ktime_get is expensive so 212204516706SJohannes Berg * do it once in 128 reads 212304516706SJohannes Berg */ 212404516706SJohannes Berg if (offs % 128 == 0 && ktime_after(ktime_get(), 212504516706SJohannes Berg timeout)) 212604516706SJohannes Berg break; 212704516706SJohannes Berg } 2128e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2129e705c121SKalle Valo } else { 213004516706SJohannes Berg return -EBUSY; 2131e705c121SKalle Valo } 213204516706SJohannes Berg } 213304516706SJohannes Berg 213404516706SJohannes Berg return 0; 2135e705c121SKalle Valo } 2136e705c121SKalle Valo 2137e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2138e705c121SKalle Valo const void *buf, int dwords) 2139e705c121SKalle Valo { 2140e705c121SKalle Valo unsigned long flags; 2141e705c121SKalle Valo int offs, ret = 0; 2142e705c121SKalle Valo const u32 *vals = buf; 2143e705c121SKalle Valo 214423ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2145e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2146e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2147e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2148e705c121SKalle Valo vals ? vals[offs] : 0); 2149e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2150e705c121SKalle Valo } else { 2151e705c121SKalle Valo ret = -EBUSY; 2152e705c121SKalle Valo } 2153e705c121SKalle Valo return ret; 2154e705c121SKalle Valo } 2155e705c121SKalle Valo 21567f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 21577f1fe1d4SLuca Coelho u32 *val) 21587f1fe1d4SLuca Coelho { 21597f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 21607f1fe1d4SLuca Coelho ofs, val); 21617f1fe1d4SLuca Coelho } 21627f1fe1d4SLuca Coelho 21630cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21640cd58eaaSEmmanuel Grumbach { 21650cd58eaaSEmmanuel Grumbach int i; 21660cd58eaaSEmmanuel Grumbach 2167286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 21684f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 21690cd58eaaSEmmanuel Grumbach 21704f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 21710cd58eaaSEmmanuel Grumbach continue; 21720cd58eaaSEmmanuel Grumbach 21730cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 21740cd58eaaSEmmanuel Grumbach 21750cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 21760cd58eaaSEmmanuel Grumbach txq->block--; 21770cd58eaaSEmmanuel Grumbach if (!txq->block) { 21780cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2179bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 21800cd58eaaSEmmanuel Grumbach } 21810cd58eaaSEmmanuel Grumbach } else if (block) { 21820cd58eaaSEmmanuel Grumbach txq->block++; 21830cd58eaaSEmmanuel Grumbach } 21840cd58eaaSEmmanuel Grumbach 21850cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 21860cd58eaaSEmmanuel Grumbach } 21870cd58eaaSEmmanuel Grumbach } 21880cd58eaaSEmmanuel Grumbach 2189e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2190e705c121SKalle Valo 219192536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 219292536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 219392536c96SSara Sharon { 219492536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 219592536c96SSara Sharon 219692536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 219792536c96SSara Sharon return -EINVAL; 219892536c96SSara Sharon 219992536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 220092536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 220192536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 220292536c96SSara Sharon data->fr_bd_wid = 0; 220392536c96SSara Sharon 220492536c96SSara Sharon return 0; 220592536c96SSara Sharon } 220692536c96SSara Sharon 2207d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2208e705c121SKalle Valo { 2209e705c121SKalle Valo struct iwl_txq *txq; 2210e705c121SKalle Valo unsigned long now = jiffies; 22112ae48edcSSara Sharon bool overflow_tx; 2212e705c121SKalle Valo u8 wr_ptr; 2213e705c121SKalle Valo 22142b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2215f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2216f60c9e59SEmmanuel Grumbach return -ENODEV; 22172b3fae66SMatt Chen 22184f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2219d6d517b7SSara Sharon return -EINVAL; 2220e705c121SKalle Valo 2221d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 22224f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 22232ae48edcSSara Sharon 22242ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22252ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22262ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22272ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 22282ae48edcSSara Sharon 22296aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2230e705c121SKalle Valo 22312ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 22322ae48edcSSara Sharon overflow_tx) && 2233e705c121SKalle Valo !time_after(jiffies, 2234e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22356aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2236e705c121SKalle Valo 22372ae48edcSSara Sharon /* 22382ae48edcSSara Sharon * If write pointer moved during the wait, warn only 22392ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 22402ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 22412ae48edcSSara Sharon */ 22422ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2243e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2244e705c121SKalle Valo wr_ptr, write_ptr)) 2245e705c121SKalle Valo return -ETIMEDOUT; 22462ae48edcSSara Sharon wr_ptr = write_ptr; 22472ae48edcSSara Sharon 2248192185d6SJohannes Berg usleep_range(1000, 2000); 22492ae48edcSSara Sharon 22502ae48edcSSara Sharon spin_lock_bh(&txq->lock); 22512ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 22522ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 22532ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2254e705c121SKalle Valo } 2255e705c121SKalle Valo 2256bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2257e705c121SKalle Valo IWL_ERR(trans, 2258d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 22590cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2260d6d517b7SSara Sharon return -ETIMEDOUT; 2261e705c121SKalle Valo } 2262e705c121SKalle Valo 2263d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2264d6d517b7SSara Sharon 2265d6d517b7SSara Sharon return 0; 2266d6d517b7SSara Sharon } 2267d6d517b7SSara Sharon 2268d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2269d6d517b7SSara Sharon { 2270d6d517b7SSara Sharon int cnt; 2271d6d517b7SSara Sharon int ret = 0; 2272d6d517b7SSara Sharon 2273d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 227479b6c8feSLuca Coelho for (cnt = 0; 2275286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 227679b6c8feSLuca Coelho cnt++) { 2277d6d517b7SSara Sharon 22784f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2279d6d517b7SSara Sharon continue; 22804f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2281d6d517b7SSara Sharon continue; 2282d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2283d6d517b7SSara Sharon continue; 2284d6d517b7SSara Sharon 2285d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 228638398efbSSara Sharon if (ret) 2287d6d517b7SSara Sharon break; 2288d6d517b7SSara Sharon } 2289e705c121SKalle Valo 2290e705c121SKalle Valo return ret; 2291e705c121SKalle Valo } 2292e705c121SKalle Valo 2293e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2294e705c121SKalle Valo u32 mask, u32 value) 2295e705c121SKalle Valo { 2296e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2297e705c121SKalle Valo unsigned long flags; 2298e705c121SKalle Valo 2299e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2300e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2301e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2302e705c121SKalle Valo } 2303e705c121SKalle Valo 2304e705c121SKalle Valo static const char *get_csr_string(int cmd) 2305e705c121SKalle Valo { 2306e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2307e705c121SKalle Valo switch (cmd) { 2308e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2309e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2310e705c121SKalle Valo IWL_CMD(CSR_INT); 2311e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2312e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2313e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2314e705c121SKalle Valo IWL_CMD(CSR_RESET); 2315e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2316e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2317e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2318e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2319e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2320e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2321e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2322e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2323e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2324e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2325e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2326e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2327e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2328e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2329e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2330e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2331e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2332e705c121SKalle Valo default: 2333e705c121SKalle Valo return "UNKNOWN"; 2334e705c121SKalle Valo } 2335e705c121SKalle Valo #undef IWL_CMD 2336e705c121SKalle Valo } 2337e705c121SKalle Valo 2338e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2339e705c121SKalle Valo { 2340e705c121SKalle Valo int i; 2341e705c121SKalle Valo static const u32 csr_tbl[] = { 2342e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2343e705c121SKalle Valo CSR_INT_COALESCING, 2344e705c121SKalle Valo CSR_INT, 2345e705c121SKalle Valo CSR_INT_MASK, 2346e705c121SKalle Valo CSR_FH_INT_STATUS, 2347e705c121SKalle Valo CSR_GPIO_IN, 2348e705c121SKalle Valo CSR_RESET, 2349e705c121SKalle Valo CSR_GP_CNTRL, 2350e705c121SKalle Valo CSR_HW_REV, 2351e705c121SKalle Valo CSR_EEPROM_REG, 2352e705c121SKalle Valo CSR_EEPROM_GP, 2353e705c121SKalle Valo CSR_OTP_GP_REG, 2354e705c121SKalle Valo CSR_GIO_REG, 2355e705c121SKalle Valo CSR_GP_UCODE_REG, 2356e705c121SKalle Valo CSR_GP_DRIVER_REG, 2357e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2358e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2359e705c121SKalle Valo CSR_LED_REG, 2360e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2361e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2362e705c121SKalle Valo CSR_ANA_PLL_CFG, 2363e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2364e705c121SKalle Valo CSR_HW_REV_WA_REG, 2365e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2366e705c121SKalle Valo }; 2367e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2368e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2369e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2370e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2371e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2372e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2373e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2374e705c121SKalle Valo } 2375e705c121SKalle Valo } 2376e705c121SKalle Valo 2377e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2378e705c121SKalle Valo /* create and remove of files */ 2379e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2380cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2381cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2382e705c121SKalle Valo } while (0) 2383e705c121SKalle Valo 2384e705c121SKalle Valo /* file operation */ 2385e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2386e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2387e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2388e705c121SKalle Valo .open = simple_open, \ 2389e705c121SKalle Valo .llseek = generic_file_llseek, \ 2390e705c121SKalle Valo }; 2391e705c121SKalle Valo 2392e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2393e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2394e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2395e705c121SKalle Valo .open = simple_open, \ 2396e705c121SKalle Valo .llseek = generic_file_llseek, \ 2397e705c121SKalle Valo }; 2398e705c121SKalle Valo 2399e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2400e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2401e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2402e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2403e705c121SKalle Valo .open = simple_open, \ 2404e705c121SKalle Valo .llseek = generic_file_llseek, \ 2405e705c121SKalle Valo }; 2406e705c121SKalle Valo 2407df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2408df67a1beSJohannes Berg struct iwl_trans *trans; 2409df67a1beSJohannes Berg }; 2410df67a1beSJohannes Berg 2411df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2412df67a1beSJohannes Berg loff_t pos; 2413df67a1beSJohannes Berg }; 2414df67a1beSJohannes Berg 2415df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2416e705c121SKalle Valo { 2417df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2418df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2419df67a1beSJohannes Berg 2420df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2421df67a1beSJohannes Berg return NULL; 2422df67a1beSJohannes Berg 2423df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2424df67a1beSJohannes Berg if (!state) 2425df67a1beSJohannes Berg return NULL; 2426df67a1beSJohannes Berg state->pos = *pos; 2427df67a1beSJohannes Berg return state; 2428df67a1beSJohannes Berg } 2429df67a1beSJohannes Berg 2430df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2431df67a1beSJohannes Berg void *v, loff_t *pos) 2432df67a1beSJohannes Berg { 2433df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2434df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2435df67a1beSJohannes Berg 2436df67a1beSJohannes Berg *pos = ++state->pos; 2437df67a1beSJohannes Berg 2438df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2439df67a1beSJohannes Berg return NULL; 2440df67a1beSJohannes Berg 2441df67a1beSJohannes Berg return state; 2442df67a1beSJohannes Berg } 2443df67a1beSJohannes Berg 2444df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2445df67a1beSJohannes Berg { 2446df67a1beSJohannes Berg kfree(v); 2447df67a1beSJohannes Berg } 2448df67a1beSJohannes Berg 2449df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2450df67a1beSJohannes Berg { 2451df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2452df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2453df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 24544f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2455e705c121SKalle Valo 2456df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2457df67a1beSJohannes Berg (unsigned int)state->pos, 24584f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 24594f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2460df67a1beSJohannes Berg if (txq) 2461df67a1beSJohannes Berg seq_printf(seq, 246295a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2463df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 246495a9e44fSJohannes Berg txq->need_update, txq->frozen, 246595a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2466df67a1beSJohannes Berg else 2467df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2468e705c121SKalle Valo 24694f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2470df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2471df67a1beSJohannes Berg seq_puts(seq, "\n"); 2472e705c121SKalle Valo 2473df67a1beSJohannes Berg return 0; 2474df67a1beSJohannes Berg } 2475df67a1beSJohannes Berg 2476df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2477df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2478df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2479df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2480df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2481df67a1beSJohannes Berg }; 2482df67a1beSJohannes Berg 2483df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2484df67a1beSJohannes Berg { 2485df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2486df67a1beSJohannes Berg 2487df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2488df67a1beSJohannes Berg sizeof(*priv)); 2489df67a1beSJohannes Berg 2490df67a1beSJohannes Berg if (!priv) 2491e705c121SKalle Valo return -ENOMEM; 2492e705c121SKalle Valo 2493df67a1beSJohannes Berg priv->trans = inode->i_private; 2494df67a1beSJohannes Berg return 0; 2495e705c121SKalle Valo } 2496e705c121SKalle Valo 2497e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2498e705c121SKalle Valo char __user *user_buf, 2499e705c121SKalle Valo size_t count, loff_t *ppos) 2500e705c121SKalle Valo { 2501e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2502e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 250378485054SSara Sharon char *buf; 250478485054SSara Sharon int pos = 0, i, ret; 2505eb3dc36eSColin Ian King size_t bufsz; 2506e705c121SKalle Valo 250778485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 250878485054SSara Sharon 250978485054SSara Sharon if (!trans_pcie->rxq) 251078485054SSara Sharon return -EAGAIN; 251178485054SSara Sharon 251278485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 251378485054SSara Sharon if (!buf) 251478485054SSara Sharon return -ENOMEM; 251578485054SSara Sharon 251678485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 251778485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 251878485054SSara Sharon 251978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 252078485054SSara Sharon i); 252178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2522e705c121SKalle Valo rxq->read); 252378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2524e705c121SKalle Valo rxq->write); 252578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2526e705c121SKalle Valo rxq->write_actual); 252778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2528e705c121SKalle Valo rxq->need_update); 252978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2530e705c121SKalle Valo rxq->free_count); 2531e705c121SKalle Valo if (rxq->rb_stts) { 25320307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25330307c839SGolan Ben Ami rxq)); 253478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 253578485054SSara Sharon "\tclosed_rb_num: %u\n", 25360307c839SGolan Ben Ami r & 0x0FFF); 2537e705c121SKalle Valo } else { 2538e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 253978485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2540e705c121SKalle Valo } 254178485054SSara Sharon } 254278485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 254378485054SSara Sharon kfree(buf); 254478485054SSara Sharon 254578485054SSara Sharon return ret; 2546e705c121SKalle Valo } 2547e705c121SKalle Valo 2548e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2549e705c121SKalle Valo char __user *user_buf, 2550e705c121SKalle Valo size_t count, loff_t *ppos) 2551e705c121SKalle Valo { 2552e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2553e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2554e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2555e705c121SKalle Valo 2556e705c121SKalle Valo int pos = 0; 2557e705c121SKalle Valo char *buf; 2558e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2559e705c121SKalle Valo ssize_t ret; 2560e705c121SKalle Valo 2561e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2562e705c121SKalle Valo if (!buf) 2563e705c121SKalle Valo return -ENOMEM; 2564e705c121SKalle Valo 2565e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2566e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2567e705c121SKalle Valo 2568e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2569e705c121SKalle Valo isr_stats->hw); 2570e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2571e705c121SKalle Valo isr_stats->sw); 2572e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2573e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2574e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2575e705c121SKalle Valo isr_stats->err_code); 2576e705c121SKalle Valo } 2577e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2578e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2579e705c121SKalle Valo isr_stats->sch); 2580e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2581e705c121SKalle Valo isr_stats->alive); 2582e705c121SKalle Valo #endif 2583e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2584e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2585e705c121SKalle Valo 2586e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2587e705c121SKalle Valo isr_stats->ctkill); 2588e705c121SKalle Valo 2589e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2590e705c121SKalle Valo isr_stats->wakeup); 2591e705c121SKalle Valo 2592e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2593e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2594e705c121SKalle Valo 2595e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2596e705c121SKalle Valo isr_stats->tx); 2597e705c121SKalle Valo 2598e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2599e705c121SKalle Valo isr_stats->unhandled); 2600e705c121SKalle Valo 2601e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2602e705c121SKalle Valo kfree(buf); 2603e705c121SKalle Valo return ret; 2604e705c121SKalle Valo } 2605e705c121SKalle Valo 2606e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2607e705c121SKalle Valo const char __user *user_buf, 2608e705c121SKalle Valo size_t count, loff_t *ppos) 2609e705c121SKalle Valo { 2610e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2611e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2612e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2613e705c121SKalle Valo u32 reset_flag; 2614078f1131SJohannes Berg int ret; 2615e705c121SKalle Valo 2616078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2617078f1131SJohannes Berg if (ret) 2618078f1131SJohannes Berg return ret; 2619e705c121SKalle Valo if (reset_flag == 0) 2620e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2621e705c121SKalle Valo 2622e705c121SKalle Valo return count; 2623e705c121SKalle Valo } 2624e705c121SKalle Valo 2625e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2626e705c121SKalle Valo const char __user *user_buf, 2627e705c121SKalle Valo size_t count, loff_t *ppos) 2628e705c121SKalle Valo { 2629e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2630e705c121SKalle Valo 2631e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2632e705c121SKalle Valo 2633e705c121SKalle Valo return count; 2634e705c121SKalle Valo } 2635e705c121SKalle Valo 2636e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2637e705c121SKalle Valo char __user *user_buf, 2638e705c121SKalle Valo size_t count, loff_t *ppos) 2639e705c121SKalle Valo { 2640e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2641e705c121SKalle Valo char *buf = NULL; 2642e705c121SKalle Valo ssize_t ret; 2643e705c121SKalle Valo 2644e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2645e705c121SKalle Valo if (ret < 0) 2646e705c121SKalle Valo return ret; 2647e705c121SKalle Valo if (!buf) 2648e705c121SKalle Valo return -EINVAL; 2649e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2650e705c121SKalle Valo kfree(buf); 2651e705c121SKalle Valo return ret; 2652e705c121SKalle Valo } 2653e705c121SKalle Valo 2654fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2655fa4de7f7SJohannes Berg char __user *user_buf, 2656fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2657fa4de7f7SJohannes Berg { 2658fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2659fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2660fa4de7f7SJohannes Berg char buf[100]; 2661fa4de7f7SJohannes Berg int pos; 2662fa4de7f7SJohannes Berg 2663fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2664fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2665fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2666fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2667fa4de7f7SJohannes Berg 2668fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2669fa4de7f7SJohannes Berg } 2670fa4de7f7SJohannes Berg 2671fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2672fa4de7f7SJohannes Berg const char __user *user_buf, 2673fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2674fa4de7f7SJohannes Berg { 2675fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2676fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2677c5bf4fa1SJohannes Berg bool new_value; 2678fa4de7f7SJohannes Berg int ret; 2679fa4de7f7SJohannes Berg 2680c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2681fa4de7f7SJohannes Berg if (ret) 2682fa4de7f7SJohannes Berg return ret; 2683c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2684fa4de7f7SJohannes Berg return count; 2685fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2686c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2687c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2688fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2689fa4de7f7SJohannes Berg 2690fa4de7f7SJohannes Berg return count; 2691fa4de7f7SJohannes Berg } 2692fa4de7f7SJohannes Berg 2693f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2694f7805b33SLior Cohen struct file *file) 2695f7805b33SLior Cohen { 2696f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2697f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2698f7805b33SLior Cohen 269991c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 270091c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2701f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2702f7805b33SLior Cohen return -ENOENT; 2703f7805b33SLior Cohen } 2704f7805b33SLior Cohen 2705f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2706f7805b33SLior Cohen return -EBUSY; 2707f7805b33SLior Cohen 2708f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2709f7805b33SLior Cohen return simple_open(inode, file); 2710f7805b33SLior Cohen } 2711f7805b33SLior Cohen 2712f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2713f7805b33SLior Cohen struct file *file) 2714f7805b33SLior Cohen { 2715f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2716f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2717f7805b33SLior Cohen 2718f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2719f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2720f7805b33SLior Cohen return 0; 2721f7805b33SLior Cohen } 2722f7805b33SLior Cohen 2723f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2724f7805b33SLior Cohen void *buf, ssize_t *size, 2725f7805b33SLior Cohen ssize_t *bytes_copied) 2726f7805b33SLior Cohen { 2727f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2728f7805b33SLior Cohen 2729f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2730f7805b33SLior Cohen if (*size > buf_size_left) 2731f7805b33SLior Cohen *size = buf_size_left; 2732f7805b33SLior Cohen 2733f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2734f7805b33SLior Cohen *bytes_copied += *size; 2735f7805b33SLior Cohen 2736f7805b33SLior Cohen if (buf_size_left == *size) 2737f7805b33SLior Cohen return true; 2738f7805b33SLior Cohen return false; 2739f7805b33SLior Cohen } 2740f7805b33SLior Cohen 2741f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2742f7805b33SLior Cohen char __user *user_buf, 2743f7805b33SLior Cohen size_t count, loff_t *ppos) 2744f7805b33SLior Cohen { 2745f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2746f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 274769f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2748f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2749f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2750f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2751f7805b33SLior Cohen bool b_full; 2752f7805b33SLior Cohen 275391c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2754f7805b33SLior Cohen write_ptr_addr = 275591c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 275691c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2757f7805b33SLior Cohen } else { 2758f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2759f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2760f7805b33SLior Cohen } 2761f7805b33SLior Cohen 276291c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2763f7805b33SLior Cohen return 0; 2764f7805b33SLior Cohen 2765f7805b33SLior Cohen mutex_lock(&data->mutex); 2766f7805b33SLior Cohen if (data->state == 2767f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2768f7805b33SLior Cohen mutex_unlock(&data->mutex); 2769f7805b33SLior Cohen return 0; 2770f7805b33SLior Cohen } 2771f7805b33SLior Cohen 2772f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2773f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2774f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2775f7805b33SLior Cohen 2776f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2777f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2778f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2779f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2780f7805b33SLior Cohen curr_buf, &size, 2781f7805b33SLior Cohen &bytes_copied); 2782f7805b33SLior Cohen data->prev_wr_ptr += size; 2783f7805b33SLior Cohen 2784f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2785f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 278669f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2787f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2788f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2789f7805b33SLior Cohen curr_buf, &size, 2790f7805b33SLior Cohen &bytes_copied); 2791f7805b33SLior Cohen data->prev_wr_ptr += size; 2792f7805b33SLior Cohen 2793f7805b33SLior Cohen if (!b_full) { 2794f7805b33SLior Cohen size = write_ptr; 2795f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2796f7805b33SLior Cohen cpu_addr, &size, 2797f7805b33SLior Cohen &bytes_copied); 2798f7805b33SLior Cohen data->prev_wr_ptr = size; 2799f7805b33SLior Cohen data->prev_wrap_cnt++; 2800f7805b33SLior Cohen } 2801f7805b33SLior Cohen } else { 2802f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2803f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2804f7805b33SLior Cohen IWL_WARN(trans, 2805f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2806f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2807f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2808f7805b33SLior Cohen IWL_WARN(trans, 2809f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2810f7805b33SLior Cohen 2811f7805b33SLior Cohen size = write_ptr; 2812f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2813f7805b33SLior Cohen cpu_addr, &size, 2814f7805b33SLior Cohen &bytes_copied); 2815f7805b33SLior Cohen data->prev_wr_ptr = size; 2816f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2817f7805b33SLior Cohen } 2818f7805b33SLior Cohen 2819f7805b33SLior Cohen mutex_unlock(&data->mutex); 2820f7805b33SLior Cohen 2821f7805b33SLior Cohen return bytes_copied; 2822f7805b33SLior Cohen } 2823f7805b33SLior Cohen 2824e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2825e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2826e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2827e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2828fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2829df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2830df67a1beSJohannes Berg .owner = THIS_MODULE, 2831df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2832df67a1beSJohannes Berg .read = seq_read, 2833df67a1beSJohannes Berg .llseek = seq_lseek, 2834df67a1beSJohannes Berg .release = seq_release_private, 2835df67a1beSJohannes Berg }; 2836e705c121SKalle Valo 2837f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2838f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2839f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2840f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2841f7805b33SLior Cohen }; 2842f7805b33SLior Cohen 2843f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2844cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2845e705c121SKalle Valo { 2846f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2847f8a1edb7SJohannes Berg 28482ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 28492ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 28502ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 28512ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 28522ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 28532ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2854f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2855e705c121SKalle Valo } 2856f7805b33SLior Cohen 2857f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2858f7805b33SLior Cohen { 2859f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2860f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2861f7805b33SLior Cohen 2862f7805b33SLior Cohen mutex_lock(&data->mutex); 2863f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2864f7805b33SLior Cohen mutex_unlock(&data->mutex); 2865f7805b33SLior Cohen } 2866e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2867e705c121SKalle Valo 28686983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2869e705c121SKalle Valo { 2870e705c121SKalle Valo u32 cmdlen = 0; 2871e705c121SKalle Valo int i; 2872e705c121SKalle Valo 2873885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 28740179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 2875e705c121SKalle Valo 2876e705c121SKalle Valo return cmdlen; 2877e705c121SKalle Valo } 2878e705c121SKalle Valo 2879e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2880e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2881e705c121SKalle Valo int allocated_rb_nums) 2882e705c121SKalle Valo { 2883e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 288480084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 288578485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 288678485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2887e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2888e705c121SKalle Valo 2889e705c121SKalle Valo spin_lock(&rxq->lock); 2890e705c121SKalle Valo 28910307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2892e705c121SKalle Valo 2893e705c121SKalle Valo for (i = rxq->read, j = 0; 2894e705c121SKalle Valo i != r && j < allocated_rb_nums; 2895e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2896e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2897e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2898e705c121SKalle Valo 2899e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2900e705c121SKalle Valo DMA_FROM_DEVICE); 2901e705c121SKalle Valo 2902e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2903e705c121SKalle Valo 2904e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2905e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2906e705c121SKalle Valo rb = (void *)(*data)->data; 2907e705c121SKalle Valo rb->index = cpu_to_le32(i); 2908e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2909e705c121SKalle Valo /* remap the page for the free benefit */ 2910cfdc20efSJohannes Berg rxb->page_dma = dma_map_page(trans->dev, rxb->page, 2911cfdc20efSJohannes Berg rxb->offset, max_len, 2912e705c121SKalle Valo DMA_FROM_DEVICE); 2913e705c121SKalle Valo 2914e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2915e705c121SKalle Valo } 2916e705c121SKalle Valo 2917e705c121SKalle Valo spin_unlock(&rxq->lock); 2918e705c121SKalle Valo 2919e705c121SKalle Valo return rb_len; 2920e705c121SKalle Valo } 2921e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2922e705c121SKalle Valo 2923e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2924e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2925e705c121SKalle Valo { 2926e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2927e705c121SKalle Valo __le32 *val; 2928e705c121SKalle Valo int i; 2929e705c121SKalle Valo 2930e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2931e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2932e705c121SKalle Valo val = (void *)(*data)->data; 2933e705c121SKalle Valo 2934e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2935e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2936e705c121SKalle Valo 2937e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2938e705c121SKalle Valo 2939e705c121SKalle Valo return csr_len; 2940e705c121SKalle Valo } 2941e705c121SKalle Valo 2942e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2943e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2944e705c121SKalle Valo { 2945e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2946e705c121SKalle Valo unsigned long flags; 2947e705c121SKalle Valo __le32 *val; 2948e705c121SKalle Valo int i; 2949e705c121SKalle Valo 295023ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2951e705c121SKalle Valo return 0; 2952e705c121SKalle Valo 2953e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2954e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2955e705c121SKalle Valo val = (void *)(*data)->data; 2956e705c121SKalle Valo 2957286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 2958723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2959723b45e2SLiad Kaufman i += sizeof(u32)) 2960e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2961723b45e2SLiad Kaufman else 2962ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 2963ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 2964723b45e2SLiad Kaufman i += sizeof(u32)) 2965723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2966723b45e2SLiad Kaufman i)); 2967e705c121SKalle Valo 2968e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2969e705c121SKalle Valo 2970e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2971e705c121SKalle Valo 2972e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2973e705c121SKalle Valo } 2974e705c121SKalle Valo 2975e705c121SKalle Valo static u32 2976e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2977e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2978e705c121SKalle Valo u32 monitor_len) 2979e705c121SKalle Valo { 2980e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2981e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2982e705c121SKalle Valo unsigned long flags; 2983e705c121SKalle Valo u32 i; 2984e705c121SKalle Valo 298523ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2986e705c121SKalle Valo return 0; 2987e705c121SKalle Valo 2988ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2989e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 2990ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 299114ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 2992ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2993e705c121SKalle Valo 2994e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2995e705c121SKalle Valo 2996e705c121SKalle Valo return monitor_len; 2997e705c121SKalle Valo } 2998e705c121SKalle Valo 29997a14c23dSSara Sharon static void 30007a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30017a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30027a14c23dSSara Sharon { 3003c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30047a14c23dSSara Sharon 3005286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3006c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3007c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3008c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3009c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 301091c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 301191c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 301291c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 301391c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30147a14c23dSSara Sharon } else { 30157a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30167a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 30177a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 30187a14c23dSSara Sharon } 3019c88580e1SShahar S Matityahu 3020c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 30217a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 30227a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 30237a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 30247a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3025286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3026c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3027c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3028c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3029cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3030cc598782SRotem Saado write_ptr_val >>= 2; 3031c88580e1SShahar S Matityahu } 3032c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 30337a14c23dSSara Sharon } 30347a14c23dSSara Sharon 3035e705c121SKalle Valo static u32 3036e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3037e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3038e705c121SKalle Valo u32 monitor_len) 3039e705c121SKalle Valo { 304069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3041e705c121SKalle Valo u32 len = 0; 3042e705c121SKalle Valo 304391c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 304469f0e505SShahar S Matityahu (fw_mon->size && 3045286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3046286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3047e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3048e705c121SKalle Valo 3049e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3050e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 30517a14c23dSSara Sharon 30527a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3053e705c121SKalle Valo 3054e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 305569f0e505SShahar S Matityahu if (fw_mon->size) { 305669f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 305769f0e505SShahar S Matityahu monitor_len = fw_mon->size; 305891c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 30597a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3060e705c121SKalle Valo /* 3061e705c121SKalle Valo * Update pointers to reflect actual values after 3062e705c121SKalle Valo * shifting 3063e705c121SKalle Valo */ 306491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3065fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3066fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 306791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3068fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3069fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3070fd527eb5SGolan Ben Ami } else { 3071e705c121SKalle Valo base = iwl_read_prph(trans, base) << 307291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3073fd527eb5SGolan Ben Ami } 3074fd527eb5SGolan Ben Ami 3075e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3076e705c121SKalle Valo monitor_len / sizeof(u32)); 307791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3078e705c121SKalle Valo monitor_len = 3079e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3080e705c121SKalle Valo fw_mon_data, 3081e705c121SKalle Valo monitor_len); 3082e705c121SKalle Valo } else { 3083e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3084e705c121SKalle Valo monitor_len = 0; 3085e705c121SKalle Valo } 3086e705c121SKalle Valo 3087e705c121SKalle Valo len += monitor_len; 3088e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3089e705c121SKalle Valo } 3090e705c121SKalle Valo 3091e705c121SKalle Valo return len; 3092e705c121SKalle Valo } 3093e705c121SKalle Valo 309493079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3095e705c121SKalle Valo { 309669f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3097da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3098da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 309969f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 310069f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 310191c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3102da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3103e705c121SKalle Valo 310491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 310591c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3106fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3107fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 310891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3109fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3110fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3111fd527eb5SGolan Ben Ami 3112fd527eb5SGolan Ben Ami monitor_len = 3113fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 311491c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3115fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3116fd527eb5SGolan Ben Ami } else { 311791c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 311891c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3119e705c121SKalle Valo 3120e705c121SKalle Valo base = iwl_read_prph(trans, base) << 312191c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3122e705c121SKalle Valo end = iwl_read_prph(trans, end) << 312391c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3124e705c121SKalle Valo 3125e705c121SKalle Valo /* Make "end" point to the actual end */ 3126286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3127fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 312891c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 312991c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3130e705c121SKalle Valo monitor_len = end - base; 3131fd527eb5SGolan Ben Ami } 3132da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3133da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3134e705c121SKalle Valo monitor_len; 3135da752717SShahar S Matityahu return monitor_len; 3136e705c121SKalle Valo } 3137da752717SShahar S Matityahu return 0; 3138da752717SShahar S Matityahu } 3139da752717SShahar S Matityahu 3140da752717SShahar S Matityahu static struct iwl_trans_dump_data 3141da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 314279f033f6SSara Sharon u32 dump_mask) 3143da752717SShahar S Matityahu { 3144da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3145da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 31464f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3147da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3148da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3149fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3150da752717SShahar S Matityahu int i, ptr; 3151da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3152286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 315379f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 315479f033f6SSara Sharon 315579f033f6SSara Sharon if (!dump_mask) 315679f033f6SSara Sharon return NULL; 3157da752717SShahar S Matityahu 3158da752717SShahar S Matityahu /* transport dump header */ 3159da752717SShahar S Matityahu len = sizeof(*dump_data); 3160da752717SShahar S Matityahu 3161da752717SShahar S Matityahu /* host commands */ 3162e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3163da752717SShahar S Matityahu len += sizeof(*data) + 31648672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 31658672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3166da752717SShahar S Matityahu 3167da752717SShahar S Matityahu /* FW monitor */ 3168fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3169da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3170e705c121SKalle Valo 3171e705c121SKalle Valo /* CSR registers */ 317279f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3173e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3174e705c121SKalle Valo 3175e705c121SKalle Valo /* FH registers */ 317679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3177286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3178723b45e2SLiad Kaufman len += sizeof(*data) + 3179ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3180ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3181723b45e2SLiad Kaufman else 3182723b45e2SLiad Kaufman len += sizeof(*data) + 3183520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3184520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3185520f03eaSShahar S Matityahu } 3186e705c121SKalle Valo 3187e705c121SKalle Valo if (dump_rbs) { 318878485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 318978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3190e705c121SKalle Valo /* RBs */ 31910307c839SGolan Ben Ami num_rbs = 31920307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3193e705c121SKalle Valo & 0x0FFF; 319478485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3195e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3196e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3197e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3198e705c121SKalle Valo } 3199e705c121SKalle Valo 32005538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3201286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3202505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32035538409bSLiad Kaufman len += sizeof(*data) + 32045538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3205505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32065538409bSLiad Kaufman 3207e705c121SKalle Valo dump_data = vzalloc(len); 3208e705c121SKalle Valo if (!dump_data) 3209e705c121SKalle Valo return NULL; 3210e705c121SKalle Valo 3211e705c121SKalle Valo len = 0; 3212e705c121SKalle Valo data = (void *)dump_data->data; 3213520f03eaSShahar S Matityahu 3214e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3215885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3216520f03eaSShahar S Matityahu 3217e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3218e705c121SKalle Valo txcmd = (void *)data->data; 3219e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3220bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3221bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 32220cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 322308326a97SJohannes Berg u8 tfdidx; 3224e705c121SKalle Valo u32 caplen, cmdlen; 3225e705c121SKalle Valo 322608326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 322708326a97SJohannes Berg tfdidx = idx; 322808326a97SJohannes Berg else 322908326a97SJohannes Berg tfdidx = ptr; 323008326a97SJohannes Berg 3231520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 323208326a97SJohannes Berg (u8 *)cmdq->tfds + 323308326a97SJohannes Berg tfd_size * tfdidx); 3234e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3235e705c121SKalle Valo 3236e705c121SKalle Valo if (cmdlen) { 3237e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3238e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3239e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3240520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3241520f03eaSShahar S Matityahu caplen); 3242e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3243e705c121SKalle Valo } 3244e705c121SKalle Valo 32450cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3246e705c121SKalle Valo } 3247e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3248e705c121SKalle Valo 3249e705c121SKalle Valo data->len = cpu_to_le32(len); 3250e705c121SKalle Valo len += sizeof(*data); 3251e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3252520f03eaSShahar S Matityahu } 3253e705c121SKalle Valo 325479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3255e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 325679f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3257e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3258e705c121SKalle Valo if (dump_rbs) 3259e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3260e705c121SKalle Valo 32615538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3262286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 326379b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3264505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 32655538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3266505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 32675538409bSLiad Kaufman 32685538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 32695538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 32705538409bSLiad Kaufman paging = (void *)data->data; 32715538409bSLiad Kaufman paging->index = cpu_to_le32(i); 32725538409bSLiad Kaufman memcpy(paging->data, 3273505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 32745538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 32755538409bSLiad Kaufman 32765538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 32775538409bSLiad Kaufman } 32785538409bSLiad Kaufman } 327979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3280e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3281e705c121SKalle Valo 3282e705c121SKalle Valo dump_data->len = len; 3283e705c121SKalle Valo 3284e705c121SKalle Valo return dump_data; 3285e705c121SKalle Valo } 3286e705c121SKalle Valo 32874cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 32884cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 32894cbb8e50SLuciano Coelho { 32904cbb8e50SLuciano Coelho return 0; 32914cbb8e50SLuciano Coelho } 32924cbb8e50SLuciano Coelho 32934cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 32944cbb8e50SLuciano Coelho { 32954cbb8e50SLuciano Coelho } 32964cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 32974cbb8e50SLuciano Coelho 3298623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3299623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3300623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3301623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3302623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3303623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3304623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3305623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3306623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 33077f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3308623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3309623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3310870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3311623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3312623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3313623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3314623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3315623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3316d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 3317d1967ce6SShahar S Matityahu .sync_nmi = iwl_trans_pcie_sync_nmi 3318623e7766SSara Sharon 3319623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3320623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3321623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3322623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3323623e7766SSara Sharon #else 3324623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3325623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3326623e7766SSara Sharon 3327e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3328623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3329623e7766SSara Sharon IWL_TRANS_PM_OPS 3330e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3331e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3332e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3333e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3334e705c121SKalle Valo 3335e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3336e705c121SKalle Valo 3337e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3338a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3339e705c121SKalle Valo 3340e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3341e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3342e705c121SKalle Valo 334342db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 334442db09c1SLiad Kaufman 3345d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3346d6d517b7SSara Sharon 3347a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 33480cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3349f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3350f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3351f7805b33SLior Cohen #endif 3352623e7766SSara Sharon }; 3353e705c121SKalle Valo 3354623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3355623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3356623e7766SSara Sharon IWL_TRANS_PM_OPS 3357623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3358eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3359eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 336077c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3361e705c121SKalle Valo 3362ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3363e705c121SKalle Valo 33640cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3365a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3366623e7766SSara Sharon 3367a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3368ba7136f3SAlex Malamud 33690cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 33700cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3371d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 337292536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 33736654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3374f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3375f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3376f7805b33SLior Cohen #endif 3377e705c121SKalle Valo }; 3378e705c121SKalle Valo 3379e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3380e705c121SKalle Valo const struct pci_device_id *ent, 33817e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3382e705c121SKalle Valo { 3383e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3384e705c121SKalle Valo struct iwl_trans *trans; 3385fda1bd0dSMordechay Goodstein int ret, addr_size; 3386a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3387a89c72ffSJohannes Berg 3388fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3389a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3390e705c121SKalle Valo 33915a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 33925a41a86cSSharon Dvir if (ret) 33935a41a86cSSharon Dvir return ERR_PTR(ret); 33945a41a86cSSharon Dvir 3395a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3396fda1bd0dSMordechay Goodstein cfg_trans); 3397e705c121SKalle Valo if (!trans) 3398e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3399e705c121SKalle Valo 3400e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3401e705c121SKalle Valo 3402e705c121SKalle Valo trans_pcie->trans = trans; 3403326477e4SJohannes Berg trans_pcie->opmode_down = true; 3404e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3405e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3406cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3407e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3408e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3409*906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 34108188a18eSJohannes Berg 34118188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 34128188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 34138188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 34148188a18eSJohannes Berg ret = -ENOMEM; 34158188a18eSJohannes Berg goto out_free_trans; 34168188a18eSJohannes Berg } 34178188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 34188188a18eSJohannes Berg 3419c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3420e705c121SKalle Valo 34217e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3422e705c121SKalle Valo /* 3423e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3424e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3425e705c121SKalle Valo * lot of power. 3426e705c121SKalle Valo */ 3427e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3428e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3429e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3430e705c121SKalle Valo } 3431e705c121SKalle Valo 34329416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 34339416560eSGolan Ben Ami 3434e705c121SKalle Valo pci_set_master(pdev); 3435e705c121SKalle Valo 3436885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 343796a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3438e705c121SKalle Valo if (!ret) 343996a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 344096a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3441e705c121SKalle Valo if (ret) { 3442e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3443e705c121SKalle Valo if (!ret) 3444e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3445e705c121SKalle Valo DMA_BIT_MASK(32)); 3446e705c121SKalle Valo /* both attempts failed: */ 3447e705c121SKalle Valo if (ret) { 3448e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 34495a41a86cSSharon Dvir goto out_no_pci; 3450e705c121SKalle Valo } 3451e705c121SKalle Valo } 3452e705c121SKalle Valo 34535a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3454e705c121SKalle Valo if (ret) { 34555a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 34565a41a86cSSharon Dvir goto out_no_pci; 3457e705c121SKalle Valo } 3458e705c121SKalle Valo 34595a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3460e705c121SKalle Valo if (!trans_pcie->hw_base) { 34615a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3462e705c121SKalle Valo ret = -ENODEV; 34635a41a86cSSharon Dvir goto out_no_pci; 3464e705c121SKalle Valo } 3465e705c121SKalle Valo 3466e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3467e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3468e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3469e705c121SKalle Valo 3470e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3471e705c121SKalle Valo iwl_disable_interrupts(trans); 3472e705c121SKalle Valo 3473e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 34749a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 34759a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 34769a098a89SRajat Jain ret = -EIO; 34779a098a89SRajat Jain goto out_no_pci; 34789a098a89SRajat Jain } 34799a098a89SRajat Jain 3480e705c121SKalle Valo /* 3481e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3482e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3483e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3484e705c121SKalle Valo * in the old format. 3485e705c121SKalle Valo */ 34864adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3487e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3488e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3489e705c121SKalle Valo 349099be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 349199be6166SLuca Coelho 34927e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3493e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3494e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3495e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3496e705c121SKalle Valo 3497e705c121SKalle Valo /* Initialize the wait queue for commands */ 3498e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3499e705c121SKalle Valo 3500e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3501e5f3f215SHaim Dreyfuss 3502c239feecSJohannes Berg 35032e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 35042388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 35052388bd7bSDan Carpenter if (ret) 35065a41a86cSSharon Dvir goto out_no_pci; 35072e5d4a8fSHaim Dreyfuss } else { 3508e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3509e705c121SKalle Valo if (ret) 35105a41a86cSSharon Dvir goto out_no_pci; 3511e705c121SKalle Valo 35125a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 35135a41a86cSSharon Dvir iwl_pcie_isr, 3514e705c121SKalle Valo iwl_pcie_irq_handler, 3515e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3516e705c121SKalle Valo if (ret) { 3517e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3518e705c121SKalle Valo goto out_free_ict; 3519e705c121SKalle Valo } 35202e5d4a8fSHaim Dreyfuss } 3521e705c121SKalle Valo 3522f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3523f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3524f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3525f7805b33SLior Cohen #endif 3526f7805b33SLior Cohen 3527a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3528a9248de4SShahar S Matityahu 3529e705c121SKalle Valo return trans; 3530e705c121SKalle Valo 3531e705c121SKalle Valo out_free_ict: 3532e705c121SKalle Valo iwl_pcie_free_ict(trans); 3533e705c121SKalle Valo out_no_pci: 35348188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 35358188a18eSJohannes Berg out_free_trans: 3536e705c121SKalle Valo iwl_trans_free(trans); 3537e705c121SKalle Valo return ERR_PTR(ret); 3538e705c121SKalle Valo } 3539b8a7547dSShahar S Matityahu 3540d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3541b8a7547dSShahar S Matityahu { 35421c6bca6dSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3543b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3544e4eee943SShahar S Matityahu bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 35451c6bca6dSShahar S Matityahu u32 inta_addr, sw_err_bit; 35461c6bca6dSShahar S Matityahu 35471c6bca6dSShahar S Matityahu if (trans_pcie->msix_enabled) { 35481c6bca6dSShahar S Matityahu inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 35491c6bca6dSShahar S Matityahu sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 35501c6bca6dSShahar S Matityahu } else { 35511c6bca6dSShahar S Matityahu inta_addr = CSR_INT; 35521c6bca6dSShahar S Matityahu sw_err_bit = CSR_INT_BIT_SW_ERR; 35531c6bca6dSShahar S Matityahu } 3554b8a7547dSShahar S Matityahu 3555e4eee943SShahar S Matityahu /* if the interrupts were already disabled, there is no point in 3556e4eee943SShahar S Matityahu * calling iwl_disable_interrupts 3557e4eee943SShahar S Matityahu */ 3558e4eee943SShahar S Matityahu if (interrupts_enabled) 3559b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3560e4eee943SShahar S Matityahu 3561b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3562b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 35631c6bca6dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, inta_addr); 3564b8a7547dSShahar S Matityahu 3565b8a7547dSShahar S Matityahu /* Error detected by uCode */ 35661c6bca6dSShahar S Matityahu if (inta_hw & sw_err_bit) { 3567b8a7547dSShahar S Matityahu /* Clear causes register */ 35681c6bca6dSShahar S Matityahu iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3569b8a7547dSShahar S Matityahu break; 3570b8a7547dSShahar S Matityahu } 3571b8a7547dSShahar S Matityahu 3572b8a7547dSShahar S Matityahu mdelay(1); 3573b8a7547dSShahar S Matityahu } 3574e4eee943SShahar S Matityahu 3575e4eee943SShahar S Matityahu /* enable interrupts only if there were already enabled before this 3576e4eee943SShahar S Matityahu * function to avoid a case were the driver enable interrupts before 3577e4eee943SShahar S Matityahu * proper configurations were made 3578e4eee943SShahar S Matityahu */ 3579e4eee943SShahar S Matityahu if (interrupts_enabled) 3580b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3581e4eee943SShahar S Matityahu 3582b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3583b8a7547dSShahar S Matityahu } 3584