1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34a8cbb46fSGolan Ben Ami * Copyright(c) 2018 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/pci-aspm.h> 66e705c121SKalle Valo #include <linux/interrupt.h> 67e705c121SKalle Valo #include <linux/debugfs.h> 68e705c121SKalle Valo #include <linux/sched.h> 69e705c121SKalle Valo #include <linux/bitops.h> 70e705c121SKalle Valo #include <linux/gfp.h> 71e705c121SKalle Valo #include <linux/vmalloc.h> 72b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 7349564a80SLuca Coelho #include <linux/module.h> 74e705c121SKalle Valo 75e705c121SKalle Valo #include "iwl-drv.h" 76e705c121SKalle Valo #include "iwl-trans.h" 77e705c121SKalle Valo #include "iwl-csr.h" 78e705c121SKalle Valo #include "iwl-prph.h" 79e705c121SKalle Valo #include "iwl-scd.h" 80e705c121SKalle Valo #include "iwl-agn-hw.h" 81d962f9b1SJohannes Berg #include "fw/error-dump.h" 82520f03eaSShahar S Matityahu #include "fw/dbg.h" 83e705c121SKalle Valo #include "internal.h" 84e705c121SKalle Valo #include "iwl-fh.h" 85e705c121SKalle Valo 86e705c121SKalle Valo /* extended range in FW SRAM */ 87e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 89e705c121SKalle Valo 904290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 91a6d24fadSRajat Jain { 92a6d24fadSRajat Jain #define PCI_DUMP_SIZE 64 93a6d24fadSRajat Jain #define PREFIX_LEN 32 94a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 95a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 96a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 97a6d24fadSRajat Jain char *prefix; 98a6d24fadSRajat Jain 99a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 100a6d24fadSRajat Jain return; 101a6d24fadSRajat Jain 102a6d24fadSRajat Jain /* Should be a multiple of 4 */ 103a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 104a6d24fadSRajat Jain /* Alloc a max size buffer */ 105a6d24fadSRajat Jain if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 106a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 107a6d24fadSRajat Jain else 108a6d24fadSRajat Jain alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 109a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 110a6d24fadSRajat Jain if (!buf) 111a6d24fadSRajat Jain return; 112a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 113a6d24fadSRajat Jain 114a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 115a6d24fadSRajat Jain 116a6d24fadSRajat Jain /* Print wifi device registers */ 117a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 118a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 119a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 120a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 121a6d24fadSRajat Jain goto err_read; 122a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 123a6d24fadSRajat Jain 124a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 125a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 126a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 127a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 128a6d24fadSRajat Jain 129a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 130a6d24fadSRajat Jain if (pos) { 131a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 132a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 133a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 134a6d24fadSRajat Jain goto err_read; 135a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 136a6d24fadSRajat Jain 32, 4, buf, i, 0); 137a6d24fadSRajat Jain } 138a6d24fadSRajat Jain 139a6d24fadSRajat Jain /* Print parent device registers next */ 140a6d24fadSRajat Jain if (!pdev->bus->self) 141a6d24fadSRajat Jain goto out; 142a6d24fadSRajat Jain 143a6d24fadSRajat Jain pdev = pdev->bus->self; 144a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 145a6d24fadSRajat Jain 146a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 147a6d24fadSRajat Jain pci_name(pdev)); 148a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 149a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 150a6d24fadSRajat Jain goto err_read; 151a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 152a6d24fadSRajat Jain 153a6d24fadSRajat Jain /* Print root port AER registers */ 154a6d24fadSRajat Jain pos = 0; 155a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 156a6d24fadSRajat Jain if (pdev) 157a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 158a6d24fadSRajat Jain if (pos) { 159a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 160a6d24fadSRajat Jain pci_name(pdev)); 161a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 162a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 163a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 164a6d24fadSRajat Jain goto err_read; 165a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 166a6d24fadSRajat Jain 4, buf, i, 0); 167a6d24fadSRajat Jain } 168f3402d6dSSara Sharon goto out; 169a6d24fadSRajat Jain 170a6d24fadSRajat Jain err_read: 171a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 172a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 173a6d24fadSRajat Jain out: 174a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 175a6d24fadSRajat Jain kfree(buf); 176a6d24fadSRajat Jain } 177a6d24fadSRajat Jain 178870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 179870c2a11SGolan Ben Ami { 180870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 181a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 182a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_sw_reset)); 183870c2a11SGolan Ben Ami usleep_range(5000, 6000); 184870c2a11SGolan Ben Ami } 185870c2a11SGolan Ben Ami 186e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 187e705c121SKalle Valo { 18888964b2eSSara Sharon int i; 189e705c121SKalle Valo 19088964b2eSSara Sharon for (i = 0; i < trans->num_blocks; i++) { 19188964b2eSSara Sharon dma_free_coherent(trans->dev, trans->fw_mon[i].size, 19288964b2eSSara Sharon trans->fw_mon[i].block, 19388964b2eSSara Sharon trans->fw_mon[i].physical); 19488964b2eSSara Sharon trans->fw_mon[i].block = NULL; 19588964b2eSSara Sharon trans->fw_mon[i].physical = 0; 19688964b2eSSara Sharon trans->fw_mon[i].size = 0; 19788964b2eSSara Sharon trans->num_blocks--; 19888964b2eSSara Sharon } 199e705c121SKalle Valo } 200e705c121SKalle Valo 20188964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20288964b2eSSara Sharon u8 max_power, u8 min_power) 203e705c121SKalle Valo { 204c5f97542SShahar S Matityahu void *cpu_addr = NULL; 20588964b2eSSara Sharon dma_addr_t phys = 0; 206e705c121SKalle Valo u32 size = 0; 207e705c121SKalle Valo u8 power; 208e705c121SKalle Valo 20988964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 210e705c121SKalle Valo size = BIT(power); 211c5f97542SShahar S Matityahu cpu_addr = dma_alloc_coherent(trans->dev, size, &phys, 212c5f97542SShahar S Matityahu GFP_KERNEL | __GFP_NOWARN | 213c5f97542SShahar S Matityahu __GFP_ZERO | __GFP_COMP); 214c5f97542SShahar S Matityahu if (!cpu_addr) 215e705c121SKalle Valo continue; 216e705c121SKalle Valo 217e705c121SKalle Valo IWL_INFO(trans, 218c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 219c5f97542SShahar S Matityahu size); 220e705c121SKalle Valo break; 221e705c121SKalle Valo } 222e705c121SKalle Valo 223c5f97542SShahar S Matityahu if (WARN_ON_ONCE(!cpu_addr)) 224e705c121SKalle Valo return; 225e705c121SKalle Valo 226e705c121SKalle Valo if (power != max_power) 227e705c121SKalle Valo IWL_ERR(trans, 228e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 229e705c121SKalle Valo (unsigned long)BIT(power - 10), 230e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 231e705c121SKalle Valo 23288964b2eSSara Sharon trans->fw_mon[trans->num_blocks].block = cpu_addr; 23388964b2eSSara Sharon trans->fw_mon[trans->num_blocks].physical = phys; 23488964b2eSSara Sharon trans->fw_mon[trans->num_blocks].size = size; 23588964b2eSSara Sharon trans->num_blocks++; 23688964b2eSSara Sharon } 23788964b2eSSara Sharon 23888964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 23988964b2eSSara Sharon { 24088964b2eSSara Sharon if (!max_power) { 24188964b2eSSara Sharon /* default max_power is maximum */ 24288964b2eSSara Sharon max_power = 26; 24388964b2eSSara Sharon } else { 24488964b2eSSara Sharon max_power += 11; 24588964b2eSSara Sharon } 24688964b2eSSara Sharon 24788964b2eSSara Sharon if (WARN(max_power > 26, 24888964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 24988964b2eSSara Sharon max_power)) 25088964b2eSSara Sharon return; 25188964b2eSSara Sharon 25288964b2eSSara Sharon /* 25388964b2eSSara Sharon * This function allocats the default fw monitor. 25488964b2eSSara Sharon * The optional additional ones will be allocated in runtime 25588964b2eSSara Sharon */ 25688964b2eSSara Sharon if (trans->num_blocks) 25788964b2eSSara Sharon return; 25888964b2eSSara Sharon 25988964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 260e705c121SKalle Valo } 261e705c121SKalle Valo 262e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 263e705c121SKalle Valo { 264e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 265e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 266e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 267e705c121SKalle Valo } 268e705c121SKalle Valo 269e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 270e705c121SKalle Valo { 271e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 272e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 273e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 274e705c121SKalle Valo } 275e705c121SKalle Valo 276e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 277e705c121SKalle Valo { 278e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 279e705c121SKalle Valo return; 280e705c121SKalle Valo 281e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 282e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 283e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 284e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 285e705c121SKalle Valo else 286e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 287e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 288e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 289e705c121SKalle Valo } 290e705c121SKalle Valo 291e705c121SKalle Valo /* PCI registers */ 292e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 293e705c121SKalle Valo 294eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 295e705c121SKalle Valo { 296e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 297e705c121SKalle Valo u16 lctl; 298e705c121SKalle Valo u16 cap; 299e705c121SKalle Valo 300e705c121SKalle Valo /* 301e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 302e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 303e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 304e705c121SKalle Valo * costs negligible amount of power savings. 305e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 306e705c121SKalle Valo * power savings, even without L1. 307e705c121SKalle Valo */ 308e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 309e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 310e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 311e705c121SKalle Valo else 312e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 313e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 314e705c121SKalle Valo 315e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 316e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 317d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 318e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 319e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 320e705c121SKalle Valo } 321e705c121SKalle Valo 322e705c121SKalle Valo /* 323e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 324e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 325e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 326e705c121SKalle Valo */ 327e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 328e705c121SKalle Valo { 32952b6e168SEmmanuel Grumbach int ret; 33052b6e168SEmmanuel Grumbach 331e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 332e705c121SKalle Valo 333e705c121SKalle Valo /* 334e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 335e705c121SKalle Valo * bits already set by default after reset. 336e705c121SKalle Valo */ 337e705c121SKalle Valo 338e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3396e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 340e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 341e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 342e705c121SKalle Valo 343e705c121SKalle Valo /* 344e705c121SKalle Valo * Disable L0s without affecting L1; 345e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 346e705c121SKalle Valo */ 347e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 348e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 349e705c121SKalle Valo 350e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 351e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 352e705c121SKalle Valo 353e705c121SKalle Valo /* 354e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 355e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 356e705c121SKalle Valo */ 357e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 358e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 359e705c121SKalle Valo 360e705c121SKalle Valo iwl_pcie_apm_config(trans); 361e705c121SKalle Valo 362e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 36377d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 36477d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 365e705c121SKalle Valo 366e705c121SKalle Valo /* 367e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 368e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 369e705c121SKalle Valo */ 370a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 371a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 372e705c121SKalle Valo 373e705c121SKalle Valo /* 374e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 375e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 376e705c121SKalle Valo * and accesses to uCode SRAM. 377e705c121SKalle Valo */ 378e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 379a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 380a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 381a8cbb46fSGolan Ben Ami 25000); 382e705c121SKalle Valo if (ret < 0) { 38352b6e168SEmmanuel Grumbach IWL_ERR(trans, "Failed to init the card\n"); 38452b6e168SEmmanuel Grumbach return ret; 385e705c121SKalle Valo } 386e705c121SKalle Valo 387e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 388e705c121SKalle Valo /* 389e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 390e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 391e705c121SKalle Valo * not related to host_interrupt_operation_mode. 392e705c121SKalle Valo * 393e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 394e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 395e705c121SKalle Valo * that we wake up from L1 on time. 396e705c121SKalle Valo * 397e705c121SKalle Valo * This looks weird: read twice the same register, discard the 398e705c121SKalle Valo * value, set a bit, and yet again, read that same register 399e705c121SKalle Valo * just to discard the value. But that's the way the hardware 400e705c121SKalle Valo * seems to like it. 401e705c121SKalle Valo */ 402e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 403e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 404e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 405e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 406e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 407e705c121SKalle Valo } 408e705c121SKalle Valo 409e705c121SKalle Valo /* 410e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 411e705c121SKalle Valo * 412e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 413e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 414e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 415e705c121SKalle Valo */ 416e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 417e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 418e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 419e705c121SKalle Valo udelay(20); 420e705c121SKalle Valo 421e705c121SKalle Valo /* Disable L1-Active */ 422e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 423e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 424e705c121SKalle Valo 425e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 426e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 427e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 428e705c121SKalle Valo } 429e705c121SKalle Valo 430e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 431e705c121SKalle Valo 43252b6e168SEmmanuel Grumbach return 0; 433e705c121SKalle Valo } 434e705c121SKalle Valo 435e705c121SKalle Valo /* 436e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 437e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 438e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 439e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 440e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 441e705c121SKalle Valo */ 442e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 443e705c121SKalle Valo { 444e705c121SKalle Valo int ret; 445e705c121SKalle Valo u32 apmg_gp1_reg; 446e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 447e705c121SKalle Valo u32 dl_cfg_reg; 448e705c121SKalle Valo 449e705c121SKalle Valo /* Force XTAL ON */ 450e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 451e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 452e705c121SKalle Valo 453870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 454e705c121SKalle Valo 455e705c121SKalle Valo /* 456e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 457e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 458e705c121SKalle Valo */ 459a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 460a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 461e705c121SKalle Valo 462e705c121SKalle Valo /* 463e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 464e705c121SKalle Valo * device-internal resources is possible. 465e705c121SKalle Valo */ 466e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 467a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 468a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 469e705c121SKalle Valo 25000); 470e705c121SKalle Valo if (WARN_ON(ret < 0)) { 471e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 472e705c121SKalle Valo /* Release XTAL ON request */ 473e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 474e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 475e705c121SKalle Valo return; 476e705c121SKalle Valo } 477e705c121SKalle Valo 478e705c121SKalle Valo /* 479e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 480e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 481e705c121SKalle Valo */ 482e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 483e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 484e705c121SKalle Valo 485e705c121SKalle Valo /* 486e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 487e705c121SKalle Valo * caused by APMG idle state. 488e705c121SKalle Valo */ 489e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 490e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 491e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 492e705c121SKalle Valo apmg_xtal_cfg_reg | 493e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 494e705c121SKalle Valo 495870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 496e705c121SKalle Valo 497e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 498e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 499e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 500e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 501e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 502e705c121SKalle Valo 503e705c121SKalle Valo /* Clear delay line clock power up */ 504e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 505e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 506e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 507e705c121SKalle Valo 508e705c121SKalle Valo /* 509e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 510e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 511e705c121SKalle Valo */ 512e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 513e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 514e705c121SKalle Valo 515e705c121SKalle Valo /* 516e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 517e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 518e705c121SKalle Valo */ 519e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 520a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 521e705c121SKalle Valo 522e705c121SKalle Valo /* Activates XTAL resources monitor */ 523e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 524e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 525e705c121SKalle Valo 526e705c121SKalle Valo /* Release XTAL ON request */ 527e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 528e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 529e705c121SKalle Valo udelay(10); 530e705c121SKalle Valo 531e705c121SKalle Valo /* Release APMG XTAL */ 532e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 533e705c121SKalle Valo apmg_xtal_cfg_reg & 534e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 535e705c121SKalle Valo } 536e705c121SKalle Valo 537e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 538e705c121SKalle Valo { 539e8c8935eSJohannes Berg int ret; 540e705c121SKalle Valo 541e705c121SKalle Valo /* stop device's busmaster DMA activity */ 542a8cbb46fSGolan Ben Ami iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset, 543a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_stop_master)); 544e705c121SKalle Valo 545a8cbb46fSGolan Ben Ami ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset, 546a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 547a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_master_dis), 100); 548e705c121SKalle Valo if (ret < 0) 549e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 550e705c121SKalle Valo 551e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 552e705c121SKalle Valo } 553e705c121SKalle Valo 554e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 555e705c121SKalle Valo { 556e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 557e705c121SKalle Valo 558e705c121SKalle Valo if (op_mode_leave) { 559e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 560e705c121SKalle Valo iwl_pcie_apm_init(trans); 561e705c121SKalle Valo 562e705c121SKalle Valo /* inform ME that we are leaving */ 563e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 564e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 565e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5666e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 567e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 568e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 569e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 570e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 571e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 572e705c121SKalle Valo mdelay(1); 573e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 574e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 575e705c121SKalle Valo } 576e705c121SKalle Valo mdelay(5); 577e705c121SKalle Valo } 578e705c121SKalle Valo 579e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 580e705c121SKalle Valo 581e705c121SKalle Valo /* Stop device's DMA activity */ 582e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 583e705c121SKalle Valo 584e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 585e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 586e705c121SKalle Valo return; 587e705c121SKalle Valo } 588e705c121SKalle Valo 589870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 590e705c121SKalle Valo 591e705c121SKalle Valo /* 592e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 593e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 594e705c121SKalle Valo */ 595e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 596a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 597e705c121SKalle Valo } 598e705c121SKalle Valo 599e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 600e705c121SKalle Valo { 601e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 60252b6e168SEmmanuel Grumbach int ret; 603e705c121SKalle Valo 604e705c121SKalle Valo /* nic_init */ 605e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 60652b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 607e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 608e705c121SKalle Valo 60952b6e168SEmmanuel Grumbach if (ret) 61052b6e168SEmmanuel Grumbach return ret; 61152b6e168SEmmanuel Grumbach 612e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 613e705c121SKalle Valo 614e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 615e705c121SKalle Valo 616e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 617e705c121SKalle Valo iwl_pcie_rx_init(trans); 618e705c121SKalle Valo 619e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 620e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 621e705c121SKalle Valo return -ENOMEM; 622e705c121SKalle Valo 623e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 624e705c121SKalle Valo /* enable shadow regs in HW */ 625e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 626e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 627e705c121SKalle Valo } 628e705c121SKalle Valo 629e705c121SKalle Valo return 0; 630e705c121SKalle Valo } 631e705c121SKalle Valo 632e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 633e705c121SKalle Valo 634e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 635e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 636e705c121SKalle Valo { 637e705c121SKalle Valo int ret; 638e705c121SKalle Valo 639e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 640e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 641e705c121SKalle Valo 642e705c121SKalle Valo /* See if we got it */ 643e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 644e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 645e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 646e705c121SKalle Valo HW_READY_TIMEOUT); 647e705c121SKalle Valo 648e705c121SKalle Valo if (ret >= 0) 649e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 650e705c121SKalle Valo 651e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 652e705c121SKalle Valo return ret; 653e705c121SKalle Valo } 654e705c121SKalle Valo 655e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 656eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 657e705c121SKalle Valo { 658e705c121SKalle Valo int ret; 659e705c121SKalle Valo int t = 0; 660e705c121SKalle Valo int iter; 661e705c121SKalle Valo 662e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 663e705c121SKalle Valo 664e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 665e705c121SKalle Valo /* If the card is ready, exit 0 */ 666e705c121SKalle Valo if (ret >= 0) 667e705c121SKalle Valo return 0; 668e705c121SKalle Valo 669e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 670e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 671192185d6SJohannes Berg usleep_range(1000, 2000); 672e705c121SKalle Valo 673e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 674e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 675e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 676e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 677e705c121SKalle Valo 678e705c121SKalle Valo do { 679e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 680e705c121SKalle Valo if (ret >= 0) 681e705c121SKalle Valo return 0; 682e705c121SKalle Valo 683e705c121SKalle Valo usleep_range(200, 1000); 684e705c121SKalle Valo t += 200; 685e705c121SKalle Valo } while (t < 150000); 686e705c121SKalle Valo msleep(25); 687e705c121SKalle Valo } 688e705c121SKalle Valo 689e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 690e705c121SKalle Valo 691e705c121SKalle Valo return ret; 692e705c121SKalle Valo } 693e705c121SKalle Valo 694e705c121SKalle Valo /* 695e705c121SKalle Valo * ucode 696e705c121SKalle Valo */ 697564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 698564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 699564cdce7SSara Sharon u32 byte_cnt) 700e705c121SKalle Valo { 701bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 702e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 703e705c121SKalle Valo 704bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 705e705c121SKalle Valo dst_addr); 706e705c121SKalle Valo 707bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 708e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 709e705c121SKalle Valo 710bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 711e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 712e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 713e705c121SKalle Valo 714bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 715bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 716bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 717e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 718e705c121SKalle Valo 719bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 720e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 721e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 722e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 723564cdce7SSara Sharon } 724e705c121SKalle Valo 725564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 726564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 727564cdce7SSara Sharon u32 byte_cnt) 728564cdce7SSara Sharon { 729564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 730564cdce7SSara Sharon unsigned long flags; 731564cdce7SSara Sharon int ret; 732564cdce7SSara Sharon 733564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 734564cdce7SSara Sharon 735564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 736564cdce7SSara Sharon return -EIO; 737564cdce7SSara Sharon 738564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 739564cdce7SSara Sharon byte_cnt); 740bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 741bac842daSEmmanuel Grumbach 742e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 743e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 744e705c121SKalle Valo if (!ret) { 745e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 746fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 747e705c121SKalle Valo return -ETIMEDOUT; 748e705c121SKalle Valo } 749e705c121SKalle Valo 750e705c121SKalle Valo return 0; 751e705c121SKalle Valo } 752e705c121SKalle Valo 753e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 754e705c121SKalle Valo const struct fw_desc *section) 755e705c121SKalle Valo { 756e705c121SKalle Valo u8 *v_addr; 757e705c121SKalle Valo dma_addr_t p_addr; 758e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 759e705c121SKalle Valo int ret = 0; 760e705c121SKalle Valo 761e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 762e705c121SKalle Valo section_num); 763e705c121SKalle Valo 764e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 765e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 766e705c121SKalle Valo if (!v_addr) { 767e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 768e705c121SKalle Valo chunk_sz = PAGE_SIZE; 769e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 770e705c121SKalle Valo &p_addr, GFP_KERNEL); 771e705c121SKalle Valo if (!v_addr) 772e705c121SKalle Valo return -ENOMEM; 773e705c121SKalle Valo } 774e705c121SKalle Valo 775e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 776e705c121SKalle Valo u32 copy_size, dst_addr; 777e705c121SKalle Valo bool extended_addr = false; 778e705c121SKalle Valo 779e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 780e705c121SKalle Valo dst_addr = section->offset + offset; 781e705c121SKalle Valo 782e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 783e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 784e705c121SKalle Valo extended_addr = true; 785e705c121SKalle Valo 786e705c121SKalle Valo if (extended_addr) 787e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 788e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 789e705c121SKalle Valo 790e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 791e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 792e705c121SKalle Valo copy_size); 793e705c121SKalle Valo 794e705c121SKalle Valo if (extended_addr) 795e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 796e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 797e705c121SKalle Valo 798e705c121SKalle Valo if (ret) { 799e705c121SKalle Valo IWL_ERR(trans, 800e705c121SKalle Valo "Could not load the [%d] uCode section\n", 801e705c121SKalle Valo section_num); 802e705c121SKalle Valo break; 803e705c121SKalle Valo } 804e705c121SKalle Valo } 805e705c121SKalle Valo 806e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 807e705c121SKalle Valo return ret; 808e705c121SKalle Valo } 809e705c121SKalle Valo 810e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 811e705c121SKalle Valo const struct fw_img *image, 812e705c121SKalle Valo int cpu, 813e705c121SKalle Valo int *first_ucode_section) 814e705c121SKalle Valo { 815e705c121SKalle Valo int shift_param; 816e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 817e705c121SKalle Valo u32 val, last_read_idx = 0; 818e705c121SKalle Valo 819e705c121SKalle Valo if (cpu == 1) { 820e705c121SKalle Valo shift_param = 0; 821e705c121SKalle Valo *first_ucode_section = 0; 822e705c121SKalle Valo } else { 823e705c121SKalle Valo shift_param = 16; 824e705c121SKalle Valo (*first_ucode_section)++; 825e705c121SKalle Valo } 826e705c121SKalle Valo 827eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 828e705c121SKalle Valo last_read_idx = i; 829e705c121SKalle Valo 830e705c121SKalle Valo /* 831e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 832e705c121SKalle Valo * CPU1 to CPU2. 833e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 834e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 835e705c121SKalle Valo */ 836e705c121SKalle Valo if (!image->sec[i].data || 837e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 838e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 839e705c121SKalle Valo IWL_DEBUG_FW(trans, 840e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 841e705c121SKalle Valo i); 842e705c121SKalle Valo break; 843e705c121SKalle Valo } 844e705c121SKalle Valo 845e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 846e705c121SKalle Valo if (ret) 847e705c121SKalle Valo return ret; 848e705c121SKalle Valo 849d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 850e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 851e705c121SKalle Valo val = val | (sec_num << shift_param); 852e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 853eda50cdeSSara Sharon 854e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 855e705c121SKalle Valo } 856e705c121SKalle Valo 857e705c121SKalle Valo *first_ucode_section = last_read_idx; 858e705c121SKalle Valo 8592aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8602aabdbdcSEmmanuel Grumbach 861d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 862e705c121SKalle Valo if (cpu == 1) 863d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 864d6a2c5c7SSara Sharon 0xFFFF); 865e705c121SKalle Valo else 866d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 867d6a2c5c7SSara Sharon 0xFFFFFFFF); 868d6a2c5c7SSara Sharon } else { 869d6a2c5c7SSara Sharon if (cpu == 1) 870d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 871d6a2c5c7SSara Sharon 0xFFFF); 872d6a2c5c7SSara Sharon else 873d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 874d6a2c5c7SSara Sharon 0xFFFFFFFF); 875d6a2c5c7SSara Sharon } 876e705c121SKalle Valo 877e705c121SKalle Valo return 0; 878e705c121SKalle Valo } 879e705c121SKalle Valo 880e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 881e705c121SKalle Valo const struct fw_img *image, 882e705c121SKalle Valo int cpu, 883e705c121SKalle Valo int *first_ucode_section) 884e705c121SKalle Valo { 885e705c121SKalle Valo int i, ret = 0; 886e705c121SKalle Valo u32 last_read_idx = 0; 887e705c121SKalle Valo 8883ce4a038SKirtika Ruchandani if (cpu == 1) 889e705c121SKalle Valo *first_ucode_section = 0; 8903ce4a038SKirtika Ruchandani else 891e705c121SKalle Valo (*first_ucode_section)++; 892e705c121SKalle Valo 893eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 894e705c121SKalle Valo last_read_idx = i; 895e705c121SKalle Valo 896e705c121SKalle Valo /* 897e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 898e705c121SKalle Valo * CPU1 to CPU2. 899e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 900e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 901e705c121SKalle Valo */ 902e705c121SKalle Valo if (!image->sec[i].data || 903e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 904e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 905e705c121SKalle Valo IWL_DEBUG_FW(trans, 906e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 907e705c121SKalle Valo i); 908e705c121SKalle Valo break; 909e705c121SKalle Valo } 910e705c121SKalle Valo 911e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 912e705c121SKalle Valo if (ret) 913e705c121SKalle Valo return ret; 914e705c121SKalle Valo } 915e705c121SKalle Valo 916e705c121SKalle Valo *first_ucode_section = last_read_idx; 917e705c121SKalle Valo 918e705c121SKalle Valo return 0; 919e705c121SKalle Valo } 920e705c121SKalle Valo 921c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 922e705c121SKalle Valo { 923fd527eb5SGolan Ben Ami const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv; 924e705c121SKalle Valo int i; 925e705c121SKalle Valo 926e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 927e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 928e705c121SKalle Valo 929e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 930e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 931e705c121SKalle Valo else 932e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 933e705c121SKalle Valo 934e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 935e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 936e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 937e705c121SKalle Valo 938e705c121SKalle Valo switch (dest->reg_ops[i].op) { 939e705c121SKalle Valo case CSR_ASSIGN: 940e705c121SKalle Valo iwl_write32(trans, addr, val); 941e705c121SKalle Valo break; 942e705c121SKalle Valo case CSR_SETBIT: 943e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 944e705c121SKalle Valo break; 945e705c121SKalle Valo case CSR_CLEARBIT: 946e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 947e705c121SKalle Valo break; 948e705c121SKalle Valo case PRPH_ASSIGN: 949e705c121SKalle Valo iwl_write_prph(trans, addr, val); 950e705c121SKalle Valo break; 951e705c121SKalle Valo case PRPH_SETBIT: 952e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 953e705c121SKalle Valo break; 954e705c121SKalle Valo case PRPH_CLEARBIT: 955e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 956e705c121SKalle Valo break; 957e705c121SKalle Valo case PRPH_BLOCKBIT: 958e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 959e705c121SKalle Valo IWL_ERR(trans, 960e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 961e705c121SKalle Valo val, addr); 962e705c121SKalle Valo goto monitor; 963e705c121SKalle Valo } 964e705c121SKalle Valo break; 965e705c121SKalle Valo default: 966e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 967e705c121SKalle Valo dest->reg_ops[i].op); 968e705c121SKalle Valo break; 969e705c121SKalle Valo } 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo monitor: 97388964b2eSSara Sharon if (dest->monitor_mode == EXTERNAL_MODE && trans->fw_mon[0].size) { 974e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 97588964b2eSSara Sharon trans->fw_mon[0].physical >> dest->base_shift); 9766e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 977e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 97888964b2eSSara Sharon (trans->fw_mon[0].physical + 97988964b2eSSara Sharon trans->fw_mon[0].size - 256) >> 98062d7476dSEmmanuel Grumbach dest->end_shift); 98162d7476dSEmmanuel Grumbach else 98262d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98388964b2eSSara Sharon (trans->fw_mon[0].physical + 98488964b2eSSara Sharon trans->fw_mon[0].size) >> 98562d7476dSEmmanuel Grumbach dest->end_shift); 986e705c121SKalle Valo } 987e705c121SKalle Valo } 988e705c121SKalle Valo 989e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 990e705c121SKalle Valo const struct fw_img *image) 991e705c121SKalle Valo { 992e705c121SKalle Valo int ret = 0; 993e705c121SKalle Valo int first_ucode_section; 994e705c121SKalle Valo 995e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 996e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 997e705c121SKalle Valo 998e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 999e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1000e705c121SKalle Valo if (ret) 1001e705c121SKalle Valo return ret; 1002e705c121SKalle Valo 1003e705c121SKalle Valo if (image->is_dual_cpus) { 1004e705c121SKalle Valo /* set CPU2 header address */ 1005e705c121SKalle Valo iwl_write_prph(trans, 1006e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1007e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1010e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1011e705c121SKalle Valo &first_ucode_section); 1012e705c121SKalle Valo if (ret) 1013e705c121SKalle Valo return ret; 1014e705c121SKalle Valo } 1015e705c121SKalle Valo 1016e705c121SKalle Valo /* supported for 7000 only for the moment */ 1017e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1018e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1019e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1020e705c121SKalle Valo 102188964b2eSSara Sharon if (trans->fw_mon[0].size) { 1022e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 102388964b2eSSara Sharon trans->fw_mon[0].physical >> 4); 1024e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 102588964b2eSSara Sharon (trans->fw_mon[0].physical + 102688964b2eSSara Sharon trans->fw_mon[0].size) >> 4); 1027e705c121SKalle Valo } 1028e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 1029e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1030e705c121SKalle Valo } 1031e705c121SKalle Valo 10322aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10332aabdbdcSEmmanuel Grumbach 1034e705c121SKalle Valo /* release CPU reset */ 1035e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1036e705c121SKalle Valo 1037e705c121SKalle Valo return 0; 1038e705c121SKalle Valo } 1039e705c121SKalle Valo 1040e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1041e705c121SKalle Valo const struct fw_img *image) 1042e705c121SKalle Valo { 1043e705c121SKalle Valo int ret = 0; 1044e705c121SKalle Valo int first_ucode_section; 1045e705c121SKalle Valo 1046e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1047e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1048e705c121SKalle Valo 1049e705c121SKalle Valo if (trans->dbg_dest_tlv) 1050e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1051e705c121SKalle Valo 105282ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 105382ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 105482ea7966SSara Sharon 105582ea7966SSara Sharon /* 105682ea7966SSara Sharon * Set default value. On resume reading the values that were 105782ea7966SSara Sharon * zeored can provide debug data on the resume flow. 105882ea7966SSara Sharon * This is for debugging only and has no functional impact. 105982ea7966SSara Sharon */ 106082ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 106182ea7966SSara Sharon 1062e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1063e705c121SKalle Valo /* release CPU reset */ 1064e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1065e705c121SKalle Valo 1066e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1067e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1068e705c121SKalle Valo &first_ucode_section); 1069e705c121SKalle Valo if (ret) 1070e705c121SKalle Valo return ret; 1071e705c121SKalle Valo 1072e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1073e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1074e705c121SKalle Valo &first_ucode_section); 1075e705c121SKalle Valo } 1076e705c121SKalle Valo 10779ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1078727c02dfSSara Sharon { 1079326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1080727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1081326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1082326477e4SJohannes Berg bool report; 1083727c02dfSSara Sharon 1084326477e4SJohannes Berg if (hw_rfkill) { 1085326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1086326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1087326477e4SJohannes Berg } else { 1088326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1089326477e4SJohannes Berg if (trans_pcie->opmode_down) 1090326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1091326477e4SJohannes Berg } 1092727c02dfSSara Sharon 1093326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1094326477e4SJohannes Berg 1095326477e4SJohannes Berg if (prev != report) 1096326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1097727c02dfSSara Sharon 1098727c02dfSSara Sharon return hw_rfkill; 1099727c02dfSSara Sharon } 1100727c02dfSSara Sharon 11017ca00409SHaim Dreyfuss struct iwl_causes_list { 11027ca00409SHaim Dreyfuss u32 cause_num; 11037ca00409SHaim Dreyfuss u32 mask_reg; 11047ca00409SHaim Dreyfuss u8 addr; 11057ca00409SHaim Dreyfuss }; 11067ca00409SHaim Dreyfuss 11077ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11087ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11097ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11107ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11117ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11127ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11137ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11147ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11157ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11167ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11177ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11187ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11197ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11207ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11217ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11227ca00409SHaim Dreyfuss }; 11237ca00409SHaim Dreyfuss 11249b58419eSGolan Ben Ami static struct iwl_causes_list causes_list_v2[] = { 11259b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11269b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11279b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11289b58419eSGolan Ben Ami {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11299b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11309b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_IPC, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11319b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2, CSR_MSIX_HW_INT_MASK_AD, 0x15}, 11329b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11339b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11349b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11359b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11369b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11379b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11389b58419eSGolan Ben Ami {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11399b58419eSGolan Ben Ami }; 11409b58419eSGolan Ben Ami 11417ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11427ca00409SHaim Dreyfuss { 11437ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11447ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11459b58419eSGolan Ben Ami int i, arr_size = 11469b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11479b58419eSGolan Ben Ami ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2); 11487ca00409SHaim Dreyfuss 11497ca00409SHaim Dreyfuss /* 11507ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11517ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11527ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11537ca00409SHaim Dreyfuss */ 11549b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11559b58419eSGolan Ben Ami struct iwl_causes_list *causes = 11569b58419eSGolan Ben Ami (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ? 11579b58419eSGolan Ben Ami causes_list : causes_list_v2; 11589b58419eSGolan Ben Ami 11599b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11609b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11619b58419eSGolan Ben Ami causes[i].cause_num); 11627ca00409SHaim Dreyfuss } 11637ca00409SHaim Dreyfuss } 11647ca00409SHaim Dreyfuss 11657ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11667ca00409SHaim Dreyfuss { 11677ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11687ca00409SHaim Dreyfuss u32 offset = 11697ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11707ca00409SHaim Dreyfuss u32 val, idx; 11717ca00409SHaim Dreyfuss 11727ca00409SHaim Dreyfuss /* 11737ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11747ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11757ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11767ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11777ca00409SHaim Dreyfuss */ 11787ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11797ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11807ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11817ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11827ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11837ca00409SHaim Dreyfuss } 11847ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11857ca00409SHaim Dreyfuss 11867ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11877ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11887ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11897ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11907ca00409SHaim Dreyfuss 11917ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11927ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11937ca00409SHaim Dreyfuss } 11947ca00409SHaim Dreyfuss 119577c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11967ca00409SHaim Dreyfuss { 11977ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11987ca00409SHaim Dreyfuss 11997ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1200d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1201d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12027ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, 12037ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 12047ca00409SHaim Dreyfuss return; 12057ca00409SHaim Dreyfuss } 1206d7270d61SHaim Dreyfuss /* 1207d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1208d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1209d7270d61SHaim Dreyfuss * prph. 1210d7270d61SHaim Dreyfuss */ 1211d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 12127ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12137ca00409SHaim Dreyfuss 12147ca00409SHaim Dreyfuss /* 12157ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12167ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12177ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12187ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12197ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12207ca00409SHaim Dreyfuss */ 12217ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12227ca00409SHaim Dreyfuss 12237ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 122483730058SHaim Dreyfuss } 12257ca00409SHaim Dreyfuss 122683730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122783730058SHaim Dreyfuss { 122883730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122983730058SHaim Dreyfuss 123083730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 123183730058SHaim Dreyfuss 123283730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 123383730058SHaim Dreyfuss return; 123483730058SHaim Dreyfuss 123583730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12367ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123783730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12387ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12397ca00409SHaim Dreyfuss } 12407ca00409SHaim Dreyfuss 1241e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1242e705c121SKalle Valo { 1243e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1244e705c121SKalle Valo 1245e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1246e705c121SKalle Valo 1247e705c121SKalle Valo if (trans_pcie->is_down) 1248e705c121SKalle Valo return; 1249e705c121SKalle Valo 1250e705c121SKalle Valo trans_pcie->is_down = true; 1251e705c121SKalle Valo 12520232d2cdSSara Sharon /* Stop dbgc before stopping device */ 12535cfe79c8SSara Sharon _iwl_fw_dbg_stop_recording(trans, NULL); 12540232d2cdSSara Sharon 1255e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1256e705c121SKalle Valo iwl_disable_interrupts(trans); 1257e705c121SKalle Valo 1258e705c121SKalle Valo /* device going down, Stop using ICT table */ 1259e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1260e705c121SKalle Valo 1261e705c121SKalle Valo /* 1262e705c121SKalle Valo * If a HW restart happens during firmware loading, 1263e705c121SKalle Valo * then the firmware loading might call this function 1264e705c121SKalle Valo * and later it might be called again due to the 1265e705c121SKalle Valo * restart. So don't process again if the device is 1266e705c121SKalle Valo * already dead. 1267e705c121SKalle Valo */ 1268e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1269a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1270a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1271e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1272e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1273e705c121SKalle Valo 1274e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1275e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1276e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1277e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1278e705c121SKalle Valo udelay(5); 1279e705c121SKalle Valo } 1280e705c121SKalle Valo } 1281e705c121SKalle Valo 1282e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1283e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1284a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1285e705c121SKalle Valo 1286e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1287e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1288e705c121SKalle Valo 1289870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1290e705c121SKalle Valo 1291e705c121SKalle Valo /* 1292f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1293f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1294f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1295f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1296f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1297f4a1f04aSGolan Ben Ami */ 1298f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1299f4a1f04aSGolan Ben Ami 1300f4a1f04aSGolan Ben Ami /* 1301e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1302e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1303e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1304e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1305e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1306e705c121SKalle Valo */ 1307e705c121SKalle Valo iwl_disable_interrupts(trans); 1308e705c121SKalle Valo 1309e705c121SKalle Valo /* clear all status bits */ 1310e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1311e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1312e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1313e705c121SKalle Valo 1314e705c121SKalle Valo /* 1315e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1316e705c121SKalle Valo * interrupt 1317e705c121SKalle Valo */ 1318e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1319e705c121SKalle Valo 1320a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1321e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1322e705c121SKalle Valo } 1323e705c121SKalle Valo 1324eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13252e5d4a8fSHaim Dreyfuss { 13262e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13272e5d4a8fSHaim Dreyfuss 13282e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13292e5d4a8fSHaim Dreyfuss int i; 13302e5d4a8fSHaim Dreyfuss 1331496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13322e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13332e5d4a8fSHaim Dreyfuss } else { 13342e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13352e5d4a8fSHaim Dreyfuss } 13362e5d4a8fSHaim Dreyfuss } 13372e5d4a8fSHaim Dreyfuss 1338a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1339a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1340a6bd005fSEmmanuel Grumbach { 1341a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1342a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1343a6bd005fSEmmanuel Grumbach int ret; 1344a6bd005fSEmmanuel Grumbach 1345a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1346a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1347a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1348a6bd005fSEmmanuel Grumbach ret = -EIO; 1349a6bd005fSEmmanuel Grumbach goto out; 1350a6bd005fSEmmanuel Grumbach } 1351a6bd005fSEmmanuel Grumbach 1352a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1353a6bd005fSEmmanuel Grumbach 1354a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1355a6bd005fSEmmanuel Grumbach 1356a6bd005fSEmmanuel Grumbach /* 1357a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1358a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1359a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1360a6bd005fSEmmanuel Grumbach */ 1361a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1362a6bd005fSEmmanuel Grumbach 1363a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13642e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1365a6bd005fSEmmanuel Grumbach 1366a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1367a6bd005fSEmmanuel Grumbach 1368a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13699ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1370a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1371a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1372a6bd005fSEmmanuel Grumbach goto out; 1373a6bd005fSEmmanuel Grumbach } 1374a6bd005fSEmmanuel Grumbach 1375a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1376a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1377a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1378a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 137920aa99bbSAnton Protopopov ret = -EIO; 1380a6bd005fSEmmanuel Grumbach goto out; 1381a6bd005fSEmmanuel Grumbach } 1382a6bd005fSEmmanuel Grumbach 1383a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1384a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1385a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1386a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1387a6bd005fSEmmanuel Grumbach 1388a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1389a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1390a6bd005fSEmmanuel Grumbach 1391a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1392a6bd005fSEmmanuel Grumbach if (ret) { 1393a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1394a6bd005fSEmmanuel Grumbach goto out; 1395a6bd005fSEmmanuel Grumbach } 1396a6bd005fSEmmanuel Grumbach 1397a6bd005fSEmmanuel Grumbach /* 1398a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1399a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1400a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1401a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1402a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1403a6bd005fSEmmanuel Grumbach */ 1404a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1405a6bd005fSEmmanuel Grumbach 1406a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1407a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1408a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1409a6bd005fSEmmanuel Grumbach 1410a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 14116e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1412a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1413a6bd005fSEmmanuel Grumbach else 1414a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1415a6bd005fSEmmanuel Grumbach 1416a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14179ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1418a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1419a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1420a6bd005fSEmmanuel Grumbach 1421a6bd005fSEmmanuel Grumbach out: 1422a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1423a6bd005fSEmmanuel Grumbach return ret; 1424a6bd005fSEmmanuel Grumbach } 1425a6bd005fSEmmanuel Grumbach 1426a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1427a6bd005fSEmmanuel Grumbach { 1428a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1429a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1430a6bd005fSEmmanuel Grumbach } 1431a6bd005fSEmmanuel Grumbach 1432326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1433326477e4SJohannes Berg bool was_in_rfkill) 1434326477e4SJohannes Berg { 1435326477e4SJohannes Berg bool hw_rfkill; 1436326477e4SJohannes Berg 1437326477e4SJohannes Berg /* 1438326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1439326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1440326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1441326477e4SJohannes Berg * op_mode. 1442326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1443326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1444326477e4SJohannes Berg * notification without endless recursion. Under very rare 1445326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1446326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1447326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1448326477e4SJohannes Berg */ 1449326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1450326477e4SJohannes Berg if (hw_rfkill) { 1451326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1452326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1453326477e4SJohannes Berg } else { 1454326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1455326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1456326477e4SJohannes Berg } 1457326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1458326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1459326477e4SJohannes Berg } 1460326477e4SJohannes Berg 1461e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1462e705c121SKalle Valo { 1463e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1464326477e4SJohannes Berg bool was_in_rfkill; 1465e705c121SKalle Valo 1466e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1467326477e4SJohannes Berg trans_pcie->opmode_down = true; 1468326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1469e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1470326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1471e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1472e705c121SKalle Valo } 1473e705c121SKalle Valo 1474e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1475e705c121SKalle Valo { 1476e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1477e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1478e705c121SKalle Valo 1479e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1480e705c121SKalle Valo 1481326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1482326477e4SJohannes Berg state ? "disabled" : "enabled"); 148377c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 148477c09bc8SSara Sharon if (trans->cfg->gen2) 148577c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 148677c09bc8SSara Sharon else 1487e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1488e705c121SKalle Valo } 148977c09bc8SSara Sharon } 1490e705c121SKalle Valo 149123ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 149223ae6128SMatti Gottlieb bool reset) 1493e705c121SKalle Valo { 149423ae6128SMatti Gottlieb if (!reset) { 1495e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1496e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1497e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1498e705c121SKalle Valo } 1499e705c121SKalle Valo 1500e705c121SKalle Valo iwl_disable_interrupts(trans); 1501e705c121SKalle Valo 1502e705c121SKalle Valo /* 1503e705c121SKalle Valo * in testing mode, the host stays awake and the 1504e705c121SKalle Valo * hardware won't be reset (not even partially) 1505e705c121SKalle Valo */ 1506e705c121SKalle Valo if (test) 1507e705c121SKalle Valo return; 1508e705c121SKalle Valo 1509e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1510e705c121SKalle Valo 15112e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1512e705c121SKalle Valo 1513e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1514a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1515e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1516a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1517e705c121SKalle Valo 15181316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, false); 15191316d595SSara Sharon 152023ae6128SMatti Gottlieb if (reset) { 1521e705c121SKalle Valo /* 1522e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1523e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1524e705c121SKalle Valo * to execute some invalid memory upon resume 1525e705c121SKalle Valo */ 1526e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1527e705c121SKalle Valo } 1528e705c121SKalle Valo 1529e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1530e705c121SKalle Valo } 1531e705c121SKalle Valo 1532e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1533e705c121SKalle Valo enum iwl_d3_status *status, 153423ae6128SMatti Gottlieb bool test, bool reset) 1535e705c121SKalle Valo { 1536d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1537e705c121SKalle Valo u32 val; 1538e705c121SKalle Valo int ret; 1539e705c121SKalle Valo 1540e705c121SKalle Valo if (test) { 1541e705c121SKalle Valo iwl_enable_interrupts(trans); 1542e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1543e705c121SKalle Valo return 0; 1544e705c121SKalle Valo } 1545e705c121SKalle Valo 15461316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 15471316d595SSara Sharon 1548a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1549a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1550a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1551a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 1552e705c121SKalle Valo 15536e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1554e705c121SKalle Valo udelay(2); 1555e705c121SKalle Valo 1556e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1557a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1558a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 1559e705c121SKalle Valo 25000); 1560e705c121SKalle Valo if (ret < 0) { 1561e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1562e705c121SKalle Valo return ret; 1563e705c121SKalle Valo } 1564e705c121SKalle Valo 1565f98ad635SEmmanuel Grumbach /* 1566f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1567f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1568f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1569f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1570f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1571f98ad635SEmmanuel Grumbach */ 1572f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1573f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1574f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1575f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1576f98ad635SEmmanuel Grumbach 1577e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1578e705c121SKalle Valo 157923ae6128SMatti Gottlieb if (!reset) { 1580e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1581a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 1582e705c121SKalle Valo } else { 1583e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1584e705c121SKalle Valo 1585e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1586e705c121SKalle Valo if (ret) { 1587e705c121SKalle Valo IWL_ERR(trans, 1588e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1589e705c121SKalle Valo return ret; 1590e705c121SKalle Valo } 1591e705c121SKalle Valo } 1592e705c121SKalle Valo 159382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 159482ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 159582ea7966SSara Sharon 1596e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1597e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1598e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1599e705c121SKalle Valo else 1600e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1601e705c121SKalle Valo 1602e705c121SKalle Valo return 0; 1603e705c121SKalle Valo } 1604e705c121SKalle Valo 16052e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16062e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 16072e5d4a8fSHaim Dreyfuss { 16082e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1609ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16102e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16112e5d4a8fSHaim Dreyfuss 161206f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 161306f4b081SSara Sharon goto enable_msi; 161406f4b081SSara Sharon 1615ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 161606f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16172e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16182e5d4a8fSHaim Dreyfuss 161906f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16202e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 162106f4b081SSara Sharon max_irqs); 162206f4b081SSara Sharon if (num_irqs < 0) { 1623496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 162406f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 162506f4b081SSara Sharon num_irqs); 162606f4b081SSara Sharon goto enable_msi; 1627496d83caSHaim Dreyfuss } 162806f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1629496d83caSHaim Dreyfuss 16302e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 163106f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 163206f4b081SSara Sharon num_irqs); 163306f4b081SSara Sharon 1634496d83caSHaim Dreyfuss /* 163506f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 163606f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1637496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1638496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1639496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1640496d83caSHaim Dreyfuss */ 1641ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 164206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1643496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1644496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1645ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 164606f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1647496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1648496d83caSHaim Dreyfuss } else { 164906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1650496d83caSHaim Dreyfuss } 1651ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16522e5d4a8fSHaim Dreyfuss 165306f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1654496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16552e5d4a8fSHaim Dreyfuss return; 16562e5d4a8fSHaim Dreyfuss 165706f4b081SSara Sharon enable_msi: 165806f4b081SSara Sharon ret = pci_enable_msi(pdev); 165906f4b081SSara Sharon if (ret) { 166006f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16612e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16622e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16632e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16642e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16652e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16662e5d4a8fSHaim Dreyfuss } 16672e5d4a8fSHaim Dreyfuss } 16682e5d4a8fSHaim Dreyfuss } 16692e5d4a8fSHaim Dreyfuss 16707c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16717c8d91ebSHaim Dreyfuss { 16727c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16737c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16747c8d91ebSHaim Dreyfuss 16757c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16767c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16777c8d91ebSHaim Dreyfuss offset = 1 + i; 16787c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16797c8d91ebSHaim Dreyfuss /* 16807c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16817c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16827c8d91ebSHaim Dreyfuss */ 16837c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16847c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16857c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16867c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16877c8d91ebSHaim Dreyfuss if (ret) 16887c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16897c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16907c8d91ebSHaim Dreyfuss i); 16917c8d91ebSHaim Dreyfuss } 16927c8d91ebSHaim Dreyfuss } 16937c8d91ebSHaim Dreyfuss 16942e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16952e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16962e5d4a8fSHaim Dreyfuss { 1697496d83caSHaim Dreyfuss int i; 16982e5d4a8fSHaim Dreyfuss 1699496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17002e5d4a8fSHaim Dreyfuss int ret; 17015a41a86cSSharon Dvir struct msix_entry *msix_entry; 170264fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 170364fa3affSSharon Dvir 170464fa3affSSharon Dvir if (!qname) 170564fa3affSSharon Dvir return -ENOMEM; 17062e5d4a8fSHaim Dreyfuss 17075a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17085a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17095a41a86cSSharon Dvir msix_entry->vector, 17102e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1711496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17122e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17132e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17142e5d4a8fSHaim Dreyfuss IRQF_SHARED, 171564fa3affSSharon Dvir qname, 17165a41a86cSSharon Dvir msix_entry); 17172e5d4a8fSHaim Dreyfuss if (ret) { 17182e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17192e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17205a41a86cSSharon Dvir 17212e5d4a8fSHaim Dreyfuss return ret; 17222e5d4a8fSHaim Dreyfuss } 17232e5d4a8fSHaim Dreyfuss } 17247c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17252e5d4a8fSHaim Dreyfuss 17262e5d4a8fSHaim Dreyfuss return 0; 17272e5d4a8fSHaim Dreyfuss } 17282e5d4a8fSHaim Dreyfuss 1729e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1730e705c121SKalle Valo { 1731e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1732e705c121SKalle Valo int err; 1733e705c121SKalle Valo 1734e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1735e705c121SKalle Valo 1736e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1737e705c121SKalle Valo if (err) { 1738e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1739e705c121SKalle Valo return err; 1740e705c121SKalle Valo } 1741e705c121SKalle Valo 1742870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1743e705c121SKalle Valo 174452b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 174552b6e168SEmmanuel Grumbach if (err) 174652b6e168SEmmanuel Grumbach return err; 1747e705c121SKalle Valo 17482e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 174983730058SHaim Dreyfuss 1750e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1751e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1752e705c121SKalle Valo 1753326477e4SJohannes Berg trans_pcie->opmode_down = false; 1754326477e4SJohannes Berg 1755e705c121SKalle Valo /* Set is_down to false here so that...*/ 1756e705c121SKalle Valo trans_pcie->is_down = false; 1757e705c121SKalle Valo 1758e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17599ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1760e705c121SKalle Valo 17614cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 17624cbb8e50SLuciano Coelho if (low_power) 17634cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 17644cbb8e50SLuciano Coelho 1765e705c121SKalle Valo return 0; 1766e705c121SKalle Valo } 1767e705c121SKalle Valo 1768e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1769e705c121SKalle Valo { 1770e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1771e705c121SKalle Valo int ret; 1772e705c121SKalle Valo 1773e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1774e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1775e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1776e705c121SKalle Valo 1777e705c121SKalle Valo return ret; 1778e705c121SKalle Valo } 1779e705c121SKalle Valo 1780e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1781e705c121SKalle Valo { 1782e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1783e705c121SKalle Valo 1784e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1785e705c121SKalle Valo 1786e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1787e705c121SKalle Valo iwl_disable_interrupts(trans); 1788e705c121SKalle Valo 1789e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1790e705c121SKalle Valo 1791e705c121SKalle Valo iwl_disable_interrupts(trans); 1792e705c121SKalle Valo 1793e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1794e705c121SKalle Valo 1795e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1796e705c121SKalle Valo 17972e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1798e705c121SKalle Valo } 1799e705c121SKalle Valo 1800e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1801e705c121SKalle Valo { 1802e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1803e705c121SKalle Valo } 1804e705c121SKalle Valo 1805e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1806e705c121SKalle Valo { 1807e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1808e705c121SKalle Valo } 1809e705c121SKalle Valo 1810e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1811e705c121SKalle Valo { 1812e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 181584fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 181684fb372cSSara Sharon { 181784fb372cSSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) 181884fb372cSSara Sharon return 0x00FFFFFF; 181984fb372cSSara Sharon else 182084fb372cSSara Sharon return 0x000FFFFF; 182184fb372cSSara Sharon } 182284fb372cSSara Sharon 1823e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1824e705c121SKalle Valo { 182584fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 182684fb372cSSara Sharon 1827e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 182884fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1829e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1830e705c121SKalle Valo } 1831e705c121SKalle Valo 1832e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1833e705c121SKalle Valo u32 val) 1834e705c121SKalle Valo { 183584fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 183684fb372cSSara Sharon 1837e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 183884fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1839e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1840e705c121SKalle Valo } 1841e705c121SKalle Valo 1842e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1843e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1844e705c121SKalle Valo { 1845e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1846e705c121SKalle Valo 1847e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1848e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1849e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1850e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1851e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1852e705c121SKalle Valo else 1853e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1854e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1855e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1856e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1857e705c121SKalle Valo 18586c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18596c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18606c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1861e705c121SKalle Valo 1862e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1863e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 186441837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1865e705c121SKalle Valo 186621cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 186721cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 186821cb3222SJohannes Berg 186939bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 187039bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 187139bdb17eSSharon Dvir 1872e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1873e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1874e705c121SKalle Valo * As this function may be called again in some corner cases don't 1875e705c121SKalle Valo * do anything if NAPI was already initialized. 1876e705c121SKalle Valo */ 1877bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1878e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1879e705c121SKalle Valo } 1880e705c121SKalle Valo 1881e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1882e705c121SKalle Valo { 1883e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18846eb5e529SEmmanuel Grumbach int i; 1885e705c121SKalle Valo 18862e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1887e705c121SKalle Valo 188813a3a390SSara Sharon if (trans->cfg->gen2) 188913a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 189013a3a390SSara Sharon else 1891e705c121SKalle Valo iwl_pcie_tx_free(trans); 1892e705c121SKalle Valo iwl_pcie_rx_free(trans); 1893e705c121SKalle Valo 189410a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 189510a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 189610a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 189710a54d81SLuca Coelho } 189810a54d81SLuca Coelho 18992e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19007c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19017c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19027c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19037c8d91ebSHaim Dreyfuss NULL); 19047c8d91ebSHaim Dreyfuss } 19052e5d4a8fSHaim Dreyfuss 19062e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19072e5d4a8fSHaim Dreyfuss } else { 1908e705c121SKalle Valo iwl_pcie_free_ict(trans); 19092e5d4a8fSHaim Dreyfuss } 1910e705c121SKalle Valo 1911e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1912e705c121SKalle Valo 19136eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19146eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19156eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19166eb5e529SEmmanuel Grumbach 19176eb5e529SEmmanuel Grumbach if (p->page) 19186eb5e529SEmmanuel Grumbach __free_page(p->page); 19196eb5e529SEmmanuel Grumbach } 19206eb5e529SEmmanuel Grumbach 19216eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1922a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1923e705c121SKalle Valo iwl_trans_free(trans); 1924e705c121SKalle Valo } 1925e705c121SKalle Valo 1926e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1927e705c121SKalle Valo { 1928e705c121SKalle Valo if (state) 1929e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1930e705c121SKalle Valo else 1931e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1932e705c121SKalle Valo } 1933e705c121SKalle Valo 193449564a80SLuca Coelho struct iwl_trans_pcie_removal { 193549564a80SLuca Coelho struct pci_dev *pdev; 193649564a80SLuca Coelho struct work_struct work; 193749564a80SLuca Coelho }; 193849564a80SLuca Coelho 193949564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 194049564a80SLuca Coelho { 194149564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 194249564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 194349564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 194449564a80SLuca Coelho char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 194549564a80SLuca Coelho 194649564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 194749564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 194849564a80SLuca Coelho pci_lock_rescan_remove(); 194949564a80SLuca Coelho pci_dev_put(pdev); 195049564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 195149564a80SLuca Coelho pci_unlock_rescan_remove(); 195249564a80SLuca Coelho 195349564a80SLuca Coelho kfree(removal); 195449564a80SLuca Coelho module_put(THIS_MODULE); 195549564a80SLuca Coelho } 195649564a80SLuca Coelho 195723ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1958e705c121SKalle Valo unsigned long *flags) 1959e705c121SKalle Valo { 1960e705c121SKalle Valo int ret; 1961e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1962e705c121SKalle Valo 1963e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1964e705c121SKalle Valo 1965e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1966e705c121SKalle Valo goto out; 1967e705c121SKalle Valo 1968e705c121SKalle Valo /* this bit wakes up the NIC */ 1969e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1970a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 19716e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1972e705c121SKalle Valo udelay(2); 1973e705c121SKalle Valo 1974e705c121SKalle Valo /* 1975e705c121SKalle Valo * These bits say the device is running, and should keep running for 1976e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1977e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1978fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1979fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1980e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1981e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1982e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1983e705c121SKalle Valo * to keep device from sleeping. 1984e705c121SKalle Valo * 1985e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1986e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1987fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 1988fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 1989fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 1990e705c121SKalle Valo * 1991e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1992e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1993e705c121SKalle Valo */ 1994e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1995a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_val_mac_access_en), 1996a8cbb46fSGolan Ben Ami (BIT(trans->cfg->csr->flag_mac_clock_ready) | 1997e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1998e705c121SKalle Valo if (unlikely(ret < 0)) { 199949564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 200049564a80SLuca Coelho 2001e705c121SKalle Valo WARN_ONCE(1, 2002e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 200349564a80SLuca Coelho cntrl); 200449564a80SLuca Coelho 200549564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 200649564a80SLuca Coelho 200749564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 200849564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 200949564a80SLuca Coelho 2010f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 201149564a80SLuca Coelho goto err; 201249564a80SLuca Coelho 201349564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 201449564a80SLuca Coelho 201549564a80SLuca Coelho /* 201649564a80SLuca Coelho * get a module reference to avoid doing this 201749564a80SLuca Coelho * while unloading anyway and to avoid 201849564a80SLuca Coelho * scheduling a work with code that's being 201949564a80SLuca Coelho * removed. 202049564a80SLuca Coelho */ 202149564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 202249564a80SLuca Coelho IWL_ERR(trans, 202349564a80SLuca Coelho "Module is being unloaded - abort\n"); 202449564a80SLuca Coelho goto err; 202549564a80SLuca Coelho } 202649564a80SLuca Coelho 202749564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 202849564a80SLuca Coelho if (!removal) { 202949564a80SLuca Coelho module_put(THIS_MODULE); 203049564a80SLuca Coelho goto err; 203149564a80SLuca Coelho } 203249564a80SLuca Coelho /* 203349564a80SLuca Coelho * we don't need to clear this flag, because 203449564a80SLuca Coelho * the trans will be freed and reallocated. 203549564a80SLuca Coelho */ 2036f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 203749564a80SLuca Coelho 203849564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 203949564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 204049564a80SLuca Coelho pci_dev_get(removal->pdev); 204149564a80SLuca Coelho schedule_work(&removal->work); 204249564a80SLuca Coelho } else { 204349564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 204449564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 204549564a80SLuca Coelho } 204649564a80SLuca Coelho 204749564a80SLuca Coelho err: 2048e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2049e705c121SKalle Valo return false; 2050e705c121SKalle Valo } 2051e705c121SKalle Valo 2052e705c121SKalle Valo out: 2053e705c121SKalle Valo /* 2054e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2055e705c121SKalle Valo * track nic_access anyway. 2056e705c121SKalle Valo */ 2057e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2058e705c121SKalle Valo return true; 2059e705c121SKalle Valo } 2060e705c121SKalle Valo 2061e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2062e705c121SKalle Valo unsigned long *flags) 2063e705c121SKalle Valo { 2064e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2065e705c121SKalle Valo 2066e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2067e705c121SKalle Valo 2068e705c121SKalle Valo /* 2069e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2070e705c121SKalle Valo * track nic_access anyway. 2071e705c121SKalle Valo */ 2072e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2073e705c121SKalle Valo 2074e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2075e705c121SKalle Valo goto out; 2076e705c121SKalle Valo 2077e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2078a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_access_req)); 2079e705c121SKalle Valo /* 2080e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2081e705c121SKalle Valo * any previous writes, but we need the write that clears the 2082e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2083e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2084e705c121SKalle Valo */ 2085e705c121SKalle Valo mmiowb(); 2086e705c121SKalle Valo out: 2087e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2088e705c121SKalle Valo } 2089e705c121SKalle Valo 2090e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2091e705c121SKalle Valo void *buf, int dwords) 2092e705c121SKalle Valo { 2093e705c121SKalle Valo unsigned long flags; 2094e705c121SKalle Valo int offs, ret = 0; 2095e705c121SKalle Valo u32 *vals = buf; 2096e705c121SKalle Valo 209723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2098e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2099e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2100e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2101e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2102e705c121SKalle Valo } else { 2103e705c121SKalle Valo ret = -EBUSY; 2104e705c121SKalle Valo } 2105e705c121SKalle Valo return ret; 2106e705c121SKalle Valo } 2107e705c121SKalle Valo 2108e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2109e705c121SKalle Valo const void *buf, int dwords) 2110e705c121SKalle Valo { 2111e705c121SKalle Valo unsigned long flags; 2112e705c121SKalle Valo int offs, ret = 0; 2113e705c121SKalle Valo const u32 *vals = buf; 2114e705c121SKalle Valo 211523ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2116e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2117e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2118e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2119e705c121SKalle Valo vals ? vals[offs] : 0); 2120e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2121e705c121SKalle Valo } else { 2122e705c121SKalle Valo ret = -EBUSY; 2123e705c121SKalle Valo } 2124e705c121SKalle Valo return ret; 2125e705c121SKalle Valo } 2126e705c121SKalle Valo 2127e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2128e705c121SKalle Valo unsigned long txqs, 2129e705c121SKalle Valo bool freeze) 2130e705c121SKalle Valo { 2131e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2132e705c121SKalle Valo int queue; 2133e705c121SKalle Valo 2134e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2135b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2136e705c121SKalle Valo unsigned long now; 2137e705c121SKalle Valo 2138e705c121SKalle Valo spin_lock_bh(&txq->lock); 2139e705c121SKalle Valo 2140e705c121SKalle Valo now = jiffies; 2141e705c121SKalle Valo 2142e705c121SKalle Valo if (txq->frozen == freeze) 2143e705c121SKalle Valo goto next_queue; 2144e705c121SKalle Valo 2145e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2146e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2147e705c121SKalle Valo 2148e705c121SKalle Valo txq->frozen = freeze; 2149e705c121SKalle Valo 2150bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2151e705c121SKalle Valo goto next_queue; 2152e705c121SKalle Valo 2153e705c121SKalle Valo if (freeze) { 2154e705c121SKalle Valo if (unlikely(time_after(now, 2155e705c121SKalle Valo txq->stuck_timer.expires))) { 2156e705c121SKalle Valo /* 2157e705c121SKalle Valo * The timer should have fired, maybe it is 2158e705c121SKalle Valo * spinning right now on the lock. 2159e705c121SKalle Valo */ 2160e705c121SKalle Valo goto next_queue; 2161e705c121SKalle Valo } 2162e705c121SKalle Valo /* remember how long until the timer fires */ 2163e705c121SKalle Valo txq->frozen_expiry_remainder = 2164e705c121SKalle Valo txq->stuck_timer.expires - now; 2165e705c121SKalle Valo del_timer(&txq->stuck_timer); 2166e705c121SKalle Valo goto next_queue; 2167e705c121SKalle Valo } 2168e705c121SKalle Valo 2169e705c121SKalle Valo /* 2170e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2171e705c121SKalle Valo * remainder before it froze 2172e705c121SKalle Valo */ 2173e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2174e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2175e705c121SKalle Valo 2176e705c121SKalle Valo next_queue: 2177e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2178e705c121SKalle Valo } 2179e705c121SKalle Valo } 2180e705c121SKalle Valo 21810cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21820cd58eaaSEmmanuel Grumbach { 21830cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21840cd58eaaSEmmanuel Grumbach int i; 21850cd58eaaSEmmanuel Grumbach 21860cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2187b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 21880cd58eaaSEmmanuel Grumbach 21890cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 21900cd58eaaSEmmanuel Grumbach continue; 21910cd58eaaSEmmanuel Grumbach 21920cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 21930cd58eaaSEmmanuel Grumbach 21940cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 21950cd58eaaSEmmanuel Grumbach txq->block--; 21960cd58eaaSEmmanuel Grumbach if (!txq->block) { 21970cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2198bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 21990cd58eaaSEmmanuel Grumbach } 22000cd58eaaSEmmanuel Grumbach } else if (block) { 22010cd58eaaSEmmanuel Grumbach txq->block++; 22020cd58eaaSEmmanuel Grumbach } 22030cd58eaaSEmmanuel Grumbach 22040cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22050cd58eaaSEmmanuel Grumbach } 22060cd58eaaSEmmanuel Grumbach } 22070cd58eaaSEmmanuel Grumbach 2208e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2209e705c121SKalle Valo 221038398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 221138398efbSSara Sharon { 2212afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2213afb84431SEmmanuel Grumbach u32 status; 2214afb84431SEmmanuel Grumbach bool active; 2215afb84431SEmmanuel Grumbach u8 fifo; 221638398efbSSara Sharon 2217afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2218afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2219bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2220ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2221ae79785fSSara Sharon return; 2222afb84431SEmmanuel Grumbach } 2223ae79785fSSara Sharon 2224afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2225afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2226afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 222738398efbSSara Sharon 222838398efbSSara Sharon IWL_ERR(trans, 2229afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2230afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2231afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2232afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2233afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 22347b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2235afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 22367b3e42eaSGolan Ben Ami (trans->cfg->base_params->max_tfd_queue_size - 1), 2237afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 223838398efbSSara Sharon } 223938398efbSSara Sharon 224092536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 224192536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 224292536c96SSara Sharon { 224392536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 224492536c96SSara Sharon 224592536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 224692536c96SSara Sharon return -EINVAL; 224792536c96SSara Sharon 224892536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 224992536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 225092536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 225192536c96SSara Sharon data->fr_bd_wid = 0; 225292536c96SSara Sharon 225392536c96SSara Sharon return 0; 225492536c96SSara Sharon } 225592536c96SSara Sharon 2256d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2257e705c121SKalle Valo { 2258e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2259e705c121SKalle Valo struct iwl_txq *txq; 2260e705c121SKalle Valo unsigned long now = jiffies; 2261e705c121SKalle Valo u8 wr_ptr; 2262e705c121SKalle Valo 22632b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2264f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2265f60c9e59SEmmanuel Grumbach return -ENODEV; 22662b3fae66SMatt Chen 2267d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2268d6d517b7SSara Sharon return -EINVAL; 2269e705c121SKalle Valo 2270d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2271d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 22726aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2273e705c121SKalle Valo 22746aa7de05SMark Rutland while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2275e705c121SKalle Valo !time_after(jiffies, 2276e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 22776aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2278e705c121SKalle Valo 2279e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 2280e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2281e705c121SKalle Valo wr_ptr, write_ptr)) 2282e705c121SKalle Valo return -ETIMEDOUT; 2283192185d6SJohannes Berg usleep_range(1000, 2000); 2284e705c121SKalle Valo } 2285e705c121SKalle Valo 2286bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2287e705c121SKalle Valo IWL_ERR(trans, 2288d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2289d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2290d6d517b7SSara Sharon return -ETIMEDOUT; 2291e705c121SKalle Valo } 2292e705c121SKalle Valo 2293d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2294d6d517b7SSara Sharon 2295d6d517b7SSara Sharon return 0; 2296d6d517b7SSara Sharon } 2297d6d517b7SSara Sharon 2298d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2299d6d517b7SSara Sharon { 2300d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2301d6d517b7SSara Sharon int cnt; 2302d6d517b7SSara Sharon int ret = 0; 2303d6d517b7SSara Sharon 2304d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2305d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2306d6d517b7SSara Sharon 2307d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2308d6d517b7SSara Sharon continue; 2309d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2310d6d517b7SSara Sharon continue; 2311d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2312d6d517b7SSara Sharon continue; 2313d6d517b7SSara Sharon 2314d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 231538398efbSSara Sharon if (ret) 2316d6d517b7SSara Sharon break; 2317d6d517b7SSara Sharon } 2318e705c121SKalle Valo 2319e705c121SKalle Valo return ret; 2320e705c121SKalle Valo } 2321e705c121SKalle Valo 2322e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2323e705c121SKalle Valo u32 mask, u32 value) 2324e705c121SKalle Valo { 2325e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2326e705c121SKalle Valo unsigned long flags; 2327e705c121SKalle Valo 2328e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2329e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2330e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2331e705c121SKalle Valo } 2332e705c121SKalle Valo 2333c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2334e705c121SKalle Valo { 2335e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2336e705c121SKalle Valo 2337e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2338e705c121SKalle Valo return; 2339e705c121SKalle Valo 2340b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 23415d93f3a2SLuca Coelho 23425d93f3a2SLuca Coelho #ifdef CONFIG_PM 23435d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23445d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23455d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2346e705c121SKalle Valo } 2347e705c121SKalle Valo 2348c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2349e705c121SKalle Valo { 2350e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2351e705c121SKalle Valo 2352e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2353e705c121SKalle Valo return; 2354e705c121SKalle Valo 2355b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2356b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2357b3ff1270SLuca Coelho 23585d93f3a2SLuca Coelho #ifdef CONFIG_PM 23595d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 23605d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 23615d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2362e705c121SKalle Valo } 2363e705c121SKalle Valo 2364e705c121SKalle Valo static const char *get_csr_string(int cmd) 2365e705c121SKalle Valo { 2366e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2367e705c121SKalle Valo switch (cmd) { 2368e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2369e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2370e705c121SKalle Valo IWL_CMD(CSR_INT); 2371e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2372e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2373e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2374e705c121SKalle Valo IWL_CMD(CSR_RESET); 2375e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2376e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2377e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2378e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2379e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2380e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2381e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2382e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2383e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2384e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2385e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2386e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2387e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2388e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2389e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2390e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2391e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2392e705c121SKalle Valo default: 2393e705c121SKalle Valo return "UNKNOWN"; 2394e705c121SKalle Valo } 2395e705c121SKalle Valo #undef IWL_CMD 2396e705c121SKalle Valo } 2397e705c121SKalle Valo 2398e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2399e705c121SKalle Valo { 2400e705c121SKalle Valo int i; 2401e705c121SKalle Valo static const u32 csr_tbl[] = { 2402e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2403e705c121SKalle Valo CSR_INT_COALESCING, 2404e705c121SKalle Valo CSR_INT, 2405e705c121SKalle Valo CSR_INT_MASK, 2406e705c121SKalle Valo CSR_FH_INT_STATUS, 2407e705c121SKalle Valo CSR_GPIO_IN, 2408e705c121SKalle Valo CSR_RESET, 2409e705c121SKalle Valo CSR_GP_CNTRL, 2410e705c121SKalle Valo CSR_HW_REV, 2411e705c121SKalle Valo CSR_EEPROM_REG, 2412e705c121SKalle Valo CSR_EEPROM_GP, 2413e705c121SKalle Valo CSR_OTP_GP_REG, 2414e705c121SKalle Valo CSR_GIO_REG, 2415e705c121SKalle Valo CSR_GP_UCODE_REG, 2416e705c121SKalle Valo CSR_GP_DRIVER_REG, 2417e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2418e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2419e705c121SKalle Valo CSR_LED_REG, 2420e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2421e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2422e705c121SKalle Valo CSR_ANA_PLL_CFG, 2423e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2424e705c121SKalle Valo CSR_HW_REV_WA_REG, 2425e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2426e705c121SKalle Valo }; 2427e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2428e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2429e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2430e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2431e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2432e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2433e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2434e705c121SKalle Valo } 2435e705c121SKalle Valo } 2436e705c121SKalle Valo 2437e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2438e705c121SKalle Valo /* create and remove of files */ 2439e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2440e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 2441e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 2442e705c121SKalle Valo goto err; \ 2443e705c121SKalle Valo } while (0) 2444e705c121SKalle Valo 2445e705c121SKalle Valo /* file operation */ 2446e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2447e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2448e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2449e705c121SKalle Valo .open = simple_open, \ 2450e705c121SKalle Valo .llseek = generic_file_llseek, \ 2451e705c121SKalle Valo }; 2452e705c121SKalle Valo 2453e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2454e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2455e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2456e705c121SKalle Valo .open = simple_open, \ 2457e705c121SKalle Valo .llseek = generic_file_llseek, \ 2458e705c121SKalle Valo }; 2459e705c121SKalle Valo 2460e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2461e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2462e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2463e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2464e705c121SKalle Valo .open = simple_open, \ 2465e705c121SKalle Valo .llseek = generic_file_llseek, \ 2466e705c121SKalle Valo }; 2467e705c121SKalle Valo 2468e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2469e705c121SKalle Valo char __user *user_buf, 2470e705c121SKalle Valo size_t count, loff_t *ppos) 2471e705c121SKalle Valo { 2472e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2473e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2474e705c121SKalle Valo struct iwl_txq *txq; 2475e705c121SKalle Valo char *buf; 2476e705c121SKalle Valo int pos = 0; 2477e705c121SKalle Valo int cnt; 2478e705c121SKalle Valo int ret; 2479e705c121SKalle Valo size_t bufsz; 2480e705c121SKalle Valo 2481e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2482e705c121SKalle Valo 2483b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2484e705c121SKalle Valo return -EAGAIN; 2485e705c121SKalle Valo 2486e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2487e705c121SKalle Valo if (!buf) 2488e705c121SKalle Valo return -ENOMEM; 2489e705c121SKalle Valo 2490e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2491b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2492e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2493e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2494bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2495e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2496e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2497e705c121SKalle Valo txq->need_update, txq->frozen, 2498e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2499e705c121SKalle Valo } 2500e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2501e705c121SKalle Valo kfree(buf); 2502e705c121SKalle Valo return ret; 2503e705c121SKalle Valo } 2504e705c121SKalle Valo 2505e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2506e705c121SKalle Valo char __user *user_buf, 2507e705c121SKalle Valo size_t count, loff_t *ppos) 2508e705c121SKalle Valo { 2509e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2510e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251178485054SSara Sharon char *buf; 251278485054SSara Sharon int pos = 0, i, ret; 251378485054SSara Sharon size_t bufsz = sizeof(buf); 2514e705c121SKalle Valo 251578485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 251678485054SSara Sharon 251778485054SSara Sharon if (!trans_pcie->rxq) 251878485054SSara Sharon return -EAGAIN; 251978485054SSara Sharon 252078485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 252178485054SSara Sharon if (!buf) 252278485054SSara Sharon return -ENOMEM; 252378485054SSara Sharon 252478485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 252578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 252678485054SSara Sharon 252778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 252878485054SSara Sharon i); 252978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2530e705c121SKalle Valo rxq->read); 253178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2532e705c121SKalle Valo rxq->write); 253378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2534e705c121SKalle Valo rxq->write_actual); 253578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2536e705c121SKalle Valo rxq->need_update); 253778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2538e705c121SKalle Valo rxq->free_count); 2539e705c121SKalle Valo if (rxq->rb_stts) { 25400307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 25410307c839SGolan Ben Ami rxq)); 254278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 254378485054SSara Sharon "\tclosed_rb_num: %u\n", 25440307c839SGolan Ben Ami r & 0x0FFF); 2545e705c121SKalle Valo } else { 2546e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 254778485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2548e705c121SKalle Valo } 254978485054SSara Sharon } 255078485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 255178485054SSara Sharon kfree(buf); 255278485054SSara Sharon 255378485054SSara Sharon return ret; 2554e705c121SKalle Valo } 2555e705c121SKalle Valo 2556e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2557e705c121SKalle Valo char __user *user_buf, 2558e705c121SKalle Valo size_t count, loff_t *ppos) 2559e705c121SKalle Valo { 2560e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2561e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2562e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2563e705c121SKalle Valo 2564e705c121SKalle Valo int pos = 0; 2565e705c121SKalle Valo char *buf; 2566e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2567e705c121SKalle Valo ssize_t ret; 2568e705c121SKalle Valo 2569e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2570e705c121SKalle Valo if (!buf) 2571e705c121SKalle Valo return -ENOMEM; 2572e705c121SKalle Valo 2573e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2574e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2575e705c121SKalle Valo 2576e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2577e705c121SKalle Valo isr_stats->hw); 2578e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2579e705c121SKalle Valo isr_stats->sw); 2580e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2581e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2582e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2583e705c121SKalle Valo isr_stats->err_code); 2584e705c121SKalle Valo } 2585e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2586e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2587e705c121SKalle Valo isr_stats->sch); 2588e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2589e705c121SKalle Valo isr_stats->alive); 2590e705c121SKalle Valo #endif 2591e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2592e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2593e705c121SKalle Valo 2594e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2595e705c121SKalle Valo isr_stats->ctkill); 2596e705c121SKalle Valo 2597e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2598e705c121SKalle Valo isr_stats->wakeup); 2599e705c121SKalle Valo 2600e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2601e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2602e705c121SKalle Valo 2603e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2604e705c121SKalle Valo isr_stats->tx); 2605e705c121SKalle Valo 2606e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2607e705c121SKalle Valo isr_stats->unhandled); 2608e705c121SKalle Valo 2609e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2610e705c121SKalle Valo kfree(buf); 2611e705c121SKalle Valo return ret; 2612e705c121SKalle Valo } 2613e705c121SKalle Valo 2614e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2615e705c121SKalle Valo const char __user *user_buf, 2616e705c121SKalle Valo size_t count, loff_t *ppos) 2617e705c121SKalle Valo { 2618e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2619e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2620e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2621e705c121SKalle Valo u32 reset_flag; 2622078f1131SJohannes Berg int ret; 2623e705c121SKalle Valo 2624078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2625078f1131SJohannes Berg if (ret) 2626078f1131SJohannes Berg return ret; 2627e705c121SKalle Valo if (reset_flag == 0) 2628e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2629e705c121SKalle Valo 2630e705c121SKalle Valo return count; 2631e705c121SKalle Valo } 2632e705c121SKalle Valo 2633e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2634e705c121SKalle Valo const char __user *user_buf, 2635e705c121SKalle Valo size_t count, loff_t *ppos) 2636e705c121SKalle Valo { 2637e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2638e705c121SKalle Valo 2639e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2640e705c121SKalle Valo 2641e705c121SKalle Valo return count; 2642e705c121SKalle Valo } 2643e705c121SKalle Valo 2644e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2645e705c121SKalle Valo char __user *user_buf, 2646e705c121SKalle Valo size_t count, loff_t *ppos) 2647e705c121SKalle Valo { 2648e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2649e705c121SKalle Valo char *buf = NULL; 2650e705c121SKalle Valo ssize_t ret; 2651e705c121SKalle Valo 2652e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2653e705c121SKalle Valo if (ret < 0) 2654e705c121SKalle Valo return ret; 2655e705c121SKalle Valo if (!buf) 2656e705c121SKalle Valo return -EINVAL; 2657e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2658e705c121SKalle Valo kfree(buf); 2659e705c121SKalle Valo return ret; 2660e705c121SKalle Valo } 2661e705c121SKalle Valo 2662fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2663fa4de7f7SJohannes Berg char __user *user_buf, 2664fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2665fa4de7f7SJohannes Berg { 2666fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2667fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2668fa4de7f7SJohannes Berg char buf[100]; 2669fa4de7f7SJohannes Berg int pos; 2670fa4de7f7SJohannes Berg 2671fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2672fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2673fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2674fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2675fa4de7f7SJohannes Berg 2676fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2677fa4de7f7SJohannes Berg } 2678fa4de7f7SJohannes Berg 2679fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2680fa4de7f7SJohannes Berg const char __user *user_buf, 2681fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2682fa4de7f7SJohannes Berg { 2683fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2684fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2685fa4de7f7SJohannes Berg bool old = trans_pcie->debug_rfkill; 2686fa4de7f7SJohannes Berg int ret; 2687fa4de7f7SJohannes Berg 2688fa4de7f7SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2689fa4de7f7SJohannes Berg if (ret) 2690fa4de7f7SJohannes Berg return ret; 2691fa4de7f7SJohannes Berg if (old == trans_pcie->debug_rfkill) 2692fa4de7f7SJohannes Berg return count; 2693fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2694fa4de7f7SJohannes Berg old, trans_pcie->debug_rfkill); 2695fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2696fa4de7f7SJohannes Berg 2697fa4de7f7SJohannes Berg return count; 2698fa4de7f7SJohannes Berg } 2699fa4de7f7SJohannes Berg 2700e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2701e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2702e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2703e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2704e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2705fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2706e705c121SKalle Valo 2707f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2708f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2709e705c121SKalle Valo { 2710f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2711f8a1edb7SJohannes Berg 27122ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 27132ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 27142ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 27152ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 27162ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 27172ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2718e705c121SKalle Valo return 0; 2719e705c121SKalle Valo 2720e705c121SKalle Valo err: 2721e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2722e705c121SKalle Valo return -ENOMEM; 2723e705c121SKalle Valo } 2724e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2725e705c121SKalle Valo 27266983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2727e705c121SKalle Valo { 27283cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2729e705c121SKalle Valo u32 cmdlen = 0; 2730e705c121SKalle Valo int i; 2731e705c121SKalle Valo 27323cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 27336983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2734e705c121SKalle Valo 2735e705c121SKalle Valo return cmdlen; 2736e705c121SKalle Valo } 2737e705c121SKalle Valo 2738e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2739e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2740e705c121SKalle Valo int allocated_rb_nums) 2741e705c121SKalle Valo { 2742e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2743e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 274478485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 274578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2746e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2747e705c121SKalle Valo 2748e705c121SKalle Valo spin_lock(&rxq->lock); 2749e705c121SKalle Valo 27500307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2751e705c121SKalle Valo 2752e705c121SKalle Valo for (i = rxq->read, j = 0; 2753e705c121SKalle Valo i != r && j < allocated_rb_nums; 2754e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2755e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2756e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2757e705c121SKalle Valo 2758e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2759e705c121SKalle Valo DMA_FROM_DEVICE); 2760e705c121SKalle Valo 2761e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2762e705c121SKalle Valo 2763e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2764e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2765e705c121SKalle Valo rb = (void *)(*data)->data; 2766e705c121SKalle Valo rb->index = cpu_to_le32(i); 2767e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2768e705c121SKalle Valo /* remap the page for the free benefit */ 2769e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2770e705c121SKalle Valo max_len, 2771e705c121SKalle Valo DMA_FROM_DEVICE); 2772e705c121SKalle Valo 2773e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2774e705c121SKalle Valo } 2775e705c121SKalle Valo 2776e705c121SKalle Valo spin_unlock(&rxq->lock); 2777e705c121SKalle Valo 2778e705c121SKalle Valo return rb_len; 2779e705c121SKalle Valo } 2780e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2781e705c121SKalle Valo 2782e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2783e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2784e705c121SKalle Valo { 2785e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2786e705c121SKalle Valo __le32 *val; 2787e705c121SKalle Valo int i; 2788e705c121SKalle Valo 2789e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2790e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2791e705c121SKalle Valo val = (void *)(*data)->data; 2792e705c121SKalle Valo 2793e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2794e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2795e705c121SKalle Valo 2796e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2797e705c121SKalle Valo 2798e705c121SKalle Valo return csr_len; 2799e705c121SKalle Valo } 2800e705c121SKalle Valo 2801e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2802e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2803e705c121SKalle Valo { 2804e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2805e705c121SKalle Valo unsigned long flags; 2806e705c121SKalle Valo __le32 *val; 2807e705c121SKalle Valo int i; 2808e705c121SKalle Valo 280923ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2810e705c121SKalle Valo return 0; 2811e705c121SKalle Valo 2812e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2813e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2814e705c121SKalle Valo val = (void *)(*data)->data; 2815e705c121SKalle Valo 2816723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2817723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2818723b45e2SLiad Kaufman i += sizeof(u32)) 2819e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2820723b45e2SLiad Kaufman else 2821723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2822723b45e2SLiad Kaufman i += sizeof(u32)) 2823723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2824723b45e2SLiad Kaufman i)); 2825e705c121SKalle Valo 2826e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2827e705c121SKalle Valo 2828e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2829e705c121SKalle Valo 2830e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2831e705c121SKalle Valo } 2832e705c121SKalle Valo 2833e705c121SKalle Valo static u32 2834e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2835e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2836e705c121SKalle Valo u32 monitor_len) 2837e705c121SKalle Valo { 2838e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2839e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2840e705c121SKalle Valo unsigned long flags; 2841e705c121SKalle Valo u32 i; 2842e705c121SKalle Valo 284323ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2844e705c121SKalle Valo return 0; 2845e705c121SKalle Valo 284614ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2847e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 284814ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 284914ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 285014ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2851e705c121SKalle Valo 2852e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2853e705c121SKalle Valo 2854e705c121SKalle Valo return monitor_len; 2855e705c121SKalle Valo } 2856e705c121SKalle Valo 2857e705c121SKalle Valo static u32 2858e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2859e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2860e705c121SKalle Valo u32 monitor_len) 2861e705c121SKalle Valo { 2862e705c121SKalle Valo u32 len = 0; 2863e705c121SKalle Valo 286488964b2eSSara Sharon if ((trans->num_blocks && 2865e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2866e705c121SKalle Valo trans->dbg_dest_tlv) { 2867e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2868e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2869e705c121SKalle Valo 2870e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2871e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2872e705c121SKalle Valo write_ptr = 2873e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2874e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2875e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2876e705c121SKalle Valo } else { 2877e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2878e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2879e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2880e705c121SKalle Valo } 2881e705c121SKalle Valo 2882e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2883e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2884e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2885e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2886e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2887e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2888e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2889e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2890e705c121SKalle Valo 2891e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 289288964b2eSSara Sharon if (trans->num_blocks) { 2893e705c121SKalle Valo memcpy(fw_mon_data->data, 289488964b2eSSara Sharon trans->fw_mon[0].block, 289588964b2eSSara Sharon trans->fw_mon[0].size); 2896e705c121SKalle Valo 289788964b2eSSara Sharon monitor_len = trans->fw_mon[0].size; 2898e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2899e705c121SKalle Valo /* 2900e705c121SKalle Valo * Update pointers to reflect actual values after 2901e705c121SKalle Valo * shifting 2902e705c121SKalle Valo */ 2903fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version) { 2904fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 2905fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 2906fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 2907fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 2908fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 2909fd527eb5SGolan Ben Ami } else { 2910e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2911e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2912fd527eb5SGolan Ben Ami } 2913fd527eb5SGolan Ben Ami 2914e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2915e705c121SKalle Valo monitor_len / sizeof(u32)); 2916e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2917e705c121SKalle Valo monitor_len = 2918e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2919e705c121SKalle Valo fw_mon_data, 2920e705c121SKalle Valo monitor_len); 2921e705c121SKalle Valo } else { 2922e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2923e705c121SKalle Valo monitor_len = 0; 2924e705c121SKalle Valo } 2925e705c121SKalle Valo 2926e705c121SKalle Valo len += monitor_len; 2927e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2928e705c121SKalle Valo } 2929e705c121SKalle Valo 2930e705c121SKalle Valo return len; 2931e705c121SKalle Valo } 2932e705c121SKalle Valo 2933da752717SShahar S Matityahu static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, int *len) 2934e705c121SKalle Valo { 293588964b2eSSara Sharon if (trans->num_blocks) { 2936da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 2937da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 293888964b2eSSara Sharon trans->fw_mon[0].size; 293988964b2eSSara Sharon return trans->fw_mon[0].size; 2940e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2941da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 2942e705c121SKalle Valo 2943fd527eb5SGolan Ben Ami if (trans->dbg_dest_tlv->version == 1) { 2944fd527eb5SGolan Ben Ami cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2945fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 2946fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 2947fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->base_shift; 2948fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 2949fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 2950fd527eb5SGolan Ben Ami 2951fd527eb5SGolan Ben Ami monitor_len = 2952fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 2953fd527eb5SGolan Ben Ami trans->dbg_dest_tlv->end_shift; 2954fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 2955fd527eb5SGolan Ben Ami } else { 2956e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2957e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2958e705c121SKalle Valo 2959e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2960e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2961e705c121SKalle Valo end = iwl_read_prph(trans, end) << 2962e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 2963e705c121SKalle Valo 2964e705c121SKalle Valo /* Make "end" point to the actual end */ 2965fd527eb5SGolan Ben Ami if (trans->cfg->device_family >= 2966fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 2967e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2968e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 2969e705c121SKalle Valo monitor_len = end - base; 2970fd527eb5SGolan Ben Ami } 2971da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 2972da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 2973e705c121SKalle Valo monitor_len; 2974da752717SShahar S Matityahu return monitor_len; 2975e705c121SKalle Valo } 2976da752717SShahar S Matityahu return 0; 2977da752717SShahar S Matityahu } 2978da752717SShahar S Matityahu 2979da752717SShahar S Matityahu static struct iwl_trans_dump_data 2980da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2981da752717SShahar S Matityahu const struct iwl_fw_dbg_trigger_tlv *trigger) 2982da752717SShahar S Matityahu { 2983da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2984da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 2985da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2986da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 2987da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 2988da752717SShahar S Matityahu u32 len, num_rbs = 0; 2989da752717SShahar S Matityahu u32 monitor_len; 2990da752717SShahar S Matityahu int i, ptr; 2991da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 2992da752717SShahar S Matityahu !trans->cfg->mq_rx_supported && 2993da752717SShahar S Matityahu trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 2994da752717SShahar S Matityahu 2995da752717SShahar S Matityahu /* transport dump header */ 2996da752717SShahar S Matityahu len = sizeof(*dump_data); 2997da752717SShahar S Matityahu 2998da752717SShahar S Matityahu /* host commands */ 2999da752717SShahar S Matityahu len += sizeof(*data) + 3000da752717SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 3001da752717SShahar S Matityahu 3002da752717SShahar S Matityahu /* FW monitor */ 3003da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3004e705c121SKalle Valo 3005e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 3006520f03eaSShahar S Matityahu if (!(trans->dbg_dump_mask & 3007520f03eaSShahar S Matityahu BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))) 3008520f03eaSShahar S Matityahu return NULL; 3009520f03eaSShahar S Matityahu 3010e705c121SKalle Valo dump_data = vzalloc(len); 3011e705c121SKalle Valo if (!dump_data) 3012e705c121SKalle Valo return NULL; 3013e705c121SKalle Valo 3014e705c121SKalle Valo data = (void *)dump_data->data; 3015e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3016e705c121SKalle Valo dump_data->len = len; 3017e705c121SKalle Valo 3018e705c121SKalle Valo return dump_data; 3019e705c121SKalle Valo } 3020e705c121SKalle Valo 3021e705c121SKalle Valo /* CSR registers */ 3022520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3023e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3024e705c121SKalle Valo 3025e705c121SKalle Valo /* FH registers */ 3026520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3027723b45e2SLiad Kaufman if (trans->cfg->gen2) 3028723b45e2SLiad Kaufman len += sizeof(*data) + 3029520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND_GEN2 - 3030520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND_GEN2); 3031723b45e2SLiad Kaufman else 3032723b45e2SLiad Kaufman len += sizeof(*data) + 3033520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3034520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3035520f03eaSShahar S Matityahu } 3036e705c121SKalle Valo 3037e705c121SKalle Valo if (dump_rbs) { 303878485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 303978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3040e705c121SKalle Valo /* RBs */ 30410307c839SGolan Ben Ami num_rbs = 30420307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3043e705c121SKalle Valo & 0x0FFF; 304478485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3045e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3046e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3047e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3048e705c121SKalle Valo } 3049e705c121SKalle Valo 30505538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3051520f03eaSShahar S Matityahu if (trans->cfg->gen2 && 3052520f03eaSShahar S Matityahu trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 30535538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 30545538409bSLiad Kaufman len += sizeof(*data) + 30555538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 30565538409bSLiad Kaufman trans_pcie->init_dram.paging[i].size; 30575538409bSLiad Kaufman 3058e705c121SKalle Valo dump_data = vzalloc(len); 3059e705c121SKalle Valo if (!dump_data) 3060e705c121SKalle Valo return NULL; 3061e705c121SKalle Valo 3062e705c121SKalle Valo len = 0; 3063e705c121SKalle Valo data = (void *)dump_data->data; 3064520f03eaSShahar S Matityahu 3065520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) { 3066520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3067520f03eaSShahar S Matityahu 3068e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3069e705c121SKalle Valo txcmd = (void *)data->data; 3070e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3071bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3072bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 30734ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 3074e705c121SKalle Valo u32 caplen, cmdlen; 3075e705c121SKalle Valo 3076520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3077520f03eaSShahar S Matityahu cmdq->tfds + 3078520f03eaSShahar S Matityahu tfd_size * ptr); 3079e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3080e705c121SKalle Valo 3081e705c121SKalle Valo if (cmdlen) { 3082e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3083e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3084e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3085520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3086520f03eaSShahar S Matityahu caplen); 3087e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3088e705c121SKalle Valo } 3089e705c121SKalle Valo 30907b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3091e705c121SKalle Valo } 3092e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3093e705c121SKalle Valo 3094e705c121SKalle Valo data->len = cpu_to_le32(len); 3095e705c121SKalle Valo len += sizeof(*data); 3096e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3097520f03eaSShahar S Matityahu } 3098e705c121SKalle Valo 3099520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3100e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 3101520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3102e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3103e705c121SKalle Valo if (dump_rbs) 3104e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3105e705c121SKalle Valo 31065538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3107520f03eaSShahar S Matityahu if (trans->cfg->gen2 && 3108520f03eaSShahar S Matityahu trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 31095538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 31105538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 31115538409bSLiad Kaufman dma_addr_t addr = 31125538409bSLiad Kaufman trans_pcie->init_dram.paging[i].physical; 31135538409bSLiad Kaufman u32 page_len = trans_pcie->init_dram.paging[i].size; 31145538409bSLiad Kaufman 31155538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 31165538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 31175538409bSLiad Kaufman paging = (void *)data->data; 31185538409bSLiad Kaufman paging->index = cpu_to_le32(i); 31195538409bSLiad Kaufman dma_sync_single_for_cpu(trans->dev, addr, page_len, 31205538409bSLiad Kaufman DMA_BIDIRECTIONAL); 31215538409bSLiad Kaufman memcpy(paging->data, 31225538409bSLiad Kaufman trans_pcie->init_dram.paging[i].block, page_len); 31235538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 31245538409bSLiad Kaufman 31255538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 31265538409bSLiad Kaufman } 31275538409bSLiad Kaufman } 3128520f03eaSShahar S Matityahu if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3129e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3130e705c121SKalle Valo 3131e705c121SKalle Valo dump_data->len = len; 3132e705c121SKalle Valo 3133e705c121SKalle Valo return dump_data; 3134e705c121SKalle Valo } 3135e705c121SKalle Valo 31364cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 31374cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 31384cbb8e50SLuciano Coelho { 3139e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3140e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 31414cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 31424cbb8e50SLuciano Coelho 31434cbb8e50SLuciano Coelho return 0; 31444cbb8e50SLuciano Coelho } 31454cbb8e50SLuciano Coelho 31464cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 31474cbb8e50SLuciano Coelho { 3148e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3149e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 31504cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 31514cbb8e50SLuciano Coelho } 31524cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 31534cbb8e50SLuciano Coelho 3154623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3155623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3156623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3157623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3158623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3159623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3160623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3161623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3162623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3163623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3164623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3165870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3166623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3167623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3168623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3169623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3170623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3171623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3172623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3173623e7766SSara Sharon .d3_resume = iwl_trans_pcie_d3_resume 3174623e7766SSara Sharon 3175623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3176623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3177623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3178623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3179623e7766SSara Sharon #else 3180623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3181623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3182623e7766SSara Sharon 3183e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3184623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3185623e7766SSara Sharon IWL_TRANS_PM_OPS 3186e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3187e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3188e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3189e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3190e705c121SKalle Valo 3191e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3192e705c121SKalle Valo 3193e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3194e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3195e705c121SKalle Valo 3196e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3197e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3198e705c121SKalle Valo 319942db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 320042db09c1SLiad Kaufman 3201d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3202d6d517b7SSara Sharon 3203e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 32040cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3205623e7766SSara Sharon }; 3206e705c121SKalle Valo 3207623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3208623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3209623e7766SSara Sharon IWL_TRANS_PM_OPS 3210623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3211eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3212eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 321377c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3214e705c121SKalle Valo 3215ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3216e705c121SKalle Valo 3217ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3218623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3219623e7766SSara Sharon 32206b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 32216b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3222d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 322392536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3224e705c121SKalle Valo }; 3225e705c121SKalle Valo 3226e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3227e705c121SKalle Valo const struct pci_device_id *ent, 3228e705c121SKalle Valo const struct iwl_cfg *cfg) 3229e705c121SKalle Valo { 3230e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3231e705c121SKalle Valo struct iwl_trans *trans; 323296a6497bSSara Sharon int ret, addr_size; 3233e705c121SKalle Valo 32345a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 32355a41a86cSSharon Dvir if (ret) 32365a41a86cSSharon Dvir return ERR_PTR(ret); 32375a41a86cSSharon Dvir 3238623e7766SSara Sharon if (cfg->gen2) 3239623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3240623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3241623e7766SSara Sharon else 3242e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 32431ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3244e705c121SKalle Valo if (!trans) 3245e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3246e705c121SKalle Valo 3247e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3248e705c121SKalle Valo 3249e705c121SKalle Valo trans_pcie->trans = trans; 3250326477e4SJohannes Berg trans_pcie->opmode_down = true; 3251e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3252e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3253e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3254e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 32556eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 32566eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 32576eb5e529SEmmanuel Grumbach ret = -ENOMEM; 32586eb5e529SEmmanuel Grumbach goto out_no_pci; 32596eb5e529SEmmanuel Grumbach } 3260e705c121SKalle Valo 3261e705c121SKalle Valo 3262e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3263e705c121SKalle Valo /* 3264e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3265e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3266e705c121SKalle Valo * lot of power. 3267e705c121SKalle Valo */ 3268e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3269e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3270e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3271e705c121SKalle Valo } 3272e705c121SKalle Valo 32739416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 32749416560eSGolan Ben Ami 32756983ba69SSara Sharon if (cfg->use_tfh) { 32762c6262b7SSara Sharon addr_size = 64; 32773cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 32788352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 32796983ba69SSara Sharon } else { 32802c6262b7SSara Sharon addr_size = 36; 32813cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 32826983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 32836983ba69SSara Sharon } 32843cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 32853cd1980bSSara Sharon 3286e705c121SKalle Valo pci_set_master(pdev); 3287e705c121SKalle Valo 328896a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3289e705c121SKalle Valo if (!ret) 329096a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 329196a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3292e705c121SKalle Valo if (ret) { 3293e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3294e705c121SKalle Valo if (!ret) 3295e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3296e705c121SKalle Valo DMA_BIT_MASK(32)); 3297e705c121SKalle Valo /* both attempts failed: */ 3298e705c121SKalle Valo if (ret) { 3299e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 33005a41a86cSSharon Dvir goto out_no_pci; 3301e705c121SKalle Valo } 3302e705c121SKalle Valo } 3303e705c121SKalle Valo 33045a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3305e705c121SKalle Valo if (ret) { 33065a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 33075a41a86cSSharon Dvir goto out_no_pci; 3308e705c121SKalle Valo } 3309e705c121SKalle Valo 33105a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3311e705c121SKalle Valo if (!trans_pcie->hw_base) { 33125a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3313e705c121SKalle Valo ret = -ENODEV; 33145a41a86cSSharon Dvir goto out_no_pci; 3315e705c121SKalle Valo } 3316e705c121SKalle Valo 3317e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3318e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3319e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3320e705c121SKalle Valo 3321e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3322e705c121SKalle Valo iwl_disable_interrupts(trans); 3323e705c121SKalle Valo 3324e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 33259a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 33269a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 33279a098a89SRajat Jain ret = -EIO; 33289a098a89SRajat Jain goto out_no_pci; 33299a098a89SRajat Jain } 33309a098a89SRajat Jain 3331e705c121SKalle Valo /* 3332e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3333e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3334e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3335e705c121SKalle Valo * in the old format. 3336e705c121SKalle Valo */ 33376e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3338e705c121SKalle Valo unsigned long flags; 3339e705c121SKalle Valo 3340e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3341e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3342e705c121SKalle Valo 3343e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3344e705c121SKalle Valo if (ret) { 3345e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 33465a41a86cSSharon Dvir goto out_no_pci; 3347e705c121SKalle Valo } 3348e705c121SKalle Valo 3349e705c121SKalle Valo /* 3350e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3351e705c121SKalle Valo * id located at the AUX bus MISC address space. 3352e705c121SKalle Valo */ 3353e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 3354a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_init_done)); 3355e705c121SKalle Valo udelay(2); 3356e705c121SKalle Valo 3357e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3358a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3359a8cbb46fSGolan Ben Ami BIT(trans->cfg->csr->flag_mac_clock_ready), 3360e705c121SKalle Valo 25000); 3361e705c121SKalle Valo if (ret < 0) { 3362e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 33635a41a86cSSharon Dvir goto out_no_pci; 3364e705c121SKalle Valo } 3365e705c121SKalle Valo 336623ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3367e705c121SKalle Valo u32 hw_step; 3368e705c121SKalle Valo 336914ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3370e705c121SKalle Valo hw_step |= ENABLE_WFPM; 337114ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 337214ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3373e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3374e705c121SKalle Valo if (hw_step == 0x3) 3375e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3376e705c121SKalle Valo (SILICON_C_STEP << 2); 3377e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3378e705c121SKalle Valo } 3379e705c121SKalle Valo } 3380e705c121SKalle Valo 3381c00ee467SJohannes Berg /* 3382c00ee467SJohannes Berg * 9000-series integrated A-step has a problem with suspend/resume 3383c00ee467SJohannes Berg * and sometimes even causes the whole platform to get stuck. This 3384c00ee467SJohannes Berg * workaround makes the hardware not go into the problematic state. 3385c00ee467SJohannes Berg */ 3386c00ee467SJohannes Berg if (trans->cfg->integrated && 3387c00ee467SJohannes Berg trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3388c00ee467SJohannes Berg CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3389c00ee467SJohannes Berg iwl_set_bit(trans, CSR_HOST_CHICKEN, 3390c00ee467SJohannes Berg CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3391c00ee467SJohannes Berg 3392f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 33931afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 339433708052SLuca Coelho 339533708052SLuca Coelho if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) == 339633708052SLuca Coelho CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) { 3397f6586b69STzipi Peres u32 hw_status; 3398f6586b69STzipi Peres 3399f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 340033708052SLuca Coelho if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP) 340133708052SLuca Coelho /* 340233708052SLuca Coelho * b step fw is the same for physical card and fpga 340333708052SLuca Coelho */ 340433708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0; 340533708052SLuca Coelho else if ((hw_status & UMAG_GEN_HW_IS_FPGA) && 340633708052SLuca Coelho CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) { 340733708052SLuca Coelho trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0; 340833708052SLuca Coelho } else { 340933708052SLuca Coelho /* 341033708052SLuca Coelho * a step no FPGA 341133708052SLuca Coelho */ 34122f7a3863SLuca Coelho trans->cfg = &iwl22000_2ac_cfg_hr; 3413f6586b69STzipi Peres } 341433708052SLuca Coelho } 3415f6586b69STzipi Peres #endif 34161afb0ae4SHaim Dreyfuss 34172e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3418e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3419e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3420e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3421e705c121SKalle Valo 3422e705c121SKalle Valo /* Initialize the wait queue for commands */ 3423e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3424e705c121SKalle Valo 34254cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 34264cbb8e50SLuciano Coelho 34272e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 34282388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 34292388bd7bSDan Carpenter if (ret) 34305a41a86cSSharon Dvir goto out_no_pci; 34312e5d4a8fSHaim Dreyfuss } else { 3432e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3433e705c121SKalle Valo if (ret) 34345a41a86cSSharon Dvir goto out_no_pci; 3435e705c121SKalle Valo 34365a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 34375a41a86cSSharon Dvir iwl_pcie_isr, 3438e705c121SKalle Valo iwl_pcie_irq_handler, 3439e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3440e705c121SKalle Valo if (ret) { 3441e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3442e705c121SKalle Valo goto out_free_ict; 3443e705c121SKalle Valo } 3444e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 34452e5d4a8fSHaim Dreyfuss } 3446e705c121SKalle Valo 344710a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 344810a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 344910a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 345010a54d81SLuca Coelho 3451b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3452b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3453b3ff1270SLuca Coelho #else 3454b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3455b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3456b3ff1270SLuca Coelho 3457e705c121SKalle Valo return trans; 3458e705c121SKalle Valo 3459e705c121SKalle Valo out_free_ict: 3460e705c121SKalle Valo iwl_pcie_free_ict(trans); 3461e705c121SKalle Valo out_no_pci: 34626eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3463e705c121SKalle Valo iwl_trans_free(trans); 3464e705c121SKalle Valo return ERR_PTR(ret); 3465e705c121SKalle Valo } 3466