18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 38e99ea8dSJohannes Berg * Copyright (C) 2007-2015, 2018-2020 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 27e705c121SKalle Valo #include "internal.h" 28e705c121SKalle Valo #include "iwl-fh.h" 296654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 30e705c121SKalle Valo 31e705c121SKalle Valo /* extended range in FW SRAM */ 32e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 34e705c121SKalle Valo 354290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 36a6d24fadSRajat Jain { 37c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 38c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 39c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 40a6d24fadSRajat Jain #define PREFIX_LEN 32 41a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 42a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 43a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 44a6d24fadSRajat Jain char *prefix; 45a6d24fadSRajat Jain 46a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 47a6d24fadSRajat Jain return; 48a6d24fadSRajat Jain 49a6d24fadSRajat Jain /* Should be a multiple of 4 */ 50a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 51c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho 54a6d24fadSRajat Jain /* Alloc a max size buffer */ 55a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 56c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho 60a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 61a6d24fadSRajat Jain if (!buf) 62a6d24fadSRajat Jain return; 63a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 64a6d24fadSRajat Jain 65a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 66a6d24fadSRajat Jain 67a6d24fadSRajat Jain /* Print wifi device registers */ 68a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 69a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 70a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 71a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 72a6d24fadSRajat Jain goto err_read; 73a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 74a6d24fadSRajat Jain 75a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 76c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 77a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 78a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79a6d24fadSRajat Jain 80a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 81a6d24fadSRajat Jain if (pos) { 82a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 83a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 84a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 85a6d24fadSRajat Jain goto err_read; 86a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 87a6d24fadSRajat Jain 32, 4, buf, i, 0); 88a6d24fadSRajat Jain } 89a6d24fadSRajat Jain 90a6d24fadSRajat Jain /* Print parent device registers next */ 91a6d24fadSRajat Jain if (!pdev->bus->self) 92a6d24fadSRajat Jain goto out; 93a6d24fadSRajat Jain 94a6d24fadSRajat Jain pdev = pdev->bus->self; 95a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 96a6d24fadSRajat Jain 97a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 98a6d24fadSRajat Jain pci_name(pdev)); 99c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 100a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 101a6d24fadSRajat Jain goto err_read; 102a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Print root port AER registers */ 105a6d24fadSRajat Jain pos = 0; 106a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 107a6d24fadSRajat Jain if (pdev) 108a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 109a6d24fadSRajat Jain if (pos) { 110a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 111a6d24fadSRajat Jain pci_name(pdev)); 112a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 113a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 114a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 115a6d24fadSRajat Jain goto err_read; 116a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 117a6d24fadSRajat Jain 4, buf, i, 0); 118a6d24fadSRajat Jain } 119f3402d6dSSara Sharon goto out; 120a6d24fadSRajat Jain 121a6d24fadSRajat Jain err_read: 122a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 123a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 124a6d24fadSRajat Jain out: 125a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 126a6d24fadSRajat Jain kfree(buf); 127a6d24fadSRajat Jain } 128a6d24fadSRajat Jain 129870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 130870c2a11SGolan Ben Ami { 131870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1321b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1331b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_GP_CNTRL, 1341b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_SW_RESET); 1351b6598c3SRoee Goldfiner else 1361b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_RESET, 1371b6598c3SRoee Goldfiner CSR_RESET_REG_FLAG_SW_RESET); 138870c2a11SGolan Ben Ami usleep_range(5000, 6000); 139870c2a11SGolan Ben Ami } 140870c2a11SGolan Ben Ami 141e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 142e705c121SKalle Valo { 14369f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 144e705c121SKalle Valo 14569f0e505SShahar S Matityahu if (!fw_mon->size) 14669f0e505SShahar S Matityahu return; 14769f0e505SShahar S Matityahu 14869f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 14969f0e505SShahar S Matityahu fw_mon->physical); 15069f0e505SShahar S Matityahu 15169f0e505SShahar S Matityahu fw_mon->block = NULL; 15269f0e505SShahar S Matityahu fw_mon->physical = 0; 15369f0e505SShahar S Matityahu fw_mon->size = 0; 154e705c121SKalle Valo } 155e705c121SKalle Valo 15688964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 15788964b2eSSara Sharon u8 max_power, u8 min_power) 158e705c121SKalle Valo { 15969f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 16069f0e505SShahar S Matityahu void *block = NULL; 16169f0e505SShahar S Matityahu dma_addr_t physical = 0; 162e705c121SKalle Valo u32 size = 0; 163e705c121SKalle Valo u8 power; 164e705c121SKalle Valo 16569f0e505SShahar S Matityahu if (fw_mon->size) 16669f0e505SShahar S Matityahu return; 16769f0e505SShahar S Matityahu 16888964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 169e705c121SKalle Valo size = BIT(power); 17069f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1712d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 17269f0e505SShahar S Matityahu if (!block) 173e705c121SKalle Valo continue; 174e705c121SKalle Valo 175e705c121SKalle Valo IWL_INFO(trans, 176c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 177c5f97542SShahar S Matityahu size); 178e705c121SKalle Valo break; 179e705c121SKalle Valo } 180e705c121SKalle Valo 18169f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 182e705c121SKalle Valo return; 183e705c121SKalle Valo 184e705c121SKalle Valo if (power != max_power) 185e705c121SKalle Valo IWL_ERR(trans, 186e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 187e705c121SKalle Valo (unsigned long)BIT(power - 10), 188e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 189e705c121SKalle Valo 19069f0e505SShahar S Matityahu fw_mon->block = block; 19169f0e505SShahar S Matityahu fw_mon->physical = physical; 19269f0e505SShahar S Matityahu fw_mon->size = size; 19388964b2eSSara Sharon } 19488964b2eSSara Sharon 19588964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 19688964b2eSSara Sharon { 19788964b2eSSara Sharon if (!max_power) { 19888964b2eSSara Sharon /* default max_power is maximum */ 19988964b2eSSara Sharon max_power = 26; 20088964b2eSSara Sharon } else { 20188964b2eSSara Sharon max_power += 11; 20288964b2eSSara Sharon } 20388964b2eSSara Sharon 20488964b2eSSara Sharon if (WARN(max_power > 26, 20588964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 20688964b2eSSara Sharon max_power)) 20788964b2eSSara Sharon return; 20888964b2eSSara Sharon 20969f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 21088964b2eSSara Sharon return; 21188964b2eSSara Sharon 21288964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 213e705c121SKalle Valo } 214e705c121SKalle Valo 215e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 216e705c121SKalle Valo { 217e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 218e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 219e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 220e705c121SKalle Valo } 221e705c121SKalle Valo 222e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 223e705c121SKalle Valo { 224e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 225e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 226e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 227e705c121SKalle Valo } 228e705c121SKalle Valo 229e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 230e705c121SKalle Valo { 231e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 232e705c121SKalle Valo return; 233e705c121SKalle Valo 234e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 235e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 236e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 237e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 238e705c121SKalle Valo else 239e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 240e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 241e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 242e705c121SKalle Valo } 243e705c121SKalle Valo 244e705c121SKalle Valo /* PCI registers */ 245e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 246e705c121SKalle Valo 247eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 248e705c121SKalle Valo { 249e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 250e705c121SKalle Valo u16 lctl; 251e705c121SKalle Valo u16 cap; 252e705c121SKalle Valo 253e705c121SKalle Valo /* 254cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 255cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 256cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 257e705c121SKalle Valo */ 2583d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 259cc894b85SLuca Coelho 260cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 261e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 262e705c121SKalle Valo 263e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 264e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 265d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 266e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 267e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 268e705c121SKalle Valo } 269e705c121SKalle Valo 270e705c121SKalle Valo /* 271e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 272e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 273e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 274e705c121SKalle Valo */ 275e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 276e705c121SKalle Valo { 27752b6e168SEmmanuel Grumbach int ret; 27852b6e168SEmmanuel Grumbach 279e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 280e705c121SKalle Valo 281e705c121SKalle Valo /* 282e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 283e705c121SKalle Valo * bits already set by default after reset. 284e705c121SKalle Valo */ 285e705c121SKalle Valo 286e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 287286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 288e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 289e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 290e705c121SKalle Valo 291e705c121SKalle Valo /* 292e705c121SKalle Valo * Disable L0s without affecting L1; 293e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 294e705c121SKalle Valo */ 295e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 296e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 297e705c121SKalle Valo 298e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 299e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 300e705c121SKalle Valo 301e705c121SKalle Valo /* 302e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 303e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 304e705c121SKalle Valo */ 305e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 306e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 307e705c121SKalle Valo 308e705c121SKalle Valo iwl_pcie_apm_config(trans); 309e705c121SKalle Valo 310e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 311286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 31277d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 313e705c121SKalle Valo 314425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 315c96b5eecSJohannes Berg if (ret) 31652b6e168SEmmanuel Grumbach return ret; 317e705c121SKalle Valo 318e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 319e705c121SKalle Valo /* 320e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 321e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 322e705c121SKalle Valo * not related to host_interrupt_operation_mode. 323e705c121SKalle Valo * 324e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 325e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 326e705c121SKalle Valo * that we wake up from L1 on time. 327e705c121SKalle Valo * 328e705c121SKalle Valo * This looks weird: read twice the same register, discard the 329e705c121SKalle Valo * value, set a bit, and yet again, read that same register 330e705c121SKalle Valo * just to discard the value. But that's the way the hardware 331e705c121SKalle Valo * seems to like it. 332e705c121SKalle Valo */ 333e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 334e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 335e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 336e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 337e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 338e705c121SKalle Valo } 339e705c121SKalle Valo 340e705c121SKalle Valo /* 341e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 342e705c121SKalle Valo * 343e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 344e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 345e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 346e705c121SKalle Valo */ 347e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 348e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 349e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 350e705c121SKalle Valo udelay(20); 351e705c121SKalle Valo 352e705c121SKalle Valo /* Disable L1-Active */ 353e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 354e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 355e705c121SKalle Valo 356e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 357e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 358e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 359e705c121SKalle Valo } 360e705c121SKalle Valo 361e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 362e705c121SKalle Valo 36352b6e168SEmmanuel Grumbach return 0; 364e705c121SKalle Valo } 365e705c121SKalle Valo 366e705c121SKalle Valo /* 367e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 368e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 369e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 370e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 371e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 372e705c121SKalle Valo */ 373e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 374e705c121SKalle Valo { 375e705c121SKalle Valo int ret; 376e705c121SKalle Valo u32 apmg_gp1_reg; 377e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 378e705c121SKalle Valo u32 dl_cfg_reg; 379e705c121SKalle Valo 380e705c121SKalle Valo /* Force XTAL ON */ 381e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 382e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 383e705c121SKalle Valo 384870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 385e705c121SKalle Valo 386425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 387c96b5eecSJohannes Berg if (WARN_ON(ret)) { 388e705c121SKalle Valo /* Release XTAL ON request */ 389e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 390e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 391e705c121SKalle Valo return; 392e705c121SKalle Valo } 393e705c121SKalle Valo 394e705c121SKalle Valo /* 395e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 396e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 397e705c121SKalle Valo */ 398e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 399e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 400e705c121SKalle Valo 401e705c121SKalle Valo /* 402e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 403e705c121SKalle Valo * caused by APMG idle state. 404e705c121SKalle Valo */ 405e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 406e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 407e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 408e705c121SKalle Valo apmg_xtal_cfg_reg | 409e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 410e705c121SKalle Valo 411870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 412e705c121SKalle Valo 413e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 414e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 415e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 416e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 417e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 418e705c121SKalle Valo 419e705c121SKalle Valo /* Clear delay line clock power up */ 420e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 421e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 422e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 423e705c121SKalle Valo 424e705c121SKalle Valo /* 425e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 426e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 427e705c121SKalle Valo */ 428e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 429e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 430e705c121SKalle Valo 431e705c121SKalle Valo /* 432e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 433e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 434e705c121SKalle Valo */ 4356dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 436e705c121SKalle Valo 437e705c121SKalle Valo /* Activates XTAL resources monitor */ 438e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 439e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 440e705c121SKalle Valo 441e705c121SKalle Valo /* Release XTAL ON request */ 442e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 443e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 444e705c121SKalle Valo udelay(10); 445e705c121SKalle Valo 446e705c121SKalle Valo /* Release APMG XTAL */ 447e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 448e705c121SKalle Valo apmg_xtal_cfg_reg & 449e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 450e705c121SKalle Valo } 451e705c121SKalle Valo 452e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 453e705c121SKalle Valo { 454e8c8935eSJohannes Berg int ret; 455e705c121SKalle Valo 456e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4579ce041f5SJohannes Berg 4589ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4599ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4609ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4619ce041f5SJohannes Berg 4629ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4639ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4649ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4659ce041f5SJohannes Berg 100); 46644b2dd40SRoee Goldfiner msleep(100); 4679ce041f5SJohannes Berg } else { 4686dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 469e705c121SKalle Valo 4706dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4716dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4726dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4739ce041f5SJohannes Berg } 4749ce041f5SJohannes Berg 475e705c121SKalle Valo if (ret < 0) 476e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 477e705c121SKalle Valo 478e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 479e705c121SKalle Valo } 480e705c121SKalle Valo 481e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 482e705c121SKalle Valo { 483e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 484e705c121SKalle Valo 485e705c121SKalle Valo if (op_mode_leave) { 486e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 487e705c121SKalle Valo iwl_pcie_apm_init(trans); 488e705c121SKalle Valo 489e705c121SKalle Valo /* inform ME that we are leaving */ 490286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 491e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 492e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 493286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 49479b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 495e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 496e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 497e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 498e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 499e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 500e705c121SKalle Valo mdelay(1); 501e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 502e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 503e705c121SKalle Valo } 504e705c121SKalle Valo mdelay(5); 505e705c121SKalle Valo } 506e705c121SKalle Valo 507e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 508e705c121SKalle Valo 509e705c121SKalle Valo /* Stop device's DMA activity */ 510e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 511e705c121SKalle Valo 512e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 513e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 514e705c121SKalle Valo return; 515e705c121SKalle Valo } 516e705c121SKalle Valo 517870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 518e705c121SKalle Valo 519e705c121SKalle Valo /* 520e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 521e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 522e705c121SKalle Valo */ 5236dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 524e705c121SKalle Valo } 525e705c121SKalle Valo 526e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 527e705c121SKalle Valo { 528e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 52952b6e168SEmmanuel Grumbach int ret; 530e705c121SKalle Valo 531e705c121SKalle Valo /* nic_init */ 53225edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 53352b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 53425edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 535e705c121SKalle Valo 53652b6e168SEmmanuel Grumbach if (ret) 53752b6e168SEmmanuel Grumbach return ret; 53852b6e168SEmmanuel Grumbach 539e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 540e705c121SKalle Valo 541e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 542e705c121SKalle Valo 543e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5449cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5459cf671d6SEmmanuel Grumbach if (ret) 5469cf671d6SEmmanuel Grumbach return ret; 547e705c121SKalle Valo 548e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5499cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5509cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 551e705c121SKalle Valo return -ENOMEM; 5529cf671d6SEmmanuel Grumbach } 553e705c121SKalle Valo 554286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 555e705c121SKalle Valo /* enable shadow regs in HW */ 556e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 557e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 558e705c121SKalle Valo } 559e705c121SKalle Valo 560e705c121SKalle Valo return 0; 561e705c121SKalle Valo } 562e705c121SKalle Valo 563e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 564e705c121SKalle Valo 565e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 566e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 567e705c121SKalle Valo { 568e705c121SKalle Valo int ret; 569e705c121SKalle Valo 570e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 571e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 572e705c121SKalle Valo 573e705c121SKalle Valo /* See if we got it */ 574e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 575e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 576e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 577e705c121SKalle Valo HW_READY_TIMEOUT); 578e705c121SKalle Valo 579e705c121SKalle Valo if (ret >= 0) 580e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 581e705c121SKalle Valo 582e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 583e705c121SKalle Valo return ret; 584e705c121SKalle Valo } 585e705c121SKalle Valo 586e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 587eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 588e705c121SKalle Valo { 589e705c121SKalle Valo int ret; 590e705c121SKalle Valo int t = 0; 591e705c121SKalle Valo int iter; 592e705c121SKalle Valo 593e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 594e705c121SKalle Valo 595e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 596e705c121SKalle Valo /* If the card is ready, exit 0 */ 597e705c121SKalle Valo if (ret >= 0) 598e705c121SKalle Valo return 0; 599e705c121SKalle Valo 600e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 601e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 602192185d6SJohannes Berg usleep_range(1000, 2000); 603e705c121SKalle Valo 604e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 605e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 606e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 607e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 608e705c121SKalle Valo 609e705c121SKalle Valo do { 610e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 611e705c121SKalle Valo if (ret >= 0) 612e705c121SKalle Valo return 0; 613e705c121SKalle Valo 614e705c121SKalle Valo usleep_range(200, 1000); 615e705c121SKalle Valo t += 200; 616e705c121SKalle Valo } while (t < 150000); 617e705c121SKalle Valo msleep(25); 618e705c121SKalle Valo } 619e705c121SKalle Valo 620e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 621e705c121SKalle Valo 622e705c121SKalle Valo return ret; 623e705c121SKalle Valo } 624e705c121SKalle Valo 625e705c121SKalle Valo /* 626e705c121SKalle Valo * ucode 627e705c121SKalle Valo */ 628564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 629564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 630564cdce7SSara Sharon u32 byte_cnt) 631e705c121SKalle Valo { 632bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 633e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 634e705c121SKalle Valo 635bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 636e705c121SKalle Valo dst_addr); 637e705c121SKalle Valo 638bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 639e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 640e705c121SKalle Valo 641bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 642e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 643e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 644e705c121SKalle Valo 645bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 646bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 647bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 648e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 649e705c121SKalle Valo 650bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 651e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 652e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 653e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 654564cdce7SSara Sharon } 655e705c121SKalle Valo 656564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 657564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 658564cdce7SSara Sharon u32 byte_cnt) 659564cdce7SSara Sharon { 660564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 661564cdce7SSara Sharon int ret; 662564cdce7SSara Sharon 663564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 664564cdce7SSara Sharon 6651ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 666564cdce7SSara Sharon return -EIO; 667564cdce7SSara Sharon 668564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 669564cdce7SSara Sharon byte_cnt); 6701ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 671bac842daSEmmanuel Grumbach 672e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 673e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 674e705c121SKalle Valo if (!ret) { 675e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 676fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 677e705c121SKalle Valo return -ETIMEDOUT; 678e705c121SKalle Valo } 679e705c121SKalle Valo 680e705c121SKalle Valo return 0; 681e705c121SKalle Valo } 682e705c121SKalle Valo 683e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 684e705c121SKalle Valo const struct fw_desc *section) 685e705c121SKalle Valo { 686e705c121SKalle Valo u8 *v_addr; 687e705c121SKalle Valo dma_addr_t p_addr; 688e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 689e705c121SKalle Valo int ret = 0; 690e705c121SKalle Valo 691e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 692e705c121SKalle Valo section_num); 693e705c121SKalle Valo 694e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 695e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 696e705c121SKalle Valo if (!v_addr) { 697e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 698e705c121SKalle Valo chunk_sz = PAGE_SIZE; 699e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 700e705c121SKalle Valo &p_addr, GFP_KERNEL); 701e705c121SKalle Valo if (!v_addr) 702e705c121SKalle Valo return -ENOMEM; 703e705c121SKalle Valo } 704e705c121SKalle Valo 705e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 706e705c121SKalle Valo u32 copy_size, dst_addr; 707e705c121SKalle Valo bool extended_addr = false; 708e705c121SKalle Valo 709e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 710e705c121SKalle Valo dst_addr = section->offset + offset; 711e705c121SKalle Valo 712e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 713e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 714e705c121SKalle Valo extended_addr = true; 715e705c121SKalle Valo 716e705c121SKalle Valo if (extended_addr) 717e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 718e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 719e705c121SKalle Valo 720e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 721e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 722e705c121SKalle Valo copy_size); 723e705c121SKalle Valo 724e705c121SKalle Valo if (extended_addr) 725e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 726e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 727e705c121SKalle Valo 728e705c121SKalle Valo if (ret) { 729e705c121SKalle Valo IWL_ERR(trans, 730e705c121SKalle Valo "Could not load the [%d] uCode section\n", 731e705c121SKalle Valo section_num); 732e705c121SKalle Valo break; 733e705c121SKalle Valo } 734e705c121SKalle Valo } 735e705c121SKalle Valo 736e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 737e705c121SKalle Valo return ret; 738e705c121SKalle Valo } 739e705c121SKalle Valo 740e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 741e705c121SKalle Valo const struct fw_img *image, 742e705c121SKalle Valo int cpu, 743e705c121SKalle Valo int *first_ucode_section) 744e705c121SKalle Valo { 745e705c121SKalle Valo int shift_param; 746e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 747e705c121SKalle Valo u32 val, last_read_idx = 0; 748e705c121SKalle Valo 749e705c121SKalle Valo if (cpu == 1) { 750e705c121SKalle Valo shift_param = 0; 751e705c121SKalle Valo *first_ucode_section = 0; 752e705c121SKalle Valo } else { 753e705c121SKalle Valo shift_param = 16; 754e705c121SKalle Valo (*first_ucode_section)++; 755e705c121SKalle Valo } 756e705c121SKalle Valo 757eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 758e705c121SKalle Valo last_read_idx = i; 759e705c121SKalle Valo 760e705c121SKalle Valo /* 761e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 762e705c121SKalle Valo * CPU1 to CPU2. 763e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 764e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 765e705c121SKalle Valo */ 766e705c121SKalle Valo if (!image->sec[i].data || 767e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 768e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 769e705c121SKalle Valo IWL_DEBUG_FW(trans, 770e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 771e705c121SKalle Valo i); 772e705c121SKalle Valo break; 773e705c121SKalle Valo } 774e705c121SKalle Valo 775e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 776e705c121SKalle Valo if (ret) 777e705c121SKalle Valo return ret; 778e705c121SKalle Valo 779d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 780e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 781e705c121SKalle Valo val = val | (sec_num << shift_param); 782e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 783eda50cdeSSara Sharon 784e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 785e705c121SKalle Valo } 786e705c121SKalle Valo 787e705c121SKalle Valo *first_ucode_section = last_read_idx; 788e705c121SKalle Valo 7892aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 7902aabdbdcSEmmanuel Grumbach 791286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 792e705c121SKalle Valo if (cpu == 1) 793d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 794d6a2c5c7SSara Sharon 0xFFFF); 795e705c121SKalle Valo else 796d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 797d6a2c5c7SSara Sharon 0xFFFFFFFF); 798d6a2c5c7SSara Sharon } else { 799d6a2c5c7SSara Sharon if (cpu == 1) 800d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 801d6a2c5c7SSara Sharon 0xFFFF); 802d6a2c5c7SSara Sharon else 803d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 804d6a2c5c7SSara Sharon 0xFFFFFFFF); 805d6a2c5c7SSara Sharon } 806e705c121SKalle Valo 807e705c121SKalle Valo return 0; 808e705c121SKalle Valo } 809e705c121SKalle Valo 810e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 811e705c121SKalle Valo const struct fw_img *image, 812e705c121SKalle Valo int cpu, 813e705c121SKalle Valo int *first_ucode_section) 814e705c121SKalle Valo { 815e705c121SKalle Valo int i, ret = 0; 816e705c121SKalle Valo u32 last_read_idx = 0; 817e705c121SKalle Valo 8183ce4a038SKirtika Ruchandani if (cpu == 1) 819e705c121SKalle Valo *first_ucode_section = 0; 8203ce4a038SKirtika Ruchandani else 821e705c121SKalle Valo (*first_ucode_section)++; 822e705c121SKalle Valo 823eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 824e705c121SKalle Valo last_read_idx = i; 825e705c121SKalle Valo 826e705c121SKalle Valo /* 827e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 828e705c121SKalle Valo * CPU1 to CPU2. 829e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 830e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 831e705c121SKalle Valo */ 832e705c121SKalle Valo if (!image->sec[i].data || 833e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 834e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 835e705c121SKalle Valo IWL_DEBUG_FW(trans, 836e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 837e705c121SKalle Valo i); 838e705c121SKalle Valo break; 839e705c121SKalle Valo } 840e705c121SKalle Valo 841e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 842e705c121SKalle Valo if (ret) 843e705c121SKalle Valo return ret; 844e705c121SKalle Valo } 845e705c121SKalle Valo 846e705c121SKalle Valo *first_ucode_section = last_read_idx; 847e705c121SKalle Valo 848e705c121SKalle Valo return 0; 849e705c121SKalle Valo } 850e705c121SKalle Valo 851593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 852593fae3eSShahar S Matityahu { 853593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 854593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 855593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 856593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 857593fae3eSShahar S Matityahu 858593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 859593fae3eSShahar S Matityahu return; 860593fae3eSShahar S Matityahu 861593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 862593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 863593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 864593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 865593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 866593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 867593fae3eSShahar S Matityahu 868593fae3eSShahar S Matityahu return; 869593fae3eSShahar S Matityahu } 870593fae3eSShahar S Matityahu 871593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 872593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 873593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 874593fae3eSShahar S Matityahu return; 875593fae3eSShahar S Matityahu 876593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 877593fae3eSShahar S Matityahu 878593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 879593fae3eSShahar S Matityahu alloc_id); 880593fae3eSShahar S Matityahu 881593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 882593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 883593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 884593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 885593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 886593fae3eSShahar S Matityahu } 887593fae3eSShahar S Matityahu 888c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 889e705c121SKalle Valo { 89091c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 89169f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 892e705c121SKalle Valo int i; 893e705c121SKalle Valo 894a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 895593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 8967a14c23dSSara Sharon return; 8977a14c23dSSara Sharon } 8987a14c23dSSara Sharon 899e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 900e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 901e705c121SKalle Valo 902e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 903e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 904e705c121SKalle Valo else 905e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 906e705c121SKalle Valo 90791c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 908e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 909e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 910e705c121SKalle Valo 911e705c121SKalle Valo switch (dest->reg_ops[i].op) { 912e705c121SKalle Valo case CSR_ASSIGN: 913e705c121SKalle Valo iwl_write32(trans, addr, val); 914e705c121SKalle Valo break; 915e705c121SKalle Valo case CSR_SETBIT: 916e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 917e705c121SKalle Valo break; 918e705c121SKalle Valo case CSR_CLEARBIT: 919e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 920e705c121SKalle Valo break; 921e705c121SKalle Valo case PRPH_ASSIGN: 922e705c121SKalle Valo iwl_write_prph(trans, addr, val); 923e705c121SKalle Valo break; 924e705c121SKalle Valo case PRPH_SETBIT: 925e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 926e705c121SKalle Valo break; 927e705c121SKalle Valo case PRPH_CLEARBIT: 928e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 929e705c121SKalle Valo break; 930e705c121SKalle Valo case PRPH_BLOCKBIT: 931e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 932e705c121SKalle Valo IWL_ERR(trans, 933e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 934e705c121SKalle Valo val, addr); 935e705c121SKalle Valo goto monitor; 936e705c121SKalle Valo } 937e705c121SKalle Valo break; 938e705c121SKalle Valo default: 939e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 940e705c121SKalle Valo dest->reg_ops[i].op); 941e705c121SKalle Valo break; 942e705c121SKalle Valo } 943e705c121SKalle Valo } 944e705c121SKalle Valo 945e705c121SKalle Valo monitor: 94669f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 947e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 94869f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 949286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 950e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 95169f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 95269f0e505SShahar S Matityahu 256) >> dest->end_shift); 95362d7476dSEmmanuel Grumbach else 95462d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 95569f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 95662d7476dSEmmanuel Grumbach dest->end_shift); 957e705c121SKalle Valo } 958e705c121SKalle Valo } 959e705c121SKalle Valo 960e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 961e705c121SKalle Valo const struct fw_img *image) 962e705c121SKalle Valo { 963e705c121SKalle Valo int ret = 0; 964e705c121SKalle Valo int first_ucode_section; 965e705c121SKalle Valo 966e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 967e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 968e705c121SKalle Valo 969e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 970e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 971e705c121SKalle Valo if (ret) 972e705c121SKalle Valo return ret; 973e705c121SKalle Valo 974e705c121SKalle Valo if (image->is_dual_cpus) { 975e705c121SKalle Valo /* set CPU2 header address */ 976e705c121SKalle Valo iwl_write_prph(trans, 977e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 978e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 979e705c121SKalle Valo 980e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 981e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 982e705c121SKalle Valo &first_ucode_section); 983e705c121SKalle Valo if (ret) 984e705c121SKalle Valo return ret; 985e705c121SKalle Valo } 986e705c121SKalle Valo 9879efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 988e705c121SKalle Valo iwl_pcie_apply_destination(trans); 989e705c121SKalle Valo 9902aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 9912aabdbdcSEmmanuel Grumbach 992e705c121SKalle Valo /* release CPU reset */ 993e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 994e705c121SKalle Valo 995e705c121SKalle Valo return 0; 996e705c121SKalle Valo } 997e705c121SKalle Valo 998e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 999e705c121SKalle Valo const struct fw_img *image) 1000e705c121SKalle Valo { 1001e705c121SKalle Valo int ret = 0; 1002e705c121SKalle Valo int first_ucode_section; 1003e705c121SKalle Valo 1004e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1005e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1006e705c121SKalle Valo 10077a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1008e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1009e705c121SKalle Valo 101082ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 101182ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 101282ea7966SSara Sharon 101382ea7966SSara Sharon /* 101482ea7966SSara Sharon * Set default value. On resume reading the values that were 101582ea7966SSara Sharon * zeored can provide debug data on the resume flow. 101682ea7966SSara Sharon * This is for debugging only and has no functional impact. 101782ea7966SSara Sharon */ 101882ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 101982ea7966SSara Sharon 1020e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1021e705c121SKalle Valo /* release CPU reset */ 1022e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1023e705c121SKalle Valo 1024e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1025e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1026e705c121SKalle Valo &first_ucode_section); 1027e705c121SKalle Valo if (ret) 1028e705c121SKalle Valo return ret; 1029e705c121SKalle Valo 1030e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1031e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1032e705c121SKalle Valo &first_ucode_section); 1033e705c121SKalle Valo } 1034e705c121SKalle Valo 10359ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1036727c02dfSSara Sharon { 1037326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1038727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1039326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1040326477e4SJohannes Berg bool report; 1041727c02dfSSara Sharon 1042326477e4SJohannes Berg if (hw_rfkill) { 1043326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1044326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1045326477e4SJohannes Berg } else { 1046326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1047326477e4SJohannes Berg if (trans_pcie->opmode_down) 1048326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1049326477e4SJohannes Berg } 1050727c02dfSSara Sharon 1051326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1052326477e4SJohannes Berg 1053326477e4SJohannes Berg if (prev != report) 1054326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1055727c02dfSSara Sharon 1056727c02dfSSara Sharon return hw_rfkill; 1057727c02dfSSara Sharon } 1058727c02dfSSara Sharon 10597ca00409SHaim Dreyfuss struct iwl_causes_list { 10607ca00409SHaim Dreyfuss u32 cause_num; 10617ca00409SHaim Dreyfuss u32 mask_reg; 10627ca00409SHaim Dreyfuss u8 addr; 10637ca00409SHaim Dreyfuss }; 10647ca00409SHaim Dreyfuss 1065*571836a0SMike Golant static const struct iwl_causes_list causes_list_common[] = { 10667ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 10677ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 10687ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 10697ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 10707ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 10717ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1072906d4eb8SJohannes Berg {MSIX_HW_INT_CAUSES_REG_RESET_DONE, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 10737ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 10747ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 10757ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 10767ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 10777ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 10787ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 10797ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 10807ca00409SHaim Dreyfuss }; 10817ca00409SHaim Dreyfuss 1082*571836a0SMike Golant static const struct iwl_causes_list causes_list_pre_bz[] = { 1083*571836a0SMike Golant {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1084*571836a0SMike Golant }; 10857ca00409SHaim Dreyfuss 1086*571836a0SMike Golant static const struct iwl_causes_list causes_list_bz[] = { 1087*571836a0SMike Golant {MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 1088*571836a0SMike Golant }; 1089*571836a0SMike Golant 1090*571836a0SMike Golant static void iwl_pcie_map_list(struct iwl_trans *trans, 1091*571836a0SMike Golant const struct iwl_causes_list *causes, 1092*571836a0SMike Golant int arr_size, int val) 1093*571836a0SMike Golant { 1094*571836a0SMike Golant int i; 1095*571836a0SMike Golant 10969b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 10979b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 10989b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 10999b58419eSGolan Ben Ami causes[i].cause_num); 11007ca00409SHaim Dreyfuss } 11017ca00409SHaim Dreyfuss } 11027ca00409SHaim Dreyfuss 1103*571836a0SMike Golant static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1104*571836a0SMike Golant { 1105*571836a0SMike Golant struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1106*571836a0SMike Golant int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1107*571836a0SMike Golant /* 1108*571836a0SMike Golant * Access all non RX causes and map them to the default irq. 1109*571836a0SMike Golant * In case we are missing at least one interrupt vector, 1110*571836a0SMike Golant * the first interrupt vector will serve non-RX and FBQ causes. 1111*571836a0SMike Golant */ 1112*571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_common, 1113*571836a0SMike Golant ARRAY_SIZE(causes_list_common), val); 1114*571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1115*571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_bz, 1116*571836a0SMike Golant ARRAY_SIZE(causes_list_bz), val); 1117*571836a0SMike Golant else 1118*571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_pre_bz, 1119*571836a0SMike Golant ARRAY_SIZE(causes_list_pre_bz), val); 1120*571836a0SMike Golant } 1121*571836a0SMike Golant 11227ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11237ca00409SHaim Dreyfuss { 11247ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11257ca00409SHaim Dreyfuss u32 offset = 11267ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11277ca00409SHaim Dreyfuss u32 val, idx; 11287ca00409SHaim Dreyfuss 11297ca00409SHaim Dreyfuss /* 11307ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11317ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11327ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11337ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11347ca00409SHaim Dreyfuss */ 11357ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11367ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11377ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11387ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11397ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11407ca00409SHaim Dreyfuss } 11417ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11427ca00409SHaim Dreyfuss 11437ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11447ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11457ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11467ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11477ca00409SHaim Dreyfuss 11487ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11497ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11507ca00409SHaim Dreyfuss } 11517ca00409SHaim Dreyfuss 115277c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11537ca00409SHaim Dreyfuss { 11547ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11557ca00409SHaim Dreyfuss 11567ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1157286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1158d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1159ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11607ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11617ca00409SHaim Dreyfuss return; 11627ca00409SHaim Dreyfuss } 1163d7270d61SHaim Dreyfuss /* 1164d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1165d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1166d7270d61SHaim Dreyfuss * prph. 1167d7270d61SHaim Dreyfuss */ 1168d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1169ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11707ca00409SHaim Dreyfuss 11717ca00409SHaim Dreyfuss /* 11727ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11737ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11747ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11757ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11767ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11777ca00409SHaim Dreyfuss */ 11787ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 11797ca00409SHaim Dreyfuss 11807ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 118183730058SHaim Dreyfuss } 11827ca00409SHaim Dreyfuss 118383730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 118483730058SHaim Dreyfuss { 118583730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 118683730058SHaim Dreyfuss 118783730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 118883730058SHaim Dreyfuss 118983730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 119083730058SHaim Dreyfuss return; 119183730058SHaim Dreyfuss 119283730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 11937ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 119483730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 11957ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 11967ca00409SHaim Dreyfuss } 11977ca00409SHaim Dreyfuss 1198bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1199e705c121SKalle Valo { 1200e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1201e705c121SKalle Valo 1202e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1203e705c121SKalle Valo 1204e705c121SKalle Valo if (trans_pcie->is_down) 1205e705c121SKalle Valo return; 1206e705c121SKalle Valo 1207e705c121SKalle Valo trans_pcie->is_down = true; 1208e705c121SKalle Valo 1209e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1210e705c121SKalle Valo iwl_disable_interrupts(trans); 1211e705c121SKalle Valo 1212e705c121SKalle Valo /* device going down, Stop using ICT table */ 1213e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1214e705c121SKalle Valo 1215e705c121SKalle Valo /* 1216e705c121SKalle Valo * If a HW restart happens during firmware loading, 1217e705c121SKalle Valo * then the firmware loading might call this function 1218e705c121SKalle Valo * and later it might be called again due to the 1219e705c121SKalle Valo * restart. So don't process again if the device is 1220e705c121SKalle Valo * already dead. 1221e705c121SKalle Valo */ 1222e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1223a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1224a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1225e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1226e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1227e705c121SKalle Valo 1228e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1229e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1230e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1231e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1232e705c121SKalle Valo udelay(5); 1233e705c121SKalle Valo } 1234e705c121SKalle Valo } 1235e705c121SKalle Valo 1236e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 12371b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 12381b6598c3SRoee Goldfiner iwl_clear_bit(trans, CSR_GP_CNTRL, 12391b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 12401b6598c3SRoee Goldfiner else 1241e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12426dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1243e705c121SKalle Valo 1244e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1245e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1246e705c121SKalle Valo 1247870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1248e705c121SKalle Valo 1249e705c121SKalle Valo /* 1250f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1251f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1252f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1253f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1254f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1255f4a1f04aSGolan Ben Ami */ 1256f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1257f4a1f04aSGolan Ben Ami 1258f4a1f04aSGolan Ben Ami /* 1259e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1260e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1261e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1262e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1263e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1264e705c121SKalle Valo */ 1265e705c121SKalle Valo iwl_disable_interrupts(trans); 1266e705c121SKalle Valo 1267e705c121SKalle Valo /* clear all status bits */ 1268e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1269e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1270e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1271e705c121SKalle Valo 1272e705c121SKalle Valo /* 1273e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1274e705c121SKalle Valo * interrupt 1275e705c121SKalle Valo */ 1276e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1277e705c121SKalle Valo 1278a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1279e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1280e705c121SKalle Valo } 1281e705c121SKalle Valo 1282eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 12832e5d4a8fSHaim Dreyfuss { 12842e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 12852e5d4a8fSHaim Dreyfuss 12862e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 12872e5d4a8fSHaim Dreyfuss int i; 12882e5d4a8fSHaim Dreyfuss 1289496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 12902e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 12912e5d4a8fSHaim Dreyfuss } else { 12922e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 12932e5d4a8fSHaim Dreyfuss } 12942e5d4a8fSHaim Dreyfuss } 12952e5d4a8fSHaim Dreyfuss 1296a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1297a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1298a6bd005fSEmmanuel Grumbach { 1299a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1300a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1301a6bd005fSEmmanuel Grumbach int ret; 1302a6bd005fSEmmanuel Grumbach 1303a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1304a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1305a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1306a6bd005fSEmmanuel Grumbach ret = -EIO; 1307a6bd005fSEmmanuel Grumbach goto out; 1308a6bd005fSEmmanuel Grumbach } 1309a6bd005fSEmmanuel Grumbach 1310a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1311a6bd005fSEmmanuel Grumbach 1312a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1313a6bd005fSEmmanuel Grumbach 1314a6bd005fSEmmanuel Grumbach /* 1315a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1316a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1317a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1318a6bd005fSEmmanuel Grumbach */ 1319a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1320a6bd005fSEmmanuel Grumbach 1321a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13222e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1323a6bd005fSEmmanuel Grumbach 1324a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1325a6bd005fSEmmanuel Grumbach 1326a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13279ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1328a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1329a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1330a6bd005fSEmmanuel Grumbach goto out; 1331a6bd005fSEmmanuel Grumbach } 1332a6bd005fSEmmanuel Grumbach 1333a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1334a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1335a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1336a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 133720aa99bbSAnton Protopopov ret = -EIO; 1338a6bd005fSEmmanuel Grumbach goto out; 1339a6bd005fSEmmanuel Grumbach } 1340a6bd005fSEmmanuel Grumbach 1341a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1342a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1343a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1344a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1345a6bd005fSEmmanuel Grumbach 1346a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1347a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1348a6bd005fSEmmanuel Grumbach 1349a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1350a6bd005fSEmmanuel Grumbach if (ret) { 1351a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1352a6bd005fSEmmanuel Grumbach goto out; 1353a6bd005fSEmmanuel Grumbach } 1354a6bd005fSEmmanuel Grumbach 1355a6bd005fSEmmanuel Grumbach /* 1356a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1357a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1358a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1359a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1360a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1361a6bd005fSEmmanuel Grumbach */ 1362a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1363a6bd005fSEmmanuel Grumbach 1364a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1365a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1366a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1367a6bd005fSEmmanuel Grumbach 1368a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1369286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1370a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1371a6bd005fSEmmanuel Grumbach else 1372a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1373a6bd005fSEmmanuel Grumbach 1374a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 13759ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1376a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1377a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1378a6bd005fSEmmanuel Grumbach 1379a6bd005fSEmmanuel Grumbach out: 1380a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1381a6bd005fSEmmanuel Grumbach return ret; 1382a6bd005fSEmmanuel Grumbach } 1383a6bd005fSEmmanuel Grumbach 1384a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1385a6bd005fSEmmanuel Grumbach { 1386a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1387a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1388a6bd005fSEmmanuel Grumbach } 1389a6bd005fSEmmanuel Grumbach 1390326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1391326477e4SJohannes Berg bool was_in_rfkill) 1392326477e4SJohannes Berg { 1393326477e4SJohannes Berg bool hw_rfkill; 1394326477e4SJohannes Berg 1395326477e4SJohannes Berg /* 1396326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1397326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1398326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1399326477e4SJohannes Berg * op_mode. 1400326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1401326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1402326477e4SJohannes Berg * notification without endless recursion. Under very rare 1403326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1404326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1405326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1406326477e4SJohannes Berg */ 1407326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1408326477e4SJohannes Berg if (hw_rfkill) { 1409326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1410326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1411326477e4SJohannes Berg } else { 1412326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1413326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1414326477e4SJohannes Berg } 1415326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1416326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1417326477e4SJohannes Berg } 1418326477e4SJohannes Berg 1419bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1420e705c121SKalle Valo { 1421e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1422326477e4SJohannes Berg bool was_in_rfkill; 1423e705c121SKalle Valo 1424d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1425d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1426d0129315SMordechay Goodstein NULL); 1427d0129315SMordechay Goodstein 1428e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1429326477e4SJohannes Berg trans_pcie->opmode_down = true; 1430326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1431bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1432326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1433e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1434e705c121SKalle Valo } 1435e705c121SKalle Valo 1436e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1437e705c121SKalle Valo { 1438e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1439e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1440e705c121SKalle Valo 1441e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1442e705c121SKalle Valo 1443326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1444326477e4SJohannes Berg state ? "disabled" : "enabled"); 144577c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1446286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1447bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 144877c09bc8SSara Sharon else 1449bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1450e705c121SKalle Valo } 145177c09bc8SSara Sharon } 1452e705c121SKalle Valo 1453e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1454e5f3f215SHaim Dreyfuss bool test, bool reset) 1455e705c121SKalle Valo { 1456e705c121SKalle Valo iwl_disable_interrupts(trans); 1457e705c121SKalle Valo 1458e705c121SKalle Valo /* 1459e705c121SKalle Valo * in testing mode, the host stays awake and the 1460e705c121SKalle Valo * hardware won't be reset (not even partially) 1461e705c121SKalle Valo */ 1462e705c121SKalle Valo if (test) 1463e705c121SKalle Valo return; 1464e705c121SKalle Valo 1465e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1466e705c121SKalle Valo 14672e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1468e705c121SKalle Valo 1469e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 14706dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 14716dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1472e705c121SKalle Valo 147323ae6128SMatti Gottlieb if (reset) { 1474e705c121SKalle Valo /* 1475e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1476e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1477e705c121SKalle Valo * to execute some invalid memory upon resume 1478e705c121SKalle Valo */ 1479e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1480e705c121SKalle Valo } 1481e705c121SKalle Valo 1482e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1483e705c121SKalle Valo } 1484e705c121SKalle Valo 1485e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1486e5f3f215SHaim Dreyfuss bool reset) 1487e5f3f215SHaim Dreyfuss { 1488e5f3f215SHaim Dreyfuss int ret; 1489e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1490e5f3f215SHaim Dreyfuss 1491771db3a1SHaim Dreyfuss if (!reset) 1492e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1493e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1494e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1495e5f3f215SHaim Dreyfuss 1496e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1497e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1498e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1499e5f3f215SHaim Dreyfuss 1500e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1501e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1502e5f3f215SHaim Dreyfuss /* 1503e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1504e5f3f215SHaim Dreyfuss */ 1505e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1506e5f3f215SHaim Dreyfuss 1507e5f3f215SHaim Dreyfuss if (!ret) { 1508e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1509e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1510e5f3f215SHaim Dreyfuss } 1511e5f3f215SHaim Dreyfuss } 1512e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1513e5f3f215SHaim Dreyfuss 1514e5f3f215SHaim Dreyfuss return 0; 1515e5f3f215SHaim Dreyfuss } 1516e5f3f215SHaim Dreyfuss 1517e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1518e705c121SKalle Valo enum iwl_d3_status *status, 151923ae6128SMatti Gottlieb bool test, bool reset) 1520e705c121SKalle Valo { 1521d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1522e705c121SKalle Valo u32 val; 1523e705c121SKalle Valo int ret; 1524e705c121SKalle Valo 1525e705c121SKalle Valo if (test) { 1526e705c121SKalle Valo iwl_enable_interrupts(trans); 1527e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1528e5f3f215SHaim Dreyfuss goto out; 1529e705c121SKalle Valo } 1530e705c121SKalle Valo 1531a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15326dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1533e705c121SKalle Valo 1534425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 1535c96b5eecSJohannes Berg if (ret) 1536e705c121SKalle Valo return ret; 1537e705c121SKalle Valo 1538f98ad635SEmmanuel Grumbach /* 1539f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1540f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1541f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1542f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1543f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1544f98ad635SEmmanuel Grumbach */ 1545f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1546f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1547f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1548f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1549f98ad635SEmmanuel Grumbach 1550e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1551e705c121SKalle Valo 155223ae6128SMatti Gottlieb if (!reset) { 1553e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15546dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1555e705c121SKalle Valo } else { 1556e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1557e705c121SKalle Valo 1558e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1559e705c121SKalle Valo if (ret) { 1560e705c121SKalle Valo IWL_ERR(trans, 1561e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1562e705c121SKalle Valo return ret; 1563e705c121SKalle Valo } 1564e705c121SKalle Valo } 1565e705c121SKalle Valo 156682ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1567ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 156882ea7966SSara Sharon 1569e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1570e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1571e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1572e705c121SKalle Valo else 1573e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1574e705c121SKalle Valo 1575e5f3f215SHaim Dreyfuss out: 1576e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1577e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1578e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1579e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1580e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1581e5f3f215SHaim Dreyfuss 1582e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1583e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1584e5f3f215SHaim Dreyfuss /* 1585e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1586e5f3f215SHaim Dreyfuss */ 1587e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1588e5f3f215SHaim Dreyfuss 1589e5f3f215SHaim Dreyfuss if (!ret) { 1590e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1591e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1592e5f3f215SHaim Dreyfuss } 1593e5f3f215SHaim Dreyfuss } 1594e705c121SKalle Valo return 0; 1595e705c121SKalle Valo } 1596e705c121SKalle Valo 15970c18714aSLuca Coelho static void 15980c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15990c18714aSLuca Coelho struct iwl_trans *trans, 16000c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16012e5d4a8fSHaim Dreyfuss { 16022e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1603ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16042e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16050cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 16062e5d4a8fSHaim Dreyfuss 16070c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 160806f4b081SSara Sharon goto enable_msi; 160906f4b081SSara Sharon 16100cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 16110cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 16120cd38f4dSMordechay Goodstein 16130cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 161406f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16152e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16162e5d4a8fSHaim Dreyfuss 161706f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16182e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 161906f4b081SSara Sharon max_irqs); 162006f4b081SSara Sharon if (num_irqs < 0) { 1621496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 162206f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 162306f4b081SSara Sharon num_irqs); 162406f4b081SSara Sharon goto enable_msi; 1625496d83caSHaim Dreyfuss } 162606f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1627496d83caSHaim Dreyfuss 16282e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 162906f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 163006f4b081SSara Sharon num_irqs); 163106f4b081SSara Sharon 1632496d83caSHaim Dreyfuss /* 163306f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 163406f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1635496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1636496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1637496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1638496d83caSHaim Dreyfuss */ 1639ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 164006f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1641496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1642496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1643ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 164406f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1645496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1646496d83caSHaim Dreyfuss } else { 164706f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1648496d83caSHaim Dreyfuss } 16499d401222SMordechay Goodstein 16509d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16519d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16529d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16539d401222SMordechay Goodstein 1654ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16552e5d4a8fSHaim Dreyfuss 165606f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1657496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16582e5d4a8fSHaim Dreyfuss return; 16592e5d4a8fSHaim Dreyfuss 166006f4b081SSara Sharon enable_msi: 166106f4b081SSara Sharon ret = pci_enable_msi(pdev); 166206f4b081SSara Sharon if (ret) { 166306f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16642e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16652e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16662e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16672e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16682e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16692e5d4a8fSHaim Dreyfuss } 16702e5d4a8fSHaim Dreyfuss } 16712e5d4a8fSHaim Dreyfuss } 16722e5d4a8fSHaim Dreyfuss 16737c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16747c8d91ebSHaim Dreyfuss { 16757c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16767c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16777c8d91ebSHaim Dreyfuss 16787c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16797c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16807c8d91ebSHaim Dreyfuss offset = 1 + i; 16817c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16827c8d91ebSHaim Dreyfuss /* 16837c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16847c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16857c8d91ebSHaim Dreyfuss */ 16867c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16877c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16887c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16897c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16907c8d91ebSHaim Dreyfuss if (ret) 16917c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16927c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 169357e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 16947c8d91ebSHaim Dreyfuss } 16957c8d91ebSHaim Dreyfuss } 16967c8d91ebSHaim Dreyfuss 16972e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 16982e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 16992e5d4a8fSHaim Dreyfuss { 1700496d83caSHaim Dreyfuss int i; 17012e5d4a8fSHaim Dreyfuss 1702496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17032e5d4a8fSHaim Dreyfuss int ret; 17045a41a86cSSharon Dvir struct msix_entry *msix_entry; 170564fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 170664fa3affSSharon Dvir 170764fa3affSSharon Dvir if (!qname) 170864fa3affSSharon Dvir return -ENOMEM; 17092e5d4a8fSHaim Dreyfuss 17105a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17115a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17125a41a86cSSharon Dvir msix_entry->vector, 17132e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1714496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17152e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17162e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17172e5d4a8fSHaim Dreyfuss IRQF_SHARED, 171864fa3affSSharon Dvir qname, 17195a41a86cSSharon Dvir msix_entry); 17202e5d4a8fSHaim Dreyfuss if (ret) { 17212e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17222e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17235a41a86cSSharon Dvir 17242e5d4a8fSHaim Dreyfuss return ret; 17252e5d4a8fSHaim Dreyfuss } 17262e5d4a8fSHaim Dreyfuss } 17277c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17282e5d4a8fSHaim Dreyfuss 17292e5d4a8fSHaim Dreyfuss return 0; 17302e5d4a8fSHaim Dreyfuss } 17312e5d4a8fSHaim Dreyfuss 173244f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 173344f61b5cSShahar S Matityahu { 173444f61b5cSShahar S Matityahu u32 hpm, wprot; 173544f61b5cSShahar S Matityahu 1736286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 173744f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 173844f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 173944f61b5cSShahar S Matityahu break; 174044f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 174144f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 174244f61b5cSShahar S Matityahu break; 174344f61b5cSShahar S Matityahu default: 174444f61b5cSShahar S Matityahu return 0; 174544f61b5cSShahar S Matityahu } 174644f61b5cSShahar S Matityahu 174744f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 174844f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 174944f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 175044f61b5cSShahar S Matityahu 175144f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 175244f61b5cSShahar S Matityahu IWL_ERR(trans, 175344f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 175444f61b5cSShahar S Matityahu return -EPERM; 175544f61b5cSShahar S Matityahu } 175644f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 175744f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 175844f61b5cSShahar S Matityahu } 175944f61b5cSShahar S Matityahu 176044f61b5cSShahar S Matityahu return 0; 176144f61b5cSShahar S Matityahu } 176244f61b5cSShahar S Matityahu 17630df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17640df36b90SLuca Coelho { 17650df36b90SLuca Coelho int ret; 17660df36b90SLuca Coelho 1767425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 17680df36b90SLuca Coelho if (ret < 0) 17690df36b90SLuca Coelho return ret; 17700df36b90SLuca Coelho 17710df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17720df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17730df36b90SLuca Coelho udelay(20); 17740df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17750df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 17760df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 17770df36b90SLuca Coelho udelay(20); 17780df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 17790df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17800df36b90SLuca Coelho 17810df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 17820df36b90SLuca Coelho 17830df36b90SLuca Coelho return 0; 17840df36b90SLuca Coelho } 17850df36b90SLuca Coelho 1786bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1787e705c121SKalle Valo { 1788e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1789e705c121SKalle Valo int err; 1790e705c121SKalle Valo 1791e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1792e705c121SKalle Valo 1793e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1794e705c121SKalle Valo if (err) { 1795e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1796e705c121SKalle Valo return err; 1797e705c121SKalle Valo } 1798e705c121SKalle Valo 179944f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 180044f61b5cSShahar S Matityahu if (err) 180144f61b5cSShahar S Matityahu return err; 18028954e1ebSShahar S Matityahu 1803870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1804e705c121SKalle Valo 18050df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18067897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18070df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18080df36b90SLuca Coelho if (err) 18090df36b90SLuca Coelho return err; 18100df36b90SLuca Coelho } 18110df36b90SLuca Coelho 181252b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 181352b6e168SEmmanuel Grumbach if (err) 181452b6e168SEmmanuel Grumbach return err; 1815e705c121SKalle Valo 18162e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 181783730058SHaim Dreyfuss 1818e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1819e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1820e705c121SKalle Valo 1821326477e4SJohannes Berg trans_pcie->opmode_down = false; 1822326477e4SJohannes Berg 1823e705c121SKalle Valo /* Set is_down to false here so that...*/ 1824e705c121SKalle Valo trans_pcie->is_down = false; 1825e705c121SKalle Valo 1826e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18279ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1828e705c121SKalle Valo 1829e705c121SKalle Valo return 0; 1830e705c121SKalle Valo } 1831e705c121SKalle Valo 1832bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1833e705c121SKalle Valo { 1834e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1835e705c121SKalle Valo int ret; 1836e705c121SKalle Valo 1837e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1838bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1839e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1840e705c121SKalle Valo 1841e705c121SKalle Valo return ret; 1842e705c121SKalle Valo } 1843e705c121SKalle Valo 1844e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1845e705c121SKalle Valo { 1846e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1847e705c121SKalle Valo 1848e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1849e705c121SKalle Valo 1850e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1851e705c121SKalle Valo iwl_disable_interrupts(trans); 1852e705c121SKalle Valo 1853e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1854e705c121SKalle Valo 1855e705c121SKalle Valo iwl_disable_interrupts(trans); 1856e705c121SKalle Valo 1857e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1858e705c121SKalle Valo 1859e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1860e705c121SKalle Valo 18612e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1862e705c121SKalle Valo } 1863e705c121SKalle Valo 1864e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1865e705c121SKalle Valo { 1866e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1867e705c121SKalle Valo } 1868e705c121SKalle Valo 1869e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1870e705c121SKalle Valo { 1871e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1872e705c121SKalle Valo } 1873e705c121SKalle Valo 1874e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1875e705c121SKalle Valo { 1876e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1877e705c121SKalle Valo } 1878e705c121SKalle Valo 187984fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 188084fb372cSSara Sharon { 18813681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 188284fb372cSSara Sharon return 0x00FFFFFF; 188384fb372cSSara Sharon else 188484fb372cSSara Sharon return 0x000FFFFF; 188584fb372cSSara Sharon } 188684fb372cSSara Sharon 1887e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1888e705c121SKalle Valo { 188984fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 189084fb372cSSara Sharon 1891e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 189284fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1893e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1894e705c121SKalle Valo } 1895e705c121SKalle Valo 1896e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1897e705c121SKalle Valo u32 val) 1898e705c121SKalle Valo { 189984fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 190084fb372cSSara Sharon 1901e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 190284fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1903e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1904e705c121SKalle Valo } 1905e705c121SKalle Valo 1906e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1907e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1908e705c121SKalle Valo { 1909e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1910e705c121SKalle Valo 19116ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 19126ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 19136ac57200SJohannes Berg 19144f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 19154f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 19164f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 191722852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 191822852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 191922852fadSMordechay Goodstein 1920e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1921e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1922e705c121SKalle Valo else 1923e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1924e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1925e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1926e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1927e705c121SKalle Valo 19286c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19296c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19306c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 193180084e35SJohannes Berg trans_pcie->rx_buf_bytes = 193280084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1933cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1934cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1935cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1936e705c121SKalle Valo 19378e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1938e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1939e705c121SKalle Valo 194039bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 194139bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 194239bdb17eSSharon Dvir 1943e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1944e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1945e705c121SKalle Valo * As this function may be called again in some corner cases don't 1946e705c121SKalle Valo * do anything if NAPI was already initialized. 1947e705c121SKalle Valo */ 1948bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1949e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1950906d4eb8SJohannes Berg 1951906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1952e705c121SKalle Valo } 1953e705c121SKalle Valo 1954e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1955e705c121SKalle Valo { 1956e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19576eb5e529SEmmanuel Grumbach int i; 1958e705c121SKalle Valo 19592e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1960e705c121SKalle Valo 1961286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 19620cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 196313a3a390SSara Sharon else 1964e705c121SKalle Valo iwl_pcie_tx_free(trans); 1965e705c121SKalle Valo iwl_pcie_rx_free(trans); 1966e705c121SKalle Valo 196710a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 196810a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 196910a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 197010a54d81SLuca Coelho } 197110a54d81SLuca Coelho 19722e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19737c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19747c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19757c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19767c8d91ebSHaim Dreyfuss NULL); 19777c8d91ebSHaim Dreyfuss } 19782e5d4a8fSHaim Dreyfuss 19792e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19802e5d4a8fSHaim Dreyfuss } else { 1981e705c121SKalle Valo iwl_pcie_free_ict(trans); 19822e5d4a8fSHaim Dreyfuss } 1983e705c121SKalle Valo 1984e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1985e705c121SKalle Valo 198669725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 198769725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 198869725928SLuca Coelho trans_pcie->pnvm_dram.block, 198969725928SLuca Coelho trans_pcie->pnvm_dram.physical); 199069725928SLuca Coelho 19919dad325fSLuca Coelho if (trans_pcie->reduce_power_dram.size) 19929dad325fSLuca Coelho dma_free_coherent(trans->dev, 19939dad325fSLuca Coelho trans_pcie->reduce_power_dram.size, 19949dad325fSLuca Coelho trans_pcie->reduce_power_dram.block, 19959dad325fSLuca Coelho trans_pcie->reduce_power_dram.physical); 19969dad325fSLuca Coelho 1997a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1998e705c121SKalle Valo iwl_trans_free(trans); 1999e705c121SKalle Valo } 2000e705c121SKalle Valo 2001e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2002e705c121SKalle Valo { 2003e705c121SKalle Valo if (state) 2004e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2005e705c121SKalle Valo else 2006e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2007e705c121SKalle Valo } 2008e705c121SKalle Valo 200949564a80SLuca Coelho struct iwl_trans_pcie_removal { 201049564a80SLuca Coelho struct pci_dev *pdev; 201149564a80SLuca Coelho struct work_struct work; 201249564a80SLuca Coelho }; 201349564a80SLuca Coelho 201449564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 201549564a80SLuca Coelho { 201649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 201749564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 201849564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2019aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 202049564a80SLuca Coelho 202149564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 202249564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 202349564a80SLuca Coelho pci_lock_rescan_remove(); 202449564a80SLuca Coelho pci_dev_put(pdev); 202549564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 202649564a80SLuca Coelho pci_unlock_rescan_remove(); 202749564a80SLuca Coelho 202849564a80SLuca Coelho kfree(removal); 202949564a80SLuca Coelho module_put(THIS_MODULE); 203049564a80SLuca Coelho } 203149564a80SLuca Coelho 2032c544d89bSJohannes Berg /* 2033c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2034c544d89bSJohannes Berg * already disabled. 2035c544d89bSJohannes Berg */ 2036c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2037e705c121SKalle Valo { 2038e705c121SKalle Valo int ret; 2039e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 20409ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 20419ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 20429ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 20439ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2044e705c121SKalle Valo 2045c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2046e705c121SKalle Valo 2047e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2048e705c121SKalle Valo goto out; 2049e705c121SKalle Valo 20509ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 20519ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 20529ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20539ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 20549ce041f5SJohannes Berg } 20559ce041f5SJohannes Berg 2056e705c121SKalle Valo /* this bit wakes up the NIC */ 20579ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2058286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2059e705c121SKalle Valo udelay(2); 2060e705c121SKalle Valo 2061e705c121SKalle Valo /* 2062e705c121SKalle Valo * These bits say the device is running, and should keep running for 2063e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2064e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2065fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2066fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2067e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2068e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2069e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2070e705c121SKalle Valo * to keep device from sleeping. 2071e705c121SKalle Valo * 2072e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2073e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2074fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2075fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2076fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2077e705c121SKalle Valo * 2078e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2079e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2080e705c121SKalle Valo */ 20819ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2082e705c121SKalle Valo if (unlikely(ret < 0)) { 208349564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 208449564a80SLuca Coelho 2085e705c121SKalle Valo WARN_ONCE(1, 2086e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 208749564a80SLuca Coelho cntrl); 208849564a80SLuca Coelho 208949564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 209049564a80SLuca Coelho 209149564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 209249564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 209349564a80SLuca Coelho 2094f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 209549564a80SLuca Coelho goto err; 209649564a80SLuca Coelho 209749564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 209849564a80SLuca Coelho 209949564a80SLuca Coelho /* 210049564a80SLuca Coelho * get a module reference to avoid doing this 210149564a80SLuca Coelho * while unloading anyway and to avoid 210249564a80SLuca Coelho * scheduling a work with code that's being 210349564a80SLuca Coelho * removed. 210449564a80SLuca Coelho */ 210549564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 210649564a80SLuca Coelho IWL_ERR(trans, 210749564a80SLuca Coelho "Module is being unloaded - abort\n"); 210849564a80SLuca Coelho goto err; 210949564a80SLuca Coelho } 211049564a80SLuca Coelho 211149564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 211249564a80SLuca Coelho if (!removal) { 211349564a80SLuca Coelho module_put(THIS_MODULE); 211449564a80SLuca Coelho goto err; 211549564a80SLuca Coelho } 211649564a80SLuca Coelho /* 211749564a80SLuca Coelho * we don't need to clear this flag, because 211849564a80SLuca Coelho * the trans will be freed and reallocated. 211949564a80SLuca Coelho */ 2120f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 212149564a80SLuca Coelho 212249564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 212349564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 212449564a80SLuca Coelho pci_dev_get(removal->pdev); 212549564a80SLuca Coelho schedule_work(&removal->work); 212649564a80SLuca Coelho } else { 212749564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 212849564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 212949564a80SLuca Coelho } 213049564a80SLuca Coelho 213149564a80SLuca Coelho err: 2132c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2133e705c121SKalle Valo return false; 2134e705c121SKalle Valo } 2135e705c121SKalle Valo 2136e705c121SKalle Valo out: 2137e705c121SKalle Valo /* 2138e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2139e705c121SKalle Valo * track nic_access anyway. 2140e705c121SKalle Valo */ 2141e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2142e705c121SKalle Valo return true; 2143e705c121SKalle Valo } 2144e705c121SKalle Valo 2145c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2146c544d89bSJohannes Berg { 2147c544d89bSJohannes Berg bool ret; 2148c544d89bSJohannes Berg 2149c544d89bSJohannes Berg local_bh_disable(); 2150c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2151c544d89bSJohannes Berg if (ret) { 2152c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2153c544d89bSJohannes Berg return ret; 2154c544d89bSJohannes Berg } 2155c544d89bSJohannes Berg local_bh_enable(); 2156c544d89bSJohannes Berg return false; 2157c544d89bSJohannes Berg } 2158c544d89bSJohannes Berg 21591ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2160e705c121SKalle Valo { 2161e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2162e705c121SKalle Valo 2163e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2164e705c121SKalle Valo 2165e705c121SKalle Valo /* 2166e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2167e705c121SKalle Valo * track nic_access anyway. 2168e705c121SKalle Valo */ 2169e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2170e705c121SKalle Valo 2171e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2172e705c121SKalle Valo goto out; 21731b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 21741b6598c3SRoee Goldfiner __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21751b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 21761b6598c3SRoee Goldfiner else 2177e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 21786dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2179e705c121SKalle Valo /* 2180e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2181e705c121SKalle Valo * any previous writes, but we need the write that clears the 2182e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2183e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2184e705c121SKalle Valo */ 2185e705c121SKalle Valo out: 2186874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2187e705c121SKalle Valo } 2188e705c121SKalle Valo 2189e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2190e705c121SKalle Valo void *buf, int dwords) 2191e705c121SKalle Valo { 219204516706SJohannes Berg int offs = 0; 2193e705c121SKalle Valo u32 *vals = buf; 2194e705c121SKalle Valo 219504516706SJohannes Berg while (offs < dwords) { 219604516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 219767013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 21983d372c4eSJohannes Berg bool resched = false; 219904516706SJohannes Berg 22001ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 220104516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 220204516706SJohannes Berg addr + 4 * offs); 220304516706SJohannes Berg 220404516706SJohannes Berg while (offs < dwords) { 220504516706SJohannes Berg vals[offs] = iwl_read32(trans, 220604516706SJohannes Berg HBUS_TARG_MEM_RDAT); 220704516706SJohannes Berg offs++; 220804516706SJohannes Berg 22093d372c4eSJohannes Berg if (time_after(jiffies, end)) { 22103d372c4eSJohannes Berg resched = true; 221104516706SJohannes Berg break; 221204516706SJohannes Berg } 22133d372c4eSJohannes Berg } 22141ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 22153d372c4eSJohannes Berg 22163d372c4eSJohannes Berg if (resched) 22173d372c4eSJohannes Berg cond_resched(); 2218e705c121SKalle Valo } else { 221904516706SJohannes Berg return -EBUSY; 2220e705c121SKalle Valo } 222104516706SJohannes Berg } 222204516706SJohannes Berg 222304516706SJohannes Berg return 0; 2224e705c121SKalle Valo } 2225e705c121SKalle Valo 2226e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2227e705c121SKalle Valo const void *buf, int dwords) 2228e705c121SKalle Valo { 2229e705c121SKalle Valo int offs, ret = 0; 2230e705c121SKalle Valo const u32 *vals = buf; 2231e705c121SKalle Valo 22321ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2233e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2234e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2235e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2236e705c121SKalle Valo vals ? vals[offs] : 0); 22371ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2238e705c121SKalle Valo } else { 2239e705c121SKalle Valo ret = -EBUSY; 2240e705c121SKalle Valo } 2241e705c121SKalle Valo return ret; 2242e705c121SKalle Valo } 2243e705c121SKalle Valo 22447f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22457f1fe1d4SLuca Coelho u32 *val) 22467f1fe1d4SLuca Coelho { 22477f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 22487f1fe1d4SLuca Coelho ofs, val); 22497f1fe1d4SLuca Coelho } 22507f1fe1d4SLuca Coelho 22510cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22520cd58eaaSEmmanuel Grumbach { 22530cd58eaaSEmmanuel Grumbach int i; 22540cd58eaaSEmmanuel Grumbach 2255286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 22564f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 22570cd58eaaSEmmanuel Grumbach 22584f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 22590cd58eaaSEmmanuel Grumbach continue; 22600cd58eaaSEmmanuel Grumbach 22610cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22620cd58eaaSEmmanuel Grumbach 22630cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22640cd58eaaSEmmanuel Grumbach txq->block--; 22650cd58eaaSEmmanuel Grumbach if (!txq->block) { 22660cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2267bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22680cd58eaaSEmmanuel Grumbach } 22690cd58eaaSEmmanuel Grumbach } else if (block) { 22700cd58eaaSEmmanuel Grumbach txq->block++; 22710cd58eaaSEmmanuel Grumbach } 22720cd58eaaSEmmanuel Grumbach 22730cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22740cd58eaaSEmmanuel Grumbach } 22750cd58eaaSEmmanuel Grumbach } 22760cd58eaaSEmmanuel Grumbach 2277e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2278e705c121SKalle Valo 227992536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 228092536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 228192536c96SSara Sharon { 228292536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 228392536c96SSara Sharon 228492536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 228592536c96SSara Sharon return -EINVAL; 228692536c96SSara Sharon 228792536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 228892536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 228992536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 229092536c96SSara Sharon data->fr_bd_wid = 0; 229192536c96SSara Sharon 229292536c96SSara Sharon return 0; 229392536c96SSara Sharon } 229492536c96SSara Sharon 2295d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2296e705c121SKalle Valo { 2297e705c121SKalle Valo struct iwl_txq *txq; 2298e705c121SKalle Valo unsigned long now = jiffies; 22992ae48edcSSara Sharon bool overflow_tx; 2300e705c121SKalle Valo u8 wr_ptr; 2301e705c121SKalle Valo 23022b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2303f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2304f60c9e59SEmmanuel Grumbach return -ENODEV; 23052b3fae66SMatt Chen 23064f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2307d6d517b7SSara Sharon return -EINVAL; 2308e705c121SKalle Valo 2309d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 23104f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 23112ae48edcSSara Sharon 23122ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23132ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23142ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23152ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23162ae48edcSSara Sharon 23176aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2318e705c121SKalle Valo 23192ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23202ae48edcSSara Sharon overflow_tx) && 2321e705c121SKalle Valo !time_after(jiffies, 2322e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23236aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2324e705c121SKalle Valo 23252ae48edcSSara Sharon /* 23262ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23272ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23282ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23292ae48edcSSara Sharon */ 23302ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2331e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2332e705c121SKalle Valo wr_ptr, write_ptr)) 2333e705c121SKalle Valo return -ETIMEDOUT; 23342ae48edcSSara Sharon wr_ptr = write_ptr; 23352ae48edcSSara Sharon 2336192185d6SJohannes Berg usleep_range(1000, 2000); 23372ae48edcSSara Sharon 23382ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23392ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23402ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23412ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2342e705c121SKalle Valo } 2343e705c121SKalle Valo 2344bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2345e705c121SKalle Valo IWL_ERR(trans, 2346d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 23470cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2348d6d517b7SSara Sharon return -ETIMEDOUT; 2349e705c121SKalle Valo } 2350e705c121SKalle Valo 2351d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2352d6d517b7SSara Sharon 2353d6d517b7SSara Sharon return 0; 2354d6d517b7SSara Sharon } 2355d6d517b7SSara Sharon 2356d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2357d6d517b7SSara Sharon { 2358d6d517b7SSara Sharon int cnt; 2359d6d517b7SSara Sharon int ret = 0; 2360d6d517b7SSara Sharon 2361d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 236279b6c8feSLuca Coelho for (cnt = 0; 2363286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 236479b6c8feSLuca Coelho cnt++) { 2365d6d517b7SSara Sharon 23664f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2367d6d517b7SSara Sharon continue; 23684f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2369d6d517b7SSara Sharon continue; 2370d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2371d6d517b7SSara Sharon continue; 2372d6d517b7SSara Sharon 2373d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 237438398efbSSara Sharon if (ret) 2375d6d517b7SSara Sharon break; 2376d6d517b7SSara Sharon } 2377e705c121SKalle Valo 2378e705c121SKalle Valo return ret; 2379e705c121SKalle Valo } 2380e705c121SKalle Valo 2381e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2382e705c121SKalle Valo u32 mask, u32 value) 2383e705c121SKalle Valo { 2384e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2385e705c121SKalle Valo 2386874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2387e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2388874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2389e705c121SKalle Valo } 2390e705c121SKalle Valo 2391e705c121SKalle Valo static const char *get_csr_string(int cmd) 2392e705c121SKalle Valo { 2393e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2394e705c121SKalle Valo switch (cmd) { 2395e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2396e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2397e705c121SKalle Valo IWL_CMD(CSR_INT); 2398e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2399e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2400e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2401e705c121SKalle Valo IWL_CMD(CSR_RESET); 2402e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2403e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2404e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2405e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2406e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2407e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2408e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2409e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2410e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2411e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2412e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2413e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2414e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2415e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2416e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2417e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2418e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2419e705c121SKalle Valo default: 2420e705c121SKalle Valo return "UNKNOWN"; 2421e705c121SKalle Valo } 2422e705c121SKalle Valo #undef IWL_CMD 2423e705c121SKalle Valo } 2424e705c121SKalle Valo 2425e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2426e705c121SKalle Valo { 2427e705c121SKalle Valo int i; 2428e705c121SKalle Valo static const u32 csr_tbl[] = { 2429e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2430e705c121SKalle Valo CSR_INT_COALESCING, 2431e705c121SKalle Valo CSR_INT, 2432e705c121SKalle Valo CSR_INT_MASK, 2433e705c121SKalle Valo CSR_FH_INT_STATUS, 2434e705c121SKalle Valo CSR_GPIO_IN, 2435e705c121SKalle Valo CSR_RESET, 2436e705c121SKalle Valo CSR_GP_CNTRL, 2437e705c121SKalle Valo CSR_HW_REV, 2438e705c121SKalle Valo CSR_EEPROM_REG, 2439e705c121SKalle Valo CSR_EEPROM_GP, 2440e705c121SKalle Valo CSR_OTP_GP_REG, 2441e705c121SKalle Valo CSR_GIO_REG, 2442e705c121SKalle Valo CSR_GP_UCODE_REG, 2443e705c121SKalle Valo CSR_GP_DRIVER_REG, 2444e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2445e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2446e705c121SKalle Valo CSR_LED_REG, 2447e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2448e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2449e705c121SKalle Valo CSR_ANA_PLL_CFG, 2450e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2451e705c121SKalle Valo CSR_HW_REV_WA_REG, 2452e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2453e705c121SKalle Valo }; 2454e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2455e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2456e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2457e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2458e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2459e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2460e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2461e705c121SKalle Valo } 2462e705c121SKalle Valo } 2463e705c121SKalle Valo 2464e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2465e705c121SKalle Valo /* create and remove of files */ 2466e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2467cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2468cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2469e705c121SKalle Valo } while (0) 2470e705c121SKalle Valo 2471e705c121SKalle Valo /* file operation */ 2472e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2473e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2474e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2475e705c121SKalle Valo .open = simple_open, \ 2476e705c121SKalle Valo .llseek = generic_file_llseek, \ 2477e705c121SKalle Valo }; 2478e705c121SKalle Valo 2479e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2480e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2481e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2482e705c121SKalle Valo .open = simple_open, \ 2483e705c121SKalle Valo .llseek = generic_file_llseek, \ 2484e705c121SKalle Valo }; 2485e705c121SKalle Valo 2486e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2487e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2488e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2489e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2490e705c121SKalle Valo .open = simple_open, \ 2491e705c121SKalle Valo .llseek = generic_file_llseek, \ 2492e705c121SKalle Valo }; 2493e705c121SKalle Valo 2494df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2495df67a1beSJohannes Berg struct iwl_trans *trans; 2496df67a1beSJohannes Berg }; 2497df67a1beSJohannes Berg 2498df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2499df67a1beSJohannes Berg loff_t pos; 2500df67a1beSJohannes Berg }; 2501df67a1beSJohannes Berg 2502df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2503e705c121SKalle Valo { 2504df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2505df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2506df67a1beSJohannes Berg 2507df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2508df67a1beSJohannes Berg return NULL; 2509df67a1beSJohannes Berg 2510df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2511df67a1beSJohannes Berg if (!state) 2512df67a1beSJohannes Berg return NULL; 2513df67a1beSJohannes Berg state->pos = *pos; 2514df67a1beSJohannes Berg return state; 2515df67a1beSJohannes Berg } 2516df67a1beSJohannes Berg 2517df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2518df67a1beSJohannes Berg void *v, loff_t *pos) 2519df67a1beSJohannes Berg { 2520df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2521df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2522df67a1beSJohannes Berg 2523df67a1beSJohannes Berg *pos = ++state->pos; 2524df67a1beSJohannes Berg 2525df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2526df67a1beSJohannes Berg return NULL; 2527df67a1beSJohannes Berg 2528df67a1beSJohannes Berg return state; 2529df67a1beSJohannes Berg } 2530df67a1beSJohannes Berg 2531df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2532df67a1beSJohannes Berg { 2533df67a1beSJohannes Berg kfree(v); 2534df67a1beSJohannes Berg } 2535df67a1beSJohannes Berg 2536df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2537df67a1beSJohannes Berg { 2538df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2539df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2540df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 25414f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2542e705c121SKalle Valo 2543df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2544df67a1beSJohannes Berg (unsigned int)state->pos, 25454f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 25464f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2547df67a1beSJohannes Berg if (txq) 2548df67a1beSJohannes Berg seq_printf(seq, 254995a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2550df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 255195a9e44fSJohannes Berg txq->need_update, txq->frozen, 255295a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2553df67a1beSJohannes Berg else 2554df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2555e705c121SKalle Valo 25564f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2557df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2558df67a1beSJohannes Berg seq_puts(seq, "\n"); 2559e705c121SKalle Valo 2560df67a1beSJohannes Berg return 0; 2561df67a1beSJohannes Berg } 2562df67a1beSJohannes Berg 2563df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2564df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2565df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2566df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2567df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2568df67a1beSJohannes Berg }; 2569df67a1beSJohannes Berg 2570df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2571df67a1beSJohannes Berg { 2572df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2573df67a1beSJohannes Berg 2574df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2575df67a1beSJohannes Berg sizeof(*priv)); 2576df67a1beSJohannes Berg 2577df67a1beSJohannes Berg if (!priv) 2578e705c121SKalle Valo return -ENOMEM; 2579e705c121SKalle Valo 2580df67a1beSJohannes Berg priv->trans = inode->i_private; 2581df67a1beSJohannes Berg return 0; 2582e705c121SKalle Valo } 2583e705c121SKalle Valo 2584e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2585e705c121SKalle Valo char __user *user_buf, 2586e705c121SKalle Valo size_t count, loff_t *ppos) 2587e705c121SKalle Valo { 2588e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2589e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 259078485054SSara Sharon char *buf; 259178485054SSara Sharon int pos = 0, i, ret; 2592eb3dc36eSColin Ian King size_t bufsz; 2593e705c121SKalle Valo 259478485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 259578485054SSara Sharon 259678485054SSara Sharon if (!trans_pcie->rxq) 259778485054SSara Sharon return -EAGAIN; 259878485054SSara Sharon 259978485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 260078485054SSara Sharon if (!buf) 260178485054SSara Sharon return -ENOMEM; 260278485054SSara Sharon 260378485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 260478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 260578485054SSara Sharon 260678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 260778485054SSara Sharon i); 260878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2609e705c121SKalle Valo rxq->read); 261078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2611e705c121SKalle Valo rxq->write); 261278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2613e705c121SKalle Valo rxq->write_actual); 261478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2615e705c121SKalle Valo rxq->need_update); 261678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2617e705c121SKalle Valo rxq->free_count); 2618e705c121SKalle Valo if (rxq->rb_stts) { 26190307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26200307c839SGolan Ben Ami rxq)); 262178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 262278485054SSara Sharon "\tclosed_rb_num: %u\n", 26230307c839SGolan Ben Ami r & 0x0FFF); 2624e705c121SKalle Valo } else { 2625e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 262678485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2627e705c121SKalle Valo } 262878485054SSara Sharon } 262978485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 263078485054SSara Sharon kfree(buf); 263178485054SSara Sharon 263278485054SSara Sharon return ret; 2633e705c121SKalle Valo } 2634e705c121SKalle Valo 2635e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2636e705c121SKalle Valo char __user *user_buf, 2637e705c121SKalle Valo size_t count, loff_t *ppos) 2638e705c121SKalle Valo { 2639e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2640e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2641e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2642e705c121SKalle Valo 2643e705c121SKalle Valo int pos = 0; 2644e705c121SKalle Valo char *buf; 2645e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2646e705c121SKalle Valo ssize_t ret; 2647e705c121SKalle Valo 2648e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2649e705c121SKalle Valo if (!buf) 2650e705c121SKalle Valo return -ENOMEM; 2651e705c121SKalle Valo 2652e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2653e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2654e705c121SKalle Valo 2655e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2656e705c121SKalle Valo isr_stats->hw); 2657e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2658e705c121SKalle Valo isr_stats->sw); 2659e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2660e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2661e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2662e705c121SKalle Valo isr_stats->err_code); 2663e705c121SKalle Valo } 2664e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2665e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2666e705c121SKalle Valo isr_stats->sch); 2667e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2668e705c121SKalle Valo isr_stats->alive); 2669e705c121SKalle Valo #endif 2670e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2671e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2672e705c121SKalle Valo 2673e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2674e705c121SKalle Valo isr_stats->ctkill); 2675e705c121SKalle Valo 2676e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2677e705c121SKalle Valo isr_stats->wakeup); 2678e705c121SKalle Valo 2679e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2680e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2681e705c121SKalle Valo 2682e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2683e705c121SKalle Valo isr_stats->tx); 2684e705c121SKalle Valo 2685e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2686e705c121SKalle Valo isr_stats->unhandled); 2687e705c121SKalle Valo 2688e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2689e705c121SKalle Valo kfree(buf); 2690e705c121SKalle Valo return ret; 2691e705c121SKalle Valo } 2692e705c121SKalle Valo 2693e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2694e705c121SKalle Valo const char __user *user_buf, 2695e705c121SKalle Valo size_t count, loff_t *ppos) 2696e705c121SKalle Valo { 2697e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2698e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2699e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2700e705c121SKalle Valo u32 reset_flag; 2701078f1131SJohannes Berg int ret; 2702e705c121SKalle Valo 2703078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2704078f1131SJohannes Berg if (ret) 2705078f1131SJohannes Berg return ret; 2706e705c121SKalle Valo if (reset_flag == 0) 2707e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2708e705c121SKalle Valo 2709e705c121SKalle Valo return count; 2710e705c121SKalle Valo } 2711e705c121SKalle Valo 2712e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2713e705c121SKalle Valo const char __user *user_buf, 2714e705c121SKalle Valo size_t count, loff_t *ppos) 2715e705c121SKalle Valo { 2716e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2717e705c121SKalle Valo 2718e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2719e705c121SKalle Valo 2720e705c121SKalle Valo return count; 2721e705c121SKalle Valo } 2722e705c121SKalle Valo 2723e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2724e705c121SKalle Valo char __user *user_buf, 2725e705c121SKalle Valo size_t count, loff_t *ppos) 2726e705c121SKalle Valo { 2727e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2728e705c121SKalle Valo char *buf = NULL; 2729e705c121SKalle Valo ssize_t ret; 2730e705c121SKalle Valo 2731e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2732e705c121SKalle Valo if (ret < 0) 2733e705c121SKalle Valo return ret; 2734e705c121SKalle Valo if (!buf) 2735e705c121SKalle Valo return -EINVAL; 2736e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2737e705c121SKalle Valo kfree(buf); 2738e705c121SKalle Valo return ret; 2739e705c121SKalle Valo } 2740e705c121SKalle Valo 2741fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2742fa4de7f7SJohannes Berg char __user *user_buf, 2743fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2744fa4de7f7SJohannes Berg { 2745fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2746fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2747fa4de7f7SJohannes Berg char buf[100]; 2748fa4de7f7SJohannes Berg int pos; 2749fa4de7f7SJohannes Berg 2750fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2751fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2752fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2753fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2754fa4de7f7SJohannes Berg 2755fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2756fa4de7f7SJohannes Berg } 2757fa4de7f7SJohannes Berg 2758fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2759fa4de7f7SJohannes Berg const char __user *user_buf, 2760fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2761fa4de7f7SJohannes Berg { 2762fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2763fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2764c5bf4fa1SJohannes Berg bool new_value; 2765fa4de7f7SJohannes Berg int ret; 2766fa4de7f7SJohannes Berg 2767c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2768fa4de7f7SJohannes Berg if (ret) 2769fa4de7f7SJohannes Berg return ret; 2770c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2771fa4de7f7SJohannes Berg return count; 2772fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2773c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2774c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2775fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2776fa4de7f7SJohannes Berg 2777fa4de7f7SJohannes Berg return count; 2778fa4de7f7SJohannes Berg } 2779fa4de7f7SJohannes Berg 2780f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2781f7805b33SLior Cohen struct file *file) 2782f7805b33SLior Cohen { 2783f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2784f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2785f7805b33SLior Cohen 278691c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 278791c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2788f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2789f7805b33SLior Cohen return -ENOENT; 2790f7805b33SLior Cohen } 2791f7805b33SLior Cohen 2792f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2793f7805b33SLior Cohen return -EBUSY; 2794f7805b33SLior Cohen 2795f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2796f7805b33SLior Cohen return simple_open(inode, file); 2797f7805b33SLior Cohen } 2798f7805b33SLior Cohen 2799f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2800f7805b33SLior Cohen struct file *file) 2801f7805b33SLior Cohen { 2802f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2803f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2804f7805b33SLior Cohen 2805f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2806f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2807f7805b33SLior Cohen return 0; 2808f7805b33SLior Cohen } 2809f7805b33SLior Cohen 2810f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2811f7805b33SLior Cohen void *buf, ssize_t *size, 2812f7805b33SLior Cohen ssize_t *bytes_copied) 2813f7805b33SLior Cohen { 2814f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2815f7805b33SLior Cohen 2816f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2817f7805b33SLior Cohen if (*size > buf_size_left) 2818f7805b33SLior Cohen *size = buf_size_left; 2819f7805b33SLior Cohen 2820f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2821f7805b33SLior Cohen *bytes_copied += *size; 2822f7805b33SLior Cohen 2823f7805b33SLior Cohen if (buf_size_left == *size) 2824f7805b33SLior Cohen return true; 2825f7805b33SLior Cohen return false; 2826f7805b33SLior Cohen } 2827f7805b33SLior Cohen 2828f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2829f7805b33SLior Cohen char __user *user_buf, 2830f7805b33SLior Cohen size_t count, loff_t *ppos) 2831f7805b33SLior Cohen { 2832f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2833f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 283469f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2835f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2836f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2837f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2838f7805b33SLior Cohen bool b_full; 2839f7805b33SLior Cohen 284091c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2841f7805b33SLior Cohen write_ptr_addr = 284291c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 284391c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2844f7805b33SLior Cohen } else { 2845f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2846f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2847f7805b33SLior Cohen } 2848f7805b33SLior Cohen 284991c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2850f7805b33SLior Cohen return 0; 2851f7805b33SLior Cohen 2852f7805b33SLior Cohen mutex_lock(&data->mutex); 2853f7805b33SLior Cohen if (data->state == 2854f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2855f7805b33SLior Cohen mutex_unlock(&data->mutex); 2856f7805b33SLior Cohen return 0; 2857f7805b33SLior Cohen } 2858f7805b33SLior Cohen 2859f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2860f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2861f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2862f7805b33SLior Cohen 2863f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2864f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2865f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2866f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2867f7805b33SLior Cohen curr_buf, &size, 2868f7805b33SLior Cohen &bytes_copied); 2869f7805b33SLior Cohen data->prev_wr_ptr += size; 2870f7805b33SLior Cohen 2871f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2872f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 287369f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2874f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2875f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2876f7805b33SLior Cohen curr_buf, &size, 2877f7805b33SLior Cohen &bytes_copied); 2878f7805b33SLior Cohen data->prev_wr_ptr += size; 2879f7805b33SLior Cohen 2880f7805b33SLior Cohen if (!b_full) { 2881f7805b33SLior Cohen size = write_ptr; 2882f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2883f7805b33SLior Cohen cpu_addr, &size, 2884f7805b33SLior Cohen &bytes_copied); 2885f7805b33SLior Cohen data->prev_wr_ptr = size; 2886f7805b33SLior Cohen data->prev_wrap_cnt++; 2887f7805b33SLior Cohen } 2888f7805b33SLior Cohen } else { 2889f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2890f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2891f7805b33SLior Cohen IWL_WARN(trans, 2892f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2893f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2894f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2895f7805b33SLior Cohen IWL_WARN(trans, 2896f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2897f7805b33SLior Cohen 2898f7805b33SLior Cohen size = write_ptr; 2899f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2900f7805b33SLior Cohen cpu_addr, &size, 2901f7805b33SLior Cohen &bytes_copied); 2902f7805b33SLior Cohen data->prev_wr_ptr = size; 2903f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2904f7805b33SLior Cohen } 2905f7805b33SLior Cohen 2906f7805b33SLior Cohen mutex_unlock(&data->mutex); 2907f7805b33SLior Cohen 2908f7805b33SLior Cohen return bytes_copied; 2909f7805b33SLior Cohen } 2910f7805b33SLior Cohen 2911aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 2912aa899e68SJohannes Berg char __user *user_buf, 2913aa899e68SJohannes Berg size_t count, loff_t *ppos) 2914aa899e68SJohannes Berg { 2915aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 2916aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2917aa899e68SJohannes Berg 2918aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 2919aa899e68SJohannes Berg return -ENODEV; 2920aa899e68SJohannes Berg 2921aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 2922aa899e68SJohannes Berg trans_pcie->rf_name, 2923aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 2924aa899e68SJohannes Berg } 2925aa899e68SJohannes Berg 2926e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2927e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2928e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2929e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2930fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2931aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 2932aa899e68SJohannes Berg 2933df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2934df67a1beSJohannes Berg .owner = THIS_MODULE, 2935df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2936df67a1beSJohannes Berg .read = seq_read, 2937df67a1beSJohannes Berg .llseek = seq_lseek, 2938df67a1beSJohannes Berg .release = seq_release_private, 2939df67a1beSJohannes Berg }; 2940e705c121SKalle Valo 2941f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2942f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2943f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2944f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2945f7805b33SLior Cohen }; 2946f7805b33SLior Cohen 2947f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2948cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2949e705c121SKalle Valo { 2950f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2951f8a1edb7SJohannes Berg 29522ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 29532ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 29542ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 29552ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 29562ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 29572ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2958f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2959aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 2960e705c121SKalle Valo } 2961f7805b33SLior Cohen 2962f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2963f7805b33SLior Cohen { 2964f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2965f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2966f7805b33SLior Cohen 2967f7805b33SLior Cohen mutex_lock(&data->mutex); 2968f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2969f7805b33SLior Cohen mutex_unlock(&data->mutex); 2970f7805b33SLior Cohen } 2971e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2972e705c121SKalle Valo 29736983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2974e705c121SKalle Valo { 2975e705c121SKalle Valo u32 cmdlen = 0; 2976e705c121SKalle Valo int i; 2977e705c121SKalle Valo 2978885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 29790179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 2980e705c121SKalle Valo 2981e705c121SKalle Valo return cmdlen; 2982e705c121SKalle Valo } 2983e705c121SKalle Valo 2984e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2985e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2986e705c121SKalle Valo int allocated_rb_nums) 2987e705c121SKalle Valo { 2988e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 298980084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 299078485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 299178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2992e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2993e705c121SKalle Valo 2994e705c121SKalle Valo spin_lock(&rxq->lock); 2995e705c121SKalle Valo 29960307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2997e705c121SKalle Valo 2998e705c121SKalle Valo for (i = rxq->read, j = 0; 2999e705c121SKalle Valo i != r && j < allocated_rb_nums; 3000e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3001e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3002e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3003e705c121SKalle Valo 300459a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 300559a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 3006e705c121SKalle Valo 3007e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3008e705c121SKalle Valo 3009e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3010e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3011e705c121SKalle Valo rb = (void *)(*data)->data; 3012e705c121SKalle Valo rb->index = cpu_to_le32(i); 3013e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3014e705c121SKalle Valo 3015e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3016e705c121SKalle Valo } 3017e705c121SKalle Valo 3018e705c121SKalle Valo spin_unlock(&rxq->lock); 3019e705c121SKalle Valo 3020e705c121SKalle Valo return rb_len; 3021e705c121SKalle Valo } 3022e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3023e705c121SKalle Valo 3024e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3025e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3026e705c121SKalle Valo { 3027e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3028e705c121SKalle Valo __le32 *val; 3029e705c121SKalle Valo int i; 3030e705c121SKalle Valo 3031e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3032e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3033e705c121SKalle Valo val = (void *)(*data)->data; 3034e705c121SKalle Valo 3035e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3036e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3037e705c121SKalle Valo 3038e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3039e705c121SKalle Valo 3040e705c121SKalle Valo return csr_len; 3041e705c121SKalle Valo } 3042e705c121SKalle Valo 3043e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3044e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3045e705c121SKalle Valo { 3046e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3047e705c121SKalle Valo __le32 *val; 3048e705c121SKalle Valo int i; 3049e705c121SKalle Valo 30501ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3051e705c121SKalle Valo return 0; 3052e705c121SKalle Valo 3053e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3054e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3055e705c121SKalle Valo val = (void *)(*data)->data; 3056e705c121SKalle Valo 3057286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3058723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3059723b45e2SLiad Kaufman i += sizeof(u32)) 3060e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3061723b45e2SLiad Kaufman else 3062ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3063ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3064723b45e2SLiad Kaufman i += sizeof(u32)) 3065723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3066723b45e2SLiad Kaufman i)); 3067e705c121SKalle Valo 30681ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3069e705c121SKalle Valo 3070e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3071e705c121SKalle Valo 3072e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3073e705c121SKalle Valo } 3074e705c121SKalle Valo 3075e705c121SKalle Valo static u32 3076e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3077e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3078e705c121SKalle Valo u32 monitor_len) 3079e705c121SKalle Valo { 3080e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3081e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3082e705c121SKalle Valo u32 i; 3083e705c121SKalle Valo 30841ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3085e705c121SKalle Valo return 0; 3086e705c121SKalle Valo 3087ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3088e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3089ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 309014ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3091ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3092e705c121SKalle Valo 30931ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3094e705c121SKalle Valo 3095e705c121SKalle Valo return monitor_len; 3096e705c121SKalle Valo } 3097e705c121SKalle Valo 30987a14c23dSSara Sharon static void 30997a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31007a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31017a14c23dSSara Sharon { 3102c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 31037a14c23dSSara Sharon 3104286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3105c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3106c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3107c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3108c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 310991c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 311091c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 311191c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 311291c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 31137a14c23dSSara Sharon } else { 31147a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 31157a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31167a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31177a14c23dSSara Sharon } 3118c88580e1SShahar S Matityahu 3119c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31207a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31217a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31227a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31237a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3124286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3125c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3126c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3127c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3128cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3129cc598782SRotem Saado write_ptr_val >>= 2; 3130c88580e1SShahar S Matityahu } 3131c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31327a14c23dSSara Sharon } 31337a14c23dSSara Sharon 3134e705c121SKalle Valo static u32 3135e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3136e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3137e705c121SKalle Valo u32 monitor_len) 3138e705c121SKalle Valo { 313969f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3140e705c121SKalle Valo u32 len = 0; 3141e705c121SKalle Valo 314291c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 314369f0e505SShahar S Matityahu (fw_mon->size && 3144286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3145286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3146e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3147e705c121SKalle Valo 3148e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3149e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 31507a14c23dSSara Sharon 31517a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3152e705c121SKalle Valo 3153e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 315469f0e505SShahar S Matityahu if (fw_mon->size) { 315569f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 315669f0e505SShahar S Matityahu monitor_len = fw_mon->size; 315791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 31587a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3159e705c121SKalle Valo /* 3160e705c121SKalle Valo * Update pointers to reflect actual values after 3161e705c121SKalle Valo * shifting 3162e705c121SKalle Valo */ 316391c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3164fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3165fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 316691c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3167fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3168fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3169fd527eb5SGolan Ben Ami } else { 3170e705c121SKalle Valo base = iwl_read_prph(trans, base) << 317191c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3172fd527eb5SGolan Ben Ami } 3173fd527eb5SGolan Ben Ami 3174e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3175e705c121SKalle Valo monitor_len / sizeof(u32)); 317691c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3177e705c121SKalle Valo monitor_len = 3178e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3179e705c121SKalle Valo fw_mon_data, 3180e705c121SKalle Valo monitor_len); 3181e705c121SKalle Valo } else { 3182e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3183e705c121SKalle Valo monitor_len = 0; 3184e705c121SKalle Valo } 3185e705c121SKalle Valo 3186e705c121SKalle Valo len += monitor_len; 3187e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3188e705c121SKalle Valo } 3189e705c121SKalle Valo 3190e705c121SKalle Valo return len; 3191e705c121SKalle Valo } 3192e705c121SKalle Valo 319393079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3194e705c121SKalle Valo { 319569f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3196da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3197da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 319869f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 319969f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 320091c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3201da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3202e705c121SKalle Valo 320391c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 320491c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3205fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3206fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 320791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3208fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3209fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3210fd527eb5SGolan Ben Ami 3211fd527eb5SGolan Ben Ami monitor_len = 3212fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 321391c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3214fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3215fd527eb5SGolan Ben Ami } else { 321691c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 321791c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3218e705c121SKalle Valo 3219e705c121SKalle Valo base = iwl_read_prph(trans, base) << 322091c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3221e705c121SKalle Valo end = iwl_read_prph(trans, end) << 322291c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3223e705c121SKalle Valo 3224e705c121SKalle Valo /* Make "end" point to the actual end */ 3225286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3226fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 322791c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 322891c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3229e705c121SKalle Valo monitor_len = end - base; 3230fd527eb5SGolan Ben Ami } 3231da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3232da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3233e705c121SKalle Valo monitor_len; 3234da752717SShahar S Matityahu return monitor_len; 3235e705c121SKalle Valo } 3236da752717SShahar S Matityahu return 0; 3237da752717SShahar S Matityahu } 3238da752717SShahar S Matityahu 3239fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3240fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3241fdb70083SJohannes Berg u32 dump_mask, 3242fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3243fdb70083SJohannes Berg void *sanitize_ctx) 3244da752717SShahar S Matityahu { 3245da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3246da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 32474f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3248da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3249da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3250fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3251da752717SShahar S Matityahu int i, ptr; 3252da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3253286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 325479f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 325579f033f6SSara Sharon 325679f033f6SSara Sharon if (!dump_mask) 325779f033f6SSara Sharon return NULL; 3258da752717SShahar S Matityahu 3259da752717SShahar S Matityahu /* transport dump header */ 3260da752717SShahar S Matityahu len = sizeof(*dump_data); 3261da752717SShahar S Matityahu 3262da752717SShahar S Matityahu /* host commands */ 3263e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3264da752717SShahar S Matityahu len += sizeof(*data) + 32658672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 32668672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3267da752717SShahar S Matityahu 3268da752717SShahar S Matityahu /* FW monitor */ 3269fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3270da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3271e705c121SKalle Valo 3272e705c121SKalle Valo /* CSR registers */ 327379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3274e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3275e705c121SKalle Valo 3276e705c121SKalle Valo /* FH registers */ 327779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3278286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3279723b45e2SLiad Kaufman len += sizeof(*data) + 3280ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3281ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3282723b45e2SLiad Kaufman else 3283723b45e2SLiad Kaufman len += sizeof(*data) + 3284520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3285520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3286520f03eaSShahar S Matityahu } 3287e705c121SKalle Valo 3288e705c121SKalle Valo if (dump_rbs) { 328978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 329078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3291e705c121SKalle Valo /* RBs */ 32920307c839SGolan Ben Ami num_rbs = 32930307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3294e705c121SKalle Valo & 0x0FFF; 329578485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3296e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3297e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3298e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3299e705c121SKalle Valo } 3300e705c121SKalle Valo 33015538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3302286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3303505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 33045538409bSLiad Kaufman len += sizeof(*data) + 33055538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3306505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 33075538409bSLiad Kaufman 3308e705c121SKalle Valo dump_data = vzalloc(len); 3309e705c121SKalle Valo if (!dump_data) 3310e705c121SKalle Valo return NULL; 3311e705c121SKalle Valo 3312e705c121SKalle Valo len = 0; 3313e705c121SKalle Valo data = (void *)dump_data->data; 3314520f03eaSShahar S Matityahu 3315e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3316885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3317520f03eaSShahar S Matityahu 3318e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3319e705c121SKalle Valo txcmd = (void *)data->data; 3320e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3321bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3322bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33230cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 332408326a97SJohannes Berg u8 tfdidx; 3325e705c121SKalle Valo u32 caplen, cmdlen; 3326e705c121SKalle Valo 332708326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 332808326a97SJohannes Berg tfdidx = idx; 332908326a97SJohannes Berg else 333008326a97SJohannes Berg tfdidx = ptr; 333108326a97SJohannes Berg 3332520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 333308326a97SJohannes Berg (u8 *)cmdq->tfds + 333408326a97SJohannes Berg tfd_size * tfdidx); 3335e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3336e705c121SKalle Valo 3337e705c121SKalle Valo if (cmdlen) { 3338e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3339e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3340e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3341520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3342520f03eaSShahar S Matityahu caplen); 3343fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3344fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3345fdb70083SJohannes Berg txcmd->data, 3346fdb70083SJohannes Berg caplen); 3347e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3348e705c121SKalle Valo } 3349e705c121SKalle Valo 33500cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3351e705c121SKalle Valo } 3352e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3353e705c121SKalle Valo 3354e705c121SKalle Valo data->len = cpu_to_le32(len); 3355e705c121SKalle Valo len += sizeof(*data); 3356e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3357520f03eaSShahar S Matityahu } 3358e705c121SKalle Valo 335979f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3360e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 336179f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3362e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3363e705c121SKalle Valo if (dump_rbs) 3364e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3365e705c121SKalle Valo 33665538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3367286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 336879b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3369505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 33705538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3371505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 33725538409bSLiad Kaufman 33735538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 33745538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 33755538409bSLiad Kaufman paging = (void *)data->data; 33765538409bSLiad Kaufman paging->index = cpu_to_le32(i); 33775538409bSLiad Kaufman memcpy(paging->data, 3378505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 33795538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33805538409bSLiad Kaufman 33815538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33825538409bSLiad Kaufman } 33835538409bSLiad Kaufman } 338479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3385e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3386e705c121SKalle Valo 3387e705c121SKalle Valo dump_data->len = len; 3388e705c121SKalle Valo 3389e705c121SKalle Valo return dump_data; 3390e705c121SKalle Valo } 3391e705c121SKalle Valo 33923161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 33934cbb8e50SLuciano Coelho { 33943161a34dSMordechay Goodstein if (enable) 33953161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 33963161a34dSMordechay Goodstein else 33973161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 33984cbb8e50SLuciano Coelho } 33994cbb8e50SLuciano Coelho 34003161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 34014cbb8e50SLuciano Coelho { 34023161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 34033161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 34043161a34dSMordechay Goodstein 34053161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 34063161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3407*571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3408*571836a0SMike Golant sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3409*571836a0SMike Golant else 34103161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 34113161a34dSMordechay Goodstein } else { 34123161a34dSMordechay Goodstein inta_addr = CSR_INT; 34133161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 34144cbb8e50SLuciano Coelho } 34153161a34dSMordechay Goodstein 34163161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 34173161a34dSMordechay Goodstein } 34184cbb8e50SLuciano Coelho 3419623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3420623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3421623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3422623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3423623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3424623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3425623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3426623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3427623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 34287f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3429623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3430623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3431870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3432623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3433623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3434623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3435623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3436623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3437d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 34383161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 34393161a34dSMordechay Goodstein .sync_nmi = iwl_trans_pcie_sync_nmi \ 3440623e7766SSara Sharon 3441e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3442623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3443e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3444e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3445e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3446e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3447e705c121SKalle Valo 344813f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3449e705c121SKalle Valo 3450e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3451a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3452e705c121SKalle Valo 3453e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3454e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3455e705c121SKalle Valo 345642db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 345742db09c1SLiad Kaufman 3458d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3459d6d517b7SSara Sharon 3460a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 34610cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3462f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3463f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3464f7805b33SLior Cohen #endif 3465623e7766SSara Sharon }; 3466e705c121SKalle Valo 3467623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3468623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3469623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3470eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3471eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 347277c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3473e705c121SKalle Valo 347413f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3475e705c121SKalle Valo 34760cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3477a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3478623e7766SSara Sharon 3479a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3480ba7136f3SAlex Malamud 34810cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 34820cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3483d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 348492536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 34856654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 34869dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3487f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3488f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3489f7805b33SLior Cohen #endif 3490e705c121SKalle Valo }; 3491e705c121SKalle Valo 3492e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3493e705c121SKalle Valo const struct pci_device_id *ent, 34947e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3495e705c121SKalle Valo { 3496e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3497e705c121SKalle Valo struct iwl_trans *trans; 3498fda1bd0dSMordechay Goodstein int ret, addr_size; 3499a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3500f00c3f9eSJohannes Berg void __iomem * const *table; 3501a89c72ffSJohannes Berg 3502fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3503a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3504e705c121SKalle Valo 35055a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 35065a41a86cSSharon Dvir if (ret) 35075a41a86cSSharon Dvir return ERR_PTR(ret); 35085a41a86cSSharon Dvir 3509a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3510fda1bd0dSMordechay Goodstein cfg_trans); 3511e705c121SKalle Valo if (!trans) 3512e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3513e705c121SKalle Valo 3514e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3515e705c121SKalle Valo 3516e705c121SKalle Valo trans_pcie->trans = trans; 3517326477e4SJohannes Berg trans_pcie->opmode_down = true; 3518e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3519e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3520cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3521e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3522e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3523906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 35248188a18eSJohannes Berg 35258188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35268188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35278188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35288188a18eSJohannes Berg ret = -ENOMEM; 35298188a18eSJohannes Berg goto out_free_trans; 35308188a18eSJohannes Berg } 35318188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35328188a18eSJohannes Berg 3533c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3534e705c121SKalle Valo 35357e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3536e705c121SKalle Valo /* 3537e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3538e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3539e705c121SKalle Valo * lot of power. 3540e705c121SKalle Valo */ 3541e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3542e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3543e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3544e705c121SKalle Valo } 3545e705c121SKalle Valo 35469416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 35479416560eSGolan Ben Ami 3548e705c121SKalle Valo pci_set_master(pdev); 3549e705c121SKalle Valo 3550885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3551ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3552e705c121SKalle Valo if (ret) { 3553ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3554e705c121SKalle Valo /* both attempts failed: */ 3555e705c121SKalle Valo if (ret) { 3556e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 35575a41a86cSSharon Dvir goto out_no_pci; 3558e705c121SKalle Valo } 3559e705c121SKalle Valo } 3560e705c121SKalle Valo 35615a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3562e705c121SKalle Valo if (ret) { 35635a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 35645a41a86cSSharon Dvir goto out_no_pci; 3565e705c121SKalle Valo } 3566e705c121SKalle Valo 3567f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3568f00c3f9eSJohannes Berg if (!table) { 35695a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3570f00c3f9eSJohannes Berg ret = -ENOMEM; 3571f00c3f9eSJohannes Berg goto out_no_pci; 3572f00c3f9eSJohannes Berg } 3573f00c3f9eSJohannes Berg 3574f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3575f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3576f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3577e705c121SKalle Valo ret = -ENODEV; 35785a41a86cSSharon Dvir goto out_no_pci; 3579e705c121SKalle Valo } 3580e705c121SKalle Valo 3581e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3582e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3583e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3584e705c121SKalle Valo 3585e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3586e705c121SKalle Valo iwl_disable_interrupts(trans); 3587e705c121SKalle Valo 3588e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35899a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35909a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35919a098a89SRajat Jain ret = -EIO; 35929a098a89SRajat Jain goto out_no_pci; 35939a098a89SRajat Jain } 35949a098a89SRajat Jain 3595e705c121SKalle Valo /* 3596e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3597e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3598e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3599e705c121SKalle Valo * in the old format. 3600e705c121SKalle Valo */ 36014adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3602e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3603e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3604e705c121SKalle Valo 360599be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 360699be6166SLuca Coelho 36077e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3608e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3609e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3610e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3611e705c121SKalle Valo 3612e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3613e5f3f215SHaim Dreyfuss 3614c239feecSJohannes Berg 36152e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36162388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36172388bd7bSDan Carpenter if (ret) 36185a41a86cSSharon Dvir goto out_no_pci; 36192e5d4a8fSHaim Dreyfuss } else { 3620e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3621e705c121SKalle Valo if (ret) 36225a41a86cSSharon Dvir goto out_no_pci; 3623e705c121SKalle Valo 36245a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36255a41a86cSSharon Dvir iwl_pcie_isr, 3626e705c121SKalle Valo iwl_pcie_irq_handler, 3627e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3628e705c121SKalle Valo if (ret) { 3629e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3630e705c121SKalle Valo goto out_free_ict; 3631e705c121SKalle Valo } 36322e5d4a8fSHaim Dreyfuss } 3633e705c121SKalle Valo 3634f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3635f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3636f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3637f7805b33SLior Cohen #endif 3638f7805b33SLior Cohen 3639a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3640a9248de4SShahar S Matityahu 3641e705c121SKalle Valo return trans; 3642e705c121SKalle Valo 3643e705c121SKalle Valo out_free_ict: 3644e705c121SKalle Valo iwl_pcie_free_ict(trans); 3645e705c121SKalle Valo out_no_pci: 36468188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 36478188a18eSJohannes Berg out_free_trans: 3648e705c121SKalle Valo iwl_trans_free(trans); 3649e705c121SKalle Valo return ERR_PTR(ret); 3650e705c121SKalle Valo } 3651