1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 12e705c121SKalle Valo * 13e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 14e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 15e705c121SKalle Valo * published by the Free Software Foundation. 16e705c121SKalle Valo * 17e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 18e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 19e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20e705c121SKalle Valo * General Public License for more details. 21e705c121SKalle Valo * 22e705c121SKalle Valo * The full GNU General Public License is included in this distribution 23e705c121SKalle Valo * in the file called COPYING. 24e705c121SKalle Valo * 25e705c121SKalle Valo * Contact Information: 26cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 27e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 28e705c121SKalle Valo * 29e705c121SKalle Valo * BSD LICENSE 30e705c121SKalle Valo * 31e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 32e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 33afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 34ea695b7cSShaul Triebitz * Copyright(c) 2018 - 2019 Intel Corporation 35e705c121SKalle Valo * All rights reserved. 36e705c121SKalle Valo * 37e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 38e705c121SKalle Valo * modification, are permitted provided that the following conditions 39e705c121SKalle Valo * are met: 40e705c121SKalle Valo * 41e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 42e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 43e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 44e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 45e705c121SKalle Valo * the documentation and/or other materials provided with the 46e705c121SKalle Valo * distribution. 47e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 48e705c121SKalle Valo * contributors may be used to endorse or promote products derived 49e705c121SKalle Valo * from this software without specific prior written permission. 50e705c121SKalle Valo * 51e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 52e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 53e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 54e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 55e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 56e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 57e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 61e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e705c121SKalle Valo * 63e705c121SKalle Valo *****************************************************************************/ 64e705c121SKalle Valo #include <linux/pci.h> 65e705c121SKalle Valo #include <linux/interrupt.h> 66e705c121SKalle Valo #include <linux/debugfs.h> 67e705c121SKalle Valo #include <linux/sched.h> 68e705c121SKalle Valo #include <linux/bitops.h> 69e705c121SKalle Valo #include <linux/gfp.h> 70e705c121SKalle Valo #include <linux/vmalloc.h> 7149564a80SLuca Coelho #include <linux/module.h> 72f7805b33SLior Cohen #include <linux/wait.h> 73e705c121SKalle Valo 74e705c121SKalle Valo #include "iwl-drv.h" 75e705c121SKalle Valo #include "iwl-trans.h" 76e705c121SKalle Valo #include "iwl-csr.h" 77e705c121SKalle Valo #include "iwl-prph.h" 78e705c121SKalle Valo #include "iwl-scd.h" 79e705c121SKalle Valo #include "iwl-agn-hw.h" 80d962f9b1SJohannes Berg #include "fw/error-dump.h" 81520f03eaSShahar S Matityahu #include "fw/dbg.h" 82a89c72ffSJohannes Berg #include "fw/api/tx.h" 83e705c121SKalle Valo #include "internal.h" 84e705c121SKalle Valo #include "iwl-fh.h" 85e705c121SKalle Valo 86e705c121SKalle Valo /* extended range in FW SRAM */ 87e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 89e705c121SKalle Valo 904290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 91a6d24fadSRajat Jain { 92c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 93c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 94c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 95a6d24fadSRajat Jain #define PREFIX_LEN 32 96a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 97a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 98a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 99a6d24fadSRajat Jain char *prefix; 100a6d24fadSRajat Jain 101a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 102a6d24fadSRajat Jain return; 103a6d24fadSRajat Jain 104a6d24fadSRajat Jain /* Should be a multiple of 4 */ 105a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 106c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 107c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 108c4d3f2eeSLuca Coelho 109a6d24fadSRajat Jain /* Alloc a max size buffer */ 110a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 111c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 112c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 113c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 114c4d3f2eeSLuca Coelho 115a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 116a6d24fadSRajat Jain if (!buf) 117a6d24fadSRajat Jain return; 118a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 119a6d24fadSRajat Jain 120a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain /* Print wifi device registers */ 123a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 124a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 125a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 126a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 127a6d24fadSRajat Jain goto err_read; 128a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129a6d24fadSRajat Jain 130a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 131c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 132a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 133a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 134a6d24fadSRajat Jain 135a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 136a6d24fadSRajat Jain if (pos) { 137a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 138a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 139a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 140a6d24fadSRajat Jain goto err_read; 141a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 142a6d24fadSRajat Jain 32, 4, buf, i, 0); 143a6d24fadSRajat Jain } 144a6d24fadSRajat Jain 145a6d24fadSRajat Jain /* Print parent device registers next */ 146a6d24fadSRajat Jain if (!pdev->bus->self) 147a6d24fadSRajat Jain goto out; 148a6d24fadSRajat Jain 149a6d24fadSRajat Jain pdev = pdev->bus->self; 150a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 151a6d24fadSRajat Jain 152a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 153a6d24fadSRajat Jain pci_name(pdev)); 154c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 155a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 156a6d24fadSRajat Jain goto err_read; 157a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 158a6d24fadSRajat Jain 159a6d24fadSRajat Jain /* Print root port AER registers */ 160a6d24fadSRajat Jain pos = 0; 161a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 162a6d24fadSRajat Jain if (pdev) 163a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 164a6d24fadSRajat Jain if (pos) { 165a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 166a6d24fadSRajat Jain pci_name(pdev)); 167a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 168a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 169a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 170a6d24fadSRajat Jain goto err_read; 171a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 172a6d24fadSRajat Jain 4, buf, i, 0); 173a6d24fadSRajat Jain } 174f3402d6dSSara Sharon goto out; 175a6d24fadSRajat Jain 176a6d24fadSRajat Jain err_read: 177a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 178a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 179a6d24fadSRajat Jain out: 180a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 181a6d24fadSRajat Jain kfree(buf); 182a6d24fadSRajat Jain } 183a6d24fadSRajat Jain 184870c2a11SGolan Ben Ami static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans) 185870c2a11SGolan Ben Ami { 186870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 187286ca8ebSLuca Coelho iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset, 188286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_sw_reset)); 189870c2a11SGolan Ben Ami usleep_range(5000, 6000); 190870c2a11SGolan Ben Ami } 191870c2a11SGolan Ben Ami 192e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 193e705c121SKalle Valo { 19469f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 195e705c121SKalle Valo 19669f0e505SShahar S Matityahu if (!fw_mon->size) 19769f0e505SShahar S Matityahu return; 19869f0e505SShahar S Matityahu 19969f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 20069f0e505SShahar S Matityahu fw_mon->physical); 20169f0e505SShahar S Matityahu 20269f0e505SShahar S Matityahu fw_mon->block = NULL; 20369f0e505SShahar S Matityahu fw_mon->physical = 0; 20469f0e505SShahar S Matityahu fw_mon->size = 0; 205e705c121SKalle Valo } 206e705c121SKalle Valo 20788964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 20888964b2eSSara Sharon u8 max_power, u8 min_power) 209e705c121SKalle Valo { 21069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 21169f0e505SShahar S Matityahu void *block = NULL; 21269f0e505SShahar S Matityahu dma_addr_t physical = 0; 213e705c121SKalle Valo u32 size = 0; 214e705c121SKalle Valo u8 power; 215e705c121SKalle Valo 21669f0e505SShahar S Matityahu if (fw_mon->size) 21769f0e505SShahar S Matityahu return; 21869f0e505SShahar S Matityahu 21988964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 220e705c121SKalle Valo size = BIT(power); 22169f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 2222d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 22369f0e505SShahar S Matityahu if (!block) 224e705c121SKalle Valo continue; 225e705c121SKalle Valo 226e705c121SKalle Valo IWL_INFO(trans, 227c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 228c5f97542SShahar S Matityahu size); 229e705c121SKalle Valo break; 230e705c121SKalle Valo } 231e705c121SKalle Valo 23269f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 233e705c121SKalle Valo return; 234e705c121SKalle Valo 235e705c121SKalle Valo if (power != max_power) 236e705c121SKalle Valo IWL_ERR(trans, 237e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 238e705c121SKalle Valo (unsigned long)BIT(power - 10), 239e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 240e705c121SKalle Valo 24169f0e505SShahar S Matityahu fw_mon->block = block; 24269f0e505SShahar S Matityahu fw_mon->physical = physical; 24369f0e505SShahar S Matityahu fw_mon->size = size; 24488964b2eSSara Sharon } 24588964b2eSSara Sharon 24688964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 24788964b2eSSara Sharon { 24888964b2eSSara Sharon if (!max_power) { 24988964b2eSSara Sharon /* default max_power is maximum */ 25088964b2eSSara Sharon max_power = 26; 25188964b2eSSara Sharon } else { 25288964b2eSSara Sharon max_power += 11; 25388964b2eSSara Sharon } 25488964b2eSSara Sharon 25588964b2eSSara Sharon if (WARN(max_power > 26, 25688964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 25788964b2eSSara Sharon max_power)) 25888964b2eSSara Sharon return; 25988964b2eSSara Sharon 26069f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 26188964b2eSSara Sharon return; 26288964b2eSSara Sharon 26388964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 264e705c121SKalle Valo } 265e705c121SKalle Valo 266e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 267e705c121SKalle Valo { 268e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 269e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 270e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 271e705c121SKalle Valo } 272e705c121SKalle Valo 273e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 274e705c121SKalle Valo { 275e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 276e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 277e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 278e705c121SKalle Valo } 279e705c121SKalle Valo 280e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 281e705c121SKalle Valo { 282e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 283e705c121SKalle Valo return; 284e705c121SKalle Valo 285e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 286e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 287e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 288e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 289e705c121SKalle Valo else 290e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 291e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 292e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 293e705c121SKalle Valo } 294e705c121SKalle Valo 295e705c121SKalle Valo /* PCI registers */ 296e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 297e705c121SKalle Valo 298eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 299e705c121SKalle Valo { 300e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301e705c121SKalle Valo u16 lctl; 302e705c121SKalle Valo u16 cap; 303e705c121SKalle Valo 304e705c121SKalle Valo /* 305e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 306e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 307e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 308e705c121SKalle Valo * costs negligible amount of power savings. 309e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 310e705c121SKalle Valo * power savings, even without L1. 311e705c121SKalle Valo */ 312e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 313e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 3143d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 315e705c121SKalle Valo else 3163d1b28fdSLuca Coelho iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 317e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 318e705c121SKalle Valo 319e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 320e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 321d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 322e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 323e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 324e705c121SKalle Valo } 325e705c121SKalle Valo 326e705c121SKalle Valo /* 327e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 328e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 329e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 330e705c121SKalle Valo */ 331e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 332e705c121SKalle Valo { 33352b6e168SEmmanuel Grumbach int ret; 33452b6e168SEmmanuel Grumbach 335e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 336e705c121SKalle Valo 337e705c121SKalle Valo /* 338e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 339e705c121SKalle Valo * bits already set by default after reset. 340e705c121SKalle Valo */ 341e705c121SKalle Valo 342e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 343286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 344e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 345e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 346e705c121SKalle Valo 347e705c121SKalle Valo /* 348e705c121SKalle Valo * Disable L0s without affecting L1; 349e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 350e705c121SKalle Valo */ 351e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 352e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 353e705c121SKalle Valo 354e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 355e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 356e705c121SKalle Valo 357e705c121SKalle Valo /* 358e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 359e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 360e705c121SKalle Valo */ 361e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 362e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 363e705c121SKalle Valo 364e705c121SKalle Valo iwl_pcie_apm_config(trans); 365e705c121SKalle Valo 366e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 367286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 36877d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 369e705c121SKalle Valo 3707d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 371c96b5eecSJohannes Berg if (ret) 37252b6e168SEmmanuel Grumbach return ret; 373e705c121SKalle Valo 374e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 375e705c121SKalle Valo /* 376e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 377e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 378e705c121SKalle Valo * not related to host_interrupt_operation_mode. 379e705c121SKalle Valo * 380e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 381e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 382e705c121SKalle Valo * that we wake up from L1 on time. 383e705c121SKalle Valo * 384e705c121SKalle Valo * This looks weird: read twice the same register, discard the 385e705c121SKalle Valo * value, set a bit, and yet again, read that same register 386e705c121SKalle Valo * just to discard the value. But that's the way the hardware 387e705c121SKalle Valo * seems to like it. 388e705c121SKalle Valo */ 389e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 390e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 391e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 392e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 393e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 394e705c121SKalle Valo } 395e705c121SKalle Valo 396e705c121SKalle Valo /* 397e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 398e705c121SKalle Valo * 399e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 400e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 401e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 402e705c121SKalle Valo */ 403e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 404e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 405e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 406e705c121SKalle Valo udelay(20); 407e705c121SKalle Valo 408e705c121SKalle Valo /* Disable L1-Active */ 409e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 410e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 411e705c121SKalle Valo 412e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 413e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 414e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 415e705c121SKalle Valo } 416e705c121SKalle Valo 417e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 418e705c121SKalle Valo 41952b6e168SEmmanuel Grumbach return 0; 420e705c121SKalle Valo } 421e705c121SKalle Valo 422e705c121SKalle Valo /* 423e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 424e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 425e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 426e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 427e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 428e705c121SKalle Valo */ 429e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 430e705c121SKalle Valo { 431e705c121SKalle Valo int ret; 432e705c121SKalle Valo u32 apmg_gp1_reg; 433e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 434e705c121SKalle Valo u32 dl_cfg_reg; 435e705c121SKalle Valo 436e705c121SKalle Valo /* Force XTAL ON */ 437e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 438e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 439e705c121SKalle Valo 440870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 441e705c121SKalle Valo 4427d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 443c96b5eecSJohannes Berg if (WARN_ON(ret)) { 444e705c121SKalle Valo /* Release XTAL ON request */ 445e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 446e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 447e705c121SKalle Valo return; 448e705c121SKalle Valo } 449e705c121SKalle Valo 450e705c121SKalle Valo /* 451e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 452e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 453e705c121SKalle Valo */ 454e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 455e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 456e705c121SKalle Valo 457e705c121SKalle Valo /* 458e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 459e705c121SKalle Valo * caused by APMG idle state. 460e705c121SKalle Valo */ 461e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 462e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 463e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 464e705c121SKalle Valo apmg_xtal_cfg_reg | 465e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 466e705c121SKalle Valo 467870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 468e705c121SKalle Valo 469e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 470e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 471e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 472e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 473e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 474e705c121SKalle Valo 475e705c121SKalle Valo /* Clear delay line clock power up */ 476e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 477e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 478e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 479e705c121SKalle Valo 480e705c121SKalle Valo /* 481e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 482e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 483e705c121SKalle Valo */ 484e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 486e705c121SKalle Valo 487e705c121SKalle Valo /* 488e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 489e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 490e705c121SKalle Valo */ 491e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 492286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_init_done)); 493e705c121SKalle Valo 494e705c121SKalle Valo /* Activates XTAL resources monitor */ 495e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 496e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 497e705c121SKalle Valo 498e705c121SKalle Valo /* Release XTAL ON request */ 499e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 500e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 501e705c121SKalle Valo udelay(10); 502e705c121SKalle Valo 503e705c121SKalle Valo /* Release APMG XTAL */ 504e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 505e705c121SKalle Valo apmg_xtal_cfg_reg & 506e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 507e705c121SKalle Valo } 508e705c121SKalle Valo 509e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 510e705c121SKalle Valo { 511e8c8935eSJohannes Berg int ret; 512e705c121SKalle Valo 513e705c121SKalle Valo /* stop device's busmaster DMA activity */ 514286ca8ebSLuca Coelho iwl_set_bit(trans, trans->trans_cfg->csr->addr_sw_reset, 515286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_stop_master)); 516e705c121SKalle Valo 517286ca8ebSLuca Coelho ret = iwl_poll_bit(trans, trans->trans_cfg->csr->addr_sw_reset, 518286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_master_dis), 519286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_master_dis), 100); 520e705c121SKalle Valo if (ret < 0) 521e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 522e705c121SKalle Valo 523e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 524e705c121SKalle Valo } 525e705c121SKalle Valo 526e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 527e705c121SKalle Valo { 528e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 529e705c121SKalle Valo 530e705c121SKalle Valo if (op_mode_leave) { 531e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 532e705c121SKalle Valo iwl_pcie_apm_init(trans); 533e705c121SKalle Valo 534e705c121SKalle Valo /* inform ME that we are leaving */ 535286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 536e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 537e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 538286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 53979b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 540e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 541e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 542e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 543e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 544e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 545e705c121SKalle Valo mdelay(1); 546e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 547e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 548e705c121SKalle Valo } 549e705c121SKalle Valo mdelay(5); 550e705c121SKalle Valo } 551e705c121SKalle Valo 552e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 553e705c121SKalle Valo 554e705c121SKalle Valo /* Stop device's DMA activity */ 555e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 556e705c121SKalle Valo 557e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 558e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 559e705c121SKalle Valo return; 560e705c121SKalle Valo } 561e705c121SKalle Valo 562870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 563e705c121SKalle Valo 564e705c121SKalle Valo /* 565e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 566e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 567e705c121SKalle Valo */ 568e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 569286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_init_done)); 570e705c121SKalle Valo } 571e705c121SKalle Valo 572e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 573e705c121SKalle Valo { 574e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 57552b6e168SEmmanuel Grumbach int ret; 576e705c121SKalle Valo 577e705c121SKalle Valo /* nic_init */ 578e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 57952b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 580e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 581e705c121SKalle Valo 58252b6e168SEmmanuel Grumbach if (ret) 58352b6e168SEmmanuel Grumbach return ret; 58452b6e168SEmmanuel Grumbach 585e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 586e705c121SKalle Valo 587e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 588e705c121SKalle Valo 589e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 590e705c121SKalle Valo iwl_pcie_rx_init(trans); 591e705c121SKalle Valo 592e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 593e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 594e705c121SKalle Valo return -ENOMEM; 595e705c121SKalle Valo 596286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 597e705c121SKalle Valo /* enable shadow regs in HW */ 598e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 599e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 600e705c121SKalle Valo } 601e705c121SKalle Valo 602e705c121SKalle Valo return 0; 603e705c121SKalle Valo } 604e705c121SKalle Valo 605e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 606e705c121SKalle Valo 607e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 608e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 609e705c121SKalle Valo { 610e705c121SKalle Valo int ret; 611e705c121SKalle Valo 612e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 613e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 614e705c121SKalle Valo 615e705c121SKalle Valo /* See if we got it */ 616e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 617e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 618e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 619e705c121SKalle Valo HW_READY_TIMEOUT); 620e705c121SKalle Valo 621e705c121SKalle Valo if (ret >= 0) 622e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 623e705c121SKalle Valo 624e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 625e705c121SKalle Valo return ret; 626e705c121SKalle Valo } 627e705c121SKalle Valo 628e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 629eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 630e705c121SKalle Valo { 631e705c121SKalle Valo int ret; 632e705c121SKalle Valo int t = 0; 633e705c121SKalle Valo int iter; 634e705c121SKalle Valo 635e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 636e705c121SKalle Valo 637e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 638e705c121SKalle Valo /* If the card is ready, exit 0 */ 639e705c121SKalle Valo if (ret >= 0) 640e705c121SKalle Valo return 0; 641e705c121SKalle Valo 642e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 643e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 644192185d6SJohannes Berg usleep_range(1000, 2000); 645e705c121SKalle Valo 646e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 647e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 648e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 649e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 650e705c121SKalle Valo 651e705c121SKalle Valo do { 652e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 653e705c121SKalle Valo if (ret >= 0) 654e705c121SKalle Valo return 0; 655e705c121SKalle Valo 656e705c121SKalle Valo usleep_range(200, 1000); 657e705c121SKalle Valo t += 200; 658e705c121SKalle Valo } while (t < 150000); 659e705c121SKalle Valo msleep(25); 660e705c121SKalle Valo } 661e705c121SKalle Valo 662e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 663e705c121SKalle Valo 664e705c121SKalle Valo return ret; 665e705c121SKalle Valo } 666e705c121SKalle Valo 667e705c121SKalle Valo /* 668e705c121SKalle Valo * ucode 669e705c121SKalle Valo */ 670564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 671564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 672564cdce7SSara Sharon u32 byte_cnt) 673e705c121SKalle Valo { 674bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 675e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 676e705c121SKalle Valo 677bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 678e705c121SKalle Valo dst_addr); 679e705c121SKalle Valo 680bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 681e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 682e705c121SKalle Valo 683bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 684e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 685e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 686e705c121SKalle Valo 687bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 688bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 689bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 690e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 691e705c121SKalle Valo 692bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 693e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 694e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 695e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 696564cdce7SSara Sharon } 697e705c121SKalle Valo 698564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 699564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 700564cdce7SSara Sharon u32 byte_cnt) 701564cdce7SSara Sharon { 702564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 703564cdce7SSara Sharon unsigned long flags; 704564cdce7SSara Sharon int ret; 705564cdce7SSara Sharon 706564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 707564cdce7SSara Sharon 708564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 709564cdce7SSara Sharon return -EIO; 710564cdce7SSara Sharon 711564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 712564cdce7SSara Sharon byte_cnt); 713bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 714bac842daSEmmanuel Grumbach 715e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 716e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 717e705c121SKalle Valo if (!ret) { 718e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 719fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 720e705c121SKalle Valo return -ETIMEDOUT; 721e705c121SKalle Valo } 722e705c121SKalle Valo 723e705c121SKalle Valo return 0; 724e705c121SKalle Valo } 725e705c121SKalle Valo 726e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 727e705c121SKalle Valo const struct fw_desc *section) 728e705c121SKalle Valo { 729e705c121SKalle Valo u8 *v_addr; 730e705c121SKalle Valo dma_addr_t p_addr; 731e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 732e705c121SKalle Valo int ret = 0; 733e705c121SKalle Valo 734e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 735e705c121SKalle Valo section_num); 736e705c121SKalle Valo 737e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 738e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 739e705c121SKalle Valo if (!v_addr) { 740e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 741e705c121SKalle Valo chunk_sz = PAGE_SIZE; 742e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 743e705c121SKalle Valo &p_addr, GFP_KERNEL); 744e705c121SKalle Valo if (!v_addr) 745e705c121SKalle Valo return -ENOMEM; 746e705c121SKalle Valo } 747e705c121SKalle Valo 748e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 749e705c121SKalle Valo u32 copy_size, dst_addr; 750e705c121SKalle Valo bool extended_addr = false; 751e705c121SKalle Valo 752e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 753e705c121SKalle Valo dst_addr = section->offset + offset; 754e705c121SKalle Valo 755e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 756e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 757e705c121SKalle Valo extended_addr = true; 758e705c121SKalle Valo 759e705c121SKalle Valo if (extended_addr) 760e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 761e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 762e705c121SKalle Valo 763e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 764e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 765e705c121SKalle Valo copy_size); 766e705c121SKalle Valo 767e705c121SKalle Valo if (extended_addr) 768e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 769e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 770e705c121SKalle Valo 771e705c121SKalle Valo if (ret) { 772e705c121SKalle Valo IWL_ERR(trans, 773e705c121SKalle Valo "Could not load the [%d] uCode section\n", 774e705c121SKalle Valo section_num); 775e705c121SKalle Valo break; 776e705c121SKalle Valo } 777e705c121SKalle Valo } 778e705c121SKalle Valo 779e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 780e705c121SKalle Valo return ret; 781e705c121SKalle Valo } 782e705c121SKalle Valo 783e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 784e705c121SKalle Valo const struct fw_img *image, 785e705c121SKalle Valo int cpu, 786e705c121SKalle Valo int *first_ucode_section) 787e705c121SKalle Valo { 788e705c121SKalle Valo int shift_param; 789e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 790e705c121SKalle Valo u32 val, last_read_idx = 0; 791e705c121SKalle Valo 792e705c121SKalle Valo if (cpu == 1) { 793e705c121SKalle Valo shift_param = 0; 794e705c121SKalle Valo *first_ucode_section = 0; 795e705c121SKalle Valo } else { 796e705c121SKalle Valo shift_param = 16; 797e705c121SKalle Valo (*first_ucode_section)++; 798e705c121SKalle Valo } 799e705c121SKalle Valo 800eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 801e705c121SKalle Valo last_read_idx = i; 802e705c121SKalle Valo 803e705c121SKalle Valo /* 804e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 805e705c121SKalle Valo * CPU1 to CPU2. 806e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 807e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 808e705c121SKalle Valo */ 809e705c121SKalle Valo if (!image->sec[i].data || 810e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 811e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 812e705c121SKalle Valo IWL_DEBUG_FW(trans, 813e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 814e705c121SKalle Valo i); 815e705c121SKalle Valo break; 816e705c121SKalle Valo } 817e705c121SKalle Valo 818e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 819e705c121SKalle Valo if (ret) 820e705c121SKalle Valo return ret; 821e705c121SKalle Valo 822d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 823e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 824e705c121SKalle Valo val = val | (sec_num << shift_param); 825e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 826eda50cdeSSara Sharon 827e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 828e705c121SKalle Valo } 829e705c121SKalle Valo 830e705c121SKalle Valo *first_ucode_section = last_read_idx; 831e705c121SKalle Valo 8322aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8332aabdbdcSEmmanuel Grumbach 834286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 835e705c121SKalle Valo if (cpu == 1) 836d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 837d6a2c5c7SSara Sharon 0xFFFF); 838e705c121SKalle Valo else 839d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 840d6a2c5c7SSara Sharon 0xFFFFFFFF); 841d6a2c5c7SSara Sharon } else { 842d6a2c5c7SSara Sharon if (cpu == 1) 843d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 844d6a2c5c7SSara Sharon 0xFFFF); 845d6a2c5c7SSara Sharon else 846d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 847d6a2c5c7SSara Sharon 0xFFFFFFFF); 848d6a2c5c7SSara Sharon } 849e705c121SKalle Valo 850e705c121SKalle Valo return 0; 851e705c121SKalle Valo } 852e705c121SKalle Valo 853e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 854e705c121SKalle Valo const struct fw_img *image, 855e705c121SKalle Valo int cpu, 856e705c121SKalle Valo int *first_ucode_section) 857e705c121SKalle Valo { 858e705c121SKalle Valo int i, ret = 0; 859e705c121SKalle Valo u32 last_read_idx = 0; 860e705c121SKalle Valo 8613ce4a038SKirtika Ruchandani if (cpu == 1) 862e705c121SKalle Valo *first_ucode_section = 0; 8633ce4a038SKirtika Ruchandani else 864e705c121SKalle Valo (*first_ucode_section)++; 865e705c121SKalle Valo 866eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 867e705c121SKalle Valo last_read_idx = i; 868e705c121SKalle Valo 869e705c121SKalle Valo /* 870e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 871e705c121SKalle Valo * CPU1 to CPU2. 872e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 873e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 874e705c121SKalle Valo */ 875e705c121SKalle Valo if (!image->sec[i].data || 876e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 877e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 878e705c121SKalle Valo IWL_DEBUG_FW(trans, 879e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 880e705c121SKalle Valo i); 881e705c121SKalle Valo break; 882e705c121SKalle Valo } 883e705c121SKalle Valo 884e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 885e705c121SKalle Valo if (ret) 886e705c121SKalle Valo return ret; 887e705c121SKalle Valo } 888e705c121SKalle Valo 889e705c121SKalle Valo *first_ucode_section = last_read_idx; 890e705c121SKalle Valo 891e705c121SKalle Valo return 0; 892e705c121SKalle Valo } 893e705c121SKalle Valo 894593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 895593fae3eSShahar S Matityahu { 896593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 897593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 898593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 899593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 900593fae3eSShahar S Matityahu 901593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 902593fae3eSShahar S Matityahu return; 903593fae3eSShahar S Matityahu 904593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 905593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 906593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 907593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 908593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 909593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 910593fae3eSShahar S Matityahu 911593fae3eSShahar S Matityahu return; 912593fae3eSShahar S Matityahu } 913593fae3eSShahar S Matityahu 914593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 915593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 916593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 917593fae3eSShahar S Matityahu return; 918593fae3eSShahar S Matityahu 919593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 920593fae3eSShahar S Matityahu 921593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 922593fae3eSShahar S Matityahu alloc_id); 923593fae3eSShahar S Matityahu 924593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 925593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 926593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 927593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 928593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 929593fae3eSShahar S Matityahu } 930593fae3eSShahar S Matityahu 931c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 932e705c121SKalle Valo { 93391c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 93469f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 935e705c121SKalle Valo int i; 936e705c121SKalle Valo 937a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 938593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9397a14c23dSSara Sharon return; 9407a14c23dSSara Sharon } 9417a14c23dSSara Sharon 942e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 943e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 944e705c121SKalle Valo 945e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 946e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 947e705c121SKalle Valo else 948e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 949e705c121SKalle Valo 95091c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 951e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 952e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 953e705c121SKalle Valo 954e705c121SKalle Valo switch (dest->reg_ops[i].op) { 955e705c121SKalle Valo case CSR_ASSIGN: 956e705c121SKalle Valo iwl_write32(trans, addr, val); 957e705c121SKalle Valo break; 958e705c121SKalle Valo case CSR_SETBIT: 959e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 960e705c121SKalle Valo break; 961e705c121SKalle Valo case CSR_CLEARBIT: 962e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 963e705c121SKalle Valo break; 964e705c121SKalle Valo case PRPH_ASSIGN: 965e705c121SKalle Valo iwl_write_prph(trans, addr, val); 966e705c121SKalle Valo break; 967e705c121SKalle Valo case PRPH_SETBIT: 968e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 969e705c121SKalle Valo break; 970e705c121SKalle Valo case PRPH_CLEARBIT: 971e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 972e705c121SKalle Valo break; 973e705c121SKalle Valo case PRPH_BLOCKBIT: 974e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 975e705c121SKalle Valo IWL_ERR(trans, 976e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 977e705c121SKalle Valo val, addr); 978e705c121SKalle Valo goto monitor; 979e705c121SKalle Valo } 980e705c121SKalle Valo break; 981e705c121SKalle Valo default: 982e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 983e705c121SKalle Valo dest->reg_ops[i].op); 984e705c121SKalle Valo break; 985e705c121SKalle Valo } 986e705c121SKalle Valo } 987e705c121SKalle Valo 988e705c121SKalle Valo monitor: 98969f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 990e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 99169f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 992286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 993e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99469f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 99569f0e505SShahar S Matityahu 256) >> dest->end_shift); 99662d7476dSEmmanuel Grumbach else 99762d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 99869f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 99962d7476dSEmmanuel Grumbach dest->end_shift); 1000e705c121SKalle Valo } 1001e705c121SKalle Valo } 1002e705c121SKalle Valo 1003e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1004e705c121SKalle Valo const struct fw_img *image) 1005e705c121SKalle Valo { 1006e705c121SKalle Valo int ret = 0; 1007e705c121SKalle Valo int first_ucode_section; 1008e705c121SKalle Valo 1009e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1010e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1011e705c121SKalle Valo 1012e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1013e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1014e705c121SKalle Valo if (ret) 1015e705c121SKalle Valo return ret; 1016e705c121SKalle Valo 1017e705c121SKalle Valo if (image->is_dual_cpus) { 1018e705c121SKalle Valo /* set CPU2 header address */ 1019e705c121SKalle Valo iwl_write_prph(trans, 1020e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1021e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1022e705c121SKalle Valo 1023e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1024e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1025e705c121SKalle Valo &first_ucode_section); 1026e705c121SKalle Valo if (ret) 1027e705c121SKalle Valo return ret; 1028e705c121SKalle Valo } 1029e705c121SKalle Valo 1030e705c121SKalle Valo /* supported for 7000 only for the moment */ 1031e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1032286ca8ebSLuca Coelho trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 103369f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 1034e705c121SKalle Valo 103569f0e505SShahar S Matityahu iwl_pcie_alloc_fw_monitor(trans, 0); 103669f0e505SShahar S Matityahu if (fw_mon->size) { 1037e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 103869f0e505SShahar S Matityahu fw_mon->physical >> 4); 1039e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 104069f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 4); 1041e705c121SKalle Valo } 10427a14c23dSSara Sharon } else if (iwl_pcie_dbg_on(trans)) { 1043e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1044e705c121SKalle Valo } 1045e705c121SKalle Valo 10462aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10472aabdbdcSEmmanuel Grumbach 1048e705c121SKalle Valo /* release CPU reset */ 1049e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1050e705c121SKalle Valo 1051e705c121SKalle Valo return 0; 1052e705c121SKalle Valo } 1053e705c121SKalle Valo 1054e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1055e705c121SKalle Valo const struct fw_img *image) 1056e705c121SKalle Valo { 1057e705c121SKalle Valo int ret = 0; 1058e705c121SKalle Valo int first_ucode_section; 1059e705c121SKalle Valo 1060e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1061e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1062e705c121SKalle Valo 10637a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1064e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1065e705c121SKalle Valo 106682ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 106782ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 106882ea7966SSara Sharon 106982ea7966SSara Sharon /* 107082ea7966SSara Sharon * Set default value. On resume reading the values that were 107182ea7966SSara Sharon * zeored can provide debug data on the resume flow. 107282ea7966SSara Sharon * This is for debugging only and has no functional impact. 107382ea7966SSara Sharon */ 107482ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 107582ea7966SSara Sharon 1076e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1077e705c121SKalle Valo /* release CPU reset */ 1078e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1079e705c121SKalle Valo 1080e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1081e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1082e705c121SKalle Valo &first_ucode_section); 1083e705c121SKalle Valo if (ret) 1084e705c121SKalle Valo return ret; 1085e705c121SKalle Valo 1086e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1087e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1088e705c121SKalle Valo &first_ucode_section); 1089e705c121SKalle Valo } 1090e705c121SKalle Valo 10919ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1092727c02dfSSara Sharon { 1093326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1094727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1095326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1096326477e4SJohannes Berg bool report; 1097727c02dfSSara Sharon 1098326477e4SJohannes Berg if (hw_rfkill) { 1099326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1100326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1101326477e4SJohannes Berg } else { 1102326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1103326477e4SJohannes Berg if (trans_pcie->opmode_down) 1104326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1105326477e4SJohannes Berg } 1106727c02dfSSara Sharon 1107326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1108326477e4SJohannes Berg 1109326477e4SJohannes Berg if (prev != report) 1110326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1111727c02dfSSara Sharon 1112727c02dfSSara Sharon return hw_rfkill; 1113727c02dfSSara Sharon } 1114727c02dfSSara Sharon 11157ca00409SHaim Dreyfuss struct iwl_causes_list { 11167ca00409SHaim Dreyfuss u32 cause_num; 11177ca00409SHaim Dreyfuss u32 mask_reg; 11187ca00409SHaim Dreyfuss u8 addr; 11197ca00409SHaim Dreyfuss }; 11207ca00409SHaim Dreyfuss 11217ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11227ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11237ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11247ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11257ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11267ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11277ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 1128ff911dcaSShaul Triebitz {MSIX_HW_INT_CAUSES_REG_IML, CSR_MSIX_HW_INT_MASK_AD, 0x12}, 11297ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11307ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11317ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11327ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11337ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11347ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11357ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11367ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11377ca00409SHaim Dreyfuss }; 11387ca00409SHaim Dreyfuss 11397ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11407ca00409SHaim Dreyfuss { 11417ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11427ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11433681021fSJohannes Berg int i, arr_size = ARRAY_SIZE(causes_list); 11443681021fSJohannes Berg struct iwl_causes_list *causes = causes_list; 11457ca00409SHaim Dreyfuss 11467ca00409SHaim Dreyfuss /* 11477ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11487ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11497ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11507ca00409SHaim Dreyfuss */ 11519b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11529b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11539b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 11549b58419eSGolan Ben Ami causes[i].cause_num); 11557ca00409SHaim Dreyfuss } 11567ca00409SHaim Dreyfuss } 11577ca00409SHaim Dreyfuss 11587ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11597ca00409SHaim Dreyfuss { 11607ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11617ca00409SHaim Dreyfuss u32 offset = 11627ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11637ca00409SHaim Dreyfuss u32 val, idx; 11647ca00409SHaim Dreyfuss 11657ca00409SHaim Dreyfuss /* 11667ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11677ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11687ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11697ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11707ca00409SHaim Dreyfuss */ 11717ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11727ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11737ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11747ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11757ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11767ca00409SHaim Dreyfuss } 11777ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11787ca00409SHaim Dreyfuss 11797ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11807ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11817ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11827ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11837ca00409SHaim Dreyfuss 11847ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11857ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11867ca00409SHaim Dreyfuss } 11877ca00409SHaim Dreyfuss 118877c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11897ca00409SHaim Dreyfuss { 11907ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11917ca00409SHaim Dreyfuss 11927ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1193286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1194d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1195ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11967ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11977ca00409SHaim Dreyfuss return; 11987ca00409SHaim Dreyfuss } 1199d7270d61SHaim Dreyfuss /* 1200d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1201d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1202d7270d61SHaim Dreyfuss * prph. 1203d7270d61SHaim Dreyfuss */ 1204d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1205ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12067ca00409SHaim Dreyfuss 12077ca00409SHaim Dreyfuss /* 12087ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12097ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12107ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12117ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12127ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12137ca00409SHaim Dreyfuss */ 12147ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12157ca00409SHaim Dreyfuss 12167ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 121783730058SHaim Dreyfuss } 12187ca00409SHaim Dreyfuss 121983730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122083730058SHaim Dreyfuss { 122183730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122283730058SHaim Dreyfuss 122383730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122483730058SHaim Dreyfuss 122583730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 122683730058SHaim Dreyfuss return; 122783730058SHaim Dreyfuss 122883730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12297ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123083730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12317ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12327ca00409SHaim Dreyfuss } 12337ca00409SHaim Dreyfuss 1234bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1235e705c121SKalle Valo { 1236e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1237e705c121SKalle Valo 1238e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1239e705c121SKalle Valo 1240e705c121SKalle Valo if (trans_pcie->is_down) 1241e705c121SKalle Valo return; 1242e705c121SKalle Valo 1243e705c121SKalle Valo trans_pcie->is_down = true; 1244e705c121SKalle Valo 1245e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1246e705c121SKalle Valo iwl_disable_interrupts(trans); 1247e705c121SKalle Valo 1248e705c121SKalle Valo /* device going down, Stop using ICT table */ 1249e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1250e705c121SKalle Valo 1251e705c121SKalle Valo /* 1252e705c121SKalle Valo * If a HW restart happens during firmware loading, 1253e705c121SKalle Valo * then the firmware loading might call this function 1254e705c121SKalle Valo * and later it might be called again due to the 1255e705c121SKalle Valo * restart. So don't process again if the device is 1256e705c121SKalle Valo * already dead. 1257e705c121SKalle Valo */ 1258e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1259a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1260a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1261e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1262e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1263e705c121SKalle Valo 1264e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1265e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1266e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1267e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1268e705c121SKalle Valo udelay(5); 1269e705c121SKalle Valo } 1270e705c121SKalle Valo } 1271e705c121SKalle Valo 1272e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1273e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1274286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1275e705c121SKalle Valo 1276e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1277e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1278e705c121SKalle Valo 1279870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1280e705c121SKalle Valo 1281e705c121SKalle Valo /* 1282f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1283f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1284f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1285f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1286f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1287f4a1f04aSGolan Ben Ami */ 1288f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1289f4a1f04aSGolan Ben Ami 1290f4a1f04aSGolan Ben Ami /* 1291e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1292e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1293e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1294e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1295e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1296e705c121SKalle Valo */ 1297e705c121SKalle Valo iwl_disable_interrupts(trans); 1298e705c121SKalle Valo 1299e705c121SKalle Valo /* clear all status bits */ 1300e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1301e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1302e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1303e705c121SKalle Valo 1304e705c121SKalle Valo /* 1305e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1306e705c121SKalle Valo * interrupt 1307e705c121SKalle Valo */ 1308e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1309e705c121SKalle Valo 1310a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1311e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1312e705c121SKalle Valo } 1313e705c121SKalle Valo 1314eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13152e5d4a8fSHaim Dreyfuss { 13162e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13172e5d4a8fSHaim Dreyfuss 13182e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13192e5d4a8fSHaim Dreyfuss int i; 13202e5d4a8fSHaim Dreyfuss 1321496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13222e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13232e5d4a8fSHaim Dreyfuss } else { 13242e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13252e5d4a8fSHaim Dreyfuss } 13262e5d4a8fSHaim Dreyfuss } 13272e5d4a8fSHaim Dreyfuss 1328a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1329a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1330a6bd005fSEmmanuel Grumbach { 1331a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1332a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1333a6bd005fSEmmanuel Grumbach int ret; 1334a6bd005fSEmmanuel Grumbach 1335a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1336a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1337a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1338a6bd005fSEmmanuel Grumbach ret = -EIO; 1339a6bd005fSEmmanuel Grumbach goto out; 1340a6bd005fSEmmanuel Grumbach } 1341a6bd005fSEmmanuel Grumbach 1342a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1343a6bd005fSEmmanuel Grumbach 1344a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1345a6bd005fSEmmanuel Grumbach 1346a6bd005fSEmmanuel Grumbach /* 1347a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1348a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1349a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1350a6bd005fSEmmanuel Grumbach */ 1351a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1352a6bd005fSEmmanuel Grumbach 1353a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13542e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1355a6bd005fSEmmanuel Grumbach 1356a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1357a6bd005fSEmmanuel Grumbach 1358a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13599ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1360a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1361a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1362a6bd005fSEmmanuel Grumbach goto out; 1363a6bd005fSEmmanuel Grumbach } 1364a6bd005fSEmmanuel Grumbach 1365a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1366a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1367a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1368a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136920aa99bbSAnton Protopopov ret = -EIO; 1370a6bd005fSEmmanuel Grumbach goto out; 1371a6bd005fSEmmanuel Grumbach } 1372a6bd005fSEmmanuel Grumbach 1373a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1374a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1375a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1376a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1377a6bd005fSEmmanuel Grumbach 1378a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1379a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1382a6bd005fSEmmanuel Grumbach if (ret) { 1383a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1384a6bd005fSEmmanuel Grumbach goto out; 1385a6bd005fSEmmanuel Grumbach } 1386a6bd005fSEmmanuel Grumbach 1387a6bd005fSEmmanuel Grumbach /* 1388a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1389a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1390a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1391a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1392a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1393a6bd005fSEmmanuel Grumbach */ 1394a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1395a6bd005fSEmmanuel Grumbach 1396a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1397a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1398a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1399a6bd005fSEmmanuel Grumbach 1400a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1401286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1402a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1403a6bd005fSEmmanuel Grumbach else 1404a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1405a6bd005fSEmmanuel Grumbach 1406a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14079ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1408a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1409a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1410a6bd005fSEmmanuel Grumbach 1411a6bd005fSEmmanuel Grumbach out: 1412a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1413a6bd005fSEmmanuel Grumbach return ret; 1414a6bd005fSEmmanuel Grumbach } 1415a6bd005fSEmmanuel Grumbach 1416a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1417a6bd005fSEmmanuel Grumbach { 1418a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1419a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1420a6bd005fSEmmanuel Grumbach } 1421a6bd005fSEmmanuel Grumbach 1422326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1423326477e4SJohannes Berg bool was_in_rfkill) 1424326477e4SJohannes Berg { 1425326477e4SJohannes Berg bool hw_rfkill; 1426326477e4SJohannes Berg 1427326477e4SJohannes Berg /* 1428326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1429326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1430326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1431326477e4SJohannes Berg * op_mode. 1432326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1433326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1434326477e4SJohannes Berg * notification without endless recursion. Under very rare 1435326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1436326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1437326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1438326477e4SJohannes Berg */ 1439326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1440326477e4SJohannes Berg if (hw_rfkill) { 1441326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1442326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1443326477e4SJohannes Berg } else { 1444326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1445326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1446326477e4SJohannes Berg } 1447326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1448326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1449326477e4SJohannes Berg } 1450326477e4SJohannes Berg 1451bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1452e705c121SKalle Valo { 1453e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1454326477e4SJohannes Berg bool was_in_rfkill; 1455e705c121SKalle Valo 1456e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1457326477e4SJohannes Berg trans_pcie->opmode_down = true; 1458326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1459bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1460326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1461e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1462e705c121SKalle Valo } 1463e705c121SKalle Valo 1464e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1465e705c121SKalle Valo { 1466e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1467e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1468e705c121SKalle Valo 1469e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1470e705c121SKalle Valo 1471326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1472326477e4SJohannes Berg state ? "disabled" : "enabled"); 147377c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1474286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1475bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 147677c09bc8SSara Sharon else 1477bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1478e705c121SKalle Valo } 147977c09bc8SSara Sharon } 1480e705c121SKalle Valo 1481e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1482e5f3f215SHaim Dreyfuss bool test, bool reset) 1483e705c121SKalle Valo { 1484e705c121SKalle Valo iwl_disable_interrupts(trans); 1485e705c121SKalle Valo 1486e705c121SKalle Valo /* 1487e705c121SKalle Valo * in testing mode, the host stays awake and the 1488e705c121SKalle Valo * hardware won't be reset (not even partially) 1489e705c121SKalle Valo */ 1490e705c121SKalle Valo if (test) 1491e705c121SKalle Valo return; 1492e705c121SKalle Valo 1493e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1494e705c121SKalle Valo 14952e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1496e705c121SKalle Valo 1497e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1498286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1499e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1500286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_init_done)); 1501e705c121SKalle Valo 150223ae6128SMatti Gottlieb if (reset) { 1503e705c121SKalle Valo /* 1504e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1505e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1506e705c121SKalle Valo * to execute some invalid memory upon resume 1507e705c121SKalle Valo */ 1508e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1509e705c121SKalle Valo } 1510e705c121SKalle Valo 1511e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1512e705c121SKalle Valo } 1513e705c121SKalle Valo 1514e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1515e5f3f215SHaim Dreyfuss bool reset) 1516e5f3f215SHaim Dreyfuss { 1517e5f3f215SHaim Dreyfuss int ret; 1518e5f3f215SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1519e5f3f215SHaim Dreyfuss 1520e5f3f215SHaim Dreyfuss /* 1521e5f3f215SHaim Dreyfuss * Family IWL_DEVICE_FAMILY_AX210 and above persist mode is set by FW. 1522e5f3f215SHaim Dreyfuss */ 1523e5f3f215SHaim Dreyfuss if (!reset && trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 1524e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1525e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1526e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1527e5f3f215SHaim Dreyfuss } 1528e5f3f215SHaim Dreyfuss 1529e5f3f215SHaim Dreyfuss if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1530e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1531e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_SUSPEND); 1532e5f3f215SHaim Dreyfuss 1533e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1534e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1535e5f3f215SHaim Dreyfuss /* 1536e5f3f215SHaim Dreyfuss * Invalidate it toward resume. 1537e5f3f215SHaim Dreyfuss */ 1538e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1539e5f3f215SHaim Dreyfuss 1540e5f3f215SHaim Dreyfuss if (!ret) { 1541e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout entering D3\n"); 1542e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1543e5f3f215SHaim Dreyfuss } 1544e5f3f215SHaim Dreyfuss } 1545e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1546e5f3f215SHaim Dreyfuss 1547e5f3f215SHaim Dreyfuss return 0; 1548e5f3f215SHaim Dreyfuss } 1549e5f3f215SHaim Dreyfuss 1550e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1551e705c121SKalle Valo enum iwl_d3_status *status, 155223ae6128SMatti Gottlieb bool test, bool reset) 1553e705c121SKalle Valo { 1554d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1555e705c121SKalle Valo u32 val; 1556e705c121SKalle Valo int ret; 1557e705c121SKalle Valo 1558e705c121SKalle Valo if (test) { 1559e705c121SKalle Valo iwl_enable_interrupts(trans); 1560e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1561e5f3f215SHaim Dreyfuss goto out; 1562e705c121SKalle Valo } 1563e705c121SKalle Valo 1564a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 1565286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1566e705c121SKalle Valo 15677d34a7d7SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 1568c96b5eecSJohannes Berg if (ret) 1569e705c121SKalle Valo return ret; 1570e705c121SKalle Valo 1571f98ad635SEmmanuel Grumbach /* 1572f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1573f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1574f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1575f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1576f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1577f98ad635SEmmanuel Grumbach */ 1578f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1579f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1580f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1581f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1582f98ad635SEmmanuel Grumbach 1583e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1584e705c121SKalle Valo 158523ae6128SMatti Gottlieb if (!reset) { 1586e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1587286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 1588e705c121SKalle Valo } else { 1589e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1590e705c121SKalle Valo 1591e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1592e705c121SKalle Valo if (ret) { 1593e705c121SKalle Valo IWL_ERR(trans, 1594e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1595e705c121SKalle Valo return ret; 1596e705c121SKalle Valo } 1597e705c121SKalle Valo } 1598e705c121SKalle Valo 159982ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1600ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 160182ea7966SSara Sharon 1602e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1603e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1604e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1605e705c121SKalle Valo else 1606e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1607e705c121SKalle Valo 1608e5f3f215SHaim Dreyfuss out: 1609e5f3f215SHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE && 1610e5f3f215SHaim Dreyfuss trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1611e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1612e5f3f215SHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1613e5f3f215SHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1614e5f3f215SHaim Dreyfuss 1615e5f3f215SHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1616e5f3f215SHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1617e5f3f215SHaim Dreyfuss /* 1618e5f3f215SHaim Dreyfuss * Invalidate it toward next suspend. 1619e5f3f215SHaim Dreyfuss */ 1620e5f3f215SHaim Dreyfuss trans_pcie->sx_complete = false; 1621e5f3f215SHaim Dreyfuss 1622e5f3f215SHaim Dreyfuss if (!ret) { 1623e5f3f215SHaim Dreyfuss IWL_ERR(trans, "Timeout exiting D3\n"); 1624e5f3f215SHaim Dreyfuss return -ETIMEDOUT; 1625e5f3f215SHaim Dreyfuss } 1626e5f3f215SHaim Dreyfuss } 1627e705c121SKalle Valo return 0; 1628e705c121SKalle Valo } 1629e705c121SKalle Valo 16300c18714aSLuca Coelho static void 16310c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16320c18714aSLuca Coelho struct iwl_trans *trans, 16330c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16342e5d4a8fSHaim Dreyfuss { 16352e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1636ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16372e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16382e5d4a8fSHaim Dreyfuss 16390c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 164006f4b081SSara Sharon goto enable_msi; 164106f4b081SSara Sharon 1642ab1068d6SHao Wei Tee max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES); 164306f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16442e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16452e5d4a8fSHaim Dreyfuss 164606f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16472e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 164806f4b081SSara Sharon max_irqs); 164906f4b081SSara Sharon if (num_irqs < 0) { 1650496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 165106f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 165206f4b081SSara Sharon num_irqs); 165306f4b081SSara Sharon goto enable_msi; 1654496d83caSHaim Dreyfuss } 165506f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1656496d83caSHaim Dreyfuss 16572e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 165806f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 165906f4b081SSara Sharon num_irqs); 166006f4b081SSara Sharon 1661496d83caSHaim Dreyfuss /* 166206f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 166306f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1664496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1665496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1666496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1667496d83caSHaim Dreyfuss */ 1668ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 166906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1670496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1671496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1672ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 167306f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1674496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1675496d83caSHaim Dreyfuss } else { 167606f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1677496d83caSHaim Dreyfuss } 1678ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16792e5d4a8fSHaim Dreyfuss 168006f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1681496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16822e5d4a8fSHaim Dreyfuss return; 16832e5d4a8fSHaim Dreyfuss 168406f4b081SSara Sharon enable_msi: 168506f4b081SSara Sharon ret = pci_enable_msi(pdev); 168606f4b081SSara Sharon if (ret) { 168706f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16882e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16892e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16902e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16912e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16922e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16932e5d4a8fSHaim Dreyfuss } 16942e5d4a8fSHaim Dreyfuss } 16952e5d4a8fSHaim Dreyfuss } 16962e5d4a8fSHaim Dreyfuss 16977c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16987c8d91ebSHaim Dreyfuss { 16997c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 17007c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17017c8d91ebSHaim Dreyfuss 17027c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 17037c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 17047c8d91ebSHaim Dreyfuss offset = 1 + i; 17057c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 17067c8d91ebSHaim Dreyfuss /* 17077c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 17087c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17097c8d91ebSHaim Dreyfuss */ 17107c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17117c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17127c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17137c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17147c8d91ebSHaim Dreyfuss if (ret) 17157c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17167c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 17177c8d91ebSHaim Dreyfuss i); 17187c8d91ebSHaim Dreyfuss } 17197c8d91ebSHaim Dreyfuss } 17207c8d91ebSHaim Dreyfuss 17212e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17222e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17232e5d4a8fSHaim Dreyfuss { 1724496d83caSHaim Dreyfuss int i; 17252e5d4a8fSHaim Dreyfuss 1726496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17272e5d4a8fSHaim Dreyfuss int ret; 17285a41a86cSSharon Dvir struct msix_entry *msix_entry; 172964fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 173064fa3affSSharon Dvir 173164fa3affSSharon Dvir if (!qname) 173264fa3affSSharon Dvir return -ENOMEM; 17332e5d4a8fSHaim Dreyfuss 17345a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17355a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17365a41a86cSSharon Dvir msix_entry->vector, 17372e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1738496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17392e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17402e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17412e5d4a8fSHaim Dreyfuss IRQF_SHARED, 174264fa3affSSharon Dvir qname, 17435a41a86cSSharon Dvir msix_entry); 17442e5d4a8fSHaim Dreyfuss if (ret) { 17452e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17462e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17475a41a86cSSharon Dvir 17482e5d4a8fSHaim Dreyfuss return ret; 17492e5d4a8fSHaim Dreyfuss } 17502e5d4a8fSHaim Dreyfuss } 17517c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17522e5d4a8fSHaim Dreyfuss 17532e5d4a8fSHaim Dreyfuss return 0; 17542e5d4a8fSHaim Dreyfuss } 17552e5d4a8fSHaim Dreyfuss 175644f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 175744f61b5cSShahar S Matityahu { 175844f61b5cSShahar S Matityahu u32 hpm, wprot; 175944f61b5cSShahar S Matityahu 1760286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 176144f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 176244f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 176344f61b5cSShahar S Matityahu break; 176444f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 176544f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 176644f61b5cSShahar S Matityahu break; 176744f61b5cSShahar S Matityahu default: 176844f61b5cSShahar S Matityahu return 0; 176944f61b5cSShahar S Matityahu } 177044f61b5cSShahar S Matityahu 177144f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 177244f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 177344f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 177444f61b5cSShahar S Matityahu 177544f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 177644f61b5cSShahar S Matityahu IWL_ERR(trans, 177744f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 177844f61b5cSShahar S Matityahu return -EPERM; 177944f61b5cSShahar S Matityahu } 178044f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 178144f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 178244f61b5cSShahar S Matityahu } 178344f61b5cSShahar S Matityahu 178444f61b5cSShahar S Matityahu return 0; 178544f61b5cSShahar S Matityahu } 178644f61b5cSShahar S Matityahu 17870df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 17880df36b90SLuca Coelho { 17890df36b90SLuca Coelho int ret; 17900df36b90SLuca Coelho 17910df36b90SLuca Coelho ret = iwl_finish_nic_init(trans, trans->trans_cfg); 17920df36b90SLuca Coelho if (ret < 0) 17930df36b90SLuca Coelho return ret; 17940df36b90SLuca Coelho 17950df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17960df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 17970df36b90SLuca Coelho udelay(20); 17980df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 17990df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 18000df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 18010df36b90SLuca Coelho udelay(20); 18020df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 18030df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18040df36b90SLuca Coelho 18050df36b90SLuca Coelho iwl_trans_pcie_sw_reset(trans); 18060df36b90SLuca Coelho 18070df36b90SLuca Coelho return 0; 18080df36b90SLuca Coelho } 18090df36b90SLuca Coelho 1810bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1811e705c121SKalle Valo { 1812e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1813e705c121SKalle Valo int err; 1814e705c121SKalle Valo 1815e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1816e705c121SKalle Valo 1817e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1818e705c121SKalle Valo if (err) { 1819e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1820e705c121SKalle Valo return err; 1821e705c121SKalle Valo } 1822e705c121SKalle Valo 182344f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 182444f61b5cSShahar S Matityahu if (err) 182544f61b5cSShahar S Matityahu return err; 18268954e1ebSShahar S Matityahu 1827870c2a11SGolan Ben Ami iwl_trans_pcie_sw_reset(trans); 1828e705c121SKalle Valo 18290df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18300df36b90SLuca Coelho trans->cfg->integrated) { 18310df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18320df36b90SLuca Coelho if (err) 18330df36b90SLuca Coelho return err; 18340df36b90SLuca Coelho } 18350df36b90SLuca Coelho 183652b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 183752b6e168SEmmanuel Grumbach if (err) 183852b6e168SEmmanuel Grumbach return err; 1839e705c121SKalle Valo 18402e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 184183730058SHaim Dreyfuss 1842e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1843e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1844e705c121SKalle Valo 1845326477e4SJohannes Berg trans_pcie->opmode_down = false; 1846326477e4SJohannes Berg 1847e705c121SKalle Valo /* Set is_down to false here so that...*/ 1848e705c121SKalle Valo trans_pcie->is_down = false; 1849e705c121SKalle Valo 1850e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18519ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1852e705c121SKalle Valo 1853e705c121SKalle Valo return 0; 1854e705c121SKalle Valo } 1855e705c121SKalle Valo 1856bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1857e705c121SKalle Valo { 1858e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1859e705c121SKalle Valo int ret; 1860e705c121SKalle Valo 1861e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1862bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1863e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1864e705c121SKalle Valo 1865e705c121SKalle Valo return ret; 1866e705c121SKalle Valo } 1867e705c121SKalle Valo 1868e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1869e705c121SKalle Valo { 1870e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1871e705c121SKalle Valo 1872e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1873e705c121SKalle Valo 1874e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1875e705c121SKalle Valo iwl_disable_interrupts(trans); 1876e705c121SKalle Valo 1877e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1878e705c121SKalle Valo 1879e705c121SKalle Valo iwl_disable_interrupts(trans); 1880e705c121SKalle Valo 1881e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1882e705c121SKalle Valo 1883e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1884e705c121SKalle Valo 18852e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 1888e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1889e705c121SKalle Valo { 1890e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1891e705c121SKalle Valo } 1892e705c121SKalle Valo 1893e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1894e705c121SKalle Valo { 1895e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1896e705c121SKalle Valo } 1897e705c121SKalle Valo 1898e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1899e705c121SKalle Valo { 1900e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1901e705c121SKalle Valo } 1902e705c121SKalle Valo 190384fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 190484fb372cSSara Sharon { 19053681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 190684fb372cSSara Sharon return 0x00FFFFFF; 190784fb372cSSara Sharon else 190884fb372cSSara Sharon return 0x000FFFFF; 190984fb372cSSara Sharon } 191084fb372cSSara Sharon 1911e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1912e705c121SKalle Valo { 191384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 191484fb372cSSara Sharon 1915e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 191684fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1917e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 1920e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1921e705c121SKalle Valo u32 val) 1922e705c121SKalle Valo { 192384fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 192484fb372cSSara Sharon 1925e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 192684fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1927e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1928e705c121SKalle Valo } 1929e705c121SKalle Valo 1930e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1931e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1932e705c121SKalle Valo { 1933e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1934e705c121SKalle Valo 1935e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1936e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1937e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1938e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1939e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1940e705c121SKalle Valo else 1941e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1942e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1943e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1944e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1945e705c121SKalle Valo 19466c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19476c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19486c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1949e705c121SKalle Valo 1950e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1951e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 195241837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1953e705c121SKalle Valo 195421cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 195521cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 195621cb3222SJohannes Berg 195739bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 195839bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 195939bdb17eSSharon Dvir 1960e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1961e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1962e705c121SKalle Valo * As this function may be called again in some corner cases don't 1963e705c121SKalle Valo * do anything if NAPI was already initialized. 1964e705c121SKalle Valo */ 1965bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1966e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1967e705c121SKalle Valo } 1968e705c121SKalle Valo 1969e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1970e705c121SKalle Valo { 1971e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19726eb5e529SEmmanuel Grumbach int i; 1973e705c121SKalle Valo 19742e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1975e705c121SKalle Valo 1976286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 197713a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 197813a3a390SSara Sharon else 1979e705c121SKalle Valo iwl_pcie_tx_free(trans); 1980e705c121SKalle Valo iwl_pcie_rx_free(trans); 1981e705c121SKalle Valo 198210a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 198310a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 198410a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 198510a54d81SLuca Coelho } 198610a54d81SLuca Coelho 19872e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 19887c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 19897c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 19907c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 19917c8d91ebSHaim Dreyfuss NULL); 19927c8d91ebSHaim Dreyfuss } 19932e5d4a8fSHaim Dreyfuss 19942e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19952e5d4a8fSHaim Dreyfuss } else { 1996e705c121SKalle Valo iwl_pcie_free_ict(trans); 19972e5d4a8fSHaim Dreyfuss } 1998e705c121SKalle Valo 1999e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 2000e705c121SKalle Valo 20016eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 20026eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 20036eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 20046eb5e529SEmmanuel Grumbach 20056eb5e529SEmmanuel Grumbach if (p->page) 20066eb5e529SEmmanuel Grumbach __free_page(p->page); 20076eb5e529SEmmanuel Grumbach } 20086eb5e529SEmmanuel Grumbach 20096eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 2010a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2011e705c121SKalle Valo iwl_trans_free(trans); 2012e705c121SKalle Valo } 2013e705c121SKalle Valo 2014e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2015e705c121SKalle Valo { 2016e705c121SKalle Valo if (state) 2017e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2018e705c121SKalle Valo else 2019e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2020e705c121SKalle Valo } 2021e705c121SKalle Valo 202249564a80SLuca Coelho struct iwl_trans_pcie_removal { 202349564a80SLuca Coelho struct pci_dev *pdev; 202449564a80SLuca Coelho struct work_struct work; 202549564a80SLuca Coelho }; 202649564a80SLuca Coelho 202749564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 202849564a80SLuca Coelho { 202949564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 203049564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 203149564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2032aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 203349564a80SLuca Coelho 203449564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 203549564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 203649564a80SLuca Coelho pci_lock_rescan_remove(); 203749564a80SLuca Coelho pci_dev_put(pdev); 203849564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 203949564a80SLuca Coelho pci_unlock_rescan_remove(); 204049564a80SLuca Coelho 204149564a80SLuca Coelho kfree(removal); 204249564a80SLuca Coelho module_put(THIS_MODULE); 204349564a80SLuca Coelho } 204449564a80SLuca Coelho 204523ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 2046e705c121SKalle Valo unsigned long *flags) 2047e705c121SKalle Valo { 2048e705c121SKalle Valo int ret; 2049e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2050e705c121SKalle Valo 2051e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 2052e705c121SKalle Valo 2053e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2054e705c121SKalle Valo goto out; 2055e705c121SKalle Valo 2056e705c121SKalle Valo /* this bit wakes up the NIC */ 2057e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 2058286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 2059286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2060e705c121SKalle Valo udelay(2); 2061e705c121SKalle Valo 2062e705c121SKalle Valo /* 2063e705c121SKalle Valo * These bits say the device is running, and should keep running for 2064e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2065e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2066fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2067fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2068e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2069e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2070e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2071e705c121SKalle Valo * to keep device from sleeping. 2072e705c121SKalle Valo * 2073e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2074e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2075fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2076fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2077fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2078e705c121SKalle Valo * 2079e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2080e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2081e705c121SKalle Valo */ 2082e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2083286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_val_mac_access_en), 2084286ca8ebSLuca Coelho (BIT(trans->trans_cfg->csr->flag_mac_clock_ready) | 2085e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 2086e705c121SKalle Valo if (unlikely(ret < 0)) { 208749564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 208849564a80SLuca Coelho 2089e705c121SKalle Valo WARN_ONCE(1, 2090e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 209149564a80SLuca Coelho cntrl); 209249564a80SLuca Coelho 209349564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 209449564a80SLuca Coelho 209549564a80SLuca Coelho if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) { 209649564a80SLuca Coelho struct iwl_trans_pcie_removal *removal; 209749564a80SLuca Coelho 2098f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 209949564a80SLuca Coelho goto err; 210049564a80SLuca Coelho 210149564a80SLuca Coelho IWL_ERR(trans, "Device gone - scheduling removal!\n"); 210249564a80SLuca Coelho 210349564a80SLuca Coelho /* 210449564a80SLuca Coelho * get a module reference to avoid doing this 210549564a80SLuca Coelho * while unloading anyway and to avoid 210649564a80SLuca Coelho * scheduling a work with code that's being 210749564a80SLuca Coelho * removed. 210849564a80SLuca Coelho */ 210949564a80SLuca Coelho if (!try_module_get(THIS_MODULE)) { 211049564a80SLuca Coelho IWL_ERR(trans, 211149564a80SLuca Coelho "Module is being unloaded - abort\n"); 211249564a80SLuca Coelho goto err; 211349564a80SLuca Coelho } 211449564a80SLuca Coelho 211549564a80SLuca Coelho removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 211649564a80SLuca Coelho if (!removal) { 211749564a80SLuca Coelho module_put(THIS_MODULE); 211849564a80SLuca Coelho goto err; 211949564a80SLuca Coelho } 212049564a80SLuca Coelho /* 212149564a80SLuca Coelho * we don't need to clear this flag, because 212249564a80SLuca Coelho * the trans will be freed and reallocated. 212349564a80SLuca Coelho */ 2124f60c9e59SEmmanuel Grumbach set_bit(STATUS_TRANS_DEAD, &trans->status); 212549564a80SLuca Coelho 212649564a80SLuca Coelho removal->pdev = to_pci_dev(trans->dev); 212749564a80SLuca Coelho INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 212849564a80SLuca Coelho pci_dev_get(removal->pdev); 212949564a80SLuca Coelho schedule_work(&removal->work); 213049564a80SLuca Coelho } else { 213149564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 213249564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 213349564a80SLuca Coelho } 213449564a80SLuca Coelho 213549564a80SLuca Coelho err: 2136e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2137e705c121SKalle Valo return false; 2138e705c121SKalle Valo } 2139e705c121SKalle Valo 2140e705c121SKalle Valo out: 2141e705c121SKalle Valo /* 2142e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2143e705c121SKalle Valo * track nic_access anyway. 2144e705c121SKalle Valo */ 2145e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2146e705c121SKalle Valo return true; 2147e705c121SKalle Valo } 2148e705c121SKalle Valo 2149e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 2150e705c121SKalle Valo unsigned long *flags) 2151e705c121SKalle Valo { 2152e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2153e705c121SKalle Valo 2154e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2155e705c121SKalle Valo 2156e705c121SKalle Valo /* 2157e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2158e705c121SKalle Valo * track nic_access anyway. 2159e705c121SKalle Valo */ 2160e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2161e705c121SKalle Valo 2162e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2163e705c121SKalle Valo goto out; 2164e705c121SKalle Valo 2165e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2166286ca8ebSLuca Coelho BIT(trans->trans_cfg->csr->flag_mac_access_req)); 2167e705c121SKalle Valo /* 2168e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2169e705c121SKalle Valo * any previous writes, but we need the write that clears the 2170e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2171e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2172e705c121SKalle Valo */ 2173e705c121SKalle Valo out: 2174e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2175e705c121SKalle Valo } 2176e705c121SKalle Valo 2177e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2178e705c121SKalle Valo void *buf, int dwords) 2179e705c121SKalle Valo { 2180e705c121SKalle Valo unsigned long flags; 2181e705c121SKalle Valo int offs, ret = 0; 2182e705c121SKalle Valo u32 *vals = buf; 2183e705c121SKalle Valo 218423ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2185e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2186e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2187e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2188e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2189e705c121SKalle Valo } else { 2190e705c121SKalle Valo ret = -EBUSY; 2191e705c121SKalle Valo } 2192e705c121SKalle Valo return ret; 2193e705c121SKalle Valo } 2194e705c121SKalle Valo 2195e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2196e705c121SKalle Valo const void *buf, int dwords) 2197e705c121SKalle Valo { 2198e705c121SKalle Valo unsigned long flags; 2199e705c121SKalle Valo int offs, ret = 0; 2200e705c121SKalle Valo const u32 *vals = buf; 2201e705c121SKalle Valo 220223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2203e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2204e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2205e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2206e705c121SKalle Valo vals ? vals[offs] : 0); 2207e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2208e705c121SKalle Valo } else { 2209e705c121SKalle Valo ret = -EBUSY; 2210e705c121SKalle Valo } 2211e705c121SKalle Valo return ret; 2212e705c121SKalle Valo } 2213e705c121SKalle Valo 2214e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2215e705c121SKalle Valo unsigned long txqs, 2216e705c121SKalle Valo bool freeze) 2217e705c121SKalle Valo { 2218e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2219e705c121SKalle Valo int queue; 2220e705c121SKalle Valo 2221e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2222b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2223e705c121SKalle Valo unsigned long now; 2224e705c121SKalle Valo 2225e705c121SKalle Valo spin_lock_bh(&txq->lock); 2226e705c121SKalle Valo 2227e705c121SKalle Valo now = jiffies; 2228e705c121SKalle Valo 2229e705c121SKalle Valo if (txq->frozen == freeze) 2230e705c121SKalle Valo goto next_queue; 2231e705c121SKalle Valo 2232e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2233e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2234e705c121SKalle Valo 2235e705c121SKalle Valo txq->frozen = freeze; 2236e705c121SKalle Valo 2237bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2238e705c121SKalle Valo goto next_queue; 2239e705c121SKalle Valo 2240e705c121SKalle Valo if (freeze) { 2241e705c121SKalle Valo if (unlikely(time_after(now, 2242e705c121SKalle Valo txq->stuck_timer.expires))) { 2243e705c121SKalle Valo /* 2244e705c121SKalle Valo * The timer should have fired, maybe it is 2245e705c121SKalle Valo * spinning right now on the lock. 2246e705c121SKalle Valo */ 2247e705c121SKalle Valo goto next_queue; 2248e705c121SKalle Valo } 2249e705c121SKalle Valo /* remember how long until the timer fires */ 2250e705c121SKalle Valo txq->frozen_expiry_remainder = 2251e705c121SKalle Valo txq->stuck_timer.expires - now; 2252e705c121SKalle Valo del_timer(&txq->stuck_timer); 2253e705c121SKalle Valo goto next_queue; 2254e705c121SKalle Valo } 2255e705c121SKalle Valo 2256e705c121SKalle Valo /* 2257e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2258e705c121SKalle Valo * remainder before it froze 2259e705c121SKalle Valo */ 2260e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2261e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2262e705c121SKalle Valo 2263e705c121SKalle Valo next_queue: 2264e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2265e705c121SKalle Valo } 2266e705c121SKalle Valo } 2267e705c121SKalle Valo 22680cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 22690cd58eaaSEmmanuel Grumbach { 22700cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 22710cd58eaaSEmmanuel Grumbach int i; 22720cd58eaaSEmmanuel Grumbach 2273286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2274b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 22750cd58eaaSEmmanuel Grumbach 22760cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 22770cd58eaaSEmmanuel Grumbach continue; 22780cd58eaaSEmmanuel Grumbach 22790cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 22800cd58eaaSEmmanuel Grumbach 22810cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 22820cd58eaaSEmmanuel Grumbach txq->block--; 22830cd58eaaSEmmanuel Grumbach if (!txq->block) { 22840cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2285bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 22860cd58eaaSEmmanuel Grumbach } 22870cd58eaaSEmmanuel Grumbach } else if (block) { 22880cd58eaaSEmmanuel Grumbach txq->block++; 22890cd58eaaSEmmanuel Grumbach } 22900cd58eaaSEmmanuel Grumbach 22910cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 22920cd58eaaSEmmanuel Grumbach } 22930cd58eaaSEmmanuel Grumbach } 22940cd58eaaSEmmanuel Grumbach 2295e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2296e705c121SKalle Valo 229738398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 229838398efbSSara Sharon { 2299afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2300afb84431SEmmanuel Grumbach u32 status; 2301afb84431SEmmanuel Grumbach bool active; 2302afb84431SEmmanuel Grumbach u8 fifo; 230338398efbSSara Sharon 2304286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 2305afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2306bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2307ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2308ae79785fSSara Sharon return; 2309afb84431SEmmanuel Grumbach } 2310ae79785fSSara Sharon 2311afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2312afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2313afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 231438398efbSSara Sharon 231538398efbSSara Sharon IWL_ERR(trans, 2316afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2317afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2318afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2319afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2320afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 2321286ca8ebSLuca Coelho (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2322afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2323286ca8ebSLuca Coelho (trans->trans_cfg->base_params->max_tfd_queue_size - 1), 2324afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 232538398efbSSara Sharon } 232638398efbSSara Sharon 232792536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 232892536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 232992536c96SSara Sharon { 233092536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 233192536c96SSara Sharon 233292536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 233392536c96SSara Sharon return -EINVAL; 233492536c96SSara Sharon 233592536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 233692536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 233792536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 233892536c96SSara Sharon data->fr_bd_wid = 0; 233992536c96SSara Sharon 234092536c96SSara Sharon return 0; 234192536c96SSara Sharon } 234292536c96SSara Sharon 2343d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2344e705c121SKalle Valo { 2345e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2346e705c121SKalle Valo struct iwl_txq *txq; 2347e705c121SKalle Valo unsigned long now = jiffies; 23482ae48edcSSara Sharon bool overflow_tx; 2349e705c121SKalle Valo u8 wr_ptr; 2350e705c121SKalle Valo 23512b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2352f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2353f60c9e59SEmmanuel Grumbach return -ENODEV; 23542b3fae66SMatt Chen 2355d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2356d6d517b7SSara Sharon return -EINVAL; 2357e705c121SKalle Valo 2358d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2359d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 23602ae48edcSSara Sharon 23612ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23622ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23632ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23642ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23652ae48edcSSara Sharon 23666aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2367e705c121SKalle Valo 23682ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23692ae48edcSSara Sharon overflow_tx) && 2370e705c121SKalle Valo !time_after(jiffies, 2371e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23726aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2373e705c121SKalle Valo 23742ae48edcSSara Sharon /* 23752ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23762ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23772ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23782ae48edcSSara Sharon */ 23792ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2380e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2381e705c121SKalle Valo wr_ptr, write_ptr)) 2382e705c121SKalle Valo return -ETIMEDOUT; 23832ae48edcSSara Sharon wr_ptr = write_ptr; 23842ae48edcSSara Sharon 2385192185d6SJohannes Berg usleep_range(1000, 2000); 23862ae48edcSSara Sharon 23872ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23882ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23892ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23902ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2391e705c121SKalle Valo } 2392e705c121SKalle Valo 2393bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2394e705c121SKalle Valo IWL_ERR(trans, 2395d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2396d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2397d6d517b7SSara Sharon return -ETIMEDOUT; 2398e705c121SKalle Valo } 2399e705c121SKalle Valo 2400d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2401d6d517b7SSara Sharon 2402d6d517b7SSara Sharon return 0; 2403d6d517b7SSara Sharon } 2404d6d517b7SSara Sharon 2405d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2406d6d517b7SSara Sharon { 2407d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2408d6d517b7SSara Sharon int cnt; 2409d6d517b7SSara Sharon int ret = 0; 2410d6d517b7SSara Sharon 2411d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 241279b6c8feSLuca Coelho for (cnt = 0; 2413286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 241479b6c8feSLuca Coelho cnt++) { 2415d6d517b7SSara Sharon 2416d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2417d6d517b7SSara Sharon continue; 2418d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2419d6d517b7SSara Sharon continue; 2420d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2421d6d517b7SSara Sharon continue; 2422d6d517b7SSara Sharon 2423d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 242438398efbSSara Sharon if (ret) 2425d6d517b7SSara Sharon break; 2426d6d517b7SSara Sharon } 2427e705c121SKalle Valo 2428e705c121SKalle Valo return ret; 2429e705c121SKalle Valo } 2430e705c121SKalle Valo 2431e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2432e705c121SKalle Valo u32 mask, u32 value) 2433e705c121SKalle Valo { 2434e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2435e705c121SKalle Valo unsigned long flags; 2436e705c121SKalle Valo 2437e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2438e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2439e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2440e705c121SKalle Valo } 2441e705c121SKalle Valo 2442e705c121SKalle Valo static const char *get_csr_string(int cmd) 2443e705c121SKalle Valo { 2444e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2445e705c121SKalle Valo switch (cmd) { 2446e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2447e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2448e705c121SKalle Valo IWL_CMD(CSR_INT); 2449e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2450e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2451e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2452e705c121SKalle Valo IWL_CMD(CSR_RESET); 2453e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2454e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2455e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2456e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2457e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2458e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2459e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2460e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2461e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2462e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2463e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2464e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2465e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2466e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2467e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2468e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2469e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2470e705c121SKalle Valo default: 2471e705c121SKalle Valo return "UNKNOWN"; 2472e705c121SKalle Valo } 2473e705c121SKalle Valo #undef IWL_CMD 2474e705c121SKalle Valo } 2475e705c121SKalle Valo 2476e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2477e705c121SKalle Valo { 2478e705c121SKalle Valo int i; 2479e705c121SKalle Valo static const u32 csr_tbl[] = { 2480e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2481e705c121SKalle Valo CSR_INT_COALESCING, 2482e705c121SKalle Valo CSR_INT, 2483e705c121SKalle Valo CSR_INT_MASK, 2484e705c121SKalle Valo CSR_FH_INT_STATUS, 2485e705c121SKalle Valo CSR_GPIO_IN, 2486e705c121SKalle Valo CSR_RESET, 2487e705c121SKalle Valo CSR_GP_CNTRL, 2488e705c121SKalle Valo CSR_HW_REV, 2489e705c121SKalle Valo CSR_EEPROM_REG, 2490e705c121SKalle Valo CSR_EEPROM_GP, 2491e705c121SKalle Valo CSR_OTP_GP_REG, 2492e705c121SKalle Valo CSR_GIO_REG, 2493e705c121SKalle Valo CSR_GP_UCODE_REG, 2494e705c121SKalle Valo CSR_GP_DRIVER_REG, 2495e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2496e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2497e705c121SKalle Valo CSR_LED_REG, 2498e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2499e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2500e705c121SKalle Valo CSR_ANA_PLL_CFG, 2501e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2502e705c121SKalle Valo CSR_HW_REV_WA_REG, 2503e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2504e705c121SKalle Valo }; 2505e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2506e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2507e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2508e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2509e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2510e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2511e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2512e705c121SKalle Valo } 2513e705c121SKalle Valo } 2514e705c121SKalle Valo 2515e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2516e705c121SKalle Valo /* create and remove of files */ 2517e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2518cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2519cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2520e705c121SKalle Valo } while (0) 2521e705c121SKalle Valo 2522e705c121SKalle Valo /* file operation */ 2523e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2524e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2525e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2526e705c121SKalle Valo .open = simple_open, \ 2527e705c121SKalle Valo .llseek = generic_file_llseek, \ 2528e705c121SKalle Valo }; 2529e705c121SKalle Valo 2530e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2531e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2532e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2533e705c121SKalle Valo .open = simple_open, \ 2534e705c121SKalle Valo .llseek = generic_file_llseek, \ 2535e705c121SKalle Valo }; 2536e705c121SKalle Valo 2537e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2538e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2539e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2540e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2541e705c121SKalle Valo .open = simple_open, \ 2542e705c121SKalle Valo .llseek = generic_file_llseek, \ 2543e705c121SKalle Valo }; 2544e705c121SKalle Valo 2545e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2546e705c121SKalle Valo char __user *user_buf, 2547e705c121SKalle Valo size_t count, loff_t *ppos) 2548e705c121SKalle Valo { 2549e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2550e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2551e705c121SKalle Valo struct iwl_txq *txq; 2552e705c121SKalle Valo char *buf; 2553e705c121SKalle Valo int pos = 0; 2554e705c121SKalle Valo int cnt; 2555e705c121SKalle Valo int ret; 2556e705c121SKalle Valo size_t bufsz; 2557e705c121SKalle Valo 255879b6c8feSLuca Coelho bufsz = sizeof(char) * 75 * 2559286ca8ebSLuca Coelho trans->trans_cfg->base_params->num_of_queues; 2560e705c121SKalle Valo 2561b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2562e705c121SKalle Valo return -EAGAIN; 2563e705c121SKalle Valo 2564e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2565e705c121SKalle Valo if (!buf) 2566e705c121SKalle Valo return -ENOMEM; 2567e705c121SKalle Valo 256879b6c8feSLuca Coelho for (cnt = 0; 2569286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 257079b6c8feSLuca Coelho cnt++) { 2571b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2572e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2573e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2574bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2575e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2576e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2577e705c121SKalle Valo txq->need_update, txq->frozen, 2578e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2579e705c121SKalle Valo } 2580e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2581e705c121SKalle Valo kfree(buf); 2582e705c121SKalle Valo return ret; 2583e705c121SKalle Valo } 2584e705c121SKalle Valo 2585e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2586e705c121SKalle Valo char __user *user_buf, 2587e705c121SKalle Valo size_t count, loff_t *ppos) 2588e705c121SKalle Valo { 2589e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2590e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 259178485054SSara Sharon char *buf; 259278485054SSara Sharon int pos = 0, i, ret; 2593eb3dc36eSColin Ian King size_t bufsz; 2594e705c121SKalle Valo 259578485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 259678485054SSara Sharon 259778485054SSara Sharon if (!trans_pcie->rxq) 259878485054SSara Sharon return -EAGAIN; 259978485054SSara Sharon 260078485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 260178485054SSara Sharon if (!buf) 260278485054SSara Sharon return -ENOMEM; 260378485054SSara Sharon 260478485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 260578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 260678485054SSara Sharon 260778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 260878485054SSara Sharon i); 260978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2610e705c121SKalle Valo rxq->read); 261178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2612e705c121SKalle Valo rxq->write); 261378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2614e705c121SKalle Valo rxq->write_actual); 261578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2616e705c121SKalle Valo rxq->need_update); 261778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2618e705c121SKalle Valo rxq->free_count); 2619e705c121SKalle Valo if (rxq->rb_stts) { 26200307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26210307c839SGolan Ben Ami rxq)); 262278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 262378485054SSara Sharon "\tclosed_rb_num: %u\n", 26240307c839SGolan Ben Ami r & 0x0FFF); 2625e705c121SKalle Valo } else { 2626e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 262778485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2628e705c121SKalle Valo } 262978485054SSara Sharon } 263078485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 263178485054SSara Sharon kfree(buf); 263278485054SSara Sharon 263378485054SSara Sharon return ret; 2634e705c121SKalle Valo } 2635e705c121SKalle Valo 2636e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2637e705c121SKalle Valo char __user *user_buf, 2638e705c121SKalle Valo size_t count, loff_t *ppos) 2639e705c121SKalle Valo { 2640e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2641e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2642e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2643e705c121SKalle Valo 2644e705c121SKalle Valo int pos = 0; 2645e705c121SKalle Valo char *buf; 2646e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2647e705c121SKalle Valo ssize_t ret; 2648e705c121SKalle Valo 2649e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2650e705c121SKalle Valo if (!buf) 2651e705c121SKalle Valo return -ENOMEM; 2652e705c121SKalle Valo 2653e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2654e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2655e705c121SKalle Valo 2656e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2657e705c121SKalle Valo isr_stats->hw); 2658e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2659e705c121SKalle Valo isr_stats->sw); 2660e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2661e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2662e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2663e705c121SKalle Valo isr_stats->err_code); 2664e705c121SKalle Valo } 2665e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2666e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2667e705c121SKalle Valo isr_stats->sch); 2668e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2669e705c121SKalle Valo isr_stats->alive); 2670e705c121SKalle Valo #endif 2671e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2672e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2673e705c121SKalle Valo 2674e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2675e705c121SKalle Valo isr_stats->ctkill); 2676e705c121SKalle Valo 2677e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2678e705c121SKalle Valo isr_stats->wakeup); 2679e705c121SKalle Valo 2680e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2681e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2682e705c121SKalle Valo 2683e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2684e705c121SKalle Valo isr_stats->tx); 2685e705c121SKalle Valo 2686e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2687e705c121SKalle Valo isr_stats->unhandled); 2688e705c121SKalle Valo 2689e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2690e705c121SKalle Valo kfree(buf); 2691e705c121SKalle Valo return ret; 2692e705c121SKalle Valo } 2693e705c121SKalle Valo 2694e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2695e705c121SKalle Valo const char __user *user_buf, 2696e705c121SKalle Valo size_t count, loff_t *ppos) 2697e705c121SKalle Valo { 2698e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2699e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2700e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2701e705c121SKalle Valo u32 reset_flag; 2702078f1131SJohannes Berg int ret; 2703e705c121SKalle Valo 2704078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2705078f1131SJohannes Berg if (ret) 2706078f1131SJohannes Berg return ret; 2707e705c121SKalle Valo if (reset_flag == 0) 2708e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2709e705c121SKalle Valo 2710e705c121SKalle Valo return count; 2711e705c121SKalle Valo } 2712e705c121SKalle Valo 2713e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2714e705c121SKalle Valo const char __user *user_buf, 2715e705c121SKalle Valo size_t count, loff_t *ppos) 2716e705c121SKalle Valo { 2717e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2718e705c121SKalle Valo 2719e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2720e705c121SKalle Valo 2721e705c121SKalle Valo return count; 2722e705c121SKalle Valo } 2723e705c121SKalle Valo 2724e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2725e705c121SKalle Valo char __user *user_buf, 2726e705c121SKalle Valo size_t count, loff_t *ppos) 2727e705c121SKalle Valo { 2728e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2729e705c121SKalle Valo char *buf = NULL; 2730e705c121SKalle Valo ssize_t ret; 2731e705c121SKalle Valo 2732e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2733e705c121SKalle Valo if (ret < 0) 2734e705c121SKalle Valo return ret; 2735e705c121SKalle Valo if (!buf) 2736e705c121SKalle Valo return -EINVAL; 2737e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2738e705c121SKalle Valo kfree(buf); 2739e705c121SKalle Valo return ret; 2740e705c121SKalle Valo } 2741e705c121SKalle Valo 2742fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2743fa4de7f7SJohannes Berg char __user *user_buf, 2744fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2745fa4de7f7SJohannes Berg { 2746fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2747fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2748fa4de7f7SJohannes Berg char buf[100]; 2749fa4de7f7SJohannes Berg int pos; 2750fa4de7f7SJohannes Berg 2751fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2752fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2753fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2754fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2755fa4de7f7SJohannes Berg 2756fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2757fa4de7f7SJohannes Berg } 2758fa4de7f7SJohannes Berg 2759fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2760fa4de7f7SJohannes Berg const char __user *user_buf, 2761fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2762fa4de7f7SJohannes Berg { 2763fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2764fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2765c5bf4fa1SJohannes Berg bool new_value; 2766fa4de7f7SJohannes Berg int ret; 2767fa4de7f7SJohannes Berg 2768c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2769fa4de7f7SJohannes Berg if (ret) 2770fa4de7f7SJohannes Berg return ret; 2771c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2772fa4de7f7SJohannes Berg return count; 2773fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2774c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2775c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2776fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2777fa4de7f7SJohannes Berg 2778fa4de7f7SJohannes Berg return count; 2779fa4de7f7SJohannes Berg } 2780fa4de7f7SJohannes Berg 2781f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2782f7805b33SLior Cohen struct file *file) 2783f7805b33SLior Cohen { 2784f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2785f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2786f7805b33SLior Cohen 278791c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 278891c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2789f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2790f7805b33SLior Cohen return -ENOENT; 2791f7805b33SLior Cohen } 2792f7805b33SLior Cohen 2793f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2794f7805b33SLior Cohen return -EBUSY; 2795f7805b33SLior Cohen 2796f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2797f7805b33SLior Cohen return simple_open(inode, file); 2798f7805b33SLior Cohen } 2799f7805b33SLior Cohen 2800f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2801f7805b33SLior Cohen struct file *file) 2802f7805b33SLior Cohen { 2803f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2804f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2805f7805b33SLior Cohen 2806f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2807f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2808f7805b33SLior Cohen return 0; 2809f7805b33SLior Cohen } 2810f7805b33SLior Cohen 2811f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2812f7805b33SLior Cohen void *buf, ssize_t *size, 2813f7805b33SLior Cohen ssize_t *bytes_copied) 2814f7805b33SLior Cohen { 2815f7805b33SLior Cohen int buf_size_left = count - *bytes_copied; 2816f7805b33SLior Cohen 2817f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2818f7805b33SLior Cohen if (*size > buf_size_left) 2819f7805b33SLior Cohen *size = buf_size_left; 2820f7805b33SLior Cohen 2821f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2822f7805b33SLior Cohen *bytes_copied += *size; 2823f7805b33SLior Cohen 2824f7805b33SLior Cohen if (buf_size_left == *size) 2825f7805b33SLior Cohen return true; 2826f7805b33SLior Cohen return false; 2827f7805b33SLior Cohen } 2828f7805b33SLior Cohen 2829f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2830f7805b33SLior Cohen char __user *user_buf, 2831f7805b33SLior Cohen size_t count, loff_t *ppos) 2832f7805b33SLior Cohen { 2833f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2834f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 283569f0e505SShahar S Matityahu void *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2836f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2837f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2838f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2839f7805b33SLior Cohen bool b_full; 2840f7805b33SLior Cohen 284191c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2842f7805b33SLior Cohen write_ptr_addr = 284391c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 284491c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2845f7805b33SLior Cohen } else { 2846f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2847f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2848f7805b33SLior Cohen } 2849f7805b33SLior Cohen 285091c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2851f7805b33SLior Cohen return 0; 2852f7805b33SLior Cohen 2853f7805b33SLior Cohen mutex_lock(&data->mutex); 2854f7805b33SLior Cohen if (data->state == 2855f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2856f7805b33SLior Cohen mutex_unlock(&data->mutex); 2857f7805b33SLior Cohen return 0; 2858f7805b33SLior Cohen } 2859f7805b33SLior Cohen 2860f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2861f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2862f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2863f7805b33SLior Cohen 2864f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2865f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2866f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2867f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2868f7805b33SLior Cohen curr_buf, &size, 2869f7805b33SLior Cohen &bytes_copied); 2870f7805b33SLior Cohen data->prev_wr_ptr += size; 2871f7805b33SLior Cohen 2872f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2873f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 287469f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2875f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2876f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2877f7805b33SLior Cohen curr_buf, &size, 2878f7805b33SLior Cohen &bytes_copied); 2879f7805b33SLior Cohen data->prev_wr_ptr += size; 2880f7805b33SLior Cohen 2881f7805b33SLior Cohen if (!b_full) { 2882f7805b33SLior Cohen size = write_ptr; 2883f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2884f7805b33SLior Cohen cpu_addr, &size, 2885f7805b33SLior Cohen &bytes_copied); 2886f7805b33SLior Cohen data->prev_wr_ptr = size; 2887f7805b33SLior Cohen data->prev_wrap_cnt++; 2888f7805b33SLior Cohen } 2889f7805b33SLior Cohen } else { 2890f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2891f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2892f7805b33SLior Cohen IWL_WARN(trans, 2893f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2894f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2895f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2896f7805b33SLior Cohen IWL_WARN(trans, 2897f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2898f7805b33SLior Cohen 2899f7805b33SLior Cohen size = write_ptr; 2900f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2901f7805b33SLior Cohen cpu_addr, &size, 2902f7805b33SLior Cohen &bytes_copied); 2903f7805b33SLior Cohen data->prev_wr_ptr = size; 2904f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2905f7805b33SLior Cohen } 2906f7805b33SLior Cohen 2907f7805b33SLior Cohen mutex_unlock(&data->mutex); 2908f7805b33SLior Cohen 2909f7805b33SLior Cohen return bytes_copied; 2910f7805b33SLior Cohen } 2911f7805b33SLior Cohen 2912e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2913e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2914e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2915e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2916e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2917fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2918e705c121SKalle Valo 2919f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2920f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2921f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2922f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2923f7805b33SLior Cohen }; 2924f7805b33SLior Cohen 2925f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2926cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2927e705c121SKalle Valo { 2928f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2929f8a1edb7SJohannes Berg 29302ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 29312ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 29322ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 29332ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 29342ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 29352ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 2936f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 2937e705c121SKalle Valo } 2938f7805b33SLior Cohen 2939f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 2940f7805b33SLior Cohen { 2941f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2942f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2943f7805b33SLior Cohen 2944f7805b33SLior Cohen mutex_lock(&data->mutex); 2945f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 2946f7805b33SLior Cohen mutex_unlock(&data->mutex); 2947f7805b33SLior Cohen } 2948e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2949e705c121SKalle Valo 29506983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2951e705c121SKalle Valo { 29523cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2953e705c121SKalle Valo u32 cmdlen = 0; 2954e705c121SKalle Valo int i; 2955e705c121SKalle Valo 29563cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 29576983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2958e705c121SKalle Valo 2959e705c121SKalle Valo return cmdlen; 2960e705c121SKalle Valo } 2961e705c121SKalle Valo 2962e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2963e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2964e705c121SKalle Valo int allocated_rb_nums) 2965e705c121SKalle Valo { 2966e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2967e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 296878485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 296978485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2970e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2971e705c121SKalle Valo 2972e705c121SKalle Valo spin_lock(&rxq->lock); 2973e705c121SKalle Valo 29740307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 2975e705c121SKalle Valo 2976e705c121SKalle Valo for (i = rxq->read, j = 0; 2977e705c121SKalle Valo i != r && j < allocated_rb_nums; 2978e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2979e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2980e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2981e705c121SKalle Valo 2982e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2983e705c121SKalle Valo DMA_FROM_DEVICE); 2984e705c121SKalle Valo 2985e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2986e705c121SKalle Valo 2987e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2988e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2989e705c121SKalle Valo rb = (void *)(*data)->data; 2990e705c121SKalle Valo rb->index = cpu_to_le32(i); 2991e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2992e705c121SKalle Valo /* remap the page for the free benefit */ 2993e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2994e705c121SKalle Valo max_len, 2995e705c121SKalle Valo DMA_FROM_DEVICE); 2996e705c121SKalle Valo 2997e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2998e705c121SKalle Valo } 2999e705c121SKalle Valo 3000e705c121SKalle Valo spin_unlock(&rxq->lock); 3001e705c121SKalle Valo 3002e705c121SKalle Valo return rb_len; 3003e705c121SKalle Valo } 3004e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3005e705c121SKalle Valo 3006e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3007e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3008e705c121SKalle Valo { 3009e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3010e705c121SKalle Valo __le32 *val; 3011e705c121SKalle Valo int i; 3012e705c121SKalle Valo 3013e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3014e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3015e705c121SKalle Valo val = (void *)(*data)->data; 3016e705c121SKalle Valo 3017e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3018e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3019e705c121SKalle Valo 3020e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3021e705c121SKalle Valo 3022e705c121SKalle Valo return csr_len; 3023e705c121SKalle Valo } 3024e705c121SKalle Valo 3025e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3026e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3027e705c121SKalle Valo { 3028e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3029e705c121SKalle Valo unsigned long flags; 3030e705c121SKalle Valo __le32 *val; 3031e705c121SKalle Valo int i; 3032e705c121SKalle Valo 303323ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3034e705c121SKalle Valo return 0; 3035e705c121SKalle Valo 3036e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3037e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3038e705c121SKalle Valo val = (void *)(*data)->data; 3039e705c121SKalle Valo 3040286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3041723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3042723b45e2SLiad Kaufman i += sizeof(u32)) 3043e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3044723b45e2SLiad Kaufman else 3045ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3046ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3047723b45e2SLiad Kaufman i += sizeof(u32)) 3048723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3049723b45e2SLiad Kaufman i)); 3050e705c121SKalle Valo 3051e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3052e705c121SKalle Valo 3053e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3054e705c121SKalle Valo 3055e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3056e705c121SKalle Valo } 3057e705c121SKalle Valo 3058e705c121SKalle Valo static u32 3059e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3060e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3061e705c121SKalle Valo u32 monitor_len) 3062e705c121SKalle Valo { 3063e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3064e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3065e705c121SKalle Valo unsigned long flags; 3066e705c121SKalle Valo u32 i; 3067e705c121SKalle Valo 306823ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 3069e705c121SKalle Valo return 0; 3070e705c121SKalle Valo 3071ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3072e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3073ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 307414ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3075ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3076e705c121SKalle Valo 3077e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3078e705c121SKalle Valo 3079e705c121SKalle Valo return monitor_len; 3080e705c121SKalle Valo } 3081e705c121SKalle Valo 30827a14c23dSSara Sharon static void 30837a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 30847a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 30857a14c23dSSara Sharon { 3086c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 30877a14c23dSSara Sharon 3088286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3089c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3090c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3091c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3092c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 309391c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 309491c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 309591c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 309691c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 30977a14c23dSSara Sharon } else { 30987a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 30997a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31007a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31017a14c23dSSara Sharon } 3102c88580e1SShahar S Matityahu 3103c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31047a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31057a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31067a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31077a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3108286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3109c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3110c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3111c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3112c88580e1SShahar S Matityahu } 3113c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31147a14c23dSSara Sharon } 31157a14c23dSSara Sharon 3116e705c121SKalle Valo static u32 3117e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3118e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3119e705c121SKalle Valo u32 monitor_len) 3120e705c121SKalle Valo { 312169f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3122e705c121SKalle Valo u32 len = 0; 3123e705c121SKalle Valo 312491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 312569f0e505SShahar S Matityahu (fw_mon->size && 3126286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3127286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3128e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3129e705c121SKalle Valo 3130e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3131e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 31327a14c23dSSara Sharon 31337a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3134e705c121SKalle Valo 3135e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 313669f0e505SShahar S Matityahu if (fw_mon->size) { 313769f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 313869f0e505SShahar S Matityahu monitor_len = fw_mon->size; 313991c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 31407a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3141e705c121SKalle Valo /* 3142e705c121SKalle Valo * Update pointers to reflect actual values after 3143e705c121SKalle Valo * shifting 3144e705c121SKalle Valo */ 314591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3146fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3147fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 314891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3149fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3150fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3151fd527eb5SGolan Ben Ami } else { 3152e705c121SKalle Valo base = iwl_read_prph(trans, base) << 315391c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3154fd527eb5SGolan Ben Ami } 3155fd527eb5SGolan Ben Ami 3156e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3157e705c121SKalle Valo monitor_len / sizeof(u32)); 315891c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3159e705c121SKalle Valo monitor_len = 3160e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3161e705c121SKalle Valo fw_mon_data, 3162e705c121SKalle Valo monitor_len); 3163e705c121SKalle Valo } else { 3164e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3165e705c121SKalle Valo monitor_len = 0; 3166e705c121SKalle Valo } 3167e705c121SKalle Valo 3168e705c121SKalle Valo len += monitor_len; 3169e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3170e705c121SKalle Valo } 3171e705c121SKalle Valo 3172e705c121SKalle Valo return len; 3173e705c121SKalle Valo } 3174e705c121SKalle Valo 317593079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3176e705c121SKalle Valo { 317769f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3178da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3179da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 318069f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 318169f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 318291c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3183da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3184e705c121SKalle Valo 318591c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 318691c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3187fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3188fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 318991c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3190fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3191fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3192fd527eb5SGolan Ben Ami 3193fd527eb5SGolan Ben Ami monitor_len = 3194fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 319591c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3196fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3197fd527eb5SGolan Ben Ami } else { 319891c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 319991c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3200e705c121SKalle Valo 3201e705c121SKalle Valo base = iwl_read_prph(trans, base) << 320291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3203e705c121SKalle Valo end = iwl_read_prph(trans, end) << 320491c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3205e705c121SKalle Valo 3206e705c121SKalle Valo /* Make "end" point to the actual end */ 3207286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3208fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 320991c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 321091c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3211e705c121SKalle Valo monitor_len = end - base; 3212fd527eb5SGolan Ben Ami } 3213da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3214da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3215e705c121SKalle Valo monitor_len; 3216da752717SShahar S Matityahu return monitor_len; 3217e705c121SKalle Valo } 3218da752717SShahar S Matityahu return 0; 3219da752717SShahar S Matityahu } 3220da752717SShahar S Matityahu 3221da752717SShahar S Matityahu static struct iwl_trans_dump_data 3222da752717SShahar S Matityahu *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 322379f033f6SSara Sharon u32 dump_mask) 3224da752717SShahar S Matityahu { 3225da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3226da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 3227da752717SShahar S Matityahu struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 3228da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3229da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3230fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3231da752717SShahar S Matityahu int i, ptr; 3232da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3233286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 323479f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 323579f033f6SSara Sharon 323679f033f6SSara Sharon if (!dump_mask) 323779f033f6SSara Sharon return NULL; 3238da752717SShahar S Matityahu 3239da752717SShahar S Matityahu /* transport dump header */ 3240da752717SShahar S Matityahu len = sizeof(*dump_data); 3241da752717SShahar S Matityahu 3242da752717SShahar S Matityahu /* host commands */ 3243e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3244da752717SShahar S Matityahu len += sizeof(*data) + 32458672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 32468672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3247da752717SShahar S Matityahu 3248da752717SShahar S Matityahu /* FW monitor */ 3249fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3250da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3251e705c121SKalle Valo 3252e705c121SKalle Valo /* CSR registers */ 325379f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3254e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3255e705c121SKalle Valo 3256e705c121SKalle Valo /* FH registers */ 325779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3258286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3259723b45e2SLiad Kaufman len += sizeof(*data) + 3260ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3261ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3262723b45e2SLiad Kaufman else 3263723b45e2SLiad Kaufman len += sizeof(*data) + 3264520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3265520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3266520f03eaSShahar S Matityahu } 3267e705c121SKalle Valo 3268e705c121SKalle Valo if (dump_rbs) { 326978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 327078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3271e705c121SKalle Valo /* RBs */ 32720307c839SGolan Ben Ami num_rbs = 32730307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3274e705c121SKalle Valo & 0x0FFF; 327578485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3276e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3277e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3278e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3279e705c121SKalle Valo } 3280e705c121SKalle Valo 32815538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3282286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3283505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 32845538409bSLiad Kaufman len += sizeof(*data) + 32855538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3286505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 32875538409bSLiad Kaufman 3288e705c121SKalle Valo dump_data = vzalloc(len); 3289e705c121SKalle Valo if (!dump_data) 3290e705c121SKalle Valo return NULL; 3291e705c121SKalle Valo 3292e705c121SKalle Valo len = 0; 3293e705c121SKalle Valo data = (void *)dump_data->data; 3294520f03eaSShahar S Matityahu 3295e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3296520f03eaSShahar S Matityahu u16 tfd_size = trans_pcie->tfd_size; 3297520f03eaSShahar S Matityahu 3298e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3299e705c121SKalle Valo txcmd = (void *)data->data; 3300e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3301bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3302bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33034ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 330408326a97SJohannes Berg u8 tfdidx; 3305e705c121SKalle Valo u32 caplen, cmdlen; 3306e705c121SKalle Valo 330708326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 330808326a97SJohannes Berg tfdidx = idx; 330908326a97SJohannes Berg else 331008326a97SJohannes Berg tfdidx = ptr; 331108326a97SJohannes Berg 3312520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 331308326a97SJohannes Berg (u8 *)cmdq->tfds + 331408326a97SJohannes Berg tfd_size * tfdidx); 3315e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3316e705c121SKalle Valo 3317e705c121SKalle Valo if (cmdlen) { 3318e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3319e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3320e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3321520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3322520f03eaSShahar S Matityahu caplen); 3323e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3324e705c121SKalle Valo } 3325e705c121SKalle Valo 33267b3e42eaSGolan Ben Ami ptr = iwl_queue_dec_wrap(trans, ptr); 3327e705c121SKalle Valo } 3328e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3329e705c121SKalle Valo 3330e705c121SKalle Valo data->len = cpu_to_le32(len); 3331e705c121SKalle Valo len += sizeof(*data); 3332e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3333520f03eaSShahar S Matityahu } 3334e705c121SKalle Valo 333579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3336e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 333779f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3338e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3339e705c121SKalle Valo if (dump_rbs) 3340e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3341e705c121SKalle Valo 33425538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3343286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 334479b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3345505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 33465538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3347505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 33485538409bSLiad Kaufman 33495538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 33505538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 33515538409bSLiad Kaufman paging = (void *)data->data; 33525538409bSLiad Kaufman paging->index = cpu_to_le32(i); 33535538409bSLiad Kaufman memcpy(paging->data, 3354505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 33555538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 33565538409bSLiad Kaufman 33575538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 33585538409bSLiad Kaufman } 33595538409bSLiad Kaufman } 336079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3361e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3362e705c121SKalle Valo 3363e705c121SKalle Valo dump_data->len = len; 3364e705c121SKalle Valo 3365e705c121SKalle Valo return dump_data; 3366e705c121SKalle Valo } 3367e705c121SKalle Valo 33684cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 33694cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 33704cbb8e50SLuciano Coelho { 33714cbb8e50SLuciano Coelho return 0; 33724cbb8e50SLuciano Coelho } 33734cbb8e50SLuciano Coelho 33744cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 33754cbb8e50SLuciano Coelho { 33764cbb8e50SLuciano Coelho } 33774cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 33784cbb8e50SLuciano Coelho 3379623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3380623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3381623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3382623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3383623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3384623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3385623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3386623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3387623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3388623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3389623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3390870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3391623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3392623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3393623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3394623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3395623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3396d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 3397d1967ce6SShahar S Matityahu .sync_nmi = iwl_trans_pcie_sync_nmi 3398623e7766SSara Sharon 3399623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3400623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3401623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3402623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3403623e7766SSara Sharon #else 3404623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3405623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3406623e7766SSara Sharon 3407e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3408623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3409623e7766SSara Sharon IWL_TRANS_PM_OPS 3410e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3411e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3412e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3413e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3414e705c121SKalle Valo 3415e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3416e705c121SKalle Valo 3417e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3418e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3419e705c121SKalle Valo 3420e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3421e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3422e705c121SKalle Valo 342342db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 342442db09c1SLiad Kaufman 3425d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3426d6d517b7SSara Sharon 3427e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 34280cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3429f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3430f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3431f7805b33SLior Cohen #endif 3432623e7766SSara Sharon }; 3433e705c121SKalle Valo 3434623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3435623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3436623e7766SSara Sharon IWL_TRANS_PM_OPS 3437623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3438eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3439eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 344077c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3441e705c121SKalle Valo 3442ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3443e705c121SKalle Valo 3444ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3445623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3446623e7766SSara Sharon 3447ba7136f3SAlex Malamud .set_q_ptrs = iwl_trans_pcie_set_q_ptrs, 3448ba7136f3SAlex Malamud 34496b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 34506b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3451d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 345292536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3453f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3454f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3455f7805b33SLior Cohen #endif 3456e705c121SKalle Valo }; 3457e705c121SKalle Valo 3458e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3459e705c121SKalle Valo const struct pci_device_id *ent, 34607e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3461e705c121SKalle Valo { 3462e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3463e705c121SKalle Valo struct iwl_trans *trans; 3464a89c72ffSJohannes Berg int ret, addr_size, txcmd_size, txcmd_align; 3465a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3466a89c72ffSJohannes Berg 3467a89c72ffSJohannes Berg if (!cfg_trans->gen2) { 3468a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3469a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd); 3470a89c72ffSJohannes Berg txcmd_align = sizeof(void *); 3471a89c72ffSJohannes Berg } else if (cfg_trans->device_family < IWL_DEVICE_FAMILY_AX210) { 3472a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd_gen2); 3473a89c72ffSJohannes Berg txcmd_align = 64; 3474a89c72ffSJohannes Berg } else { 3475a89c72ffSJohannes Berg txcmd_size = sizeof(struct iwl_tx_cmd_gen3); 3476a89c72ffSJohannes Berg txcmd_align = 128; 3477a89c72ffSJohannes Berg } 3478a89c72ffSJohannes Berg 3479a89c72ffSJohannes Berg txcmd_size += sizeof(struct iwl_cmd_header); 3480a89c72ffSJohannes Berg txcmd_size += 36; /* biggest possible 802.11 header */ 3481a89c72ffSJohannes Berg 3482a89c72ffSJohannes Berg /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */ 3483a89c72ffSJohannes Berg if (WARN_ON(cfg_trans->gen2 && txcmd_size >= txcmd_align)) 3484a89c72ffSJohannes Berg return ERR_PTR(-EINVAL); 3485e705c121SKalle Valo 34865a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 34875a41a86cSSharon Dvir if (ret) 34885a41a86cSSharon Dvir return ERR_PTR(ret); 34895a41a86cSSharon Dvir 3490a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3491a89c72ffSJohannes Berg txcmd_size, txcmd_align); 3492e705c121SKalle Valo if (!trans) 3493e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3494e705c121SKalle Valo 3495e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3496e705c121SKalle Valo 3497e705c121SKalle Valo trans_pcie->trans = trans; 3498326477e4SJohannes Berg trans_pcie->opmode_down = true; 3499e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3500e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3501e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3502e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 35038188a18eSJohannes Berg 35048188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35058188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35068188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35078188a18eSJohannes Berg ret = -ENOMEM; 35088188a18eSJohannes Berg goto out_free_trans; 35098188a18eSJohannes Berg } 35108188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35118188a18eSJohannes Berg 35126eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 35136eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 35146eb5e529SEmmanuel Grumbach ret = -ENOMEM; 35156eb5e529SEmmanuel Grumbach goto out_no_pci; 35166eb5e529SEmmanuel Grumbach } 3517c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3518e705c121SKalle Valo 35197e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3520e705c121SKalle Valo /* 3521e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3522e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3523e705c121SKalle Valo * lot of power. 3524e705c121SKalle Valo */ 3525e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3526e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3527e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3528e705c121SKalle Valo } 3529e705c121SKalle Valo 35309416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 35319416560eSGolan Ben Ami 35327e8258c0SLuca Coelho if (cfg_trans->use_tfh) { 35332c6262b7SSara Sharon addr_size = 64; 35343cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 35358352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 35366983ba69SSara Sharon } else { 35372c6262b7SSara Sharon addr_size = 36; 35383cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 35396983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 35406983ba69SSara Sharon } 35413cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 35423cd1980bSSara Sharon 3543e705c121SKalle Valo pci_set_master(pdev); 3544e705c121SKalle Valo 354596a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3546e705c121SKalle Valo if (!ret) 354796a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 354896a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3549e705c121SKalle Valo if (ret) { 3550e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3551e705c121SKalle Valo if (!ret) 3552e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3553e705c121SKalle Valo DMA_BIT_MASK(32)); 3554e705c121SKalle Valo /* both attempts failed: */ 3555e705c121SKalle Valo if (ret) { 3556e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 35575a41a86cSSharon Dvir goto out_no_pci; 3558e705c121SKalle Valo } 3559e705c121SKalle Valo } 3560e705c121SKalle Valo 35615a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3562e705c121SKalle Valo if (ret) { 35635a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 35645a41a86cSSharon Dvir goto out_no_pci; 3565e705c121SKalle Valo } 3566e705c121SKalle Valo 35675a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3568e705c121SKalle Valo if (!trans_pcie->hw_base) { 35695a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3570e705c121SKalle Valo ret = -ENODEV; 35715a41a86cSSharon Dvir goto out_no_pci; 3572e705c121SKalle Valo } 3573e705c121SKalle Valo 3574e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3575e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3576e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3577e705c121SKalle Valo 3578e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3579e705c121SKalle Valo iwl_disable_interrupts(trans); 3580e705c121SKalle Valo 3581e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 35829a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 35839a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 35849a098a89SRajat Jain ret = -EIO; 35859a098a89SRajat Jain goto out_no_pci; 35869a098a89SRajat Jain } 35879a098a89SRajat Jain 3588e705c121SKalle Valo /* 3589e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3590e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3591e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3592e705c121SKalle Valo * in the old format. 3593e705c121SKalle Valo */ 35947e8258c0SLuca Coelho if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) { 3595e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3596e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3597e705c121SKalle Valo 3598e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3599e705c121SKalle Valo if (ret) { 3600e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 36015a41a86cSSharon Dvir goto out_no_pci; 3602e705c121SKalle Valo } 3603e705c121SKalle Valo 3604e705c121SKalle Valo /* 3605e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3606e705c121SKalle Valo * id located at the AUX bus MISC address space. 3607e705c121SKalle Valo */ 36087e8258c0SLuca Coelho ret = iwl_finish_nic_init(trans, cfg_trans); 3609c96b5eecSJohannes Berg if (ret) 36105a41a86cSSharon Dvir goto out_no_pci; 3611e705c121SKalle Valo 3612e705c121SKalle Valo } 3613e705c121SKalle Valo 361499be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 361599be6166SLuca Coelho 36167e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3617e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3618e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3619e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3620e705c121SKalle Valo 3621e705c121SKalle Valo /* Initialize the wait queue for commands */ 3622e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3623e705c121SKalle Valo 3624e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3625e5f3f215SHaim Dreyfuss 36262e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36272388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36282388bd7bSDan Carpenter if (ret) 36295a41a86cSSharon Dvir goto out_no_pci; 36302e5d4a8fSHaim Dreyfuss } else { 3631e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3632e705c121SKalle Valo if (ret) 36335a41a86cSSharon Dvir goto out_no_pci; 3634e705c121SKalle Valo 36355a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36365a41a86cSSharon Dvir iwl_pcie_isr, 3637e705c121SKalle Valo iwl_pcie_irq_handler, 3638e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3639e705c121SKalle Valo if (ret) { 3640e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3641e705c121SKalle Valo goto out_free_ict; 3642e705c121SKalle Valo } 3643e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 36442e5d4a8fSHaim Dreyfuss } 3645e705c121SKalle Valo 3646f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3647f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3648f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3649f7805b33SLior Cohen #endif 3650f7805b33SLior Cohen 3651a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3652a9248de4SShahar S Matityahu 3653e705c121SKalle Valo return trans; 3654e705c121SKalle Valo 3655e705c121SKalle Valo out_free_ict: 3656e705c121SKalle Valo iwl_pcie_free_ict(trans); 3657e705c121SKalle Valo out_no_pci: 36586eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 36598188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 36608188a18eSJohannes Berg out_free_trans: 3661e705c121SKalle Valo iwl_trans_free(trans); 3662e705c121SKalle Valo return ERR_PTR(ret); 3663e705c121SKalle Valo } 3664b8a7547dSShahar S Matityahu 3665d1967ce6SShahar S Matityahu void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3666b8a7547dSShahar S Matityahu { 36671c6bca6dSShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3668b8a7547dSShahar S Matityahu unsigned long timeout = jiffies + IWL_TRANS_NMI_TIMEOUT; 3669e4eee943SShahar S Matityahu bool interrupts_enabled = test_bit(STATUS_INT_ENABLED, &trans->status); 36701c6bca6dSShahar S Matityahu u32 inta_addr, sw_err_bit; 36711c6bca6dSShahar S Matityahu 36721c6bca6dSShahar S Matityahu if (trans_pcie->msix_enabled) { 36731c6bca6dSShahar S Matityahu inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 36741c6bca6dSShahar S Matityahu sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 36751c6bca6dSShahar S Matityahu } else { 36761c6bca6dSShahar S Matityahu inta_addr = CSR_INT; 36771c6bca6dSShahar S Matityahu sw_err_bit = CSR_INT_BIT_SW_ERR; 36781c6bca6dSShahar S Matityahu } 3679b8a7547dSShahar S Matityahu 3680e4eee943SShahar S Matityahu /* if the interrupts were already disabled, there is no point in 3681e4eee943SShahar S Matityahu * calling iwl_disable_interrupts 3682e4eee943SShahar S Matityahu */ 3683e4eee943SShahar S Matityahu if (interrupts_enabled) 3684b8a7547dSShahar S Matityahu iwl_disable_interrupts(trans); 3685e4eee943SShahar S Matityahu 3686b8a7547dSShahar S Matityahu iwl_force_nmi(trans); 3687b8a7547dSShahar S Matityahu while (time_after(timeout, jiffies)) { 36881c6bca6dSShahar S Matityahu u32 inta_hw = iwl_read32(trans, inta_addr); 3689b8a7547dSShahar S Matityahu 3690b8a7547dSShahar S Matityahu /* Error detected by uCode */ 36911c6bca6dSShahar S Matityahu if (inta_hw & sw_err_bit) { 3692b8a7547dSShahar S Matityahu /* Clear causes register */ 36931c6bca6dSShahar S Matityahu iwl_write32(trans, inta_addr, inta_hw & sw_err_bit); 3694b8a7547dSShahar S Matityahu break; 3695b8a7547dSShahar S Matityahu } 3696b8a7547dSShahar S Matityahu 3697b8a7547dSShahar S Matityahu mdelay(1); 3698b8a7547dSShahar S Matityahu } 3699e4eee943SShahar S Matityahu 3700e4eee943SShahar S Matityahu /* enable interrupts only if there were already enabled before this 3701e4eee943SShahar S Matityahu * function to avoid a case were the driver enable interrupts before 3702e4eee943SShahar S Matityahu * proper configurations were made 3703e4eee943SShahar S Matityahu */ 3704e4eee943SShahar S Matityahu if (interrupts_enabled) 3705b8a7547dSShahar S Matityahu iwl_enable_interrupts(trans); 3706e4eee943SShahar S Matityahu 3707b8a7547dSShahar S Matityahu iwl_trans_fw_error(trans); 3708b8a7547dSShahar S Matityahu } 3709