18e99ea8dSJohannes Berg // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 28e99ea8dSJohannes Berg /* 3227f2597SJohannes Berg * Copyright (C) 2007-2015, 2018-2022 Intel Corporation 48e99ea8dSJohannes Berg * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 58e99ea8dSJohannes Berg * Copyright (C) 2016-2017 Intel Deutschland GmbH 68e99ea8dSJohannes Berg */ 7e705c121SKalle Valo #include <linux/pci.h> 8e705c121SKalle Valo #include <linux/interrupt.h> 9e705c121SKalle Valo #include <linux/debugfs.h> 10e705c121SKalle Valo #include <linux/sched.h> 11e705c121SKalle Valo #include <linux/bitops.h> 12e705c121SKalle Valo #include <linux/gfp.h> 13e705c121SKalle Valo #include <linux/vmalloc.h> 1449564a80SLuca Coelho #include <linux/module.h> 15f7805b33SLior Cohen #include <linux/wait.h> 16df67a1beSJohannes Berg #include <linux/seq_file.h> 17e705c121SKalle Valo 18e705c121SKalle Valo #include "iwl-drv.h" 19e705c121SKalle Valo #include "iwl-trans.h" 20e705c121SKalle Valo #include "iwl-csr.h" 21e705c121SKalle Valo #include "iwl-prph.h" 22e705c121SKalle Valo #include "iwl-scd.h" 23e705c121SKalle Valo #include "iwl-agn-hw.h" 24d962f9b1SJohannes Berg #include "fw/error-dump.h" 25520f03eaSShahar S Matityahu #include "fw/dbg.h" 26a89c72ffSJohannes Berg #include "fw/api/tx.h" 276d19a5ebSEmmanuel Grumbach #include "mei/iwl-mei.h" 28e705c121SKalle Valo #include "internal.h" 29e705c121SKalle Valo #include "iwl-fh.h" 306654cd4eSLuca Coelho #include "iwl-context-info-gen3.h" 31e705c121SKalle Valo 32e705c121SKalle Valo /* extended range in FW SRAM */ 33e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 34e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 35e705c121SKalle Valo 364290eaadSJohannes Berg void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 37a6d24fadSRajat Jain { 38c4d3f2eeSLuca Coelho #define PCI_DUMP_SIZE 352 39c4d3f2eeSLuca Coelho #define PCI_MEM_DUMP_SIZE 64 40c4d3f2eeSLuca Coelho #define PCI_PARENT_DUMP_SIZE 524 41a6d24fadSRajat Jain #define PREFIX_LEN 32 42a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 43a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 44a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 45a6d24fadSRajat Jain char *prefix; 46a6d24fadSRajat Jain 47a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 48a6d24fadSRajat Jain return; 49a6d24fadSRajat Jain 50a6d24fadSRajat Jain /* Should be a multiple of 4 */ 51a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 52c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 53c4d3f2eeSLuca Coelho BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 54c4d3f2eeSLuca Coelho 55a6d24fadSRajat Jain /* Alloc a max size buffer */ 56a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 57c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 58c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 59c4d3f2eeSLuca Coelho alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 60c4d3f2eeSLuca Coelho 61a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 62a6d24fadSRajat Jain if (!buf) 63a6d24fadSRajat Jain return; 64a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 65a6d24fadSRajat Jain 66a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 67a6d24fadSRajat Jain 68a6d24fadSRajat Jain /* Print wifi device registers */ 69a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 70a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 71a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 72a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 73a6d24fadSRajat Jain goto err_read; 74a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 75a6d24fadSRajat Jain 76a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 77c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 78a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 79a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 80a6d24fadSRajat Jain 81a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 82a6d24fadSRajat Jain if (pos) { 83a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 84a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 85a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 86a6d24fadSRajat Jain goto err_read; 87a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 88a6d24fadSRajat Jain 32, 4, buf, i, 0); 89a6d24fadSRajat Jain } 90a6d24fadSRajat Jain 91a6d24fadSRajat Jain /* Print parent device registers next */ 92a6d24fadSRajat Jain if (!pdev->bus->self) 93a6d24fadSRajat Jain goto out; 94a6d24fadSRajat Jain 95a6d24fadSRajat Jain pdev = pdev->bus->self; 96a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 97a6d24fadSRajat Jain 98a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 99a6d24fadSRajat Jain pci_name(pdev)); 100c4d3f2eeSLuca Coelho for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 101a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 102a6d24fadSRajat Jain goto err_read; 103a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 104a6d24fadSRajat Jain 105a6d24fadSRajat Jain /* Print root port AER registers */ 106a6d24fadSRajat Jain pos = 0; 107a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 108a6d24fadSRajat Jain if (pdev) 109a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 110a6d24fadSRajat Jain if (pos) { 111a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 112a6d24fadSRajat Jain pci_name(pdev)); 113a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 114a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 115a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 116a6d24fadSRajat Jain goto err_read; 117a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 118a6d24fadSRajat Jain 4, buf, i, 0); 119a6d24fadSRajat Jain } 120f3402d6dSSara Sharon goto out; 121a6d24fadSRajat Jain 122a6d24fadSRajat Jain err_read: 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 125a6d24fadSRajat Jain out: 126a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 127a6d24fadSRajat Jain kfree(buf); 128a6d24fadSRajat Jain } 129a6d24fadSRajat Jain 13015bf5ac6SJohannes Berg static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 13115bf5ac6SJohannes Berg bool retake_ownership) 132870c2a11SGolan Ben Ami { 133870c2a11SGolan Ben Ami /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 1341b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1351b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_GP_CNTRL, 1361b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_SW_RESET); 1371b6598c3SRoee Goldfiner else 1381b6598c3SRoee Goldfiner iwl_set_bit(trans, CSR_RESET, 1391b6598c3SRoee Goldfiner CSR_RESET_REG_FLAG_SW_RESET); 140870c2a11SGolan Ben Ami usleep_range(5000, 6000); 14115bf5ac6SJohannes Berg 14215bf5ac6SJohannes Berg if (retake_ownership) 14315bf5ac6SJohannes Berg return iwl_pcie_prepare_card_hw(trans); 14415bf5ac6SJohannes Berg 14515bf5ac6SJohannes Berg return 0; 146870c2a11SGolan Ben Ami } 147870c2a11SGolan Ben Ami 148e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 149e705c121SKalle Valo { 15069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 151e705c121SKalle Valo 15269f0e505SShahar S Matityahu if (!fw_mon->size) 15369f0e505SShahar S Matityahu return; 15469f0e505SShahar S Matityahu 15569f0e505SShahar S Matityahu dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 15669f0e505SShahar S Matityahu fw_mon->physical); 15769f0e505SShahar S Matityahu 15869f0e505SShahar S Matityahu fw_mon->block = NULL; 15969f0e505SShahar S Matityahu fw_mon->physical = 0; 16069f0e505SShahar S Matityahu fw_mon->size = 0; 161e705c121SKalle Valo } 162e705c121SKalle Valo 16388964b2eSSara Sharon static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 16488964b2eSSara Sharon u8 max_power, u8 min_power) 165e705c121SKalle Valo { 16669f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 16769f0e505SShahar S Matityahu void *block = NULL; 16869f0e505SShahar S Matityahu dma_addr_t physical = 0; 169e705c121SKalle Valo u32 size = 0; 170e705c121SKalle Valo u8 power; 171e705c121SKalle Valo 17269f0e505SShahar S Matityahu if (fw_mon->size) 17369f0e505SShahar S Matityahu return; 17469f0e505SShahar S Matityahu 17588964b2eSSara Sharon for (power = max_power; power >= min_power; power--) { 176e705c121SKalle Valo size = BIT(power); 17769f0e505SShahar S Matityahu block = dma_alloc_coherent(trans->dev, size, &physical, 1782d46f7afSChristoph Hellwig GFP_KERNEL | __GFP_NOWARN); 17969f0e505SShahar S Matityahu if (!block) 180e705c121SKalle Valo continue; 181e705c121SKalle Valo 182e705c121SKalle Valo IWL_INFO(trans, 183c5f97542SShahar S Matityahu "Allocated 0x%08x bytes for firmware monitor.\n", 184c5f97542SShahar S Matityahu size); 185e705c121SKalle Valo break; 186e705c121SKalle Valo } 187e705c121SKalle Valo 18869f0e505SShahar S Matityahu if (WARN_ON_ONCE(!block)) 189e705c121SKalle Valo return; 190e705c121SKalle Valo 191e705c121SKalle Valo if (power != max_power) 192e705c121SKalle Valo IWL_ERR(trans, 193e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 194e705c121SKalle Valo (unsigned long)BIT(power - 10), 195e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 196e705c121SKalle Valo 19769f0e505SShahar S Matityahu fw_mon->block = block; 19869f0e505SShahar S Matityahu fw_mon->physical = physical; 19969f0e505SShahar S Matityahu fw_mon->size = size; 20088964b2eSSara Sharon } 20188964b2eSSara Sharon 20288964b2eSSara Sharon void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 20388964b2eSSara Sharon { 20488964b2eSSara Sharon if (!max_power) { 20588964b2eSSara Sharon /* default max_power is maximum */ 20688964b2eSSara Sharon max_power = 26; 20788964b2eSSara Sharon } else { 20888964b2eSSara Sharon max_power += 11; 20988964b2eSSara Sharon } 21088964b2eSSara Sharon 21188964b2eSSara Sharon if (WARN(max_power > 26, 21288964b2eSSara Sharon "External buffer size for monitor is too big %d, check the FW TLV\n", 21388964b2eSSara Sharon max_power)) 21488964b2eSSara Sharon return; 21588964b2eSSara Sharon 21669f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) 21788964b2eSSara Sharon return; 21888964b2eSSara Sharon 21988964b2eSSara Sharon iwl_pcie_alloc_fw_monitor_block(trans, max_power, 11); 220e705c121SKalle Valo } 221e705c121SKalle Valo 222e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 223e705c121SKalle Valo { 224e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 225e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 226e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 227e705c121SKalle Valo } 228e705c121SKalle Valo 229e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 230e705c121SKalle Valo { 231e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 232e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 233e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 234e705c121SKalle Valo } 235e705c121SKalle Valo 236e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 237e705c121SKalle Valo { 238e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 239e705c121SKalle Valo return; 240e705c121SKalle Valo 241e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 242e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 243e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 244e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 245e705c121SKalle Valo else 246e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 247e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 248e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 249e705c121SKalle Valo } 250e705c121SKalle Valo 251e705c121SKalle Valo /* PCI registers */ 252e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 253e705c121SKalle Valo 254eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 255e705c121SKalle Valo { 256e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 257e705c121SKalle Valo u16 lctl; 258e705c121SKalle Valo u16 cap; 259e705c121SKalle Valo 260e705c121SKalle Valo /* 261cc894b85SLuca Coelho * L0S states have been found to be unstable with our devices 262cc894b85SLuca Coelho * and in newer hardware they are not officially supported at 263cc894b85SLuca Coelho * all, so we must always set the L0S_DISABLED bit. 264e705c121SKalle Valo */ 2653d1b28fdSLuca Coelho iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 266cc894b85SLuca Coelho 267cc894b85SLuca Coelho pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 268e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 269e705c121SKalle Valo 270e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 271e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 272d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 273e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 274e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 275e705c121SKalle Valo } 276e705c121SKalle Valo 277e705c121SKalle Valo /* 278e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 279e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 280e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 281e705c121SKalle Valo */ 282e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 283e705c121SKalle Valo { 28452b6e168SEmmanuel Grumbach int ret; 28552b6e168SEmmanuel Grumbach 286e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 287e705c121SKalle Valo 288e705c121SKalle Valo /* 289e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 290e705c121SKalle Valo * bits already set by default after reset. 291e705c121SKalle Valo */ 292e705c121SKalle Valo 293e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 294286ca8ebSLuca Coelho if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 295e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 296e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 297e705c121SKalle Valo 298e705c121SKalle Valo /* 299e705c121SKalle Valo * Disable L0s without affecting L1; 300e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 301e705c121SKalle Valo */ 302e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 303e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 304e705c121SKalle Valo 305e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 306e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 307e705c121SKalle Valo 308e705c121SKalle Valo /* 309e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 310e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 311e705c121SKalle Valo */ 312e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 313e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 314e705c121SKalle Valo 315e705c121SKalle Valo iwl_pcie_apm_config(trans); 316e705c121SKalle Valo 317e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 318286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->pll_cfg) 31977d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 320e705c121SKalle Valo 321425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 322c96b5eecSJohannes Berg if (ret) 32352b6e168SEmmanuel Grumbach return ret; 324e705c121SKalle Valo 325e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 326e705c121SKalle Valo /* 327e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 328e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 329e705c121SKalle Valo * not related to host_interrupt_operation_mode. 330e705c121SKalle Valo * 331e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 332e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 333e705c121SKalle Valo * that we wake up from L1 on time. 334e705c121SKalle Valo * 335e705c121SKalle Valo * This looks weird: read twice the same register, discard the 336e705c121SKalle Valo * value, set a bit, and yet again, read that same register 337e705c121SKalle Valo * just to discard the value. But that's the way the hardware 338e705c121SKalle Valo * seems to like it. 339e705c121SKalle Valo */ 340e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 341e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 342e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 343e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 344e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 345e705c121SKalle Valo } 346e705c121SKalle Valo 347e705c121SKalle Valo /* 348e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 349e705c121SKalle Valo * 350e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 351e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 352e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 353e705c121SKalle Valo */ 354e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 355e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 356e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 357e705c121SKalle Valo udelay(20); 358e705c121SKalle Valo 359e705c121SKalle Valo /* Disable L1-Active */ 360e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 361e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 362e705c121SKalle Valo 363e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 364e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 365e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 366e705c121SKalle Valo } 367e705c121SKalle Valo 368e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 369e705c121SKalle Valo 37052b6e168SEmmanuel Grumbach return 0; 371e705c121SKalle Valo } 372e705c121SKalle Valo 373e705c121SKalle Valo /* 374e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 375e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 376e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 377e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 378e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 379e705c121SKalle Valo */ 380e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 381e705c121SKalle Valo { 382e705c121SKalle Valo int ret; 383e705c121SKalle Valo u32 apmg_gp1_reg; 384e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 385e705c121SKalle Valo u32 dl_cfg_reg; 386e705c121SKalle Valo 387e705c121SKalle Valo /* Force XTAL ON */ 388e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 389e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 390e705c121SKalle Valo 39115bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 392e705c121SKalle Valo 39315bf5ac6SJohannes Berg if (!ret) 394425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 39515bf5ac6SJohannes Berg 396c96b5eecSJohannes Berg if (WARN_ON(ret)) { 397e705c121SKalle Valo /* Release XTAL ON request */ 398e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 399e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 400e705c121SKalle Valo return; 401e705c121SKalle Valo } 402e705c121SKalle Valo 403e705c121SKalle Valo /* 404e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 405e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 406e705c121SKalle Valo */ 407e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 408e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 409e705c121SKalle Valo 410e705c121SKalle Valo /* 411e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 412e705c121SKalle Valo * caused by APMG idle state. 413e705c121SKalle Valo */ 414e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 415e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 417e705c121SKalle Valo apmg_xtal_cfg_reg | 418e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 419e705c121SKalle Valo 42015bf5ac6SJohannes Berg ret = iwl_trans_pcie_sw_reset(trans, true); 42115bf5ac6SJohannes Berg if (ret) 42215bf5ac6SJohannes Berg IWL_ERR(trans, 42315bf5ac6SJohannes Berg "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 424e705c121SKalle Valo 425e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 426e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 427e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 428e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 429e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 430e705c121SKalle Valo 431e705c121SKalle Valo /* Clear delay line clock power up */ 432e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 433e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 434e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 435e705c121SKalle Valo 436e705c121SKalle Valo /* 437e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 438e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 439e705c121SKalle Valo */ 440e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 441e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 442e705c121SKalle Valo 443e705c121SKalle Valo /* 444e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 445e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 446e705c121SKalle Valo */ 4476dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 448e705c121SKalle Valo 449e705c121SKalle Valo /* Activates XTAL resources monitor */ 450e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 451e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 452e705c121SKalle Valo 453e705c121SKalle Valo /* Release XTAL ON request */ 454e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 455e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 456e705c121SKalle Valo udelay(10); 457e705c121SKalle Valo 458e705c121SKalle Valo /* Release APMG XTAL */ 459e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 460e705c121SKalle Valo apmg_xtal_cfg_reg & 461e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 462e705c121SKalle Valo } 463e705c121SKalle Valo 464e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 465e705c121SKalle Valo { 466e8c8935eSJohannes Berg int ret; 467e705c121SKalle Valo 468e705c121SKalle Valo /* stop device's busmaster DMA activity */ 4699ce041f5SJohannes Berg 4709ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4719ce041f5SJohannes Berg iwl_set_bit(trans, CSR_GP_CNTRL, 4729ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 4739ce041f5SJohannes Berg 4749ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 4759ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4769ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 4779ce041f5SJohannes Berg 100); 47844b2dd40SRoee Goldfiner msleep(100); 4799ce041f5SJohannes Berg } else { 4806dece0e9SLuca Coelho iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 481e705c121SKalle Valo 4826dece0e9SLuca Coelho ret = iwl_poll_bit(trans, CSR_RESET, 4836dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 4846dece0e9SLuca Coelho CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 4859ce041f5SJohannes Berg } 4869ce041f5SJohannes Berg 487e705c121SKalle Valo if (ret < 0) 488e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 489e705c121SKalle Valo 490e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 491e705c121SKalle Valo } 492e705c121SKalle Valo 493e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 494e705c121SKalle Valo { 495e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 496e705c121SKalle Valo 497e705c121SKalle Valo if (op_mode_leave) { 498e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 499e705c121SKalle Valo iwl_pcie_apm_init(trans); 500e705c121SKalle Valo 501e705c121SKalle Valo /* inform ME that we are leaving */ 502286ca8ebSLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 503e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 504e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 505286ca8ebSLuca Coelho else if (trans->trans_cfg->device_family >= 50679b6c8feSLuca Coelho IWL_DEVICE_FAMILY_8000) { 507e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 508e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 509e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 510e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 511e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 512e705c121SKalle Valo mdelay(1); 513e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 514e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 515e705c121SKalle Valo } 516e705c121SKalle Valo mdelay(5); 517e705c121SKalle Valo } 518e705c121SKalle Valo 519e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 520e705c121SKalle Valo 521e705c121SKalle Valo /* Stop device's DMA activity */ 522e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 523e705c121SKalle Valo 524e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 525e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 526e705c121SKalle Valo return; 527e705c121SKalle Valo } 528e705c121SKalle Valo 52915bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, false); 530e705c121SKalle Valo 531e705c121SKalle Valo /* 532e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 533e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 534e705c121SKalle Valo */ 5356dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 536e705c121SKalle Valo } 537e705c121SKalle Valo 538e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 539e705c121SKalle Valo { 540e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 54152b6e168SEmmanuel Grumbach int ret; 542e705c121SKalle Valo 543e705c121SKalle Valo /* nic_init */ 54425edc8f2SJohannes Berg spin_lock_bh(&trans_pcie->irq_lock); 54552b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 54625edc8f2SJohannes Berg spin_unlock_bh(&trans_pcie->irq_lock); 547e705c121SKalle Valo 54852b6e168SEmmanuel Grumbach if (ret) 54952b6e168SEmmanuel Grumbach return ret; 55052b6e168SEmmanuel Grumbach 551e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 552e705c121SKalle Valo 553e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 554e705c121SKalle Valo 555e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 5569cf671d6SEmmanuel Grumbach ret = iwl_pcie_rx_init(trans); 5579cf671d6SEmmanuel Grumbach if (ret) 5589cf671d6SEmmanuel Grumbach return ret; 559e705c121SKalle Valo 560e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 5619cf671d6SEmmanuel Grumbach if (iwl_pcie_tx_init(trans)) { 5629cf671d6SEmmanuel Grumbach iwl_pcie_rx_free(trans); 563e705c121SKalle Valo return -ENOMEM; 5649cf671d6SEmmanuel Grumbach } 565e705c121SKalle Valo 566286ca8ebSLuca Coelho if (trans->trans_cfg->base_params->shadow_reg_enable) { 567e705c121SKalle Valo /* enable shadow regs in HW */ 568e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 569e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 570e705c121SKalle Valo } 571e705c121SKalle Valo 572e705c121SKalle Valo return 0; 573e705c121SKalle Valo } 574e705c121SKalle Valo 575e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 576e705c121SKalle Valo 577e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 578e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 579e705c121SKalle Valo { 580e705c121SKalle Valo int ret; 581e705c121SKalle Valo 582e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 583e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 584e705c121SKalle Valo 585e705c121SKalle Valo /* See if we got it */ 586e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 587e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 588e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 589e705c121SKalle Valo HW_READY_TIMEOUT); 590e705c121SKalle Valo 591e705c121SKalle Valo if (ret >= 0) 592e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 593e705c121SKalle Valo 594e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 595e705c121SKalle Valo return ret; 596e705c121SKalle Valo } 597e705c121SKalle Valo 598e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 599eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 600e705c121SKalle Valo { 601e705c121SKalle Valo int ret; 602e705c121SKalle Valo int iter; 603e705c121SKalle Valo 604e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 605e705c121SKalle Valo 606e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 607e705c121SKalle Valo /* If the card is ready, exit 0 */ 6086d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6096d19a5ebSEmmanuel Grumbach trans->csme_own = false; 610e705c121SKalle Valo return 0; 6116d19a5ebSEmmanuel Grumbach } 612e705c121SKalle Valo 613e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 614e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 615192185d6SJohannes Berg usleep_range(1000, 2000); 616e705c121SKalle Valo 617e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 618*28965ec0SEmmanuel Grumbach int t = 0; 619*28965ec0SEmmanuel Grumbach 620e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 621e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 622e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 623e705c121SKalle Valo 624e705c121SKalle Valo do { 625e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 6266d19a5ebSEmmanuel Grumbach if (ret >= 0) { 6276d19a5ebSEmmanuel Grumbach trans->csme_own = false; 628e705c121SKalle Valo return 0; 6296d19a5ebSEmmanuel Grumbach } 6306d19a5ebSEmmanuel Grumbach 6316d19a5ebSEmmanuel Grumbach if (iwl_mei_is_connected()) { 6326d19a5ebSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 6336d19a5ebSEmmanuel Grumbach "Couldn't prepare the card but SAP is connected\n"); 6346d19a5ebSEmmanuel Grumbach trans->csme_own = true; 6356d19a5ebSEmmanuel Grumbach if (trans->trans_cfg->device_family != 6366d19a5ebSEmmanuel Grumbach IWL_DEVICE_FAMILY_9000) 6376d19a5ebSEmmanuel Grumbach IWL_ERR(trans, 6386d19a5ebSEmmanuel Grumbach "SAP not supported for this NIC family\n"); 6396d19a5ebSEmmanuel Grumbach 6406d19a5ebSEmmanuel Grumbach return -EBUSY; 6416d19a5ebSEmmanuel Grumbach } 642e705c121SKalle Valo 643e705c121SKalle Valo usleep_range(200, 1000); 644e705c121SKalle Valo t += 200; 645e705c121SKalle Valo } while (t < 150000); 646e705c121SKalle Valo msleep(25); 647e705c121SKalle Valo } 648e705c121SKalle Valo 649e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 650e705c121SKalle Valo 651e705c121SKalle Valo return ret; 652e705c121SKalle Valo } 653e705c121SKalle Valo 654e705c121SKalle Valo /* 655e705c121SKalle Valo * ucode 656e705c121SKalle Valo */ 657564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 658564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 659564cdce7SSara Sharon u32 byte_cnt) 660e705c121SKalle Valo { 661bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 662e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 663e705c121SKalle Valo 664bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 665e705c121SKalle Valo dst_addr); 666e705c121SKalle Valo 667bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 668e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 669e705c121SKalle Valo 670bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 671e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 672e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 673e705c121SKalle Valo 674bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 675bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 676bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 677e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 678e705c121SKalle Valo 679bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 680e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 681e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 682e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 683564cdce7SSara Sharon } 684e705c121SKalle Valo 685564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 686564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 687564cdce7SSara Sharon u32 byte_cnt) 688564cdce7SSara Sharon { 689564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 690564cdce7SSara Sharon int ret; 691564cdce7SSara Sharon 692564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 693564cdce7SSara Sharon 6941ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 695564cdce7SSara Sharon return -EIO; 696564cdce7SSara Sharon 697564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 698564cdce7SSara Sharon byte_cnt); 6991ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 700bac842daSEmmanuel Grumbach 701e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 702e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 703e705c121SKalle Valo if (!ret) { 704e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 705fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 706e705c121SKalle Valo return -ETIMEDOUT; 707e705c121SKalle Valo } 708e705c121SKalle Valo 709e705c121SKalle Valo return 0; 710e705c121SKalle Valo } 711e705c121SKalle Valo 712e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 713e705c121SKalle Valo const struct fw_desc *section) 714e705c121SKalle Valo { 715e705c121SKalle Valo u8 *v_addr; 716e705c121SKalle Valo dma_addr_t p_addr; 717e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 718e705c121SKalle Valo int ret = 0; 719e705c121SKalle Valo 720e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 721e705c121SKalle Valo section_num); 722e705c121SKalle Valo 723e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 724e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 725e705c121SKalle Valo if (!v_addr) { 726e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 727e705c121SKalle Valo chunk_sz = PAGE_SIZE; 728e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 729e705c121SKalle Valo &p_addr, GFP_KERNEL); 730e705c121SKalle Valo if (!v_addr) 731e705c121SKalle Valo return -ENOMEM; 732e705c121SKalle Valo } 733e705c121SKalle Valo 734e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 735e705c121SKalle Valo u32 copy_size, dst_addr; 736e705c121SKalle Valo bool extended_addr = false; 737e705c121SKalle Valo 738e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 739e705c121SKalle Valo dst_addr = section->offset + offset; 740e705c121SKalle Valo 741e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 742e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 743e705c121SKalle Valo extended_addr = true; 744e705c121SKalle Valo 745e705c121SKalle Valo if (extended_addr) 746e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 747e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 748e705c121SKalle Valo 74973c289baSBjoern A. Zeeb memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 750e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 751e705c121SKalle Valo copy_size); 752e705c121SKalle Valo 753e705c121SKalle Valo if (extended_addr) 754e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 755e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 756e705c121SKalle Valo 757e705c121SKalle Valo if (ret) { 758e705c121SKalle Valo IWL_ERR(trans, 759e705c121SKalle Valo "Could not load the [%d] uCode section\n", 760e705c121SKalle Valo section_num); 761e705c121SKalle Valo break; 762e705c121SKalle Valo } 763e705c121SKalle Valo } 764e705c121SKalle Valo 765e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 766e705c121SKalle Valo return ret; 767e705c121SKalle Valo } 768e705c121SKalle Valo 769e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 770e705c121SKalle Valo const struct fw_img *image, 771e705c121SKalle Valo int cpu, 772e705c121SKalle Valo int *first_ucode_section) 773e705c121SKalle Valo { 774e705c121SKalle Valo int shift_param; 775e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 776e705c121SKalle Valo u32 val, last_read_idx = 0; 777e705c121SKalle Valo 778e705c121SKalle Valo if (cpu == 1) { 779e705c121SKalle Valo shift_param = 0; 780e705c121SKalle Valo *first_ucode_section = 0; 781e705c121SKalle Valo } else { 782e705c121SKalle Valo shift_param = 16; 783e705c121SKalle Valo (*first_ucode_section)++; 784e705c121SKalle Valo } 785e705c121SKalle Valo 786eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 787e705c121SKalle Valo last_read_idx = i; 788e705c121SKalle Valo 789e705c121SKalle Valo /* 790e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 791e705c121SKalle Valo * CPU1 to CPU2. 792e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 793e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 794e705c121SKalle Valo */ 795e705c121SKalle Valo if (!image->sec[i].data || 796e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 797e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 798e705c121SKalle Valo IWL_DEBUG_FW(trans, 799e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 800e705c121SKalle Valo i); 801e705c121SKalle Valo break; 802e705c121SKalle Valo } 803e705c121SKalle Valo 804e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 805e705c121SKalle Valo if (ret) 806e705c121SKalle Valo return ret; 807e705c121SKalle Valo 808d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 809e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 810e705c121SKalle Valo val = val | (sec_num << shift_param); 811e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 812eda50cdeSSara Sharon 813e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 814e705c121SKalle Valo } 815e705c121SKalle Valo 816e705c121SKalle Valo *first_ucode_section = last_read_idx; 817e705c121SKalle Valo 8182aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8192aabdbdcSEmmanuel Grumbach 820286ca8ebSLuca Coelho if (trans->trans_cfg->use_tfh) { 821e705c121SKalle Valo if (cpu == 1) 822d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 823d6a2c5c7SSara Sharon 0xFFFF); 824e705c121SKalle Valo else 825d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 826d6a2c5c7SSara Sharon 0xFFFFFFFF); 827d6a2c5c7SSara Sharon } else { 828d6a2c5c7SSara Sharon if (cpu == 1) 829d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 830d6a2c5c7SSara Sharon 0xFFFF); 831d6a2c5c7SSara Sharon else 832d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 833d6a2c5c7SSara Sharon 0xFFFFFFFF); 834d6a2c5c7SSara Sharon } 835e705c121SKalle Valo 836e705c121SKalle Valo return 0; 837e705c121SKalle Valo } 838e705c121SKalle Valo 839e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 840e705c121SKalle Valo const struct fw_img *image, 841e705c121SKalle Valo int cpu, 842e705c121SKalle Valo int *first_ucode_section) 843e705c121SKalle Valo { 844e705c121SKalle Valo int i, ret = 0; 845e705c121SKalle Valo u32 last_read_idx = 0; 846e705c121SKalle Valo 8473ce4a038SKirtika Ruchandani if (cpu == 1) 848e705c121SKalle Valo *first_ucode_section = 0; 8493ce4a038SKirtika Ruchandani else 850e705c121SKalle Valo (*first_ucode_section)++; 851e705c121SKalle Valo 852eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 853e705c121SKalle Valo last_read_idx = i; 854e705c121SKalle Valo 855e705c121SKalle Valo /* 856e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 857e705c121SKalle Valo * CPU1 to CPU2. 858e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 859e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 860e705c121SKalle Valo */ 861e705c121SKalle Valo if (!image->sec[i].data || 862e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 863e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 864e705c121SKalle Valo IWL_DEBUG_FW(trans, 865e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 866e705c121SKalle Valo i); 867e705c121SKalle Valo break; 868e705c121SKalle Valo } 869e705c121SKalle Valo 870e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 871e705c121SKalle Valo if (ret) 872e705c121SKalle Valo return ret; 873e705c121SKalle Valo } 874e705c121SKalle Valo 875e705c121SKalle Valo *first_ucode_section = last_read_idx; 876e705c121SKalle Valo 877e705c121SKalle Valo return 0; 878e705c121SKalle Valo } 879e705c121SKalle Valo 880593fae3eSShahar S Matityahu static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 881593fae3eSShahar S Matityahu { 882593fae3eSShahar S Matityahu enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 883593fae3eSShahar S Matityahu struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 884593fae3eSShahar S Matityahu &trans->dbg.fw_mon_cfg[alloc_id]; 885593fae3eSShahar S Matityahu struct iwl_dram_data *frag; 886593fae3eSShahar S Matityahu 887593fae3eSShahar S Matityahu if (!iwl_trans_dbg_ini_valid(trans)) 888593fae3eSShahar S Matityahu return; 889593fae3eSShahar S Matityahu 890593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) == 891593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_SRAM_PATH) { 892593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 893593fae3eSShahar S Matityahu /* set sram monitor by enabling bit 7 */ 894593fae3eSShahar S Matityahu iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 895593fae3eSShahar S Matityahu CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 896593fae3eSShahar S Matityahu 897593fae3eSShahar S Matityahu return; 898593fae3eSShahar S Matityahu } 899593fae3eSShahar S Matityahu 900593fae3eSShahar S Matityahu if (le32_to_cpu(fw_mon_cfg->buf_location) != 901593fae3eSShahar S Matityahu IWL_FW_INI_LOCATION_DRAM_PATH || 902593fae3eSShahar S Matityahu !trans->dbg.fw_mon_ini[alloc_id].num_frags) 903593fae3eSShahar S Matityahu return; 904593fae3eSShahar S Matityahu 905593fae3eSShahar S Matityahu frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 906593fae3eSShahar S Matityahu 907593fae3eSShahar S Matityahu IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 908593fae3eSShahar S Matityahu alloc_id); 909593fae3eSShahar S Matityahu 910593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 911593fae3eSShahar S Matityahu frag->physical >> MON_BUFF_SHIFT_VER2); 912593fae3eSShahar S Matityahu iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 913593fae3eSShahar S Matityahu (frag->physical + frag->size - 256) >> 914593fae3eSShahar S Matityahu MON_BUFF_SHIFT_VER2); 915593fae3eSShahar S Matityahu } 916593fae3eSShahar S Matityahu 917c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 918e705c121SKalle Valo { 91991c28b83SShahar S Matityahu const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 92069f0e505SShahar S Matityahu const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 921e705c121SKalle Valo int i; 922e705c121SKalle Valo 923a1af4c48SShahar S Matityahu if (iwl_trans_dbg_ini_valid(trans)) { 924593fae3eSShahar S Matityahu iwl_pcie_apply_destination_ini(trans); 9257a14c23dSSara Sharon return; 9267a14c23dSSara Sharon } 9277a14c23dSSara Sharon 928e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 929e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 930e705c121SKalle Valo 931e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 932e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 933e705c121SKalle Valo else 934e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 935e705c121SKalle Valo 93691c28b83SShahar S Matityahu for (i = 0; i < trans->dbg.n_dest_reg; i++) { 937e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 938e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 939e705c121SKalle Valo 940e705c121SKalle Valo switch (dest->reg_ops[i].op) { 941e705c121SKalle Valo case CSR_ASSIGN: 942e705c121SKalle Valo iwl_write32(trans, addr, val); 943e705c121SKalle Valo break; 944e705c121SKalle Valo case CSR_SETBIT: 945e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 946e705c121SKalle Valo break; 947e705c121SKalle Valo case CSR_CLEARBIT: 948e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 949e705c121SKalle Valo break; 950e705c121SKalle Valo case PRPH_ASSIGN: 951e705c121SKalle Valo iwl_write_prph(trans, addr, val); 952e705c121SKalle Valo break; 953e705c121SKalle Valo case PRPH_SETBIT: 954e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 955e705c121SKalle Valo break; 956e705c121SKalle Valo case PRPH_CLEARBIT: 957e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 958e705c121SKalle Valo break; 959e705c121SKalle Valo case PRPH_BLOCKBIT: 960e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 961e705c121SKalle Valo IWL_ERR(trans, 962e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 963e705c121SKalle Valo val, addr); 964e705c121SKalle Valo goto monitor; 965e705c121SKalle Valo } 966e705c121SKalle Valo break; 967e705c121SKalle Valo default: 968e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 969e705c121SKalle Valo dest->reg_ops[i].op); 970e705c121SKalle Valo break; 971e705c121SKalle Valo } 972e705c121SKalle Valo } 973e705c121SKalle Valo 974e705c121SKalle Valo monitor: 97569f0e505SShahar S Matityahu if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 976e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 97769f0e505SShahar S Matityahu fw_mon->physical >> dest->base_shift); 978286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 979e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98069f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size - 98169f0e505SShahar S Matityahu 256) >> dest->end_shift); 98262d7476dSEmmanuel Grumbach else 98362d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98469f0e505SShahar S Matityahu (fw_mon->physical + fw_mon->size) >> 98562d7476dSEmmanuel Grumbach dest->end_shift); 986e705c121SKalle Valo } 987e705c121SKalle Valo } 988e705c121SKalle Valo 989e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 990e705c121SKalle Valo const struct fw_img *image) 991e705c121SKalle Valo { 992e705c121SKalle Valo int ret = 0; 993e705c121SKalle Valo int first_ucode_section; 994e705c121SKalle Valo 995e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 996e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 997e705c121SKalle Valo 998e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 999e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1000e705c121SKalle Valo if (ret) 1001e705c121SKalle Valo return ret; 1002e705c121SKalle Valo 1003e705c121SKalle Valo if (image->is_dual_cpus) { 1004e705c121SKalle Valo /* set CPU2 header address */ 1005e705c121SKalle Valo iwl_write_prph(trans, 1006e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1007e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1010e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1011e705c121SKalle Valo &first_ucode_section); 1012e705c121SKalle Valo if (ret) 1013e705c121SKalle Valo return ret; 1014e705c121SKalle Valo } 1015e705c121SKalle Valo 10169efab1adSEmmanuel Grumbach if (iwl_pcie_dbg_on(trans)) 1017e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1018e705c121SKalle Valo 10192aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10202aabdbdcSEmmanuel Grumbach 1021e705c121SKalle Valo /* release CPU reset */ 1022e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1023e705c121SKalle Valo 1024e705c121SKalle Valo return 0; 1025e705c121SKalle Valo } 1026e705c121SKalle Valo 1027e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1028e705c121SKalle Valo const struct fw_img *image) 1029e705c121SKalle Valo { 1030e705c121SKalle Valo int ret = 0; 1031e705c121SKalle Valo int first_ucode_section; 1032e705c121SKalle Valo 1033e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1034e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1035e705c121SKalle Valo 10367a14c23dSSara Sharon if (iwl_pcie_dbg_on(trans)) 1037e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1038e705c121SKalle Valo 103982ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 104082ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 104182ea7966SSara Sharon 104282ea7966SSara Sharon /* 104382ea7966SSara Sharon * Set default value. On resume reading the values that were 104482ea7966SSara Sharon * zeored can provide debug data on the resume flow. 104582ea7966SSara Sharon * This is for debugging only and has no functional impact. 104682ea7966SSara Sharon */ 104782ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 104882ea7966SSara Sharon 1049e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1050e705c121SKalle Valo /* release CPU reset */ 1051e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1052e705c121SKalle Valo 1053e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1054e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1055e705c121SKalle Valo &first_ucode_section); 1056e705c121SKalle Valo if (ret) 1057e705c121SKalle Valo return ret; 1058e705c121SKalle Valo 1059e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1060e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1061e705c121SKalle Valo &first_ucode_section); 1062e705c121SKalle Valo } 1063e705c121SKalle Valo 10649ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1065727c02dfSSara Sharon { 1066326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1067727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1068326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1069326477e4SJohannes Berg bool report; 1070727c02dfSSara Sharon 1071326477e4SJohannes Berg if (hw_rfkill) { 1072326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1073326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1074326477e4SJohannes Berg } else { 1075326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1076326477e4SJohannes Berg if (trans_pcie->opmode_down) 1077326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1078326477e4SJohannes Berg } 1079727c02dfSSara Sharon 1080326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1081326477e4SJohannes Berg 1082326477e4SJohannes Berg if (prev != report) 1083326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1084727c02dfSSara Sharon 1085727c02dfSSara Sharon return hw_rfkill; 1086727c02dfSSara Sharon } 1087727c02dfSSara Sharon 10887ca00409SHaim Dreyfuss struct iwl_causes_list { 1089c1918196SJohannes Berg u16 mask_reg; 1090c1918196SJohannes Berg u8 bit; 10917ca00409SHaim Dreyfuss u8 addr; 10927ca00409SHaim Dreyfuss }; 10937ca00409SHaim Dreyfuss 10949c683731SJohannes Berg #define IWL_CAUSE(reg, mask) \ 1095c1918196SJohannes Berg { \ 1096c1918196SJohannes Berg .mask_reg = reg, \ 1097c1918196SJohannes Berg .bit = ilog2(mask), \ 1098c1918196SJohannes Berg .addr = ilog2(mask) + \ 1099c1918196SJohannes Berg ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1100c1918196SJohannes Berg (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1101c1918196SJohannes Berg 0xffff), /* causes overflow warning */ \ 1102c1918196SJohannes Berg } 1103c1918196SJohannes Berg 1104571836a0SMike Golant static const struct iwl_causes_list causes_list_common[] = { 11059c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 11069c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 11079c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 11089c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 11099c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 11109c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 11119c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 11129c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 11139c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 11149c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 11159c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 11169c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 11179c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 11189c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 11197ca00409SHaim Dreyfuss }; 11207ca00409SHaim Dreyfuss 1121571836a0SMike Golant static const struct iwl_causes_list causes_list_pre_bz[] = { 11229c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1123571836a0SMike Golant }; 11247ca00409SHaim Dreyfuss 1125571836a0SMike Golant static const struct iwl_causes_list causes_list_bz[] = { 11269c683731SJohannes Berg IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1127571836a0SMike Golant }; 1128571836a0SMike Golant 1129571836a0SMike Golant static void iwl_pcie_map_list(struct iwl_trans *trans, 1130571836a0SMike Golant const struct iwl_causes_list *causes, 1131571836a0SMike Golant int arr_size, int val) 1132571836a0SMike Golant { 1133571836a0SMike Golant int i; 1134571836a0SMike Golant 11359b58419eSGolan Ben Ami for (i = 0; i < arr_size; i++) { 11369b58419eSGolan Ben Ami iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 11379b58419eSGolan Ben Ami iwl_clear_bit(trans, causes[i].mask_reg, 1138c1918196SJohannes Berg BIT(causes[i].bit)); 11397ca00409SHaim Dreyfuss } 11407ca00409SHaim Dreyfuss } 11417ca00409SHaim Dreyfuss 1142571836a0SMike Golant static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1143571836a0SMike Golant { 1144571836a0SMike Golant struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1145571836a0SMike Golant int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1146571836a0SMike Golant /* 1147571836a0SMike Golant * Access all non RX causes and map them to the default irq. 1148571836a0SMike Golant * In case we are missing at least one interrupt vector, 1149571836a0SMike Golant * the first interrupt vector will serve non-RX and FBQ causes. 1150571836a0SMike Golant */ 1151571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_common, 1152571836a0SMike Golant ARRAY_SIZE(causes_list_common), val); 1153571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1154571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_bz, 1155571836a0SMike Golant ARRAY_SIZE(causes_list_bz), val); 1156571836a0SMike Golant else 1157571836a0SMike Golant iwl_pcie_map_list(trans, causes_list_pre_bz, 1158571836a0SMike Golant ARRAY_SIZE(causes_list_pre_bz), val); 1159571836a0SMike Golant } 1160571836a0SMike Golant 11617ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11627ca00409SHaim Dreyfuss { 11637ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11647ca00409SHaim Dreyfuss u32 offset = 11657ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11667ca00409SHaim Dreyfuss u32 val, idx; 11677ca00409SHaim Dreyfuss 11687ca00409SHaim Dreyfuss /* 11697ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11707ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11717ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11727ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11737ca00409SHaim Dreyfuss */ 11747ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11757ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11767ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11777ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11787ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11797ca00409SHaim Dreyfuss } 11807ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11817ca00409SHaim Dreyfuss 11827ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11837ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11847ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11857ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11867ca00409SHaim Dreyfuss 11877ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11887ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11897ca00409SHaim Dreyfuss } 11907ca00409SHaim Dreyfuss 119177c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11927ca00409SHaim Dreyfuss { 11937ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11947ca00409SHaim Dreyfuss 11957ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1196286ca8ebSLuca Coelho if (trans->trans_cfg->mq_rx_supported && 1197d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1198ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, 11997ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 12007ca00409SHaim Dreyfuss return; 12017ca00409SHaim Dreyfuss } 1202d7270d61SHaim Dreyfuss /* 1203d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1204d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1205d7270d61SHaim Dreyfuss * prph. 1206d7270d61SHaim Dreyfuss */ 1207d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1208ea695b7cSShaul Triebitz iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 12097ca00409SHaim Dreyfuss 12107ca00409SHaim Dreyfuss /* 12117ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 12127ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 12137ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 12147ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 12157ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 12167ca00409SHaim Dreyfuss */ 12177ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12187ca00409SHaim Dreyfuss 12197ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 122083730058SHaim Dreyfuss } 12217ca00409SHaim Dreyfuss 122283730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 122383730058SHaim Dreyfuss { 122483730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 122583730058SHaim Dreyfuss 122683730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 122783730058SHaim Dreyfuss 122883730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 122983730058SHaim Dreyfuss return; 123083730058SHaim Dreyfuss 123183730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12327ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 123383730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12347ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12357ca00409SHaim Dreyfuss } 12367ca00409SHaim Dreyfuss 1237bab3cb92SEmmanuel Grumbach static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1238e705c121SKalle Valo { 1239e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1240e705c121SKalle Valo 1241e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1242e705c121SKalle Valo 1243e705c121SKalle Valo if (trans_pcie->is_down) 1244e705c121SKalle Valo return; 1245e705c121SKalle Valo 1246e705c121SKalle Valo trans_pcie->is_down = true; 1247e705c121SKalle Valo 1248e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1249e705c121SKalle Valo iwl_disable_interrupts(trans); 1250e705c121SKalle Valo 1251e705c121SKalle Valo /* device going down, Stop using ICT table */ 1252e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1253e705c121SKalle Valo 1254e705c121SKalle Valo /* 1255e705c121SKalle Valo * If a HW restart happens during firmware loading, 1256e705c121SKalle Valo * then the firmware loading might call this function 1257e705c121SKalle Valo * and later it might be called again due to the 1258e705c121SKalle Valo * restart. So don't process again if the device is 1259e705c121SKalle Valo * already dead. 1260e705c121SKalle Valo */ 1261e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1262a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1263a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 12645af2bb31SGregory Greenman iwl_pcie_rx_napi_sync(trans); 1265e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1266e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1267e705c121SKalle Valo 1268e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1269e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1270e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1271e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1272e705c121SKalle Valo udelay(5); 1273e705c121SKalle Valo } 1274e705c121SKalle Valo } 1275e705c121SKalle Valo 1276e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 12771b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 12781b6598c3SRoee Goldfiner iwl_clear_bit(trans, CSR_GP_CNTRL, 12791b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 12801b6598c3SRoee Goldfiner else 1281e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 12826dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1283e705c121SKalle Valo 1284e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1285e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1286e705c121SKalle Valo 128715bf5ac6SJohannes Berg /* re-take ownership to prevent other users from stealing the device */ 128815bf5ac6SJohannes Berg iwl_trans_pcie_sw_reset(trans, true); 1289e705c121SKalle Valo 1290e705c121SKalle Valo /* 1291f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1292f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1293f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1294f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1295f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1296f4a1f04aSGolan Ben Ami */ 1297f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1298f4a1f04aSGolan Ben Ami 1299f4a1f04aSGolan Ben Ami /* 1300e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1301e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1302e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1303e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1304e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1305e705c121SKalle Valo */ 1306e705c121SKalle Valo iwl_disable_interrupts(trans); 1307e705c121SKalle Valo 1308e705c121SKalle Valo /* clear all status bits */ 1309e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1310e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1311e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1312e705c121SKalle Valo 1313e705c121SKalle Valo /* 1314e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1315e705c121SKalle Valo * interrupt 1316e705c121SKalle Valo */ 1317e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1318e705c121SKalle Valo } 1319e705c121SKalle Valo 1320eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13212e5d4a8fSHaim Dreyfuss { 13222e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13232e5d4a8fSHaim Dreyfuss 13242e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13252e5d4a8fSHaim Dreyfuss int i; 13262e5d4a8fSHaim Dreyfuss 1327496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13282e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13292e5d4a8fSHaim Dreyfuss } else { 13302e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13312e5d4a8fSHaim Dreyfuss } 13322e5d4a8fSHaim Dreyfuss } 13332e5d4a8fSHaim Dreyfuss 1334a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1335a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1336a6bd005fSEmmanuel Grumbach { 1337a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1338a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1339a6bd005fSEmmanuel Grumbach int ret; 1340a6bd005fSEmmanuel Grumbach 1341a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1342a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1343a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1344e9848aedSJohannes Berg return -EIO; 1345a6bd005fSEmmanuel Grumbach } 1346a6bd005fSEmmanuel Grumbach 1347a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1348a6bd005fSEmmanuel Grumbach 1349a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1350a6bd005fSEmmanuel Grumbach 1351a6bd005fSEmmanuel Grumbach /* 1352a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1353a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1354a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1355a6bd005fSEmmanuel Grumbach */ 1356a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1357a6bd005fSEmmanuel Grumbach 1358a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13592e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1360a6bd005fSEmmanuel Grumbach 1361a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1362a6bd005fSEmmanuel Grumbach 1363a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13649ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1365a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1366a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1367a6bd005fSEmmanuel Grumbach goto out; 1368a6bd005fSEmmanuel Grumbach } 1369a6bd005fSEmmanuel Grumbach 1370a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1371a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1372a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1373a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 137420aa99bbSAnton Protopopov ret = -EIO; 1375a6bd005fSEmmanuel Grumbach goto out; 1376a6bd005fSEmmanuel Grumbach } 1377a6bd005fSEmmanuel Grumbach 1378a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1379a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1380a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1381a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1382a6bd005fSEmmanuel Grumbach 1383a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1384a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1385a6bd005fSEmmanuel Grumbach 1386a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1387a6bd005fSEmmanuel Grumbach if (ret) { 1388a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1389a6bd005fSEmmanuel Grumbach goto out; 1390a6bd005fSEmmanuel Grumbach } 1391a6bd005fSEmmanuel Grumbach 1392a6bd005fSEmmanuel Grumbach /* 1393a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1394a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1395a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1396a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1397a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1398a6bd005fSEmmanuel Grumbach */ 1399a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1400a6bd005fSEmmanuel Grumbach 1401a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1402a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1403a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1404a6bd005fSEmmanuel Grumbach 1405a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1406286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1407a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1408a6bd005fSEmmanuel Grumbach else 1409a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1410a6bd005fSEmmanuel Grumbach 1411a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14129ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1413a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1414a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1415a6bd005fSEmmanuel Grumbach 1416a6bd005fSEmmanuel Grumbach out: 1417a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1418a6bd005fSEmmanuel Grumbach return ret; 1419a6bd005fSEmmanuel Grumbach } 1420a6bd005fSEmmanuel Grumbach 1421a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1422a6bd005fSEmmanuel Grumbach { 1423a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1424a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1425a6bd005fSEmmanuel Grumbach } 1426a6bd005fSEmmanuel Grumbach 1427326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1428326477e4SJohannes Berg bool was_in_rfkill) 1429326477e4SJohannes Berg { 1430326477e4SJohannes Berg bool hw_rfkill; 1431326477e4SJohannes Berg 1432326477e4SJohannes Berg /* 1433326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1434326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1435326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1436326477e4SJohannes Berg * op_mode. 1437326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1438326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1439326477e4SJohannes Berg * notification without endless recursion. Under very rare 1440326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1441326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1442326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1443326477e4SJohannes Berg */ 1444326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1445326477e4SJohannes Berg if (hw_rfkill) { 1446326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1447326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1448326477e4SJohannes Berg } else { 1449326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1450326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1451326477e4SJohannes Berg } 1452326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1453326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1454326477e4SJohannes Berg } 1455326477e4SJohannes Berg 1456bab3cb92SEmmanuel Grumbach static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1457e705c121SKalle Valo { 1458e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1459326477e4SJohannes Berg bool was_in_rfkill; 1460e705c121SKalle Valo 1461d0129315SMordechay Goodstein iwl_op_mode_time_point(trans->op_mode, 1462d0129315SMordechay Goodstein IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1463d0129315SMordechay Goodstein NULL); 1464d0129315SMordechay Goodstein 1465e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1466326477e4SJohannes Berg trans_pcie->opmode_down = true; 1467326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1468bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1469326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1470e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1471e705c121SKalle Valo } 1472e705c121SKalle Valo 1473e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1474e705c121SKalle Valo { 1475e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1476e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1477e705c121SKalle Valo 1478e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1479e705c121SKalle Valo 1480326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1481326477e4SJohannes Berg state ? "disabled" : "enabled"); 148277c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1483286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 1484bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_gen2_stop_device(trans); 148577c09bc8SSara Sharon else 1486bab3cb92SEmmanuel Grumbach _iwl_trans_pcie_stop_device(trans); 1487e705c121SKalle Valo } 148877c09bc8SSara Sharon } 1489e705c121SKalle Valo 1490e5f3f215SHaim Dreyfuss void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1491e5f3f215SHaim Dreyfuss bool test, bool reset) 1492e705c121SKalle Valo { 1493e705c121SKalle Valo iwl_disable_interrupts(trans); 1494e705c121SKalle Valo 1495e705c121SKalle Valo /* 1496e705c121SKalle Valo * in testing mode, the host stays awake and the 1497e705c121SKalle Valo * hardware won't be reset (not even partially) 1498e705c121SKalle Valo */ 1499e705c121SKalle Valo if (test) 1500e705c121SKalle Valo return; 1501e705c121SKalle Valo 1502e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1503e705c121SKalle Valo 15042e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1505e705c121SKalle Valo 1506e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 15076dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 15086dece0e9SLuca Coelho iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1509e705c121SKalle Valo 151023ae6128SMatti Gottlieb if (reset) { 1511e705c121SKalle Valo /* 1512e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1513e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1514e705c121SKalle Valo * to execute some invalid memory upon resume 1515e705c121SKalle Valo */ 1516e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1517e705c121SKalle Valo } 1518e705c121SKalle Valo 1519e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1520e705c121SKalle Valo } 1521e705c121SKalle Valo 1522af08571dSHaim Dreyfuss static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1523af08571dSHaim Dreyfuss { 1524af08571dSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1525af08571dSHaim Dreyfuss int ret; 1526af08571dSHaim Dreyfuss 1527277f56a1SAvraham Stern if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1528af08571dSHaim Dreyfuss iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1529af08571dSHaim Dreyfuss suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1530af08571dSHaim Dreyfuss UREG_DOORBELL_TO_ISR6_RESUME); 1531277f56a1SAvraham Stern else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1532af08571dSHaim Dreyfuss iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1533af08571dSHaim Dreyfuss suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1534af08571dSHaim Dreyfuss CSR_IPC_SLEEP_CONTROL_RESUME); 1535277f56a1SAvraham Stern else 1536af08571dSHaim Dreyfuss return 0; 1537af08571dSHaim Dreyfuss 1538af08571dSHaim Dreyfuss ret = wait_event_timeout(trans_pcie->sx_waitq, 1539af08571dSHaim Dreyfuss trans_pcie->sx_complete, 2 * HZ); 1540af08571dSHaim Dreyfuss 1541af08571dSHaim Dreyfuss /* Invalidate it toward next suspend or resume */ 1542af08571dSHaim Dreyfuss trans_pcie->sx_complete = false; 1543af08571dSHaim Dreyfuss 1544af08571dSHaim Dreyfuss if (!ret) { 1545af08571dSHaim Dreyfuss IWL_ERR(trans, "Timeout %s D3\n", 1546af08571dSHaim Dreyfuss suspend ? "entering" : "exiting"); 1547af08571dSHaim Dreyfuss return -ETIMEDOUT; 1548af08571dSHaim Dreyfuss } 1549af08571dSHaim Dreyfuss 1550af08571dSHaim Dreyfuss return 0; 1551af08571dSHaim Dreyfuss } 1552af08571dSHaim Dreyfuss 1553e5f3f215SHaim Dreyfuss static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1554e5f3f215SHaim Dreyfuss bool reset) 1555e5f3f215SHaim Dreyfuss { 1556e5f3f215SHaim Dreyfuss int ret; 1557e5f3f215SHaim Dreyfuss 1558771db3a1SHaim Dreyfuss if (!reset) 1559e5f3f215SHaim Dreyfuss /* Enable persistence mode to avoid reset */ 1560e5f3f215SHaim Dreyfuss iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1561e5f3f215SHaim Dreyfuss CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1562e5f3f215SHaim Dreyfuss 1563af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, true); 1564af08571dSHaim Dreyfuss if (ret) 1565af08571dSHaim Dreyfuss return ret; 1566e5f3f215SHaim Dreyfuss 1567e5f3f215SHaim Dreyfuss iwl_pcie_d3_complete_suspend(trans, test, reset); 1568e5f3f215SHaim Dreyfuss 1569e5f3f215SHaim Dreyfuss return 0; 1570e5f3f215SHaim Dreyfuss } 1571e5f3f215SHaim Dreyfuss 1572e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1573e705c121SKalle Valo enum iwl_d3_status *status, 157423ae6128SMatti Gottlieb bool test, bool reset) 1575e705c121SKalle Valo { 1576d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1577e705c121SKalle Valo u32 val; 1578e705c121SKalle Valo int ret; 1579e705c121SKalle Valo 1580e705c121SKalle Valo if (test) { 1581e705c121SKalle Valo iwl_enable_interrupts(trans); 1582e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1583af08571dSHaim Dreyfuss ret = 0; 1584e5f3f215SHaim Dreyfuss goto out; 1585e705c121SKalle Valo } 1586e705c121SKalle Valo 1587a8cbb46fSGolan Ben Ami iwl_set_bit(trans, CSR_GP_CNTRL, 15886dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1589e705c121SKalle Valo 1590425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 1591c96b5eecSJohannes Berg if (ret) 1592e705c121SKalle Valo return ret; 1593e705c121SKalle Valo 1594f98ad635SEmmanuel Grumbach /* 1595f98ad635SEmmanuel Grumbach * Reconfigure IVAR table in case of MSIX or reset ict table in 1596f98ad635SEmmanuel Grumbach * MSI mode since HW reset erased it. 1597f98ad635SEmmanuel Grumbach * Also enables interrupts - none will happen as 1598f98ad635SEmmanuel Grumbach * the device doesn't know we're waking it up, only when 1599f98ad635SEmmanuel Grumbach * the opmode actually tells it after this call. 1600f98ad635SEmmanuel Grumbach */ 1601f98ad635SEmmanuel Grumbach iwl_pcie_conf_msix_hw(trans_pcie); 1602f98ad635SEmmanuel Grumbach if (!trans_pcie->msix_enabled) 1603f98ad635SEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1604f98ad635SEmmanuel Grumbach iwl_enable_interrupts(trans); 1605f98ad635SEmmanuel Grumbach 1606e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1607e705c121SKalle Valo 160823ae6128SMatti Gottlieb if (!reset) { 1609e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 16106dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1611e705c121SKalle Valo } else { 1612e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1613e705c121SKalle Valo 1614e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1615e705c121SKalle Valo if (ret) { 1616e705c121SKalle Valo IWL_ERR(trans, 1617e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1618e705c121SKalle Valo return ret; 1619e705c121SKalle Valo } 1620e705c121SKalle Valo } 1621e705c121SKalle Valo 162282ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1623ea695b7cSShaul Triebitz iwl_read_umac_prph(trans, WFPM_GP2)); 162482ea7966SSara Sharon 1625e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1626e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1627e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1628e705c121SKalle Valo else 1629e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1630e705c121SKalle Valo 1631e5f3f215SHaim Dreyfuss out: 1632af08571dSHaim Dreyfuss if (*status == IWL_D3_STATUS_ALIVE) 1633af08571dSHaim Dreyfuss ret = iwl_pcie_d3_handshake(trans, false); 1634e5f3f215SHaim Dreyfuss 1635af08571dSHaim Dreyfuss return ret; 1636e705c121SKalle Valo } 1637e705c121SKalle Valo 16380c18714aSLuca Coelho static void 16390c18714aSLuca Coelho iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 16400c18714aSLuca Coelho struct iwl_trans *trans, 16410c18714aSLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 16422e5d4a8fSHaim Dreyfuss { 16432e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1644ab1068d6SHao Wei Tee int max_irqs, num_irqs, i, ret; 16452e5d4a8fSHaim Dreyfuss u16 pci_cmd; 16460cd38f4dSMordechay Goodstein u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 16472e5d4a8fSHaim Dreyfuss 16480c18714aSLuca Coelho if (!cfg_trans->mq_rx_supported) 164906f4b081SSara Sharon goto enable_msi; 165006f4b081SSara Sharon 16510cd38f4dSMordechay Goodstein if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 16520cd38f4dSMordechay Goodstein max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 16530cd38f4dSMordechay Goodstein 16540cd38f4dSMordechay Goodstein max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 165506f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16562e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16572e5d4a8fSHaim Dreyfuss 165806f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16592e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 166006f4b081SSara Sharon max_irqs); 166106f4b081SSara Sharon if (num_irqs < 0) { 1662496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 166306f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 166406f4b081SSara Sharon num_irqs); 166506f4b081SSara Sharon goto enable_msi; 1666496d83caSHaim Dreyfuss } 166706f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1668496d83caSHaim Dreyfuss 16692e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 167006f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 167106f4b081SSara Sharon num_irqs); 167206f4b081SSara Sharon 1673496d83caSHaim Dreyfuss /* 167406f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 167506f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1676496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1677496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1678496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1679496d83caSHaim Dreyfuss */ 1680ab1068d6SHao Wei Tee if (num_irqs <= max_irqs - 2) { 168106f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1682496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1683496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 1684ab1068d6SHao Wei Tee } else if (num_irqs == max_irqs - 1) { 168506f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1686496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1687496d83caSHaim Dreyfuss } else { 168806f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1689496d83caSHaim Dreyfuss } 16909d401222SMordechay Goodstein 16919d401222SMordechay Goodstein IWL_DEBUG_INFO(trans, 16929d401222SMordechay Goodstein "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 16939d401222SMordechay Goodstein trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 16949d401222SMordechay Goodstein 1695ab1068d6SHao Wei Tee WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 16962e5d4a8fSHaim Dreyfuss 169706f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1698496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16992e5d4a8fSHaim Dreyfuss return; 17002e5d4a8fSHaim Dreyfuss 170106f4b081SSara Sharon enable_msi: 170206f4b081SSara Sharon ret = pci_enable_msi(pdev); 170306f4b081SSara Sharon if (ret) { 170406f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 17052e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 17062e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 17072e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 17082e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 17092e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 17102e5d4a8fSHaim Dreyfuss } 17112e5d4a8fSHaim Dreyfuss } 17122e5d4a8fSHaim Dreyfuss } 17132e5d4a8fSHaim Dreyfuss 17147c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 17157c8d91ebSHaim Dreyfuss { 17167c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 17177c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17187c8d91ebSHaim Dreyfuss 17197c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 17207c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 17217c8d91ebSHaim Dreyfuss offset = 1 + i; 17227c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 17237c8d91ebSHaim Dreyfuss /* 17247c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 17257c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 17267c8d91ebSHaim Dreyfuss */ 17277c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 17287c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 17297c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 17307c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 17317c8d91ebSHaim Dreyfuss if (ret) 17327c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17337c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 173457e6492cSJohannes Berg trans_pcie->msix_entries[i].vector); 17357c8d91ebSHaim Dreyfuss } 17367c8d91ebSHaim Dreyfuss } 17377c8d91ebSHaim Dreyfuss 17382e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17392e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17402e5d4a8fSHaim Dreyfuss { 1741496d83caSHaim Dreyfuss int i; 17422e5d4a8fSHaim Dreyfuss 1743496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17442e5d4a8fSHaim Dreyfuss int ret; 17455a41a86cSSharon Dvir struct msix_entry *msix_entry; 174664fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 174764fa3affSSharon Dvir 174864fa3affSSharon Dvir if (!qname) 174964fa3affSSharon Dvir return -ENOMEM; 17502e5d4a8fSHaim Dreyfuss 17515a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17525a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17535a41a86cSSharon Dvir msix_entry->vector, 17542e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1755496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17562e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17572e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17582e5d4a8fSHaim Dreyfuss IRQF_SHARED, 175964fa3affSSharon Dvir qname, 17605a41a86cSSharon Dvir msix_entry); 17612e5d4a8fSHaim Dreyfuss if (ret) { 17622e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17632e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17645a41a86cSSharon Dvir 17652e5d4a8fSHaim Dreyfuss return ret; 17662e5d4a8fSHaim Dreyfuss } 17672e5d4a8fSHaim Dreyfuss } 17687c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17692e5d4a8fSHaim Dreyfuss 17702e5d4a8fSHaim Dreyfuss return 0; 17712e5d4a8fSHaim Dreyfuss } 17722e5d4a8fSHaim Dreyfuss 177344f61b5cSShahar S Matityahu static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 177444f61b5cSShahar S Matityahu { 177544f61b5cSShahar S Matityahu u32 hpm, wprot; 177644f61b5cSShahar S Matityahu 1777286ca8ebSLuca Coelho switch (trans->trans_cfg->device_family) { 177844f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_9000: 177944f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_9000; 178044f61b5cSShahar S Matityahu break; 178144f61b5cSShahar S Matityahu case IWL_DEVICE_FAMILY_22000: 178244f61b5cSShahar S Matityahu wprot = PREG_PRPH_WPROT_22000; 178344f61b5cSShahar S Matityahu break; 178444f61b5cSShahar S Matityahu default: 178544f61b5cSShahar S Matityahu return 0; 178644f61b5cSShahar S Matityahu } 178744f61b5cSShahar S Matityahu 178844f61b5cSShahar S Matityahu hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 178944f61b5cSShahar S Matityahu if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) { 179044f61b5cSShahar S Matityahu u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 179144f61b5cSShahar S Matityahu 179244f61b5cSShahar S Matityahu if (wprot_val & PREG_WFPM_ACCESS) { 179344f61b5cSShahar S Matityahu IWL_ERR(trans, 179444f61b5cSShahar S Matityahu "Error, can not clear persistence bit\n"); 179544f61b5cSShahar S Matityahu return -EPERM; 179644f61b5cSShahar S Matityahu } 179744f61b5cSShahar S Matityahu iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 179844f61b5cSShahar S Matityahu hpm & ~PERSISTENCE_BIT); 179944f61b5cSShahar S Matityahu } 180044f61b5cSShahar S Matityahu 180144f61b5cSShahar S Matityahu return 0; 180244f61b5cSShahar S Matityahu } 180344f61b5cSShahar S Matityahu 18040df36b90SLuca Coelho static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 18050df36b90SLuca Coelho { 18060df36b90SLuca Coelho int ret; 18070df36b90SLuca Coelho 1808425d66d8SJohannes Berg ret = iwl_finish_nic_init(trans); 18090df36b90SLuca Coelho if (ret < 0) 18100df36b90SLuca Coelho return ret; 18110df36b90SLuca Coelho 18120df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18130df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18140df36b90SLuca Coelho udelay(20); 18150df36b90SLuca Coelho iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 18160df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_PG_EN | 18170df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_SLP_EN); 18180df36b90SLuca Coelho udelay(20); 18190df36b90SLuca Coelho iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 18200df36b90SLuca Coelho HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 18210df36b90SLuca Coelho 182215bf5ac6SJohannes Berg return iwl_trans_pcie_sw_reset(trans, true); 18230df36b90SLuca Coelho } 18240df36b90SLuca Coelho 1825bab3cb92SEmmanuel Grumbach static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1826e705c121SKalle Valo { 1827e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1828e705c121SKalle Valo int err; 1829e705c121SKalle Valo 1830e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1831e705c121SKalle Valo 1832e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1833e705c121SKalle Valo if (err) { 1834e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1835e705c121SKalle Valo return err; 1836e705c121SKalle Valo } 1837e705c121SKalle Valo 183844f61b5cSShahar S Matityahu err = iwl_trans_pcie_clear_persistence_bit(trans); 183944f61b5cSShahar S Matityahu if (err) 184044f61b5cSShahar S Matityahu return err; 18418954e1ebSShahar S Matityahu 184215bf5ac6SJohannes Berg err = iwl_trans_pcie_sw_reset(trans, true); 184315bf5ac6SJohannes Berg if (err) 184415bf5ac6SJohannes Berg return err; 1845e705c121SKalle Valo 18460df36b90SLuca Coelho if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 18477897dfa2SLuca Coelho trans->trans_cfg->integrated) { 18480df36b90SLuca Coelho err = iwl_pcie_gen2_force_power_gating(trans); 18490df36b90SLuca Coelho if (err) 18500df36b90SLuca Coelho return err; 18510df36b90SLuca Coelho } 18520df36b90SLuca Coelho 185352b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 185452b6e168SEmmanuel Grumbach if (err) 185552b6e168SEmmanuel Grumbach return err; 1856e705c121SKalle Valo 18572e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 185883730058SHaim Dreyfuss 1859e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1860e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1861e705c121SKalle Valo 1862326477e4SJohannes Berg trans_pcie->opmode_down = false; 1863326477e4SJohannes Berg 1864e705c121SKalle Valo /* Set is_down to false here so that...*/ 1865e705c121SKalle Valo trans_pcie->is_down = false; 1866e705c121SKalle Valo 1867e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 18689ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1869e705c121SKalle Valo 1870e705c121SKalle Valo return 0; 1871e705c121SKalle Valo } 1872e705c121SKalle Valo 1873bab3cb92SEmmanuel Grumbach static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1874e705c121SKalle Valo { 1875e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1876e705c121SKalle Valo int ret; 1877e705c121SKalle Valo 1878e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1879bab3cb92SEmmanuel Grumbach ret = _iwl_trans_pcie_start_hw(trans); 1880e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1881e705c121SKalle Valo 1882e705c121SKalle Valo return ret; 1883e705c121SKalle Valo } 1884e705c121SKalle Valo 1885e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1886e705c121SKalle Valo { 1887e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1888e705c121SKalle Valo 1889e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1890e705c121SKalle Valo 1891e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1892e705c121SKalle Valo iwl_disable_interrupts(trans); 1893e705c121SKalle Valo 1894e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1895e705c121SKalle Valo 1896e705c121SKalle Valo iwl_disable_interrupts(trans); 1897e705c121SKalle Valo 1898e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1899e705c121SKalle Valo 1900e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1901e705c121SKalle Valo 19022e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1903e705c121SKalle Valo } 1904e705c121SKalle Valo 1905e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1906e705c121SKalle Valo { 1907e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1908e705c121SKalle Valo } 1909e705c121SKalle Valo 1910e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1911e705c121SKalle Valo { 1912e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1913e705c121SKalle Valo } 1914e705c121SKalle Valo 1915e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1916e705c121SKalle Valo { 1917e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1918e705c121SKalle Valo } 1919e705c121SKalle Valo 192084fb372cSSara Sharon static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 192184fb372cSSara Sharon { 19223681021fSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 192384fb372cSSara Sharon return 0x00FFFFFF; 192484fb372cSSara Sharon else 192584fb372cSSara Sharon return 0x000FFFFF; 192684fb372cSSara Sharon } 192784fb372cSSara Sharon 1928e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1929e705c121SKalle Valo { 193084fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 193184fb372cSSara Sharon 1932e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 193384fb372cSSara Sharon ((reg & mask) | (3 << 24))); 1934e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1935e705c121SKalle Valo } 1936e705c121SKalle Valo 1937e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1938e705c121SKalle Valo u32 val) 1939e705c121SKalle Valo { 194084fb372cSSara Sharon u32 mask = iwl_trans_pcie_prph_msk(trans); 194184fb372cSSara Sharon 1942e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 194384fb372cSSara Sharon ((addr & mask) | (3 << 24))); 1944e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1945e705c121SKalle Valo } 1946e705c121SKalle Valo 1947e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1948e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1949e705c121SKalle Valo { 1950e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1951e705c121SKalle Valo 19526ac57200SJohannes Berg /* free all first - we might be reconfigured for a different size */ 19536ac57200SJohannes Berg iwl_pcie_free_rbs_pool(trans); 19546ac57200SJohannes Berg 19554f4822b7SMordechay Goodstein trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 19564f4822b7SMordechay Goodstein trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 19574f4822b7SMordechay Goodstein trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 195822852fadSMordechay Goodstein trans->txqs.page_offs = trans_cfg->cb_data_offs; 195922852fadSMordechay Goodstein trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 1960227f2597SJohannes Berg trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 196122852fadSMordechay Goodstein 1962e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1963e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1964e705c121SKalle Valo else 1965e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1966e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1967e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1968e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1969e705c121SKalle Valo 19706c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 19716c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 19726c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 197380084e35SJohannes Berg trans_pcie->rx_buf_bytes = 197480084e35SJohannes Berg iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 1975cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 1976cfdc20efSJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1977cfdc20efSJohannes Berg trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 1978e705c121SKalle Valo 19798e3b79f8SMordechay Goodstein trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 1980e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 1981e705c121SKalle Valo 198239bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 198339bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 198439bdb17eSSharon Dvir 1985e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1986e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1987e705c121SKalle Valo * As this function may be called again in some corner cases don't 1988e705c121SKalle Valo * do anything if NAPI was already initialized. 1989e705c121SKalle Valo */ 1990bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1991e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1992906d4eb8SJohannes Berg 1993906d4eb8SJohannes Berg trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 1994e705c121SKalle Valo } 1995e705c121SKalle Valo 1996e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1997e705c121SKalle Valo { 1998e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 19996eb5e529SEmmanuel Grumbach int i; 2000e705c121SKalle Valo 20012e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 2002e705c121SKalle Valo 2003286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 20040cd1ad2dSMordechay Goodstein iwl_txq_gen2_tx_free(trans); 200513a3a390SSara Sharon else 2006e705c121SKalle Valo iwl_pcie_tx_free(trans); 2007e705c121SKalle Valo iwl_pcie_rx_free(trans); 2008e705c121SKalle Valo 200910a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 201010a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 201110a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 201210a54d81SLuca Coelho } 201310a54d81SLuca Coelho 20142e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 20157c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 20167c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 20177c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 20187c8d91ebSHaim Dreyfuss NULL); 20197c8d91ebSHaim Dreyfuss } 20202e5d4a8fSHaim Dreyfuss 20212e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 20222e5d4a8fSHaim Dreyfuss } else { 2023e705c121SKalle Valo iwl_pcie_free_ict(trans); 20242e5d4a8fSHaim Dreyfuss } 2025e705c121SKalle Valo 2026e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 2027e705c121SKalle Valo 202869725928SLuca Coelho if (trans_pcie->pnvm_dram.size) 202969725928SLuca Coelho dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size, 203069725928SLuca Coelho trans_pcie->pnvm_dram.block, 203169725928SLuca Coelho trans_pcie->pnvm_dram.physical); 203269725928SLuca Coelho 20339dad325fSLuca Coelho if (trans_pcie->reduce_power_dram.size) 20349dad325fSLuca Coelho dma_free_coherent(trans->dev, 20359dad325fSLuca Coelho trans_pcie->reduce_power_dram.size, 20369dad325fSLuca Coelho trans_pcie->reduce_power_dram.block, 20379dad325fSLuca Coelho trans_pcie->reduce_power_dram.physical); 20389dad325fSLuca Coelho 2039a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 2040e705c121SKalle Valo iwl_trans_free(trans); 2041e705c121SKalle Valo } 2042e705c121SKalle Valo 2043e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2044e705c121SKalle Valo { 2045e705c121SKalle Valo if (state) 2046e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 2047e705c121SKalle Valo else 2048e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 2049e705c121SKalle Valo } 2050e705c121SKalle Valo 205149564a80SLuca Coelho struct iwl_trans_pcie_removal { 205249564a80SLuca Coelho struct pci_dev *pdev; 205349564a80SLuca Coelho struct work_struct work; 2054b8133439SAvraham Stern bool rescan; 205549564a80SLuca Coelho }; 205649564a80SLuca Coelho 205749564a80SLuca Coelho static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 205849564a80SLuca Coelho { 205949564a80SLuca Coelho struct iwl_trans_pcie_removal *removal = 206049564a80SLuca Coelho container_of(wk, struct iwl_trans_pcie_removal, work); 206149564a80SLuca Coelho struct pci_dev *pdev = removal->pdev; 2062aba1e632SColin Ian King static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2063b8133439SAvraham Stern struct pci_bus *bus = pdev->bus; 206449564a80SLuca Coelho 206549564a80SLuca Coelho dev_err(&pdev->dev, "Device gone - attempting removal\n"); 206649564a80SLuca Coelho kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 206749564a80SLuca Coelho pci_lock_rescan_remove(); 206849564a80SLuca Coelho pci_dev_put(pdev); 206949564a80SLuca Coelho pci_stop_and_remove_bus_device(pdev); 2070b8133439SAvraham Stern if (removal->rescan) 2071b8133439SAvraham Stern pci_rescan_bus(bus->parent); 207249564a80SLuca Coelho pci_unlock_rescan_remove(); 207349564a80SLuca Coelho 207449564a80SLuca Coelho kfree(removal); 207549564a80SLuca Coelho module_put(THIS_MODULE); 207649564a80SLuca Coelho } 207749564a80SLuca Coelho 2078b8133439SAvraham Stern void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2079b8133439SAvraham Stern { 2080b8133439SAvraham Stern struct iwl_trans_pcie_removal *removal; 2081b8133439SAvraham Stern 2082b8133439SAvraham Stern if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2083b8133439SAvraham Stern return; 2084b8133439SAvraham Stern 2085b8133439SAvraham Stern IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2086b8133439SAvraham Stern 2087b8133439SAvraham Stern /* 2088b8133439SAvraham Stern * get a module reference to avoid doing this 2089b8133439SAvraham Stern * while unloading anyway and to avoid 2090b8133439SAvraham Stern * scheduling a work with code that's being 2091b8133439SAvraham Stern * removed. 2092b8133439SAvraham Stern */ 2093b8133439SAvraham Stern if (!try_module_get(THIS_MODULE)) { 2094b8133439SAvraham Stern IWL_ERR(trans, 2095b8133439SAvraham Stern "Module is being unloaded - abort\n"); 2096b8133439SAvraham Stern return; 2097b8133439SAvraham Stern } 2098b8133439SAvraham Stern 2099b8133439SAvraham Stern removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2100b8133439SAvraham Stern if (!removal) { 2101b8133439SAvraham Stern module_put(THIS_MODULE); 2102b8133439SAvraham Stern return; 2103b8133439SAvraham Stern } 2104b8133439SAvraham Stern /* 2105b8133439SAvraham Stern * we don't need to clear this flag, because 2106b8133439SAvraham Stern * the trans will be freed and reallocated. 2107b8133439SAvraham Stern */ 2108b8133439SAvraham Stern set_bit(STATUS_TRANS_DEAD, &trans->status); 2109b8133439SAvraham Stern 2110b8133439SAvraham Stern removal->pdev = to_pci_dev(trans->dev); 2111b8133439SAvraham Stern removal->rescan = rescan; 2112b8133439SAvraham Stern INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2113b8133439SAvraham Stern pci_dev_get(removal->pdev); 2114b8133439SAvraham Stern schedule_work(&removal->work); 2115b8133439SAvraham Stern } 2116b8133439SAvraham Stern EXPORT_SYMBOL(iwl_trans_pcie_remove); 2117b8133439SAvraham Stern 2118c544d89bSJohannes Berg /* 2119c544d89bSJohannes Berg * This version doesn't disable BHs but rather assumes they're 2120c544d89bSJohannes Berg * already disabled. 2121c544d89bSJohannes Berg */ 2122c544d89bSJohannes Berg bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2123e705c121SKalle Valo { 2124e705c121SKalle Valo int ret; 2125e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21269ce041f5SJohannes Berg u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 21279ce041f5SJohannes Berg u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 21289ce041f5SJohannes Berg CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 21299ce041f5SJohannes Berg u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2130e705c121SKalle Valo 2131c544d89bSJohannes Berg spin_lock(&trans_pcie->reg_lock); 2132e705c121SKalle Valo 2133e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2134e705c121SKalle Valo goto out; 2135e705c121SKalle Valo 21369ce041f5SJohannes Berg if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 21379ce041f5SJohannes Berg write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 21389ce041f5SJohannes Berg mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21399ce041f5SJohannes Berg poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 21409ce041f5SJohannes Berg } 21419ce041f5SJohannes Berg 2142e705c121SKalle Valo /* this bit wakes up the NIC */ 21439ce041f5SJohannes Berg __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2144286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2145e705c121SKalle Valo udelay(2); 2146e705c121SKalle Valo 2147e705c121SKalle Valo /* 2148e705c121SKalle Valo * These bits say the device is running, and should keep running for 2149e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2150e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 2151fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 2152fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 2153e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 2154e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2155e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 2156e705c121SKalle Valo * to keep device from sleeping. 2157e705c121SKalle Valo * 2158e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2159e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 2160fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 2161fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 2162fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 2163e705c121SKalle Valo * 2164e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 2165e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 2166e705c121SKalle Valo */ 21679ce041f5SJohannes Berg ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2168e705c121SKalle Valo if (unlikely(ret < 0)) { 216949564a80SLuca Coelho u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 217049564a80SLuca Coelho 2171e705c121SKalle Valo WARN_ONCE(1, 2172e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 217349564a80SLuca Coelho cntrl); 217449564a80SLuca Coelho 217549564a80SLuca Coelho iwl_trans_pcie_dump_regs(trans); 217649564a80SLuca Coelho 2177b8133439SAvraham Stern if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2178b8133439SAvraham Stern iwl_trans_pcie_remove(trans, false); 2179b8133439SAvraham Stern else 218049564a80SLuca Coelho iwl_write32(trans, CSR_RESET, 218149564a80SLuca Coelho CSR_RESET_REG_FLAG_FORCE_NMI); 218249564a80SLuca Coelho 2183c544d89bSJohannes Berg spin_unlock(&trans_pcie->reg_lock); 2184e705c121SKalle Valo return false; 2185e705c121SKalle Valo } 2186e705c121SKalle Valo 2187e705c121SKalle Valo out: 2188e705c121SKalle Valo /* 2189e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 2190e705c121SKalle Valo * track nic_access anyway. 2191e705c121SKalle Valo */ 2192e705c121SKalle Valo __release(&trans_pcie->reg_lock); 2193e705c121SKalle Valo return true; 2194e705c121SKalle Valo } 2195e705c121SKalle Valo 2196c544d89bSJohannes Berg static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2197c544d89bSJohannes Berg { 2198c544d89bSJohannes Berg bool ret; 2199c544d89bSJohannes Berg 2200c544d89bSJohannes Berg local_bh_disable(); 2201c544d89bSJohannes Berg ret = __iwl_trans_pcie_grab_nic_access(trans); 2202c544d89bSJohannes Berg if (ret) { 2203c544d89bSJohannes Berg /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2204c544d89bSJohannes Berg return ret; 2205c544d89bSJohannes Berg } 2206c544d89bSJohannes Berg local_bh_enable(); 2207c544d89bSJohannes Berg return false; 2208c544d89bSJohannes Berg } 2209c544d89bSJohannes Berg 22101ed08f6fSJohannes Berg static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2211e705c121SKalle Valo { 2212e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2213e705c121SKalle Valo 2214e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 2215e705c121SKalle Valo 2216e705c121SKalle Valo /* 2217e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 2218e705c121SKalle Valo * track nic_access anyway. 2219e705c121SKalle Valo */ 2220e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 2221e705c121SKalle Valo 2222e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2223e705c121SKalle Valo goto out; 22241b6598c3SRoee Goldfiner if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 22251b6598c3SRoee Goldfiner __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22261b6598c3SRoee Goldfiner CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 22271b6598c3SRoee Goldfiner else 2228e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 22296dece0e9SLuca Coelho CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2230e705c121SKalle Valo /* 2231e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2232e705c121SKalle Valo * any previous writes, but we need the write that clears the 2233e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2234e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2235e705c121SKalle Valo */ 2236e705c121SKalle Valo out: 2237874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2238e705c121SKalle Valo } 2239e705c121SKalle Valo 2240e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2241e705c121SKalle Valo void *buf, int dwords) 2242e705c121SKalle Valo { 224304516706SJohannes Berg int offs = 0; 2244e705c121SKalle Valo u32 *vals = buf; 2245e705c121SKalle Valo 224604516706SJohannes Berg while (offs < dwords) { 224704516706SJohannes Berg /* limit the time we spin here under lock to 1/2s */ 224867013174SJohannes Berg unsigned long end = jiffies + HZ / 2; 22493d372c4eSJohannes Berg bool resched = false; 225004516706SJohannes Berg 22511ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 225204516706SJohannes Berg iwl_write32(trans, HBUS_TARG_MEM_RADDR, 225304516706SJohannes Berg addr + 4 * offs); 225404516706SJohannes Berg 225504516706SJohannes Berg while (offs < dwords) { 225604516706SJohannes Berg vals[offs] = iwl_read32(trans, 225704516706SJohannes Berg HBUS_TARG_MEM_RDAT); 225804516706SJohannes Berg offs++; 225904516706SJohannes Berg 22603d372c4eSJohannes Berg if (time_after(jiffies, end)) { 22613d372c4eSJohannes Berg resched = true; 226204516706SJohannes Berg break; 226304516706SJohannes Berg } 22643d372c4eSJohannes Berg } 22651ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 22663d372c4eSJohannes Berg 22673d372c4eSJohannes Berg if (resched) 22683d372c4eSJohannes Berg cond_resched(); 2269e705c121SKalle Valo } else { 227004516706SJohannes Berg return -EBUSY; 2271e705c121SKalle Valo } 227204516706SJohannes Berg } 227304516706SJohannes Berg 227404516706SJohannes Berg return 0; 2275e705c121SKalle Valo } 2276e705c121SKalle Valo 2277e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2278e705c121SKalle Valo const void *buf, int dwords) 2279e705c121SKalle Valo { 2280e705c121SKalle Valo int offs, ret = 0; 2281e705c121SKalle Valo const u32 *vals = buf; 2282e705c121SKalle Valo 22831ed08f6fSJohannes Berg if (iwl_trans_grab_nic_access(trans)) { 2284e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2285e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2286e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2287e705c121SKalle Valo vals ? vals[offs] : 0); 22881ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 2289e705c121SKalle Valo } else { 2290e705c121SKalle Valo ret = -EBUSY; 2291e705c121SKalle Valo } 2292e705c121SKalle Valo return ret; 2293e705c121SKalle Valo } 2294e705c121SKalle Valo 22957f1fe1d4SLuca Coelho static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 22967f1fe1d4SLuca Coelho u32 *val) 22977f1fe1d4SLuca Coelho { 22987f1fe1d4SLuca Coelho return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 22997f1fe1d4SLuca Coelho ofs, val); 23007f1fe1d4SLuca Coelho } 23017f1fe1d4SLuca Coelho 23020cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 23030cd58eaaSEmmanuel Grumbach { 23040cd58eaaSEmmanuel Grumbach int i; 23050cd58eaaSEmmanuel Grumbach 2306286ca8ebSLuca Coelho for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 23074f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[i]; 23080cd58eaaSEmmanuel Grumbach 23094f4822b7SMordechay Goodstein if (i == trans->txqs.cmd.q_id) 23100cd58eaaSEmmanuel Grumbach continue; 23110cd58eaaSEmmanuel Grumbach 23120cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 23130cd58eaaSEmmanuel Grumbach 23140cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 23150cd58eaaSEmmanuel Grumbach txq->block--; 23160cd58eaaSEmmanuel Grumbach if (!txq->block) { 23170cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2318bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 23190cd58eaaSEmmanuel Grumbach } 23200cd58eaaSEmmanuel Grumbach } else if (block) { 23210cd58eaaSEmmanuel Grumbach txq->block++; 23220cd58eaaSEmmanuel Grumbach } 23230cd58eaaSEmmanuel Grumbach 23240cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 23250cd58eaaSEmmanuel Grumbach } 23260cd58eaaSEmmanuel Grumbach } 23270cd58eaaSEmmanuel Grumbach 2328e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2329e705c121SKalle Valo 233092536c96SSara Sharon static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 233192536c96SSara Sharon struct iwl_trans_rxq_dma_data *data) 233292536c96SSara Sharon { 233392536c96SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 233492536c96SSara Sharon 233592536c96SSara Sharon if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 233692536c96SSara Sharon return -EINVAL; 233792536c96SSara Sharon 233892536c96SSara Sharon data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 233992536c96SSara Sharon data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 234092536c96SSara Sharon data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 234192536c96SSara Sharon data->fr_bd_wid = 0; 234292536c96SSara Sharon 234392536c96SSara Sharon return 0; 234492536c96SSara Sharon } 234592536c96SSara Sharon 2346d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2347e705c121SKalle Valo { 2348e705c121SKalle Valo struct iwl_txq *txq; 2349e705c121SKalle Valo unsigned long now = jiffies; 23502ae48edcSSara Sharon bool overflow_tx; 2351e705c121SKalle Valo u8 wr_ptr; 2352e705c121SKalle Valo 23532b3fae66SMatt Chen /* Make sure the NIC is still alive in the bus */ 2354f60c9e59SEmmanuel Grumbach if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2355f60c9e59SEmmanuel Grumbach return -ENODEV; 23562b3fae66SMatt Chen 23574f4822b7SMordechay Goodstein if (!test_bit(txq_idx, trans->txqs.queue_used)) 2358d6d517b7SSara Sharon return -EINVAL; 2359e705c121SKalle Valo 2360d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 23614f4822b7SMordechay Goodstein txq = trans->txqs.txq[txq_idx]; 23622ae48edcSSara Sharon 23632ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23642ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23652ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23662ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 23672ae48edcSSara Sharon 23686aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2369e705c121SKalle Valo 23702ae48edcSSara Sharon while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 23712ae48edcSSara Sharon overflow_tx) && 2372e705c121SKalle Valo !time_after(jiffies, 2373e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 23746aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2375e705c121SKalle Valo 23762ae48edcSSara Sharon /* 23772ae48edcSSara Sharon * If write pointer moved during the wait, warn only 23782ae48edcSSara Sharon * if the TX came from op mode. In case TX came from 23792ae48edcSSara Sharon * trans layer (overflow TX) don't warn. 23802ae48edcSSara Sharon */ 23812ae48edcSSara Sharon if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2382e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2383e705c121SKalle Valo wr_ptr, write_ptr)) 2384e705c121SKalle Valo return -ETIMEDOUT; 23852ae48edcSSara Sharon wr_ptr = write_ptr; 23862ae48edcSSara Sharon 2387192185d6SJohannes Berg usleep_range(1000, 2000); 23882ae48edcSSara Sharon 23892ae48edcSSara Sharon spin_lock_bh(&txq->lock); 23902ae48edcSSara Sharon overflow_tx = txq->overflow_tx || 23912ae48edcSSara Sharon !skb_queue_empty(&txq->overflow_q); 23922ae48edcSSara Sharon spin_unlock_bh(&txq->lock); 2393e705c121SKalle Valo } 2394e705c121SKalle Valo 2395bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2396e705c121SKalle Valo IWL_ERR(trans, 2397d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 23980cd1ad2dSMordechay Goodstein iwl_txq_log_scd_error(trans, txq); 2399d6d517b7SSara Sharon return -ETIMEDOUT; 2400e705c121SKalle Valo } 2401e705c121SKalle Valo 2402d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2403d6d517b7SSara Sharon 2404d6d517b7SSara Sharon return 0; 2405d6d517b7SSara Sharon } 2406d6d517b7SSara Sharon 2407d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2408d6d517b7SSara Sharon { 2409d6d517b7SSara Sharon int cnt; 2410d6d517b7SSara Sharon int ret = 0; 2411d6d517b7SSara Sharon 2412d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 241379b6c8feSLuca Coelho for (cnt = 0; 2414286ca8ebSLuca Coelho cnt < trans->trans_cfg->base_params->num_of_queues; 241579b6c8feSLuca Coelho cnt++) { 2416d6d517b7SSara Sharon 24174f4822b7SMordechay Goodstein if (cnt == trans->txqs.cmd.q_id) 2418d6d517b7SSara Sharon continue; 24194f4822b7SMordechay Goodstein if (!test_bit(cnt, trans->txqs.queue_used)) 2420d6d517b7SSara Sharon continue; 2421d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2422d6d517b7SSara Sharon continue; 2423d6d517b7SSara Sharon 2424d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 242538398efbSSara Sharon if (ret) 2426d6d517b7SSara Sharon break; 2427d6d517b7SSara Sharon } 2428e705c121SKalle Valo 2429e705c121SKalle Valo return ret; 2430e705c121SKalle Valo } 2431e705c121SKalle Valo 2432e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2433e705c121SKalle Valo u32 mask, u32 value) 2434e705c121SKalle Valo { 2435e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2436e705c121SKalle Valo 2437874020f8SJohannes Berg spin_lock_bh(&trans_pcie->reg_lock); 2438e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2439874020f8SJohannes Berg spin_unlock_bh(&trans_pcie->reg_lock); 2440e705c121SKalle Valo } 2441e705c121SKalle Valo 2442e705c121SKalle Valo static const char *get_csr_string(int cmd) 2443e705c121SKalle Valo { 2444e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2445e705c121SKalle Valo switch (cmd) { 2446e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2447e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2448e705c121SKalle Valo IWL_CMD(CSR_INT); 2449e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2450e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2451e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2452e705c121SKalle Valo IWL_CMD(CSR_RESET); 2453e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2454e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2455e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2456e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2457e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2458e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2459e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2460e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2461e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2462e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2463e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2464e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2465e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2466e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2467e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2468e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2469e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2470e705c121SKalle Valo default: 2471e705c121SKalle Valo return "UNKNOWN"; 2472e705c121SKalle Valo } 2473e705c121SKalle Valo #undef IWL_CMD 2474e705c121SKalle Valo } 2475e705c121SKalle Valo 2476e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2477e705c121SKalle Valo { 2478e705c121SKalle Valo int i; 2479e705c121SKalle Valo static const u32 csr_tbl[] = { 2480e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2481e705c121SKalle Valo CSR_INT_COALESCING, 2482e705c121SKalle Valo CSR_INT, 2483e705c121SKalle Valo CSR_INT_MASK, 2484e705c121SKalle Valo CSR_FH_INT_STATUS, 2485e705c121SKalle Valo CSR_GPIO_IN, 2486e705c121SKalle Valo CSR_RESET, 2487e705c121SKalle Valo CSR_GP_CNTRL, 2488e705c121SKalle Valo CSR_HW_REV, 2489e705c121SKalle Valo CSR_EEPROM_REG, 2490e705c121SKalle Valo CSR_EEPROM_GP, 2491e705c121SKalle Valo CSR_OTP_GP_REG, 2492e705c121SKalle Valo CSR_GIO_REG, 2493e705c121SKalle Valo CSR_GP_UCODE_REG, 2494e705c121SKalle Valo CSR_GP_DRIVER_REG, 2495e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2496e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2497e705c121SKalle Valo CSR_LED_REG, 2498e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2499e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2500e705c121SKalle Valo CSR_ANA_PLL_CFG, 2501e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2502e705c121SKalle Valo CSR_HW_REV_WA_REG, 2503e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2504e705c121SKalle Valo }; 2505e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2506e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2507e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2508e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2509e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2510e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2511e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2512e705c121SKalle Valo } 2513e705c121SKalle Valo } 2514e705c121SKalle Valo 2515e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2516e705c121SKalle Valo /* create and remove of files */ 2517e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2518cf5d5663SGreg Kroah-Hartman debugfs_create_file(#name, mode, parent, trans, \ 2519cf5d5663SGreg Kroah-Hartman &iwl_dbgfs_##name##_ops); \ 2520e705c121SKalle Valo } while (0) 2521e705c121SKalle Valo 2522e705c121SKalle Valo /* file operation */ 2523e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2524e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2525e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2526e705c121SKalle Valo .open = simple_open, \ 2527e705c121SKalle Valo .llseek = generic_file_llseek, \ 2528e705c121SKalle Valo }; 2529e705c121SKalle Valo 2530e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2531e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2532e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2533e705c121SKalle Valo .open = simple_open, \ 2534e705c121SKalle Valo .llseek = generic_file_llseek, \ 2535e705c121SKalle Valo }; 2536e705c121SKalle Valo 2537e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2538e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2539e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2540e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2541e705c121SKalle Valo .open = simple_open, \ 2542e705c121SKalle Valo .llseek = generic_file_llseek, \ 2543e705c121SKalle Valo }; 2544e705c121SKalle Valo 2545df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv { 2546df67a1beSJohannes Berg struct iwl_trans *trans; 2547df67a1beSJohannes Berg }; 2548df67a1beSJohannes Berg 2549df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state { 2550df67a1beSJohannes Berg loff_t pos; 2551df67a1beSJohannes Berg }; 2552df67a1beSJohannes Berg 2553df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2554e705c121SKalle Valo { 2555df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2556df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state; 2557df67a1beSJohannes Berg 2558df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2559df67a1beSJohannes Berg return NULL; 2560df67a1beSJohannes Berg 2561df67a1beSJohannes Berg state = kmalloc(sizeof(*state), GFP_KERNEL); 2562df67a1beSJohannes Berg if (!state) 2563df67a1beSJohannes Berg return NULL; 2564df67a1beSJohannes Berg state->pos = *pos; 2565df67a1beSJohannes Berg return state; 2566df67a1beSJohannes Berg } 2567df67a1beSJohannes Berg 2568df67a1beSJohannes Berg static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2569df67a1beSJohannes Berg void *v, loff_t *pos) 2570df67a1beSJohannes Berg { 2571df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2572df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2573df67a1beSJohannes Berg 2574df67a1beSJohannes Berg *pos = ++state->pos; 2575df67a1beSJohannes Berg 2576df67a1beSJohannes Berg if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2577df67a1beSJohannes Berg return NULL; 2578df67a1beSJohannes Berg 2579df67a1beSJohannes Berg return state; 2580df67a1beSJohannes Berg } 2581df67a1beSJohannes Berg 2582df67a1beSJohannes Berg static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2583df67a1beSJohannes Berg { 2584df67a1beSJohannes Berg kfree(v); 2585df67a1beSJohannes Berg } 2586df67a1beSJohannes Berg 2587df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2588df67a1beSJohannes Berg { 2589df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2590df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_state *state = v; 2591df67a1beSJohannes Berg struct iwl_trans *trans = priv->trans; 25924f4822b7SMordechay Goodstein struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2593e705c121SKalle Valo 2594df67a1beSJohannes Berg seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2595df67a1beSJohannes Berg (unsigned int)state->pos, 25964f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_used), 25974f4822b7SMordechay Goodstein !!test_bit(state->pos, trans->txqs.queue_stopped)); 2598df67a1beSJohannes Berg if (txq) 2599df67a1beSJohannes Berg seq_printf(seq, 260095a9e44fSJohannes Berg "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2601df67a1beSJohannes Berg txq->read_ptr, txq->write_ptr, 260295a9e44fSJohannes Berg txq->need_update, txq->frozen, 260395a9e44fSJohannes Berg txq->n_window, txq->ampdu); 2604df67a1beSJohannes Berg else 2605df67a1beSJohannes Berg seq_puts(seq, "(unallocated)"); 2606e705c121SKalle Valo 26074f4822b7SMordechay Goodstein if (state->pos == trans->txqs.cmd.q_id) 2608df67a1beSJohannes Berg seq_puts(seq, " (HCMD)"); 2609df67a1beSJohannes Berg seq_puts(seq, "\n"); 2610e705c121SKalle Valo 2611df67a1beSJohannes Berg return 0; 2612df67a1beSJohannes Berg } 2613df67a1beSJohannes Berg 2614df67a1beSJohannes Berg static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2615df67a1beSJohannes Berg .start = iwl_dbgfs_tx_queue_seq_start, 2616df67a1beSJohannes Berg .next = iwl_dbgfs_tx_queue_seq_next, 2617df67a1beSJohannes Berg .stop = iwl_dbgfs_tx_queue_seq_stop, 2618df67a1beSJohannes Berg .show = iwl_dbgfs_tx_queue_seq_show, 2619df67a1beSJohannes Berg }; 2620df67a1beSJohannes Berg 2621df67a1beSJohannes Berg static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2622df67a1beSJohannes Berg { 2623df67a1beSJohannes Berg struct iwl_dbgfs_tx_queue_priv *priv; 2624df67a1beSJohannes Berg 2625df67a1beSJohannes Berg priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2626df67a1beSJohannes Berg sizeof(*priv)); 2627df67a1beSJohannes Berg 2628df67a1beSJohannes Berg if (!priv) 2629e705c121SKalle Valo return -ENOMEM; 2630e705c121SKalle Valo 2631df67a1beSJohannes Berg priv->trans = inode->i_private; 2632df67a1beSJohannes Berg return 0; 2633e705c121SKalle Valo } 2634e705c121SKalle Valo 2635e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2636e705c121SKalle Valo char __user *user_buf, 2637e705c121SKalle Valo size_t count, loff_t *ppos) 2638e705c121SKalle Valo { 2639e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2640e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 264178485054SSara Sharon char *buf; 264278485054SSara Sharon int pos = 0, i, ret; 2643eb3dc36eSColin Ian King size_t bufsz; 2644e705c121SKalle Valo 264578485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 264678485054SSara Sharon 264778485054SSara Sharon if (!trans_pcie->rxq) 264878485054SSara Sharon return -EAGAIN; 264978485054SSara Sharon 265078485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 265178485054SSara Sharon if (!buf) 265278485054SSara Sharon return -ENOMEM; 265378485054SSara Sharon 265478485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 265578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 265678485054SSara Sharon 265778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 265878485054SSara Sharon i); 265978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2660e705c121SKalle Valo rxq->read); 266178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2662e705c121SKalle Valo rxq->write); 266378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2664e705c121SKalle Valo rxq->write_actual); 266578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2666e705c121SKalle Valo rxq->need_update); 266778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2668e705c121SKalle Valo rxq->free_count); 2669e705c121SKalle Valo if (rxq->rb_stts) { 26700307c839SGolan Ben Ami u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 26710307c839SGolan Ben Ami rxq)); 267278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 267378485054SSara Sharon "\tclosed_rb_num: %u\n", 26740307c839SGolan Ben Ami r & 0x0FFF); 2675e705c121SKalle Valo } else { 2676e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 267778485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2678e705c121SKalle Valo } 267978485054SSara Sharon } 268078485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 268178485054SSara Sharon kfree(buf); 268278485054SSara Sharon 268378485054SSara Sharon return ret; 2684e705c121SKalle Valo } 2685e705c121SKalle Valo 2686e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2687e705c121SKalle Valo char __user *user_buf, 2688e705c121SKalle Valo size_t count, loff_t *ppos) 2689e705c121SKalle Valo { 2690e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2691e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2692e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2693e705c121SKalle Valo 2694e705c121SKalle Valo int pos = 0; 2695e705c121SKalle Valo char *buf; 2696e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2697e705c121SKalle Valo ssize_t ret; 2698e705c121SKalle Valo 2699e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2700e705c121SKalle Valo if (!buf) 2701e705c121SKalle Valo return -ENOMEM; 2702e705c121SKalle Valo 2703e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2704e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2705e705c121SKalle Valo 2706e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2707e705c121SKalle Valo isr_stats->hw); 2708e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2709e705c121SKalle Valo isr_stats->sw); 2710e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2711e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2712e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2713e705c121SKalle Valo isr_stats->err_code); 2714e705c121SKalle Valo } 2715e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2716e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2717e705c121SKalle Valo isr_stats->sch); 2718e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2719e705c121SKalle Valo isr_stats->alive); 2720e705c121SKalle Valo #endif 2721e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2722e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2723e705c121SKalle Valo 2724e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2725e705c121SKalle Valo isr_stats->ctkill); 2726e705c121SKalle Valo 2727e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2728e705c121SKalle Valo isr_stats->wakeup); 2729e705c121SKalle Valo 2730e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2731e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2732e705c121SKalle Valo 2733e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2734e705c121SKalle Valo isr_stats->tx); 2735e705c121SKalle Valo 2736e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2737e705c121SKalle Valo isr_stats->unhandled); 2738e705c121SKalle Valo 2739e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2740e705c121SKalle Valo kfree(buf); 2741e705c121SKalle Valo return ret; 2742e705c121SKalle Valo } 2743e705c121SKalle Valo 2744e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2745e705c121SKalle Valo const char __user *user_buf, 2746e705c121SKalle Valo size_t count, loff_t *ppos) 2747e705c121SKalle Valo { 2748e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2749e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2750e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2751e705c121SKalle Valo u32 reset_flag; 2752078f1131SJohannes Berg int ret; 2753e705c121SKalle Valo 2754078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2755078f1131SJohannes Berg if (ret) 2756078f1131SJohannes Berg return ret; 2757e705c121SKalle Valo if (reset_flag == 0) 2758e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2759e705c121SKalle Valo 2760e705c121SKalle Valo return count; 2761e705c121SKalle Valo } 2762e705c121SKalle Valo 2763e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2764e705c121SKalle Valo const char __user *user_buf, 2765e705c121SKalle Valo size_t count, loff_t *ppos) 2766e705c121SKalle Valo { 2767e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2768e705c121SKalle Valo 2769e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2770e705c121SKalle Valo 2771e705c121SKalle Valo return count; 2772e705c121SKalle Valo } 2773e705c121SKalle Valo 2774e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2775e705c121SKalle Valo char __user *user_buf, 2776e705c121SKalle Valo size_t count, loff_t *ppos) 2777e705c121SKalle Valo { 2778e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2779e705c121SKalle Valo char *buf = NULL; 2780e705c121SKalle Valo ssize_t ret; 2781e705c121SKalle Valo 2782e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2783e705c121SKalle Valo if (ret < 0) 2784e705c121SKalle Valo return ret; 2785e705c121SKalle Valo if (!buf) 2786e705c121SKalle Valo return -EINVAL; 2787e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2788e705c121SKalle Valo kfree(buf); 2789e705c121SKalle Valo return ret; 2790e705c121SKalle Valo } 2791e705c121SKalle Valo 2792fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2793fa4de7f7SJohannes Berg char __user *user_buf, 2794fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2795fa4de7f7SJohannes Berg { 2796fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2797fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2798fa4de7f7SJohannes Berg char buf[100]; 2799fa4de7f7SJohannes Berg int pos; 2800fa4de7f7SJohannes Berg 2801fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2802fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2803fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2804fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2805fa4de7f7SJohannes Berg 2806fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2807fa4de7f7SJohannes Berg } 2808fa4de7f7SJohannes Berg 2809fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2810fa4de7f7SJohannes Berg const char __user *user_buf, 2811fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2812fa4de7f7SJohannes Berg { 2813fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2814fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2815c5bf4fa1SJohannes Berg bool new_value; 2816fa4de7f7SJohannes Berg int ret; 2817fa4de7f7SJohannes Berg 2818c5bf4fa1SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &new_value); 2819fa4de7f7SJohannes Berg if (ret) 2820fa4de7f7SJohannes Berg return ret; 2821c5bf4fa1SJohannes Berg if (new_value == trans_pcie->debug_rfkill) 2822fa4de7f7SJohannes Berg return count; 2823fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2824c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill, new_value); 2825c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = new_value; 2826fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2827fa4de7f7SJohannes Berg 2828fa4de7f7SJohannes Berg return count; 2829fa4de7f7SJohannes Berg } 2830fa4de7f7SJohannes Berg 2831f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2832f7805b33SLior Cohen struct file *file) 2833f7805b33SLior Cohen { 2834f7805b33SLior Cohen struct iwl_trans *trans = inode->i_private; 2835f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2836f7805b33SLior Cohen 283791c28b83SShahar S Matityahu if (!trans->dbg.dest_tlv || 283891c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2839f7805b33SLior Cohen IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2840f7805b33SLior Cohen return -ENOENT; 2841f7805b33SLior Cohen } 2842f7805b33SLior Cohen 2843f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2844f7805b33SLior Cohen return -EBUSY; 2845f7805b33SLior Cohen 2846f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2847f7805b33SLior Cohen return simple_open(inode, file); 2848f7805b33SLior Cohen } 2849f7805b33SLior Cohen 2850f7805b33SLior Cohen static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2851f7805b33SLior Cohen struct file *file) 2852f7805b33SLior Cohen { 2853f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = 2854f7805b33SLior Cohen IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2855f7805b33SLior Cohen 2856f7805b33SLior Cohen if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2857f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2858f7805b33SLior Cohen return 0; 2859f7805b33SLior Cohen } 2860f7805b33SLior Cohen 2861f7805b33SLior Cohen static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2862f7805b33SLior Cohen void *buf, ssize_t *size, 2863f7805b33SLior Cohen ssize_t *bytes_copied) 2864f7805b33SLior Cohen { 286558d1b717SHyunwoo Kim ssize_t buf_size_left = count - *bytes_copied; 2866f7805b33SLior Cohen 2867f7805b33SLior Cohen buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2868f7805b33SLior Cohen if (*size > buf_size_left) 2869f7805b33SLior Cohen *size = buf_size_left; 2870f7805b33SLior Cohen 2871f7805b33SLior Cohen *size -= copy_to_user(user_buf, buf, *size); 2872f7805b33SLior Cohen *bytes_copied += *size; 2873f7805b33SLior Cohen 2874f7805b33SLior Cohen if (buf_size_left == *size) 2875f7805b33SLior Cohen return true; 2876f7805b33SLior Cohen return false; 2877f7805b33SLior Cohen } 2878f7805b33SLior Cohen 2879f7805b33SLior Cohen static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2880f7805b33SLior Cohen char __user *user_buf, 2881f7805b33SLior Cohen size_t count, loff_t *ppos) 2882f7805b33SLior Cohen { 2883f7805b33SLior Cohen struct iwl_trans *trans = file->private_data; 2884f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 28853827cb59SJohannes Berg u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2886f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 2887f7805b33SLior Cohen u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2888f7805b33SLior Cohen ssize_t size, bytes_copied = 0; 2889f7805b33SLior Cohen bool b_full; 2890f7805b33SLior Cohen 289191c28b83SShahar S Matityahu if (trans->dbg.dest_tlv) { 2892f7805b33SLior Cohen write_ptr_addr = 289391c28b83SShahar S Matityahu le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 289491c28b83SShahar S Matityahu wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2895f7805b33SLior Cohen } else { 2896f7805b33SLior Cohen write_ptr_addr = MON_BUFF_WRPTR; 2897f7805b33SLior Cohen wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2898f7805b33SLior Cohen } 2899f7805b33SLior Cohen 290091c28b83SShahar S Matityahu if (unlikely(!trans->dbg.rec_on)) 2901f7805b33SLior Cohen return 0; 2902f7805b33SLior Cohen 2903f7805b33SLior Cohen mutex_lock(&data->mutex); 2904f7805b33SLior Cohen if (data->state == 2905f7805b33SLior Cohen IWL_FW_MON_DBGFS_STATE_DISABLED) { 2906f7805b33SLior Cohen mutex_unlock(&data->mutex); 2907f7805b33SLior Cohen return 0; 2908f7805b33SLior Cohen } 2909f7805b33SLior Cohen 2910f7805b33SLior Cohen /* write_ptr position in bytes rather then DW */ 2911f7805b33SLior Cohen write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2912f7805b33SLior Cohen wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2913f7805b33SLior Cohen 2914f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt) { 2915f7805b33SLior Cohen size = write_ptr - data->prev_wr_ptr; 2916f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2917f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2918f7805b33SLior Cohen curr_buf, &size, 2919f7805b33SLior Cohen &bytes_copied); 2920f7805b33SLior Cohen data->prev_wr_ptr += size; 2921f7805b33SLior Cohen 2922f7805b33SLior Cohen } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2923f7805b33SLior Cohen write_ptr < data->prev_wr_ptr) { 292469f0e505SShahar S Matityahu size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 2925f7805b33SLior Cohen curr_buf = cpu_addr + data->prev_wr_ptr; 2926f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2927f7805b33SLior Cohen curr_buf, &size, 2928f7805b33SLior Cohen &bytes_copied); 2929f7805b33SLior Cohen data->prev_wr_ptr += size; 2930f7805b33SLior Cohen 2931f7805b33SLior Cohen if (!b_full) { 2932f7805b33SLior Cohen size = write_ptr; 2933f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2934f7805b33SLior Cohen cpu_addr, &size, 2935f7805b33SLior Cohen &bytes_copied); 2936f7805b33SLior Cohen data->prev_wr_ptr = size; 2937f7805b33SLior Cohen data->prev_wrap_cnt++; 2938f7805b33SLior Cohen } 2939f7805b33SLior Cohen } else { 2940f7805b33SLior Cohen if (data->prev_wrap_cnt == wrap_cnt - 1 && 2941f7805b33SLior Cohen write_ptr > data->prev_wr_ptr) 2942f7805b33SLior Cohen IWL_WARN(trans, 2943f7805b33SLior Cohen "write pointer passed previous write pointer, start copying from the beginning\n"); 2944f7805b33SLior Cohen else if (!unlikely(data->prev_wrap_cnt == 0 && 2945f7805b33SLior Cohen data->prev_wr_ptr == 0)) 2946f7805b33SLior Cohen IWL_WARN(trans, 2947f7805b33SLior Cohen "monitor data is out of sync, start copying from the beginning\n"); 2948f7805b33SLior Cohen 2949f7805b33SLior Cohen size = write_ptr; 2950f7805b33SLior Cohen b_full = iwl_write_to_user_buf(user_buf, count, 2951f7805b33SLior Cohen cpu_addr, &size, 2952f7805b33SLior Cohen &bytes_copied); 2953f7805b33SLior Cohen data->prev_wr_ptr = size; 2954f7805b33SLior Cohen data->prev_wrap_cnt = wrap_cnt; 2955f7805b33SLior Cohen } 2956f7805b33SLior Cohen 2957f7805b33SLior Cohen mutex_unlock(&data->mutex); 2958f7805b33SLior Cohen 2959f7805b33SLior Cohen return bytes_copied; 2960f7805b33SLior Cohen } 2961f7805b33SLior Cohen 2962aa899e68SJohannes Berg static ssize_t iwl_dbgfs_rf_read(struct file *file, 2963aa899e68SJohannes Berg char __user *user_buf, 2964aa899e68SJohannes Berg size_t count, loff_t *ppos) 2965aa899e68SJohannes Berg { 2966aa899e68SJohannes Berg struct iwl_trans *trans = file->private_data; 2967aa899e68SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2968aa899e68SJohannes Berg 2969aa899e68SJohannes Berg if (!trans_pcie->rf_name[0]) 2970aa899e68SJohannes Berg return -ENODEV; 2971aa899e68SJohannes Berg 2972aa899e68SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, 2973aa899e68SJohannes Berg trans_pcie->rf_name, 2974aa899e68SJohannes Berg strlen(trans_pcie->rf_name)); 2975aa899e68SJohannes Berg } 2976aa899e68SJohannes Berg 2977e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2978e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2979e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2980e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2981fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2982aa899e68SJohannes Berg DEBUGFS_READ_FILE_OPS(rf); 2983aa899e68SJohannes Berg 2984df67a1beSJohannes Berg static const struct file_operations iwl_dbgfs_tx_queue_ops = { 2985df67a1beSJohannes Berg .owner = THIS_MODULE, 2986df67a1beSJohannes Berg .open = iwl_dbgfs_tx_queue_open, 2987df67a1beSJohannes Berg .read = seq_read, 2988df67a1beSJohannes Berg .llseek = seq_lseek, 2989df67a1beSJohannes Berg .release = seq_release_private, 2990df67a1beSJohannes Berg }; 2991e705c121SKalle Valo 2992f7805b33SLior Cohen static const struct file_operations iwl_dbgfs_monitor_data_ops = { 2993f7805b33SLior Cohen .read = iwl_dbgfs_monitor_data_read, 2994f7805b33SLior Cohen .open = iwl_dbgfs_monitor_data_open, 2995f7805b33SLior Cohen .release = iwl_dbgfs_monitor_data_release, 2996f7805b33SLior Cohen }; 2997f7805b33SLior Cohen 2998f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2999cf5d5663SGreg Kroah-Hartman void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3000e705c121SKalle Valo { 3001f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 3002f8a1edb7SJohannes Berg 30032ef00c53SJoe Perches DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 30042ef00c53SJoe Perches DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 30052ef00c53SJoe Perches DEBUGFS_ADD_FILE(interrupt, dir, 0600); 30062ef00c53SJoe Perches DEBUGFS_ADD_FILE(csr, dir, 0200); 30072ef00c53SJoe Perches DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 30082ef00c53SJoe Perches DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3009f7805b33SLior Cohen DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3010aa899e68SJohannes Berg DEBUGFS_ADD_FILE(rf, dir, 0400); 3011e705c121SKalle Valo } 3012f7805b33SLior Cohen 3013f7805b33SLior Cohen static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3014f7805b33SLior Cohen { 3015f7805b33SLior Cohen struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3016f7805b33SLior Cohen struct cont_rec *data = &trans_pcie->fw_mon_data; 3017f7805b33SLior Cohen 3018f7805b33SLior Cohen mutex_lock(&data->mutex); 3019f7805b33SLior Cohen data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3020f7805b33SLior Cohen mutex_unlock(&data->mutex); 3021f7805b33SLior Cohen } 3022e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3023e705c121SKalle Valo 30246983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3025e705c121SKalle Valo { 3026e705c121SKalle Valo u32 cmdlen = 0; 3027e705c121SKalle Valo int i; 3028e705c121SKalle Valo 3029885375d0SMordechay Goodstein for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 30300179bfffSMordechay Goodstein cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3031e705c121SKalle Valo 3032e705c121SKalle Valo return cmdlen; 3033e705c121SKalle Valo } 3034e705c121SKalle Valo 3035e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3036e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3037e705c121SKalle Valo int allocated_rb_nums) 3038e705c121SKalle Valo { 3039e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 304080084e35SJohannes Berg int max_len = trans_pcie->rx_buf_bytes; 304178485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 304278485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3043e705c121SKalle Valo u32 i, r, j, rb_len = 0; 3044e705c121SKalle Valo 3045e705c121SKalle Valo spin_lock(&rxq->lock); 3046e705c121SKalle Valo 30470307c839SGolan Ben Ami r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3048e705c121SKalle Valo 3049e705c121SKalle Valo for (i = rxq->read, j = 0; 3050e705c121SKalle Valo i != r && j < allocated_rb_nums; 3051e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 3052e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3053e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 3054e705c121SKalle Valo 305559a6ee97SJohannes Berg dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 305659a6ee97SJohannes Berg max_len, DMA_FROM_DEVICE); 3057e705c121SKalle Valo 3058e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3059e705c121SKalle Valo 3060e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3061e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3062e705c121SKalle Valo rb = (void *)(*data)->data; 3063e705c121SKalle Valo rb->index = cpu_to_le32(i); 3064e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 3065e705c121SKalle Valo 3066e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3067e705c121SKalle Valo } 3068e705c121SKalle Valo 3069e705c121SKalle Valo spin_unlock(&rxq->lock); 3070e705c121SKalle Valo 3071e705c121SKalle Valo return rb_len; 3072e705c121SKalle Valo } 3073e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 3074e705c121SKalle Valo 3075e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3076e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3077e705c121SKalle Valo { 3078e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3079e705c121SKalle Valo __le32 *val; 3080e705c121SKalle Valo int i; 3081e705c121SKalle Valo 3082e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3083e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3084e705c121SKalle Valo val = (void *)(*data)->data; 3085e705c121SKalle Valo 3086e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3087e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3088e705c121SKalle Valo 3089e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3090e705c121SKalle Valo 3091e705c121SKalle Valo return csr_len; 3092e705c121SKalle Valo } 3093e705c121SKalle Valo 3094e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3095e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 3096e705c121SKalle Valo { 3097e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3098e705c121SKalle Valo __le32 *val; 3099e705c121SKalle Valo int i; 3100e705c121SKalle Valo 31011ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3102e705c121SKalle Valo return 0; 3103e705c121SKalle Valo 3104e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3105e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 3106e705c121SKalle Valo val = (void *)(*data)->data; 3107e705c121SKalle Valo 3108286ca8ebSLuca Coelho if (!trans->trans_cfg->gen2) 3109723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3110723b45e2SLiad Kaufman i += sizeof(u32)) 3111e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3112723b45e2SLiad Kaufman else 3113ea695b7cSShaul Triebitz for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3114ea695b7cSShaul Triebitz i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3115723b45e2SLiad Kaufman i += sizeof(u32)) 3116723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3117723b45e2SLiad Kaufman i)); 3118e705c121SKalle Valo 31191ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3120e705c121SKalle Valo 3121e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 3122e705c121SKalle Valo 3123e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 3124e705c121SKalle Valo } 3125e705c121SKalle Valo 3126e705c121SKalle Valo static u32 3127e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3128e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3129e705c121SKalle Valo u32 monitor_len) 3130e705c121SKalle Valo { 3131e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 3132e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 3133e705c121SKalle Valo u32 i; 3134e705c121SKalle Valo 31351ed08f6fSJohannes Berg if (!iwl_trans_grab_nic_access(trans)) 3136e705c121SKalle Valo return 0; 3137e705c121SKalle Valo 3138ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3139e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 3140ea695b7cSShaul Triebitz buffer[i] = iwl_read_umac_prph_no_grab(trans, 314114ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 3142ea695b7cSShaul Triebitz iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3143e705c121SKalle Valo 31441ed08f6fSJohannes Berg iwl_trans_release_nic_access(trans); 3145e705c121SKalle Valo 3146e705c121SKalle Valo return monitor_len; 3147e705c121SKalle Valo } 3148e705c121SKalle Valo 31497a14c23dSSara Sharon static void 31507a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 31517a14c23dSSara Sharon struct iwl_fw_error_dump_fw_mon *fw_mon_data) 31527a14c23dSSara Sharon { 3153c88580e1SShahar S Matityahu u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 31547a14c23dSSara Sharon 3155286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3156c88580e1SShahar S Matityahu base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3157c88580e1SShahar S Matityahu base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3158c88580e1SShahar S Matityahu write_ptr = DBGC_CUR_DBGBUF_STATUS; 3159c88580e1SShahar S Matityahu wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 316091c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 316191c28b83SShahar S Matityahu write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 316291c28b83SShahar S Matityahu wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 316391c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 31647a14c23dSSara Sharon } else { 31657a14c23dSSara Sharon base = MON_BUFF_BASE_ADDR; 31667a14c23dSSara Sharon write_ptr = MON_BUFF_WRPTR; 31677a14c23dSSara Sharon wrap_cnt = MON_BUFF_CYCLE_CNT; 31687a14c23dSSara Sharon } 3169c88580e1SShahar S Matityahu 3170c88580e1SShahar S Matityahu write_ptr_val = iwl_read_prph(trans, write_ptr); 31717a14c23dSSara Sharon fw_mon_data->fw_mon_cycle_cnt = 31727a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 31737a14c23dSSara Sharon fw_mon_data->fw_mon_base_ptr = 31747a14c23dSSara Sharon cpu_to_le32(iwl_read_prph(trans, base)); 3175286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3176c88580e1SShahar S Matityahu fw_mon_data->fw_mon_base_high_ptr = 3177c88580e1SShahar S Matityahu cpu_to_le32(iwl_read_prph(trans, base_high)); 3178c88580e1SShahar S Matityahu write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3179cc598782SRotem Saado /* convert wrtPtr to DWs, to align with all HWs */ 3180cc598782SRotem Saado write_ptr_val >>= 2; 3181c88580e1SShahar S Matityahu } 3182c88580e1SShahar S Matityahu fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 31837a14c23dSSara Sharon } 31847a14c23dSSara Sharon 3185e705c121SKalle Valo static u32 3186e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3187e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 3188e705c121SKalle Valo u32 monitor_len) 3189e705c121SKalle Valo { 319069f0e505SShahar S Matityahu struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3191e705c121SKalle Valo u32 len = 0; 3192e705c121SKalle Valo 319391c28b83SShahar S Matityahu if (trans->dbg.dest_tlv || 319469f0e505SShahar S Matityahu (fw_mon->size && 3195286ca8ebSLuca Coelho (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3196286ca8ebSLuca Coelho trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3197e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3198e705c121SKalle Valo 3199e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3200e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 32017a14c23dSSara Sharon 32027a14c23dSSara Sharon iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3203e705c121SKalle Valo 3204e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 320569f0e505SShahar S Matityahu if (fw_mon->size) { 320669f0e505SShahar S Matityahu memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 320769f0e505SShahar S Matityahu monitor_len = fw_mon->size; 320891c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 32097a14c23dSSara Sharon u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3210e705c121SKalle Valo /* 3211e705c121SKalle Valo * Update pointers to reflect actual values after 3212e705c121SKalle Valo * shifting 3213e705c121SKalle Valo */ 321491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version) { 3215fd527eb5SGolan Ben Ami base = (iwl_read_prph(trans, base) & 3216fd527eb5SGolan Ben Ami IWL_LDBG_M2S_BUF_BA_MSK) << 321791c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3218fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3219fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3220fd527eb5SGolan Ben Ami } else { 3221e705c121SKalle Valo base = iwl_read_prph(trans, base) << 322291c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3223fd527eb5SGolan Ben Ami } 3224fd527eb5SGolan Ben Ami 3225e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 3226e705c121SKalle Valo monitor_len / sizeof(u32)); 322791c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3228e705c121SKalle Valo monitor_len = 3229e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 3230e705c121SKalle Valo fw_mon_data, 3231e705c121SKalle Valo monitor_len); 3232e705c121SKalle Valo } else { 3233e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 3234e705c121SKalle Valo monitor_len = 0; 3235e705c121SKalle Valo } 3236e705c121SKalle Valo 3237e705c121SKalle Valo len += monitor_len; 3238e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3239e705c121SKalle Valo } 3240e705c121SKalle Valo 3241e705c121SKalle Valo return len; 3242e705c121SKalle Valo } 3243e705c121SKalle Valo 324493079fd5SJohannes Berg static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3245e705c121SKalle Valo { 324669f0e505SShahar S Matityahu if (trans->dbg.fw_mon.size) { 3247da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3248da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 324969f0e505SShahar S Matityahu trans->dbg.fw_mon.size; 325069f0e505SShahar S Matityahu return trans->dbg.fw_mon.size; 325191c28b83SShahar S Matityahu } else if (trans->dbg.dest_tlv) { 3252da752717SShahar S Matityahu u32 base, end, cfg_reg, monitor_len; 3253e705c121SKalle Valo 325491c28b83SShahar S Matityahu if (trans->dbg.dest_tlv->version == 1) { 325591c28b83SShahar S Matityahu cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3256fd527eb5SGolan Ben Ami cfg_reg = iwl_read_prph(trans, cfg_reg); 3257fd527eb5SGolan Ben Ami base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 325891c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3259fd527eb5SGolan Ben Ami base *= IWL_M2S_UNIT_SIZE; 3260fd527eb5SGolan Ben Ami base += trans->cfg->smem_offset; 3261fd527eb5SGolan Ben Ami 3262fd527eb5SGolan Ben Ami monitor_len = 3263fd527eb5SGolan Ben Ami (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 326491c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3265fd527eb5SGolan Ben Ami monitor_len *= IWL_M2S_UNIT_SIZE; 3266fd527eb5SGolan Ben Ami } else { 326791c28b83SShahar S Matityahu base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 326891c28b83SShahar S Matityahu end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3269e705c121SKalle Valo 3270e705c121SKalle Valo base = iwl_read_prph(trans, base) << 327191c28b83SShahar S Matityahu trans->dbg.dest_tlv->base_shift; 3272e705c121SKalle Valo end = iwl_read_prph(trans, end) << 327391c28b83SShahar S Matityahu trans->dbg.dest_tlv->end_shift; 3274e705c121SKalle Valo 3275e705c121SKalle Valo /* Make "end" point to the actual end */ 3276286ca8ebSLuca Coelho if (trans->trans_cfg->device_family >= 3277fd527eb5SGolan Ben Ami IWL_DEVICE_FAMILY_8000 || 327891c28b83SShahar S Matityahu trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 327991c28b83SShahar S Matityahu end += (1 << trans->dbg.dest_tlv->end_shift); 3280e705c121SKalle Valo monitor_len = end - base; 3281fd527eb5SGolan Ben Ami } 3282da752717SShahar S Matityahu *len += sizeof(struct iwl_fw_error_dump_data) + 3283da752717SShahar S Matityahu sizeof(struct iwl_fw_error_dump_fw_mon) + 3284e705c121SKalle Valo monitor_len; 3285da752717SShahar S Matityahu return monitor_len; 3286e705c121SKalle Valo } 3287da752717SShahar S Matityahu return 0; 3288da752717SShahar S Matityahu } 3289da752717SShahar S Matityahu 3290fdb70083SJohannes Berg static struct iwl_trans_dump_data * 3291fdb70083SJohannes Berg iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3292fdb70083SJohannes Berg u32 dump_mask, 3293fdb70083SJohannes Berg const struct iwl_dump_sanitize_ops *sanitize_ops, 3294fdb70083SJohannes Berg void *sanitize_ctx) 3295da752717SShahar S Matityahu { 3296da752717SShahar S Matityahu struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3297da752717SShahar S Matityahu struct iwl_fw_error_dump_data *data; 32984f4822b7SMordechay Goodstein struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3299da752717SShahar S Matityahu struct iwl_fw_error_dump_txcmd *txcmd; 3300da752717SShahar S Matityahu struct iwl_trans_dump_data *dump_data; 3301fefbf853SShahar S Matityahu u32 len, num_rbs = 0, monitor_len = 0; 3302da752717SShahar S Matityahu int i, ptr; 3303da752717SShahar S Matityahu bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3304286ca8ebSLuca Coelho !trans->trans_cfg->mq_rx_supported && 330579f033f6SSara Sharon dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 330679f033f6SSara Sharon 330779f033f6SSara Sharon if (!dump_mask) 330879f033f6SSara Sharon return NULL; 3309da752717SShahar S Matityahu 3310da752717SShahar S Matityahu /* transport dump header */ 3311da752717SShahar S Matityahu len = sizeof(*dump_data); 3312da752717SShahar S Matityahu 3313da752717SShahar S Matityahu /* host commands */ 3314e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3315da752717SShahar S Matityahu len += sizeof(*data) + 33168672aad3SShahar S Matityahu cmdq->n_window * (sizeof(*txcmd) + 33178672aad3SShahar S Matityahu TFD_MAX_PAYLOAD_SIZE); 3318da752717SShahar S Matityahu 3319da752717SShahar S Matityahu /* FW monitor */ 3320fefbf853SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3321da752717SShahar S Matityahu monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3322e705c121SKalle Valo 3323e705c121SKalle Valo /* CSR registers */ 332479f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3325e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 3326e705c121SKalle Valo 3327e705c121SKalle Valo /* FH registers */ 332879f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3329286ca8ebSLuca Coelho if (trans->trans_cfg->gen2) 3330723b45e2SLiad Kaufman len += sizeof(*data) + 3331ea695b7cSShaul Triebitz (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3332ea695b7cSShaul Triebitz iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3333723b45e2SLiad Kaufman else 3334723b45e2SLiad Kaufman len += sizeof(*data) + 3335520f03eaSShahar S Matityahu (FH_MEM_UPPER_BOUND - 3336520f03eaSShahar S Matityahu FH_MEM_LOWER_BOUND); 3337520f03eaSShahar S Matityahu } 3338e705c121SKalle Valo 3339e705c121SKalle Valo if (dump_rbs) { 334078485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 334178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3342e705c121SKalle Valo /* RBs */ 33430307c839SGolan Ben Ami num_rbs = 33440307c839SGolan Ben Ami le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3345e705c121SKalle Valo & 0x0FFF; 334678485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3347e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 3348e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 3349e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 3350e705c121SKalle Valo } 3351e705c121SKalle Valo 33525538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3353286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3354505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) 33555538409bSLiad Kaufman len += sizeof(*data) + 33565538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 3357505a00c0SShahar S Matityahu trans->init_dram.paging[i].size; 33585538409bSLiad Kaufman 3359e705c121SKalle Valo dump_data = vzalloc(len); 3360e705c121SKalle Valo if (!dump_data) 3361e705c121SKalle Valo return NULL; 3362e705c121SKalle Valo 3363e705c121SKalle Valo len = 0; 3364e705c121SKalle Valo data = (void *)dump_data->data; 3365520f03eaSShahar S Matityahu 3366e4eee943SShahar S Matityahu if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3367885375d0SMordechay Goodstein u16 tfd_size = trans->txqs.tfd.size; 3368520f03eaSShahar S Matityahu 3369e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3370e705c121SKalle Valo txcmd = (void *)data->data; 3371e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 3372bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 3373bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 33740cd1ad2dSMordechay Goodstein u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 337508326a97SJohannes Berg u8 tfdidx; 3376e705c121SKalle Valo u32 caplen, cmdlen; 3377e705c121SKalle Valo 337808326a97SJohannes Berg if (trans->trans_cfg->use_tfh) 337908326a97SJohannes Berg tfdidx = idx; 338008326a97SJohannes Berg else 338108326a97SJohannes Berg tfdidx = ptr; 338208326a97SJohannes Berg 3383520f03eaSShahar S Matityahu cmdlen = iwl_trans_pcie_get_cmdlen(trans, 338408326a97SJohannes Berg (u8 *)cmdq->tfds + 338508326a97SJohannes Berg tfd_size * tfdidx); 3386e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3387e705c121SKalle Valo 3388e705c121SKalle Valo if (cmdlen) { 3389e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 3390e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 3391e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 3392520f03eaSShahar S Matityahu memcpy(txcmd->data, cmdq->entries[idx].cmd, 3393520f03eaSShahar S Matityahu caplen); 3394fdb70083SJohannes Berg if (sanitize_ops && sanitize_ops->frob_hcmd) 3395fdb70083SJohannes Berg sanitize_ops->frob_hcmd(sanitize_ctx, 3396fdb70083SJohannes Berg txcmd->data, 3397fdb70083SJohannes Berg caplen); 3398e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 3399e705c121SKalle Valo } 3400e705c121SKalle Valo 34010cd1ad2dSMordechay Goodstein ptr = iwl_txq_dec_wrap(trans, ptr); 3402e705c121SKalle Valo } 3403e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 3404e705c121SKalle Valo 3405e705c121SKalle Valo data->len = cpu_to_le32(len); 3406e705c121SKalle Valo len += sizeof(*data); 3407e705c121SKalle Valo data = iwl_fw_error_next_data(data); 3408520f03eaSShahar S Matityahu } 3409e705c121SKalle Valo 341079f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3411e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 341279f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3413e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3414e705c121SKalle Valo if (dump_rbs) 3415e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3416e705c121SKalle Valo 34175538409bSLiad Kaufman /* Paged memory for gen2 HW */ 3418286ca8ebSLuca Coelho if (trans->trans_cfg->gen2 && 341979b6c8feSLuca Coelho dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3420505a00c0SShahar S Matityahu for (i = 0; i < trans->init_dram.paging_cnt; i++) { 34215538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 3422505a00c0SShahar S Matityahu u32 page_len = trans->init_dram.paging[i].size; 34235538409bSLiad Kaufman 34245538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 34255538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 34265538409bSLiad Kaufman paging = (void *)data->data; 34275538409bSLiad Kaufman paging->index = cpu_to_le32(i); 34285538409bSLiad Kaufman memcpy(paging->data, 3429505a00c0SShahar S Matityahu trans->init_dram.paging[i].block, page_len); 34305538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 34315538409bSLiad Kaufman 34325538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 34335538409bSLiad Kaufman } 34345538409bSLiad Kaufman } 343579f033f6SSara Sharon if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3436e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3437e705c121SKalle Valo 3438e705c121SKalle Valo dump_data->len = len; 3439e705c121SKalle Valo 3440e705c121SKalle Valo return dump_data; 3441e705c121SKalle Valo } 3442e705c121SKalle Valo 34433161a34dSMordechay Goodstein static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 34444cbb8e50SLuciano Coelho { 34453161a34dSMordechay Goodstein if (enable) 34463161a34dSMordechay Goodstein iwl_enable_interrupts(trans); 34473161a34dSMordechay Goodstein else 34483161a34dSMordechay Goodstein iwl_disable_interrupts(trans); 34494cbb8e50SLuciano Coelho } 34504cbb8e50SLuciano Coelho 34513161a34dSMordechay Goodstein static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 34524cbb8e50SLuciano Coelho { 34533161a34dSMordechay Goodstein u32 inta_addr, sw_err_bit; 34543161a34dSMordechay Goodstein struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 34553161a34dSMordechay Goodstein 34563161a34dSMordechay Goodstein if (trans_pcie->msix_enabled) { 34573161a34dSMordechay Goodstein inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3458571836a0SMike Golant if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3459571836a0SMike Golant sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3460571836a0SMike Golant else 34613161a34dSMordechay Goodstein sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 34623161a34dSMordechay Goodstein } else { 34633161a34dSMordechay Goodstein inta_addr = CSR_INT; 34643161a34dSMordechay Goodstein sw_err_bit = CSR_INT_BIT_SW_ERR; 34654cbb8e50SLuciano Coelho } 34663161a34dSMordechay Goodstein 34673161a34dSMordechay Goodstein iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 34683161a34dSMordechay Goodstein } 34694cbb8e50SLuciano Coelho 3470623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3471623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3472623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3473623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3474623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3475623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3476623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3477623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3478623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 34797f1fe1d4SLuca Coelho .read_config32 = iwl_trans_pcie_read_config32, \ 3480623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3481623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3482870c2a11SGolan Ben Ami .sw_reset = iwl_trans_pcie_sw_reset, \ 3483623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3484623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3485623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3486623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3487623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3488d1967ce6SShahar S Matityahu .d3_resume = iwl_trans_pcie_d3_resume, \ 34893161a34dSMordechay Goodstein .interrupts = iwl_trans_pci_interrupts, \ 3490c0941aceSMukesh Sisodiya .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3491c0941aceSMukesh Sisodiya .imr_dma_data = iwl_trans_pcie_copy_imr \ 3492623e7766SSara Sharon 3493e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3494623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3495e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3496e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3497e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3498e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3499e705c121SKalle Valo 350013f028b4SMordechay Goodstein .send_cmd = iwl_pcie_enqueue_hcmd, 3501e705c121SKalle Valo 3502e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3503a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3504e705c121SKalle Valo 3505e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3506e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3507e705c121SKalle Valo 350842db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 350942db09c1SLiad Kaufman 3510d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3511d6d517b7SSara Sharon 3512a4450980SMordechay Goodstein .freeze_txq_timer = iwl_trans_txq_freeze_timer, 35130cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3514f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3515f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3516f7805b33SLior Cohen #endif 3517623e7766SSara Sharon }; 3518e705c121SKalle Valo 3519623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3520623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3521623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3522eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3523eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 352477c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3525e705c121SKalle Valo 352613f028b4SMordechay Goodstein .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3527e705c121SKalle Valo 35280cd1ad2dSMordechay Goodstein .tx = iwl_txq_gen2_tx, 3529a4450980SMordechay Goodstein .reclaim = iwl_txq_reclaim, 3530623e7766SSara Sharon 3531a4450980SMordechay Goodstein .set_q_ptrs = iwl_txq_set_q_ptrs, 3532ba7136f3SAlex Malamud 35330cd1ad2dSMordechay Goodstein .txq_alloc = iwl_txq_dyn_alloc, 35340cd1ad2dSMordechay Goodstein .txq_free = iwl_txq_dyn_free, 3535d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 353692536c96SSara Sharon .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 35376654cd4eSLuca Coelho .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 35389dad325fSLuca Coelho .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3539f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3540f7805b33SLior Cohen .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3541f7805b33SLior Cohen #endif 3542e705c121SKalle Valo }; 3543e705c121SKalle Valo 3544e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3545e705c121SKalle Valo const struct pci_device_id *ent, 35467e8258c0SLuca Coelho const struct iwl_cfg_trans_params *cfg_trans) 3547e705c121SKalle Valo { 3548e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3549e705c121SKalle Valo struct iwl_trans *trans; 3550fda1bd0dSMordechay Goodstein int ret, addr_size; 3551a89c72ffSJohannes Berg const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3552f00c3f9eSJohannes Berg void __iomem * const *table; 3553a89c72ffSJohannes Berg 3554fda1bd0dSMordechay Goodstein if (!cfg_trans->gen2) 3555a89c72ffSJohannes Berg ops = &trans_ops_pcie; 3556e705c121SKalle Valo 35575a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 35585a41a86cSSharon Dvir if (ret) 35595a41a86cSSharon Dvir return ERR_PTR(ret); 35605a41a86cSSharon Dvir 3561a89c72ffSJohannes Berg trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3562fda1bd0dSMordechay Goodstein cfg_trans); 3563e705c121SKalle Valo if (!trans) 3564e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3565e705c121SKalle Valo 3566e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3567e705c121SKalle Valo 3568e705c121SKalle Valo trans_pcie->trans = trans; 3569326477e4SJohannes Berg trans_pcie->opmode_down = true; 3570e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3571e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3572cfdc20efSJohannes Berg spin_lock_init(&trans_pcie->alloc_page_lock); 3573e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3574e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3575906d4eb8SJohannes Berg init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3576c0941aceSMukesh Sisodiya init_waitqueue_head(&trans_pcie->imr_waitq); 35778188a18eSJohannes Berg 35788188a18eSJohannes Berg trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 35798188a18eSJohannes Berg WQ_HIGHPRI | WQ_UNBOUND, 1); 35808188a18eSJohannes Berg if (!trans_pcie->rba.alloc_wq) { 35818188a18eSJohannes Berg ret = -ENOMEM; 35828188a18eSJohannes Berg goto out_free_trans; 35838188a18eSJohannes Berg } 35848188a18eSJohannes Berg INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 35858188a18eSJohannes Berg 3586c5bf4fa1SJohannes Berg trans_pcie->debug_rfkill = -1; 3587e705c121SKalle Valo 35887e8258c0SLuca Coelho if (!cfg_trans->base_params->pcie_l1_allowed) { 3589e705c121SKalle Valo /* 3590e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3591e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3592e705c121SKalle Valo * lot of power. 3593e705c121SKalle Valo */ 3594e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3595e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3596e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3597e705c121SKalle Valo } 3598e705c121SKalle Valo 35999416560eSGolan Ben Ami trans_pcie->def_rx_queue = 0; 36009416560eSGolan Ben Ami 3601e705c121SKalle Valo pci_set_master(pdev); 3602e705c121SKalle Valo 3603885375d0SMordechay Goodstein addr_size = trans->txqs.tfd.addr_size; 3604ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3605e705c121SKalle Valo if (ret) { 3606ebe9e651SChristophe JAILLET ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3607e705c121SKalle Valo /* both attempts failed: */ 3608e705c121SKalle Valo if (ret) { 3609e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 36105a41a86cSSharon Dvir goto out_no_pci; 3611e705c121SKalle Valo } 3612e705c121SKalle Valo } 3613e705c121SKalle Valo 36145a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3615e705c121SKalle Valo if (ret) { 36165a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 36175a41a86cSSharon Dvir goto out_no_pci; 3618e705c121SKalle Valo } 3619e705c121SKalle Valo 3620f00c3f9eSJohannes Berg table = pcim_iomap_table(pdev); 3621f00c3f9eSJohannes Berg if (!table) { 36225a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3623f00c3f9eSJohannes Berg ret = -ENOMEM; 3624f00c3f9eSJohannes Berg goto out_no_pci; 3625f00c3f9eSJohannes Berg } 3626f00c3f9eSJohannes Berg 3627f00c3f9eSJohannes Berg trans_pcie->hw_base = table[0]; 3628f00c3f9eSJohannes Berg if (!trans_pcie->hw_base) { 3629f00c3f9eSJohannes Berg dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3630e705c121SKalle Valo ret = -ENODEV; 36315a41a86cSSharon Dvir goto out_no_pci; 3632e705c121SKalle Valo } 3633e705c121SKalle Valo 3634e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3635e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3636e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3637e705c121SKalle Valo 3638e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3639e705c121SKalle Valo iwl_disable_interrupts(trans); 3640e705c121SKalle Valo 3641e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 36429a098a89SRajat Jain if (trans->hw_rev == 0xffffffff) { 36439a098a89SRajat Jain dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 36449a098a89SRajat Jain ret = -EIO; 36459a098a89SRajat Jain goto out_no_pci; 36469a098a89SRajat Jain } 36479a098a89SRajat Jain 3648e705c121SKalle Valo /* 3649e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3650e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3651e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3652e705c121SKalle Valo * in the old format. 3653e705c121SKalle Valo */ 36544adfaf9bSEmmanuel Grumbach if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 365555c6d8f8SMike Golant trans->hw_rev_step = trans->hw_rev & 0xF; 365655c6d8f8SMike Golant else 365755c6d8f8SMike Golant trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3658e705c121SKalle Valo 365999be6166SLuca Coelho IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 366099be6166SLuca Coelho 36617e8258c0SLuca Coelho iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3662e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3663e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3664e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3665e705c121SKalle Valo 3666e5f3f215SHaim Dreyfuss init_waitqueue_head(&trans_pcie->sx_waitq); 3667e5f3f215SHaim Dreyfuss 3668c239feecSJohannes Berg 36692e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 36702388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 36712388bd7bSDan Carpenter if (ret) 36725a41a86cSSharon Dvir goto out_no_pci; 36732e5d4a8fSHaim Dreyfuss } else { 3674e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3675e705c121SKalle Valo if (ret) 36765a41a86cSSharon Dvir goto out_no_pci; 3677e705c121SKalle Valo 36785a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 36795a41a86cSSharon Dvir iwl_pcie_isr, 3680e705c121SKalle Valo iwl_pcie_irq_handler, 3681e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3682e705c121SKalle Valo if (ret) { 3683e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3684e705c121SKalle Valo goto out_free_ict; 3685e705c121SKalle Valo } 36862e5d4a8fSHaim Dreyfuss } 3687e705c121SKalle Valo 3688f7805b33SLior Cohen #ifdef CONFIG_IWLWIFI_DEBUGFS 3689f7805b33SLior Cohen trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3690f7805b33SLior Cohen mutex_init(&trans_pcie->fw_mon_data.mutex); 3691f7805b33SLior Cohen #endif 3692f7805b33SLior Cohen 3693a9248de4SShahar S Matityahu iwl_dbg_tlv_init(trans); 3694a9248de4SShahar S Matityahu 3695e705c121SKalle Valo return trans; 3696e705c121SKalle Valo 3697e705c121SKalle Valo out_free_ict: 3698e705c121SKalle Valo iwl_pcie_free_ict(trans); 3699e705c121SKalle Valo out_no_pci: 37008188a18eSJohannes Berg destroy_workqueue(trans_pcie->rba.alloc_wq); 37018188a18eSJohannes Berg out_free_trans: 3702e705c121SKalle Valo iwl_trans_free(trans); 3703e705c121SKalle Valo return ERR_PTR(ret); 3704e705c121SKalle Valo } 3705c0941aceSMukesh Sisodiya 3706c0941aceSMukesh Sisodiya void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3707c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3708c0941aceSMukesh Sisodiya { 3709c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_UREG_CHICK, 3710c0941aceSMukesh Sisodiya iwl_read_prph(trans, IMR_UREG_CHICK) | 3711c0941aceSMukesh Sisodiya IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3712c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3713c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3714c0941aceSMukesh Sisodiya (u32)(src_addr & 0xFFFFFFFF)); 3715c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3716c0941aceSMukesh Sisodiya iwl_get_dma_hi_addr(src_addr)); 3717c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3718c0941aceSMukesh Sisodiya iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3719c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3720c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3721c0941aceSMukesh Sisodiya IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3722c0941aceSMukesh Sisodiya } 3723c0941aceSMukesh Sisodiya 3724c0941aceSMukesh Sisodiya int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3725c0941aceSMukesh Sisodiya u32 dst_addr, u64 src_addr, u32 byte_cnt) 3726c0941aceSMukesh Sisodiya { 3727c0941aceSMukesh Sisodiya struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3728c0941aceSMukesh Sisodiya int ret = -1; 3729c0941aceSMukesh Sisodiya 3730c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_REQUESTED; 3731c0941aceSMukesh Sisodiya iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3732c0941aceSMukesh Sisodiya ret = wait_event_timeout(trans_pcie->imr_waitq, 3733c0941aceSMukesh Sisodiya trans_pcie->imr_status != 3734c0941aceSMukesh Sisodiya IMR_D2S_REQUESTED, 5 * HZ); 3735c0941aceSMukesh Sisodiya if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3736c0941aceSMukesh Sisodiya IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3737c0941aceSMukesh Sisodiya iwl_trans_pcie_dump_regs(trans); 3738c0941aceSMukesh Sisodiya return -ETIMEDOUT; 3739c0941aceSMukesh Sisodiya } 3740c0941aceSMukesh Sisodiya trans_pcie->imr_status = IMR_D2S_IDLE; 3741c0941aceSMukesh Sisodiya return 0; 3742c0941aceSMukesh Sisodiya } 3743