1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10e705c121SKalle Valo * 11e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 12e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 13e705c121SKalle Valo * published by the Free Software Foundation. 14e705c121SKalle Valo * 15e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 16e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 17e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18e705c121SKalle Valo * General Public License for more details. 19e705c121SKalle Valo * 20e705c121SKalle Valo * You should have received a copy of the GNU General Public License 21e705c121SKalle Valo * along with this program; if not, write to the Free Software 22e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 23e705c121SKalle Valo * USA 24e705c121SKalle Valo * 25e705c121SKalle Valo * The full GNU General Public License is included in this distribution 26e705c121SKalle Valo * in the file called COPYING. 27e705c121SKalle Valo * 28e705c121SKalle Valo * Contact Information: 29cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 30e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 31e705c121SKalle Valo * 32e705c121SKalle Valo * BSD LICENSE 33e705c121SKalle Valo * 34e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 35e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 36e705c121SKalle Valo * All rights reserved. 37e705c121SKalle Valo * 38e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 39e705c121SKalle Valo * modification, are permitted provided that the following conditions 40e705c121SKalle Valo * are met: 41e705c121SKalle Valo * 42e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 43e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 44e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 45e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 46e705c121SKalle Valo * the documentation and/or other materials provided with the 47e705c121SKalle Valo * distribution. 48e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 49e705c121SKalle Valo * contributors may be used to endorse or promote products derived 50e705c121SKalle Valo * from this software without specific prior written permission. 51e705c121SKalle Valo * 52e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 53e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 54e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 55e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 56e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 57e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 58e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 62e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63e705c121SKalle Valo * 64e705c121SKalle Valo *****************************************************************************/ 65e705c121SKalle Valo #include <linux/pci.h> 66e705c121SKalle Valo #include <linux/pci-aspm.h> 67e705c121SKalle Valo #include <linux/interrupt.h> 68e705c121SKalle Valo #include <linux/debugfs.h> 69e705c121SKalle Valo #include <linux/sched.h> 70e705c121SKalle Valo #include <linux/bitops.h> 71e705c121SKalle Valo #include <linux/gfp.h> 72e705c121SKalle Valo #include <linux/vmalloc.h> 73e705c121SKalle Valo 74e705c121SKalle Valo #include "iwl-drv.h" 75e705c121SKalle Valo #include "iwl-trans.h" 76e705c121SKalle Valo #include "iwl-csr.h" 77e705c121SKalle Valo #include "iwl-prph.h" 78e705c121SKalle Valo #include "iwl-scd.h" 79e705c121SKalle Valo #include "iwl-agn-hw.h" 80e705c121SKalle Valo #include "iwl-fw-error-dump.h" 81e705c121SKalle Valo #include "internal.h" 82e705c121SKalle Valo #include "iwl-fh.h" 83e705c121SKalle Valo 84e705c121SKalle Valo /* extended range in FW SRAM */ 85e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 86e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 87e705c121SKalle Valo 88e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 89e705c121SKalle Valo { 90e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 91e705c121SKalle Valo 92e705c121SKalle Valo if (!trans_pcie->fw_mon_page) 93e705c121SKalle Valo return; 94e705c121SKalle Valo 95e705c121SKalle Valo dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 96e705c121SKalle Valo trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 97e705c121SKalle Valo __free_pages(trans_pcie->fw_mon_page, 98e705c121SKalle Valo get_order(trans_pcie->fw_mon_size)); 99e705c121SKalle Valo trans_pcie->fw_mon_page = NULL; 100e705c121SKalle Valo trans_pcie->fw_mon_phys = 0; 101e705c121SKalle Valo trans_pcie->fw_mon_size = 0; 102e705c121SKalle Valo } 103e705c121SKalle Valo 104e705c121SKalle Valo static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 105e705c121SKalle Valo { 106e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 107e705c121SKalle Valo struct page *page = NULL; 108e705c121SKalle Valo dma_addr_t phys; 109e705c121SKalle Valo u32 size = 0; 110e705c121SKalle Valo u8 power; 111e705c121SKalle Valo 112e705c121SKalle Valo if (!max_power) { 113e705c121SKalle Valo /* default max_power is maximum */ 114e705c121SKalle Valo max_power = 26; 115e705c121SKalle Valo } else { 116e705c121SKalle Valo max_power += 11; 117e705c121SKalle Valo } 118e705c121SKalle Valo 119e705c121SKalle Valo if (WARN(max_power > 26, 120e705c121SKalle Valo "External buffer size for monitor is too big %d, check the FW TLV\n", 121e705c121SKalle Valo max_power)) 122e705c121SKalle Valo return; 123e705c121SKalle Valo 124e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 125e705c121SKalle Valo dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 126e705c121SKalle Valo trans_pcie->fw_mon_size, 127e705c121SKalle Valo DMA_FROM_DEVICE); 128e705c121SKalle Valo return; 129e705c121SKalle Valo } 130e705c121SKalle Valo 131e705c121SKalle Valo phys = 0; 132e705c121SKalle Valo for (power = max_power; power >= 11; power--) { 133e705c121SKalle Valo int order; 134e705c121SKalle Valo 135e705c121SKalle Valo size = BIT(power); 136e705c121SKalle Valo order = get_order(size); 137e705c121SKalle Valo page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 138e705c121SKalle Valo order); 139e705c121SKalle Valo if (!page) 140e705c121SKalle Valo continue; 141e705c121SKalle Valo 142e705c121SKalle Valo phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 143e705c121SKalle Valo DMA_FROM_DEVICE); 144e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys)) { 145e705c121SKalle Valo __free_pages(page, order); 146e705c121SKalle Valo page = NULL; 147e705c121SKalle Valo continue; 148e705c121SKalle Valo } 149e705c121SKalle Valo IWL_INFO(trans, 150e705c121SKalle Valo "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 151e705c121SKalle Valo size, order); 152e705c121SKalle Valo break; 153e705c121SKalle Valo } 154e705c121SKalle Valo 155e705c121SKalle Valo if (WARN_ON_ONCE(!page)) 156e705c121SKalle Valo return; 157e705c121SKalle Valo 158e705c121SKalle Valo if (power != max_power) 159e705c121SKalle Valo IWL_ERR(trans, 160e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 161e705c121SKalle Valo (unsigned long)BIT(power - 10), 162e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 163e705c121SKalle Valo 164e705c121SKalle Valo trans_pcie->fw_mon_page = page; 165e705c121SKalle Valo trans_pcie->fw_mon_phys = phys; 166e705c121SKalle Valo trans_pcie->fw_mon_size = size; 167e705c121SKalle Valo } 168e705c121SKalle Valo 169e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 170e705c121SKalle Valo { 171e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 172e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 173e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 174e705c121SKalle Valo } 175e705c121SKalle Valo 176e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 177e705c121SKalle Valo { 178e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 179e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 180e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 181e705c121SKalle Valo } 182e705c121SKalle Valo 183e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 184e705c121SKalle Valo { 185e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 186e705c121SKalle Valo return; 187e705c121SKalle Valo 188e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 189e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 190e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 191e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 192e705c121SKalle Valo else 193e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 194e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 195e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 196e705c121SKalle Valo } 197e705c121SKalle Valo 198e705c121SKalle Valo /* PCI registers */ 199e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 200e705c121SKalle Valo 201e705c121SKalle Valo static void iwl_pcie_apm_config(struct iwl_trans *trans) 202e705c121SKalle Valo { 203e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 204e705c121SKalle Valo u16 lctl; 205e705c121SKalle Valo u16 cap; 206e705c121SKalle Valo 207e705c121SKalle Valo /* 208e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 209e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 210e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 211e705c121SKalle Valo * costs negligible amount of power savings. 212e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 213e705c121SKalle Valo * power savings, even without L1. 214e705c121SKalle Valo */ 215e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 216e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 217e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 218e705c121SKalle Valo else 219e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 220e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 221e705c121SKalle Valo 222e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 223e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 224e705c121SKalle Valo dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 225e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 226e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 227e705c121SKalle Valo } 228e705c121SKalle Valo 229e705c121SKalle Valo /* 230e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 231e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 232e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 233e705c121SKalle Valo */ 234e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 235e705c121SKalle Valo { 236e705c121SKalle Valo int ret = 0; 237e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 238e705c121SKalle Valo 239e705c121SKalle Valo /* 240e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 241e705c121SKalle Valo * bits already set by default after reset. 242e705c121SKalle Valo */ 243e705c121SKalle Valo 244e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 245e705c121SKalle Valo if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 246e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 247e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 248e705c121SKalle Valo 249e705c121SKalle Valo /* 250e705c121SKalle Valo * Disable L0s without affecting L1; 251e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 252e705c121SKalle Valo */ 253e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 254e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 255e705c121SKalle Valo 256e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 257e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 258e705c121SKalle Valo 259e705c121SKalle Valo /* 260e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 261e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 262e705c121SKalle Valo */ 263e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 264e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 265e705c121SKalle Valo 266e705c121SKalle Valo iwl_pcie_apm_config(trans); 267e705c121SKalle Valo 268e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 269e705c121SKalle Valo if (trans->cfg->base_params->pll_cfg_val) 270e705c121SKalle Valo iwl_set_bit(trans, CSR_ANA_PLL_CFG, 271e705c121SKalle Valo trans->cfg->base_params->pll_cfg_val); 272e705c121SKalle Valo 273e705c121SKalle Valo /* 274e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 275e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 276e705c121SKalle Valo */ 277e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 278e705c121SKalle Valo 279e705c121SKalle Valo /* 280e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 281e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 282e705c121SKalle Valo * and accesses to uCode SRAM. 283e705c121SKalle Valo */ 284e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 285e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 286e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 287e705c121SKalle Valo if (ret < 0) { 288e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 289e705c121SKalle Valo goto out; 290e705c121SKalle Valo } 291e705c121SKalle Valo 292e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 293e705c121SKalle Valo /* 294e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 295e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 296e705c121SKalle Valo * not related to host_interrupt_operation_mode. 297e705c121SKalle Valo * 298e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 299e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 300e705c121SKalle Valo * that we wake up from L1 on time. 301e705c121SKalle Valo * 302e705c121SKalle Valo * This looks weird: read twice the same register, discard the 303e705c121SKalle Valo * value, set a bit, and yet again, read that same register 304e705c121SKalle Valo * just to discard the value. But that's the way the hardware 305e705c121SKalle Valo * seems to like it. 306e705c121SKalle Valo */ 307e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 308e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 309e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 310e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 311e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 312e705c121SKalle Valo } 313e705c121SKalle Valo 314e705c121SKalle Valo /* 315e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 316e705c121SKalle Valo * 317e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 318e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 319e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 320e705c121SKalle Valo */ 321e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 322e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 323e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 324e705c121SKalle Valo udelay(20); 325e705c121SKalle Valo 326e705c121SKalle Valo /* Disable L1-Active */ 327e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 328e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 329e705c121SKalle Valo 330e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 331e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 332e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 333e705c121SKalle Valo } 334e705c121SKalle Valo 335e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 336e705c121SKalle Valo 337e705c121SKalle Valo out: 338e705c121SKalle Valo return ret; 339e705c121SKalle Valo } 340e705c121SKalle Valo 341e705c121SKalle Valo /* 342e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 343e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 344e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 345e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 346e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 347e705c121SKalle Valo */ 348e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 349e705c121SKalle Valo { 350e705c121SKalle Valo int ret; 351e705c121SKalle Valo u32 apmg_gp1_reg; 352e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 353e705c121SKalle Valo u32 dl_cfg_reg; 354e705c121SKalle Valo 355e705c121SKalle Valo /* Force XTAL ON */ 356e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 357e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 358e705c121SKalle Valo 359e705c121SKalle Valo /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 360e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 361e705c121SKalle Valo 362e705c121SKalle Valo udelay(10); 363e705c121SKalle Valo 364e705c121SKalle Valo /* 365e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 366e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 367e705c121SKalle Valo */ 368e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 369e705c121SKalle Valo 370e705c121SKalle Valo /* 371e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 372e705c121SKalle Valo * device-internal resources is possible. 373e705c121SKalle Valo */ 374e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 375e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 376e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377e705c121SKalle Valo 25000); 378e705c121SKalle Valo if (WARN_ON(ret < 0)) { 379e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 380e705c121SKalle Valo /* Release XTAL ON request */ 381e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 382e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 383e705c121SKalle Valo return; 384e705c121SKalle Valo } 385e705c121SKalle Valo 386e705c121SKalle Valo /* 387e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 388e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 389e705c121SKalle Valo */ 390e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 391e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 392e705c121SKalle Valo 393e705c121SKalle Valo /* 394e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 395e705c121SKalle Valo * caused by APMG idle state. 396e705c121SKalle Valo */ 397e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 398e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 399e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 400e705c121SKalle Valo apmg_xtal_cfg_reg | 401e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 402e705c121SKalle Valo 403e705c121SKalle Valo /* 404e705c121SKalle Valo * Reset entire device again - do controller reset (results in 405e705c121SKalle Valo * SHRD_HW_RST). Turn MAC off before proceeding. 406e705c121SKalle Valo */ 407e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 408e705c121SKalle Valo 409e705c121SKalle Valo udelay(10); 410e705c121SKalle Valo 411e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 412e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 413e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 414e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 415e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 416e705c121SKalle Valo 417e705c121SKalle Valo /* Clear delay line clock power up */ 418e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 419e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 420e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 421e705c121SKalle Valo 422e705c121SKalle Valo /* 423e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 424e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 425e705c121SKalle Valo */ 426e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 427e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 428e705c121SKalle Valo 429e705c121SKalle Valo /* 430e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 431e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 432e705c121SKalle Valo */ 433e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 434e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 435e705c121SKalle Valo 436e705c121SKalle Valo /* Activates XTAL resources monitor */ 437e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 438e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 439e705c121SKalle Valo 440e705c121SKalle Valo /* Release XTAL ON request */ 441e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 442e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 443e705c121SKalle Valo udelay(10); 444e705c121SKalle Valo 445e705c121SKalle Valo /* Release APMG XTAL */ 446e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 447e705c121SKalle Valo apmg_xtal_cfg_reg & 448e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 449e705c121SKalle Valo } 450e705c121SKalle Valo 451e705c121SKalle Valo static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 452e705c121SKalle Valo { 453e705c121SKalle Valo int ret = 0; 454e705c121SKalle Valo 455e705c121SKalle Valo /* stop device's busmaster DMA activity */ 456e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 457e705c121SKalle Valo 458e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_RESET, 459e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 460e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 461e705c121SKalle Valo if (ret < 0) 462e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 463e705c121SKalle Valo 464e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 465e705c121SKalle Valo 466e705c121SKalle Valo return ret; 467e705c121SKalle Valo } 468e705c121SKalle Valo 469e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 470e705c121SKalle Valo { 471e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 472e705c121SKalle Valo 473e705c121SKalle Valo if (op_mode_leave) { 474e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 475e705c121SKalle Valo iwl_pcie_apm_init(trans); 476e705c121SKalle Valo 477e705c121SKalle Valo /* inform ME that we are leaving */ 478e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 479e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 480e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 481e705c121SKalle Valo else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 482e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 483e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 484e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 485e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 486e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 487e705c121SKalle Valo mdelay(1); 488e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 489e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 490e705c121SKalle Valo } 491e705c121SKalle Valo mdelay(5); 492e705c121SKalle Valo } 493e705c121SKalle Valo 494e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 495e705c121SKalle Valo 496e705c121SKalle Valo /* Stop device's DMA activity */ 497e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 498e705c121SKalle Valo 499e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 500e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 501e705c121SKalle Valo return; 502e705c121SKalle Valo } 503e705c121SKalle Valo 504e705c121SKalle Valo /* Reset the entire device */ 505e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 506e705c121SKalle Valo 507e705c121SKalle Valo udelay(10); 508e705c121SKalle Valo 509e705c121SKalle Valo /* 510e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 511e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 512e705c121SKalle Valo */ 513e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 514e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 515e705c121SKalle Valo } 516e705c121SKalle Valo 517e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 518e705c121SKalle Valo { 519e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 520e705c121SKalle Valo 521e705c121SKalle Valo /* nic_init */ 522e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 523e705c121SKalle Valo iwl_pcie_apm_init(trans); 524e705c121SKalle Valo 525e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 526e705c121SKalle Valo 527e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 528e705c121SKalle Valo 529e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 530e705c121SKalle Valo 531e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 532e705c121SKalle Valo iwl_pcie_rx_init(trans); 533e705c121SKalle Valo 534e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 535e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 536e705c121SKalle Valo return -ENOMEM; 537e705c121SKalle Valo 538e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 539e705c121SKalle Valo /* enable shadow regs in HW */ 540e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 541e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 542e705c121SKalle Valo } 543e705c121SKalle Valo 544e705c121SKalle Valo return 0; 545e705c121SKalle Valo } 546e705c121SKalle Valo 547e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 548e705c121SKalle Valo 549e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 550e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 551e705c121SKalle Valo { 552e705c121SKalle Valo int ret; 553e705c121SKalle Valo 554e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 555e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 556e705c121SKalle Valo 557e705c121SKalle Valo /* See if we got it */ 558e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 559e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 560e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 561e705c121SKalle Valo HW_READY_TIMEOUT); 562e705c121SKalle Valo 563e705c121SKalle Valo if (ret >= 0) 564e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 565e705c121SKalle Valo 566e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 567e705c121SKalle Valo return ret; 568e705c121SKalle Valo } 569e705c121SKalle Valo 570e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 571e705c121SKalle Valo static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 572e705c121SKalle Valo { 573e705c121SKalle Valo int ret; 574e705c121SKalle Valo int t = 0; 575e705c121SKalle Valo int iter; 576e705c121SKalle Valo 577e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 578e705c121SKalle Valo 579e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 580e705c121SKalle Valo /* If the card is ready, exit 0 */ 581e705c121SKalle Valo if (ret >= 0) 582e705c121SKalle Valo return 0; 583e705c121SKalle Valo 584e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 585e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 586e705c121SKalle Valo msleep(1); 587e705c121SKalle Valo 588e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 589e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 590e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 591e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 592e705c121SKalle Valo 593e705c121SKalle Valo do { 594e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 595e705c121SKalle Valo if (ret >= 0) 596e705c121SKalle Valo return 0; 597e705c121SKalle Valo 598e705c121SKalle Valo usleep_range(200, 1000); 599e705c121SKalle Valo t += 200; 600e705c121SKalle Valo } while (t < 150000); 601e705c121SKalle Valo msleep(25); 602e705c121SKalle Valo } 603e705c121SKalle Valo 604e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 605e705c121SKalle Valo 606e705c121SKalle Valo return ret; 607e705c121SKalle Valo } 608e705c121SKalle Valo 609e705c121SKalle Valo /* 610e705c121SKalle Valo * ucode 611e705c121SKalle Valo */ 612e705c121SKalle Valo static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, 613e705c121SKalle Valo dma_addr_t phy_addr, u32 byte_cnt) 614e705c121SKalle Valo { 615e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 616e705c121SKalle Valo int ret; 617e705c121SKalle Valo 618e705c121SKalle Valo trans_pcie->ucode_write_complete = false; 619e705c121SKalle Valo 620e705c121SKalle Valo iwl_write_direct32(trans, 621e705c121SKalle Valo FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 622e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 623e705c121SKalle Valo 624e705c121SKalle Valo iwl_write_direct32(trans, 625e705c121SKalle Valo FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 626e705c121SKalle Valo dst_addr); 627e705c121SKalle Valo 628e705c121SKalle Valo iwl_write_direct32(trans, 629e705c121SKalle Valo FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 630e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 631e705c121SKalle Valo 632e705c121SKalle Valo iwl_write_direct32(trans, 633e705c121SKalle Valo FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 634e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 635e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 636e705c121SKalle Valo 637e705c121SKalle Valo iwl_write_direct32(trans, 638e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 639e705c121SKalle Valo 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 640e705c121SKalle Valo 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 641e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 642e705c121SKalle Valo 643e705c121SKalle Valo iwl_write_direct32(trans, 644e705c121SKalle Valo FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 645e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 646e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 647e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 648e705c121SKalle Valo 649e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 650e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 651e705c121SKalle Valo if (!ret) { 652e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 653e705c121SKalle Valo return -ETIMEDOUT; 654e705c121SKalle Valo } 655e705c121SKalle Valo 656e705c121SKalle Valo return 0; 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 660e705c121SKalle Valo const struct fw_desc *section) 661e705c121SKalle Valo { 662e705c121SKalle Valo u8 *v_addr; 663e705c121SKalle Valo dma_addr_t p_addr; 664e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 665e705c121SKalle Valo int ret = 0; 666e705c121SKalle Valo 667e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 668e705c121SKalle Valo section_num); 669e705c121SKalle Valo 670e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 671e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 672e705c121SKalle Valo if (!v_addr) { 673e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 674e705c121SKalle Valo chunk_sz = PAGE_SIZE; 675e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 676e705c121SKalle Valo &p_addr, GFP_KERNEL); 677e705c121SKalle Valo if (!v_addr) 678e705c121SKalle Valo return -ENOMEM; 679e705c121SKalle Valo } 680e705c121SKalle Valo 681e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 682e705c121SKalle Valo u32 copy_size, dst_addr; 683e705c121SKalle Valo bool extended_addr = false; 684e705c121SKalle Valo 685e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 686e705c121SKalle Valo dst_addr = section->offset + offset; 687e705c121SKalle Valo 688e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 689e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 690e705c121SKalle Valo extended_addr = true; 691e705c121SKalle Valo 692e705c121SKalle Valo if (extended_addr) 693e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 694e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 695e705c121SKalle Valo 696e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 697e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 698e705c121SKalle Valo copy_size); 699e705c121SKalle Valo 700e705c121SKalle Valo if (extended_addr) 701e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 702e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 703e705c121SKalle Valo 704e705c121SKalle Valo if (ret) { 705e705c121SKalle Valo IWL_ERR(trans, 706e705c121SKalle Valo "Could not load the [%d] uCode section\n", 707e705c121SKalle Valo section_num); 708e705c121SKalle Valo break; 709e705c121SKalle Valo } 710e705c121SKalle Valo } 711e705c121SKalle Valo 712e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 713e705c121SKalle Valo return ret; 714e705c121SKalle Valo } 715e705c121SKalle Valo 716e705c121SKalle Valo /* 717e705c121SKalle Valo * Driver Takes the ownership on secure machine before FW load 718e705c121SKalle Valo * and prevent race with the BT load. 719e705c121SKalle Valo * W/A for ROM bug. (should be remove in the next Si step) 720e705c121SKalle Valo */ 721e705c121SKalle Valo static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 722e705c121SKalle Valo { 723e705c121SKalle Valo u32 val, loop = 1000; 724e705c121SKalle Valo 725e705c121SKalle Valo /* 726e705c121SKalle Valo * Check the RSA semaphore is accessible. 727e705c121SKalle Valo * If the HW isn't locked and the rsa semaphore isn't accessible, 728e705c121SKalle Valo * we are in trouble. 729e705c121SKalle Valo */ 730e705c121SKalle Valo val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 731e705c121SKalle Valo if (val & (BIT(1) | BIT(17))) { 732e705c121SKalle Valo IWL_INFO(trans, 733e705c121SKalle Valo "can't access the RSA semaphore it is write protected\n"); 734e705c121SKalle Valo return 0; 735e705c121SKalle Valo } 736e705c121SKalle Valo 737e705c121SKalle Valo /* take ownership on the AUX IF */ 738e705c121SKalle Valo iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 739e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 740e705c121SKalle Valo 741e705c121SKalle Valo do { 742e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 743e705c121SKalle Valo val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 744e705c121SKalle Valo if (val == 0x1) { 745e705c121SKalle Valo iwl_write_prph(trans, RSA_ENABLE, 0); 746e705c121SKalle Valo return 0; 747e705c121SKalle Valo } 748e705c121SKalle Valo 749e705c121SKalle Valo udelay(10); 750e705c121SKalle Valo loop--; 751e705c121SKalle Valo } while (loop > 0); 752e705c121SKalle Valo 753e705c121SKalle Valo IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 754e705c121SKalle Valo return -EIO; 755e705c121SKalle Valo } 756e705c121SKalle Valo 757e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 758e705c121SKalle Valo const struct fw_img *image, 759e705c121SKalle Valo int cpu, 760e705c121SKalle Valo int *first_ucode_section) 761e705c121SKalle Valo { 762e705c121SKalle Valo int shift_param; 763e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 764e705c121SKalle Valo u32 val, last_read_idx = 0; 765e705c121SKalle Valo 766e705c121SKalle Valo if (cpu == 1) { 767e705c121SKalle Valo shift_param = 0; 768e705c121SKalle Valo *first_ucode_section = 0; 769e705c121SKalle Valo } else { 770e705c121SKalle Valo shift_param = 16; 771e705c121SKalle Valo (*first_ucode_section)++; 772e705c121SKalle Valo } 773e705c121SKalle Valo 774e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 775e705c121SKalle Valo last_read_idx = i; 776e705c121SKalle Valo 777e705c121SKalle Valo /* 778e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 779e705c121SKalle Valo * CPU1 to CPU2. 780e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 781e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 782e705c121SKalle Valo */ 783e705c121SKalle Valo if (!image->sec[i].data || 784e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 785e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 786e705c121SKalle Valo IWL_DEBUG_FW(trans, 787e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 788e705c121SKalle Valo i); 789e705c121SKalle Valo break; 790e705c121SKalle Valo } 791e705c121SKalle Valo 792e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 793e705c121SKalle Valo if (ret) 794e705c121SKalle Valo return ret; 795e705c121SKalle Valo 796e705c121SKalle Valo /* Notify the ucode of the loaded section number and status */ 797e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 798e705c121SKalle Valo val = val | (sec_num << shift_param); 799e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 800e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 801e705c121SKalle Valo } 802e705c121SKalle Valo 803e705c121SKalle Valo *first_ucode_section = last_read_idx; 804e705c121SKalle Valo 805e705c121SKalle Valo if (cpu == 1) 806e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); 807e705c121SKalle Valo else 808e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 809e705c121SKalle Valo 810e705c121SKalle Valo return 0; 811e705c121SKalle Valo } 812e705c121SKalle Valo 813e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 814e705c121SKalle Valo const struct fw_img *image, 815e705c121SKalle Valo int cpu, 816e705c121SKalle Valo int *first_ucode_section) 817e705c121SKalle Valo { 818e705c121SKalle Valo int shift_param; 819e705c121SKalle Valo int i, ret = 0; 820e705c121SKalle Valo u32 last_read_idx = 0; 821e705c121SKalle Valo 822e705c121SKalle Valo if (cpu == 1) { 823e705c121SKalle Valo shift_param = 0; 824e705c121SKalle Valo *first_ucode_section = 0; 825e705c121SKalle Valo } else { 826e705c121SKalle Valo shift_param = 16; 827e705c121SKalle Valo (*first_ucode_section)++; 828e705c121SKalle Valo } 829e705c121SKalle Valo 830e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 831e705c121SKalle Valo last_read_idx = i; 832e705c121SKalle Valo 833e705c121SKalle Valo /* 834e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 835e705c121SKalle Valo * CPU1 to CPU2. 836e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 837e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 838e705c121SKalle Valo */ 839e705c121SKalle Valo if (!image->sec[i].data || 840e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 841e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 842e705c121SKalle Valo IWL_DEBUG_FW(trans, 843e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 844e705c121SKalle Valo i); 845e705c121SKalle Valo break; 846e705c121SKalle Valo } 847e705c121SKalle Valo 848e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 849e705c121SKalle Valo if (ret) 850e705c121SKalle Valo return ret; 851e705c121SKalle Valo } 852e705c121SKalle Valo 853e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 854e705c121SKalle Valo iwl_set_bits_prph(trans, 855e705c121SKalle Valo CSR_UCODE_LOAD_STATUS_ADDR, 856e705c121SKalle Valo (LMPM_CPU_UCODE_LOADING_COMPLETED | 857e705c121SKalle Valo LMPM_CPU_HDRS_LOADING_COMPLETED | 858e705c121SKalle Valo LMPM_CPU_UCODE_LOADING_STARTED) << 859e705c121SKalle Valo shift_param); 860e705c121SKalle Valo 861e705c121SKalle Valo *first_ucode_section = last_read_idx; 862e705c121SKalle Valo 863e705c121SKalle Valo return 0; 864e705c121SKalle Valo } 865e705c121SKalle Valo 866e705c121SKalle Valo static void iwl_pcie_apply_destination(struct iwl_trans *trans) 867e705c121SKalle Valo { 868e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 869e705c121SKalle Valo const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 870e705c121SKalle Valo int i; 871e705c121SKalle Valo 872e705c121SKalle Valo if (dest->version) 873e705c121SKalle Valo IWL_ERR(trans, 874e705c121SKalle Valo "DBG DEST version is %d - expect issues\n", 875e705c121SKalle Valo dest->version); 876e705c121SKalle Valo 877e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 878e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 879e705c121SKalle Valo 880e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 881e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 882e705c121SKalle Valo else 883e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 884e705c121SKalle Valo 885e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 886e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 887e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 888e705c121SKalle Valo 889e705c121SKalle Valo switch (dest->reg_ops[i].op) { 890e705c121SKalle Valo case CSR_ASSIGN: 891e705c121SKalle Valo iwl_write32(trans, addr, val); 892e705c121SKalle Valo break; 893e705c121SKalle Valo case CSR_SETBIT: 894e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 895e705c121SKalle Valo break; 896e705c121SKalle Valo case CSR_CLEARBIT: 897e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 898e705c121SKalle Valo break; 899e705c121SKalle Valo case PRPH_ASSIGN: 900e705c121SKalle Valo iwl_write_prph(trans, addr, val); 901e705c121SKalle Valo break; 902e705c121SKalle Valo case PRPH_SETBIT: 903e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 904e705c121SKalle Valo break; 905e705c121SKalle Valo case PRPH_CLEARBIT: 906e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 907e705c121SKalle Valo break; 908e705c121SKalle Valo case PRPH_BLOCKBIT: 909e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 910e705c121SKalle Valo IWL_ERR(trans, 911e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 912e705c121SKalle Valo val, addr); 913e705c121SKalle Valo goto monitor; 914e705c121SKalle Valo } 915e705c121SKalle Valo break; 916e705c121SKalle Valo default: 917e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 918e705c121SKalle Valo dest->reg_ops[i].op); 919e705c121SKalle Valo break; 920e705c121SKalle Valo } 921e705c121SKalle Valo } 922e705c121SKalle Valo 923e705c121SKalle Valo monitor: 924e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 925e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 926e705c121SKalle Valo trans_pcie->fw_mon_phys >> dest->base_shift); 927e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 928e705c121SKalle Valo (trans_pcie->fw_mon_phys + 929e705c121SKalle Valo trans_pcie->fw_mon_size) >> dest->end_shift); 930e705c121SKalle Valo } 931e705c121SKalle Valo } 932e705c121SKalle Valo 933e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 934e705c121SKalle Valo const struct fw_img *image) 935e705c121SKalle Valo { 936e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 937e705c121SKalle Valo int ret = 0; 938e705c121SKalle Valo int first_ucode_section; 939e705c121SKalle Valo 940e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 941e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 942e705c121SKalle Valo 943e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 944e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 945e705c121SKalle Valo if (ret) 946e705c121SKalle Valo return ret; 947e705c121SKalle Valo 948e705c121SKalle Valo if (image->is_dual_cpus) { 949e705c121SKalle Valo /* set CPU2 header address */ 950e705c121SKalle Valo iwl_write_prph(trans, 951e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 952e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 953e705c121SKalle Valo 954e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 955e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 956e705c121SKalle Valo &first_ucode_section); 957e705c121SKalle Valo if (ret) 958e705c121SKalle Valo return ret; 959e705c121SKalle Valo } 960e705c121SKalle Valo 961e705c121SKalle Valo /* supported for 7000 only for the moment */ 962e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 963e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 964e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 965e705c121SKalle Valo 966e705c121SKalle Valo if (trans_pcie->fw_mon_size) { 967e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 968e705c121SKalle Valo trans_pcie->fw_mon_phys >> 4); 969e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 970e705c121SKalle Valo (trans_pcie->fw_mon_phys + 971e705c121SKalle Valo trans_pcie->fw_mon_size) >> 4); 972e705c121SKalle Valo } 973e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 974e705c121SKalle Valo iwl_pcie_apply_destination(trans); 975e705c121SKalle Valo } 976e705c121SKalle Valo 977e705c121SKalle Valo /* release CPU reset */ 978e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 979e705c121SKalle Valo 980e705c121SKalle Valo return 0; 981e705c121SKalle Valo } 982e705c121SKalle Valo 983e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 984e705c121SKalle Valo const struct fw_img *image) 985e705c121SKalle Valo { 986e705c121SKalle Valo int ret = 0; 987e705c121SKalle Valo int first_ucode_section; 988e705c121SKalle Valo 989e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 990e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 991e705c121SKalle Valo 992e705c121SKalle Valo if (trans->dbg_dest_tlv) 993e705c121SKalle Valo iwl_pcie_apply_destination(trans); 994e705c121SKalle Valo 995e705c121SKalle Valo /* TODO: remove in the next Si step */ 996e705c121SKalle Valo ret = iwl_pcie_rsa_race_bug_wa(trans); 997e705c121SKalle Valo if (ret) 998e705c121SKalle Valo return ret; 999e705c121SKalle Valo 1000e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1001e705c121SKalle Valo /* release CPU reset */ 1002e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1003e705c121SKalle Valo 1004e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1005e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1006e705c121SKalle Valo &first_ucode_section); 1007e705c121SKalle Valo if (ret) 1008e705c121SKalle Valo return ret; 1009e705c121SKalle Valo 1010e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1011e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1012e705c121SKalle Valo &first_ucode_section); 1013e705c121SKalle Valo } 1014e705c121SKalle Valo 1015e705c121SKalle Valo static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1016e705c121SKalle Valo const struct fw_img *fw, bool run_in_rfkill) 1017e705c121SKalle Valo { 1018e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1019e705c121SKalle Valo bool hw_rfkill; 1020e705c121SKalle Valo int ret; 1021e705c121SKalle Valo 1022e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1023e705c121SKalle Valo 1024e705c121SKalle Valo /* Someone called stop_device, don't try to start_fw */ 1025e705c121SKalle Valo if (trans_pcie->is_down) { 1026e705c121SKalle Valo IWL_WARN(trans, 1027e705c121SKalle Valo "Can't start_fw since the HW hasn't been started\n"); 1028e705c121SKalle Valo ret = EIO; 1029e705c121SKalle Valo goto out; 1030e705c121SKalle Valo } 1031e705c121SKalle Valo 1032e705c121SKalle Valo /* This may fail if AMT took ownership of the device */ 1033e705c121SKalle Valo if (iwl_pcie_prepare_card_hw(trans)) { 1034e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 1035e705c121SKalle Valo ret = -EIO; 1036e705c121SKalle Valo goto out; 1037e705c121SKalle Valo } 1038e705c121SKalle Valo 1039e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1040e705c121SKalle Valo 1041e705c121SKalle Valo /* If platform's RF_KILL switch is NOT set to KILL */ 1042e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1043e705c121SKalle Valo if (hw_rfkill) 1044e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1045e705c121SKalle Valo else 1046e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1047e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1048e705c121SKalle Valo if (hw_rfkill && !run_in_rfkill) { 1049e705c121SKalle Valo ret = -ERFKILL; 1050e705c121SKalle Valo goto out; 1051e705c121SKalle Valo } 1052e705c121SKalle Valo 1053e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1054e705c121SKalle Valo 1055e705c121SKalle Valo ret = iwl_pcie_nic_init(trans); 1056e705c121SKalle Valo if (ret) { 1057e705c121SKalle Valo IWL_ERR(trans, "Unable to init nic\n"); 1058e705c121SKalle Valo goto out; 1059e705c121SKalle Valo } 1060e705c121SKalle Valo 1061e705c121SKalle Valo /* make sure rfkill handshake bits are cleared */ 1062e705c121SKalle Valo iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1063e705c121SKalle Valo iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1064e705c121SKalle Valo CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1065e705c121SKalle Valo 1066e705c121SKalle Valo /* clear (again), then enable host interrupts */ 1067e705c121SKalle Valo iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1068e705c121SKalle Valo iwl_enable_interrupts(trans); 1069e705c121SKalle Valo 1070e705c121SKalle Valo /* really make sure rfkill handshake bits are cleared */ 1071e705c121SKalle Valo iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1072e705c121SKalle Valo iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1073e705c121SKalle Valo 1074e705c121SKalle Valo /* Load the given image to the HW */ 1075e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1076e705c121SKalle Valo ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1077e705c121SKalle Valo else 1078e705c121SKalle Valo ret = iwl_pcie_load_given_ucode(trans, fw); 1079e705c121SKalle Valo 1080e705c121SKalle Valo out: 1081e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1082e705c121SKalle Valo return ret; 1083e705c121SKalle Valo } 1084e705c121SKalle Valo 1085e705c121SKalle Valo static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1086e705c121SKalle Valo { 1087e705c121SKalle Valo iwl_pcie_reset_ict(trans); 1088e705c121SKalle Valo iwl_pcie_tx_start(trans, scd_addr); 1089e705c121SKalle Valo } 1090e705c121SKalle Valo 1091e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1092e705c121SKalle Valo { 1093e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1094e705c121SKalle Valo bool hw_rfkill, was_hw_rfkill; 1095e705c121SKalle Valo 1096e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1097e705c121SKalle Valo 1098e705c121SKalle Valo if (trans_pcie->is_down) 1099e705c121SKalle Valo return; 1100e705c121SKalle Valo 1101e705c121SKalle Valo trans_pcie->is_down = true; 1102e705c121SKalle Valo 1103e705c121SKalle Valo was_hw_rfkill = iwl_is_rfkill_set(trans); 1104e705c121SKalle Valo 1105e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1106e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1107e705c121SKalle Valo iwl_disable_interrupts(trans); 1108e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1109e705c121SKalle Valo 1110e705c121SKalle Valo /* device going down, Stop using ICT table */ 1111e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1112e705c121SKalle Valo 1113e705c121SKalle Valo /* 1114e705c121SKalle Valo * If a HW restart happens during firmware loading, 1115e705c121SKalle Valo * then the firmware loading might call this function 1116e705c121SKalle Valo * and later it might be called again due to the 1117e705c121SKalle Valo * restart. So don't process again if the device is 1118e705c121SKalle Valo * already dead. 1119e705c121SKalle Valo */ 1120e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1121e705c121SKalle Valo IWL_DEBUG_INFO(trans, "DEVICE_ENABLED bit was set and is now cleared\n"); 1122e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1123e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1124e705c121SKalle Valo 1125e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1126e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1127e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1128e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1129e705c121SKalle Valo udelay(5); 1130e705c121SKalle Valo } 1131e705c121SKalle Valo } 1132e705c121SKalle Valo 1133e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1134e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1135e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1136e705c121SKalle Valo 1137e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1138e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1139e705c121SKalle Valo 1140e705c121SKalle Valo /* stop and reset the on-board processor */ 1141e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1142e705c121SKalle Valo udelay(20); 1143e705c121SKalle Valo 1144e705c121SKalle Valo /* 1145e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1146e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1147e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1148e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1149e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1150e705c121SKalle Valo */ 1151e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1152e705c121SKalle Valo iwl_disable_interrupts(trans); 1153e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1154e705c121SKalle Valo 1155e705c121SKalle Valo 1156e705c121SKalle Valo /* clear all status bits */ 1157e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1158e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1159e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1160e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1161e705c121SKalle Valo 1162e705c121SKalle Valo /* 1163e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1164e705c121SKalle Valo * interrupt 1165e705c121SKalle Valo */ 1166e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1167e705c121SKalle Valo 1168e705c121SKalle Valo /* 1169e705c121SKalle Valo * Check again since the RF kill state may have changed while 1170e705c121SKalle Valo * all the interrupts were disabled, in this case we couldn't 1171e705c121SKalle Valo * receive the RF kill interrupt and update the state in the 1172e705c121SKalle Valo * op_mode. 1173e705c121SKalle Valo * Don't call the op_mode if the rkfill state hasn't changed. 1174e705c121SKalle Valo * This allows the op_mode to call stop_device from the rfkill 1175e705c121SKalle Valo * notification without endless recursion. Under very rare 1176e705c121SKalle Valo * circumstances, we might have a small recursion if the rfkill 1177e705c121SKalle Valo * state changed exactly now while we were called from stop_device. 1178e705c121SKalle Valo * This is very unlikely but can happen and is supported. 1179e705c121SKalle Valo */ 1180e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1181e705c121SKalle Valo if (hw_rfkill) 1182e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1183e705c121SKalle Valo else 1184e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1185e705c121SKalle Valo if (hw_rfkill != was_hw_rfkill) 1186e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1187e705c121SKalle Valo 1188e705c121SKalle Valo /* re-take ownership to prevent other users from stealing the deivce */ 1189e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1190e705c121SKalle Valo } 1191e705c121SKalle Valo 1192e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1193e705c121SKalle Valo { 1194e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1195e705c121SKalle Valo 1196e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1197e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1198e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1199e705c121SKalle Valo } 1200e705c121SKalle Valo 1201e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1202e705c121SKalle Valo { 1203e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1204e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1205e705c121SKalle Valo 1206e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1207e705c121SKalle Valo 1208e705c121SKalle Valo if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1209e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1210e705c121SKalle Valo } 1211e705c121SKalle Valo 1212e705c121SKalle Valo static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) 1213e705c121SKalle Valo { 1214e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1215e705c121SKalle Valo 1216b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) { 1217e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1218e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1219e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1220e705c121SKalle Valo } 1221e705c121SKalle Valo 1222e705c121SKalle Valo iwl_disable_interrupts(trans); 1223e705c121SKalle Valo 1224e705c121SKalle Valo /* 1225e705c121SKalle Valo * in testing mode, the host stays awake and the 1226e705c121SKalle Valo * hardware won't be reset (not even partially) 1227e705c121SKalle Valo */ 1228e705c121SKalle Valo if (test) 1229e705c121SKalle Valo return; 1230e705c121SKalle Valo 1231e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1232e705c121SKalle Valo 1233e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1234e705c121SKalle Valo 1235e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1236e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1237e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1238e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1239e705c121SKalle Valo 1240b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D3) { 1241e705c121SKalle Valo /* 1242e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1243e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1244e705c121SKalle Valo * to execute some invalid memory upon resume 1245e705c121SKalle Valo */ 1246e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1247e705c121SKalle Valo } 1248e705c121SKalle Valo 1249e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1250e705c121SKalle Valo } 1251e705c121SKalle Valo 1252e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1253e705c121SKalle Valo enum iwl_d3_status *status, 1254e705c121SKalle Valo bool test) 1255e705c121SKalle Valo { 1256e705c121SKalle Valo u32 val; 1257e705c121SKalle Valo int ret; 1258e705c121SKalle Valo 1259e705c121SKalle Valo if (test) { 1260e705c121SKalle Valo iwl_enable_interrupts(trans); 1261e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1262e705c121SKalle Valo return 0; 1263e705c121SKalle Valo } 1264e705c121SKalle Valo 1265e705c121SKalle Valo /* 1266e705c121SKalle Valo * Also enables interrupts - none will happen as the device doesn't 1267e705c121SKalle Valo * know we're waking it up, only when the opmode actually tells it 1268e705c121SKalle Valo * after this call. 1269e705c121SKalle Valo */ 1270e705c121SKalle Valo iwl_pcie_reset_ict(trans); 1271e705c121SKalle Valo 1272e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1273e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1274e705c121SKalle Valo 1275e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1276e705c121SKalle Valo udelay(2); 1277e705c121SKalle Valo 1278e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1279e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1280e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1281e705c121SKalle Valo 25000); 1282e705c121SKalle Valo if (ret < 0) { 1283e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1284e705c121SKalle Valo return ret; 1285e705c121SKalle Valo } 1286e705c121SKalle Valo 1287e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1288e705c121SKalle Valo 1289b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) { 1290e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1291e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1292e705c121SKalle Valo } else { 1293e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1294e705c121SKalle Valo 1295e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1296e705c121SKalle Valo if (ret) { 1297e705c121SKalle Valo IWL_ERR(trans, 1298e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1299e705c121SKalle Valo return ret; 1300e705c121SKalle Valo } 1301e705c121SKalle Valo } 1302e705c121SKalle Valo 1303e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1304e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1305e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1306e705c121SKalle Valo else 1307e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1308e705c121SKalle Valo 1309e705c121SKalle Valo return 0; 1310e705c121SKalle Valo } 1311e705c121SKalle Valo 1312e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1313e705c121SKalle Valo { 1314e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1315e705c121SKalle Valo bool hw_rfkill; 1316e705c121SKalle Valo int err; 1317e705c121SKalle Valo 1318e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1319e705c121SKalle Valo 1320e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1321e705c121SKalle Valo if (err) { 1322e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1323e705c121SKalle Valo return err; 1324e705c121SKalle Valo } 1325e705c121SKalle Valo 1326e705c121SKalle Valo /* Reset the entire device */ 1327e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1328e705c121SKalle Valo 1329e705c121SKalle Valo usleep_range(10, 15); 1330e705c121SKalle Valo 1331e705c121SKalle Valo iwl_pcie_apm_init(trans); 1332e705c121SKalle Valo 1333e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1334e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1335e705c121SKalle Valo 1336e705c121SKalle Valo /* Set is_down to false here so that...*/ 1337e705c121SKalle Valo trans_pcie->is_down = false; 1338e705c121SKalle Valo 1339e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1340e705c121SKalle Valo if (hw_rfkill) 1341e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1342e705c121SKalle Valo else 1343e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1344e705c121SKalle Valo /* ... rfkill can call stop_device and set it false if needed */ 1345e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1346e705c121SKalle Valo 1347e705c121SKalle Valo return 0; 1348e705c121SKalle Valo } 1349e705c121SKalle Valo 1350e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1351e705c121SKalle Valo { 1352e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1353e705c121SKalle Valo int ret; 1354e705c121SKalle Valo 1355e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1356e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1357e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1358e705c121SKalle Valo 1359e705c121SKalle Valo return ret; 1360e705c121SKalle Valo } 1361e705c121SKalle Valo 1362e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1363e705c121SKalle Valo { 1364e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1365e705c121SKalle Valo 1366e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1367e705c121SKalle Valo 1368e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1369e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1370e705c121SKalle Valo iwl_disable_interrupts(trans); 1371e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1372e705c121SKalle Valo 1373e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1374e705c121SKalle Valo 1375e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1376e705c121SKalle Valo iwl_disable_interrupts(trans); 1377e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1378e705c121SKalle Valo 1379e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1380e705c121SKalle Valo 1381e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1382e705c121SKalle Valo 1383e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1384e705c121SKalle Valo } 1385e705c121SKalle Valo 1386e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1387e705c121SKalle Valo { 1388e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1389e705c121SKalle Valo } 1390e705c121SKalle Valo 1391e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1392e705c121SKalle Valo { 1393e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1394e705c121SKalle Valo } 1395e705c121SKalle Valo 1396e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1397e705c121SKalle Valo { 1398e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1399e705c121SKalle Valo } 1400e705c121SKalle Valo 1401e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1402e705c121SKalle Valo { 1403e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1404e705c121SKalle Valo ((reg & 0x000FFFFF) | (3 << 24))); 1405e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1406e705c121SKalle Valo } 1407e705c121SKalle Valo 1408e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1409e705c121SKalle Valo u32 val) 1410e705c121SKalle Valo { 1411e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1412e705c121SKalle Valo ((addr & 0x000FFFFF) | (3 << 24))); 1413e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1414e705c121SKalle Valo } 1415e705c121SKalle Valo 1416e705c121SKalle Valo static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1417e705c121SKalle Valo { 1418e705c121SKalle Valo WARN_ON(1); 1419e705c121SKalle Valo return 0; 1420e705c121SKalle Valo } 1421e705c121SKalle Valo 1422e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1423e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1424e705c121SKalle Valo { 1425e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1426e705c121SKalle Valo 1427e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1428e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1429e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1430e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1431e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1432e705c121SKalle Valo else 1433e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1434e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1435e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1436e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1437e705c121SKalle Valo 14386c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 14396c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 14406c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1441e705c121SKalle Valo 1442e705c121SKalle Valo trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; 1443e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1444e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 144541837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1446e705c121SKalle Valo 144739bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 144839bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 144939bdb17eSSharon Dvir 1450e705c121SKalle Valo /* init ref_count to 1 (should be cleared when ucode is loaded) */ 1451e705c121SKalle Valo trans_pcie->ref_count = 1; 1452e705c121SKalle Valo 1453e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1454e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1455e705c121SKalle Valo * As this function may be called again in some corner cases don't 1456e705c121SKalle Valo * do anything if NAPI was already initialized. 1457e705c121SKalle Valo */ 1458e705c121SKalle Valo if (!trans_pcie->napi.poll) { 1459e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1460e705c121SKalle Valo netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi, 1461e705c121SKalle Valo iwl_pcie_dummy_napi_poll, 64); 1462e705c121SKalle Valo } 1463e705c121SKalle Valo } 1464e705c121SKalle Valo 1465e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1466e705c121SKalle Valo { 1467e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14686eb5e529SEmmanuel Grumbach int i; 1469e705c121SKalle Valo 1470e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1471e705c121SKalle Valo 1472e705c121SKalle Valo iwl_pcie_tx_free(trans); 1473e705c121SKalle Valo iwl_pcie_rx_free(trans); 1474e705c121SKalle Valo 1475e705c121SKalle Valo free_irq(trans_pcie->pci_dev->irq, trans); 1476e705c121SKalle Valo iwl_pcie_free_ict(trans); 1477e705c121SKalle Valo 1478e705c121SKalle Valo pci_disable_msi(trans_pcie->pci_dev); 1479e705c121SKalle Valo iounmap(trans_pcie->hw_base); 1480e705c121SKalle Valo pci_release_regions(trans_pcie->pci_dev); 1481e705c121SKalle Valo pci_disable_device(trans_pcie->pci_dev); 1482e705c121SKalle Valo 1483e705c121SKalle Valo if (trans_pcie->napi.poll) 1484e705c121SKalle Valo netif_napi_del(&trans_pcie->napi); 1485e705c121SKalle Valo 1486e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1487e705c121SKalle Valo 14886eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 14896eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 14906eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 14916eb5e529SEmmanuel Grumbach 14926eb5e529SEmmanuel Grumbach if (p->page) 14936eb5e529SEmmanuel Grumbach __free_page(p->page); 14946eb5e529SEmmanuel Grumbach } 14956eb5e529SEmmanuel Grumbach 14966eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1497e705c121SKalle Valo iwl_trans_free(trans); 1498e705c121SKalle Valo } 1499e705c121SKalle Valo 1500e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1501e705c121SKalle Valo { 1502e705c121SKalle Valo if (state) 1503e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1504e705c121SKalle Valo else 1505e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1506e705c121SKalle Valo } 1507e705c121SKalle Valo 150823ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1509e705c121SKalle Valo unsigned long *flags) 1510e705c121SKalle Valo { 1511e705c121SKalle Valo int ret; 1512e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1513e705c121SKalle Valo 1514e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1515e705c121SKalle Valo 1516e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1517e705c121SKalle Valo goto out; 1518e705c121SKalle Valo 1519e705c121SKalle Valo /* this bit wakes up the NIC */ 1520e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1521e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1522e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1523e705c121SKalle Valo udelay(2); 1524e705c121SKalle Valo 1525e705c121SKalle Valo /* 1526e705c121SKalle Valo * These bits say the device is running, and should keep running for 1527e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1528e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1529e705c121SKalle Valo * 3945 and 4965 have volatile SRAM, and must save/restore contents 1530e705c121SKalle Valo * to/from host DRAM when sleeping/waking for power-saving. 1531e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1532e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1533e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1534e705c121SKalle Valo * to keep device from sleeping. 1535e705c121SKalle Valo * 1536e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1537e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1538e705c121SKalle Valo * is just for hardware register access; but GP1 MAC_SLEEP check is a 1539e705c121SKalle Valo * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1540e705c121SKalle Valo * 1541e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1542e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1543e705c121SKalle Valo */ 1544e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1545e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1546e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1547e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1548e705c121SKalle Valo if (unlikely(ret < 0)) { 1549e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1550e705c121SKalle Valo WARN_ONCE(1, 1551e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 155223ba9340SEmmanuel Grumbach iwl_read32(trans, CSR_GP_CNTRL)); 1553e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1554e705c121SKalle Valo return false; 1555e705c121SKalle Valo } 1556e705c121SKalle Valo 1557e705c121SKalle Valo out: 1558e705c121SKalle Valo /* 1559e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 1560e705c121SKalle Valo * track nic_access anyway. 1561e705c121SKalle Valo */ 1562e705c121SKalle Valo __release(&trans_pcie->reg_lock); 1563e705c121SKalle Valo return true; 1564e705c121SKalle Valo } 1565e705c121SKalle Valo 1566e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1567e705c121SKalle Valo unsigned long *flags) 1568e705c121SKalle Valo { 1569e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1570e705c121SKalle Valo 1571e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1572e705c121SKalle Valo 1573e705c121SKalle Valo /* 1574e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 1575e705c121SKalle Valo * track nic_access anyway. 1576e705c121SKalle Valo */ 1577e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 1578e705c121SKalle Valo 1579e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1580e705c121SKalle Valo goto out; 1581e705c121SKalle Valo 1582e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1583e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1584e705c121SKalle Valo /* 1585e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 1586e705c121SKalle Valo * any previous writes, but we need the write that clears the 1587e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 1588e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 1589e705c121SKalle Valo */ 1590e705c121SKalle Valo mmiowb(); 1591e705c121SKalle Valo out: 1592e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1593e705c121SKalle Valo } 1594e705c121SKalle Valo 1595e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1596e705c121SKalle Valo void *buf, int dwords) 1597e705c121SKalle Valo { 1598e705c121SKalle Valo unsigned long flags; 1599e705c121SKalle Valo int offs, ret = 0; 1600e705c121SKalle Valo u32 *vals = buf; 1601e705c121SKalle Valo 160223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1603e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1604e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1605e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1606e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1607e705c121SKalle Valo } else { 1608e705c121SKalle Valo ret = -EBUSY; 1609e705c121SKalle Valo } 1610e705c121SKalle Valo return ret; 1611e705c121SKalle Valo } 1612e705c121SKalle Valo 1613e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1614e705c121SKalle Valo const void *buf, int dwords) 1615e705c121SKalle Valo { 1616e705c121SKalle Valo unsigned long flags; 1617e705c121SKalle Valo int offs, ret = 0; 1618e705c121SKalle Valo const u32 *vals = buf; 1619e705c121SKalle Valo 162023ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1621e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1622e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1623e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1624e705c121SKalle Valo vals ? vals[offs] : 0); 1625e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1626e705c121SKalle Valo } else { 1627e705c121SKalle Valo ret = -EBUSY; 1628e705c121SKalle Valo } 1629e705c121SKalle Valo return ret; 1630e705c121SKalle Valo } 1631e705c121SKalle Valo 1632e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1633e705c121SKalle Valo unsigned long txqs, 1634e705c121SKalle Valo bool freeze) 1635e705c121SKalle Valo { 1636e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1637e705c121SKalle Valo int queue; 1638e705c121SKalle Valo 1639e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1640e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[queue]; 1641e705c121SKalle Valo unsigned long now; 1642e705c121SKalle Valo 1643e705c121SKalle Valo spin_lock_bh(&txq->lock); 1644e705c121SKalle Valo 1645e705c121SKalle Valo now = jiffies; 1646e705c121SKalle Valo 1647e705c121SKalle Valo if (txq->frozen == freeze) 1648e705c121SKalle Valo goto next_queue; 1649e705c121SKalle Valo 1650e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1651e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 1652e705c121SKalle Valo 1653e705c121SKalle Valo txq->frozen = freeze; 1654e705c121SKalle Valo 1655e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) 1656e705c121SKalle Valo goto next_queue; 1657e705c121SKalle Valo 1658e705c121SKalle Valo if (freeze) { 1659e705c121SKalle Valo if (unlikely(time_after(now, 1660e705c121SKalle Valo txq->stuck_timer.expires))) { 1661e705c121SKalle Valo /* 1662e705c121SKalle Valo * The timer should have fired, maybe it is 1663e705c121SKalle Valo * spinning right now on the lock. 1664e705c121SKalle Valo */ 1665e705c121SKalle Valo goto next_queue; 1666e705c121SKalle Valo } 1667e705c121SKalle Valo /* remember how long until the timer fires */ 1668e705c121SKalle Valo txq->frozen_expiry_remainder = 1669e705c121SKalle Valo txq->stuck_timer.expires - now; 1670e705c121SKalle Valo del_timer(&txq->stuck_timer); 1671e705c121SKalle Valo goto next_queue; 1672e705c121SKalle Valo } 1673e705c121SKalle Valo 1674e705c121SKalle Valo /* 1675e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 1676e705c121SKalle Valo * remainder before it froze 1677e705c121SKalle Valo */ 1678e705c121SKalle Valo mod_timer(&txq->stuck_timer, 1679e705c121SKalle Valo now + txq->frozen_expiry_remainder); 1680e705c121SKalle Valo 1681e705c121SKalle Valo next_queue: 1682e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1683e705c121SKalle Valo } 1684e705c121SKalle Valo } 1685e705c121SKalle Valo 16860cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 16870cd58eaaSEmmanuel Grumbach { 16880cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16890cd58eaaSEmmanuel Grumbach int i; 16900cd58eaaSEmmanuel Grumbach 16910cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 16920cd58eaaSEmmanuel Grumbach struct iwl_txq *txq = &trans_pcie->txq[i]; 16930cd58eaaSEmmanuel Grumbach 16940cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 16950cd58eaaSEmmanuel Grumbach continue; 16960cd58eaaSEmmanuel Grumbach 16970cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 16980cd58eaaSEmmanuel Grumbach 16990cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 17000cd58eaaSEmmanuel Grumbach txq->block--; 17010cd58eaaSEmmanuel Grumbach if (!txq->block) { 17020cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 17030cd58eaaSEmmanuel Grumbach txq->q.write_ptr | (i << 8)); 17040cd58eaaSEmmanuel Grumbach } 17050cd58eaaSEmmanuel Grumbach } else if (block) { 17060cd58eaaSEmmanuel Grumbach txq->block++; 17070cd58eaaSEmmanuel Grumbach } 17080cd58eaaSEmmanuel Grumbach 17090cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 17100cd58eaaSEmmanuel Grumbach } 17110cd58eaaSEmmanuel Grumbach } 17120cd58eaaSEmmanuel Grumbach 1713e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 1714e705c121SKalle Valo 1715e705c121SKalle Valo static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 1716e705c121SKalle Valo { 1717e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1718e705c121SKalle Valo struct iwl_txq *txq; 1719e705c121SKalle Valo struct iwl_queue *q; 1720e705c121SKalle Valo int cnt; 1721e705c121SKalle Valo unsigned long now = jiffies; 1722e705c121SKalle Valo u32 scd_sram_addr; 1723e705c121SKalle Valo u8 buf[16]; 1724e705c121SKalle Valo int ret = 0; 1725e705c121SKalle Valo 1726e705c121SKalle Valo /* waiting for all the tx frames complete might take a while */ 1727e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1728e705c121SKalle Valo u8 wr_ptr; 1729e705c121SKalle Valo 1730e705c121SKalle Valo if (cnt == trans_pcie->cmd_queue) 1731e705c121SKalle Valo continue; 1732e705c121SKalle Valo if (!test_bit(cnt, trans_pcie->queue_used)) 1733e705c121SKalle Valo continue; 1734e705c121SKalle Valo if (!(BIT(cnt) & txq_bm)) 1735e705c121SKalle Valo continue; 1736e705c121SKalle Valo 1737e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 1738e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 1739e705c121SKalle Valo q = &txq->q; 1740e705c121SKalle Valo wr_ptr = ACCESS_ONCE(q->write_ptr); 1741e705c121SKalle Valo 1742e705c121SKalle Valo while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && 1743e705c121SKalle Valo !time_after(jiffies, 1744e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 1745e705c121SKalle Valo u8 write_ptr = ACCESS_ONCE(q->write_ptr); 1746e705c121SKalle Valo 1747e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 1748e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 1749e705c121SKalle Valo wr_ptr, write_ptr)) 1750e705c121SKalle Valo return -ETIMEDOUT; 1751e705c121SKalle Valo msleep(1); 1752e705c121SKalle Valo } 1753e705c121SKalle Valo 1754e705c121SKalle Valo if (q->read_ptr != q->write_ptr) { 1755e705c121SKalle Valo IWL_ERR(trans, 1756e705c121SKalle Valo "fail to flush all tx fifo queues Q %d\n", cnt); 1757e705c121SKalle Valo ret = -ETIMEDOUT; 1758e705c121SKalle Valo break; 1759e705c121SKalle Valo } 1760e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 1761e705c121SKalle Valo } 1762e705c121SKalle Valo 1763e705c121SKalle Valo if (!ret) 1764e705c121SKalle Valo return 0; 1765e705c121SKalle Valo 1766e705c121SKalle Valo IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1767e705c121SKalle Valo txq->q.read_ptr, txq->q.write_ptr); 1768e705c121SKalle Valo 1769e705c121SKalle Valo scd_sram_addr = trans_pcie->scd_base_addr + 1770e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 1771e705c121SKalle Valo iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 1772e705c121SKalle Valo 1773e705c121SKalle Valo iwl_print_hex_error(trans, buf, sizeof(buf)); 1774e705c121SKalle Valo 1775e705c121SKalle Valo for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 1776e705c121SKalle Valo IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 1777e705c121SKalle Valo iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 1778e705c121SKalle Valo 1779e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1780e705c121SKalle Valo u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 1781e705c121SKalle Valo u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 1782e705c121SKalle Valo bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 1783e705c121SKalle Valo u32 tbl_dw = 1784e705c121SKalle Valo iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 1785e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 1786e705c121SKalle Valo 1787e705c121SKalle Valo if (cnt & 0x1) 1788e705c121SKalle Valo tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 1789e705c121SKalle Valo else 1790e705c121SKalle Valo tbl_dw = tbl_dw & 0x0000FFFF; 1791e705c121SKalle Valo 1792e705c121SKalle Valo IWL_ERR(trans, 1793e705c121SKalle Valo "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 1794e705c121SKalle Valo cnt, active ? "" : "in", fifo, tbl_dw, 1795e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 1796e705c121SKalle Valo (TFD_QUEUE_SIZE_MAX - 1), 1797e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 1798e705c121SKalle Valo } 1799e705c121SKalle Valo 1800e705c121SKalle Valo return ret; 1801e705c121SKalle Valo } 1802e705c121SKalle Valo 1803e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 1804e705c121SKalle Valo u32 mask, u32 value) 1805e705c121SKalle Valo { 1806e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1807e705c121SKalle Valo unsigned long flags; 1808e705c121SKalle Valo 1809e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1810e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 1811e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1812e705c121SKalle Valo } 1813e705c121SKalle Valo 1814e705c121SKalle Valo void iwl_trans_pcie_ref(struct iwl_trans *trans) 1815e705c121SKalle Valo { 1816e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1817e705c121SKalle Valo unsigned long flags; 1818e705c121SKalle Valo 1819e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 1820e705c121SKalle Valo return; 1821e705c121SKalle Valo 1822e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->ref_lock, flags); 1823e705c121SKalle Valo IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); 1824e705c121SKalle Valo trans_pcie->ref_count++; 1825e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1826e705c121SKalle Valo } 1827e705c121SKalle Valo 1828e705c121SKalle Valo void iwl_trans_pcie_unref(struct iwl_trans *trans) 1829e705c121SKalle Valo { 1830e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1831e705c121SKalle Valo unsigned long flags; 1832e705c121SKalle Valo 1833e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 1834e705c121SKalle Valo return; 1835e705c121SKalle Valo 1836e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->ref_lock, flags); 1837e705c121SKalle Valo IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); 1838e705c121SKalle Valo if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) { 1839e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1840e705c121SKalle Valo return; 1841e705c121SKalle Valo } 1842e705c121SKalle Valo trans_pcie->ref_count--; 1843e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1844e705c121SKalle Valo } 1845e705c121SKalle Valo 1846e705c121SKalle Valo static const char *get_csr_string(int cmd) 1847e705c121SKalle Valo { 1848e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 1849e705c121SKalle Valo switch (cmd) { 1850e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 1851e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 1852e705c121SKalle Valo IWL_CMD(CSR_INT); 1853e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 1854e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 1855e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 1856e705c121SKalle Valo IWL_CMD(CSR_RESET); 1857e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 1858e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 1859e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 1860e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 1861e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 1862e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 1863e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 1864e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 1865e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 1866e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 1867e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 1868e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 1869e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 1870e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 1871e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 1872e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 1873e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 1874e705c121SKalle Valo default: 1875e705c121SKalle Valo return "UNKNOWN"; 1876e705c121SKalle Valo } 1877e705c121SKalle Valo #undef IWL_CMD 1878e705c121SKalle Valo } 1879e705c121SKalle Valo 1880e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 1881e705c121SKalle Valo { 1882e705c121SKalle Valo int i; 1883e705c121SKalle Valo static const u32 csr_tbl[] = { 1884e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 1885e705c121SKalle Valo CSR_INT_COALESCING, 1886e705c121SKalle Valo CSR_INT, 1887e705c121SKalle Valo CSR_INT_MASK, 1888e705c121SKalle Valo CSR_FH_INT_STATUS, 1889e705c121SKalle Valo CSR_GPIO_IN, 1890e705c121SKalle Valo CSR_RESET, 1891e705c121SKalle Valo CSR_GP_CNTRL, 1892e705c121SKalle Valo CSR_HW_REV, 1893e705c121SKalle Valo CSR_EEPROM_REG, 1894e705c121SKalle Valo CSR_EEPROM_GP, 1895e705c121SKalle Valo CSR_OTP_GP_REG, 1896e705c121SKalle Valo CSR_GIO_REG, 1897e705c121SKalle Valo CSR_GP_UCODE_REG, 1898e705c121SKalle Valo CSR_GP_DRIVER_REG, 1899e705c121SKalle Valo CSR_UCODE_DRV_GP1, 1900e705c121SKalle Valo CSR_UCODE_DRV_GP2, 1901e705c121SKalle Valo CSR_LED_REG, 1902e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 1903e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 1904e705c121SKalle Valo CSR_ANA_PLL_CFG, 1905e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 1906e705c121SKalle Valo CSR_HW_REV_WA_REG, 1907e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 1908e705c121SKalle Valo }; 1909e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 1910e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 1911e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 1912e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 1913e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 1914e705c121SKalle Valo get_csr_string(csr_tbl[i]), 1915e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 1916e705c121SKalle Valo } 1917e705c121SKalle Valo } 1918e705c121SKalle Valo 1919e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 1920e705c121SKalle Valo /* create and remove of files */ 1921e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 1922e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 1923e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 1924e705c121SKalle Valo goto err; \ 1925e705c121SKalle Valo } while (0) 1926e705c121SKalle Valo 1927e705c121SKalle Valo /* file operation */ 1928e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 1929e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1930e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 1931e705c121SKalle Valo .open = simple_open, \ 1932e705c121SKalle Valo .llseek = generic_file_llseek, \ 1933e705c121SKalle Valo }; 1934e705c121SKalle Valo 1935e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 1936e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1937e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 1938e705c121SKalle Valo .open = simple_open, \ 1939e705c121SKalle Valo .llseek = generic_file_llseek, \ 1940e705c121SKalle Valo }; 1941e705c121SKalle Valo 1942e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 1943e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1944e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 1945e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 1946e705c121SKalle Valo .open = simple_open, \ 1947e705c121SKalle Valo .llseek = generic_file_llseek, \ 1948e705c121SKalle Valo }; 1949e705c121SKalle Valo 1950e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 1951e705c121SKalle Valo char __user *user_buf, 1952e705c121SKalle Valo size_t count, loff_t *ppos) 1953e705c121SKalle Valo { 1954e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 1955e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1956e705c121SKalle Valo struct iwl_txq *txq; 1957e705c121SKalle Valo struct iwl_queue *q; 1958e705c121SKalle Valo char *buf; 1959e705c121SKalle Valo int pos = 0; 1960e705c121SKalle Valo int cnt; 1961e705c121SKalle Valo int ret; 1962e705c121SKalle Valo size_t bufsz; 1963e705c121SKalle Valo 1964e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 1965e705c121SKalle Valo 1966e705c121SKalle Valo if (!trans_pcie->txq) 1967e705c121SKalle Valo return -EAGAIN; 1968e705c121SKalle Valo 1969e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 1970e705c121SKalle Valo if (!buf) 1971e705c121SKalle Valo return -ENOMEM; 1972e705c121SKalle Valo 1973e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1974e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 1975e705c121SKalle Valo q = &txq->q; 1976e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 1977e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 1978e705c121SKalle Valo cnt, q->read_ptr, q->write_ptr, 1979e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 1980e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 1981e705c121SKalle Valo txq->need_update, txq->frozen, 1982e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 1983e705c121SKalle Valo } 1984e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 1985e705c121SKalle Valo kfree(buf); 1986e705c121SKalle Valo return ret; 1987e705c121SKalle Valo } 1988e705c121SKalle Valo 1989e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 1990e705c121SKalle Valo char __user *user_buf, 1991e705c121SKalle Valo size_t count, loff_t *ppos) 1992e705c121SKalle Valo { 1993e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 1994e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1995e705c121SKalle Valo struct iwl_rxq *rxq = &trans_pcie->rxq; 1996e705c121SKalle Valo char buf[256]; 1997e705c121SKalle Valo int pos = 0; 1998e705c121SKalle Valo const size_t bufsz = sizeof(buf); 1999e705c121SKalle Valo 2000e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", 2001e705c121SKalle Valo rxq->read); 2002e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", 2003e705c121SKalle Valo rxq->write); 2004e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n", 2005e705c121SKalle Valo rxq->write_actual); 2006e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n", 2007e705c121SKalle Valo rxq->need_update); 2008e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", 2009e705c121SKalle Valo rxq->free_count); 2010e705c121SKalle Valo if (rxq->rb_stts) { 2011e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", 2012e705c121SKalle Valo le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); 2013e705c121SKalle Valo } else { 2014e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2015e705c121SKalle Valo "closed_rb_num: Not Allocated\n"); 2016e705c121SKalle Valo } 2017e705c121SKalle Valo return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2018e705c121SKalle Valo } 2019e705c121SKalle Valo 2020e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2021e705c121SKalle Valo char __user *user_buf, 2022e705c121SKalle Valo size_t count, loff_t *ppos) 2023e705c121SKalle Valo { 2024e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2025e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2026e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2027e705c121SKalle Valo 2028e705c121SKalle Valo int pos = 0; 2029e705c121SKalle Valo char *buf; 2030e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2031e705c121SKalle Valo ssize_t ret; 2032e705c121SKalle Valo 2033e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2034e705c121SKalle Valo if (!buf) 2035e705c121SKalle Valo return -ENOMEM; 2036e705c121SKalle Valo 2037e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2038e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2039e705c121SKalle Valo 2040e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2041e705c121SKalle Valo isr_stats->hw); 2042e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2043e705c121SKalle Valo isr_stats->sw); 2044e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2045e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2046e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2047e705c121SKalle Valo isr_stats->err_code); 2048e705c121SKalle Valo } 2049e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2050e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2051e705c121SKalle Valo isr_stats->sch); 2052e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2053e705c121SKalle Valo isr_stats->alive); 2054e705c121SKalle Valo #endif 2055e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2056e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2057e705c121SKalle Valo 2058e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2059e705c121SKalle Valo isr_stats->ctkill); 2060e705c121SKalle Valo 2061e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2062e705c121SKalle Valo isr_stats->wakeup); 2063e705c121SKalle Valo 2064e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2065e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2066e705c121SKalle Valo 2067e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2068e705c121SKalle Valo isr_stats->tx); 2069e705c121SKalle Valo 2070e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2071e705c121SKalle Valo isr_stats->unhandled); 2072e705c121SKalle Valo 2073e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2074e705c121SKalle Valo kfree(buf); 2075e705c121SKalle Valo return ret; 2076e705c121SKalle Valo } 2077e705c121SKalle Valo 2078e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2079e705c121SKalle Valo const char __user *user_buf, 2080e705c121SKalle Valo size_t count, loff_t *ppos) 2081e705c121SKalle Valo { 2082e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2083e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2084e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2085e705c121SKalle Valo 2086e705c121SKalle Valo char buf[8]; 2087e705c121SKalle Valo int buf_size; 2088e705c121SKalle Valo u32 reset_flag; 2089e705c121SKalle Valo 2090e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2091e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2092e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2093e705c121SKalle Valo return -EFAULT; 2094e705c121SKalle Valo if (sscanf(buf, "%x", &reset_flag) != 1) 2095e705c121SKalle Valo return -EFAULT; 2096e705c121SKalle Valo if (reset_flag == 0) 2097e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2098e705c121SKalle Valo 2099e705c121SKalle Valo return count; 2100e705c121SKalle Valo } 2101e705c121SKalle Valo 2102e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2103e705c121SKalle Valo const char __user *user_buf, 2104e705c121SKalle Valo size_t count, loff_t *ppos) 2105e705c121SKalle Valo { 2106e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2107e705c121SKalle Valo char buf[8]; 2108e705c121SKalle Valo int buf_size; 2109e705c121SKalle Valo int csr; 2110e705c121SKalle Valo 2111e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2112e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2113e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2114e705c121SKalle Valo return -EFAULT; 2115e705c121SKalle Valo if (sscanf(buf, "%d", &csr) != 1) 2116e705c121SKalle Valo return -EFAULT; 2117e705c121SKalle Valo 2118e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2119e705c121SKalle Valo 2120e705c121SKalle Valo return count; 2121e705c121SKalle Valo } 2122e705c121SKalle Valo 2123e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2124e705c121SKalle Valo char __user *user_buf, 2125e705c121SKalle Valo size_t count, loff_t *ppos) 2126e705c121SKalle Valo { 2127e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2128e705c121SKalle Valo char *buf = NULL; 2129e705c121SKalle Valo ssize_t ret; 2130e705c121SKalle Valo 2131e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2132e705c121SKalle Valo if (ret < 0) 2133e705c121SKalle Valo return ret; 2134e705c121SKalle Valo if (!buf) 2135e705c121SKalle Valo return -EINVAL; 2136e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2137e705c121SKalle Valo kfree(buf); 2138e705c121SKalle Valo return ret; 2139e705c121SKalle Valo } 2140e705c121SKalle Valo 2141e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2142e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2143e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2144e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2145e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2146e705c121SKalle Valo 2147f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2148f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2149e705c121SKalle Valo { 2150f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2151f8a1edb7SJohannes Berg 2152e705c121SKalle Valo DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2153e705c121SKalle Valo DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2154e705c121SKalle Valo DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2155e705c121SKalle Valo DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2156e705c121SKalle Valo DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2157e705c121SKalle Valo return 0; 2158e705c121SKalle Valo 2159e705c121SKalle Valo err: 2160e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2161e705c121SKalle Valo return -ENOMEM; 2162e705c121SKalle Valo } 2163e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2164e705c121SKalle Valo 2165e705c121SKalle Valo static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) 2166e705c121SKalle Valo { 2167e705c121SKalle Valo u32 cmdlen = 0; 2168e705c121SKalle Valo int i; 2169e705c121SKalle Valo 2170e705c121SKalle Valo for (i = 0; i < IWL_NUM_OF_TBS; i++) 2171e705c121SKalle Valo cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); 2172e705c121SKalle Valo 2173e705c121SKalle Valo return cmdlen; 2174e705c121SKalle Valo } 2175e705c121SKalle Valo 2176e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2177e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2178e705c121SKalle Valo int allocated_rb_nums) 2179e705c121SKalle Valo { 2180e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2181e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2182e705c121SKalle Valo struct iwl_rxq *rxq = &trans_pcie->rxq; 2183e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2184e705c121SKalle Valo 2185e705c121SKalle Valo spin_lock(&rxq->lock); 2186e705c121SKalle Valo 2187e705c121SKalle Valo r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2188e705c121SKalle Valo 2189e705c121SKalle Valo for (i = rxq->read, j = 0; 2190e705c121SKalle Valo i != r && j < allocated_rb_nums; 2191e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2192e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2193e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2194e705c121SKalle Valo 2195e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2196e705c121SKalle Valo DMA_FROM_DEVICE); 2197e705c121SKalle Valo 2198e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2199e705c121SKalle Valo 2200e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2201e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2202e705c121SKalle Valo rb = (void *)(*data)->data; 2203e705c121SKalle Valo rb->index = cpu_to_le32(i); 2204e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2205e705c121SKalle Valo /* remap the page for the free benefit */ 2206e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2207e705c121SKalle Valo max_len, 2208e705c121SKalle Valo DMA_FROM_DEVICE); 2209e705c121SKalle Valo 2210e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2211e705c121SKalle Valo } 2212e705c121SKalle Valo 2213e705c121SKalle Valo spin_unlock(&rxq->lock); 2214e705c121SKalle Valo 2215e705c121SKalle Valo return rb_len; 2216e705c121SKalle Valo } 2217e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2218e705c121SKalle Valo 2219e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2220e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2221e705c121SKalle Valo { 2222e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2223e705c121SKalle Valo __le32 *val; 2224e705c121SKalle Valo int i; 2225e705c121SKalle Valo 2226e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2227e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2228e705c121SKalle Valo val = (void *)(*data)->data; 2229e705c121SKalle Valo 2230e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2231e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2232e705c121SKalle Valo 2233e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2234e705c121SKalle Valo 2235e705c121SKalle Valo return csr_len; 2236e705c121SKalle Valo } 2237e705c121SKalle Valo 2238e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2239e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2240e705c121SKalle Valo { 2241e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2242e705c121SKalle Valo unsigned long flags; 2243e705c121SKalle Valo __le32 *val; 2244e705c121SKalle Valo int i; 2245e705c121SKalle Valo 224623ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2247e705c121SKalle Valo return 0; 2248e705c121SKalle Valo 2249e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2250e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2251e705c121SKalle Valo val = (void *)(*data)->data; 2252e705c121SKalle Valo 2253e705c121SKalle Valo for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2254e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2255e705c121SKalle Valo 2256e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2257e705c121SKalle Valo 2258e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2259e705c121SKalle Valo 2260e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2261e705c121SKalle Valo } 2262e705c121SKalle Valo 2263e705c121SKalle Valo static u32 2264e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2265e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2266e705c121SKalle Valo u32 monitor_len) 2267e705c121SKalle Valo { 2268e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2269e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2270e705c121SKalle Valo unsigned long flags; 2271e705c121SKalle Valo u32 i; 2272e705c121SKalle Valo 227323ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2274e705c121SKalle Valo return 0; 2275e705c121SKalle Valo 227614ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2277e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 227814ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 227914ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 228014ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2281e705c121SKalle Valo 2282e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2283e705c121SKalle Valo 2284e705c121SKalle Valo return monitor_len; 2285e705c121SKalle Valo } 2286e705c121SKalle Valo 2287e705c121SKalle Valo static u32 2288e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2289e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2290e705c121SKalle Valo u32 monitor_len) 2291e705c121SKalle Valo { 2292e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2293e705c121SKalle Valo u32 len = 0; 2294e705c121SKalle Valo 2295e705c121SKalle Valo if ((trans_pcie->fw_mon_page && 2296e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2297e705c121SKalle Valo trans->dbg_dest_tlv) { 2298e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2299e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2300e705c121SKalle Valo 2301e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2302e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2303e705c121SKalle Valo write_ptr = 2304e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2305e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2306e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2307e705c121SKalle Valo } else { 2308e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2309e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2310e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2311e705c121SKalle Valo } 2312e705c121SKalle Valo 2313e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2314e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2315e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2316e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2317e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2318e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2319e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2320e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2321e705c121SKalle Valo 2322e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 2323e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2324e705c121SKalle Valo /* 2325e705c121SKalle Valo * The firmware is now asserted, it won't write anything 2326e705c121SKalle Valo * to the buffer. CPU can take ownership to fetch the 2327e705c121SKalle Valo * data. The buffer will be handed back to the device 2328e705c121SKalle Valo * before the firmware will be restarted. 2329e705c121SKalle Valo */ 2330e705c121SKalle Valo dma_sync_single_for_cpu(trans->dev, 2331e705c121SKalle Valo trans_pcie->fw_mon_phys, 2332e705c121SKalle Valo trans_pcie->fw_mon_size, 2333e705c121SKalle Valo DMA_FROM_DEVICE); 2334e705c121SKalle Valo memcpy(fw_mon_data->data, 2335e705c121SKalle Valo page_address(trans_pcie->fw_mon_page), 2336e705c121SKalle Valo trans_pcie->fw_mon_size); 2337e705c121SKalle Valo 2338e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2339e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2340e705c121SKalle Valo /* 2341e705c121SKalle Valo * Update pointers to reflect actual values after 2342e705c121SKalle Valo * shifting 2343e705c121SKalle Valo */ 2344e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2345e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2346e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2347e705c121SKalle Valo monitor_len / sizeof(u32)); 2348e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2349e705c121SKalle Valo monitor_len = 2350e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2351e705c121SKalle Valo fw_mon_data, 2352e705c121SKalle Valo monitor_len); 2353e705c121SKalle Valo } else { 2354e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2355e705c121SKalle Valo monitor_len = 0; 2356e705c121SKalle Valo } 2357e705c121SKalle Valo 2358e705c121SKalle Valo len += monitor_len; 2359e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2360e705c121SKalle Valo } 2361e705c121SKalle Valo 2362e705c121SKalle Valo return len; 2363e705c121SKalle Valo } 2364e705c121SKalle Valo 2365e705c121SKalle Valo static struct iwl_trans_dump_data 2366e705c121SKalle Valo *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2367e705c121SKalle Valo struct iwl_fw_dbg_trigger_tlv *trigger) 2368e705c121SKalle Valo { 2369e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2370e705c121SKalle Valo struct iwl_fw_error_dump_data *data; 2371e705c121SKalle Valo struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2372e705c121SKalle Valo struct iwl_fw_error_dump_txcmd *txcmd; 2373e705c121SKalle Valo struct iwl_trans_dump_data *dump_data; 2374e705c121SKalle Valo u32 len, num_rbs; 2375e705c121SKalle Valo u32 monitor_len; 2376e705c121SKalle Valo int i, ptr; 2377e705c121SKalle Valo bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status); 2378e705c121SKalle Valo 2379e705c121SKalle Valo /* transport dump header */ 2380e705c121SKalle Valo len = sizeof(*dump_data); 2381e705c121SKalle Valo 2382e705c121SKalle Valo /* host commands */ 2383e705c121SKalle Valo len += sizeof(*data) + 2384e705c121SKalle Valo cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2385e705c121SKalle Valo 2386e705c121SKalle Valo /* FW monitor */ 2387e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2388e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2389e705c121SKalle Valo trans_pcie->fw_mon_size; 2390e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2391e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2392e705c121SKalle Valo u32 base, end; 2393e705c121SKalle Valo 2394e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2395e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2396e705c121SKalle Valo 2397e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2398e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2399e705c121SKalle Valo end = iwl_read_prph(trans, end) << 2400e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 2401e705c121SKalle Valo 2402e705c121SKalle Valo /* Make "end" point to the actual end */ 2403e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2404e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2405e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 2406e705c121SKalle Valo monitor_len = end - base; 2407e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2408e705c121SKalle Valo monitor_len; 2409e705c121SKalle Valo } else { 2410e705c121SKalle Valo monitor_len = 0; 2411e705c121SKalle Valo } 2412e705c121SKalle Valo 2413e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2414e705c121SKalle Valo dump_data = vzalloc(len); 2415e705c121SKalle Valo if (!dump_data) 2416e705c121SKalle Valo return NULL; 2417e705c121SKalle Valo 2418e705c121SKalle Valo data = (void *)dump_data->data; 2419e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2420e705c121SKalle Valo dump_data->len = len; 2421e705c121SKalle Valo 2422e705c121SKalle Valo return dump_data; 2423e705c121SKalle Valo } 2424e705c121SKalle Valo 2425e705c121SKalle Valo /* CSR registers */ 2426e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 2427e705c121SKalle Valo 2428e705c121SKalle Valo /* FH registers */ 2429e705c121SKalle Valo len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2430e705c121SKalle Valo 2431e705c121SKalle Valo if (dump_rbs) { 2432e705c121SKalle Valo /* RBs */ 2433e705c121SKalle Valo num_rbs = le16_to_cpu(ACCESS_ONCE( 2434e705c121SKalle Valo trans_pcie->rxq.rb_stts->closed_rb_num)) 2435e705c121SKalle Valo & 0x0FFF; 2436e705c121SKalle Valo num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK; 2437e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 2438e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 2439e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 2440e705c121SKalle Valo } 2441e705c121SKalle Valo 2442e705c121SKalle Valo dump_data = vzalloc(len); 2443e705c121SKalle Valo if (!dump_data) 2444e705c121SKalle Valo return NULL; 2445e705c121SKalle Valo 2446e705c121SKalle Valo len = 0; 2447e705c121SKalle Valo data = (void *)dump_data->data; 2448e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2449e705c121SKalle Valo txcmd = (void *)data->data; 2450e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 2451e705c121SKalle Valo ptr = cmdq->q.write_ptr; 2452e705c121SKalle Valo for (i = 0; i < cmdq->q.n_window; i++) { 2453e705c121SKalle Valo u8 idx = get_cmd_index(&cmdq->q, ptr); 2454e705c121SKalle Valo u32 caplen, cmdlen; 2455e705c121SKalle Valo 2456e705c121SKalle Valo cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); 2457e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2458e705c121SKalle Valo 2459e705c121SKalle Valo if (cmdlen) { 2460e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 2461e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 2462e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 2463e705c121SKalle Valo memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2464e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 2465e705c121SKalle Valo } 2466e705c121SKalle Valo 2467e705c121SKalle Valo ptr = iwl_queue_dec_wrap(ptr); 2468e705c121SKalle Valo } 2469e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 2470e705c121SKalle Valo 2471e705c121SKalle Valo data->len = cpu_to_le32(len); 2472e705c121SKalle Valo len += sizeof(*data); 2473e705c121SKalle Valo data = iwl_fw_error_next_data(data); 2474e705c121SKalle Valo 2475e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 2476e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2477e705c121SKalle Valo if (dump_rbs) 2478e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2479e705c121SKalle Valo 2480e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2481e705c121SKalle Valo 2482e705c121SKalle Valo dump_data->len = len; 2483e705c121SKalle Valo 2484e705c121SKalle Valo return dump_data; 2485e705c121SKalle Valo } 2486e705c121SKalle Valo 2487e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 2488e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 2489e705c121SKalle Valo .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2490e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 2491e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 2492e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 2493e705c121SKalle Valo 2494e705c121SKalle Valo .d3_suspend = iwl_trans_pcie_d3_suspend, 2495e705c121SKalle Valo .d3_resume = iwl_trans_pcie_d3_resume, 2496e705c121SKalle Valo 2497e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 2498e705c121SKalle Valo 2499e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 2500e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 2501e705c121SKalle Valo 2502e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 2503e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 2504e705c121SKalle Valo 2505e705c121SKalle Valo .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2506e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 25070cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2508e705c121SKalle Valo 2509e705c121SKalle Valo .write8 = iwl_trans_pcie_write8, 2510e705c121SKalle Valo .write32 = iwl_trans_pcie_write32, 2511e705c121SKalle Valo .read32 = iwl_trans_pcie_read32, 2512e705c121SKalle Valo .read_prph = iwl_trans_pcie_read_prph, 2513e705c121SKalle Valo .write_prph = iwl_trans_pcie_write_prph, 2514e705c121SKalle Valo .read_mem = iwl_trans_pcie_read_mem, 2515e705c121SKalle Valo .write_mem = iwl_trans_pcie_write_mem, 2516e705c121SKalle Valo .configure = iwl_trans_pcie_configure, 2517e705c121SKalle Valo .set_pmi = iwl_trans_pcie_set_pmi, 2518e705c121SKalle Valo .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2519e705c121SKalle Valo .release_nic_access = iwl_trans_pcie_release_nic_access, 2520e705c121SKalle Valo .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2521e705c121SKalle Valo 2522e705c121SKalle Valo .ref = iwl_trans_pcie_ref, 2523e705c121SKalle Valo .unref = iwl_trans_pcie_unref, 2524e705c121SKalle Valo 2525e705c121SKalle Valo .dump_data = iwl_trans_pcie_dump_data, 2526e705c121SKalle Valo }; 2527e705c121SKalle Valo 2528e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2529e705c121SKalle Valo const struct pci_device_id *ent, 2530e705c121SKalle Valo const struct iwl_cfg *cfg) 2531e705c121SKalle Valo { 2532e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 2533e705c121SKalle Valo struct iwl_trans *trans; 2534e705c121SKalle Valo u16 pci_cmd; 2535e705c121SKalle Valo int ret; 2536e705c121SKalle Valo 2537e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2538e705c121SKalle Valo &pdev->dev, cfg, &trans_ops_pcie, 0); 2539e705c121SKalle Valo if (!trans) 2540e705c121SKalle Valo return ERR_PTR(-ENOMEM); 2541e705c121SKalle Valo 2542e705c121SKalle Valo trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; 2543e705c121SKalle Valo 2544e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2545e705c121SKalle Valo 2546e705c121SKalle Valo trans_pcie->trans = trans; 2547e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 2548e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 2549e705c121SKalle Valo spin_lock_init(&trans_pcie->ref_lock); 2550e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 2551e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 25526eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 25536eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 25546eb5e529SEmmanuel Grumbach ret = -ENOMEM; 25556eb5e529SEmmanuel Grumbach goto out_no_pci; 25566eb5e529SEmmanuel Grumbach } 2557e705c121SKalle Valo 2558e705c121SKalle Valo ret = pci_enable_device(pdev); 2559e705c121SKalle Valo if (ret) 2560e705c121SKalle Valo goto out_no_pci; 2561e705c121SKalle Valo 2562e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 2563e705c121SKalle Valo /* 2564e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 2565e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 2566e705c121SKalle Valo * lot of power. 2567e705c121SKalle Valo */ 2568e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2569e705c121SKalle Valo PCIE_LINK_STATE_L1 | 2570e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 2571e705c121SKalle Valo } 2572e705c121SKalle Valo 2573e705c121SKalle Valo pci_set_master(pdev); 2574e705c121SKalle Valo 2575e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); 2576e705c121SKalle Valo if (!ret) 2577e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); 2578e705c121SKalle Valo if (ret) { 2579e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2580e705c121SKalle Valo if (!ret) 2581e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 2582e705c121SKalle Valo DMA_BIT_MASK(32)); 2583e705c121SKalle Valo /* both attempts failed: */ 2584e705c121SKalle Valo if (ret) { 2585e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 2586e705c121SKalle Valo goto out_pci_disable_device; 2587e705c121SKalle Valo } 2588e705c121SKalle Valo } 2589e705c121SKalle Valo 2590e705c121SKalle Valo ret = pci_request_regions(pdev, DRV_NAME); 2591e705c121SKalle Valo if (ret) { 2592e705c121SKalle Valo dev_err(&pdev->dev, "pci_request_regions failed\n"); 2593e705c121SKalle Valo goto out_pci_disable_device; 2594e705c121SKalle Valo } 2595e705c121SKalle Valo 2596e705c121SKalle Valo trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); 2597e705c121SKalle Valo if (!trans_pcie->hw_base) { 2598e705c121SKalle Valo dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); 2599e705c121SKalle Valo ret = -ENODEV; 2600e705c121SKalle Valo goto out_pci_release_regions; 2601e705c121SKalle Valo } 2602e705c121SKalle Valo 2603e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 2604e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 2605e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 2606e705c121SKalle Valo 2607e705c121SKalle Valo trans->dev = &pdev->dev; 2608e705c121SKalle Valo trans_pcie->pci_dev = pdev; 2609e705c121SKalle Valo iwl_disable_interrupts(trans); 2610e705c121SKalle Valo 2611e705c121SKalle Valo ret = pci_enable_msi(pdev); 2612e705c121SKalle Valo if (ret) { 2613e705c121SKalle Valo dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret); 2614e705c121SKalle Valo /* enable rfkill interrupt: hw bug w/a */ 2615e705c121SKalle Valo pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 2616e705c121SKalle Valo if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 2617e705c121SKalle Valo pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 2618e705c121SKalle Valo pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 2619e705c121SKalle Valo } 2620e705c121SKalle Valo } 2621e705c121SKalle Valo 2622e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 2623e705c121SKalle Valo /* 2624e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 2625e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 2626e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 2627e705c121SKalle Valo * in the old format. 2628e705c121SKalle Valo */ 2629e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 2630e705c121SKalle Valo unsigned long flags; 2631e705c121SKalle Valo 2632e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 2633e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 2634e705c121SKalle Valo 2635e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 2636e705c121SKalle Valo if (ret) { 2637e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 2638e705c121SKalle Valo goto out_pci_disable_msi; 2639e705c121SKalle Valo } 2640e705c121SKalle Valo 2641e705c121SKalle Valo /* 2642e705c121SKalle Valo * in-order to recognize C step driver should read chip version 2643e705c121SKalle Valo * id located at the AUX bus MISC address space. 2644e705c121SKalle Valo */ 2645e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 2646e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 2647e705c121SKalle Valo udelay(2); 2648e705c121SKalle Valo 2649e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2650e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2651e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2652e705c121SKalle Valo 25000); 2653e705c121SKalle Valo if (ret < 0) { 2654e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 2655e705c121SKalle Valo goto out_pci_disable_msi; 2656e705c121SKalle Valo } 2657e705c121SKalle Valo 265823ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2659e705c121SKalle Valo u32 hw_step; 2660e705c121SKalle Valo 266114ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 2662e705c121SKalle Valo hw_step |= ENABLE_WFPM; 266314ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 266414ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 2665e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 2666e705c121SKalle Valo if (hw_step == 0x3) 2667e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 2668e705c121SKalle Valo (SILICON_C_STEP << 2); 2669e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2670e705c121SKalle Valo } 2671e705c121SKalle Valo } 2672e705c121SKalle Valo 2673e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 2674e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 2675e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 2676e705c121SKalle Valo 2677e705c121SKalle Valo /* Initialize the wait queue for commands */ 2678e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 2679e705c121SKalle Valo 2680e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 2681e705c121SKalle Valo if (ret) 2682e705c121SKalle Valo goto out_pci_disable_msi; 2683e705c121SKalle Valo 2684e705c121SKalle Valo ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, 2685e705c121SKalle Valo iwl_pcie_irq_handler, 2686e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 2687e705c121SKalle Valo if (ret) { 2688e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 2689e705c121SKalle Valo goto out_free_ict; 2690e705c121SKalle Valo } 2691e705c121SKalle Valo 2692e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 2693e705c121SKalle Valo 2694e705c121SKalle Valo return trans; 2695e705c121SKalle Valo 2696e705c121SKalle Valo out_free_ict: 2697e705c121SKalle Valo iwl_pcie_free_ict(trans); 2698e705c121SKalle Valo out_pci_disable_msi: 2699e705c121SKalle Valo pci_disable_msi(pdev); 2700e705c121SKalle Valo out_pci_release_regions: 2701e705c121SKalle Valo pci_release_regions(pdev); 2702e705c121SKalle Valo out_pci_disable_device: 2703e705c121SKalle Valo pci_disable_device(pdev); 2704e705c121SKalle Valo out_no_pci: 27056eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 2706e705c121SKalle Valo iwl_trans_free(trans); 2707e705c121SKalle Valo return ERR_PTR(ret); 2708e705c121SKalle Valo } 2709