1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 1062d7476dSEmmanuel Grumbach * Copyright(c) 2016 Intel Deutschland GmbH 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * You should have received a copy of the GNU General Public License 22e705c121SKalle Valo * along with this program; if not, write to the Free Software 23e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24e705c121SKalle Valo * USA 25e705c121SKalle Valo * 26e705c121SKalle Valo * The full GNU General Public License is included in this distribution 27e705c121SKalle Valo * in the file called COPYING. 28e705c121SKalle Valo * 29e705c121SKalle Valo * Contact Information: 30cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 31e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32e705c121SKalle Valo * 33e705c121SKalle Valo * BSD LICENSE 34e705c121SKalle Valo * 35e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 3762d7476dSEmmanuel Grumbach * Copyright(c) 2016 Intel Deutschland GmbH 38e705c121SKalle Valo * All rights reserved. 39e705c121SKalle Valo * 40e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 41e705c121SKalle Valo * modification, are permitted provided that the following conditions 42e705c121SKalle Valo * are met: 43e705c121SKalle Valo * 44e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 45e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 46e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 47e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 48e705c121SKalle Valo * the documentation and/or other materials provided with the 49e705c121SKalle Valo * distribution. 50e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 51e705c121SKalle Valo * contributors may be used to endorse or promote products derived 52e705c121SKalle Valo * from this software without specific prior written permission. 53e705c121SKalle Valo * 54e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65e705c121SKalle Valo * 66e705c121SKalle Valo *****************************************************************************/ 67e705c121SKalle Valo #include <linux/pci.h> 68e705c121SKalle Valo #include <linux/pci-aspm.h> 69e705c121SKalle Valo #include <linux/interrupt.h> 70e705c121SKalle Valo #include <linux/debugfs.h> 71e705c121SKalle Valo #include <linux/sched.h> 72e705c121SKalle Valo #include <linux/bitops.h> 73e705c121SKalle Valo #include <linux/gfp.h> 74e705c121SKalle Valo #include <linux/vmalloc.h> 75e705c121SKalle Valo 76e705c121SKalle Valo #include "iwl-drv.h" 77e705c121SKalle Valo #include "iwl-trans.h" 78e705c121SKalle Valo #include "iwl-csr.h" 79e705c121SKalle Valo #include "iwl-prph.h" 80e705c121SKalle Valo #include "iwl-scd.h" 81e705c121SKalle Valo #include "iwl-agn-hw.h" 82e705c121SKalle Valo #include "iwl-fw-error-dump.h" 83e705c121SKalle Valo #include "internal.h" 84e705c121SKalle Valo #include "iwl-fh.h" 85e705c121SKalle Valo 86e705c121SKalle Valo /* extended range in FW SRAM */ 87e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 89e705c121SKalle Valo 90e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 91e705c121SKalle Valo { 92e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 93e705c121SKalle Valo 94e705c121SKalle Valo if (!trans_pcie->fw_mon_page) 95e705c121SKalle Valo return; 96e705c121SKalle Valo 97e705c121SKalle Valo dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 98e705c121SKalle Valo trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 99e705c121SKalle Valo __free_pages(trans_pcie->fw_mon_page, 100e705c121SKalle Valo get_order(trans_pcie->fw_mon_size)); 101e705c121SKalle Valo trans_pcie->fw_mon_page = NULL; 102e705c121SKalle Valo trans_pcie->fw_mon_phys = 0; 103e705c121SKalle Valo trans_pcie->fw_mon_size = 0; 104e705c121SKalle Valo } 105e705c121SKalle Valo 106e705c121SKalle Valo static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 107e705c121SKalle Valo { 108e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 109e705c121SKalle Valo struct page *page = NULL; 110e705c121SKalle Valo dma_addr_t phys; 111e705c121SKalle Valo u32 size = 0; 112e705c121SKalle Valo u8 power; 113e705c121SKalle Valo 114e705c121SKalle Valo if (!max_power) { 115e705c121SKalle Valo /* default max_power is maximum */ 116e705c121SKalle Valo max_power = 26; 117e705c121SKalle Valo } else { 118e705c121SKalle Valo max_power += 11; 119e705c121SKalle Valo } 120e705c121SKalle Valo 121e705c121SKalle Valo if (WARN(max_power > 26, 122e705c121SKalle Valo "External buffer size for monitor is too big %d, check the FW TLV\n", 123e705c121SKalle Valo max_power)) 124e705c121SKalle Valo return; 125e705c121SKalle Valo 126e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 127e705c121SKalle Valo dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 128e705c121SKalle Valo trans_pcie->fw_mon_size, 129e705c121SKalle Valo DMA_FROM_DEVICE); 130e705c121SKalle Valo return; 131e705c121SKalle Valo } 132e705c121SKalle Valo 133e705c121SKalle Valo phys = 0; 134e705c121SKalle Valo for (power = max_power; power >= 11; power--) { 135e705c121SKalle Valo int order; 136e705c121SKalle Valo 137e705c121SKalle Valo size = BIT(power); 138e705c121SKalle Valo order = get_order(size); 139e705c121SKalle Valo page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 140e705c121SKalle Valo order); 141e705c121SKalle Valo if (!page) 142e705c121SKalle Valo continue; 143e705c121SKalle Valo 144e705c121SKalle Valo phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 145e705c121SKalle Valo DMA_FROM_DEVICE); 146e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys)) { 147e705c121SKalle Valo __free_pages(page, order); 148e705c121SKalle Valo page = NULL; 149e705c121SKalle Valo continue; 150e705c121SKalle Valo } 151e705c121SKalle Valo IWL_INFO(trans, 152e705c121SKalle Valo "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 153e705c121SKalle Valo size, order); 154e705c121SKalle Valo break; 155e705c121SKalle Valo } 156e705c121SKalle Valo 157e705c121SKalle Valo if (WARN_ON_ONCE(!page)) 158e705c121SKalle Valo return; 159e705c121SKalle Valo 160e705c121SKalle Valo if (power != max_power) 161e705c121SKalle Valo IWL_ERR(trans, 162e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 163e705c121SKalle Valo (unsigned long)BIT(power - 10), 164e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 165e705c121SKalle Valo 166e705c121SKalle Valo trans_pcie->fw_mon_page = page; 167e705c121SKalle Valo trans_pcie->fw_mon_phys = phys; 168e705c121SKalle Valo trans_pcie->fw_mon_size = size; 169e705c121SKalle Valo } 170e705c121SKalle Valo 171e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 172e705c121SKalle Valo { 173e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 174e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 175e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 176e705c121SKalle Valo } 177e705c121SKalle Valo 178e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 179e705c121SKalle Valo { 180e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 181e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 182e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 183e705c121SKalle Valo } 184e705c121SKalle Valo 185e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 186e705c121SKalle Valo { 187e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 188e705c121SKalle Valo return; 189e705c121SKalle Valo 190e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 191e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 192e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 193e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 194e705c121SKalle Valo else 195e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 196e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 197e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 198e705c121SKalle Valo } 199e705c121SKalle Valo 200e705c121SKalle Valo /* PCI registers */ 201e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 202e705c121SKalle Valo 203e705c121SKalle Valo static void iwl_pcie_apm_config(struct iwl_trans *trans) 204e705c121SKalle Valo { 205e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 206e705c121SKalle Valo u16 lctl; 207e705c121SKalle Valo u16 cap; 208e705c121SKalle Valo 209e705c121SKalle Valo /* 210e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 211e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 212e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 213e705c121SKalle Valo * costs negligible amount of power savings. 214e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 215e705c121SKalle Valo * power savings, even without L1. 216e705c121SKalle Valo */ 217e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 218e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 219e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 220e705c121SKalle Valo else 221e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 222e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 223e705c121SKalle Valo 224e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 225e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 226e705c121SKalle Valo dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 227e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 228e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 229e705c121SKalle Valo } 230e705c121SKalle Valo 231e705c121SKalle Valo /* 232e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 233e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 234e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 235e705c121SKalle Valo */ 236e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 237e705c121SKalle Valo { 238e705c121SKalle Valo int ret = 0; 239e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 240e705c121SKalle Valo 241e705c121SKalle Valo /* 242e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 243e705c121SKalle Valo * bits already set by default after reset. 244e705c121SKalle Valo */ 245e705c121SKalle Valo 246e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 247e705c121SKalle Valo if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 248e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 249e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 250e705c121SKalle Valo 251e705c121SKalle Valo /* 252e705c121SKalle Valo * Disable L0s without affecting L1; 253e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 254e705c121SKalle Valo */ 255e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 256e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 257e705c121SKalle Valo 258e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 259e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 260e705c121SKalle Valo 261e705c121SKalle Valo /* 262e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 263e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 264e705c121SKalle Valo */ 265e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 266e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 267e705c121SKalle Valo 268e705c121SKalle Valo iwl_pcie_apm_config(trans); 269e705c121SKalle Valo 270e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 271e705c121SKalle Valo if (trans->cfg->base_params->pll_cfg_val) 272e705c121SKalle Valo iwl_set_bit(trans, CSR_ANA_PLL_CFG, 273e705c121SKalle Valo trans->cfg->base_params->pll_cfg_val); 274e705c121SKalle Valo 275e705c121SKalle Valo /* 276e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 277e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 278e705c121SKalle Valo */ 279e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 280e705c121SKalle Valo 281e705c121SKalle Valo /* 282e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 283e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 284e705c121SKalle Valo * and accesses to uCode SRAM. 285e705c121SKalle Valo */ 286e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 287e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 288e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 289e705c121SKalle Valo if (ret < 0) { 290e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 291e705c121SKalle Valo goto out; 292e705c121SKalle Valo } 293e705c121SKalle Valo 294e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 295e705c121SKalle Valo /* 296e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 297e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 298e705c121SKalle Valo * not related to host_interrupt_operation_mode. 299e705c121SKalle Valo * 300e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 301e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 302e705c121SKalle Valo * that we wake up from L1 on time. 303e705c121SKalle Valo * 304e705c121SKalle Valo * This looks weird: read twice the same register, discard the 305e705c121SKalle Valo * value, set a bit, and yet again, read that same register 306e705c121SKalle Valo * just to discard the value. But that's the way the hardware 307e705c121SKalle Valo * seems to like it. 308e705c121SKalle Valo */ 309e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 310e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 311e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 312e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 313e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 314e705c121SKalle Valo } 315e705c121SKalle Valo 316e705c121SKalle Valo /* 317e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 318e705c121SKalle Valo * 319e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 320e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 321e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 322e705c121SKalle Valo */ 323e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 324e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 325e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 326e705c121SKalle Valo udelay(20); 327e705c121SKalle Valo 328e705c121SKalle Valo /* Disable L1-Active */ 329e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 330e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 331e705c121SKalle Valo 332e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 333e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 334e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 335e705c121SKalle Valo } 336e705c121SKalle Valo 337e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 338e705c121SKalle Valo 339e705c121SKalle Valo out: 340e705c121SKalle Valo return ret; 341e705c121SKalle Valo } 342e705c121SKalle Valo 343e705c121SKalle Valo /* 344e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 345e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 346e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 347e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 348e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 349e705c121SKalle Valo */ 350e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 351e705c121SKalle Valo { 352e705c121SKalle Valo int ret; 353e705c121SKalle Valo u32 apmg_gp1_reg; 354e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 355e705c121SKalle Valo u32 dl_cfg_reg; 356e705c121SKalle Valo 357e705c121SKalle Valo /* Force XTAL ON */ 358e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 359e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 360e705c121SKalle Valo 361e705c121SKalle Valo /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 362e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 363e705c121SKalle Valo 364e705c121SKalle Valo udelay(10); 365e705c121SKalle Valo 366e705c121SKalle Valo /* 367e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 368e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 369e705c121SKalle Valo */ 370e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 371e705c121SKalle Valo 372e705c121SKalle Valo /* 373e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 374e705c121SKalle Valo * device-internal resources is possible. 375e705c121SKalle Valo */ 376e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 377e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 378e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 379e705c121SKalle Valo 25000); 380e705c121SKalle Valo if (WARN_ON(ret < 0)) { 381e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 382e705c121SKalle Valo /* Release XTAL ON request */ 383e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 384e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 385e705c121SKalle Valo return; 386e705c121SKalle Valo } 387e705c121SKalle Valo 388e705c121SKalle Valo /* 389e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 390e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 391e705c121SKalle Valo */ 392e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 393e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 394e705c121SKalle Valo 395e705c121SKalle Valo /* 396e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 397e705c121SKalle Valo * caused by APMG idle state. 398e705c121SKalle Valo */ 399e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 400e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 401e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 402e705c121SKalle Valo apmg_xtal_cfg_reg | 403e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 404e705c121SKalle Valo 405e705c121SKalle Valo /* 406e705c121SKalle Valo * Reset entire device again - do controller reset (results in 407e705c121SKalle Valo * SHRD_HW_RST). Turn MAC off before proceeding. 408e705c121SKalle Valo */ 409e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 410e705c121SKalle Valo 411e705c121SKalle Valo udelay(10); 412e705c121SKalle Valo 413e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 414e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 415e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 416e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 417e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 418e705c121SKalle Valo 419e705c121SKalle Valo /* Clear delay line clock power up */ 420e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 421e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 422e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 423e705c121SKalle Valo 424e705c121SKalle Valo /* 425e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 426e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 427e705c121SKalle Valo */ 428e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 429e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 430e705c121SKalle Valo 431e705c121SKalle Valo /* 432e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 433e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 434e705c121SKalle Valo */ 435e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 436e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 437e705c121SKalle Valo 438e705c121SKalle Valo /* Activates XTAL resources monitor */ 439e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 440e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 441e705c121SKalle Valo 442e705c121SKalle Valo /* Release XTAL ON request */ 443e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 444e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 445e705c121SKalle Valo udelay(10); 446e705c121SKalle Valo 447e705c121SKalle Valo /* Release APMG XTAL */ 448e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 449e705c121SKalle Valo apmg_xtal_cfg_reg & 450e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 451e705c121SKalle Valo } 452e705c121SKalle Valo 453e705c121SKalle Valo static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 454e705c121SKalle Valo { 455e705c121SKalle Valo int ret = 0; 456e705c121SKalle Valo 457e705c121SKalle Valo /* stop device's busmaster DMA activity */ 458e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 459e705c121SKalle Valo 460e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_RESET, 461e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 462e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 463e705c121SKalle Valo if (ret < 0) 464e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 465e705c121SKalle Valo 466e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 467e705c121SKalle Valo 468e705c121SKalle Valo return ret; 469e705c121SKalle Valo } 470e705c121SKalle Valo 471e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 472e705c121SKalle Valo { 473e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 474e705c121SKalle Valo 475e705c121SKalle Valo if (op_mode_leave) { 476e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 477e705c121SKalle Valo iwl_pcie_apm_init(trans); 478e705c121SKalle Valo 479e705c121SKalle Valo /* inform ME that we are leaving */ 480e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 481e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 482e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 483e705c121SKalle Valo else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 484e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 485e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 486e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 487e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 488e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 489e705c121SKalle Valo mdelay(1); 490e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 491e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 492e705c121SKalle Valo } 493e705c121SKalle Valo mdelay(5); 494e705c121SKalle Valo } 495e705c121SKalle Valo 496e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 497e705c121SKalle Valo 498e705c121SKalle Valo /* Stop device's DMA activity */ 499e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 500e705c121SKalle Valo 501e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 502e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 503e705c121SKalle Valo return; 504e705c121SKalle Valo } 505e705c121SKalle Valo 506e705c121SKalle Valo /* Reset the entire device */ 507e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 508e705c121SKalle Valo 509e705c121SKalle Valo udelay(10); 510e705c121SKalle Valo 511e705c121SKalle Valo /* 512e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 513e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 514e705c121SKalle Valo */ 515e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 516e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 517e705c121SKalle Valo } 518e705c121SKalle Valo 519e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 520e705c121SKalle Valo { 521e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 522e705c121SKalle Valo 523e705c121SKalle Valo /* nic_init */ 524e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 525e705c121SKalle Valo iwl_pcie_apm_init(trans); 526e705c121SKalle Valo 527e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 528e705c121SKalle Valo 529e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 530e705c121SKalle Valo 531e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 532e705c121SKalle Valo 533e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 534e705c121SKalle Valo iwl_pcie_rx_init(trans); 535e705c121SKalle Valo 536e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 537e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 538e705c121SKalle Valo return -ENOMEM; 539e705c121SKalle Valo 540e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 541e705c121SKalle Valo /* enable shadow regs in HW */ 542e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 543e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 544e705c121SKalle Valo } 545e705c121SKalle Valo 546e705c121SKalle Valo return 0; 547e705c121SKalle Valo } 548e705c121SKalle Valo 549e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 550e705c121SKalle Valo 551e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 552e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 553e705c121SKalle Valo { 554e705c121SKalle Valo int ret; 555e705c121SKalle Valo 556e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 557e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 558e705c121SKalle Valo 559e705c121SKalle Valo /* See if we got it */ 560e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 561e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 562e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 563e705c121SKalle Valo HW_READY_TIMEOUT); 564e705c121SKalle Valo 565e705c121SKalle Valo if (ret >= 0) 566e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 567e705c121SKalle Valo 568e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 569e705c121SKalle Valo return ret; 570e705c121SKalle Valo } 571e705c121SKalle Valo 572e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 573e705c121SKalle Valo static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 574e705c121SKalle Valo { 575e705c121SKalle Valo int ret; 576e705c121SKalle Valo int t = 0; 577e705c121SKalle Valo int iter; 578e705c121SKalle Valo 579e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 580e705c121SKalle Valo 581e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 582e705c121SKalle Valo /* If the card is ready, exit 0 */ 583e705c121SKalle Valo if (ret >= 0) 584e705c121SKalle Valo return 0; 585e705c121SKalle Valo 586e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 587e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 588e705c121SKalle Valo msleep(1); 589e705c121SKalle Valo 590e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 591e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 592e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 593e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 594e705c121SKalle Valo 595e705c121SKalle Valo do { 596e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 597e705c121SKalle Valo if (ret >= 0) 598e705c121SKalle Valo return 0; 599e705c121SKalle Valo 600e705c121SKalle Valo usleep_range(200, 1000); 601e705c121SKalle Valo t += 200; 602e705c121SKalle Valo } while (t < 150000); 603e705c121SKalle Valo msleep(25); 604e705c121SKalle Valo } 605e705c121SKalle Valo 606e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 607e705c121SKalle Valo 608e705c121SKalle Valo return ret; 609e705c121SKalle Valo } 610e705c121SKalle Valo 611e705c121SKalle Valo /* 612e705c121SKalle Valo * ucode 613e705c121SKalle Valo */ 614e705c121SKalle Valo static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, 615e705c121SKalle Valo dma_addr_t phy_addr, u32 byte_cnt) 616e705c121SKalle Valo { 617e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 618e705c121SKalle Valo int ret; 619e705c121SKalle Valo 620e705c121SKalle Valo trans_pcie->ucode_write_complete = false; 621e705c121SKalle Valo 622e705c121SKalle Valo iwl_write_direct32(trans, 623e705c121SKalle Valo FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 624e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 625e705c121SKalle Valo 626e705c121SKalle Valo iwl_write_direct32(trans, 627e705c121SKalle Valo FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 628e705c121SKalle Valo dst_addr); 629e705c121SKalle Valo 630e705c121SKalle Valo iwl_write_direct32(trans, 631e705c121SKalle Valo FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 632e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 633e705c121SKalle Valo 634e705c121SKalle Valo iwl_write_direct32(trans, 635e705c121SKalle Valo FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 636e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 637e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 638e705c121SKalle Valo 639e705c121SKalle Valo iwl_write_direct32(trans, 640e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 641e705c121SKalle Valo 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 642e705c121SKalle Valo 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 643e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 644e705c121SKalle Valo 645e705c121SKalle Valo iwl_write_direct32(trans, 646e705c121SKalle Valo FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 647e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 648e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 649e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 650e705c121SKalle Valo 651e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 652e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 653e705c121SKalle Valo if (!ret) { 654e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 655e705c121SKalle Valo return -ETIMEDOUT; 656e705c121SKalle Valo } 657e705c121SKalle Valo 658e705c121SKalle Valo return 0; 659e705c121SKalle Valo } 660e705c121SKalle Valo 661e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 662e705c121SKalle Valo const struct fw_desc *section) 663e705c121SKalle Valo { 664e705c121SKalle Valo u8 *v_addr; 665e705c121SKalle Valo dma_addr_t p_addr; 666e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 667e705c121SKalle Valo int ret = 0; 668e705c121SKalle Valo 669e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 670e705c121SKalle Valo section_num); 671e705c121SKalle Valo 672e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 673e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 674e705c121SKalle Valo if (!v_addr) { 675e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 676e705c121SKalle Valo chunk_sz = PAGE_SIZE; 677e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 678e705c121SKalle Valo &p_addr, GFP_KERNEL); 679e705c121SKalle Valo if (!v_addr) 680e705c121SKalle Valo return -ENOMEM; 681e705c121SKalle Valo } 682e705c121SKalle Valo 683e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 684e705c121SKalle Valo u32 copy_size, dst_addr; 685e705c121SKalle Valo bool extended_addr = false; 686e705c121SKalle Valo 687e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 688e705c121SKalle Valo dst_addr = section->offset + offset; 689e705c121SKalle Valo 690e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 691e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 692e705c121SKalle Valo extended_addr = true; 693e705c121SKalle Valo 694e705c121SKalle Valo if (extended_addr) 695e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 696e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 697e705c121SKalle Valo 698e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 699e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 700e705c121SKalle Valo copy_size); 701e705c121SKalle Valo 702e705c121SKalle Valo if (extended_addr) 703e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 704e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 705e705c121SKalle Valo 706e705c121SKalle Valo if (ret) { 707e705c121SKalle Valo IWL_ERR(trans, 708e705c121SKalle Valo "Could not load the [%d] uCode section\n", 709e705c121SKalle Valo section_num); 710e705c121SKalle Valo break; 711e705c121SKalle Valo } 712e705c121SKalle Valo } 713e705c121SKalle Valo 714e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 715e705c121SKalle Valo return ret; 716e705c121SKalle Valo } 717e705c121SKalle Valo 718e705c121SKalle Valo /* 719e705c121SKalle Valo * Driver Takes the ownership on secure machine before FW load 720e705c121SKalle Valo * and prevent race with the BT load. 721e705c121SKalle Valo * W/A for ROM bug. (should be remove in the next Si step) 722e705c121SKalle Valo */ 723e705c121SKalle Valo static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 724e705c121SKalle Valo { 725e705c121SKalle Valo u32 val, loop = 1000; 726e705c121SKalle Valo 727e705c121SKalle Valo /* 728e705c121SKalle Valo * Check the RSA semaphore is accessible. 729e705c121SKalle Valo * If the HW isn't locked and the rsa semaphore isn't accessible, 730e705c121SKalle Valo * we are in trouble. 731e705c121SKalle Valo */ 732e705c121SKalle Valo val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 733e705c121SKalle Valo if (val & (BIT(1) | BIT(17))) { 734e705c121SKalle Valo IWL_INFO(trans, 735e705c121SKalle Valo "can't access the RSA semaphore it is write protected\n"); 736e705c121SKalle Valo return 0; 737e705c121SKalle Valo } 738e705c121SKalle Valo 739e705c121SKalle Valo /* take ownership on the AUX IF */ 740e705c121SKalle Valo iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 741e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 742e705c121SKalle Valo 743e705c121SKalle Valo do { 744e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 745e705c121SKalle Valo val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 746e705c121SKalle Valo if (val == 0x1) { 747e705c121SKalle Valo iwl_write_prph(trans, RSA_ENABLE, 0); 748e705c121SKalle Valo return 0; 749e705c121SKalle Valo } 750e705c121SKalle Valo 751e705c121SKalle Valo udelay(10); 752e705c121SKalle Valo loop--; 753e705c121SKalle Valo } while (loop > 0); 754e705c121SKalle Valo 755e705c121SKalle Valo IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 756e705c121SKalle Valo return -EIO; 757e705c121SKalle Valo } 758e705c121SKalle Valo 759e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 760e705c121SKalle Valo const struct fw_img *image, 761e705c121SKalle Valo int cpu, 762e705c121SKalle Valo int *first_ucode_section) 763e705c121SKalle Valo { 764e705c121SKalle Valo int shift_param; 765e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 766e705c121SKalle Valo u32 val, last_read_idx = 0; 767e705c121SKalle Valo 768e705c121SKalle Valo if (cpu == 1) { 769e705c121SKalle Valo shift_param = 0; 770e705c121SKalle Valo *first_ucode_section = 0; 771e705c121SKalle Valo } else { 772e705c121SKalle Valo shift_param = 16; 773e705c121SKalle Valo (*first_ucode_section)++; 774e705c121SKalle Valo } 775e705c121SKalle Valo 776e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 777e705c121SKalle Valo last_read_idx = i; 778e705c121SKalle Valo 779e705c121SKalle Valo /* 780e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 781e705c121SKalle Valo * CPU1 to CPU2. 782e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 783e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 784e705c121SKalle Valo */ 785e705c121SKalle Valo if (!image->sec[i].data || 786e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 787e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 788e705c121SKalle Valo IWL_DEBUG_FW(trans, 789e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 790e705c121SKalle Valo i); 791e705c121SKalle Valo break; 792e705c121SKalle Valo } 793e705c121SKalle Valo 794e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 795e705c121SKalle Valo if (ret) 796e705c121SKalle Valo return ret; 797e705c121SKalle Valo 798e705c121SKalle Valo /* Notify the ucode of the loaded section number and status */ 799e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 800e705c121SKalle Valo val = val | (sec_num << shift_param); 801e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 802e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 803e705c121SKalle Valo } 804e705c121SKalle Valo 805e705c121SKalle Valo *first_ucode_section = last_read_idx; 806e705c121SKalle Valo 807e705c121SKalle Valo if (cpu == 1) 808e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); 809e705c121SKalle Valo else 810e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 811e705c121SKalle Valo 812e705c121SKalle Valo return 0; 813e705c121SKalle Valo } 814e705c121SKalle Valo 815e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 816e705c121SKalle Valo const struct fw_img *image, 817e705c121SKalle Valo int cpu, 818e705c121SKalle Valo int *first_ucode_section) 819e705c121SKalle Valo { 820e705c121SKalle Valo int shift_param; 821e705c121SKalle Valo int i, ret = 0; 822e705c121SKalle Valo u32 last_read_idx = 0; 823e705c121SKalle Valo 824e705c121SKalle Valo if (cpu == 1) { 825e705c121SKalle Valo shift_param = 0; 826e705c121SKalle Valo *first_ucode_section = 0; 827e705c121SKalle Valo } else { 828e705c121SKalle Valo shift_param = 16; 829e705c121SKalle Valo (*first_ucode_section)++; 830e705c121SKalle Valo } 831e705c121SKalle Valo 832e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 833e705c121SKalle Valo last_read_idx = i; 834e705c121SKalle Valo 835e705c121SKalle Valo /* 836e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 837e705c121SKalle Valo * CPU1 to CPU2. 838e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 839e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 840e705c121SKalle Valo */ 841e705c121SKalle Valo if (!image->sec[i].data || 842e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 843e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 844e705c121SKalle Valo IWL_DEBUG_FW(trans, 845e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 846e705c121SKalle Valo i); 847e705c121SKalle Valo break; 848e705c121SKalle Valo } 849e705c121SKalle Valo 850e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 851e705c121SKalle Valo if (ret) 852e705c121SKalle Valo return ret; 853e705c121SKalle Valo } 854e705c121SKalle Valo 855e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 856e705c121SKalle Valo iwl_set_bits_prph(trans, 857e705c121SKalle Valo CSR_UCODE_LOAD_STATUS_ADDR, 858e705c121SKalle Valo (LMPM_CPU_UCODE_LOADING_COMPLETED | 859e705c121SKalle Valo LMPM_CPU_HDRS_LOADING_COMPLETED | 860e705c121SKalle Valo LMPM_CPU_UCODE_LOADING_STARTED) << 861e705c121SKalle Valo shift_param); 862e705c121SKalle Valo 863e705c121SKalle Valo *first_ucode_section = last_read_idx; 864e705c121SKalle Valo 865e705c121SKalle Valo return 0; 866e705c121SKalle Valo } 867e705c121SKalle Valo 868e705c121SKalle Valo static void iwl_pcie_apply_destination(struct iwl_trans *trans) 869e705c121SKalle Valo { 870e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 871e705c121SKalle Valo const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 872e705c121SKalle Valo int i; 873e705c121SKalle Valo 874e705c121SKalle Valo if (dest->version) 875e705c121SKalle Valo IWL_ERR(trans, 876e705c121SKalle Valo "DBG DEST version is %d - expect issues\n", 877e705c121SKalle Valo dest->version); 878e705c121SKalle Valo 879e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 880e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 881e705c121SKalle Valo 882e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 883e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 884e705c121SKalle Valo else 885e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 886e705c121SKalle Valo 887e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 888e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 889e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 890e705c121SKalle Valo 891e705c121SKalle Valo switch (dest->reg_ops[i].op) { 892e705c121SKalle Valo case CSR_ASSIGN: 893e705c121SKalle Valo iwl_write32(trans, addr, val); 894e705c121SKalle Valo break; 895e705c121SKalle Valo case CSR_SETBIT: 896e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 897e705c121SKalle Valo break; 898e705c121SKalle Valo case CSR_CLEARBIT: 899e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 900e705c121SKalle Valo break; 901e705c121SKalle Valo case PRPH_ASSIGN: 902e705c121SKalle Valo iwl_write_prph(trans, addr, val); 903e705c121SKalle Valo break; 904e705c121SKalle Valo case PRPH_SETBIT: 905e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 906e705c121SKalle Valo break; 907e705c121SKalle Valo case PRPH_CLEARBIT: 908e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 909e705c121SKalle Valo break; 910e705c121SKalle Valo case PRPH_BLOCKBIT: 911e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 912e705c121SKalle Valo IWL_ERR(trans, 913e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 914e705c121SKalle Valo val, addr); 915e705c121SKalle Valo goto monitor; 916e705c121SKalle Valo } 917e705c121SKalle Valo break; 918e705c121SKalle Valo default: 919e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 920e705c121SKalle Valo dest->reg_ops[i].op); 921e705c121SKalle Valo break; 922e705c121SKalle Valo } 923e705c121SKalle Valo } 924e705c121SKalle Valo 925e705c121SKalle Valo monitor: 926e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 927e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 928e705c121SKalle Valo trans_pcie->fw_mon_phys >> dest->base_shift); 92962d7476dSEmmanuel Grumbach if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 930e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 931e705c121SKalle Valo (trans_pcie->fw_mon_phys + 93262d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size - 256) >> 93362d7476dSEmmanuel Grumbach dest->end_shift); 93462d7476dSEmmanuel Grumbach else 93562d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93662d7476dSEmmanuel Grumbach (trans_pcie->fw_mon_phys + 93762d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size) >> 93862d7476dSEmmanuel Grumbach dest->end_shift); 939e705c121SKalle Valo } 940e705c121SKalle Valo } 941e705c121SKalle Valo 942e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 943e705c121SKalle Valo const struct fw_img *image) 944e705c121SKalle Valo { 945e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 946e705c121SKalle Valo int ret = 0; 947e705c121SKalle Valo int first_ucode_section; 948e705c121SKalle Valo 949e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 950e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 951e705c121SKalle Valo 952e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 953e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 954e705c121SKalle Valo if (ret) 955e705c121SKalle Valo return ret; 956e705c121SKalle Valo 957e705c121SKalle Valo if (image->is_dual_cpus) { 958e705c121SKalle Valo /* set CPU2 header address */ 959e705c121SKalle Valo iwl_write_prph(trans, 960e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 961e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 962e705c121SKalle Valo 963e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 964e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 965e705c121SKalle Valo &first_ucode_section); 966e705c121SKalle Valo if (ret) 967e705c121SKalle Valo return ret; 968e705c121SKalle Valo } 969e705c121SKalle Valo 970e705c121SKalle Valo /* supported for 7000 only for the moment */ 971e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 972e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 973e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 974e705c121SKalle Valo 975e705c121SKalle Valo if (trans_pcie->fw_mon_size) { 976e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 977e705c121SKalle Valo trans_pcie->fw_mon_phys >> 4); 978e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 979e705c121SKalle Valo (trans_pcie->fw_mon_phys + 980e705c121SKalle Valo trans_pcie->fw_mon_size) >> 4); 981e705c121SKalle Valo } 982e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 983e705c121SKalle Valo iwl_pcie_apply_destination(trans); 984e705c121SKalle Valo } 985e705c121SKalle Valo 986e705c121SKalle Valo /* release CPU reset */ 987e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 988e705c121SKalle Valo 989e705c121SKalle Valo return 0; 990e705c121SKalle Valo } 991e705c121SKalle Valo 992e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 993e705c121SKalle Valo const struct fw_img *image) 994e705c121SKalle Valo { 995e705c121SKalle Valo int ret = 0; 996e705c121SKalle Valo int first_ucode_section; 997e705c121SKalle Valo 998e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 999e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1000e705c121SKalle Valo 1001e705c121SKalle Valo if (trans->dbg_dest_tlv) 1002e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1003e705c121SKalle Valo 1004e705c121SKalle Valo /* TODO: remove in the next Si step */ 1005e705c121SKalle Valo ret = iwl_pcie_rsa_race_bug_wa(trans); 1006e705c121SKalle Valo if (ret) 1007e705c121SKalle Valo return ret; 1008e705c121SKalle Valo 1009e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1010e705c121SKalle Valo /* release CPU reset */ 1011e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1012e705c121SKalle Valo 1013e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1014e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1015e705c121SKalle Valo &first_ucode_section); 1016e705c121SKalle Valo if (ret) 1017e705c121SKalle Valo return ret; 1018e705c121SKalle Valo 1019e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1020e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1021e705c121SKalle Valo &first_ucode_section); 1022e705c121SKalle Valo } 1023e705c121SKalle Valo 1024e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1025e705c121SKalle Valo { 1026e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1027e705c121SKalle Valo bool hw_rfkill, was_hw_rfkill; 1028e705c121SKalle Valo 1029e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1030e705c121SKalle Valo 1031e705c121SKalle Valo if (trans_pcie->is_down) 1032e705c121SKalle Valo return; 1033e705c121SKalle Valo 1034e705c121SKalle Valo trans_pcie->is_down = true; 1035e705c121SKalle Valo 1036e705c121SKalle Valo was_hw_rfkill = iwl_is_rfkill_set(trans); 1037e705c121SKalle Valo 1038e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1039e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1040e705c121SKalle Valo iwl_disable_interrupts(trans); 1041e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1042e705c121SKalle Valo 1043e705c121SKalle Valo /* device going down, Stop using ICT table */ 1044e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1045e705c121SKalle Valo 1046e705c121SKalle Valo /* 1047e705c121SKalle Valo * If a HW restart happens during firmware loading, 1048e705c121SKalle Valo * then the firmware loading might call this function 1049e705c121SKalle Valo * and later it might be called again due to the 1050e705c121SKalle Valo * restart. So don't process again if the device is 1051e705c121SKalle Valo * already dead. 1052e705c121SKalle Valo */ 1053e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1054a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1055a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1056e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1057e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1058e705c121SKalle Valo 1059e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1060e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1061e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1062e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1063e705c121SKalle Valo udelay(5); 1064e705c121SKalle Valo } 1065e705c121SKalle Valo } 1066e705c121SKalle Valo 1067e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1068e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1069e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1070e705c121SKalle Valo 1071e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1072e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1073e705c121SKalle Valo 1074e705c121SKalle Valo /* stop and reset the on-board processor */ 1075e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1076e705c121SKalle Valo udelay(20); 1077e705c121SKalle Valo 1078e705c121SKalle Valo /* 1079e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1080e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1081e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1082e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1083e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1084e705c121SKalle Valo */ 1085e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1086e705c121SKalle Valo iwl_disable_interrupts(trans); 1087e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1088e705c121SKalle Valo 1089e705c121SKalle Valo /* clear all status bits */ 1090e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1091e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1092e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1093e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1094e705c121SKalle Valo 1095e705c121SKalle Valo /* 1096e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1097e705c121SKalle Valo * interrupt 1098e705c121SKalle Valo */ 1099e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1100e705c121SKalle Valo 1101e705c121SKalle Valo /* 1102e705c121SKalle Valo * Check again since the RF kill state may have changed while 1103e705c121SKalle Valo * all the interrupts were disabled, in this case we couldn't 1104e705c121SKalle Valo * receive the RF kill interrupt and update the state in the 1105e705c121SKalle Valo * op_mode. 1106e705c121SKalle Valo * Don't call the op_mode if the rkfill state hasn't changed. 1107e705c121SKalle Valo * This allows the op_mode to call stop_device from the rfkill 1108e705c121SKalle Valo * notification without endless recursion. Under very rare 1109e705c121SKalle Valo * circumstances, we might have a small recursion if the rfkill 1110e705c121SKalle Valo * state changed exactly now while we were called from stop_device. 1111e705c121SKalle Valo * This is very unlikely but can happen and is supported. 1112e705c121SKalle Valo */ 1113e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1114e705c121SKalle Valo if (hw_rfkill) 1115e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1116e705c121SKalle Valo else 1117e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1118e705c121SKalle Valo if (hw_rfkill != was_hw_rfkill) 1119e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1120e705c121SKalle Valo 1121a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1122e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1123e705c121SKalle Valo } 1124e705c121SKalle Valo 1125a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1126a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1127a6bd005fSEmmanuel Grumbach { 1128a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1129a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1130a6bd005fSEmmanuel Grumbach int ret; 1131a6bd005fSEmmanuel Grumbach 1132a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1133a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1134a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1135a6bd005fSEmmanuel Grumbach ret = -EIO; 1136a6bd005fSEmmanuel Grumbach goto out; 1137a6bd005fSEmmanuel Grumbach } 1138a6bd005fSEmmanuel Grumbach 1139a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1140a6bd005fSEmmanuel Grumbach 1141a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1142a6bd005fSEmmanuel Grumbach 1143a6bd005fSEmmanuel Grumbach /* 1144a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1145a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1146a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1147a6bd005fSEmmanuel Grumbach */ 1148a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1149a6bd005fSEmmanuel Grumbach 1150a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 1151a6bd005fSEmmanuel Grumbach synchronize_irq(trans_pcie->pci_dev->irq); 1152a6bd005fSEmmanuel Grumbach 1153a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1154a6bd005fSEmmanuel Grumbach 1155a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 1156a6bd005fSEmmanuel Grumbach hw_rfkill = iwl_is_rfkill_set(trans); 1157a6bd005fSEmmanuel Grumbach if (hw_rfkill) 1158a6bd005fSEmmanuel Grumbach set_bit(STATUS_RFKILL, &trans->status); 1159a6bd005fSEmmanuel Grumbach else 1160a6bd005fSEmmanuel Grumbach clear_bit(STATUS_RFKILL, &trans->status); 1161a6bd005fSEmmanuel Grumbach iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1162a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1163a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1164a6bd005fSEmmanuel Grumbach goto out; 1165a6bd005fSEmmanuel Grumbach } 1166a6bd005fSEmmanuel Grumbach 1167a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1168a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1169a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1170a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 117120aa99bbSAnton Protopopov ret = -EIO; 1172a6bd005fSEmmanuel Grumbach goto out; 1173a6bd005fSEmmanuel Grumbach } 1174a6bd005fSEmmanuel Grumbach 1175a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1176a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1177a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1178a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1179a6bd005fSEmmanuel Grumbach 1180a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1181a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1182a6bd005fSEmmanuel Grumbach 1183a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1184a6bd005fSEmmanuel Grumbach if (ret) { 1185a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1186a6bd005fSEmmanuel Grumbach goto out; 1187a6bd005fSEmmanuel Grumbach } 1188a6bd005fSEmmanuel Grumbach 1189a6bd005fSEmmanuel Grumbach /* 1190a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1191a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1192a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1193a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1194a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1195a6bd005fSEmmanuel Grumbach */ 1196a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1197a6bd005fSEmmanuel Grumbach 1198a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1199a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1200a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1201a6bd005fSEmmanuel Grumbach 1202a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1203a6bd005fSEmmanuel Grumbach if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1204a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1205a6bd005fSEmmanuel Grumbach else 1206a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1207a6bd005fSEmmanuel Grumbach iwl_enable_interrupts(trans); 1208a6bd005fSEmmanuel Grumbach 1209a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 1210a6bd005fSEmmanuel Grumbach hw_rfkill = iwl_is_rfkill_set(trans); 1211a6bd005fSEmmanuel Grumbach if (hw_rfkill) 1212a6bd005fSEmmanuel Grumbach set_bit(STATUS_RFKILL, &trans->status); 1213a6bd005fSEmmanuel Grumbach else 1214a6bd005fSEmmanuel Grumbach clear_bit(STATUS_RFKILL, &trans->status); 1215a6bd005fSEmmanuel Grumbach 1216a6bd005fSEmmanuel Grumbach iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1217a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1218a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1219a6bd005fSEmmanuel Grumbach 1220a6bd005fSEmmanuel Grumbach out: 1221a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1222a6bd005fSEmmanuel Grumbach return ret; 1223a6bd005fSEmmanuel Grumbach } 1224a6bd005fSEmmanuel Grumbach 1225a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1226a6bd005fSEmmanuel Grumbach { 1227a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1228a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1229a6bd005fSEmmanuel Grumbach } 1230a6bd005fSEmmanuel Grumbach 1231e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1232e705c121SKalle Valo { 1233e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1234e705c121SKalle Valo 1235e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1236e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1237e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1238e705c121SKalle Valo } 1239e705c121SKalle Valo 1240e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1241e705c121SKalle Valo { 1242e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1243e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1244e705c121SKalle Valo 1245e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1246e705c121SKalle Valo 1247e705c121SKalle Valo if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1248e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1249e705c121SKalle Valo } 1250e705c121SKalle Valo 1251e705c121SKalle Valo static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test) 1252e705c121SKalle Valo { 1253e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1254e705c121SKalle Valo 1255b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) { 1256e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1257e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1258e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1259e705c121SKalle Valo } 1260e705c121SKalle Valo 1261e705c121SKalle Valo iwl_disable_interrupts(trans); 1262e705c121SKalle Valo 1263e705c121SKalle Valo /* 1264e705c121SKalle Valo * in testing mode, the host stays awake and the 1265e705c121SKalle Valo * hardware won't be reset (not even partially) 1266e705c121SKalle Valo */ 1267e705c121SKalle Valo if (test) 1268e705c121SKalle Valo return; 1269e705c121SKalle Valo 1270e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1271e705c121SKalle Valo 1272e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1273e705c121SKalle Valo 1274e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1275e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1276e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1277e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1278e705c121SKalle Valo 1279b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D3) { 1280e705c121SKalle Valo /* 1281e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1282e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1283e705c121SKalle Valo * to execute some invalid memory upon resume 1284e705c121SKalle Valo */ 1285e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1286e705c121SKalle Valo } 1287e705c121SKalle Valo 1288e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1289e705c121SKalle Valo } 1290e705c121SKalle Valo 1291e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1292e705c121SKalle Valo enum iwl_d3_status *status, 1293e705c121SKalle Valo bool test) 1294e705c121SKalle Valo { 1295e705c121SKalle Valo u32 val; 1296e705c121SKalle Valo int ret; 1297e705c121SKalle Valo 1298e705c121SKalle Valo if (test) { 1299e705c121SKalle Valo iwl_enable_interrupts(trans); 1300e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1301e705c121SKalle Valo return 0; 1302e705c121SKalle Valo } 1303e705c121SKalle Valo 1304e705c121SKalle Valo /* 1305e705c121SKalle Valo * Also enables interrupts - none will happen as the device doesn't 1306e705c121SKalle Valo * know we're waking it up, only when the opmode actually tells it 1307e705c121SKalle Valo * after this call. 1308e705c121SKalle Valo */ 1309e705c121SKalle Valo iwl_pcie_reset_ict(trans); 1310e705c121SKalle Valo 1311e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1312e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1313e705c121SKalle Valo 1314e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1315e705c121SKalle Valo udelay(2); 1316e705c121SKalle Valo 1317e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1318e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1319e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1320e705c121SKalle Valo 25000); 1321e705c121SKalle Valo if (ret < 0) { 1322e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1323e705c121SKalle Valo return ret; 1324e705c121SKalle Valo } 1325e705c121SKalle Valo 1326e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1327e705c121SKalle Valo 1328b7282643SLuca Coelho if (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3) { 1329e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1330e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1331e705c121SKalle Valo } else { 1332e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1333e705c121SKalle Valo 1334e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1335e705c121SKalle Valo if (ret) { 1336e705c121SKalle Valo IWL_ERR(trans, 1337e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1338e705c121SKalle Valo return ret; 1339e705c121SKalle Valo } 1340e705c121SKalle Valo } 1341e705c121SKalle Valo 1342e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1343e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1344e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1345e705c121SKalle Valo else 1346e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1347e705c121SKalle Valo 1348e705c121SKalle Valo return 0; 1349e705c121SKalle Valo } 1350e705c121SKalle Valo 1351e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1352e705c121SKalle Valo { 1353e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1354e705c121SKalle Valo bool hw_rfkill; 1355e705c121SKalle Valo int err; 1356e705c121SKalle Valo 1357e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1358e705c121SKalle Valo 1359e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1360e705c121SKalle Valo if (err) { 1361e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1362e705c121SKalle Valo return err; 1363e705c121SKalle Valo } 1364e705c121SKalle Valo 1365e705c121SKalle Valo /* Reset the entire device */ 1366e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1367e705c121SKalle Valo 1368e705c121SKalle Valo usleep_range(10, 15); 1369e705c121SKalle Valo 1370e705c121SKalle Valo iwl_pcie_apm_init(trans); 1371e705c121SKalle Valo 1372e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1373e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1374e705c121SKalle Valo 1375e705c121SKalle Valo /* Set is_down to false here so that...*/ 1376e705c121SKalle Valo trans_pcie->is_down = false; 1377e705c121SKalle Valo 1378e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1379e705c121SKalle Valo if (hw_rfkill) 1380e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1381e705c121SKalle Valo else 1382e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1383e705c121SKalle Valo /* ... rfkill can call stop_device and set it false if needed */ 1384e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1385e705c121SKalle Valo 1386e705c121SKalle Valo return 0; 1387e705c121SKalle Valo } 1388e705c121SKalle Valo 1389e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1390e705c121SKalle Valo { 1391e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1392e705c121SKalle Valo int ret; 1393e705c121SKalle Valo 1394e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1395e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1396e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1397e705c121SKalle Valo 1398e705c121SKalle Valo return ret; 1399e705c121SKalle Valo } 1400e705c121SKalle Valo 1401e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1402e705c121SKalle Valo { 1403e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1404e705c121SKalle Valo 1405e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1406e705c121SKalle Valo 1407e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1408e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1409e705c121SKalle Valo iwl_disable_interrupts(trans); 1410e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1411e705c121SKalle Valo 1412e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1413e705c121SKalle Valo 1414e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1415e705c121SKalle Valo iwl_disable_interrupts(trans); 1416e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1417e705c121SKalle Valo 1418e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1419e705c121SKalle Valo 1420e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1421e705c121SKalle Valo 1422e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1423e705c121SKalle Valo } 1424e705c121SKalle Valo 1425e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1426e705c121SKalle Valo { 1427e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1428e705c121SKalle Valo } 1429e705c121SKalle Valo 1430e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1431e705c121SKalle Valo { 1432e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1433e705c121SKalle Valo } 1434e705c121SKalle Valo 1435e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1436e705c121SKalle Valo { 1437e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1438e705c121SKalle Valo } 1439e705c121SKalle Valo 1440e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1441e705c121SKalle Valo { 1442e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1443e705c121SKalle Valo ((reg & 0x000FFFFF) | (3 << 24))); 1444e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1445e705c121SKalle Valo } 1446e705c121SKalle Valo 1447e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1448e705c121SKalle Valo u32 val) 1449e705c121SKalle Valo { 1450e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1451e705c121SKalle Valo ((addr & 0x000FFFFF) | (3 << 24))); 1452e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1453e705c121SKalle Valo } 1454e705c121SKalle Valo 1455e705c121SKalle Valo static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget) 1456e705c121SKalle Valo { 1457e705c121SKalle Valo WARN_ON(1); 1458e705c121SKalle Valo return 0; 1459e705c121SKalle Valo } 1460e705c121SKalle Valo 1461e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1462e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1463e705c121SKalle Valo { 1464e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1465e705c121SKalle Valo 1466e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1467e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1468e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1469e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1470e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1471e705c121SKalle Valo else 1472e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1473e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1474e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1475e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1476e705c121SKalle Valo 14776c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 14786c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 14796c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1480e705c121SKalle Valo 1481e705c121SKalle Valo trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; 1482e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1483e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 148441837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1485e705c121SKalle Valo 148639bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 148739bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 148839bdb17eSSharon Dvir 1489e705c121SKalle Valo /* init ref_count to 1 (should be cleared when ucode is loaded) */ 1490e705c121SKalle Valo trans_pcie->ref_count = 1; 1491e705c121SKalle Valo 1492e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1493e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1494e705c121SKalle Valo * As this function may be called again in some corner cases don't 1495e705c121SKalle Valo * do anything if NAPI was already initialized. 1496e705c121SKalle Valo */ 1497e705c121SKalle Valo if (!trans_pcie->napi.poll) { 1498e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1499e705c121SKalle Valo netif_napi_add(&trans_pcie->napi_dev, &trans_pcie->napi, 1500e705c121SKalle Valo iwl_pcie_dummy_napi_poll, 64); 1501e705c121SKalle Valo } 1502e705c121SKalle Valo } 1503e705c121SKalle Valo 1504e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1505e705c121SKalle Valo { 1506e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 15076eb5e529SEmmanuel Grumbach int i; 1508e705c121SKalle Valo 1509e705c121SKalle Valo synchronize_irq(trans_pcie->pci_dev->irq); 1510e705c121SKalle Valo 1511e705c121SKalle Valo iwl_pcie_tx_free(trans); 1512e705c121SKalle Valo iwl_pcie_rx_free(trans); 1513e705c121SKalle Valo 1514e705c121SKalle Valo free_irq(trans_pcie->pci_dev->irq, trans); 1515e705c121SKalle Valo iwl_pcie_free_ict(trans); 1516e705c121SKalle Valo 1517e705c121SKalle Valo pci_disable_msi(trans_pcie->pci_dev); 1518e705c121SKalle Valo iounmap(trans_pcie->hw_base); 1519e705c121SKalle Valo pci_release_regions(trans_pcie->pci_dev); 1520e705c121SKalle Valo pci_disable_device(trans_pcie->pci_dev); 1521e705c121SKalle Valo 1522e705c121SKalle Valo if (trans_pcie->napi.poll) 1523e705c121SKalle Valo netif_napi_del(&trans_pcie->napi); 1524e705c121SKalle Valo 1525e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1526e705c121SKalle Valo 15276eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 15286eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 15296eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 15306eb5e529SEmmanuel Grumbach 15316eb5e529SEmmanuel Grumbach if (p->page) 15326eb5e529SEmmanuel Grumbach __free_page(p->page); 15336eb5e529SEmmanuel Grumbach } 15346eb5e529SEmmanuel Grumbach 15356eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1536e705c121SKalle Valo iwl_trans_free(trans); 1537e705c121SKalle Valo } 1538e705c121SKalle Valo 1539e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1540e705c121SKalle Valo { 1541e705c121SKalle Valo if (state) 1542e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1543e705c121SKalle Valo else 1544e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1545e705c121SKalle Valo } 1546e705c121SKalle Valo 154723ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1548e705c121SKalle Valo unsigned long *flags) 1549e705c121SKalle Valo { 1550e705c121SKalle Valo int ret; 1551e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1552e705c121SKalle Valo 1553e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1554e705c121SKalle Valo 1555e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1556e705c121SKalle Valo goto out; 1557e705c121SKalle Valo 1558e705c121SKalle Valo /* this bit wakes up the NIC */ 1559e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1560e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1561e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1562e705c121SKalle Valo udelay(2); 1563e705c121SKalle Valo 1564e705c121SKalle Valo /* 1565e705c121SKalle Valo * These bits say the device is running, and should keep running for 1566e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1567e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1568e705c121SKalle Valo * 3945 and 4965 have volatile SRAM, and must save/restore contents 1569e705c121SKalle Valo * to/from host DRAM when sleeping/waking for power-saving. 1570e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1571e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1572e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1573e705c121SKalle Valo * to keep device from sleeping. 1574e705c121SKalle Valo * 1575e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1576e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1577e705c121SKalle Valo * is just for hardware register access; but GP1 MAC_SLEEP check is a 1578e705c121SKalle Valo * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1579e705c121SKalle Valo * 1580e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1581e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1582e705c121SKalle Valo */ 1583e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1584e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1585e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1586e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1587e705c121SKalle Valo if (unlikely(ret < 0)) { 1588e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1589e705c121SKalle Valo WARN_ONCE(1, 1590e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 159123ba9340SEmmanuel Grumbach iwl_read32(trans, CSR_GP_CNTRL)); 1592e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1593e705c121SKalle Valo return false; 1594e705c121SKalle Valo } 1595e705c121SKalle Valo 1596e705c121SKalle Valo out: 1597e705c121SKalle Valo /* 1598e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 1599e705c121SKalle Valo * track nic_access anyway. 1600e705c121SKalle Valo */ 1601e705c121SKalle Valo __release(&trans_pcie->reg_lock); 1602e705c121SKalle Valo return true; 1603e705c121SKalle Valo } 1604e705c121SKalle Valo 1605e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1606e705c121SKalle Valo unsigned long *flags) 1607e705c121SKalle Valo { 1608e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1609e705c121SKalle Valo 1610e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1611e705c121SKalle Valo 1612e705c121SKalle Valo /* 1613e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 1614e705c121SKalle Valo * track nic_access anyway. 1615e705c121SKalle Valo */ 1616e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 1617e705c121SKalle Valo 1618e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1619e705c121SKalle Valo goto out; 1620e705c121SKalle Valo 1621e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1622e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1623e705c121SKalle Valo /* 1624e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 1625e705c121SKalle Valo * any previous writes, but we need the write that clears the 1626e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 1627e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 1628e705c121SKalle Valo */ 1629e705c121SKalle Valo mmiowb(); 1630e705c121SKalle Valo out: 1631e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1632e705c121SKalle Valo } 1633e705c121SKalle Valo 1634e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1635e705c121SKalle Valo void *buf, int dwords) 1636e705c121SKalle Valo { 1637e705c121SKalle Valo unsigned long flags; 1638e705c121SKalle Valo int offs, ret = 0; 1639e705c121SKalle Valo u32 *vals = buf; 1640e705c121SKalle Valo 164123ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1642e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1643e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1644e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1645e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1646e705c121SKalle Valo } else { 1647e705c121SKalle Valo ret = -EBUSY; 1648e705c121SKalle Valo } 1649e705c121SKalle Valo return ret; 1650e705c121SKalle Valo } 1651e705c121SKalle Valo 1652e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1653e705c121SKalle Valo const void *buf, int dwords) 1654e705c121SKalle Valo { 1655e705c121SKalle Valo unsigned long flags; 1656e705c121SKalle Valo int offs, ret = 0; 1657e705c121SKalle Valo const u32 *vals = buf; 1658e705c121SKalle Valo 165923ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1660e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1661e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1662e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1663e705c121SKalle Valo vals ? vals[offs] : 0); 1664e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1665e705c121SKalle Valo } else { 1666e705c121SKalle Valo ret = -EBUSY; 1667e705c121SKalle Valo } 1668e705c121SKalle Valo return ret; 1669e705c121SKalle Valo } 1670e705c121SKalle Valo 1671e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1672e705c121SKalle Valo unsigned long txqs, 1673e705c121SKalle Valo bool freeze) 1674e705c121SKalle Valo { 1675e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1676e705c121SKalle Valo int queue; 1677e705c121SKalle Valo 1678e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1679e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[queue]; 1680e705c121SKalle Valo unsigned long now; 1681e705c121SKalle Valo 1682e705c121SKalle Valo spin_lock_bh(&txq->lock); 1683e705c121SKalle Valo 1684e705c121SKalle Valo now = jiffies; 1685e705c121SKalle Valo 1686e705c121SKalle Valo if (txq->frozen == freeze) 1687e705c121SKalle Valo goto next_queue; 1688e705c121SKalle Valo 1689e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1690e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 1691e705c121SKalle Valo 1692e705c121SKalle Valo txq->frozen = freeze; 1693e705c121SKalle Valo 1694e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) 1695e705c121SKalle Valo goto next_queue; 1696e705c121SKalle Valo 1697e705c121SKalle Valo if (freeze) { 1698e705c121SKalle Valo if (unlikely(time_after(now, 1699e705c121SKalle Valo txq->stuck_timer.expires))) { 1700e705c121SKalle Valo /* 1701e705c121SKalle Valo * The timer should have fired, maybe it is 1702e705c121SKalle Valo * spinning right now on the lock. 1703e705c121SKalle Valo */ 1704e705c121SKalle Valo goto next_queue; 1705e705c121SKalle Valo } 1706e705c121SKalle Valo /* remember how long until the timer fires */ 1707e705c121SKalle Valo txq->frozen_expiry_remainder = 1708e705c121SKalle Valo txq->stuck_timer.expires - now; 1709e705c121SKalle Valo del_timer(&txq->stuck_timer); 1710e705c121SKalle Valo goto next_queue; 1711e705c121SKalle Valo } 1712e705c121SKalle Valo 1713e705c121SKalle Valo /* 1714e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 1715e705c121SKalle Valo * remainder before it froze 1716e705c121SKalle Valo */ 1717e705c121SKalle Valo mod_timer(&txq->stuck_timer, 1718e705c121SKalle Valo now + txq->frozen_expiry_remainder); 1719e705c121SKalle Valo 1720e705c121SKalle Valo next_queue: 1721e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1722e705c121SKalle Valo } 1723e705c121SKalle Valo } 1724e705c121SKalle Valo 17250cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 17260cd58eaaSEmmanuel Grumbach { 17270cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 17280cd58eaaSEmmanuel Grumbach int i; 17290cd58eaaSEmmanuel Grumbach 17300cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 17310cd58eaaSEmmanuel Grumbach struct iwl_txq *txq = &trans_pcie->txq[i]; 17320cd58eaaSEmmanuel Grumbach 17330cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 17340cd58eaaSEmmanuel Grumbach continue; 17350cd58eaaSEmmanuel Grumbach 17360cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 17370cd58eaaSEmmanuel Grumbach 17380cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 17390cd58eaaSEmmanuel Grumbach txq->block--; 17400cd58eaaSEmmanuel Grumbach if (!txq->block) { 17410cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 17420cd58eaaSEmmanuel Grumbach txq->q.write_ptr | (i << 8)); 17430cd58eaaSEmmanuel Grumbach } 17440cd58eaaSEmmanuel Grumbach } else if (block) { 17450cd58eaaSEmmanuel Grumbach txq->block++; 17460cd58eaaSEmmanuel Grumbach } 17470cd58eaaSEmmanuel Grumbach 17480cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 17490cd58eaaSEmmanuel Grumbach } 17500cd58eaaSEmmanuel Grumbach } 17510cd58eaaSEmmanuel Grumbach 1752e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 1753e705c121SKalle Valo 1754e705c121SKalle Valo static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 1755e705c121SKalle Valo { 1756e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1757e705c121SKalle Valo struct iwl_txq *txq; 1758e705c121SKalle Valo struct iwl_queue *q; 1759e705c121SKalle Valo int cnt; 1760e705c121SKalle Valo unsigned long now = jiffies; 1761e705c121SKalle Valo u32 scd_sram_addr; 1762e705c121SKalle Valo u8 buf[16]; 1763e705c121SKalle Valo int ret = 0; 1764e705c121SKalle Valo 1765e705c121SKalle Valo /* waiting for all the tx frames complete might take a while */ 1766e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1767e705c121SKalle Valo u8 wr_ptr; 1768e705c121SKalle Valo 1769e705c121SKalle Valo if (cnt == trans_pcie->cmd_queue) 1770e705c121SKalle Valo continue; 1771e705c121SKalle Valo if (!test_bit(cnt, trans_pcie->queue_used)) 1772e705c121SKalle Valo continue; 1773e705c121SKalle Valo if (!(BIT(cnt) & txq_bm)) 1774e705c121SKalle Valo continue; 1775e705c121SKalle Valo 1776e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 1777e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 1778e705c121SKalle Valo q = &txq->q; 1779e705c121SKalle Valo wr_ptr = ACCESS_ONCE(q->write_ptr); 1780e705c121SKalle Valo 1781e705c121SKalle Valo while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && 1782e705c121SKalle Valo !time_after(jiffies, 1783e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 1784e705c121SKalle Valo u8 write_ptr = ACCESS_ONCE(q->write_ptr); 1785e705c121SKalle Valo 1786e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 1787e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 1788e705c121SKalle Valo wr_ptr, write_ptr)) 1789e705c121SKalle Valo return -ETIMEDOUT; 1790e705c121SKalle Valo msleep(1); 1791e705c121SKalle Valo } 1792e705c121SKalle Valo 1793e705c121SKalle Valo if (q->read_ptr != q->write_ptr) { 1794e705c121SKalle Valo IWL_ERR(trans, 1795e705c121SKalle Valo "fail to flush all tx fifo queues Q %d\n", cnt); 1796e705c121SKalle Valo ret = -ETIMEDOUT; 1797e705c121SKalle Valo break; 1798e705c121SKalle Valo } 1799e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 1800e705c121SKalle Valo } 1801e705c121SKalle Valo 1802e705c121SKalle Valo if (!ret) 1803e705c121SKalle Valo return 0; 1804e705c121SKalle Valo 1805e705c121SKalle Valo IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1806e705c121SKalle Valo txq->q.read_ptr, txq->q.write_ptr); 1807e705c121SKalle Valo 1808e705c121SKalle Valo scd_sram_addr = trans_pcie->scd_base_addr + 1809e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 1810e705c121SKalle Valo iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 1811e705c121SKalle Valo 1812e705c121SKalle Valo iwl_print_hex_error(trans, buf, sizeof(buf)); 1813e705c121SKalle Valo 1814e705c121SKalle Valo for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 1815e705c121SKalle Valo IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 1816e705c121SKalle Valo iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 1817e705c121SKalle Valo 1818e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1819e705c121SKalle Valo u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 1820e705c121SKalle Valo u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 1821e705c121SKalle Valo bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 1822e705c121SKalle Valo u32 tbl_dw = 1823e705c121SKalle Valo iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 1824e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 1825e705c121SKalle Valo 1826e705c121SKalle Valo if (cnt & 0x1) 1827e705c121SKalle Valo tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 1828e705c121SKalle Valo else 1829e705c121SKalle Valo tbl_dw = tbl_dw & 0x0000FFFF; 1830e705c121SKalle Valo 1831e705c121SKalle Valo IWL_ERR(trans, 1832e705c121SKalle Valo "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 1833e705c121SKalle Valo cnt, active ? "" : "in", fifo, tbl_dw, 1834e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 1835e705c121SKalle Valo (TFD_QUEUE_SIZE_MAX - 1), 1836e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 1837e705c121SKalle Valo } 1838e705c121SKalle Valo 1839e705c121SKalle Valo return ret; 1840e705c121SKalle Valo } 1841e705c121SKalle Valo 1842e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 1843e705c121SKalle Valo u32 mask, u32 value) 1844e705c121SKalle Valo { 1845e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1846e705c121SKalle Valo unsigned long flags; 1847e705c121SKalle Valo 1848e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 1849e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 1850e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 1851e705c121SKalle Valo } 1852e705c121SKalle Valo 1853e705c121SKalle Valo void iwl_trans_pcie_ref(struct iwl_trans *trans) 1854e705c121SKalle Valo { 1855e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1856e705c121SKalle Valo unsigned long flags; 1857e705c121SKalle Valo 1858e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 1859e705c121SKalle Valo return; 1860e705c121SKalle Valo 1861e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->ref_lock, flags); 1862e705c121SKalle Valo IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); 1863e705c121SKalle Valo trans_pcie->ref_count++; 1864e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1865e705c121SKalle Valo } 1866e705c121SKalle Valo 1867e705c121SKalle Valo void iwl_trans_pcie_unref(struct iwl_trans *trans) 1868e705c121SKalle Valo { 1869e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1870e705c121SKalle Valo unsigned long flags; 1871e705c121SKalle Valo 1872e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 1873e705c121SKalle Valo return; 1874e705c121SKalle Valo 1875e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->ref_lock, flags); 1876e705c121SKalle Valo IWL_DEBUG_RPM(trans, "ref_counter: %d\n", trans_pcie->ref_count); 1877e705c121SKalle Valo if (WARN_ON_ONCE(trans_pcie->ref_count == 0)) { 1878e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1879e705c121SKalle Valo return; 1880e705c121SKalle Valo } 1881e705c121SKalle Valo trans_pcie->ref_count--; 1882e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->ref_lock, flags); 1883e705c121SKalle Valo } 1884e705c121SKalle Valo 1885e705c121SKalle Valo static const char *get_csr_string(int cmd) 1886e705c121SKalle Valo { 1887e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 1888e705c121SKalle Valo switch (cmd) { 1889e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 1890e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 1891e705c121SKalle Valo IWL_CMD(CSR_INT); 1892e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 1893e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 1894e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 1895e705c121SKalle Valo IWL_CMD(CSR_RESET); 1896e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 1897e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 1898e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 1899e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 1900e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 1901e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 1902e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 1903e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 1904e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 1905e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 1906e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 1907e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 1908e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 1909e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 1910e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 1911e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 1912e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 1913e705c121SKalle Valo default: 1914e705c121SKalle Valo return "UNKNOWN"; 1915e705c121SKalle Valo } 1916e705c121SKalle Valo #undef IWL_CMD 1917e705c121SKalle Valo } 1918e705c121SKalle Valo 1919e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 1920e705c121SKalle Valo { 1921e705c121SKalle Valo int i; 1922e705c121SKalle Valo static const u32 csr_tbl[] = { 1923e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 1924e705c121SKalle Valo CSR_INT_COALESCING, 1925e705c121SKalle Valo CSR_INT, 1926e705c121SKalle Valo CSR_INT_MASK, 1927e705c121SKalle Valo CSR_FH_INT_STATUS, 1928e705c121SKalle Valo CSR_GPIO_IN, 1929e705c121SKalle Valo CSR_RESET, 1930e705c121SKalle Valo CSR_GP_CNTRL, 1931e705c121SKalle Valo CSR_HW_REV, 1932e705c121SKalle Valo CSR_EEPROM_REG, 1933e705c121SKalle Valo CSR_EEPROM_GP, 1934e705c121SKalle Valo CSR_OTP_GP_REG, 1935e705c121SKalle Valo CSR_GIO_REG, 1936e705c121SKalle Valo CSR_GP_UCODE_REG, 1937e705c121SKalle Valo CSR_GP_DRIVER_REG, 1938e705c121SKalle Valo CSR_UCODE_DRV_GP1, 1939e705c121SKalle Valo CSR_UCODE_DRV_GP2, 1940e705c121SKalle Valo CSR_LED_REG, 1941e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 1942e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 1943e705c121SKalle Valo CSR_ANA_PLL_CFG, 1944e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 1945e705c121SKalle Valo CSR_HW_REV_WA_REG, 1946e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 1947e705c121SKalle Valo }; 1948e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 1949e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 1950e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 1951e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 1952e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 1953e705c121SKalle Valo get_csr_string(csr_tbl[i]), 1954e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 1955e705c121SKalle Valo } 1956e705c121SKalle Valo } 1957e705c121SKalle Valo 1958e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 1959e705c121SKalle Valo /* create and remove of files */ 1960e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 1961e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 1962e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 1963e705c121SKalle Valo goto err; \ 1964e705c121SKalle Valo } while (0) 1965e705c121SKalle Valo 1966e705c121SKalle Valo /* file operation */ 1967e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 1968e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1969e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 1970e705c121SKalle Valo .open = simple_open, \ 1971e705c121SKalle Valo .llseek = generic_file_llseek, \ 1972e705c121SKalle Valo }; 1973e705c121SKalle Valo 1974e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 1975e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1976e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 1977e705c121SKalle Valo .open = simple_open, \ 1978e705c121SKalle Valo .llseek = generic_file_llseek, \ 1979e705c121SKalle Valo }; 1980e705c121SKalle Valo 1981e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 1982e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 1983e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 1984e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 1985e705c121SKalle Valo .open = simple_open, \ 1986e705c121SKalle Valo .llseek = generic_file_llseek, \ 1987e705c121SKalle Valo }; 1988e705c121SKalle Valo 1989e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 1990e705c121SKalle Valo char __user *user_buf, 1991e705c121SKalle Valo size_t count, loff_t *ppos) 1992e705c121SKalle Valo { 1993e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 1994e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1995e705c121SKalle Valo struct iwl_txq *txq; 1996e705c121SKalle Valo struct iwl_queue *q; 1997e705c121SKalle Valo char *buf; 1998e705c121SKalle Valo int pos = 0; 1999e705c121SKalle Valo int cnt; 2000e705c121SKalle Valo int ret; 2001e705c121SKalle Valo size_t bufsz; 2002e705c121SKalle Valo 2003e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2004e705c121SKalle Valo 2005e705c121SKalle Valo if (!trans_pcie->txq) 2006e705c121SKalle Valo return -EAGAIN; 2007e705c121SKalle Valo 2008e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2009e705c121SKalle Valo if (!buf) 2010e705c121SKalle Valo return -ENOMEM; 2011e705c121SKalle Valo 2012e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2013e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 2014e705c121SKalle Valo q = &txq->q; 2015e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2016e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2017e705c121SKalle Valo cnt, q->read_ptr, q->write_ptr, 2018e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2019e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2020e705c121SKalle Valo txq->need_update, txq->frozen, 2021e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2022e705c121SKalle Valo } 2023e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2024e705c121SKalle Valo kfree(buf); 2025e705c121SKalle Valo return ret; 2026e705c121SKalle Valo } 2027e705c121SKalle Valo 2028e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2029e705c121SKalle Valo char __user *user_buf, 2030e705c121SKalle Valo size_t count, loff_t *ppos) 2031e705c121SKalle Valo { 2032e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2033e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2034e705c121SKalle Valo struct iwl_rxq *rxq = &trans_pcie->rxq; 2035e705c121SKalle Valo char buf[256]; 2036e705c121SKalle Valo int pos = 0; 2037e705c121SKalle Valo const size_t bufsz = sizeof(buf); 2038e705c121SKalle Valo 2039e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n", 2040e705c121SKalle Valo rxq->read); 2041e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n", 2042e705c121SKalle Valo rxq->write); 2043e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "write_actual: %u\n", 2044e705c121SKalle Valo rxq->write_actual); 2045e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "need_update: %d\n", 2046e705c121SKalle Valo rxq->need_update); 2047e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n", 2048e705c121SKalle Valo rxq->free_count); 2049e705c121SKalle Valo if (rxq->rb_stts) { 2050e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n", 2051e705c121SKalle Valo le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF); 2052e705c121SKalle Valo } else { 2053e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2054e705c121SKalle Valo "closed_rb_num: Not Allocated\n"); 2055e705c121SKalle Valo } 2056e705c121SKalle Valo return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2057e705c121SKalle Valo } 2058e705c121SKalle Valo 2059e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2060e705c121SKalle Valo char __user *user_buf, 2061e705c121SKalle Valo size_t count, loff_t *ppos) 2062e705c121SKalle Valo { 2063e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2064e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2065e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2066e705c121SKalle Valo 2067e705c121SKalle Valo int pos = 0; 2068e705c121SKalle Valo char *buf; 2069e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2070e705c121SKalle Valo ssize_t ret; 2071e705c121SKalle Valo 2072e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2073e705c121SKalle Valo if (!buf) 2074e705c121SKalle Valo return -ENOMEM; 2075e705c121SKalle Valo 2076e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2077e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2078e705c121SKalle Valo 2079e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2080e705c121SKalle Valo isr_stats->hw); 2081e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2082e705c121SKalle Valo isr_stats->sw); 2083e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2084e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2085e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2086e705c121SKalle Valo isr_stats->err_code); 2087e705c121SKalle Valo } 2088e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2089e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2090e705c121SKalle Valo isr_stats->sch); 2091e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2092e705c121SKalle Valo isr_stats->alive); 2093e705c121SKalle Valo #endif 2094e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2095e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2096e705c121SKalle Valo 2097e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2098e705c121SKalle Valo isr_stats->ctkill); 2099e705c121SKalle Valo 2100e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2101e705c121SKalle Valo isr_stats->wakeup); 2102e705c121SKalle Valo 2103e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2104e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2105e705c121SKalle Valo 2106e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2107e705c121SKalle Valo isr_stats->tx); 2108e705c121SKalle Valo 2109e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2110e705c121SKalle Valo isr_stats->unhandled); 2111e705c121SKalle Valo 2112e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2113e705c121SKalle Valo kfree(buf); 2114e705c121SKalle Valo return ret; 2115e705c121SKalle Valo } 2116e705c121SKalle Valo 2117e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2118e705c121SKalle Valo const char __user *user_buf, 2119e705c121SKalle Valo size_t count, loff_t *ppos) 2120e705c121SKalle Valo { 2121e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2122e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2123e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2124e705c121SKalle Valo 2125e705c121SKalle Valo char buf[8]; 2126e705c121SKalle Valo int buf_size; 2127e705c121SKalle Valo u32 reset_flag; 2128e705c121SKalle Valo 2129e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2130e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2131e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2132e705c121SKalle Valo return -EFAULT; 2133e705c121SKalle Valo if (sscanf(buf, "%x", &reset_flag) != 1) 2134e705c121SKalle Valo return -EFAULT; 2135e705c121SKalle Valo if (reset_flag == 0) 2136e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2137e705c121SKalle Valo 2138e705c121SKalle Valo return count; 2139e705c121SKalle Valo } 2140e705c121SKalle Valo 2141e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2142e705c121SKalle Valo const char __user *user_buf, 2143e705c121SKalle Valo size_t count, loff_t *ppos) 2144e705c121SKalle Valo { 2145e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2146e705c121SKalle Valo char buf[8]; 2147e705c121SKalle Valo int buf_size; 2148e705c121SKalle Valo int csr; 2149e705c121SKalle Valo 2150e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2151e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2152e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2153e705c121SKalle Valo return -EFAULT; 2154e705c121SKalle Valo if (sscanf(buf, "%d", &csr) != 1) 2155e705c121SKalle Valo return -EFAULT; 2156e705c121SKalle Valo 2157e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2158e705c121SKalle Valo 2159e705c121SKalle Valo return count; 2160e705c121SKalle Valo } 2161e705c121SKalle Valo 2162e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2163e705c121SKalle Valo char __user *user_buf, 2164e705c121SKalle Valo size_t count, loff_t *ppos) 2165e705c121SKalle Valo { 2166e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2167e705c121SKalle Valo char *buf = NULL; 2168e705c121SKalle Valo ssize_t ret; 2169e705c121SKalle Valo 2170e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2171e705c121SKalle Valo if (ret < 0) 2172e705c121SKalle Valo return ret; 2173e705c121SKalle Valo if (!buf) 2174e705c121SKalle Valo return -EINVAL; 2175e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2176e705c121SKalle Valo kfree(buf); 2177e705c121SKalle Valo return ret; 2178e705c121SKalle Valo } 2179e705c121SKalle Valo 2180e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2181e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2182e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2183e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2184e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2185e705c121SKalle Valo 2186f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2187f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2188e705c121SKalle Valo { 2189f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2190f8a1edb7SJohannes Berg 2191e705c121SKalle Valo DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2192e705c121SKalle Valo DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2193e705c121SKalle Valo DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2194e705c121SKalle Valo DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2195e705c121SKalle Valo DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2196e705c121SKalle Valo return 0; 2197e705c121SKalle Valo 2198e705c121SKalle Valo err: 2199e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2200e705c121SKalle Valo return -ENOMEM; 2201e705c121SKalle Valo } 2202e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2203e705c121SKalle Valo 2204e705c121SKalle Valo static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) 2205e705c121SKalle Valo { 2206e705c121SKalle Valo u32 cmdlen = 0; 2207e705c121SKalle Valo int i; 2208e705c121SKalle Valo 2209e705c121SKalle Valo for (i = 0; i < IWL_NUM_OF_TBS; i++) 2210e705c121SKalle Valo cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); 2211e705c121SKalle Valo 2212e705c121SKalle Valo return cmdlen; 2213e705c121SKalle Valo } 2214e705c121SKalle Valo 2215e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2216e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2217e705c121SKalle Valo int allocated_rb_nums) 2218e705c121SKalle Valo { 2219e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2220e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 2221e705c121SKalle Valo struct iwl_rxq *rxq = &trans_pcie->rxq; 2222e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2223e705c121SKalle Valo 2224e705c121SKalle Valo spin_lock(&rxq->lock); 2225e705c121SKalle Valo 2226e705c121SKalle Valo r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2227e705c121SKalle Valo 2228e705c121SKalle Valo for (i = rxq->read, j = 0; 2229e705c121SKalle Valo i != r && j < allocated_rb_nums; 2230e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2231e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2232e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2233e705c121SKalle Valo 2234e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2235e705c121SKalle Valo DMA_FROM_DEVICE); 2236e705c121SKalle Valo 2237e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2238e705c121SKalle Valo 2239e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2240e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2241e705c121SKalle Valo rb = (void *)(*data)->data; 2242e705c121SKalle Valo rb->index = cpu_to_le32(i); 2243e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2244e705c121SKalle Valo /* remap the page for the free benefit */ 2245e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2246e705c121SKalle Valo max_len, 2247e705c121SKalle Valo DMA_FROM_DEVICE); 2248e705c121SKalle Valo 2249e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2250e705c121SKalle Valo } 2251e705c121SKalle Valo 2252e705c121SKalle Valo spin_unlock(&rxq->lock); 2253e705c121SKalle Valo 2254e705c121SKalle Valo return rb_len; 2255e705c121SKalle Valo } 2256e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2257e705c121SKalle Valo 2258e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2259e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2260e705c121SKalle Valo { 2261e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2262e705c121SKalle Valo __le32 *val; 2263e705c121SKalle Valo int i; 2264e705c121SKalle Valo 2265e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2266e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2267e705c121SKalle Valo val = (void *)(*data)->data; 2268e705c121SKalle Valo 2269e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2270e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2271e705c121SKalle Valo 2272e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2273e705c121SKalle Valo 2274e705c121SKalle Valo return csr_len; 2275e705c121SKalle Valo } 2276e705c121SKalle Valo 2277e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2278e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2279e705c121SKalle Valo { 2280e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2281e705c121SKalle Valo unsigned long flags; 2282e705c121SKalle Valo __le32 *val; 2283e705c121SKalle Valo int i; 2284e705c121SKalle Valo 228523ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2286e705c121SKalle Valo return 0; 2287e705c121SKalle Valo 2288e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2289e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2290e705c121SKalle Valo val = (void *)(*data)->data; 2291e705c121SKalle Valo 2292e705c121SKalle Valo for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2293e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2294e705c121SKalle Valo 2295e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2296e705c121SKalle Valo 2297e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2298e705c121SKalle Valo 2299e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2300e705c121SKalle Valo } 2301e705c121SKalle Valo 2302e705c121SKalle Valo static u32 2303e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2304e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2305e705c121SKalle Valo u32 monitor_len) 2306e705c121SKalle Valo { 2307e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2308e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2309e705c121SKalle Valo unsigned long flags; 2310e705c121SKalle Valo u32 i; 2311e705c121SKalle Valo 231223ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2313e705c121SKalle Valo return 0; 2314e705c121SKalle Valo 231514ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2316e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 231714ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 231814ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 231914ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2320e705c121SKalle Valo 2321e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2322e705c121SKalle Valo 2323e705c121SKalle Valo return monitor_len; 2324e705c121SKalle Valo } 2325e705c121SKalle Valo 2326e705c121SKalle Valo static u32 2327e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2328e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2329e705c121SKalle Valo u32 monitor_len) 2330e705c121SKalle Valo { 2331e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2332e705c121SKalle Valo u32 len = 0; 2333e705c121SKalle Valo 2334e705c121SKalle Valo if ((trans_pcie->fw_mon_page && 2335e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2336e705c121SKalle Valo trans->dbg_dest_tlv) { 2337e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2338e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2339e705c121SKalle Valo 2340e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2341e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2342e705c121SKalle Valo write_ptr = 2343e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2344e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2345e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2346e705c121SKalle Valo } else { 2347e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2348e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2349e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2350e705c121SKalle Valo } 2351e705c121SKalle Valo 2352e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2353e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2354e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2355e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2356e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2357e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2358e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2359e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2360e705c121SKalle Valo 2361e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 2362e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2363e705c121SKalle Valo /* 2364e705c121SKalle Valo * The firmware is now asserted, it won't write anything 2365e705c121SKalle Valo * to the buffer. CPU can take ownership to fetch the 2366e705c121SKalle Valo * data. The buffer will be handed back to the device 2367e705c121SKalle Valo * before the firmware will be restarted. 2368e705c121SKalle Valo */ 2369e705c121SKalle Valo dma_sync_single_for_cpu(trans->dev, 2370e705c121SKalle Valo trans_pcie->fw_mon_phys, 2371e705c121SKalle Valo trans_pcie->fw_mon_size, 2372e705c121SKalle Valo DMA_FROM_DEVICE); 2373e705c121SKalle Valo memcpy(fw_mon_data->data, 2374e705c121SKalle Valo page_address(trans_pcie->fw_mon_page), 2375e705c121SKalle Valo trans_pcie->fw_mon_size); 2376e705c121SKalle Valo 2377e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2378e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2379e705c121SKalle Valo /* 2380e705c121SKalle Valo * Update pointers to reflect actual values after 2381e705c121SKalle Valo * shifting 2382e705c121SKalle Valo */ 2383e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2384e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2385e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2386e705c121SKalle Valo monitor_len / sizeof(u32)); 2387e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2388e705c121SKalle Valo monitor_len = 2389e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2390e705c121SKalle Valo fw_mon_data, 2391e705c121SKalle Valo monitor_len); 2392e705c121SKalle Valo } else { 2393e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2394e705c121SKalle Valo monitor_len = 0; 2395e705c121SKalle Valo } 2396e705c121SKalle Valo 2397e705c121SKalle Valo len += monitor_len; 2398e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2399e705c121SKalle Valo } 2400e705c121SKalle Valo 2401e705c121SKalle Valo return len; 2402e705c121SKalle Valo } 2403e705c121SKalle Valo 2404e705c121SKalle Valo static struct iwl_trans_dump_data 2405e705c121SKalle Valo *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2406a80c7a69SEmmanuel Grumbach const struct iwl_fw_dbg_trigger_tlv *trigger) 2407e705c121SKalle Valo { 2408e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2409e705c121SKalle Valo struct iwl_fw_error_dump_data *data; 2410e705c121SKalle Valo struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2411e705c121SKalle Valo struct iwl_fw_error_dump_txcmd *txcmd; 2412e705c121SKalle Valo struct iwl_trans_dump_data *dump_data; 2413e705c121SKalle Valo u32 len, num_rbs; 2414e705c121SKalle Valo u32 monitor_len; 2415e705c121SKalle Valo int i, ptr; 2416e705c121SKalle Valo bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status); 2417e705c121SKalle Valo 2418e705c121SKalle Valo /* transport dump header */ 2419e705c121SKalle Valo len = sizeof(*dump_data); 2420e705c121SKalle Valo 2421e705c121SKalle Valo /* host commands */ 2422e705c121SKalle Valo len += sizeof(*data) + 2423e705c121SKalle Valo cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2424e705c121SKalle Valo 2425e705c121SKalle Valo /* FW monitor */ 2426e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2427e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2428e705c121SKalle Valo trans_pcie->fw_mon_size; 2429e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2430e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2431e705c121SKalle Valo u32 base, end; 2432e705c121SKalle Valo 2433e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2434e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2435e705c121SKalle Valo 2436e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2437e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2438e705c121SKalle Valo end = iwl_read_prph(trans, end) << 2439e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 2440e705c121SKalle Valo 2441e705c121SKalle Valo /* Make "end" point to the actual end */ 2442e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2443e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2444e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 2445e705c121SKalle Valo monitor_len = end - base; 2446e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2447e705c121SKalle Valo monitor_len; 2448e705c121SKalle Valo } else { 2449e705c121SKalle Valo monitor_len = 0; 2450e705c121SKalle Valo } 2451e705c121SKalle Valo 2452e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2453e705c121SKalle Valo dump_data = vzalloc(len); 2454e705c121SKalle Valo if (!dump_data) 2455e705c121SKalle Valo return NULL; 2456e705c121SKalle Valo 2457e705c121SKalle Valo data = (void *)dump_data->data; 2458e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2459e705c121SKalle Valo dump_data->len = len; 2460e705c121SKalle Valo 2461e705c121SKalle Valo return dump_data; 2462e705c121SKalle Valo } 2463e705c121SKalle Valo 2464e705c121SKalle Valo /* CSR registers */ 2465e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 2466e705c121SKalle Valo 2467e705c121SKalle Valo /* FH registers */ 2468e705c121SKalle Valo len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2469e705c121SKalle Valo 2470e705c121SKalle Valo if (dump_rbs) { 2471e705c121SKalle Valo /* RBs */ 2472e705c121SKalle Valo num_rbs = le16_to_cpu(ACCESS_ONCE( 2473e705c121SKalle Valo trans_pcie->rxq.rb_stts->closed_rb_num)) 2474e705c121SKalle Valo & 0x0FFF; 2475e705c121SKalle Valo num_rbs = (num_rbs - trans_pcie->rxq.read) & RX_QUEUE_MASK; 2476e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 2477e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 2478e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 2479e705c121SKalle Valo } 2480e705c121SKalle Valo 2481e705c121SKalle Valo dump_data = vzalloc(len); 2482e705c121SKalle Valo if (!dump_data) 2483e705c121SKalle Valo return NULL; 2484e705c121SKalle Valo 2485e705c121SKalle Valo len = 0; 2486e705c121SKalle Valo data = (void *)dump_data->data; 2487e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2488e705c121SKalle Valo txcmd = (void *)data->data; 2489e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 2490e705c121SKalle Valo ptr = cmdq->q.write_ptr; 2491e705c121SKalle Valo for (i = 0; i < cmdq->q.n_window; i++) { 2492e705c121SKalle Valo u8 idx = get_cmd_index(&cmdq->q, ptr); 2493e705c121SKalle Valo u32 caplen, cmdlen; 2494e705c121SKalle Valo 2495e705c121SKalle Valo cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); 2496e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2497e705c121SKalle Valo 2498e705c121SKalle Valo if (cmdlen) { 2499e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 2500e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 2501e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 2502e705c121SKalle Valo memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2503e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 2504e705c121SKalle Valo } 2505e705c121SKalle Valo 2506e705c121SKalle Valo ptr = iwl_queue_dec_wrap(ptr); 2507e705c121SKalle Valo } 2508e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 2509e705c121SKalle Valo 2510e705c121SKalle Valo data->len = cpu_to_le32(len); 2511e705c121SKalle Valo len += sizeof(*data); 2512e705c121SKalle Valo data = iwl_fw_error_next_data(data); 2513e705c121SKalle Valo 2514e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 2515e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2516e705c121SKalle Valo if (dump_rbs) 2517e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2518e705c121SKalle Valo 2519e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2520e705c121SKalle Valo 2521e705c121SKalle Valo dump_data->len = len; 2522e705c121SKalle Valo 2523e705c121SKalle Valo return dump_data; 2524e705c121SKalle Valo } 2525e705c121SKalle Valo 2526e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 2527e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 2528e705c121SKalle Valo .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2529e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 2530e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 2531e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 2532e705c121SKalle Valo 2533e705c121SKalle Valo .d3_suspend = iwl_trans_pcie_d3_suspend, 2534e705c121SKalle Valo .d3_resume = iwl_trans_pcie_d3_resume, 2535e705c121SKalle Valo 2536e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 2537e705c121SKalle Valo 2538e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 2539e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 2540e705c121SKalle Valo 2541e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 2542e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 2543e705c121SKalle Valo 2544e705c121SKalle Valo .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2545e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 25460cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2547e705c121SKalle Valo 2548e705c121SKalle Valo .write8 = iwl_trans_pcie_write8, 2549e705c121SKalle Valo .write32 = iwl_trans_pcie_write32, 2550e705c121SKalle Valo .read32 = iwl_trans_pcie_read32, 2551e705c121SKalle Valo .read_prph = iwl_trans_pcie_read_prph, 2552e705c121SKalle Valo .write_prph = iwl_trans_pcie_write_prph, 2553e705c121SKalle Valo .read_mem = iwl_trans_pcie_read_mem, 2554e705c121SKalle Valo .write_mem = iwl_trans_pcie_write_mem, 2555e705c121SKalle Valo .configure = iwl_trans_pcie_configure, 2556e705c121SKalle Valo .set_pmi = iwl_trans_pcie_set_pmi, 2557e705c121SKalle Valo .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2558e705c121SKalle Valo .release_nic_access = iwl_trans_pcie_release_nic_access, 2559e705c121SKalle Valo .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2560e705c121SKalle Valo 2561e705c121SKalle Valo .ref = iwl_trans_pcie_ref, 2562e705c121SKalle Valo .unref = iwl_trans_pcie_unref, 2563e705c121SKalle Valo 2564e705c121SKalle Valo .dump_data = iwl_trans_pcie_dump_data, 2565e705c121SKalle Valo }; 2566e705c121SKalle Valo 2567e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2568e705c121SKalle Valo const struct pci_device_id *ent, 2569e705c121SKalle Valo const struct iwl_cfg *cfg) 2570e705c121SKalle Valo { 2571e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 2572e705c121SKalle Valo struct iwl_trans *trans; 2573e705c121SKalle Valo u16 pci_cmd; 2574e705c121SKalle Valo int ret; 2575e705c121SKalle Valo 2576e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2577e705c121SKalle Valo &pdev->dev, cfg, &trans_ops_pcie, 0); 2578e705c121SKalle Valo if (!trans) 2579e705c121SKalle Valo return ERR_PTR(-ENOMEM); 2580e705c121SKalle Valo 2581e705c121SKalle Valo trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; 2582e705c121SKalle Valo 2583e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2584e705c121SKalle Valo 2585e705c121SKalle Valo trans_pcie->trans = trans; 2586e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 2587e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 2588e705c121SKalle Valo spin_lock_init(&trans_pcie->ref_lock); 2589e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 2590e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 25916eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 25926eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 25936eb5e529SEmmanuel Grumbach ret = -ENOMEM; 25946eb5e529SEmmanuel Grumbach goto out_no_pci; 25956eb5e529SEmmanuel Grumbach } 2596e705c121SKalle Valo 2597e705c121SKalle Valo ret = pci_enable_device(pdev); 2598e705c121SKalle Valo if (ret) 2599e705c121SKalle Valo goto out_no_pci; 2600e705c121SKalle Valo 2601e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 2602e705c121SKalle Valo /* 2603e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 2604e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 2605e705c121SKalle Valo * lot of power. 2606e705c121SKalle Valo */ 2607e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2608e705c121SKalle Valo PCIE_LINK_STATE_L1 | 2609e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 2610e705c121SKalle Valo } 2611e705c121SKalle Valo 2612e705c121SKalle Valo pci_set_master(pdev); 2613e705c121SKalle Valo 2614e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); 2615e705c121SKalle Valo if (!ret) 2616e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); 2617e705c121SKalle Valo if (ret) { 2618e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2619e705c121SKalle Valo if (!ret) 2620e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 2621e705c121SKalle Valo DMA_BIT_MASK(32)); 2622e705c121SKalle Valo /* both attempts failed: */ 2623e705c121SKalle Valo if (ret) { 2624e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 2625e705c121SKalle Valo goto out_pci_disable_device; 2626e705c121SKalle Valo } 2627e705c121SKalle Valo } 2628e705c121SKalle Valo 2629e705c121SKalle Valo ret = pci_request_regions(pdev, DRV_NAME); 2630e705c121SKalle Valo if (ret) { 2631e705c121SKalle Valo dev_err(&pdev->dev, "pci_request_regions failed\n"); 2632e705c121SKalle Valo goto out_pci_disable_device; 2633e705c121SKalle Valo } 2634e705c121SKalle Valo 2635e705c121SKalle Valo trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); 2636e705c121SKalle Valo if (!trans_pcie->hw_base) { 2637e705c121SKalle Valo dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); 2638e705c121SKalle Valo ret = -ENODEV; 2639e705c121SKalle Valo goto out_pci_release_regions; 2640e705c121SKalle Valo } 2641e705c121SKalle Valo 2642e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 2643e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 2644e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 2645e705c121SKalle Valo 2646e705c121SKalle Valo trans->dev = &pdev->dev; 2647e705c121SKalle Valo trans_pcie->pci_dev = pdev; 2648e705c121SKalle Valo iwl_disable_interrupts(trans); 2649e705c121SKalle Valo 2650e705c121SKalle Valo ret = pci_enable_msi(pdev); 2651e705c121SKalle Valo if (ret) { 2652e705c121SKalle Valo dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", ret); 2653e705c121SKalle Valo /* enable rfkill interrupt: hw bug w/a */ 2654e705c121SKalle Valo pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 2655e705c121SKalle Valo if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 2656e705c121SKalle Valo pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 2657e705c121SKalle Valo pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 2658e705c121SKalle Valo } 2659e705c121SKalle Valo } 2660e705c121SKalle Valo 2661e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 2662e705c121SKalle Valo /* 2663e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 2664e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 2665e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 2666e705c121SKalle Valo * in the old format. 2667e705c121SKalle Valo */ 2668e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 2669e705c121SKalle Valo unsigned long flags; 2670e705c121SKalle Valo 2671e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 2672e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 2673e705c121SKalle Valo 2674e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 2675e705c121SKalle Valo if (ret) { 2676e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 2677e705c121SKalle Valo goto out_pci_disable_msi; 2678e705c121SKalle Valo } 2679e705c121SKalle Valo 2680e705c121SKalle Valo /* 2681e705c121SKalle Valo * in-order to recognize C step driver should read chip version 2682e705c121SKalle Valo * id located at the AUX bus MISC address space. 2683e705c121SKalle Valo */ 2684e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 2685e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 2686e705c121SKalle Valo udelay(2); 2687e705c121SKalle Valo 2688e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2689e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2690e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2691e705c121SKalle Valo 25000); 2692e705c121SKalle Valo if (ret < 0) { 2693e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 2694e705c121SKalle Valo goto out_pci_disable_msi; 2695e705c121SKalle Valo } 2696e705c121SKalle Valo 269723ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2698e705c121SKalle Valo u32 hw_step; 2699e705c121SKalle Valo 270014ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 2701e705c121SKalle Valo hw_step |= ENABLE_WFPM; 270214ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 270314ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 2704e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 2705e705c121SKalle Valo if (hw_step == 0x3) 2706e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 2707e705c121SKalle Valo (SILICON_C_STEP << 2); 2708e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2709e705c121SKalle Valo } 2710e705c121SKalle Valo } 2711e705c121SKalle Valo 2712e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 2713e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 2714e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 2715e705c121SKalle Valo 2716e705c121SKalle Valo /* Initialize the wait queue for commands */ 2717e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 2718e705c121SKalle Valo 2719e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 2720e705c121SKalle Valo if (ret) 2721e705c121SKalle Valo goto out_pci_disable_msi; 2722e705c121SKalle Valo 2723e705c121SKalle Valo ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, 2724e705c121SKalle Valo iwl_pcie_irq_handler, 2725e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 2726e705c121SKalle Valo if (ret) { 2727e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 2728e705c121SKalle Valo goto out_free_ict; 2729e705c121SKalle Valo } 2730e705c121SKalle Valo 2731e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 2732e705c121SKalle Valo 2733e705c121SKalle Valo return trans; 2734e705c121SKalle Valo 2735e705c121SKalle Valo out_free_ict: 2736e705c121SKalle Valo iwl_pcie_free_ict(trans); 2737e705c121SKalle Valo out_pci_disable_msi: 2738e705c121SKalle Valo pci_disable_msi(pdev); 2739e705c121SKalle Valo out_pci_release_regions: 2740e705c121SKalle Valo pci_release_regions(pdev); 2741e705c121SKalle Valo out_pci_disable_device: 2742e705c121SKalle Valo pci_disable_device(pdev); 2743e705c121SKalle Valo out_no_pci: 27446eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 2745e705c121SKalle Valo iwl_trans_free(trans); 2746e705c121SKalle Valo return ERR_PTR(ret); 2747e705c121SKalle Valo } 2748