1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 1062d7476dSEmmanuel Grumbach * Copyright(c) 2016 Intel Deutschland GmbH 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * You should have received a copy of the GNU General Public License 22e705c121SKalle Valo * along with this program; if not, write to the Free Software 23e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24e705c121SKalle Valo * USA 25e705c121SKalle Valo * 26e705c121SKalle Valo * The full GNU General Public License is included in this distribution 27e705c121SKalle Valo * in the file called COPYING. 28e705c121SKalle Valo * 29e705c121SKalle Valo * Contact Information: 30cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 31e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32e705c121SKalle Valo * 33e705c121SKalle Valo * BSD LICENSE 34e705c121SKalle Valo * 35e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 3762d7476dSEmmanuel Grumbach * Copyright(c) 2016 Intel Deutschland GmbH 38e705c121SKalle Valo * All rights reserved. 39e705c121SKalle Valo * 40e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 41e705c121SKalle Valo * modification, are permitted provided that the following conditions 42e705c121SKalle Valo * are met: 43e705c121SKalle Valo * 44e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 45e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 46e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 47e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 48e705c121SKalle Valo * the documentation and/or other materials provided with the 49e705c121SKalle Valo * distribution. 50e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 51e705c121SKalle Valo * contributors may be used to endorse or promote products derived 52e705c121SKalle Valo * from this software without specific prior written permission. 53e705c121SKalle Valo * 54e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65e705c121SKalle Valo * 66e705c121SKalle Valo *****************************************************************************/ 67e705c121SKalle Valo #include <linux/pci.h> 68e705c121SKalle Valo #include <linux/pci-aspm.h> 69e705c121SKalle Valo #include <linux/interrupt.h> 70e705c121SKalle Valo #include <linux/debugfs.h> 71e705c121SKalle Valo #include <linux/sched.h> 72e705c121SKalle Valo #include <linux/bitops.h> 73e705c121SKalle Valo #include <linux/gfp.h> 74e705c121SKalle Valo #include <linux/vmalloc.h> 75b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 76e705c121SKalle Valo 77e705c121SKalle Valo #include "iwl-drv.h" 78e705c121SKalle Valo #include "iwl-trans.h" 79e705c121SKalle Valo #include "iwl-csr.h" 80e705c121SKalle Valo #include "iwl-prph.h" 81e705c121SKalle Valo #include "iwl-scd.h" 82e705c121SKalle Valo #include "iwl-agn-hw.h" 83e705c121SKalle Valo #include "iwl-fw-error-dump.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 91e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 92e705c121SKalle Valo { 93e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 94e705c121SKalle Valo 95e705c121SKalle Valo if (!trans_pcie->fw_mon_page) 96e705c121SKalle Valo return; 97e705c121SKalle Valo 98e705c121SKalle Valo dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 99e705c121SKalle Valo trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 100e705c121SKalle Valo __free_pages(trans_pcie->fw_mon_page, 101e705c121SKalle Valo get_order(trans_pcie->fw_mon_size)); 102e705c121SKalle Valo trans_pcie->fw_mon_page = NULL; 103e705c121SKalle Valo trans_pcie->fw_mon_phys = 0; 104e705c121SKalle Valo trans_pcie->fw_mon_size = 0; 105e705c121SKalle Valo } 106e705c121SKalle Valo 107e705c121SKalle Valo static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 108e705c121SKalle Valo { 109e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 110e705c121SKalle Valo struct page *page = NULL; 111e705c121SKalle Valo dma_addr_t phys; 112e705c121SKalle Valo u32 size = 0; 113e705c121SKalle Valo u8 power; 114e705c121SKalle Valo 115e705c121SKalle Valo if (!max_power) { 116e705c121SKalle Valo /* default max_power is maximum */ 117e705c121SKalle Valo max_power = 26; 118e705c121SKalle Valo } else { 119e705c121SKalle Valo max_power += 11; 120e705c121SKalle Valo } 121e705c121SKalle Valo 122e705c121SKalle Valo if (WARN(max_power > 26, 123e705c121SKalle Valo "External buffer size for monitor is too big %d, check the FW TLV\n", 124e705c121SKalle Valo max_power)) 125e705c121SKalle Valo return; 126e705c121SKalle Valo 127e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 128e705c121SKalle Valo dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 129e705c121SKalle Valo trans_pcie->fw_mon_size, 130e705c121SKalle Valo DMA_FROM_DEVICE); 131e705c121SKalle Valo return; 132e705c121SKalle Valo } 133e705c121SKalle Valo 134e705c121SKalle Valo phys = 0; 135e705c121SKalle Valo for (power = max_power; power >= 11; power--) { 136e705c121SKalle Valo int order; 137e705c121SKalle Valo 138e705c121SKalle Valo size = BIT(power); 139e705c121SKalle Valo order = get_order(size); 140e705c121SKalle Valo page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 141e705c121SKalle Valo order); 142e705c121SKalle Valo if (!page) 143e705c121SKalle Valo continue; 144e705c121SKalle Valo 145e705c121SKalle Valo phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 146e705c121SKalle Valo DMA_FROM_DEVICE); 147e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys)) { 148e705c121SKalle Valo __free_pages(page, order); 149e705c121SKalle Valo page = NULL; 150e705c121SKalle Valo continue; 151e705c121SKalle Valo } 152e705c121SKalle Valo IWL_INFO(trans, 153e705c121SKalle Valo "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 154e705c121SKalle Valo size, order); 155e705c121SKalle Valo break; 156e705c121SKalle Valo } 157e705c121SKalle Valo 158e705c121SKalle Valo if (WARN_ON_ONCE(!page)) 159e705c121SKalle Valo return; 160e705c121SKalle Valo 161e705c121SKalle Valo if (power != max_power) 162e705c121SKalle Valo IWL_ERR(trans, 163e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 164e705c121SKalle Valo (unsigned long)BIT(power - 10), 165e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 166e705c121SKalle Valo 167e705c121SKalle Valo trans_pcie->fw_mon_page = page; 168e705c121SKalle Valo trans_pcie->fw_mon_phys = phys; 169e705c121SKalle Valo trans_pcie->fw_mon_size = size; 170e705c121SKalle Valo } 171e705c121SKalle Valo 172e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 173e705c121SKalle Valo { 174e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 175e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 176e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 177e705c121SKalle Valo } 178e705c121SKalle Valo 179e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 180e705c121SKalle Valo { 181e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 182e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 183e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 184e705c121SKalle Valo } 185e705c121SKalle Valo 186e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 187e705c121SKalle Valo { 188e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 189e705c121SKalle Valo return; 190e705c121SKalle Valo 191e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 192e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 193e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 194e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 195e705c121SKalle Valo else 196e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 197e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 198e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 199e705c121SKalle Valo } 200e705c121SKalle Valo 201e705c121SKalle Valo /* PCI registers */ 202e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 203e705c121SKalle Valo 204e705c121SKalle Valo static void iwl_pcie_apm_config(struct iwl_trans *trans) 205e705c121SKalle Valo { 206e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 207e705c121SKalle Valo u16 lctl; 208e705c121SKalle Valo u16 cap; 209e705c121SKalle Valo 210e705c121SKalle Valo /* 211e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 212e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 213e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 214e705c121SKalle Valo * costs negligible amount of power savings. 215e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 216e705c121SKalle Valo * power savings, even without L1. 217e705c121SKalle Valo */ 218e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 219e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 220e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 221e705c121SKalle Valo else 222e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 223e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 224e705c121SKalle Valo 225e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 226e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 227e705c121SKalle Valo dev_info(trans->dev, "L1 %sabled - LTR %sabled\n", 228e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 229e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 230e705c121SKalle Valo } 231e705c121SKalle Valo 232e705c121SKalle Valo /* 233e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 234e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 235e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 236e705c121SKalle Valo */ 237e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 238e705c121SKalle Valo { 239e705c121SKalle Valo int ret = 0; 240e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 241e705c121SKalle Valo 242e705c121SKalle Valo /* 243e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 244e705c121SKalle Valo * bits already set by default after reset. 245e705c121SKalle Valo */ 246e705c121SKalle Valo 247e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 248e705c121SKalle Valo if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000) 249e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 250e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 251e705c121SKalle Valo 252e705c121SKalle Valo /* 253e705c121SKalle Valo * Disable L0s without affecting L1; 254e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 255e705c121SKalle Valo */ 256e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 257e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 258e705c121SKalle Valo 259e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 260e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 261e705c121SKalle Valo 262e705c121SKalle Valo /* 263e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 264e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 265e705c121SKalle Valo */ 266e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 267e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 268e705c121SKalle Valo 269e705c121SKalle Valo iwl_pcie_apm_config(trans); 270e705c121SKalle Valo 271e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 272e705c121SKalle Valo if (trans->cfg->base_params->pll_cfg_val) 273e705c121SKalle Valo iwl_set_bit(trans, CSR_ANA_PLL_CFG, 274e705c121SKalle Valo trans->cfg->base_params->pll_cfg_val); 275e705c121SKalle Valo 276e705c121SKalle Valo /* 277e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 278e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 279e705c121SKalle Valo */ 280e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 281e705c121SKalle Valo 282e705c121SKalle Valo /* 283e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 284e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 285e705c121SKalle Valo * and accesses to uCode SRAM. 286e705c121SKalle Valo */ 287e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 288e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 289e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 290e705c121SKalle Valo if (ret < 0) { 291e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 292e705c121SKalle Valo goto out; 293e705c121SKalle Valo } 294e705c121SKalle Valo 295e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 296e705c121SKalle Valo /* 297e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 298e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 299e705c121SKalle Valo * not related to host_interrupt_operation_mode. 300e705c121SKalle Valo * 301e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 302e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 303e705c121SKalle Valo * that we wake up from L1 on time. 304e705c121SKalle Valo * 305e705c121SKalle Valo * This looks weird: read twice the same register, discard the 306e705c121SKalle Valo * value, set a bit, and yet again, read that same register 307e705c121SKalle Valo * just to discard the value. But that's the way the hardware 308e705c121SKalle Valo * seems to like it. 309e705c121SKalle Valo */ 310e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 311e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 312e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 313e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 314e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 315e705c121SKalle Valo } 316e705c121SKalle Valo 317e705c121SKalle Valo /* 318e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 319e705c121SKalle Valo * 320e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 321e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 322e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 323e705c121SKalle Valo */ 324e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 325e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 326e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 327e705c121SKalle Valo udelay(20); 328e705c121SKalle Valo 329e705c121SKalle Valo /* Disable L1-Active */ 330e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 331e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 332e705c121SKalle Valo 333e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 334e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 335e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 336e705c121SKalle Valo } 337e705c121SKalle Valo 338e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 339e705c121SKalle Valo 340e705c121SKalle Valo out: 341e705c121SKalle Valo return ret; 342e705c121SKalle Valo } 343e705c121SKalle Valo 344e705c121SKalle Valo /* 345e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 346e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 347e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 348e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 349e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 350e705c121SKalle Valo */ 351e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 352e705c121SKalle Valo { 353e705c121SKalle Valo int ret; 354e705c121SKalle Valo u32 apmg_gp1_reg; 355e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 356e705c121SKalle Valo u32 dl_cfg_reg; 357e705c121SKalle Valo 358e705c121SKalle Valo /* Force XTAL ON */ 359e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 360e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 361e705c121SKalle Valo 362e705c121SKalle Valo /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 363e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 364e705c121SKalle Valo 365e705c121SKalle Valo udelay(10); 366e705c121SKalle Valo 367e705c121SKalle Valo /* 368e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 369e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 370e705c121SKalle Valo */ 371e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 372e705c121SKalle Valo 373e705c121SKalle Valo /* 374e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 375e705c121SKalle Valo * device-internal resources is possible. 376e705c121SKalle Valo */ 377e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 378e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 379e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 380e705c121SKalle Valo 25000); 381e705c121SKalle Valo if (WARN_ON(ret < 0)) { 382e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 383e705c121SKalle Valo /* Release XTAL ON request */ 384e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 385e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 386e705c121SKalle Valo return; 387e705c121SKalle Valo } 388e705c121SKalle Valo 389e705c121SKalle Valo /* 390e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 391e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 392e705c121SKalle Valo */ 393e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 394e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 395e705c121SKalle Valo 396e705c121SKalle Valo /* 397e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 398e705c121SKalle Valo * caused by APMG idle state. 399e705c121SKalle Valo */ 400e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 401e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 402e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 403e705c121SKalle Valo apmg_xtal_cfg_reg | 404e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 405e705c121SKalle Valo 406e705c121SKalle Valo /* 407e705c121SKalle Valo * Reset entire device again - do controller reset (results in 408e705c121SKalle Valo * SHRD_HW_RST). Turn MAC off before proceeding. 409e705c121SKalle Valo */ 410e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 411e705c121SKalle Valo 412e705c121SKalle Valo udelay(10); 413e705c121SKalle Valo 414e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 415e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 416e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 417e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 418e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 419e705c121SKalle Valo 420e705c121SKalle Valo /* Clear delay line clock power up */ 421e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 422e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 423e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 424e705c121SKalle Valo 425e705c121SKalle Valo /* 426e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 427e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 428e705c121SKalle Valo */ 429e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 430e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 431e705c121SKalle Valo 432e705c121SKalle Valo /* 433e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 434e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 435e705c121SKalle Valo */ 436e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 437e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 438e705c121SKalle Valo 439e705c121SKalle Valo /* Activates XTAL resources monitor */ 440e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 441e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 442e705c121SKalle Valo 443e705c121SKalle Valo /* Release XTAL ON request */ 444e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 445e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 446e705c121SKalle Valo udelay(10); 447e705c121SKalle Valo 448e705c121SKalle Valo /* Release APMG XTAL */ 449e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 450e705c121SKalle Valo apmg_xtal_cfg_reg & 451e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 452e705c121SKalle Valo } 453e705c121SKalle Valo 454e705c121SKalle Valo static int iwl_pcie_apm_stop_master(struct iwl_trans *trans) 455e705c121SKalle Valo { 456e705c121SKalle Valo int ret = 0; 457e705c121SKalle Valo 458e705c121SKalle Valo /* stop device's busmaster DMA activity */ 459e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 460e705c121SKalle Valo 461e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_RESET, 462e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 463e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 464e705c121SKalle Valo if (ret < 0) 465e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 466e705c121SKalle Valo 467e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 468e705c121SKalle Valo 469e705c121SKalle Valo return ret; 470e705c121SKalle Valo } 471e705c121SKalle Valo 472e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 473e705c121SKalle Valo { 474e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 475e705c121SKalle Valo 476e705c121SKalle Valo if (op_mode_leave) { 477e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 478e705c121SKalle Valo iwl_pcie_apm_init(trans); 479e705c121SKalle Valo 480e705c121SKalle Valo /* inform ME that we are leaving */ 481e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 482e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 483e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 484e705c121SKalle Valo else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 485e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 486e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 487e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 488e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 489e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 490e705c121SKalle Valo mdelay(1); 491e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 492e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 493e705c121SKalle Valo } 494e705c121SKalle Valo mdelay(5); 495e705c121SKalle Valo } 496e705c121SKalle Valo 497e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 498e705c121SKalle Valo 499e705c121SKalle Valo /* Stop device's DMA activity */ 500e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 501e705c121SKalle Valo 502e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 503e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 504e705c121SKalle Valo return; 505e705c121SKalle Valo } 506e705c121SKalle Valo 507e705c121SKalle Valo /* Reset the entire device */ 508e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 509e705c121SKalle Valo 510e705c121SKalle Valo udelay(10); 511e705c121SKalle Valo 512e705c121SKalle Valo /* 513e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 514e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 515e705c121SKalle Valo */ 516e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 517e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 518e705c121SKalle Valo } 519e705c121SKalle Valo 520e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 521e705c121SKalle Valo { 522e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 523e705c121SKalle Valo 524e705c121SKalle Valo /* nic_init */ 525e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 526e705c121SKalle Valo iwl_pcie_apm_init(trans); 527e705c121SKalle Valo 528e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 529e705c121SKalle Valo 530e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 531e705c121SKalle Valo 532e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 533e705c121SKalle Valo 534e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 535e705c121SKalle Valo iwl_pcie_rx_init(trans); 536e705c121SKalle Valo 537e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 538e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 539e705c121SKalle Valo return -ENOMEM; 540e705c121SKalle Valo 541e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 542e705c121SKalle Valo /* enable shadow regs in HW */ 543e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 544e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 545e705c121SKalle Valo } 546e705c121SKalle Valo 547e705c121SKalle Valo return 0; 548e705c121SKalle Valo } 549e705c121SKalle Valo 550e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 551e705c121SKalle Valo 552e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 553e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 554e705c121SKalle Valo { 555e705c121SKalle Valo int ret; 556e705c121SKalle Valo 557e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 558e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 559e705c121SKalle Valo 560e705c121SKalle Valo /* See if we got it */ 561e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 562e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 563e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 564e705c121SKalle Valo HW_READY_TIMEOUT); 565e705c121SKalle Valo 566e705c121SKalle Valo if (ret >= 0) 567e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 568e705c121SKalle Valo 569e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 570e705c121SKalle Valo return ret; 571e705c121SKalle Valo } 572e705c121SKalle Valo 573e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 574e705c121SKalle Valo static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 575e705c121SKalle Valo { 576e705c121SKalle Valo int ret; 577e705c121SKalle Valo int t = 0; 578e705c121SKalle Valo int iter; 579e705c121SKalle Valo 580e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 581e705c121SKalle Valo 582e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 583e705c121SKalle Valo /* If the card is ready, exit 0 */ 584e705c121SKalle Valo if (ret >= 0) 585e705c121SKalle Valo return 0; 586e705c121SKalle Valo 587e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 588e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 589e705c121SKalle Valo msleep(1); 590e705c121SKalle Valo 591e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 592e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 593e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 594e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 595e705c121SKalle Valo 596e705c121SKalle Valo do { 597e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 598e705c121SKalle Valo if (ret >= 0) 599e705c121SKalle Valo return 0; 600e705c121SKalle Valo 601e705c121SKalle Valo usleep_range(200, 1000); 602e705c121SKalle Valo t += 200; 603e705c121SKalle Valo } while (t < 150000); 604e705c121SKalle Valo msleep(25); 605e705c121SKalle Valo } 606e705c121SKalle Valo 607e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 608e705c121SKalle Valo 609e705c121SKalle Valo return ret; 610e705c121SKalle Valo } 611e705c121SKalle Valo 612e705c121SKalle Valo /* 613e705c121SKalle Valo * ucode 614e705c121SKalle Valo */ 615e705c121SKalle Valo static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr, 616e705c121SKalle Valo dma_addr_t phy_addr, u32 byte_cnt) 617e705c121SKalle Valo { 618e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 619bac842daSEmmanuel Grumbach unsigned long flags; 620e705c121SKalle Valo int ret; 621e705c121SKalle Valo 622e705c121SKalle Valo trans_pcie->ucode_write_complete = false; 623e705c121SKalle Valo 624bac842daSEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 625bac842daSEmmanuel Grumbach return -EIO; 626bac842daSEmmanuel Grumbach 627bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 628e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 629e705c121SKalle Valo 630bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 631e705c121SKalle Valo dst_addr); 632e705c121SKalle Valo 633bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 634e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 635e705c121SKalle Valo 636bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 637e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 638e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 639e705c121SKalle Valo 640bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 641bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 642bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 643e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 644e705c121SKalle Valo 645bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 646e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 647e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 648e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 649e705c121SKalle Valo 650bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 651bac842daSEmmanuel Grumbach 652e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 653e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 654e705c121SKalle Valo if (!ret) { 655e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 656e705c121SKalle Valo return -ETIMEDOUT; 657e705c121SKalle Valo } 658e705c121SKalle Valo 659e705c121SKalle Valo return 0; 660e705c121SKalle Valo } 661e705c121SKalle Valo 662e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 663e705c121SKalle Valo const struct fw_desc *section) 664e705c121SKalle Valo { 665e705c121SKalle Valo u8 *v_addr; 666e705c121SKalle Valo dma_addr_t p_addr; 667e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 668e705c121SKalle Valo int ret = 0; 669e705c121SKalle Valo 670e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 671e705c121SKalle Valo section_num); 672e705c121SKalle Valo 673e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 674e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 675e705c121SKalle Valo if (!v_addr) { 676e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 677e705c121SKalle Valo chunk_sz = PAGE_SIZE; 678e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 679e705c121SKalle Valo &p_addr, GFP_KERNEL); 680e705c121SKalle Valo if (!v_addr) 681e705c121SKalle Valo return -ENOMEM; 682e705c121SKalle Valo } 683e705c121SKalle Valo 684e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 685e705c121SKalle Valo u32 copy_size, dst_addr; 686e705c121SKalle Valo bool extended_addr = false; 687e705c121SKalle Valo 688e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 689e705c121SKalle Valo dst_addr = section->offset + offset; 690e705c121SKalle Valo 691e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 692e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 693e705c121SKalle Valo extended_addr = true; 694e705c121SKalle Valo 695e705c121SKalle Valo if (extended_addr) 696e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 697e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 698e705c121SKalle Valo 699e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 700e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 701e705c121SKalle Valo copy_size); 702e705c121SKalle Valo 703e705c121SKalle Valo if (extended_addr) 704e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 705e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 706e705c121SKalle Valo 707e705c121SKalle Valo if (ret) { 708e705c121SKalle Valo IWL_ERR(trans, 709e705c121SKalle Valo "Could not load the [%d] uCode section\n", 710e705c121SKalle Valo section_num); 711e705c121SKalle Valo break; 712e705c121SKalle Valo } 713e705c121SKalle Valo } 714e705c121SKalle Valo 715e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 716e705c121SKalle Valo return ret; 717e705c121SKalle Valo } 718e705c121SKalle Valo 719e705c121SKalle Valo /* 720e705c121SKalle Valo * Driver Takes the ownership on secure machine before FW load 721e705c121SKalle Valo * and prevent race with the BT load. 722e705c121SKalle Valo * W/A for ROM bug. (should be remove in the next Si step) 723e705c121SKalle Valo */ 724e705c121SKalle Valo static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans) 725e705c121SKalle Valo { 726e705c121SKalle Valo u32 val, loop = 1000; 727e705c121SKalle Valo 728e705c121SKalle Valo /* 729e705c121SKalle Valo * Check the RSA semaphore is accessible. 730e705c121SKalle Valo * If the HW isn't locked and the rsa semaphore isn't accessible, 731e705c121SKalle Valo * we are in trouble. 732e705c121SKalle Valo */ 733e705c121SKalle Valo val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0); 734e705c121SKalle Valo if (val & (BIT(1) | BIT(17))) { 7359fc515bcSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 736e705c121SKalle Valo "can't access the RSA semaphore it is write protected\n"); 737e705c121SKalle Valo return 0; 738e705c121SKalle Valo } 739e705c121SKalle Valo 740e705c121SKalle Valo /* take ownership on the AUX IF */ 741e705c121SKalle Valo iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK); 742e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK); 743e705c121SKalle Valo 744e705c121SKalle Valo do { 745e705c121SKalle Valo iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1); 746e705c121SKalle Valo val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS); 747e705c121SKalle Valo if (val == 0x1) { 748e705c121SKalle Valo iwl_write_prph(trans, RSA_ENABLE, 0); 749e705c121SKalle Valo return 0; 750e705c121SKalle Valo } 751e705c121SKalle Valo 752e705c121SKalle Valo udelay(10); 753e705c121SKalle Valo loop--; 754e705c121SKalle Valo } while (loop > 0); 755e705c121SKalle Valo 756e705c121SKalle Valo IWL_ERR(trans, "Failed to take ownership on secure machine\n"); 757e705c121SKalle Valo return -EIO; 758e705c121SKalle Valo } 759e705c121SKalle Valo 760e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 761e705c121SKalle Valo const struct fw_img *image, 762e705c121SKalle Valo int cpu, 763e705c121SKalle Valo int *first_ucode_section) 764e705c121SKalle Valo { 765e705c121SKalle Valo int shift_param; 766e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 767e705c121SKalle Valo u32 val, last_read_idx = 0; 768e705c121SKalle Valo 769e705c121SKalle Valo if (cpu == 1) { 770e705c121SKalle Valo shift_param = 0; 771e705c121SKalle Valo *first_ucode_section = 0; 772e705c121SKalle Valo } else { 773e705c121SKalle Valo shift_param = 16; 774e705c121SKalle Valo (*first_ucode_section)++; 775e705c121SKalle Valo } 776e705c121SKalle Valo 777e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 778e705c121SKalle Valo last_read_idx = i; 779e705c121SKalle Valo 780e705c121SKalle Valo /* 781e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 782e705c121SKalle Valo * CPU1 to CPU2. 783e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 784e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 785e705c121SKalle Valo */ 786e705c121SKalle Valo if (!image->sec[i].data || 787e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 788e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 789e705c121SKalle Valo IWL_DEBUG_FW(trans, 790e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 791e705c121SKalle Valo i); 792e705c121SKalle Valo break; 793e705c121SKalle Valo } 794e705c121SKalle Valo 795e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 796e705c121SKalle Valo if (ret) 797e705c121SKalle Valo return ret; 798e705c121SKalle Valo 799e705c121SKalle Valo /* Notify the ucode of the loaded section number and status */ 800e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 801e705c121SKalle Valo val = val | (sec_num << shift_param); 802e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 803e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 804e705c121SKalle Valo } 805e705c121SKalle Valo 806e705c121SKalle Valo *first_ucode_section = last_read_idx; 807e705c121SKalle Valo 808e705c121SKalle Valo if (cpu == 1) 809e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFF); 810e705c121SKalle Valo else 811e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 0xFFFFFFFF); 812e705c121SKalle Valo 813e705c121SKalle Valo return 0; 814e705c121SKalle Valo } 815e705c121SKalle Valo 816e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 817e705c121SKalle Valo const struct fw_img *image, 818e705c121SKalle Valo int cpu, 819e705c121SKalle Valo int *first_ucode_section) 820e705c121SKalle Valo { 821e705c121SKalle Valo int shift_param; 822e705c121SKalle Valo int i, ret = 0; 823e705c121SKalle Valo u32 last_read_idx = 0; 824e705c121SKalle Valo 825e705c121SKalle Valo if (cpu == 1) { 826e705c121SKalle Valo shift_param = 0; 827e705c121SKalle Valo *first_ucode_section = 0; 828e705c121SKalle Valo } else { 829e705c121SKalle Valo shift_param = 16; 830e705c121SKalle Valo (*first_ucode_section)++; 831e705c121SKalle Valo } 832e705c121SKalle Valo 833e705c121SKalle Valo for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) { 834e705c121SKalle Valo last_read_idx = i; 835e705c121SKalle Valo 836e705c121SKalle Valo /* 837e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 838e705c121SKalle Valo * CPU1 to CPU2. 839e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 840e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 841e705c121SKalle Valo */ 842e705c121SKalle Valo if (!image->sec[i].data || 843e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 844e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 845e705c121SKalle Valo IWL_DEBUG_FW(trans, 846e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 847e705c121SKalle Valo i); 848e705c121SKalle Valo break; 849e705c121SKalle Valo } 850e705c121SKalle Valo 851e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 852e705c121SKalle Valo if (ret) 853e705c121SKalle Valo return ret; 854e705c121SKalle Valo } 855e705c121SKalle Valo 856e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 857e705c121SKalle Valo iwl_set_bits_prph(trans, 858e705c121SKalle Valo CSR_UCODE_LOAD_STATUS_ADDR, 859e705c121SKalle Valo (LMPM_CPU_UCODE_LOADING_COMPLETED | 860e705c121SKalle Valo LMPM_CPU_HDRS_LOADING_COMPLETED | 861e705c121SKalle Valo LMPM_CPU_UCODE_LOADING_STARTED) << 862e705c121SKalle Valo shift_param); 863e705c121SKalle Valo 864e705c121SKalle Valo *first_ucode_section = last_read_idx; 865e705c121SKalle Valo 866e705c121SKalle Valo return 0; 867e705c121SKalle Valo } 868e705c121SKalle Valo 869e705c121SKalle Valo static void iwl_pcie_apply_destination(struct iwl_trans *trans) 870e705c121SKalle Valo { 871e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 872e705c121SKalle Valo const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 873e705c121SKalle Valo int i; 874e705c121SKalle Valo 875e705c121SKalle Valo if (dest->version) 876e705c121SKalle Valo IWL_ERR(trans, 877e705c121SKalle Valo "DBG DEST version is %d - expect issues\n", 878e705c121SKalle Valo dest->version); 879e705c121SKalle Valo 880e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 881e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 882e705c121SKalle Valo 883e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 884e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 885e705c121SKalle Valo else 886e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 887e705c121SKalle Valo 888e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 889e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 890e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 891e705c121SKalle Valo 892e705c121SKalle Valo switch (dest->reg_ops[i].op) { 893e705c121SKalle Valo case CSR_ASSIGN: 894e705c121SKalle Valo iwl_write32(trans, addr, val); 895e705c121SKalle Valo break; 896e705c121SKalle Valo case CSR_SETBIT: 897e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 898e705c121SKalle Valo break; 899e705c121SKalle Valo case CSR_CLEARBIT: 900e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 901e705c121SKalle Valo break; 902e705c121SKalle Valo case PRPH_ASSIGN: 903e705c121SKalle Valo iwl_write_prph(trans, addr, val); 904e705c121SKalle Valo break; 905e705c121SKalle Valo case PRPH_SETBIT: 906e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 907e705c121SKalle Valo break; 908e705c121SKalle Valo case PRPH_CLEARBIT: 909e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 910e705c121SKalle Valo break; 911e705c121SKalle Valo case PRPH_BLOCKBIT: 912e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 913e705c121SKalle Valo IWL_ERR(trans, 914e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 915e705c121SKalle Valo val, addr); 916e705c121SKalle Valo goto monitor; 917e705c121SKalle Valo } 918e705c121SKalle Valo break; 919e705c121SKalle Valo default: 920e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 921e705c121SKalle Valo dest->reg_ops[i].op); 922e705c121SKalle Valo break; 923e705c121SKalle Valo } 924e705c121SKalle Valo } 925e705c121SKalle Valo 926e705c121SKalle Valo monitor: 927e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 928e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 929e705c121SKalle Valo trans_pcie->fw_mon_phys >> dest->base_shift); 93062d7476dSEmmanuel Grumbach if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 931e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 932e705c121SKalle Valo (trans_pcie->fw_mon_phys + 93362d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size - 256) >> 93462d7476dSEmmanuel Grumbach dest->end_shift); 93562d7476dSEmmanuel Grumbach else 93662d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 93762d7476dSEmmanuel Grumbach (trans_pcie->fw_mon_phys + 93862d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size) >> 93962d7476dSEmmanuel Grumbach dest->end_shift); 940e705c121SKalle Valo } 941e705c121SKalle Valo } 942e705c121SKalle Valo 943e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 944e705c121SKalle Valo const struct fw_img *image) 945e705c121SKalle Valo { 946e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 947e705c121SKalle Valo int ret = 0; 948e705c121SKalle Valo int first_ucode_section; 949e705c121SKalle Valo 950e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 951e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 952e705c121SKalle Valo 953e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 954e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 955e705c121SKalle Valo if (ret) 956e705c121SKalle Valo return ret; 957e705c121SKalle Valo 958e705c121SKalle Valo if (image->is_dual_cpus) { 959e705c121SKalle Valo /* set CPU2 header address */ 960e705c121SKalle Valo iwl_write_prph(trans, 961e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 962e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 963e705c121SKalle Valo 964e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 965e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 966e705c121SKalle Valo &first_ucode_section); 967e705c121SKalle Valo if (ret) 968e705c121SKalle Valo return ret; 969e705c121SKalle Valo } 970e705c121SKalle Valo 971e705c121SKalle Valo /* supported for 7000 only for the moment */ 972e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 973e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 974e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 975e705c121SKalle Valo 976e705c121SKalle Valo if (trans_pcie->fw_mon_size) { 977e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 978e705c121SKalle Valo trans_pcie->fw_mon_phys >> 4); 979e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 980e705c121SKalle Valo (trans_pcie->fw_mon_phys + 981e705c121SKalle Valo trans_pcie->fw_mon_size) >> 4); 982e705c121SKalle Valo } 983e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 984e705c121SKalle Valo iwl_pcie_apply_destination(trans); 985e705c121SKalle Valo } 986e705c121SKalle Valo 987e705c121SKalle Valo /* release CPU reset */ 988e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 989e705c121SKalle Valo 990e705c121SKalle Valo return 0; 991e705c121SKalle Valo } 992e705c121SKalle Valo 993e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 994e705c121SKalle Valo const struct fw_img *image) 995e705c121SKalle Valo { 996e705c121SKalle Valo int ret = 0; 997e705c121SKalle Valo int first_ucode_section; 998e705c121SKalle Valo 999e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1000e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1001e705c121SKalle Valo 1002e705c121SKalle Valo if (trans->dbg_dest_tlv) 1003e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1004e705c121SKalle Valo 1005e705c121SKalle Valo /* TODO: remove in the next Si step */ 1006e705c121SKalle Valo ret = iwl_pcie_rsa_race_bug_wa(trans); 1007e705c121SKalle Valo if (ret) 1008e705c121SKalle Valo return ret; 1009e705c121SKalle Valo 1010e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1011e705c121SKalle Valo /* release CPU reset */ 1012e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1013e705c121SKalle Valo 1014e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1015e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1016e705c121SKalle Valo &first_ucode_section); 1017e705c121SKalle Valo if (ret) 1018e705c121SKalle Valo return ret; 1019e705c121SKalle Valo 1020e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1021e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1022e705c121SKalle Valo &first_ucode_section); 1023e705c121SKalle Valo } 1024e705c121SKalle Valo 1025e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1026e705c121SKalle Valo { 1027e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1028e705c121SKalle Valo bool hw_rfkill, was_hw_rfkill; 1029e705c121SKalle Valo 1030e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1031e705c121SKalle Valo 1032e705c121SKalle Valo if (trans_pcie->is_down) 1033e705c121SKalle Valo return; 1034e705c121SKalle Valo 1035e705c121SKalle Valo trans_pcie->is_down = true; 1036e705c121SKalle Valo 1037e705c121SKalle Valo was_hw_rfkill = iwl_is_rfkill_set(trans); 1038e705c121SKalle Valo 1039e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1040e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1041e705c121SKalle Valo iwl_disable_interrupts(trans); 1042e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1043e705c121SKalle Valo 1044e705c121SKalle Valo /* device going down, Stop using ICT table */ 1045e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1046e705c121SKalle Valo 1047e705c121SKalle Valo /* 1048e705c121SKalle Valo * If a HW restart happens during firmware loading, 1049e705c121SKalle Valo * then the firmware loading might call this function 1050e705c121SKalle Valo * and later it might be called again due to the 1051e705c121SKalle Valo * restart. So don't process again if the device is 1052e705c121SKalle Valo * already dead. 1053e705c121SKalle Valo */ 1054e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1055a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1056a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1057e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1058e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1059e705c121SKalle Valo 1060e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1061e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1062e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1063e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1064e705c121SKalle Valo udelay(5); 1065e705c121SKalle Valo } 1066e705c121SKalle Valo } 1067e705c121SKalle Valo 1068e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1069e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1070e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1071e705c121SKalle Valo 1072e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1073e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1074e705c121SKalle Valo 1075e705c121SKalle Valo /* stop and reset the on-board processor */ 1076e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1077e705c121SKalle Valo udelay(20); 1078e705c121SKalle Valo 1079e705c121SKalle Valo /* 1080e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1081e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1082e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1083e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1084e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1085e705c121SKalle Valo */ 1086e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1087e705c121SKalle Valo iwl_disable_interrupts(trans); 1088e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1089e705c121SKalle Valo 1090e705c121SKalle Valo /* clear all status bits */ 1091e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1092e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1093e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1094e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1095e705c121SKalle Valo 1096e705c121SKalle Valo /* 1097e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1098e705c121SKalle Valo * interrupt 1099e705c121SKalle Valo */ 1100e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1101e705c121SKalle Valo 1102e705c121SKalle Valo /* 1103e705c121SKalle Valo * Check again since the RF kill state may have changed while 1104e705c121SKalle Valo * all the interrupts were disabled, in this case we couldn't 1105e705c121SKalle Valo * receive the RF kill interrupt and update the state in the 1106e705c121SKalle Valo * op_mode. 1107e705c121SKalle Valo * Don't call the op_mode if the rkfill state hasn't changed. 1108e705c121SKalle Valo * This allows the op_mode to call stop_device from the rfkill 1109e705c121SKalle Valo * notification without endless recursion. Under very rare 1110e705c121SKalle Valo * circumstances, we might have a small recursion if the rfkill 1111e705c121SKalle Valo * state changed exactly now while we were called from stop_device. 1112e705c121SKalle Valo * This is very unlikely but can happen and is supported. 1113e705c121SKalle Valo */ 1114e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1115e705c121SKalle Valo if (hw_rfkill) 1116e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1117e705c121SKalle Valo else 1118e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1119e705c121SKalle Valo if (hw_rfkill != was_hw_rfkill) 1120e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1121e705c121SKalle Valo 1122a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1123e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1124e705c121SKalle Valo } 1125e705c121SKalle Valo 11262e5d4a8fSHaim Dreyfuss static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 11272e5d4a8fSHaim Dreyfuss { 11282e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11292e5d4a8fSHaim Dreyfuss 11302e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 11312e5d4a8fSHaim Dreyfuss int i; 11322e5d4a8fSHaim Dreyfuss 11332e5d4a8fSHaim Dreyfuss for (i = 0; i < trans_pcie->allocated_vector; i++) 11342e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 11352e5d4a8fSHaim Dreyfuss } else { 11362e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 11372e5d4a8fSHaim Dreyfuss } 11382e5d4a8fSHaim Dreyfuss } 11392e5d4a8fSHaim Dreyfuss 1140a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1141a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1142a6bd005fSEmmanuel Grumbach { 1143a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1144a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1145a6bd005fSEmmanuel Grumbach int ret; 1146a6bd005fSEmmanuel Grumbach 1147a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1148a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1149a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1150a6bd005fSEmmanuel Grumbach ret = -EIO; 1151a6bd005fSEmmanuel Grumbach goto out; 1152a6bd005fSEmmanuel Grumbach } 1153a6bd005fSEmmanuel Grumbach 1154a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1155a6bd005fSEmmanuel Grumbach 1156a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1157a6bd005fSEmmanuel Grumbach 1158a6bd005fSEmmanuel Grumbach /* 1159a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1160a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1161a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1162a6bd005fSEmmanuel Grumbach */ 1163a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1164a6bd005fSEmmanuel Grumbach 1165a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 11662e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1167a6bd005fSEmmanuel Grumbach 1168a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1169a6bd005fSEmmanuel Grumbach 1170a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 1171a6bd005fSEmmanuel Grumbach hw_rfkill = iwl_is_rfkill_set(trans); 1172a6bd005fSEmmanuel Grumbach if (hw_rfkill) 1173a6bd005fSEmmanuel Grumbach set_bit(STATUS_RFKILL, &trans->status); 1174a6bd005fSEmmanuel Grumbach else 1175a6bd005fSEmmanuel Grumbach clear_bit(STATUS_RFKILL, &trans->status); 1176a6bd005fSEmmanuel Grumbach iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1177a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1178a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1179a6bd005fSEmmanuel Grumbach goto out; 1180a6bd005fSEmmanuel Grumbach } 1181a6bd005fSEmmanuel Grumbach 1182a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1183a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1184a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1185a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 118620aa99bbSAnton Protopopov ret = -EIO; 1187a6bd005fSEmmanuel Grumbach goto out; 1188a6bd005fSEmmanuel Grumbach } 1189a6bd005fSEmmanuel Grumbach 1190a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1191a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1192a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1193a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1194a6bd005fSEmmanuel Grumbach 1195a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1196a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1197a6bd005fSEmmanuel Grumbach 1198a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1199a6bd005fSEmmanuel Grumbach if (ret) { 1200a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1201a6bd005fSEmmanuel Grumbach goto out; 1202a6bd005fSEmmanuel Grumbach } 1203a6bd005fSEmmanuel Grumbach 1204a6bd005fSEmmanuel Grumbach /* 1205a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1206a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1207a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1208a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1209a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1210a6bd005fSEmmanuel Grumbach */ 1211a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1212a6bd005fSEmmanuel Grumbach 1213a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1214a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1215a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1216a6bd005fSEmmanuel Grumbach 1217a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 1218a6bd005fSEmmanuel Grumbach if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1219a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1220a6bd005fSEmmanuel Grumbach else 1221a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1222a6bd005fSEmmanuel Grumbach iwl_enable_interrupts(trans); 1223a6bd005fSEmmanuel Grumbach 1224a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 1225a6bd005fSEmmanuel Grumbach hw_rfkill = iwl_is_rfkill_set(trans); 1226a6bd005fSEmmanuel Grumbach if (hw_rfkill) 1227a6bd005fSEmmanuel Grumbach set_bit(STATUS_RFKILL, &trans->status); 1228a6bd005fSEmmanuel Grumbach else 1229a6bd005fSEmmanuel Grumbach clear_bit(STATUS_RFKILL, &trans->status); 1230a6bd005fSEmmanuel Grumbach 1231a6bd005fSEmmanuel Grumbach iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1232a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1233a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1234a6bd005fSEmmanuel Grumbach 1235a6bd005fSEmmanuel Grumbach out: 1236a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1237a6bd005fSEmmanuel Grumbach return ret; 1238a6bd005fSEmmanuel Grumbach } 1239a6bd005fSEmmanuel Grumbach 1240a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1241a6bd005fSEmmanuel Grumbach { 1242a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1243a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1244a6bd005fSEmmanuel Grumbach } 1245a6bd005fSEmmanuel Grumbach 1246e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1247e705c121SKalle Valo { 1248e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1249e705c121SKalle Valo 1250e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1251e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1252e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1253e705c121SKalle Valo } 1254e705c121SKalle Valo 1255e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1256e705c121SKalle Valo { 1257e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1258e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1259e705c121SKalle Valo 1260e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1261e705c121SKalle Valo 1262e705c121SKalle Valo if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) 1263e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1264e705c121SKalle Valo } 1265e705c121SKalle Valo 126623ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 126723ae6128SMatti Gottlieb bool reset) 1268e705c121SKalle Valo { 126923ae6128SMatti Gottlieb if (!reset) { 1270e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1271e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1272e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1273e705c121SKalle Valo } 1274e705c121SKalle Valo 1275e705c121SKalle Valo iwl_disable_interrupts(trans); 1276e705c121SKalle Valo 1277e705c121SKalle Valo /* 1278e705c121SKalle Valo * in testing mode, the host stays awake and the 1279e705c121SKalle Valo * hardware won't be reset (not even partially) 1280e705c121SKalle Valo */ 1281e705c121SKalle Valo if (test) 1282e705c121SKalle Valo return; 1283e705c121SKalle Valo 1284e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1285e705c121SKalle Valo 12862e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1287e705c121SKalle Valo 1288e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1289e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1290e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1291e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1292e705c121SKalle Valo 129323ae6128SMatti Gottlieb if (reset) { 1294e705c121SKalle Valo /* 1295e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1296e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1297e705c121SKalle Valo * to execute some invalid memory upon resume 1298e705c121SKalle Valo */ 1299e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1300e705c121SKalle Valo } 1301e705c121SKalle Valo 1302e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1303e705c121SKalle Valo } 1304e705c121SKalle Valo 1305e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1306e705c121SKalle Valo enum iwl_d3_status *status, 130723ae6128SMatti Gottlieb bool test, bool reset) 1308e705c121SKalle Valo { 1309e705c121SKalle Valo u32 val; 1310e705c121SKalle Valo int ret; 1311e705c121SKalle Valo 1312e705c121SKalle Valo if (test) { 1313e705c121SKalle Valo iwl_enable_interrupts(trans); 1314e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1315e705c121SKalle Valo return 0; 1316e705c121SKalle Valo } 1317e705c121SKalle Valo 1318e705c121SKalle Valo /* 1319e705c121SKalle Valo * Also enables interrupts - none will happen as the device doesn't 1320e705c121SKalle Valo * know we're waking it up, only when the opmode actually tells it 1321e705c121SKalle Valo * after this call. 1322e705c121SKalle Valo */ 1323e705c121SKalle Valo iwl_pcie_reset_ict(trans); 132418dcb9a9SSara Sharon iwl_enable_interrupts(trans); 1325e705c121SKalle Valo 1326e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1327e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1328e705c121SKalle Valo 1329e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1330e705c121SKalle Valo udelay(2); 1331e705c121SKalle Valo 1332e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1333e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1334e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1335e705c121SKalle Valo 25000); 1336e705c121SKalle Valo if (ret < 0) { 1337e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1338e705c121SKalle Valo return ret; 1339e705c121SKalle Valo } 1340e705c121SKalle Valo 1341e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1342e705c121SKalle Valo 134323ae6128SMatti Gottlieb if (!reset) { 1344e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1345e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1346e705c121SKalle Valo } else { 1347e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1348e705c121SKalle Valo 1349e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1350e705c121SKalle Valo if (ret) { 1351e705c121SKalle Valo IWL_ERR(trans, 1352e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1353e705c121SKalle Valo return ret; 1354e705c121SKalle Valo } 1355e705c121SKalle Valo } 1356e705c121SKalle Valo 1357e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1358e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1359e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1360e705c121SKalle Valo else 1361e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1362e705c121SKalle Valo 1363e705c121SKalle Valo return 0; 1364e705c121SKalle Valo } 1365e705c121SKalle Valo 13662e5d4a8fSHaim Dreyfuss struct iwl_causes_list { 13672e5d4a8fSHaim Dreyfuss u32 cause_num; 13682e5d4a8fSHaim Dreyfuss u32 mask_reg; 13692e5d4a8fSHaim Dreyfuss u8 addr; 13702e5d4a8fSHaim Dreyfuss }; 13712e5d4a8fSHaim Dreyfuss 13722e5d4a8fSHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 13732e5d4a8fSHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 13742e5d4a8fSHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 13752e5d4a8fSHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 13762e5d4a8fSHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 13772e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 13782e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 13792e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 13802e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 13812e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 13822e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 13832e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 13842e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 13852e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 13862e5d4a8fSHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 13872e5d4a8fSHaim Dreyfuss }; 13882e5d4a8fSHaim Dreyfuss 13892e5d4a8fSHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 13902e5d4a8fSHaim Dreyfuss { 13912e5d4a8fSHaim Dreyfuss u32 val, max_rx_vector, i; 13922e5d4a8fSHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 13932e5d4a8fSHaim Dreyfuss 13942e5d4a8fSHaim Dreyfuss max_rx_vector = trans_pcie->allocated_vector - 1; 13952e5d4a8fSHaim Dreyfuss 13962e5d4a8fSHaim Dreyfuss if (!trans_pcie->msix_enabled) 13972e5d4a8fSHaim Dreyfuss return; 13982e5d4a8fSHaim Dreyfuss 13992e5d4a8fSHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 14002e5d4a8fSHaim Dreyfuss 14012e5d4a8fSHaim Dreyfuss /* 14022e5d4a8fSHaim Dreyfuss * Each cause from the list above and the RX causes is represented as 14032e5d4a8fSHaim Dreyfuss * a byte in the IVAR table. We access the first (N - 1) bytes and map 14042e5d4a8fSHaim Dreyfuss * them to the (N - 1) vectors so these vectors will be used as rx 14052e5d4a8fSHaim Dreyfuss * vectors. Then access all non rx causes and map them to the 14062e5d4a8fSHaim Dreyfuss * default queue (N'th queue). 14072e5d4a8fSHaim Dreyfuss */ 14082e5d4a8fSHaim Dreyfuss for (i = 0; i < max_rx_vector; i++) { 14092e5d4a8fSHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(i), MSIX_FH_INT_CAUSES_Q(i)); 14102e5d4a8fSHaim Dreyfuss iwl_clear_bit(trans, CSR_MSIX_FH_INT_MASK_AD, 14112e5d4a8fSHaim Dreyfuss BIT(MSIX_FH_INT_CAUSES_Q(i))); 14122e5d4a8fSHaim Dreyfuss } 14132e5d4a8fSHaim Dreyfuss 14142e5d4a8fSHaim Dreyfuss for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 14152e5d4a8fSHaim Dreyfuss val = trans_pcie->default_irq_num | 14162e5d4a8fSHaim Dreyfuss MSIX_NON_AUTO_CLEAR_CAUSE; 14172e5d4a8fSHaim Dreyfuss iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 14182e5d4a8fSHaim Dreyfuss iwl_clear_bit(trans, causes_list[i].mask_reg, 14192e5d4a8fSHaim Dreyfuss causes_list[i].cause_num); 14202e5d4a8fSHaim Dreyfuss } 14212e5d4a8fSHaim Dreyfuss trans_pcie->fh_init_mask = 14222e5d4a8fSHaim Dreyfuss ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 14232e5d4a8fSHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 14242e5d4a8fSHaim Dreyfuss trans_pcie->hw_init_mask = 14252e5d4a8fSHaim Dreyfuss ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 14262e5d4a8fSHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 14272e5d4a8fSHaim Dreyfuss } 14282e5d4a8fSHaim Dreyfuss 14292e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 14302e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 14312e5d4a8fSHaim Dreyfuss { 14322e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 14332e5d4a8fSHaim Dreyfuss u16 pci_cmd; 14342e5d4a8fSHaim Dreyfuss int max_vector; 14352e5d4a8fSHaim Dreyfuss int ret, i; 14362e5d4a8fSHaim Dreyfuss 14372e5d4a8fSHaim Dreyfuss if (trans->cfg->mq_rx_supported) { 1438013a67eaSSara Sharon max_vector = min_t(u32, (num_possible_cpus() + 2), 14392e5d4a8fSHaim Dreyfuss IWL_MAX_RX_HW_QUEUES); 14402e5d4a8fSHaim Dreyfuss for (i = 0; i < max_vector; i++) 14412e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 14422e5d4a8fSHaim Dreyfuss 14432e5d4a8fSHaim Dreyfuss ret = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 14442e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 14452e5d4a8fSHaim Dreyfuss max_vector); 14462e5d4a8fSHaim Dreyfuss if (ret > 1) { 14472e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 14482e5d4a8fSHaim Dreyfuss "Enable MSI-X allocate %d interrupt vector\n", 14492e5d4a8fSHaim Dreyfuss ret); 14502e5d4a8fSHaim Dreyfuss trans_pcie->allocated_vector = ret; 14512e5d4a8fSHaim Dreyfuss trans_pcie->default_irq_num = 14522e5d4a8fSHaim Dreyfuss trans_pcie->allocated_vector - 1; 14532e5d4a8fSHaim Dreyfuss trans_pcie->trans->num_rx_queues = 14542e5d4a8fSHaim Dreyfuss trans_pcie->allocated_vector - 1; 14552e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = true; 14562e5d4a8fSHaim Dreyfuss 14572e5d4a8fSHaim Dreyfuss return; 14582e5d4a8fSHaim Dreyfuss } 14592e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 14602e5d4a8fSHaim Dreyfuss "ret = %d %s move to msi mode\n", ret, 14612e5d4a8fSHaim Dreyfuss (ret == 1) ? 14622e5d4a8fSHaim Dreyfuss "can't allocate more than 1 interrupt vector" : 14632e5d4a8fSHaim Dreyfuss "failed to enable msi-x mode"); 14642e5d4a8fSHaim Dreyfuss pci_disable_msix(pdev); 14652e5d4a8fSHaim Dreyfuss } 14662e5d4a8fSHaim Dreyfuss 14672e5d4a8fSHaim Dreyfuss ret = pci_enable_msi(pdev); 14682e5d4a8fSHaim Dreyfuss if (ret) { 14696ed5e4d6SEmmanuel Grumbach dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 14702e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 14712e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 14722e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 14732e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 14742e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 14752e5d4a8fSHaim Dreyfuss } 14762e5d4a8fSHaim Dreyfuss } 14772e5d4a8fSHaim Dreyfuss } 14782e5d4a8fSHaim Dreyfuss 14792e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 14802e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 14812e5d4a8fSHaim Dreyfuss { 14822e5d4a8fSHaim Dreyfuss int i, last_vector; 14832e5d4a8fSHaim Dreyfuss 14842e5d4a8fSHaim Dreyfuss last_vector = trans_pcie->trans->num_rx_queues; 14852e5d4a8fSHaim Dreyfuss 14862e5d4a8fSHaim Dreyfuss for (i = 0; i < trans_pcie->allocated_vector; i++) { 14872e5d4a8fSHaim Dreyfuss int ret; 14882e5d4a8fSHaim Dreyfuss 14892e5d4a8fSHaim Dreyfuss ret = request_threaded_irq(trans_pcie->msix_entries[i].vector, 14902e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 14912e5d4a8fSHaim Dreyfuss (i == last_vector) ? 14922e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 14932e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 14942e5d4a8fSHaim Dreyfuss IRQF_SHARED, 14952e5d4a8fSHaim Dreyfuss DRV_NAME, 14962e5d4a8fSHaim Dreyfuss &trans_pcie->msix_entries[i]); 14972e5d4a8fSHaim Dreyfuss if (ret) { 14982e5d4a8fSHaim Dreyfuss int j; 14992e5d4a8fSHaim Dreyfuss 15002e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 15012e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 15022e5d4a8fSHaim Dreyfuss for (j = 0; j < i; j++) 15038d80717aSHaim Dreyfuss free_irq(trans_pcie->msix_entries[j].vector, 15048d80717aSHaim Dreyfuss &trans_pcie->msix_entries[j]); 15052e5d4a8fSHaim Dreyfuss pci_disable_msix(pdev); 15062e5d4a8fSHaim Dreyfuss return ret; 15072e5d4a8fSHaim Dreyfuss } 15082e5d4a8fSHaim Dreyfuss } 15092e5d4a8fSHaim Dreyfuss 15102e5d4a8fSHaim Dreyfuss return 0; 15112e5d4a8fSHaim Dreyfuss } 15122e5d4a8fSHaim Dreyfuss 1513e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1514e705c121SKalle Valo { 1515e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1516e705c121SKalle Valo bool hw_rfkill; 1517e705c121SKalle Valo int err; 1518e705c121SKalle Valo 1519e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1520e705c121SKalle Valo 1521e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1522e705c121SKalle Valo if (err) { 1523e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1524e705c121SKalle Valo return err; 1525e705c121SKalle Valo } 1526e705c121SKalle Valo 1527e705c121SKalle Valo /* Reset the entire device */ 1528e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); 1529e705c121SKalle Valo 1530e705c121SKalle Valo usleep_range(10, 15); 1531e705c121SKalle Valo 1532e705c121SKalle Valo iwl_pcie_apm_init(trans); 1533e705c121SKalle Valo 15342e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 1535e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1536e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1537e705c121SKalle Valo 1538e705c121SKalle Valo /* Set is_down to false here so that...*/ 1539e705c121SKalle Valo trans_pcie->is_down = false; 1540e705c121SKalle Valo 1541e705c121SKalle Valo hw_rfkill = iwl_is_rfkill_set(trans); 1542e705c121SKalle Valo if (hw_rfkill) 1543e705c121SKalle Valo set_bit(STATUS_RFKILL, &trans->status); 1544e705c121SKalle Valo else 1545e705c121SKalle Valo clear_bit(STATUS_RFKILL, &trans->status); 1546e705c121SKalle Valo /* ... rfkill can call stop_device and set it false if needed */ 1547e705c121SKalle Valo iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1548e705c121SKalle Valo 15494cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 15504cbb8e50SLuciano Coelho if (low_power) 15514cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 15524cbb8e50SLuciano Coelho 1553e705c121SKalle Valo return 0; 1554e705c121SKalle Valo } 1555e705c121SKalle Valo 1556e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1557e705c121SKalle Valo { 1558e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1559e705c121SKalle Valo int ret; 1560e705c121SKalle Valo 1561e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1562e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1563e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1564e705c121SKalle Valo 1565e705c121SKalle Valo return ret; 1566e705c121SKalle Valo } 1567e705c121SKalle Valo 1568e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1569e705c121SKalle Valo { 1570e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1571e705c121SKalle Valo 1572e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1573e705c121SKalle Valo 1574e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1575e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1576e705c121SKalle Valo iwl_disable_interrupts(trans); 1577e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1578e705c121SKalle Valo 1579e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1580e705c121SKalle Valo 1581e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 1582e705c121SKalle Valo iwl_disable_interrupts(trans); 1583e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 1584e705c121SKalle Valo 1585e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1586e705c121SKalle Valo 1587e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1588e705c121SKalle Valo 15892e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1590e705c121SKalle Valo } 1591e705c121SKalle Valo 1592e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1593e705c121SKalle Valo { 1594e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1595e705c121SKalle Valo } 1596e705c121SKalle Valo 1597e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1598e705c121SKalle Valo { 1599e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1600e705c121SKalle Valo } 1601e705c121SKalle Valo 1602e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1603e705c121SKalle Valo { 1604e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1605e705c121SKalle Valo } 1606e705c121SKalle Valo 1607e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1608e705c121SKalle Valo { 1609e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1610e705c121SKalle Valo ((reg & 0x000FFFFF) | (3 << 24))); 1611e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1612e705c121SKalle Valo } 1613e705c121SKalle Valo 1614e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1615e705c121SKalle Valo u32 val) 1616e705c121SKalle Valo { 1617e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1618e705c121SKalle Valo ((addr & 0x000FFFFF) | (3 << 24))); 1619e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1620e705c121SKalle Valo } 1621e705c121SKalle Valo 1622e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1623e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1624e705c121SKalle Valo { 1625e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1626e705c121SKalle Valo 1627e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1628e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1629e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1630e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1631e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1632e705c121SKalle Valo else 1633e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1634e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1635e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1636e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1637e705c121SKalle Valo 16386c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 16396c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 16406c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1641e705c121SKalle Valo 1642e705c121SKalle Valo trans_pcie->wide_cmd_header = trans_cfg->wide_cmd_header; 1643e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1644e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 164541837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1646e705c121SKalle Valo 164739bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 164839bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 164939bdb17eSSharon Dvir 1650e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1651e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1652e705c121SKalle Valo * As this function may be called again in some corner cases don't 1653e705c121SKalle Valo * do anything if NAPI was already initialized. 1654e705c121SKalle Valo */ 1655bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1656e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1657e705c121SKalle Valo } 1658e705c121SKalle Valo 1659e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1660e705c121SKalle Valo { 1661e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16626eb5e529SEmmanuel Grumbach int i; 1663e705c121SKalle Valo 16642e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1665e705c121SKalle Valo 1666e705c121SKalle Valo iwl_pcie_tx_free(trans); 1667e705c121SKalle Valo iwl_pcie_rx_free(trans); 1668e705c121SKalle Valo 16692e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 16702e5d4a8fSHaim Dreyfuss for (i = 0; i < trans_pcie->allocated_vector; i++) 16712e5d4a8fSHaim Dreyfuss free_irq(trans_pcie->msix_entries[i].vector, 16722e5d4a8fSHaim Dreyfuss &trans_pcie->msix_entries[i]); 16732e5d4a8fSHaim Dreyfuss 16742e5d4a8fSHaim Dreyfuss pci_disable_msix(trans_pcie->pci_dev); 16752e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 16762e5d4a8fSHaim Dreyfuss } else { 1677e705c121SKalle Valo free_irq(trans_pcie->pci_dev->irq, trans); 16782e5d4a8fSHaim Dreyfuss 1679e705c121SKalle Valo iwl_pcie_free_ict(trans); 1680e705c121SKalle Valo 1681e705c121SKalle Valo pci_disable_msi(trans_pcie->pci_dev); 16822e5d4a8fSHaim Dreyfuss } 1683e705c121SKalle Valo iounmap(trans_pcie->hw_base); 1684e705c121SKalle Valo pci_release_regions(trans_pcie->pci_dev); 1685e705c121SKalle Valo pci_disable_device(trans_pcie->pci_dev); 1686e705c121SKalle Valo 1687e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1688e705c121SKalle Valo 16896eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 16906eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 16916eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 16926eb5e529SEmmanuel Grumbach 16936eb5e529SEmmanuel Grumbach if (p->page) 16946eb5e529SEmmanuel Grumbach __free_page(p->page); 16956eb5e529SEmmanuel Grumbach } 16966eb5e529SEmmanuel Grumbach 16976eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1698a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1699e705c121SKalle Valo iwl_trans_free(trans); 1700e705c121SKalle Valo } 1701e705c121SKalle Valo 1702e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1703e705c121SKalle Valo { 1704e705c121SKalle Valo if (state) 1705e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1706e705c121SKalle Valo else 1707e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1708e705c121SKalle Valo } 1709e705c121SKalle Valo 171023ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1711e705c121SKalle Valo unsigned long *flags) 1712e705c121SKalle Valo { 1713e705c121SKalle Valo int ret; 1714e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1715e705c121SKalle Valo 1716e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1717e705c121SKalle Valo 1718e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1719e705c121SKalle Valo goto out; 1720e705c121SKalle Valo 1721e705c121SKalle Valo /* this bit wakes up the NIC */ 1722e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1723e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1724e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) 1725e705c121SKalle Valo udelay(2); 1726e705c121SKalle Valo 1727e705c121SKalle Valo /* 1728e705c121SKalle Valo * These bits say the device is running, and should keep running for 1729e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1730e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1731e705c121SKalle Valo * 3945 and 4965 have volatile SRAM, and must save/restore contents 1732e705c121SKalle Valo * to/from host DRAM when sleeping/waking for power-saving. 1733e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1734e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1735e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1736e705c121SKalle Valo * to keep device from sleeping. 1737e705c121SKalle Valo * 1738e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1739e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1740e705c121SKalle Valo * is just for hardware register access; but GP1 MAC_SLEEP check is a 1741e705c121SKalle Valo * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log). 1742e705c121SKalle Valo * 1743e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1744e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1745e705c121SKalle Valo */ 1746e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1747e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1748e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1749e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1750e705c121SKalle Valo if (unlikely(ret < 0)) { 1751e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1752e705c121SKalle Valo WARN_ONCE(1, 1753e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 175423ba9340SEmmanuel Grumbach iwl_read32(trans, CSR_GP_CNTRL)); 1755e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1756e705c121SKalle Valo return false; 1757e705c121SKalle Valo } 1758e705c121SKalle Valo 1759e705c121SKalle Valo out: 1760e705c121SKalle Valo /* 1761e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 1762e705c121SKalle Valo * track nic_access anyway. 1763e705c121SKalle Valo */ 1764e705c121SKalle Valo __release(&trans_pcie->reg_lock); 1765e705c121SKalle Valo return true; 1766e705c121SKalle Valo } 1767e705c121SKalle Valo 1768e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1769e705c121SKalle Valo unsigned long *flags) 1770e705c121SKalle Valo { 1771e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1772e705c121SKalle Valo 1773e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1774e705c121SKalle Valo 1775e705c121SKalle Valo /* 1776e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 1777e705c121SKalle Valo * track nic_access anyway. 1778e705c121SKalle Valo */ 1779e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 1780e705c121SKalle Valo 1781e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1782e705c121SKalle Valo goto out; 1783e705c121SKalle Valo 1784e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 1785e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1786e705c121SKalle Valo /* 1787e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 1788e705c121SKalle Valo * any previous writes, but we need the write that clears the 1789e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 1790e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 1791e705c121SKalle Valo */ 1792e705c121SKalle Valo mmiowb(); 1793e705c121SKalle Valo out: 1794e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1795e705c121SKalle Valo } 1796e705c121SKalle Valo 1797e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1798e705c121SKalle Valo void *buf, int dwords) 1799e705c121SKalle Valo { 1800e705c121SKalle Valo unsigned long flags; 1801e705c121SKalle Valo int offs, ret = 0; 1802e705c121SKalle Valo u32 *vals = buf; 1803e705c121SKalle Valo 180423ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1805e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 1806e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1807e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 1808e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1809e705c121SKalle Valo } else { 1810e705c121SKalle Valo ret = -EBUSY; 1811e705c121SKalle Valo } 1812e705c121SKalle Valo return ret; 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 1815e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1816e705c121SKalle Valo const void *buf, int dwords) 1817e705c121SKalle Valo { 1818e705c121SKalle Valo unsigned long flags; 1819e705c121SKalle Valo int offs, ret = 0; 1820e705c121SKalle Valo const u32 *vals = buf; 1821e705c121SKalle Valo 182223ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 1823e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 1824e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 1825e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 1826e705c121SKalle Valo vals ? vals[offs] : 0); 1827e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 1828e705c121SKalle Valo } else { 1829e705c121SKalle Valo ret = -EBUSY; 1830e705c121SKalle Valo } 1831e705c121SKalle Valo return ret; 1832e705c121SKalle Valo } 1833e705c121SKalle Valo 1834e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 1835e705c121SKalle Valo unsigned long txqs, 1836e705c121SKalle Valo bool freeze) 1837e705c121SKalle Valo { 1838e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1839e705c121SKalle Valo int queue; 1840e705c121SKalle Valo 1841e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 1842e705c121SKalle Valo struct iwl_txq *txq = &trans_pcie->txq[queue]; 1843e705c121SKalle Valo unsigned long now; 1844e705c121SKalle Valo 1845e705c121SKalle Valo spin_lock_bh(&txq->lock); 1846e705c121SKalle Valo 1847e705c121SKalle Valo now = jiffies; 1848e705c121SKalle Valo 1849e705c121SKalle Valo if (txq->frozen == freeze) 1850e705c121SKalle Valo goto next_queue; 1851e705c121SKalle Valo 1852e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 1853e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 1854e705c121SKalle Valo 1855e705c121SKalle Valo txq->frozen = freeze; 1856e705c121SKalle Valo 1857e705c121SKalle Valo if (txq->q.read_ptr == txq->q.write_ptr) 1858e705c121SKalle Valo goto next_queue; 1859e705c121SKalle Valo 1860e705c121SKalle Valo if (freeze) { 1861e705c121SKalle Valo if (unlikely(time_after(now, 1862e705c121SKalle Valo txq->stuck_timer.expires))) { 1863e705c121SKalle Valo /* 1864e705c121SKalle Valo * The timer should have fired, maybe it is 1865e705c121SKalle Valo * spinning right now on the lock. 1866e705c121SKalle Valo */ 1867e705c121SKalle Valo goto next_queue; 1868e705c121SKalle Valo } 1869e705c121SKalle Valo /* remember how long until the timer fires */ 1870e705c121SKalle Valo txq->frozen_expiry_remainder = 1871e705c121SKalle Valo txq->stuck_timer.expires - now; 1872e705c121SKalle Valo del_timer(&txq->stuck_timer); 1873e705c121SKalle Valo goto next_queue; 1874e705c121SKalle Valo } 1875e705c121SKalle Valo 1876e705c121SKalle Valo /* 1877e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 1878e705c121SKalle Valo * remainder before it froze 1879e705c121SKalle Valo */ 1880e705c121SKalle Valo mod_timer(&txq->stuck_timer, 1881e705c121SKalle Valo now + txq->frozen_expiry_remainder); 1882e705c121SKalle Valo 1883e705c121SKalle Valo next_queue: 1884e705c121SKalle Valo spin_unlock_bh(&txq->lock); 1885e705c121SKalle Valo } 1886e705c121SKalle Valo } 1887e705c121SKalle Valo 18880cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 18890cd58eaaSEmmanuel Grumbach { 18900cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18910cd58eaaSEmmanuel Grumbach int i; 18920cd58eaaSEmmanuel Grumbach 18930cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 18940cd58eaaSEmmanuel Grumbach struct iwl_txq *txq = &trans_pcie->txq[i]; 18950cd58eaaSEmmanuel Grumbach 18960cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 18970cd58eaaSEmmanuel Grumbach continue; 18980cd58eaaSEmmanuel Grumbach 18990cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 19000cd58eaaSEmmanuel Grumbach 19010cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 19020cd58eaaSEmmanuel Grumbach txq->block--; 19030cd58eaaSEmmanuel Grumbach if (!txq->block) { 19040cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 19050cd58eaaSEmmanuel Grumbach txq->q.write_ptr | (i << 8)); 19060cd58eaaSEmmanuel Grumbach } 19070cd58eaaSEmmanuel Grumbach } else if (block) { 19080cd58eaaSEmmanuel Grumbach txq->block++; 19090cd58eaaSEmmanuel Grumbach } 19100cd58eaaSEmmanuel Grumbach 19110cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 19120cd58eaaSEmmanuel Grumbach } 19130cd58eaaSEmmanuel Grumbach } 19140cd58eaaSEmmanuel Grumbach 1915e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 1916e705c121SKalle Valo 1917e705c121SKalle Valo static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) 1918e705c121SKalle Valo { 1919e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1920e705c121SKalle Valo struct iwl_txq *txq; 1921e705c121SKalle Valo struct iwl_queue *q; 1922e705c121SKalle Valo int cnt; 1923e705c121SKalle Valo unsigned long now = jiffies; 1924e705c121SKalle Valo u32 scd_sram_addr; 1925e705c121SKalle Valo u8 buf[16]; 1926e705c121SKalle Valo int ret = 0; 1927e705c121SKalle Valo 1928e705c121SKalle Valo /* waiting for all the tx frames complete might take a while */ 1929e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1930e705c121SKalle Valo u8 wr_ptr; 1931e705c121SKalle Valo 1932e705c121SKalle Valo if (cnt == trans_pcie->cmd_queue) 1933e705c121SKalle Valo continue; 1934e705c121SKalle Valo if (!test_bit(cnt, trans_pcie->queue_used)) 1935e705c121SKalle Valo continue; 1936e705c121SKalle Valo if (!(BIT(cnt) & txq_bm)) 1937e705c121SKalle Valo continue; 1938e705c121SKalle Valo 1939e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt); 1940e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 1941e705c121SKalle Valo q = &txq->q; 1942e705c121SKalle Valo wr_ptr = ACCESS_ONCE(q->write_ptr); 1943e705c121SKalle Valo 1944e705c121SKalle Valo while (q->read_ptr != ACCESS_ONCE(q->write_ptr) && 1945e705c121SKalle Valo !time_after(jiffies, 1946e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 1947e705c121SKalle Valo u8 write_ptr = ACCESS_ONCE(q->write_ptr); 1948e705c121SKalle Valo 1949e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 1950e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 1951e705c121SKalle Valo wr_ptr, write_ptr)) 1952e705c121SKalle Valo return -ETIMEDOUT; 1953e705c121SKalle Valo msleep(1); 1954e705c121SKalle Valo } 1955e705c121SKalle Valo 1956e705c121SKalle Valo if (q->read_ptr != q->write_ptr) { 1957e705c121SKalle Valo IWL_ERR(trans, 1958e705c121SKalle Valo "fail to flush all tx fifo queues Q %d\n", cnt); 1959e705c121SKalle Valo ret = -ETIMEDOUT; 1960e705c121SKalle Valo break; 1961e705c121SKalle Valo } 1962e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt); 1963e705c121SKalle Valo } 1964e705c121SKalle Valo 1965e705c121SKalle Valo if (!ret) 1966e705c121SKalle Valo return 0; 1967e705c121SKalle Valo 1968e705c121SKalle Valo IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", 1969e705c121SKalle Valo txq->q.read_ptr, txq->q.write_ptr); 1970e705c121SKalle Valo 1971e705c121SKalle Valo scd_sram_addr = trans_pcie->scd_base_addr + 1972e705c121SKalle Valo SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); 1973e705c121SKalle Valo iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); 1974e705c121SKalle Valo 1975e705c121SKalle Valo iwl_print_hex_error(trans, buf, sizeof(buf)); 1976e705c121SKalle Valo 1977e705c121SKalle Valo for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) 1978e705c121SKalle Valo IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, 1979e705c121SKalle Valo iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); 1980e705c121SKalle Valo 1981e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 1982e705c121SKalle Valo u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); 1983e705c121SKalle Valo u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 1984e705c121SKalle Valo bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 1985e705c121SKalle Valo u32 tbl_dw = 1986e705c121SKalle Valo iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + 1987e705c121SKalle Valo SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); 1988e705c121SKalle Valo 1989e705c121SKalle Valo if (cnt & 0x1) 1990e705c121SKalle Valo tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; 1991e705c121SKalle Valo else 1992e705c121SKalle Valo tbl_dw = tbl_dw & 0x0000FFFF; 1993e705c121SKalle Valo 1994e705c121SKalle Valo IWL_ERR(trans, 1995e705c121SKalle Valo "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", 1996e705c121SKalle Valo cnt, active ? "" : "in", fifo, tbl_dw, 1997e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & 1998e705c121SKalle Valo (TFD_QUEUE_SIZE_MAX - 1), 1999e705c121SKalle Valo iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); 2000e705c121SKalle Valo } 2001e705c121SKalle Valo 2002e705c121SKalle Valo return ret; 2003e705c121SKalle Valo } 2004e705c121SKalle Valo 2005e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2006e705c121SKalle Valo u32 mask, u32 value) 2007e705c121SKalle Valo { 2008e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2009e705c121SKalle Valo unsigned long flags; 2010e705c121SKalle Valo 2011e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2012e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2013e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2014e705c121SKalle Valo } 2015e705c121SKalle Valo 2016c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2017e705c121SKalle Valo { 2018e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2019e705c121SKalle Valo 2020e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2021e705c121SKalle Valo return; 2022e705c121SKalle Valo 2023b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 20245d93f3a2SLuca Coelho 20255d93f3a2SLuca Coelho #ifdef CONFIG_PM 20265d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 20275d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 20285d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2029e705c121SKalle Valo } 2030e705c121SKalle Valo 2031c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2032e705c121SKalle Valo { 2033e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2034e705c121SKalle Valo 2035e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2036e705c121SKalle Valo return; 2037e705c121SKalle Valo 2038b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2039b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2040b3ff1270SLuca Coelho 20415d93f3a2SLuca Coelho #ifdef CONFIG_PM 20425d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 20435d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 20445d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2045e705c121SKalle Valo } 2046e705c121SKalle Valo 2047e705c121SKalle Valo static const char *get_csr_string(int cmd) 2048e705c121SKalle Valo { 2049e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2050e705c121SKalle Valo switch (cmd) { 2051e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2052e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2053e705c121SKalle Valo IWL_CMD(CSR_INT); 2054e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2055e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2056e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2057e705c121SKalle Valo IWL_CMD(CSR_RESET); 2058e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2059e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2060e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2061e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2062e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2063e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2064e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2065e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2066e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2067e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2068e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2069e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2070e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2071e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2072e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2073e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2074e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2075e705c121SKalle Valo default: 2076e705c121SKalle Valo return "UNKNOWN"; 2077e705c121SKalle Valo } 2078e705c121SKalle Valo #undef IWL_CMD 2079e705c121SKalle Valo } 2080e705c121SKalle Valo 2081e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2082e705c121SKalle Valo { 2083e705c121SKalle Valo int i; 2084e705c121SKalle Valo static const u32 csr_tbl[] = { 2085e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2086e705c121SKalle Valo CSR_INT_COALESCING, 2087e705c121SKalle Valo CSR_INT, 2088e705c121SKalle Valo CSR_INT_MASK, 2089e705c121SKalle Valo CSR_FH_INT_STATUS, 2090e705c121SKalle Valo CSR_GPIO_IN, 2091e705c121SKalle Valo CSR_RESET, 2092e705c121SKalle Valo CSR_GP_CNTRL, 2093e705c121SKalle Valo CSR_HW_REV, 2094e705c121SKalle Valo CSR_EEPROM_REG, 2095e705c121SKalle Valo CSR_EEPROM_GP, 2096e705c121SKalle Valo CSR_OTP_GP_REG, 2097e705c121SKalle Valo CSR_GIO_REG, 2098e705c121SKalle Valo CSR_GP_UCODE_REG, 2099e705c121SKalle Valo CSR_GP_DRIVER_REG, 2100e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2101e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2102e705c121SKalle Valo CSR_LED_REG, 2103e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2104e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2105e705c121SKalle Valo CSR_ANA_PLL_CFG, 2106e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2107e705c121SKalle Valo CSR_HW_REV_WA_REG, 2108e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2109e705c121SKalle Valo }; 2110e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2111e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2112e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2113e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2114e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2115e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2116e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2117e705c121SKalle Valo } 2118e705c121SKalle Valo } 2119e705c121SKalle Valo 2120e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2121e705c121SKalle Valo /* create and remove of files */ 2122e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2123e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 2124e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 2125e705c121SKalle Valo goto err; \ 2126e705c121SKalle Valo } while (0) 2127e705c121SKalle Valo 2128e705c121SKalle Valo /* file operation */ 2129e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2130e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2131e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2132e705c121SKalle Valo .open = simple_open, \ 2133e705c121SKalle Valo .llseek = generic_file_llseek, \ 2134e705c121SKalle Valo }; 2135e705c121SKalle Valo 2136e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2137e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2138e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2139e705c121SKalle Valo .open = simple_open, \ 2140e705c121SKalle Valo .llseek = generic_file_llseek, \ 2141e705c121SKalle Valo }; 2142e705c121SKalle Valo 2143e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2144e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2145e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2146e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2147e705c121SKalle Valo .open = simple_open, \ 2148e705c121SKalle Valo .llseek = generic_file_llseek, \ 2149e705c121SKalle Valo }; 2150e705c121SKalle Valo 2151e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2152e705c121SKalle Valo char __user *user_buf, 2153e705c121SKalle Valo size_t count, loff_t *ppos) 2154e705c121SKalle Valo { 2155e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2156e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2157e705c121SKalle Valo struct iwl_txq *txq; 2158e705c121SKalle Valo struct iwl_queue *q; 2159e705c121SKalle Valo char *buf; 2160e705c121SKalle Valo int pos = 0; 2161e705c121SKalle Valo int cnt; 2162e705c121SKalle Valo int ret; 2163e705c121SKalle Valo size_t bufsz; 2164e705c121SKalle Valo 2165e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2166e705c121SKalle Valo 2167e705c121SKalle Valo if (!trans_pcie->txq) 2168e705c121SKalle Valo return -EAGAIN; 2169e705c121SKalle Valo 2170e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2171e705c121SKalle Valo if (!buf) 2172e705c121SKalle Valo return -ENOMEM; 2173e705c121SKalle Valo 2174e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2175e705c121SKalle Valo txq = &trans_pcie->txq[cnt]; 2176e705c121SKalle Valo q = &txq->q; 2177e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2178e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2179e705c121SKalle Valo cnt, q->read_ptr, q->write_ptr, 2180e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2181e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2182e705c121SKalle Valo txq->need_update, txq->frozen, 2183e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2184e705c121SKalle Valo } 2185e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2186e705c121SKalle Valo kfree(buf); 2187e705c121SKalle Valo return ret; 2188e705c121SKalle Valo } 2189e705c121SKalle Valo 2190e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2191e705c121SKalle Valo char __user *user_buf, 2192e705c121SKalle Valo size_t count, loff_t *ppos) 2193e705c121SKalle Valo { 2194e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2195e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 219678485054SSara Sharon char *buf; 219778485054SSara Sharon int pos = 0, i, ret; 219878485054SSara Sharon size_t bufsz = sizeof(buf); 2199e705c121SKalle Valo 220078485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 220178485054SSara Sharon 220278485054SSara Sharon if (!trans_pcie->rxq) 220378485054SSara Sharon return -EAGAIN; 220478485054SSara Sharon 220578485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 220678485054SSara Sharon if (!buf) 220778485054SSara Sharon return -ENOMEM; 220878485054SSara Sharon 220978485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 221078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 221178485054SSara Sharon 221278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 221378485054SSara Sharon i); 221478485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2215e705c121SKalle Valo rxq->read); 221678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2217e705c121SKalle Valo rxq->write); 221878485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2219e705c121SKalle Valo rxq->write_actual); 222078485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2221e705c121SKalle Valo rxq->need_update); 222278485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2223e705c121SKalle Valo rxq->free_count); 2224e705c121SKalle Valo if (rxq->rb_stts) { 222578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 222678485054SSara Sharon "\tclosed_rb_num: %u\n", 222778485054SSara Sharon le16_to_cpu(rxq->rb_stts->closed_rb_num) & 222878485054SSara Sharon 0x0FFF); 2229e705c121SKalle Valo } else { 2230e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 223178485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2232e705c121SKalle Valo } 223378485054SSara Sharon } 223478485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 223578485054SSara Sharon kfree(buf); 223678485054SSara Sharon 223778485054SSara Sharon return ret; 2238e705c121SKalle Valo } 2239e705c121SKalle Valo 2240e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2241e705c121SKalle Valo char __user *user_buf, 2242e705c121SKalle Valo size_t count, loff_t *ppos) 2243e705c121SKalle Valo { 2244e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2245e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2246e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2247e705c121SKalle Valo 2248e705c121SKalle Valo int pos = 0; 2249e705c121SKalle Valo char *buf; 2250e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2251e705c121SKalle Valo ssize_t ret; 2252e705c121SKalle Valo 2253e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2254e705c121SKalle Valo if (!buf) 2255e705c121SKalle Valo return -ENOMEM; 2256e705c121SKalle Valo 2257e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2258e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2259e705c121SKalle Valo 2260e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2261e705c121SKalle Valo isr_stats->hw); 2262e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2263e705c121SKalle Valo isr_stats->sw); 2264e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2265e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2266e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2267e705c121SKalle Valo isr_stats->err_code); 2268e705c121SKalle Valo } 2269e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2270e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2271e705c121SKalle Valo isr_stats->sch); 2272e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2273e705c121SKalle Valo isr_stats->alive); 2274e705c121SKalle Valo #endif 2275e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2276e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2277e705c121SKalle Valo 2278e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2279e705c121SKalle Valo isr_stats->ctkill); 2280e705c121SKalle Valo 2281e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2282e705c121SKalle Valo isr_stats->wakeup); 2283e705c121SKalle Valo 2284e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2285e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2286e705c121SKalle Valo 2287e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2288e705c121SKalle Valo isr_stats->tx); 2289e705c121SKalle Valo 2290e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2291e705c121SKalle Valo isr_stats->unhandled); 2292e705c121SKalle Valo 2293e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2294e705c121SKalle Valo kfree(buf); 2295e705c121SKalle Valo return ret; 2296e705c121SKalle Valo } 2297e705c121SKalle Valo 2298e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2299e705c121SKalle Valo const char __user *user_buf, 2300e705c121SKalle Valo size_t count, loff_t *ppos) 2301e705c121SKalle Valo { 2302e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2303e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2304e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2305e705c121SKalle Valo 2306e705c121SKalle Valo char buf[8]; 2307e705c121SKalle Valo int buf_size; 2308e705c121SKalle Valo u32 reset_flag; 2309e705c121SKalle Valo 2310e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2311e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2312e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2313e705c121SKalle Valo return -EFAULT; 2314e705c121SKalle Valo if (sscanf(buf, "%x", &reset_flag) != 1) 2315e705c121SKalle Valo return -EFAULT; 2316e705c121SKalle Valo if (reset_flag == 0) 2317e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2318e705c121SKalle Valo 2319e705c121SKalle Valo return count; 2320e705c121SKalle Valo } 2321e705c121SKalle Valo 2322e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2323e705c121SKalle Valo const char __user *user_buf, 2324e705c121SKalle Valo size_t count, loff_t *ppos) 2325e705c121SKalle Valo { 2326e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2327e705c121SKalle Valo char buf[8]; 2328e705c121SKalle Valo int buf_size; 2329e705c121SKalle Valo int csr; 2330e705c121SKalle Valo 2331e705c121SKalle Valo memset(buf, 0, sizeof(buf)); 2332e705c121SKalle Valo buf_size = min(count, sizeof(buf) - 1); 2333e705c121SKalle Valo if (copy_from_user(buf, user_buf, buf_size)) 2334e705c121SKalle Valo return -EFAULT; 2335e705c121SKalle Valo if (sscanf(buf, "%d", &csr) != 1) 2336e705c121SKalle Valo return -EFAULT; 2337e705c121SKalle Valo 2338e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2339e705c121SKalle Valo 2340e705c121SKalle Valo return count; 2341e705c121SKalle Valo } 2342e705c121SKalle Valo 2343e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2344e705c121SKalle Valo char __user *user_buf, 2345e705c121SKalle Valo size_t count, loff_t *ppos) 2346e705c121SKalle Valo { 2347e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2348e705c121SKalle Valo char *buf = NULL; 2349e705c121SKalle Valo ssize_t ret; 2350e705c121SKalle Valo 2351e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2352e705c121SKalle Valo if (ret < 0) 2353e705c121SKalle Valo return ret; 2354e705c121SKalle Valo if (!buf) 2355e705c121SKalle Valo return -EINVAL; 2356e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2357e705c121SKalle Valo kfree(buf); 2358e705c121SKalle Valo return ret; 2359e705c121SKalle Valo } 2360e705c121SKalle Valo 2361e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2362e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2363e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2364e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2365e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2366e705c121SKalle Valo 2367f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2368f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2369e705c121SKalle Valo { 2370f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2371f8a1edb7SJohannes Berg 2372e705c121SKalle Valo DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2373e705c121SKalle Valo DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2374e705c121SKalle Valo DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2375e705c121SKalle Valo DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2376e705c121SKalle Valo DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2377e705c121SKalle Valo return 0; 2378e705c121SKalle Valo 2379e705c121SKalle Valo err: 2380e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2381e705c121SKalle Valo return -ENOMEM; 2382e705c121SKalle Valo } 2383e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2384e705c121SKalle Valo 2385e705c121SKalle Valo static u32 iwl_trans_pcie_get_cmdlen(struct iwl_tfd *tfd) 2386e705c121SKalle Valo { 2387e705c121SKalle Valo u32 cmdlen = 0; 2388e705c121SKalle Valo int i; 2389e705c121SKalle Valo 2390e705c121SKalle Valo for (i = 0; i < IWL_NUM_OF_TBS; i++) 2391e705c121SKalle Valo cmdlen += iwl_pcie_tfd_tb_get_len(tfd, i); 2392e705c121SKalle Valo 2393e705c121SKalle Valo return cmdlen; 2394e705c121SKalle Valo } 2395e705c121SKalle Valo 2396e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2397e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2398e705c121SKalle Valo int allocated_rb_nums) 2399e705c121SKalle Valo { 2400e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2401e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 240278485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 240378485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2404e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2405e705c121SKalle Valo 2406e705c121SKalle Valo spin_lock(&rxq->lock); 2407e705c121SKalle Valo 2408e705c121SKalle Valo r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2409e705c121SKalle Valo 2410e705c121SKalle Valo for (i = rxq->read, j = 0; 2411e705c121SKalle Valo i != r && j < allocated_rb_nums; 2412e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2413e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2414e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2415e705c121SKalle Valo 2416e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2417e705c121SKalle Valo DMA_FROM_DEVICE); 2418e705c121SKalle Valo 2419e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2420e705c121SKalle Valo 2421e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2422e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2423e705c121SKalle Valo rb = (void *)(*data)->data; 2424e705c121SKalle Valo rb->index = cpu_to_le32(i); 2425e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2426e705c121SKalle Valo /* remap the page for the free benefit */ 2427e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2428e705c121SKalle Valo max_len, 2429e705c121SKalle Valo DMA_FROM_DEVICE); 2430e705c121SKalle Valo 2431e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2432e705c121SKalle Valo } 2433e705c121SKalle Valo 2434e705c121SKalle Valo spin_unlock(&rxq->lock); 2435e705c121SKalle Valo 2436e705c121SKalle Valo return rb_len; 2437e705c121SKalle Valo } 2438e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2439e705c121SKalle Valo 2440e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2441e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2442e705c121SKalle Valo { 2443e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2444e705c121SKalle Valo __le32 *val; 2445e705c121SKalle Valo int i; 2446e705c121SKalle Valo 2447e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2448e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2449e705c121SKalle Valo val = (void *)(*data)->data; 2450e705c121SKalle Valo 2451e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2452e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2453e705c121SKalle Valo 2454e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2455e705c121SKalle Valo 2456e705c121SKalle Valo return csr_len; 2457e705c121SKalle Valo } 2458e705c121SKalle Valo 2459e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2460e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2461e705c121SKalle Valo { 2462e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2463e705c121SKalle Valo unsigned long flags; 2464e705c121SKalle Valo __le32 *val; 2465e705c121SKalle Valo int i; 2466e705c121SKalle Valo 246723ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2468e705c121SKalle Valo return 0; 2469e705c121SKalle Valo 2470e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2471e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2472e705c121SKalle Valo val = (void *)(*data)->data; 2473e705c121SKalle Valo 2474e705c121SKalle Valo for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32)) 2475e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2476e705c121SKalle Valo 2477e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2478e705c121SKalle Valo 2479e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2480e705c121SKalle Valo 2481e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2482e705c121SKalle Valo } 2483e705c121SKalle Valo 2484e705c121SKalle Valo static u32 2485e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2486e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2487e705c121SKalle Valo u32 monitor_len) 2488e705c121SKalle Valo { 2489e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2490e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2491e705c121SKalle Valo unsigned long flags; 2492e705c121SKalle Valo u32 i; 2493e705c121SKalle Valo 249423ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2495e705c121SKalle Valo return 0; 2496e705c121SKalle Valo 249714ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2498e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 249914ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 250014ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 250114ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2502e705c121SKalle Valo 2503e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2504e705c121SKalle Valo 2505e705c121SKalle Valo return monitor_len; 2506e705c121SKalle Valo } 2507e705c121SKalle Valo 2508e705c121SKalle Valo static u32 2509e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2510e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2511e705c121SKalle Valo u32 monitor_len) 2512e705c121SKalle Valo { 2513e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2514e705c121SKalle Valo u32 len = 0; 2515e705c121SKalle Valo 2516e705c121SKalle Valo if ((trans_pcie->fw_mon_page && 2517e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2518e705c121SKalle Valo trans->dbg_dest_tlv) { 2519e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2520e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2521e705c121SKalle Valo 2522e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2523e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2524e705c121SKalle Valo write_ptr = 2525e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2526e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2527e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2528e705c121SKalle Valo } else { 2529e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2530e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2531e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2532e705c121SKalle Valo } 2533e705c121SKalle Valo 2534e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2535e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2536e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2537e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2538e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2539e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2540e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2541e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2542e705c121SKalle Valo 2543e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 2544e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2545e705c121SKalle Valo /* 2546e705c121SKalle Valo * The firmware is now asserted, it won't write anything 2547e705c121SKalle Valo * to the buffer. CPU can take ownership to fetch the 2548e705c121SKalle Valo * data. The buffer will be handed back to the device 2549e705c121SKalle Valo * before the firmware will be restarted. 2550e705c121SKalle Valo */ 2551e705c121SKalle Valo dma_sync_single_for_cpu(trans->dev, 2552e705c121SKalle Valo trans_pcie->fw_mon_phys, 2553e705c121SKalle Valo trans_pcie->fw_mon_size, 2554e705c121SKalle Valo DMA_FROM_DEVICE); 2555e705c121SKalle Valo memcpy(fw_mon_data->data, 2556e705c121SKalle Valo page_address(trans_pcie->fw_mon_page), 2557e705c121SKalle Valo trans_pcie->fw_mon_size); 2558e705c121SKalle Valo 2559e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2560e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2561e705c121SKalle Valo /* 2562e705c121SKalle Valo * Update pointers to reflect actual values after 2563e705c121SKalle Valo * shifting 2564e705c121SKalle Valo */ 2565e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2566e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2567e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2568e705c121SKalle Valo monitor_len / sizeof(u32)); 2569e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2570e705c121SKalle Valo monitor_len = 2571e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2572e705c121SKalle Valo fw_mon_data, 2573e705c121SKalle Valo monitor_len); 2574e705c121SKalle Valo } else { 2575e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2576e705c121SKalle Valo monitor_len = 0; 2577e705c121SKalle Valo } 2578e705c121SKalle Valo 2579e705c121SKalle Valo len += monitor_len; 2580e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2581e705c121SKalle Valo } 2582e705c121SKalle Valo 2583e705c121SKalle Valo return len; 2584e705c121SKalle Valo } 2585e705c121SKalle Valo 2586e705c121SKalle Valo static struct iwl_trans_dump_data 2587e705c121SKalle Valo *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2588a80c7a69SEmmanuel Grumbach const struct iwl_fw_dbg_trigger_tlv *trigger) 2589e705c121SKalle Valo { 2590e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2591e705c121SKalle Valo struct iwl_fw_error_dump_data *data; 2592e705c121SKalle Valo struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue]; 2593e705c121SKalle Valo struct iwl_fw_error_dump_txcmd *txcmd; 2594e705c121SKalle Valo struct iwl_trans_dump_data *dump_data; 2595e705c121SKalle Valo u32 len, num_rbs; 2596e705c121SKalle Valo u32 monitor_len; 2597e705c121SKalle Valo int i, ptr; 259896a6497bSSara Sharon bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 259996a6497bSSara Sharon !trans->cfg->mq_rx_supported; 2600e705c121SKalle Valo 2601e705c121SKalle Valo /* transport dump header */ 2602e705c121SKalle Valo len = sizeof(*dump_data); 2603e705c121SKalle Valo 2604e705c121SKalle Valo /* host commands */ 2605e705c121SKalle Valo len += sizeof(*data) + 2606e705c121SKalle Valo cmdq->q.n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2607e705c121SKalle Valo 2608e705c121SKalle Valo /* FW monitor */ 2609e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2610e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2611e705c121SKalle Valo trans_pcie->fw_mon_size; 2612e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2613e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2614e705c121SKalle Valo u32 base, end; 2615e705c121SKalle Valo 2616e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2617e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2618e705c121SKalle Valo 2619e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2620e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2621e705c121SKalle Valo end = iwl_read_prph(trans, end) << 2622e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 2623e705c121SKalle Valo 2624e705c121SKalle Valo /* Make "end" point to the actual end */ 2625e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 || 2626e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2627e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 2628e705c121SKalle Valo monitor_len = end - base; 2629e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2630e705c121SKalle Valo monitor_len; 2631e705c121SKalle Valo } else { 2632e705c121SKalle Valo monitor_len = 0; 2633e705c121SKalle Valo } 2634e705c121SKalle Valo 2635e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2636e705c121SKalle Valo dump_data = vzalloc(len); 2637e705c121SKalle Valo if (!dump_data) 2638e705c121SKalle Valo return NULL; 2639e705c121SKalle Valo 2640e705c121SKalle Valo data = (void *)dump_data->data; 2641e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2642e705c121SKalle Valo dump_data->len = len; 2643e705c121SKalle Valo 2644e705c121SKalle Valo return dump_data; 2645e705c121SKalle Valo } 2646e705c121SKalle Valo 2647e705c121SKalle Valo /* CSR registers */ 2648e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 2649e705c121SKalle Valo 2650e705c121SKalle Valo /* FH registers */ 2651e705c121SKalle Valo len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2652e705c121SKalle Valo 2653e705c121SKalle Valo if (dump_rbs) { 265478485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 265578485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2656e705c121SKalle Valo /* RBs */ 265778485054SSara Sharon num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) 2658e705c121SKalle Valo & 0x0FFF; 265978485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2660e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 2661e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 2662e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 2663e705c121SKalle Valo } 2664e705c121SKalle Valo 2665e705c121SKalle Valo dump_data = vzalloc(len); 2666e705c121SKalle Valo if (!dump_data) 2667e705c121SKalle Valo return NULL; 2668e705c121SKalle Valo 2669e705c121SKalle Valo len = 0; 2670e705c121SKalle Valo data = (void *)dump_data->data; 2671e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2672e705c121SKalle Valo txcmd = (void *)data->data; 2673e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 2674e705c121SKalle Valo ptr = cmdq->q.write_ptr; 2675e705c121SKalle Valo for (i = 0; i < cmdq->q.n_window; i++) { 2676e705c121SKalle Valo u8 idx = get_cmd_index(&cmdq->q, ptr); 2677e705c121SKalle Valo u32 caplen, cmdlen; 2678e705c121SKalle Valo 2679e705c121SKalle Valo cmdlen = iwl_trans_pcie_get_cmdlen(&cmdq->tfds[ptr]); 2680e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2681e705c121SKalle Valo 2682e705c121SKalle Valo if (cmdlen) { 2683e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 2684e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 2685e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 2686e705c121SKalle Valo memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2687e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 2688e705c121SKalle Valo } 2689e705c121SKalle Valo 2690e705c121SKalle Valo ptr = iwl_queue_dec_wrap(ptr); 2691e705c121SKalle Valo } 2692e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 2693e705c121SKalle Valo 2694e705c121SKalle Valo data->len = cpu_to_le32(len); 2695e705c121SKalle Valo len += sizeof(*data); 2696e705c121SKalle Valo data = iwl_fw_error_next_data(data); 2697e705c121SKalle Valo 2698e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 2699e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2700e705c121SKalle Valo if (dump_rbs) 2701e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2702e705c121SKalle Valo 2703e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2704e705c121SKalle Valo 2705e705c121SKalle Valo dump_data->len = len; 2706e705c121SKalle Valo 2707e705c121SKalle Valo return dump_data; 2708e705c121SKalle Valo } 2709e705c121SKalle Valo 27104cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 27114cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 27124cbb8e50SLuciano Coelho { 27134cbb8e50SLuciano Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 27144cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 27154cbb8e50SLuciano Coelho 27164cbb8e50SLuciano Coelho return 0; 27174cbb8e50SLuciano Coelho } 27184cbb8e50SLuciano Coelho 27194cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 27204cbb8e50SLuciano Coelho { 27214cbb8e50SLuciano Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3) 27224cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 27234cbb8e50SLuciano Coelho } 27244cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 27254cbb8e50SLuciano Coelho 2726e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 2727e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 2728e705c121SKalle Valo .op_mode_leave = iwl_trans_pcie_op_mode_leave, 2729e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 2730e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 2731e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 2732e705c121SKalle Valo 2733e705c121SKalle Valo .d3_suspend = iwl_trans_pcie_d3_suspend, 2734e705c121SKalle Valo .d3_resume = iwl_trans_pcie_d3_resume, 2735e705c121SKalle Valo 27364cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 27374cbb8e50SLuciano Coelho .suspend = iwl_trans_pcie_suspend, 27384cbb8e50SLuciano Coelho .resume = iwl_trans_pcie_resume, 27394cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 27404cbb8e50SLuciano Coelho 2741e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 2742e705c121SKalle Valo 2743e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 2744e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 2745e705c121SKalle Valo 2746e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 2747e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 2748e705c121SKalle Valo 2749e705c121SKalle Valo .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty, 2750e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 27510cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 2752e705c121SKalle Valo 2753e705c121SKalle Valo .write8 = iwl_trans_pcie_write8, 2754e705c121SKalle Valo .write32 = iwl_trans_pcie_write32, 2755e705c121SKalle Valo .read32 = iwl_trans_pcie_read32, 2756e705c121SKalle Valo .read_prph = iwl_trans_pcie_read_prph, 2757e705c121SKalle Valo .write_prph = iwl_trans_pcie_write_prph, 2758e705c121SKalle Valo .read_mem = iwl_trans_pcie_read_mem, 2759e705c121SKalle Valo .write_mem = iwl_trans_pcie_write_mem, 2760e705c121SKalle Valo .configure = iwl_trans_pcie_configure, 2761e705c121SKalle Valo .set_pmi = iwl_trans_pcie_set_pmi, 2762e705c121SKalle Valo .grab_nic_access = iwl_trans_pcie_grab_nic_access, 2763e705c121SKalle Valo .release_nic_access = iwl_trans_pcie_release_nic_access, 2764e705c121SKalle Valo .set_bits_mask = iwl_trans_pcie_set_bits_mask, 2765e705c121SKalle Valo 2766e705c121SKalle Valo .ref = iwl_trans_pcie_ref, 2767e705c121SKalle Valo .unref = iwl_trans_pcie_unref, 2768e705c121SKalle Valo 2769e705c121SKalle Valo .dump_data = iwl_trans_pcie_dump_data, 2770e705c121SKalle Valo }; 2771e705c121SKalle Valo 2772e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 2773e705c121SKalle Valo const struct pci_device_id *ent, 2774e705c121SKalle Valo const struct iwl_cfg *cfg) 2775e705c121SKalle Valo { 2776e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 2777e705c121SKalle Valo struct iwl_trans *trans; 277896a6497bSSara Sharon int ret, addr_size; 2779e705c121SKalle Valo 2780e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 2781e705c121SKalle Valo &pdev->dev, cfg, &trans_ops_pcie, 0); 2782e705c121SKalle Valo if (!trans) 2783e705c121SKalle Valo return ERR_PTR(-ENOMEM); 2784e705c121SKalle Valo 2785e705c121SKalle Valo trans->max_skb_frags = IWL_PCIE_MAX_FRAGS; 2786e705c121SKalle Valo 2787e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2788e705c121SKalle Valo 2789e705c121SKalle Valo trans_pcie->trans = trans; 2790e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 2791e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 2792e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 2793e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 27946eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 27956eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 27966eb5e529SEmmanuel Grumbach ret = -ENOMEM; 27976eb5e529SEmmanuel Grumbach goto out_no_pci; 27986eb5e529SEmmanuel Grumbach } 2799e705c121SKalle Valo 2800e705c121SKalle Valo ret = pci_enable_device(pdev); 2801e705c121SKalle Valo if (ret) 2802e705c121SKalle Valo goto out_no_pci; 2803e705c121SKalle Valo 2804e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 2805e705c121SKalle Valo /* 2806e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 2807e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 2808e705c121SKalle Valo * lot of power. 2809e705c121SKalle Valo */ 2810e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 2811e705c121SKalle Valo PCIE_LINK_STATE_L1 | 2812e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 2813e705c121SKalle Valo } 2814e705c121SKalle Valo 281596a6497bSSara Sharon if (cfg->mq_rx_supported) 281696a6497bSSara Sharon addr_size = 64; 281796a6497bSSara Sharon else 281896a6497bSSara Sharon addr_size = 36; 281996a6497bSSara Sharon 2820e705c121SKalle Valo pci_set_master(pdev); 2821e705c121SKalle Valo 282296a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 2823e705c121SKalle Valo if (!ret) 282496a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 282596a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 2826e705c121SKalle Valo if (ret) { 2827e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 2828e705c121SKalle Valo if (!ret) 2829e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 2830e705c121SKalle Valo DMA_BIT_MASK(32)); 2831e705c121SKalle Valo /* both attempts failed: */ 2832e705c121SKalle Valo if (ret) { 2833e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 2834e705c121SKalle Valo goto out_pci_disable_device; 2835e705c121SKalle Valo } 2836e705c121SKalle Valo } 2837e705c121SKalle Valo 2838e705c121SKalle Valo ret = pci_request_regions(pdev, DRV_NAME); 2839e705c121SKalle Valo if (ret) { 2840e705c121SKalle Valo dev_err(&pdev->dev, "pci_request_regions failed\n"); 2841e705c121SKalle Valo goto out_pci_disable_device; 2842e705c121SKalle Valo } 2843e705c121SKalle Valo 2844e705c121SKalle Valo trans_pcie->hw_base = pci_ioremap_bar(pdev, 0); 2845e705c121SKalle Valo if (!trans_pcie->hw_base) { 2846e705c121SKalle Valo dev_err(&pdev->dev, "pci_ioremap_bar failed\n"); 2847e705c121SKalle Valo ret = -ENODEV; 2848e705c121SKalle Valo goto out_pci_release_regions; 2849e705c121SKalle Valo } 2850e705c121SKalle Valo 2851e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 2852e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 2853e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 2854e705c121SKalle Valo 2855e705c121SKalle Valo trans->dev = &pdev->dev; 2856e705c121SKalle Valo trans_pcie->pci_dev = pdev; 2857e705c121SKalle Valo iwl_disable_interrupts(trans); 2858e705c121SKalle Valo 2859e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 2860e705c121SKalle Valo /* 2861e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 2862e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 2863e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 2864e705c121SKalle Valo * in the old format. 2865e705c121SKalle Valo */ 2866e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) { 2867e705c121SKalle Valo unsigned long flags; 2868e705c121SKalle Valo 2869e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 2870e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 2871e705c121SKalle Valo 2872e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 2873e705c121SKalle Valo if (ret) { 2874e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 2875e705c121SKalle Valo goto out_pci_disable_msi; 2876e705c121SKalle Valo } 2877e705c121SKalle Valo 2878e705c121SKalle Valo /* 2879e705c121SKalle Valo * in-order to recognize C step driver should read chip version 2880e705c121SKalle Valo * id located at the AUX bus MISC address space. 2881e705c121SKalle Valo */ 2882e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 2883e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 2884e705c121SKalle Valo udelay(2); 2885e705c121SKalle Valo 2886e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 2887e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2888e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 2889e705c121SKalle Valo 25000); 2890e705c121SKalle Valo if (ret < 0) { 2891e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 2892e705c121SKalle Valo goto out_pci_disable_msi; 2893e705c121SKalle Valo } 2894e705c121SKalle Valo 289523ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2896e705c121SKalle Valo u32 hw_step; 2897e705c121SKalle Valo 289814ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 2899e705c121SKalle Valo hw_step |= ENABLE_WFPM; 290014ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 290114ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 2902e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 2903e705c121SKalle Valo if (hw_step == 0x3) 2904e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 2905e705c121SKalle Valo (SILICON_C_STEP << 2); 2906e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2907e705c121SKalle Valo } 2908e705c121SKalle Valo } 2909e705c121SKalle Valo 29101afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 29111afb0ae4SHaim Dreyfuss 29122e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 2913e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 2914e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 2915e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 2916e705c121SKalle Valo 2917e705c121SKalle Valo /* Initialize the wait queue for commands */ 2918e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 2919e705c121SKalle Valo 29204cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 29214cbb8e50SLuciano Coelho 29222e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 29232e5d4a8fSHaim Dreyfuss if (iwl_pcie_init_msix_handler(pdev, trans_pcie)) 29242e5d4a8fSHaim Dreyfuss goto out_pci_release_regions; 29252e5d4a8fSHaim Dreyfuss } else { 2926e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 2927e705c121SKalle Valo if (ret) 2928e705c121SKalle Valo goto out_pci_disable_msi; 2929e705c121SKalle Valo 2930e705c121SKalle Valo ret = request_threaded_irq(pdev->irq, iwl_pcie_isr, 2931e705c121SKalle Valo iwl_pcie_irq_handler, 2932e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 2933e705c121SKalle Valo if (ret) { 2934e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 2935e705c121SKalle Valo goto out_free_ict; 2936e705c121SKalle Valo } 2937e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 29382e5d4a8fSHaim Dreyfuss } 2939e705c121SKalle Valo 2940b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 2941b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 2942b3ff1270SLuca Coelho #else 2943b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 2944b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 2945b3ff1270SLuca Coelho 2946e705c121SKalle Valo return trans; 2947e705c121SKalle Valo 2948e705c121SKalle Valo out_free_ict: 2949e705c121SKalle Valo iwl_pcie_free_ict(trans); 2950e705c121SKalle Valo out_pci_disable_msi: 2951e705c121SKalle Valo pci_disable_msi(pdev); 2952e705c121SKalle Valo out_pci_release_regions: 2953e705c121SKalle Valo pci_release_regions(pdev); 2954e705c121SKalle Valo out_pci_disable_device: 2955e705c121SKalle Valo pci_disable_device(pdev); 2956e705c121SKalle Valo out_no_pci: 29576eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 2958e705c121SKalle Valo iwl_trans_free(trans); 2959e705c121SKalle Valo return ERR_PTR(ret); 2960e705c121SKalle Valo } 2961