1e705c121SKalle Valo /****************************************************************************** 2e705c121SKalle Valo * 3e705c121SKalle Valo * This file is provided under a dual BSD/GPLv2 license. When using or 4e705c121SKalle Valo * redistributing this file, you may do so under either license. 5e705c121SKalle Valo * 6e705c121SKalle Valo * GPL LICENSE SUMMARY 7e705c121SKalle Valo * 8e705c121SKalle Valo * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. 9e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 10afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 11e705c121SKalle Valo * 12e705c121SKalle Valo * This program is free software; you can redistribute it and/or modify 13e705c121SKalle Valo * it under the terms of version 2 of the GNU General Public License as 14e705c121SKalle Valo * published by the Free Software Foundation. 15e705c121SKalle Valo * 16e705c121SKalle Valo * This program is distributed in the hope that it will be useful, but 17e705c121SKalle Valo * WITHOUT ANY WARRANTY; without even the implied warranty of 18e705c121SKalle Valo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19e705c121SKalle Valo * General Public License for more details. 20e705c121SKalle Valo * 21e705c121SKalle Valo * You should have received a copy of the GNU General Public License 22e705c121SKalle Valo * along with this program; if not, write to the Free Software 23e705c121SKalle Valo * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 24e705c121SKalle Valo * USA 25e705c121SKalle Valo * 26e705c121SKalle Valo * The full GNU General Public License is included in this distribution 27e705c121SKalle Valo * in the file called COPYING. 28e705c121SKalle Valo * 29e705c121SKalle Valo * Contact Information: 30cb2f8277SEmmanuel Grumbach * Intel Linux Wireless <linuxwifi@intel.com> 31e705c121SKalle Valo * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 32e705c121SKalle Valo * 33e705c121SKalle Valo * BSD LICENSE 34e705c121SKalle Valo * 35e705c121SKalle Valo * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. 36e705c121SKalle Valo * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 37afb84431SEmmanuel Grumbach * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 38e705c121SKalle Valo * All rights reserved. 39e705c121SKalle Valo * 40e705c121SKalle Valo * Redistribution and use in source and binary forms, with or without 41e705c121SKalle Valo * modification, are permitted provided that the following conditions 42e705c121SKalle Valo * are met: 43e705c121SKalle Valo * 44e705c121SKalle Valo * * Redistributions of source code must retain the above copyright 45e705c121SKalle Valo * notice, this list of conditions and the following disclaimer. 46e705c121SKalle Valo * * Redistributions in binary form must reproduce the above copyright 47e705c121SKalle Valo * notice, this list of conditions and the following disclaimer in 48e705c121SKalle Valo * the documentation and/or other materials provided with the 49e705c121SKalle Valo * distribution. 50e705c121SKalle Valo * * Neither the name Intel Corporation nor the names of its 51e705c121SKalle Valo * contributors may be used to endorse or promote products derived 52e705c121SKalle Valo * from this software without specific prior written permission. 53e705c121SKalle Valo * 54e705c121SKalle Valo * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 55e705c121SKalle Valo * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 56e705c121SKalle Valo * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 57e705c121SKalle Valo * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 58e705c121SKalle Valo * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 59e705c121SKalle Valo * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 60e705c121SKalle Valo * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61e705c121SKalle Valo * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62e705c121SKalle Valo * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63e705c121SKalle Valo * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 64e705c121SKalle Valo * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65e705c121SKalle Valo * 66e705c121SKalle Valo *****************************************************************************/ 67e705c121SKalle Valo #include <linux/pci.h> 68e705c121SKalle Valo #include <linux/pci-aspm.h> 69e705c121SKalle Valo #include <linux/interrupt.h> 70e705c121SKalle Valo #include <linux/debugfs.h> 71e705c121SKalle Valo #include <linux/sched.h> 72e705c121SKalle Valo #include <linux/bitops.h> 73e705c121SKalle Valo #include <linux/gfp.h> 74e705c121SKalle Valo #include <linux/vmalloc.h> 75b3ff1270SLuca Coelho #include <linux/pm_runtime.h> 76e705c121SKalle Valo 77e705c121SKalle Valo #include "iwl-drv.h" 78e705c121SKalle Valo #include "iwl-trans.h" 79e705c121SKalle Valo #include "iwl-csr.h" 80e705c121SKalle Valo #include "iwl-prph.h" 81e705c121SKalle Valo #include "iwl-scd.h" 82e705c121SKalle Valo #include "iwl-agn-hw.h" 83d962f9b1SJohannes Berg #include "fw/error-dump.h" 84e705c121SKalle Valo #include "internal.h" 85e705c121SKalle Valo #include "iwl-fh.h" 86e705c121SKalle Valo 87e705c121SKalle Valo /* extended range in FW SRAM */ 88e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_START 0x40000 89e705c121SKalle Valo #define IWL_FW_MEM_EXTENDED_END 0x57FFF 90e705c121SKalle Valo 91fb12777aSKirtika Ruchandani static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 92a6d24fadSRajat Jain { 93a6d24fadSRajat Jain #define PCI_DUMP_SIZE 64 94a6d24fadSRajat Jain #define PREFIX_LEN 32 95a6d24fadSRajat Jain struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96a6d24fadSRajat Jain struct pci_dev *pdev = trans_pcie->pci_dev; 97a6d24fadSRajat Jain u32 i, pos, alloc_size, *ptr, *buf; 98a6d24fadSRajat Jain char *prefix; 99a6d24fadSRajat Jain 100a6d24fadSRajat Jain if (trans_pcie->pcie_dbg_dumped_once) 101a6d24fadSRajat Jain return; 102a6d24fadSRajat Jain 103a6d24fadSRajat Jain /* Should be a multiple of 4 */ 104a6d24fadSRajat Jain BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 105a6d24fadSRajat Jain /* Alloc a max size buffer */ 106a6d24fadSRajat Jain if (PCI_ERR_ROOT_ERR_SRC + 4 > PCI_DUMP_SIZE) 107a6d24fadSRajat Jain alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 108a6d24fadSRajat Jain else 109a6d24fadSRajat Jain alloc_size = PCI_DUMP_SIZE + PREFIX_LEN; 110a6d24fadSRajat Jain buf = kmalloc(alloc_size, GFP_ATOMIC); 111a6d24fadSRajat Jain if (!buf) 112a6d24fadSRajat Jain return; 113a6d24fadSRajat Jain prefix = (char *)buf + alloc_size - PREFIX_LEN; 114a6d24fadSRajat Jain 115a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 116a6d24fadSRajat Jain 117a6d24fadSRajat Jain /* Print wifi device registers */ 118a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 119a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device config registers:\n"); 120a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 121a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 122a6d24fadSRajat Jain goto err_read; 123a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 124a6d24fadSRajat Jain 125a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 126a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 127a6d24fadSRajat Jain *ptr = iwl_read32(trans, i); 128a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 129a6d24fadSRajat Jain 130a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 131a6d24fadSRajat Jain if (pos) { 132a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 133a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 134a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 135a6d24fadSRajat Jain goto err_read; 136a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 137a6d24fadSRajat Jain 32, 4, buf, i, 0); 138a6d24fadSRajat Jain } 139a6d24fadSRajat Jain 140a6d24fadSRajat Jain /* Print parent device registers next */ 141a6d24fadSRajat Jain if (!pdev->bus->self) 142a6d24fadSRajat Jain goto out; 143a6d24fadSRajat Jain 144a6d24fadSRajat Jain pdev = pdev->bus->self; 145a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 146a6d24fadSRajat Jain 147a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 148a6d24fadSRajat Jain pci_name(pdev)); 149a6d24fadSRajat Jain for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 150a6d24fadSRajat Jain if (pci_read_config_dword(pdev, i, ptr)) 151a6d24fadSRajat Jain goto err_read; 152a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 153a6d24fadSRajat Jain 154a6d24fadSRajat Jain /* Print root port AER registers */ 155a6d24fadSRajat Jain pos = 0; 156a6d24fadSRajat Jain pdev = pcie_find_root_port(pdev); 157a6d24fadSRajat Jain if (pdev) 158a6d24fadSRajat Jain pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 159a6d24fadSRajat Jain if (pos) { 160a6d24fadSRajat Jain IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 161a6d24fadSRajat Jain pci_name(pdev)); 162a6d24fadSRajat Jain sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 163a6d24fadSRajat Jain for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 164a6d24fadSRajat Jain if (pci_read_config_dword(pdev, pos + i, ptr)) 165a6d24fadSRajat Jain goto err_read; 166a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 167a6d24fadSRajat Jain 4, buf, i, 0); 168a6d24fadSRajat Jain } 169f3402d6dSSara Sharon goto out; 170a6d24fadSRajat Jain 171a6d24fadSRajat Jain err_read: 172a6d24fadSRajat Jain print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 173a6d24fadSRajat Jain IWL_ERR(trans, "Read failed at 0x%X\n", i); 174a6d24fadSRajat Jain out: 175a6d24fadSRajat Jain trans_pcie->pcie_dbg_dumped_once = 1; 176a6d24fadSRajat Jain kfree(buf); 177a6d24fadSRajat Jain } 178a6d24fadSRajat Jain 179e705c121SKalle Valo static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 180e705c121SKalle Valo { 181e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 182e705c121SKalle Valo 183e705c121SKalle Valo if (!trans_pcie->fw_mon_page) 184e705c121SKalle Valo return; 185e705c121SKalle Valo 186e705c121SKalle Valo dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys, 187e705c121SKalle Valo trans_pcie->fw_mon_size, DMA_FROM_DEVICE); 188e705c121SKalle Valo __free_pages(trans_pcie->fw_mon_page, 189e705c121SKalle Valo get_order(trans_pcie->fw_mon_size)); 190e705c121SKalle Valo trans_pcie->fw_mon_page = NULL; 191e705c121SKalle Valo trans_pcie->fw_mon_phys = 0; 192e705c121SKalle Valo trans_pcie->fw_mon_size = 0; 193e705c121SKalle Valo } 194e705c121SKalle Valo 195e705c121SKalle Valo static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 196e705c121SKalle Valo { 197e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 198e705c121SKalle Valo struct page *page = NULL; 199e705c121SKalle Valo dma_addr_t phys; 200e705c121SKalle Valo u32 size = 0; 201e705c121SKalle Valo u8 power; 202e705c121SKalle Valo 203e705c121SKalle Valo if (!max_power) { 204e705c121SKalle Valo /* default max_power is maximum */ 205e705c121SKalle Valo max_power = 26; 206e705c121SKalle Valo } else { 207e705c121SKalle Valo max_power += 11; 208e705c121SKalle Valo } 209e705c121SKalle Valo 210e705c121SKalle Valo if (WARN(max_power > 26, 211e705c121SKalle Valo "External buffer size for monitor is too big %d, check the FW TLV\n", 212e705c121SKalle Valo max_power)) 213e705c121SKalle Valo return; 214e705c121SKalle Valo 215e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 216e705c121SKalle Valo dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys, 217e705c121SKalle Valo trans_pcie->fw_mon_size, 218e705c121SKalle Valo DMA_FROM_DEVICE); 219e705c121SKalle Valo return; 220e705c121SKalle Valo } 221e705c121SKalle Valo 222e705c121SKalle Valo phys = 0; 223e705c121SKalle Valo for (power = max_power; power >= 11; power--) { 224e705c121SKalle Valo int order; 225e705c121SKalle Valo 226e705c121SKalle Valo size = BIT(power); 227e705c121SKalle Valo order = get_order(size); 228e705c121SKalle Valo page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO, 229e705c121SKalle Valo order); 230e705c121SKalle Valo if (!page) 231e705c121SKalle Valo continue; 232e705c121SKalle Valo 233e705c121SKalle Valo phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order, 234e705c121SKalle Valo DMA_FROM_DEVICE); 235e705c121SKalle Valo if (dma_mapping_error(trans->dev, phys)) { 236e705c121SKalle Valo __free_pages(page, order); 237e705c121SKalle Valo page = NULL; 238e705c121SKalle Valo continue; 239e705c121SKalle Valo } 240e705c121SKalle Valo IWL_INFO(trans, 241e705c121SKalle Valo "Allocated 0x%08x bytes (order %d) for firmware monitor.\n", 242e705c121SKalle Valo size, order); 243e705c121SKalle Valo break; 244e705c121SKalle Valo } 245e705c121SKalle Valo 246e705c121SKalle Valo if (WARN_ON_ONCE(!page)) 247e705c121SKalle Valo return; 248e705c121SKalle Valo 249e705c121SKalle Valo if (power != max_power) 250e705c121SKalle Valo IWL_ERR(trans, 251e705c121SKalle Valo "Sorry - debug buffer is only %luK while you requested %luK\n", 252e705c121SKalle Valo (unsigned long)BIT(power - 10), 253e705c121SKalle Valo (unsigned long)BIT(max_power - 10)); 254e705c121SKalle Valo 255e705c121SKalle Valo trans_pcie->fw_mon_page = page; 256e705c121SKalle Valo trans_pcie->fw_mon_phys = phys; 257e705c121SKalle Valo trans_pcie->fw_mon_size = size; 258e705c121SKalle Valo } 259e705c121SKalle Valo 260e705c121SKalle Valo static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 261e705c121SKalle Valo { 262e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 263e705c121SKalle Valo ((reg & 0x0000ffff) | (2 << 28))); 264e705c121SKalle Valo return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 265e705c121SKalle Valo } 266e705c121SKalle Valo 267e705c121SKalle Valo static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 268e705c121SKalle Valo { 269e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 270e705c121SKalle Valo iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 271e705c121SKalle Valo ((reg & 0x0000ffff) | (3 << 28))); 272e705c121SKalle Valo } 273e705c121SKalle Valo 274e705c121SKalle Valo static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 275e705c121SKalle Valo { 276e705c121SKalle Valo if (trans->cfg->apmg_not_supported) 277e705c121SKalle Valo return; 278e705c121SKalle Valo 279e705c121SKalle Valo if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 280e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 281e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 282e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 283e705c121SKalle Valo else 284e705c121SKalle Valo iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 285e705c121SKalle Valo APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 286e705c121SKalle Valo ~APMG_PS_CTRL_MSK_PWR_SRC); 287e705c121SKalle Valo } 288e705c121SKalle Valo 289e705c121SKalle Valo /* PCI registers */ 290e705c121SKalle Valo #define PCI_CFG_RETRY_TIMEOUT 0x041 291e705c121SKalle Valo 292eda50cdeSSara Sharon void iwl_pcie_apm_config(struct iwl_trans *trans) 293e705c121SKalle Valo { 294e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 295e705c121SKalle Valo u16 lctl; 296e705c121SKalle Valo u16 cap; 297e705c121SKalle Valo 298e705c121SKalle Valo /* 299e705c121SKalle Valo * HW bug W/A for instability in PCIe bus L0S->L1 transition. 300e705c121SKalle Valo * Check if BIOS (or OS) enabled L1-ASPM on this device. 301e705c121SKalle Valo * If so (likely), disable L0S, so device moves directly L0->L1; 302e705c121SKalle Valo * costs negligible amount of power savings. 303e705c121SKalle Valo * If not (unlikely), enable L0S, so there is at least some 304e705c121SKalle Valo * power savings, even without L1. 305e705c121SKalle Valo */ 306e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 307e705c121SKalle Valo if (lctl & PCI_EXP_LNKCTL_ASPM_L1) 308e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 309e705c121SKalle Valo else 310e705c121SKalle Valo iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 311e705c121SKalle Valo trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 312e705c121SKalle Valo 313e705c121SKalle Valo pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 314e705c121SKalle Valo trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 315d74a61fcSLuca Coelho IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 316e705c121SKalle Valo (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 317e705c121SKalle Valo trans->ltr_enabled ? "En" : "Dis"); 318e705c121SKalle Valo } 319e705c121SKalle Valo 320e705c121SKalle Valo /* 321e705c121SKalle Valo * Start up NIC's basic functionality after it has been reset 322e705c121SKalle Valo * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 323e705c121SKalle Valo * NOTE: This does not load uCode nor start the embedded processor 324e705c121SKalle Valo */ 325e705c121SKalle Valo static int iwl_pcie_apm_init(struct iwl_trans *trans) 326e705c121SKalle Valo { 32752b6e168SEmmanuel Grumbach int ret; 32852b6e168SEmmanuel Grumbach 329e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 330e705c121SKalle Valo 331e705c121SKalle Valo /* 332e705c121SKalle Valo * Use "set_bit" below rather than "write", to preserve any hardware 333e705c121SKalle Valo * bits already set by default after reset. 334e705c121SKalle Valo */ 335e705c121SKalle Valo 336e705c121SKalle Valo /* Disable L0S exit timer (platform NMI Work/Around) */ 3376e584873SSara Sharon if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000) 338e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 339e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 340e705c121SKalle Valo 341e705c121SKalle Valo /* 342e705c121SKalle Valo * Disable L0s without affecting L1; 343e705c121SKalle Valo * don't wait for ICH L0s (ICH bug W/A) 344e705c121SKalle Valo */ 345e705c121SKalle Valo iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 346e705c121SKalle Valo CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 347e705c121SKalle Valo 348e705c121SKalle Valo /* Set FH wait threshold to maximum (HW error during stress W/A) */ 349e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 350e705c121SKalle Valo 351e705c121SKalle Valo /* 352e705c121SKalle Valo * Enable HAP INTA (interrupt from management bus) to 353e705c121SKalle Valo * wake device's PCI Express link L1a -> L0s 354e705c121SKalle Valo */ 355e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 356e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 357e705c121SKalle Valo 358e705c121SKalle Valo iwl_pcie_apm_config(trans); 359e705c121SKalle Valo 360e705c121SKalle Valo /* Configure analog phase-lock-loop before activating to D0A */ 36177d76931SJohannes Berg if (trans->cfg->base_params->pll_cfg) 36277d76931SJohannes Berg iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 363e705c121SKalle Valo 364e705c121SKalle Valo /* 365e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 366e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 367e705c121SKalle Valo */ 368e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 369e705c121SKalle Valo 370e705c121SKalle Valo /* 371e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 372e705c121SKalle Valo * device-internal resources is supported, e.g. iwl_write_prph() 373e705c121SKalle Valo * and accesses to uCode SRAM. 374e705c121SKalle Valo */ 375e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 376e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 377e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); 378e705c121SKalle Valo if (ret < 0) { 37952b6e168SEmmanuel Grumbach IWL_ERR(trans, "Failed to init the card\n"); 38052b6e168SEmmanuel Grumbach return ret; 381e705c121SKalle Valo } 382e705c121SKalle Valo 383e705c121SKalle Valo if (trans->cfg->host_interrupt_operation_mode) { 384e705c121SKalle Valo /* 385e705c121SKalle Valo * This is a bit of an abuse - This is needed for 7260 / 3160 386e705c121SKalle Valo * only check host_interrupt_operation_mode even if this is 387e705c121SKalle Valo * not related to host_interrupt_operation_mode. 388e705c121SKalle Valo * 389e705c121SKalle Valo * Enable the oscillator to count wake up time for L1 exit. This 390e705c121SKalle Valo * consumes slightly more power (100uA) - but allows to be sure 391e705c121SKalle Valo * that we wake up from L1 on time. 392e705c121SKalle Valo * 393e705c121SKalle Valo * This looks weird: read twice the same register, discard the 394e705c121SKalle Valo * value, set a bit, and yet again, read that same register 395e705c121SKalle Valo * just to discard the value. But that's the way the hardware 396e705c121SKalle Valo * seems to like it. 397e705c121SKalle Valo */ 398e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 399e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 400e705c121SKalle Valo iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 401e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 402e705c121SKalle Valo iwl_read_prph(trans, OSC_CLK); 403e705c121SKalle Valo } 404e705c121SKalle Valo 405e705c121SKalle Valo /* 406e705c121SKalle Valo * Enable DMA clock and wait for it to stabilize. 407e705c121SKalle Valo * 408e705c121SKalle Valo * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 409e705c121SKalle Valo * bits do not disable clocks. This preserves any hardware 410e705c121SKalle Valo * bits already set by default in "CLK_CTRL_REG" after reset. 411e705c121SKalle Valo */ 412e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 413e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_EN_REG, 414e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 415e705c121SKalle Valo udelay(20); 416e705c121SKalle Valo 417e705c121SKalle Valo /* Disable L1-Active */ 418e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 419e705c121SKalle Valo APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 420e705c121SKalle Valo 421e705c121SKalle Valo /* Clear the interrupt in APMG if the NIC is in RFKILL */ 422e705c121SKalle Valo iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 423e705c121SKalle Valo APMG_RTC_INT_STT_RFKILL); 424e705c121SKalle Valo } 425e705c121SKalle Valo 426e705c121SKalle Valo set_bit(STATUS_DEVICE_ENABLED, &trans->status); 427e705c121SKalle Valo 42852b6e168SEmmanuel Grumbach return 0; 429e705c121SKalle Valo } 430e705c121SKalle Valo 431e705c121SKalle Valo /* 432e705c121SKalle Valo * Enable LP XTAL to avoid HW bug where device may consume much power if 433e705c121SKalle Valo * FW is not loaded after device reset. LP XTAL is disabled by default 434e705c121SKalle Valo * after device HW reset. Do it only if XTAL is fed by internal source. 435e705c121SKalle Valo * Configure device's "persistence" mode to avoid resetting XTAL again when 436e705c121SKalle Valo * SHRD_HW_RST occurs in S3. 437e705c121SKalle Valo */ 438e705c121SKalle Valo static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 439e705c121SKalle Valo { 440e705c121SKalle Valo int ret; 441e705c121SKalle Valo u32 apmg_gp1_reg; 442e705c121SKalle Valo u32 apmg_xtal_cfg_reg; 443e705c121SKalle Valo u32 dl_cfg_reg; 444e705c121SKalle Valo 445e705c121SKalle Valo /* Force XTAL ON */ 446e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 447e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 448e705c121SKalle Valo 449099a628bSEmmanuel Grumbach iwl_pcie_sw_reset(trans); 450e705c121SKalle Valo 451e705c121SKalle Valo /* 452e705c121SKalle Valo * Set "initialization complete" bit to move adapter from 453e705c121SKalle Valo * D0U* --> D0A* (powered-up active) state. 454e705c121SKalle Valo */ 455e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 456e705c121SKalle Valo 457e705c121SKalle Valo /* 458e705c121SKalle Valo * Wait for clock stabilization; once stabilized, access to 459e705c121SKalle Valo * device-internal resources is possible. 460e705c121SKalle Valo */ 461e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 462e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 463e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 464e705c121SKalle Valo 25000); 465e705c121SKalle Valo if (WARN_ON(ret < 0)) { 466e705c121SKalle Valo IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n"); 467e705c121SKalle Valo /* Release XTAL ON request */ 468e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 469e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 470e705c121SKalle Valo return; 471e705c121SKalle Valo } 472e705c121SKalle Valo 473e705c121SKalle Valo /* 474e705c121SKalle Valo * Clear "disable persistence" to avoid LP XTAL resetting when 475e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 476e705c121SKalle Valo */ 477e705c121SKalle Valo iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 478e705c121SKalle Valo APMG_PCIDEV_STT_VAL_PERSIST_DIS); 479e705c121SKalle Valo 480e705c121SKalle Valo /* 481e705c121SKalle Valo * Force APMG XTAL to be active to prevent its disabling by HW 482e705c121SKalle Valo * caused by APMG idle state. 483e705c121SKalle Valo */ 484e705c121SKalle Valo apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 485e705c121SKalle Valo SHR_APMG_XTAL_CFG_REG); 486e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 487e705c121SKalle Valo apmg_xtal_cfg_reg | 488e705c121SKalle Valo SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 489e705c121SKalle Valo 490099a628bSEmmanuel Grumbach iwl_pcie_sw_reset(trans); 491e705c121SKalle Valo 492e705c121SKalle Valo /* Enable LP XTAL by indirect access through CSR */ 493e705c121SKalle Valo apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 494e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 495e705c121SKalle Valo SHR_APMG_GP1_WF_XTAL_LP_EN | 496e705c121SKalle Valo SHR_APMG_GP1_CHICKEN_BIT_SELECT); 497e705c121SKalle Valo 498e705c121SKalle Valo /* Clear delay line clock power up */ 499e705c121SKalle Valo dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 500e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 501e705c121SKalle Valo ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 502e705c121SKalle Valo 503e705c121SKalle Valo /* 504e705c121SKalle Valo * Enable persistence mode to avoid LP XTAL resetting when 505e705c121SKalle Valo * SHRD_HW_RST is applied in S3. 506e705c121SKalle Valo */ 507e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 508e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 509e705c121SKalle Valo 510e705c121SKalle Valo /* 511e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 512e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 513e705c121SKalle Valo */ 514e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 515e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 516e705c121SKalle Valo 517e705c121SKalle Valo /* Activates XTAL resources monitor */ 518e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 519e705c121SKalle Valo CSR_MONITOR_XTAL_RESOURCES); 520e705c121SKalle Valo 521e705c121SKalle Valo /* Release XTAL ON request */ 522e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 523e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 524e705c121SKalle Valo udelay(10); 525e705c121SKalle Valo 526e705c121SKalle Valo /* Release APMG XTAL */ 527e705c121SKalle Valo iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 528e705c121SKalle Valo apmg_xtal_cfg_reg & 529e705c121SKalle Valo ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 530e705c121SKalle Valo } 531e705c121SKalle Valo 532e8c8935eSJohannes Berg void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 533e705c121SKalle Valo { 534e8c8935eSJohannes Berg int ret; 535e705c121SKalle Valo 536e705c121SKalle Valo /* stop device's busmaster DMA activity */ 537e705c121SKalle Valo iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 538e705c121SKalle Valo 539e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_RESET, 540e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 541e705c121SKalle Valo CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 542e705c121SKalle Valo if (ret < 0) 543e705c121SKalle Valo IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 544e705c121SKalle Valo 545e705c121SKalle Valo IWL_DEBUG_INFO(trans, "stop master\n"); 546e705c121SKalle Valo } 547e705c121SKalle Valo 548e705c121SKalle Valo static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 549e705c121SKalle Valo { 550e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 551e705c121SKalle Valo 552e705c121SKalle Valo if (op_mode_leave) { 553e705c121SKalle Valo if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 554e705c121SKalle Valo iwl_pcie_apm_init(trans); 555e705c121SKalle Valo 556e705c121SKalle Valo /* inform ME that we are leaving */ 557e705c121SKalle Valo if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) 558e705c121SKalle Valo iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 559e705c121SKalle Valo APMG_PCIDEV_STT_VAL_WAKE_ME); 5606e584873SSara Sharon else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 561e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 562e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 563e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 564e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE | 565e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_ENABLE_PME); 566e705c121SKalle Valo mdelay(1); 567e705c121SKalle Valo iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 568e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 569e705c121SKalle Valo } 570e705c121SKalle Valo mdelay(5); 571e705c121SKalle Valo } 572e705c121SKalle Valo 573e705c121SKalle Valo clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 574e705c121SKalle Valo 575e705c121SKalle Valo /* Stop device's DMA activity */ 576e705c121SKalle Valo iwl_pcie_apm_stop_master(trans); 577e705c121SKalle Valo 578e705c121SKalle Valo if (trans->cfg->lp_xtal_workaround) { 579e705c121SKalle Valo iwl_pcie_apm_lp_xtal_enable(trans); 580e705c121SKalle Valo return; 581e705c121SKalle Valo } 582e705c121SKalle Valo 583099a628bSEmmanuel Grumbach iwl_pcie_sw_reset(trans); 584e705c121SKalle Valo 585e705c121SKalle Valo /* 586e705c121SKalle Valo * Clear "initialization complete" bit to move adapter from 587e705c121SKalle Valo * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 588e705c121SKalle Valo */ 589e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 590e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 591e705c121SKalle Valo } 592e705c121SKalle Valo 593e705c121SKalle Valo static int iwl_pcie_nic_init(struct iwl_trans *trans) 594e705c121SKalle Valo { 595e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 59652b6e168SEmmanuel Grumbach int ret; 597e705c121SKalle Valo 598e705c121SKalle Valo /* nic_init */ 599e705c121SKalle Valo spin_lock(&trans_pcie->irq_lock); 60052b6e168SEmmanuel Grumbach ret = iwl_pcie_apm_init(trans); 601e705c121SKalle Valo spin_unlock(&trans_pcie->irq_lock); 602e705c121SKalle Valo 60352b6e168SEmmanuel Grumbach if (ret) 60452b6e168SEmmanuel Grumbach return ret; 60552b6e168SEmmanuel Grumbach 606e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 607e705c121SKalle Valo 608e705c121SKalle Valo iwl_op_mode_nic_config(trans->op_mode); 609e705c121SKalle Valo 610e705c121SKalle Valo /* Allocate the RX queue, or reset if it is already allocated */ 611e705c121SKalle Valo iwl_pcie_rx_init(trans); 612e705c121SKalle Valo 613e705c121SKalle Valo /* Allocate or reset and init all Tx and Command queues */ 614e705c121SKalle Valo if (iwl_pcie_tx_init(trans)) 615e705c121SKalle Valo return -ENOMEM; 616e705c121SKalle Valo 617e705c121SKalle Valo if (trans->cfg->base_params->shadow_reg_enable) { 618e705c121SKalle Valo /* enable shadow regs in HW */ 619e705c121SKalle Valo iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 620e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 621e705c121SKalle Valo } 622e705c121SKalle Valo 623e705c121SKalle Valo return 0; 624e705c121SKalle Valo } 625e705c121SKalle Valo 626e705c121SKalle Valo #define HW_READY_TIMEOUT (50) 627e705c121SKalle Valo 628e705c121SKalle Valo /* Note: returns poll_bit return value, which is >= 0 if success */ 629e705c121SKalle Valo static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 630e705c121SKalle Valo { 631e705c121SKalle Valo int ret; 632e705c121SKalle Valo 633e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 634e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 635e705c121SKalle Valo 636e705c121SKalle Valo /* See if we got it */ 637e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 638e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 639e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 640e705c121SKalle Valo HW_READY_TIMEOUT); 641e705c121SKalle Valo 642e705c121SKalle Valo if (ret >= 0) 643e705c121SKalle Valo iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 644e705c121SKalle Valo 645e705c121SKalle Valo IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 646e705c121SKalle Valo return ret; 647e705c121SKalle Valo } 648e705c121SKalle Valo 649e705c121SKalle Valo /* Note: returns standard 0/-ERROR code */ 650eda50cdeSSara Sharon int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 651e705c121SKalle Valo { 652e705c121SKalle Valo int ret; 653e705c121SKalle Valo int t = 0; 654e705c121SKalle Valo int iter; 655e705c121SKalle Valo 656e705c121SKalle Valo IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 657e705c121SKalle Valo 658e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 659e705c121SKalle Valo /* If the card is ready, exit 0 */ 660e705c121SKalle Valo if (ret >= 0) 661e705c121SKalle Valo return 0; 662e705c121SKalle Valo 663e705c121SKalle Valo iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 664e705c121SKalle Valo CSR_RESET_LINK_PWR_MGMT_DISABLED); 665192185d6SJohannes Berg usleep_range(1000, 2000); 666e705c121SKalle Valo 667e705c121SKalle Valo for (iter = 0; iter < 10; iter++) { 668e705c121SKalle Valo /* If HW is not ready, prepare the conditions to check again */ 669e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 670e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PREPARE); 671e705c121SKalle Valo 672e705c121SKalle Valo do { 673e705c121SKalle Valo ret = iwl_pcie_set_hw_ready(trans); 674e705c121SKalle Valo if (ret >= 0) 675e705c121SKalle Valo return 0; 676e705c121SKalle Valo 677e705c121SKalle Valo usleep_range(200, 1000); 678e705c121SKalle Valo t += 200; 679e705c121SKalle Valo } while (t < 150000); 680e705c121SKalle Valo msleep(25); 681e705c121SKalle Valo } 682e705c121SKalle Valo 683e705c121SKalle Valo IWL_ERR(trans, "Couldn't prepare the card\n"); 684e705c121SKalle Valo 685e705c121SKalle Valo return ret; 686e705c121SKalle Valo } 687e705c121SKalle Valo 688e705c121SKalle Valo /* 689e705c121SKalle Valo * ucode 690e705c121SKalle Valo */ 691564cdce7SSara Sharon static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 692564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 693564cdce7SSara Sharon u32 byte_cnt) 694e705c121SKalle Valo { 695bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 696e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 697e705c121SKalle Valo 698bac842daSEmmanuel Grumbach iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 699e705c121SKalle Valo dst_addr); 700e705c121SKalle Valo 701bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 702e705c121SKalle Valo phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 703e705c121SKalle Valo 704bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 705e705c121SKalle Valo (iwl_get_dma_hi_addr(phy_addr) 706e705c121SKalle Valo << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 707e705c121SKalle Valo 708bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 709bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 710bac842daSEmmanuel Grumbach BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 711e705c121SKalle Valo FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 712e705c121SKalle Valo 713bac842daSEmmanuel Grumbach iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 714e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 715e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 716e705c121SKalle Valo FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 717564cdce7SSara Sharon } 718e705c121SKalle Valo 719564cdce7SSara Sharon static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 720564cdce7SSara Sharon u32 dst_addr, dma_addr_t phy_addr, 721564cdce7SSara Sharon u32 byte_cnt) 722564cdce7SSara Sharon { 723564cdce7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 724564cdce7SSara Sharon unsigned long flags; 725564cdce7SSara Sharon int ret; 726564cdce7SSara Sharon 727564cdce7SSara Sharon trans_pcie->ucode_write_complete = false; 728564cdce7SSara Sharon 729564cdce7SSara Sharon if (!iwl_trans_grab_nic_access(trans, &flags)) 730564cdce7SSara Sharon return -EIO; 731564cdce7SSara Sharon 732564cdce7SSara Sharon iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 733564cdce7SSara Sharon byte_cnt); 734bac842daSEmmanuel Grumbach iwl_trans_release_nic_access(trans, &flags); 735bac842daSEmmanuel Grumbach 736e705c121SKalle Valo ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 737e705c121SKalle Valo trans_pcie->ucode_write_complete, 5 * HZ); 738e705c121SKalle Valo if (!ret) { 739e705c121SKalle Valo IWL_ERR(trans, "Failed to load firmware chunk!\n"); 740fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 741e705c121SKalle Valo return -ETIMEDOUT; 742e705c121SKalle Valo } 743e705c121SKalle Valo 744e705c121SKalle Valo return 0; 745e705c121SKalle Valo } 746e705c121SKalle Valo 747e705c121SKalle Valo static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 748e705c121SKalle Valo const struct fw_desc *section) 749e705c121SKalle Valo { 750e705c121SKalle Valo u8 *v_addr; 751e705c121SKalle Valo dma_addr_t p_addr; 752e705c121SKalle Valo u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 753e705c121SKalle Valo int ret = 0; 754e705c121SKalle Valo 755e705c121SKalle Valo IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 756e705c121SKalle Valo section_num); 757e705c121SKalle Valo 758e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 759e705c121SKalle Valo GFP_KERNEL | __GFP_NOWARN); 760e705c121SKalle Valo if (!v_addr) { 761e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 762e705c121SKalle Valo chunk_sz = PAGE_SIZE; 763e705c121SKalle Valo v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 764e705c121SKalle Valo &p_addr, GFP_KERNEL); 765e705c121SKalle Valo if (!v_addr) 766e705c121SKalle Valo return -ENOMEM; 767e705c121SKalle Valo } 768e705c121SKalle Valo 769e705c121SKalle Valo for (offset = 0; offset < section->len; offset += chunk_sz) { 770e705c121SKalle Valo u32 copy_size, dst_addr; 771e705c121SKalle Valo bool extended_addr = false; 772e705c121SKalle Valo 773e705c121SKalle Valo copy_size = min_t(u32, chunk_sz, section->len - offset); 774e705c121SKalle Valo dst_addr = section->offset + offset; 775e705c121SKalle Valo 776e705c121SKalle Valo if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 777e705c121SKalle Valo dst_addr <= IWL_FW_MEM_EXTENDED_END) 778e705c121SKalle Valo extended_addr = true; 779e705c121SKalle Valo 780e705c121SKalle Valo if (extended_addr) 781e705c121SKalle Valo iwl_set_bits_prph(trans, LMPM_CHICK, 782e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 783e705c121SKalle Valo 784e705c121SKalle Valo memcpy(v_addr, (u8 *)section->data + offset, copy_size); 785e705c121SKalle Valo ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 786e705c121SKalle Valo copy_size); 787e705c121SKalle Valo 788e705c121SKalle Valo if (extended_addr) 789e705c121SKalle Valo iwl_clear_bits_prph(trans, LMPM_CHICK, 790e705c121SKalle Valo LMPM_CHICK_EXTENDED_ADDR_SPACE); 791e705c121SKalle Valo 792e705c121SKalle Valo if (ret) { 793e705c121SKalle Valo IWL_ERR(trans, 794e705c121SKalle Valo "Could not load the [%d] uCode section\n", 795e705c121SKalle Valo section_num); 796e705c121SKalle Valo break; 797e705c121SKalle Valo } 798e705c121SKalle Valo } 799e705c121SKalle Valo 800e705c121SKalle Valo dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 801e705c121SKalle Valo return ret; 802e705c121SKalle Valo } 803e705c121SKalle Valo 804e705c121SKalle Valo static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 805e705c121SKalle Valo const struct fw_img *image, 806e705c121SKalle Valo int cpu, 807e705c121SKalle Valo int *first_ucode_section) 808e705c121SKalle Valo { 809e705c121SKalle Valo int shift_param; 810e705c121SKalle Valo int i, ret = 0, sec_num = 0x1; 811e705c121SKalle Valo u32 val, last_read_idx = 0; 812e705c121SKalle Valo 813e705c121SKalle Valo if (cpu == 1) { 814e705c121SKalle Valo shift_param = 0; 815e705c121SKalle Valo *first_ucode_section = 0; 816e705c121SKalle Valo } else { 817e705c121SKalle Valo shift_param = 16; 818e705c121SKalle Valo (*first_ucode_section)++; 819e705c121SKalle Valo } 820e705c121SKalle Valo 821eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 822e705c121SKalle Valo last_read_idx = i; 823e705c121SKalle Valo 824e705c121SKalle Valo /* 825e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 826e705c121SKalle Valo * CPU1 to CPU2. 827e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 828e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 829e705c121SKalle Valo */ 830e705c121SKalle Valo if (!image->sec[i].data || 831e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 832e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 833e705c121SKalle Valo IWL_DEBUG_FW(trans, 834e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 835e705c121SKalle Valo i); 836e705c121SKalle Valo break; 837e705c121SKalle Valo } 838e705c121SKalle Valo 839e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 840e705c121SKalle Valo if (ret) 841e705c121SKalle Valo return ret; 842e705c121SKalle Valo 843d6a2c5c7SSara Sharon /* Notify ucode of loaded section number and status */ 844e705c121SKalle Valo val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 845e705c121SKalle Valo val = val | (sec_num << shift_param); 846e705c121SKalle Valo iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 847eda50cdeSSara Sharon 848e705c121SKalle Valo sec_num = (sec_num << 1) | 0x1; 849e705c121SKalle Valo } 850e705c121SKalle Valo 851e705c121SKalle Valo *first_ucode_section = last_read_idx; 852e705c121SKalle Valo 8532aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 8542aabdbdcSEmmanuel Grumbach 855d6a2c5c7SSara Sharon if (trans->cfg->use_tfh) { 856e705c121SKalle Valo if (cpu == 1) 857d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 858d6a2c5c7SSara Sharon 0xFFFF); 859e705c121SKalle Valo else 860d6a2c5c7SSara Sharon iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 861d6a2c5c7SSara Sharon 0xFFFFFFFF); 862d6a2c5c7SSara Sharon } else { 863d6a2c5c7SSara Sharon if (cpu == 1) 864d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 865d6a2c5c7SSara Sharon 0xFFFF); 866d6a2c5c7SSara Sharon else 867d6a2c5c7SSara Sharon iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 868d6a2c5c7SSara Sharon 0xFFFFFFFF); 869d6a2c5c7SSara Sharon } 870e705c121SKalle Valo 871e705c121SKalle Valo return 0; 872e705c121SKalle Valo } 873e705c121SKalle Valo 874e705c121SKalle Valo static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 875e705c121SKalle Valo const struct fw_img *image, 876e705c121SKalle Valo int cpu, 877e705c121SKalle Valo int *first_ucode_section) 878e705c121SKalle Valo { 879e705c121SKalle Valo int i, ret = 0; 880e705c121SKalle Valo u32 last_read_idx = 0; 881e705c121SKalle Valo 8823ce4a038SKirtika Ruchandani if (cpu == 1) 883e705c121SKalle Valo *first_ucode_section = 0; 8843ce4a038SKirtika Ruchandani else 885e705c121SKalle Valo (*first_ucode_section)++; 886e705c121SKalle Valo 887eef187a7SSara Sharon for (i = *first_ucode_section; i < image->num_sec; i++) { 888e705c121SKalle Valo last_read_idx = i; 889e705c121SKalle Valo 890e705c121SKalle Valo /* 891e705c121SKalle Valo * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 892e705c121SKalle Valo * CPU1 to CPU2. 893e705c121SKalle Valo * PAGING_SEPARATOR_SECTION delimiter - separate between 894e705c121SKalle Valo * CPU2 non paged to CPU2 paging sec. 895e705c121SKalle Valo */ 896e705c121SKalle Valo if (!image->sec[i].data || 897e705c121SKalle Valo image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 898e705c121SKalle Valo image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 899e705c121SKalle Valo IWL_DEBUG_FW(trans, 900e705c121SKalle Valo "Break since Data not valid or Empty section, sec = %d\n", 901e705c121SKalle Valo i); 902e705c121SKalle Valo break; 903e705c121SKalle Valo } 904e705c121SKalle Valo 905e705c121SKalle Valo ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 906e705c121SKalle Valo if (ret) 907e705c121SKalle Valo return ret; 908e705c121SKalle Valo } 909e705c121SKalle Valo 910e705c121SKalle Valo *first_ucode_section = last_read_idx; 911e705c121SKalle Valo 912e705c121SKalle Valo return 0; 913e705c121SKalle Valo } 914e705c121SKalle Valo 915c9be849dSLiad Kaufman void iwl_pcie_apply_destination(struct iwl_trans *trans) 916e705c121SKalle Valo { 917e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 918e705c121SKalle Valo const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv; 919e705c121SKalle Valo int i; 920e705c121SKalle Valo 921e705c121SKalle Valo if (dest->version) 922e705c121SKalle Valo IWL_ERR(trans, 923e705c121SKalle Valo "DBG DEST version is %d - expect issues\n", 924e705c121SKalle Valo dest->version); 925e705c121SKalle Valo 926e705c121SKalle Valo IWL_INFO(trans, "Applying debug destination %s\n", 927e705c121SKalle Valo get_fw_dbg_mode_string(dest->monitor_mode)); 928e705c121SKalle Valo 929e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE) 930e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 931e705c121SKalle Valo else 932e705c121SKalle Valo IWL_WARN(trans, "PCI should have external buffer debug\n"); 933e705c121SKalle Valo 934e705c121SKalle Valo for (i = 0; i < trans->dbg_dest_reg_num; i++) { 935e705c121SKalle Valo u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 936e705c121SKalle Valo u32 val = le32_to_cpu(dest->reg_ops[i].val); 937e705c121SKalle Valo 938e705c121SKalle Valo switch (dest->reg_ops[i].op) { 939e705c121SKalle Valo case CSR_ASSIGN: 940e705c121SKalle Valo iwl_write32(trans, addr, val); 941e705c121SKalle Valo break; 942e705c121SKalle Valo case CSR_SETBIT: 943e705c121SKalle Valo iwl_set_bit(trans, addr, BIT(val)); 944e705c121SKalle Valo break; 945e705c121SKalle Valo case CSR_CLEARBIT: 946e705c121SKalle Valo iwl_clear_bit(trans, addr, BIT(val)); 947e705c121SKalle Valo break; 948e705c121SKalle Valo case PRPH_ASSIGN: 949e705c121SKalle Valo iwl_write_prph(trans, addr, val); 950e705c121SKalle Valo break; 951e705c121SKalle Valo case PRPH_SETBIT: 952e705c121SKalle Valo iwl_set_bits_prph(trans, addr, BIT(val)); 953e705c121SKalle Valo break; 954e705c121SKalle Valo case PRPH_CLEARBIT: 955e705c121SKalle Valo iwl_clear_bits_prph(trans, addr, BIT(val)); 956e705c121SKalle Valo break; 957e705c121SKalle Valo case PRPH_BLOCKBIT: 958e705c121SKalle Valo if (iwl_read_prph(trans, addr) & BIT(val)) { 959e705c121SKalle Valo IWL_ERR(trans, 960e705c121SKalle Valo "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 961e705c121SKalle Valo val, addr); 962e705c121SKalle Valo goto monitor; 963e705c121SKalle Valo } 964e705c121SKalle Valo break; 965e705c121SKalle Valo default: 966e705c121SKalle Valo IWL_ERR(trans, "FW debug - unknown OP %d\n", 967e705c121SKalle Valo dest->reg_ops[i].op); 968e705c121SKalle Valo break; 969e705c121SKalle Valo } 970e705c121SKalle Valo } 971e705c121SKalle Valo 972e705c121SKalle Valo monitor: 973e705c121SKalle Valo if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) { 974e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 975e705c121SKalle Valo trans_pcie->fw_mon_phys >> dest->base_shift); 9766e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 977e705c121SKalle Valo iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 978e705c121SKalle Valo (trans_pcie->fw_mon_phys + 97962d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size - 256) >> 98062d7476dSEmmanuel Grumbach dest->end_shift); 98162d7476dSEmmanuel Grumbach else 98262d7476dSEmmanuel Grumbach iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 98362d7476dSEmmanuel Grumbach (trans_pcie->fw_mon_phys + 98462d7476dSEmmanuel Grumbach trans_pcie->fw_mon_size) >> 98562d7476dSEmmanuel Grumbach dest->end_shift); 986e705c121SKalle Valo } 987e705c121SKalle Valo } 988e705c121SKalle Valo 989e705c121SKalle Valo static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 990e705c121SKalle Valo const struct fw_img *image) 991e705c121SKalle Valo { 992e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 993e705c121SKalle Valo int ret = 0; 994e705c121SKalle Valo int first_ucode_section; 995e705c121SKalle Valo 996e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 997e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 998e705c121SKalle Valo 999e705c121SKalle Valo /* load to FW the binary non secured sections of CPU1 */ 1000e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1001e705c121SKalle Valo if (ret) 1002e705c121SKalle Valo return ret; 1003e705c121SKalle Valo 1004e705c121SKalle Valo if (image->is_dual_cpus) { 1005e705c121SKalle Valo /* set CPU2 header address */ 1006e705c121SKalle Valo iwl_write_prph(trans, 1007e705c121SKalle Valo LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1008e705c121SKalle Valo LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1009e705c121SKalle Valo 1010e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1011e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1012e705c121SKalle Valo &first_ucode_section); 1013e705c121SKalle Valo if (ret) 1014e705c121SKalle Valo return ret; 1015e705c121SKalle Valo } 1016e705c121SKalle Valo 1017e705c121SKalle Valo /* supported for 7000 only for the moment */ 1018e705c121SKalle Valo if (iwlwifi_mod_params.fw_monitor && 1019e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 1020e705c121SKalle Valo iwl_pcie_alloc_fw_monitor(trans, 0); 1021e705c121SKalle Valo 1022e705c121SKalle Valo if (trans_pcie->fw_mon_size) { 1023e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_BASE_ADDR, 1024e705c121SKalle Valo trans_pcie->fw_mon_phys >> 4); 1025e705c121SKalle Valo iwl_write_prph(trans, MON_BUFF_END_ADDR, 1026e705c121SKalle Valo (trans_pcie->fw_mon_phys + 1027e705c121SKalle Valo trans_pcie->fw_mon_size) >> 4); 1028e705c121SKalle Valo } 1029e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 1030e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1031e705c121SKalle Valo } 1032e705c121SKalle Valo 10332aabdbdcSEmmanuel Grumbach iwl_enable_interrupts(trans); 10342aabdbdcSEmmanuel Grumbach 1035e705c121SKalle Valo /* release CPU reset */ 1036e705c121SKalle Valo iwl_write32(trans, CSR_RESET, 0); 1037e705c121SKalle Valo 1038e705c121SKalle Valo return 0; 1039e705c121SKalle Valo } 1040e705c121SKalle Valo 1041e705c121SKalle Valo static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1042e705c121SKalle Valo const struct fw_img *image) 1043e705c121SKalle Valo { 1044e705c121SKalle Valo int ret = 0; 1045e705c121SKalle Valo int first_ucode_section; 1046e705c121SKalle Valo 1047e705c121SKalle Valo IWL_DEBUG_FW(trans, "working with %s CPU\n", 1048e705c121SKalle Valo image->is_dual_cpus ? "Dual" : "Single"); 1049e705c121SKalle Valo 1050e705c121SKalle Valo if (trans->dbg_dest_tlv) 1051e705c121SKalle Valo iwl_pcie_apply_destination(trans); 1052e705c121SKalle Valo 105382ea7966SSara Sharon IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 105482ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 105582ea7966SSara Sharon 105682ea7966SSara Sharon /* 105782ea7966SSara Sharon * Set default value. On resume reading the values that were 105882ea7966SSara Sharon * zeored can provide debug data on the resume flow. 105982ea7966SSara Sharon * This is for debugging only and has no functional impact. 106082ea7966SSara Sharon */ 106182ea7966SSara Sharon iwl_write_prph(trans, WFPM_GP2, 0x01010101); 106282ea7966SSara Sharon 1063e705c121SKalle Valo /* configure the ucode to be ready to get the secured image */ 1064e705c121SKalle Valo /* release CPU reset */ 1065e705c121SKalle Valo iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1066e705c121SKalle Valo 1067e705c121SKalle Valo /* load to FW the binary Secured sections of CPU1 */ 1068e705c121SKalle Valo ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1069e705c121SKalle Valo &first_ucode_section); 1070e705c121SKalle Valo if (ret) 1071e705c121SKalle Valo return ret; 1072e705c121SKalle Valo 1073e705c121SKalle Valo /* load to FW the binary sections of CPU2 */ 1074e705c121SKalle Valo return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1075e705c121SKalle Valo &first_ucode_section); 1076e705c121SKalle Valo } 1077e705c121SKalle Valo 10789ad8fd0bSJohannes Berg bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1079727c02dfSSara Sharon { 1080326477e4SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1081727c02dfSSara Sharon bool hw_rfkill = iwl_is_rfkill_set(trans); 1082326477e4SJohannes Berg bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1083326477e4SJohannes Berg bool report; 1084727c02dfSSara Sharon 1085326477e4SJohannes Berg if (hw_rfkill) { 1086326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1087326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1088326477e4SJohannes Berg } else { 1089326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1090326477e4SJohannes Berg if (trans_pcie->opmode_down) 1091326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1092326477e4SJohannes Berg } 1093727c02dfSSara Sharon 1094326477e4SJohannes Berg report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1095326477e4SJohannes Berg 1096326477e4SJohannes Berg if (prev != report) 1097326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, report); 1098727c02dfSSara Sharon 1099727c02dfSSara Sharon return hw_rfkill; 1100727c02dfSSara Sharon } 1101727c02dfSSara Sharon 11027ca00409SHaim Dreyfuss struct iwl_causes_list { 11037ca00409SHaim Dreyfuss u32 cause_num; 11047ca00409SHaim Dreyfuss u32 mask_reg; 11057ca00409SHaim Dreyfuss u8 addr; 11067ca00409SHaim Dreyfuss }; 11077ca00409SHaim Dreyfuss 11087ca00409SHaim Dreyfuss static struct iwl_causes_list causes_list[] = { 11097ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0}, 11107ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1}, 11117ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3}, 11127ca00409SHaim Dreyfuss {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5}, 11137ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10}, 11147ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11}, 11157ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16}, 11167ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17}, 11177ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18}, 11187ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29}, 11197ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A}, 11207ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B}, 11217ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D}, 11227ca00409SHaim Dreyfuss {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E}, 11237ca00409SHaim Dreyfuss }; 11247ca00409SHaim Dreyfuss 11257ca00409SHaim Dreyfuss static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 11267ca00409SHaim Dreyfuss { 11277ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11287ca00409SHaim Dreyfuss int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 11297ca00409SHaim Dreyfuss int i; 11307ca00409SHaim Dreyfuss 11317ca00409SHaim Dreyfuss /* 11327ca00409SHaim Dreyfuss * Access all non RX causes and map them to the default irq. 11337ca00409SHaim Dreyfuss * In case we are missing at least one interrupt vector, 11347ca00409SHaim Dreyfuss * the first interrupt vector will serve non-RX and FBQ causes. 11357ca00409SHaim Dreyfuss */ 11367ca00409SHaim Dreyfuss for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 11377ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val); 11387ca00409SHaim Dreyfuss iwl_clear_bit(trans, causes_list[i].mask_reg, 11397ca00409SHaim Dreyfuss causes_list[i].cause_num); 11407ca00409SHaim Dreyfuss } 11417ca00409SHaim Dreyfuss } 11427ca00409SHaim Dreyfuss 11437ca00409SHaim Dreyfuss static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 11447ca00409SHaim Dreyfuss { 11457ca00409SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 11467ca00409SHaim Dreyfuss u32 offset = 11477ca00409SHaim Dreyfuss trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 11487ca00409SHaim Dreyfuss u32 val, idx; 11497ca00409SHaim Dreyfuss 11507ca00409SHaim Dreyfuss /* 11517ca00409SHaim Dreyfuss * The first RX queue - fallback queue, which is designated for 11527ca00409SHaim Dreyfuss * management frame, command responses etc, is always mapped to the 11537ca00409SHaim Dreyfuss * first interrupt vector. The other RX queues are mapped to 11547ca00409SHaim Dreyfuss * the other (N - 2) interrupt vectors. 11557ca00409SHaim Dreyfuss */ 11567ca00409SHaim Dreyfuss val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 11577ca00409SHaim Dreyfuss for (idx = 1; idx < trans->num_rx_queues; idx++) { 11587ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 11597ca00409SHaim Dreyfuss MSIX_FH_INT_CAUSES_Q(idx - offset)); 11607ca00409SHaim Dreyfuss val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 11617ca00409SHaim Dreyfuss } 11627ca00409SHaim Dreyfuss iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 11637ca00409SHaim Dreyfuss 11647ca00409SHaim Dreyfuss val = MSIX_FH_INT_CAUSES_Q(0); 11657ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 11667ca00409SHaim Dreyfuss val |= MSIX_NON_AUTO_CLEAR_CAUSE; 11677ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 11687ca00409SHaim Dreyfuss 11697ca00409SHaim Dreyfuss if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 11707ca00409SHaim Dreyfuss iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 11717ca00409SHaim Dreyfuss } 11727ca00409SHaim Dreyfuss 117377c09bc8SSara Sharon void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 11747ca00409SHaim Dreyfuss { 11757ca00409SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 11767ca00409SHaim Dreyfuss 11777ca00409SHaim Dreyfuss if (!trans_pcie->msix_enabled) { 1178d7270d61SHaim Dreyfuss if (trans->cfg->mq_rx_supported && 1179d7270d61SHaim Dreyfuss test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 11807ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, 11817ca00409SHaim Dreyfuss UREG_CHICK_MSI_ENABLE); 11827ca00409SHaim Dreyfuss return; 11837ca00409SHaim Dreyfuss } 1184d7270d61SHaim Dreyfuss /* 1185d7270d61SHaim Dreyfuss * The IVAR table needs to be configured again after reset, 1186d7270d61SHaim Dreyfuss * but if the device is disabled, we can't write to 1187d7270d61SHaim Dreyfuss * prph. 1188d7270d61SHaim Dreyfuss */ 1189d7270d61SHaim Dreyfuss if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 11907ca00409SHaim Dreyfuss iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 11917ca00409SHaim Dreyfuss 11927ca00409SHaim Dreyfuss /* 11937ca00409SHaim Dreyfuss * Each cause from the causes list above and the RX causes is 11947ca00409SHaim Dreyfuss * represented as a byte in the IVAR table. The first nibble 11957ca00409SHaim Dreyfuss * represents the bound interrupt vector of the cause, the second 11967ca00409SHaim Dreyfuss * represents no auto clear for this cause. This will be set if its 11977ca00409SHaim Dreyfuss * interrupt vector is bound to serve other causes. 11987ca00409SHaim Dreyfuss */ 11997ca00409SHaim Dreyfuss iwl_pcie_map_rx_causes(trans); 12007ca00409SHaim Dreyfuss 12017ca00409SHaim Dreyfuss iwl_pcie_map_non_rx_causes(trans); 120283730058SHaim Dreyfuss } 12037ca00409SHaim Dreyfuss 120483730058SHaim Dreyfuss static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 120583730058SHaim Dreyfuss { 120683730058SHaim Dreyfuss struct iwl_trans *trans = trans_pcie->trans; 120783730058SHaim Dreyfuss 120883730058SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 120983730058SHaim Dreyfuss 121083730058SHaim Dreyfuss if (!trans_pcie->msix_enabled) 121183730058SHaim Dreyfuss return; 121283730058SHaim Dreyfuss 121383730058SHaim Dreyfuss trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 12147ca00409SHaim Dreyfuss trans_pcie->fh_mask = trans_pcie->fh_init_mask; 121583730058SHaim Dreyfuss trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 12167ca00409SHaim Dreyfuss trans_pcie->hw_mask = trans_pcie->hw_init_mask; 12177ca00409SHaim Dreyfuss } 12187ca00409SHaim Dreyfuss 1219e705c121SKalle Valo static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1220e705c121SKalle Valo { 1221e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1222e705c121SKalle Valo 1223e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1224e705c121SKalle Valo 1225e705c121SKalle Valo if (trans_pcie->is_down) 1226e705c121SKalle Valo return; 1227e705c121SKalle Valo 1228e705c121SKalle Valo trans_pcie->is_down = true; 1229e705c121SKalle Valo 12300232d2cdSSara Sharon /* Stop dbgc before stopping device */ 12310232d2cdSSara Sharon if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) { 12320232d2cdSSara Sharon iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 12330232d2cdSSara Sharon } else { 12340232d2cdSSara Sharon iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); 12350232d2cdSSara Sharon udelay(100); 12360232d2cdSSara Sharon iwl_write_prph(trans, DBGC_OUT_CTRL, 0); 12370232d2cdSSara Sharon } 12380232d2cdSSara Sharon 1239e705c121SKalle Valo /* tell the device to stop sending interrupts */ 1240e705c121SKalle Valo iwl_disable_interrupts(trans); 1241e705c121SKalle Valo 1242e705c121SKalle Valo /* device going down, Stop using ICT table */ 1243e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1244e705c121SKalle Valo 1245e705c121SKalle Valo /* 1246e705c121SKalle Valo * If a HW restart happens during firmware loading, 1247e705c121SKalle Valo * then the firmware loading might call this function 1248e705c121SKalle Valo * and later it might be called again due to the 1249e705c121SKalle Valo * restart. So don't process again if the device is 1250e705c121SKalle Valo * already dead. 1251e705c121SKalle Valo */ 1252e705c121SKalle Valo if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1253a6bd005fSEmmanuel Grumbach IWL_DEBUG_INFO(trans, 1254a6bd005fSEmmanuel Grumbach "DEVICE_ENABLED bit was set and is now cleared\n"); 1255e705c121SKalle Valo iwl_pcie_tx_stop(trans); 1256e705c121SKalle Valo iwl_pcie_rx_stop(trans); 1257e705c121SKalle Valo 1258e705c121SKalle Valo /* Power-down device's busmaster DMA clocks */ 1259e705c121SKalle Valo if (!trans->cfg->apmg_not_supported) { 1260e705c121SKalle Valo iwl_write_prph(trans, APMG_CLK_DIS_REG, 1261e705c121SKalle Valo APMG_CLK_VAL_DMA_CLK_RQT); 1262e705c121SKalle Valo udelay(5); 1263e705c121SKalle Valo } 1264e705c121SKalle Valo } 1265e705c121SKalle Valo 1266e705c121SKalle Valo /* Make sure (redundant) we've released our request to stay awake */ 1267e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1268e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1269e705c121SKalle Valo 1270e705c121SKalle Valo /* Stop the device, and put it in low power state */ 1271e705c121SKalle Valo iwl_pcie_apm_stop(trans, false); 1272e705c121SKalle Valo 1273099a628bSEmmanuel Grumbach iwl_pcie_sw_reset(trans); 1274e705c121SKalle Valo 1275e705c121SKalle Valo /* 1276f4a1f04aSGolan Ben Ami * Upon stop, the IVAR table gets erased, so msi-x won't 1277f4a1f04aSGolan Ben Ami * work. This causes a bug in RF-KILL flows, since the interrupt 1278f4a1f04aSGolan Ben Ami * that enables radio won't fire on the correct irq, and the 1279f4a1f04aSGolan Ben Ami * driver won't be able to handle the interrupt. 1280f4a1f04aSGolan Ben Ami * Configure the IVAR table again after reset. 1281f4a1f04aSGolan Ben Ami */ 1282f4a1f04aSGolan Ben Ami iwl_pcie_conf_msix_hw(trans_pcie); 1283f4a1f04aSGolan Ben Ami 1284f4a1f04aSGolan Ben Ami /* 1285e705c121SKalle Valo * Upon stop, the APM issues an interrupt if HW RF kill is set. 1286e705c121SKalle Valo * This is a bug in certain verions of the hardware. 1287e705c121SKalle Valo * Certain devices also keep sending HW RF kill interrupt all 1288e705c121SKalle Valo * the time, unless the interrupt is ACKed even if the interrupt 1289e705c121SKalle Valo * should be masked. Re-ACK all the interrupts here. 1290e705c121SKalle Valo */ 1291e705c121SKalle Valo iwl_disable_interrupts(trans); 1292e705c121SKalle Valo 1293e705c121SKalle Valo /* clear all status bits */ 1294e705c121SKalle Valo clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1295e705c121SKalle Valo clear_bit(STATUS_INT_ENABLED, &trans->status); 1296e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1297e705c121SKalle Valo 1298e705c121SKalle Valo /* 1299e705c121SKalle Valo * Even if we stop the HW, we still want the RF kill 1300e705c121SKalle Valo * interrupt 1301e705c121SKalle Valo */ 1302e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1303e705c121SKalle Valo 1304a6bd005fSEmmanuel Grumbach /* re-take ownership to prevent other users from stealing the device */ 1305e705c121SKalle Valo iwl_pcie_prepare_card_hw(trans); 1306e705c121SKalle Valo } 1307e705c121SKalle Valo 1308eda50cdeSSara Sharon void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 13092e5d4a8fSHaim Dreyfuss { 13102e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 13112e5d4a8fSHaim Dreyfuss 13122e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 13132e5d4a8fSHaim Dreyfuss int i; 13142e5d4a8fSHaim Dreyfuss 1315496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) 13162e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->msix_entries[i].vector); 13172e5d4a8fSHaim Dreyfuss } else { 13182e5d4a8fSHaim Dreyfuss synchronize_irq(trans_pcie->pci_dev->irq); 13192e5d4a8fSHaim Dreyfuss } 13202e5d4a8fSHaim Dreyfuss } 13212e5d4a8fSHaim Dreyfuss 1322a6bd005fSEmmanuel Grumbach static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1323a6bd005fSEmmanuel Grumbach const struct fw_img *fw, bool run_in_rfkill) 1324a6bd005fSEmmanuel Grumbach { 1325a6bd005fSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1326a6bd005fSEmmanuel Grumbach bool hw_rfkill; 1327a6bd005fSEmmanuel Grumbach int ret; 1328a6bd005fSEmmanuel Grumbach 1329a6bd005fSEmmanuel Grumbach /* This may fail if AMT took ownership of the device */ 1330a6bd005fSEmmanuel Grumbach if (iwl_pcie_prepare_card_hw(trans)) { 1331a6bd005fSEmmanuel Grumbach IWL_WARN(trans, "Exit HW not ready\n"); 1332a6bd005fSEmmanuel Grumbach ret = -EIO; 1333a6bd005fSEmmanuel Grumbach goto out; 1334a6bd005fSEmmanuel Grumbach } 1335a6bd005fSEmmanuel Grumbach 1336a6bd005fSEmmanuel Grumbach iwl_enable_rfkill_int(trans); 1337a6bd005fSEmmanuel Grumbach 1338a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1339a6bd005fSEmmanuel Grumbach 1340a6bd005fSEmmanuel Grumbach /* 1341a6bd005fSEmmanuel Grumbach * We enabled the RF-Kill interrupt and the handler may very 1342a6bd005fSEmmanuel Grumbach * well be running. Disable the interrupts to make sure no other 1343a6bd005fSEmmanuel Grumbach * interrupt can be fired. 1344a6bd005fSEmmanuel Grumbach */ 1345a6bd005fSEmmanuel Grumbach iwl_disable_interrupts(trans); 1346a6bd005fSEmmanuel Grumbach 1347a6bd005fSEmmanuel Grumbach /* Make sure it finished running */ 13482e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1349a6bd005fSEmmanuel Grumbach 1350a6bd005fSEmmanuel Grumbach mutex_lock(&trans_pcie->mutex); 1351a6bd005fSEmmanuel Grumbach 1352a6bd005fSEmmanuel Grumbach /* If platform's RF_KILL switch is NOT set to KILL */ 13539ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1354a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) { 1355a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1356a6bd005fSEmmanuel Grumbach goto out; 1357a6bd005fSEmmanuel Grumbach } 1358a6bd005fSEmmanuel Grumbach 1359a6bd005fSEmmanuel Grumbach /* Someone called stop_device, don't try to start_fw */ 1360a6bd005fSEmmanuel Grumbach if (trans_pcie->is_down) { 1361a6bd005fSEmmanuel Grumbach IWL_WARN(trans, 1362a6bd005fSEmmanuel Grumbach "Can't start_fw since the HW hasn't been started\n"); 136320aa99bbSAnton Protopopov ret = -EIO; 1364a6bd005fSEmmanuel Grumbach goto out; 1365a6bd005fSEmmanuel Grumbach } 1366a6bd005fSEmmanuel Grumbach 1367a6bd005fSEmmanuel Grumbach /* make sure rfkill handshake bits are cleared */ 1368a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1369a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1370a6bd005fSEmmanuel Grumbach CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1371a6bd005fSEmmanuel Grumbach 1372a6bd005fSEmmanuel Grumbach /* clear (again), then enable host interrupts */ 1373a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1374a6bd005fSEmmanuel Grumbach 1375a6bd005fSEmmanuel Grumbach ret = iwl_pcie_nic_init(trans); 1376a6bd005fSEmmanuel Grumbach if (ret) { 1377a6bd005fSEmmanuel Grumbach IWL_ERR(trans, "Unable to init nic\n"); 1378a6bd005fSEmmanuel Grumbach goto out; 1379a6bd005fSEmmanuel Grumbach } 1380a6bd005fSEmmanuel Grumbach 1381a6bd005fSEmmanuel Grumbach /* 1382a6bd005fSEmmanuel Grumbach * Now, we load the firmware and don't want to be interrupted, even 1383a6bd005fSEmmanuel Grumbach * by the RF-Kill interrupt (hence mask all the interrupt besides the 1384a6bd005fSEmmanuel Grumbach * FH_TX interrupt which is needed to load the firmware). If the 1385a6bd005fSEmmanuel Grumbach * RF-Kill switch is toggled, we will find out after having loaded 1386a6bd005fSEmmanuel Grumbach * the firmware and return the proper value to the caller. 1387a6bd005fSEmmanuel Grumbach */ 1388a6bd005fSEmmanuel Grumbach iwl_enable_fw_load_int(trans); 1389a6bd005fSEmmanuel Grumbach 1390a6bd005fSEmmanuel Grumbach /* really make sure rfkill handshake bits are cleared */ 1391a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1392a6bd005fSEmmanuel Grumbach iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1393a6bd005fSEmmanuel Grumbach 1394a6bd005fSEmmanuel Grumbach /* Load the given image to the HW */ 13956e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1396a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1397a6bd005fSEmmanuel Grumbach else 1398a6bd005fSEmmanuel Grumbach ret = iwl_pcie_load_given_ucode(trans, fw); 1399a6bd005fSEmmanuel Grumbach 1400a6bd005fSEmmanuel Grumbach /* re-check RF-Kill state since we may have missed the interrupt */ 14019ad8fd0bSJohannes Berg hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1402a6bd005fSEmmanuel Grumbach if (hw_rfkill && !run_in_rfkill) 1403a6bd005fSEmmanuel Grumbach ret = -ERFKILL; 1404a6bd005fSEmmanuel Grumbach 1405a6bd005fSEmmanuel Grumbach out: 1406a6bd005fSEmmanuel Grumbach mutex_unlock(&trans_pcie->mutex); 1407a6bd005fSEmmanuel Grumbach return ret; 1408a6bd005fSEmmanuel Grumbach } 1409a6bd005fSEmmanuel Grumbach 1410a6bd005fSEmmanuel Grumbach static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1411a6bd005fSEmmanuel Grumbach { 1412a6bd005fSEmmanuel Grumbach iwl_pcie_reset_ict(trans); 1413a6bd005fSEmmanuel Grumbach iwl_pcie_tx_start(trans, scd_addr); 1414a6bd005fSEmmanuel Grumbach } 1415a6bd005fSEmmanuel Grumbach 1416326477e4SJohannes Berg void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1417326477e4SJohannes Berg bool was_in_rfkill) 1418326477e4SJohannes Berg { 1419326477e4SJohannes Berg bool hw_rfkill; 1420326477e4SJohannes Berg 1421326477e4SJohannes Berg /* 1422326477e4SJohannes Berg * Check again since the RF kill state may have changed while 1423326477e4SJohannes Berg * all the interrupts were disabled, in this case we couldn't 1424326477e4SJohannes Berg * receive the RF kill interrupt and update the state in the 1425326477e4SJohannes Berg * op_mode. 1426326477e4SJohannes Berg * Don't call the op_mode if the rkfill state hasn't changed. 1427326477e4SJohannes Berg * This allows the op_mode to call stop_device from the rfkill 1428326477e4SJohannes Berg * notification without endless recursion. Under very rare 1429326477e4SJohannes Berg * circumstances, we might have a small recursion if the rfkill 1430326477e4SJohannes Berg * state changed exactly now while we were called from stop_device. 1431326477e4SJohannes Berg * This is very unlikely but can happen and is supported. 1432326477e4SJohannes Berg */ 1433326477e4SJohannes Berg hw_rfkill = iwl_is_rfkill_set(trans); 1434326477e4SJohannes Berg if (hw_rfkill) { 1435326477e4SJohannes Berg set_bit(STATUS_RFKILL_HW, &trans->status); 1436326477e4SJohannes Berg set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1437326477e4SJohannes Berg } else { 1438326477e4SJohannes Berg clear_bit(STATUS_RFKILL_HW, &trans->status); 1439326477e4SJohannes Berg clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1440326477e4SJohannes Berg } 1441326477e4SJohannes Berg if (hw_rfkill != was_in_rfkill) 1442326477e4SJohannes Berg iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1443326477e4SJohannes Berg } 1444326477e4SJohannes Berg 1445e705c121SKalle Valo static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power) 1446e705c121SKalle Valo { 1447e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1448326477e4SJohannes Berg bool was_in_rfkill; 1449e705c121SKalle Valo 1450e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1451326477e4SJohannes Berg trans_pcie->opmode_down = true; 1452326477e4SJohannes Berg was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1453e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, low_power); 1454326477e4SJohannes Berg iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1455e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1456e705c121SKalle Valo } 1457e705c121SKalle Valo 1458e705c121SKalle Valo void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1459e705c121SKalle Valo { 1460e705c121SKalle Valo struct iwl_trans_pcie __maybe_unused *trans_pcie = 1461e705c121SKalle Valo IWL_TRANS_GET_PCIE_TRANS(trans); 1462e705c121SKalle Valo 1463e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1464e705c121SKalle Valo 1465326477e4SJohannes Berg IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1466326477e4SJohannes Berg state ? "disabled" : "enabled"); 146777c09bc8SSara Sharon if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 146877c09bc8SSara Sharon if (trans->cfg->gen2) 146977c09bc8SSara Sharon _iwl_trans_pcie_gen2_stop_device(trans, true); 147077c09bc8SSara Sharon else 1471e705c121SKalle Valo _iwl_trans_pcie_stop_device(trans, true); 1472e705c121SKalle Valo } 147377c09bc8SSara Sharon } 1474e705c121SKalle Valo 147523ae6128SMatti Gottlieb static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 147623ae6128SMatti Gottlieb bool reset) 1477e705c121SKalle Valo { 147823ae6128SMatti Gottlieb if (!reset) { 1479e705c121SKalle Valo /* Enable persistence mode to avoid reset */ 1480e705c121SKalle Valo iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1481e705c121SKalle Valo CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1482e705c121SKalle Valo } 1483e705c121SKalle Valo 1484e705c121SKalle Valo iwl_disable_interrupts(trans); 1485e705c121SKalle Valo 1486e705c121SKalle Valo /* 1487e705c121SKalle Valo * in testing mode, the host stays awake and the 1488e705c121SKalle Valo * hardware won't be reset (not even partially) 1489e705c121SKalle Valo */ 1490e705c121SKalle Valo if (test) 1491e705c121SKalle Valo return; 1492e705c121SKalle Valo 1493e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1494e705c121SKalle Valo 14952e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1496e705c121SKalle Valo 1497e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1498e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1499e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1500e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1501e705c121SKalle Valo 15021316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, false); 15031316d595SSara Sharon 150423ae6128SMatti Gottlieb if (reset) { 1505e705c121SKalle Valo /* 1506e705c121SKalle Valo * reset TX queues -- some of their registers reset during S3 1507e705c121SKalle Valo * so if we don't reset everything here the D3 image would try 1508e705c121SKalle Valo * to execute some invalid memory upon resume 1509e705c121SKalle Valo */ 1510e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1511e705c121SKalle Valo } 1512e705c121SKalle Valo 1513e705c121SKalle Valo iwl_pcie_set_pwr(trans, true); 1514e705c121SKalle Valo } 1515e705c121SKalle Valo 1516e705c121SKalle Valo static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1517e705c121SKalle Valo enum iwl_d3_status *status, 151823ae6128SMatti Gottlieb bool test, bool reset) 1519e705c121SKalle Valo { 1520d7270d61SHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1521e705c121SKalle Valo u32 val; 1522e705c121SKalle Valo int ret; 1523e705c121SKalle Valo 1524e705c121SKalle Valo if (test) { 1525e705c121SKalle Valo iwl_enable_interrupts(trans); 1526e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1527e705c121SKalle Valo return 0; 1528e705c121SKalle Valo } 1529e705c121SKalle Valo 15301316d595SSara Sharon iwl_pcie_enable_rx_wake(trans, true); 15311316d595SSara Sharon 1532e705c121SKalle Valo /* 1533d7270d61SHaim Dreyfuss * Reconfigure IVAR table in case of MSIX or reset ict table in 1534d7270d61SHaim Dreyfuss * MSI mode since HW reset erased it. 1535d7270d61SHaim Dreyfuss * Also enables interrupts - none will happen as 1536d7270d61SHaim Dreyfuss * the device doesn't know we're waking it up, only when 1537d7270d61SHaim Dreyfuss * the opmode actually tells it after this call. 1538e705c121SKalle Valo */ 1539d7270d61SHaim Dreyfuss iwl_pcie_conf_msix_hw(trans_pcie); 1540d7270d61SHaim Dreyfuss if (!trans_pcie->msix_enabled) 1541e705c121SKalle Valo iwl_pcie_reset_ict(trans); 154218dcb9a9SSara Sharon iwl_enable_interrupts(trans); 1543e705c121SKalle Valo 1544e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1545e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1546e705c121SKalle Valo 15476e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1548e705c121SKalle Valo udelay(2); 1549e705c121SKalle Valo 1550e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1551e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1552e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 1553e705c121SKalle Valo 25000); 1554e705c121SKalle Valo if (ret < 0) { 1555e705c121SKalle Valo IWL_ERR(trans, "Failed to resume the device (mac ready)\n"); 1556e705c121SKalle Valo return ret; 1557e705c121SKalle Valo } 1558e705c121SKalle Valo 1559e705c121SKalle Valo iwl_pcie_set_pwr(trans, false); 1560e705c121SKalle Valo 156123ae6128SMatti Gottlieb if (!reset) { 1562e705c121SKalle Valo iwl_clear_bit(trans, CSR_GP_CNTRL, 1563e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1564e705c121SKalle Valo } else { 1565e705c121SKalle Valo iwl_trans_pcie_tx_reset(trans); 1566e705c121SKalle Valo 1567e705c121SKalle Valo ret = iwl_pcie_rx_init(trans); 1568e705c121SKalle Valo if (ret) { 1569e705c121SKalle Valo IWL_ERR(trans, 1570e705c121SKalle Valo "Failed to resume the device (RX reset)\n"); 1571e705c121SKalle Valo return ret; 1572e705c121SKalle Valo } 1573e705c121SKalle Valo } 1574e705c121SKalle Valo 157582ea7966SSara Sharon IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 157682ea7966SSara Sharon iwl_read_prph(trans, WFPM_GP2)); 157782ea7966SSara Sharon 1578e705c121SKalle Valo val = iwl_read32(trans, CSR_RESET); 1579e705c121SKalle Valo if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1580e705c121SKalle Valo *status = IWL_D3_STATUS_RESET; 1581e705c121SKalle Valo else 1582e705c121SKalle Valo *status = IWL_D3_STATUS_ALIVE; 1583e705c121SKalle Valo 1584e705c121SKalle Valo return 0; 1585e705c121SKalle Valo } 1586e705c121SKalle Valo 15872e5d4a8fSHaim Dreyfuss static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 15882e5d4a8fSHaim Dreyfuss struct iwl_trans *trans) 15892e5d4a8fSHaim Dreyfuss { 15902e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 15919fb064dfSHaim Dreyfuss int max_irqs, num_irqs, i, ret, nr_online_cpus; 15922e5d4a8fSHaim Dreyfuss u16 pci_cmd; 15932e5d4a8fSHaim Dreyfuss 159406f4b081SSara Sharon if (!trans->cfg->mq_rx_supported) 159506f4b081SSara Sharon goto enable_msi; 159606f4b081SSara Sharon 15979fb064dfSHaim Dreyfuss nr_online_cpus = num_online_cpus(); 15989fb064dfSHaim Dreyfuss max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES); 159906f4b081SSara Sharon for (i = 0; i < max_irqs; i++) 16002e5d4a8fSHaim Dreyfuss trans_pcie->msix_entries[i].entry = i; 16012e5d4a8fSHaim Dreyfuss 160206f4b081SSara Sharon num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 16032e5d4a8fSHaim Dreyfuss MSIX_MIN_INTERRUPT_VECTORS, 160406f4b081SSara Sharon max_irqs); 160506f4b081SSara Sharon if (num_irqs < 0) { 1606496d83caSHaim Dreyfuss IWL_DEBUG_INFO(trans, 160706f4b081SSara Sharon "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 160806f4b081SSara Sharon num_irqs); 160906f4b081SSara Sharon goto enable_msi; 1610496d83caSHaim Dreyfuss } 161106f4b081SSara Sharon trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1612496d83caSHaim Dreyfuss 16132e5d4a8fSHaim Dreyfuss IWL_DEBUG_INFO(trans, 161406f4b081SSara Sharon "MSI-X enabled. %d interrupt vectors were allocated\n", 161506f4b081SSara Sharon num_irqs); 161606f4b081SSara Sharon 1617496d83caSHaim Dreyfuss /* 161806f4b081SSara Sharon * In case the OS provides fewer interrupts than requested, different 161906f4b081SSara Sharon * causes will share the same interrupt vector as follows: 1620496d83caSHaim Dreyfuss * One interrupt less: non rx causes shared with FBQ. 1621496d83caSHaim Dreyfuss * Two interrupts less: non rx causes shared with FBQ and RSS. 1622496d83caSHaim Dreyfuss * More than two interrupts: we will use fewer RSS queues. 1623496d83caSHaim Dreyfuss */ 16249fb064dfSHaim Dreyfuss if (num_irqs <= nr_online_cpus) { 162506f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs + 1; 1626496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1627496d83caSHaim Dreyfuss IWL_SHARED_IRQ_FIRST_RSS; 16289fb064dfSHaim Dreyfuss } else if (num_irqs == nr_online_cpus + 1) { 162906f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs; 1630496d83caSHaim Dreyfuss trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1631496d83caSHaim Dreyfuss } else { 163206f4b081SSara Sharon trans_pcie->trans->num_rx_queues = num_irqs - 1; 1633496d83caSHaim Dreyfuss } 16342e5d4a8fSHaim Dreyfuss 163506f4b081SSara Sharon trans_pcie->alloc_vecs = num_irqs; 1636496d83caSHaim Dreyfuss trans_pcie->msix_enabled = true; 16372e5d4a8fSHaim Dreyfuss return; 16382e5d4a8fSHaim Dreyfuss 163906f4b081SSara Sharon enable_msi: 164006f4b081SSara Sharon ret = pci_enable_msi(pdev); 164106f4b081SSara Sharon if (ret) { 164206f4b081SSara Sharon dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 16432e5d4a8fSHaim Dreyfuss /* enable rfkill interrupt: hw bug w/a */ 16442e5d4a8fSHaim Dreyfuss pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 16452e5d4a8fSHaim Dreyfuss if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 16462e5d4a8fSHaim Dreyfuss pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 16472e5d4a8fSHaim Dreyfuss pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 16482e5d4a8fSHaim Dreyfuss } 16492e5d4a8fSHaim Dreyfuss } 16502e5d4a8fSHaim Dreyfuss } 16512e5d4a8fSHaim Dreyfuss 16527c8d91ebSHaim Dreyfuss static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 16537c8d91ebSHaim Dreyfuss { 16547c8d91ebSHaim Dreyfuss int iter_rx_q, i, ret, cpu, offset; 16557c8d91ebSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 16567c8d91ebSHaim Dreyfuss 16577c8d91ebSHaim Dreyfuss i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 16587c8d91ebSHaim Dreyfuss iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 16597c8d91ebSHaim Dreyfuss offset = 1 + i; 16607c8d91ebSHaim Dreyfuss for (; i < iter_rx_q ; i++) { 16617c8d91ebSHaim Dreyfuss /* 16627c8d91ebSHaim Dreyfuss * Get the cpu prior to the place to search 16637c8d91ebSHaim Dreyfuss * (i.e. return will be > i - 1). 16647c8d91ebSHaim Dreyfuss */ 16657c8d91ebSHaim Dreyfuss cpu = cpumask_next(i - offset, cpu_online_mask); 16667c8d91ebSHaim Dreyfuss cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 16677c8d91ebSHaim Dreyfuss ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 16687c8d91ebSHaim Dreyfuss &trans_pcie->affinity_mask[i]); 16697c8d91ebSHaim Dreyfuss if (ret) 16707c8d91ebSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 16717c8d91ebSHaim Dreyfuss "Failed to set affinity mask for IRQ %d\n", 16727c8d91ebSHaim Dreyfuss i); 16737c8d91ebSHaim Dreyfuss } 16747c8d91ebSHaim Dreyfuss } 16757c8d91ebSHaim Dreyfuss 167664fa3affSSharon Dvir static const char *queue_name(struct device *dev, 167764fa3affSSharon Dvir struct iwl_trans_pcie *trans_p, int i) 167864fa3affSSharon Dvir { 167964fa3affSSharon Dvir if (trans_p->shared_vec_mask) { 168064fa3affSSharon Dvir int vec = trans_p->shared_vec_mask & 168164fa3affSSharon Dvir IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 168264fa3affSSharon Dvir 168364fa3affSSharon Dvir if (i == 0) 168464fa3affSSharon Dvir return DRV_NAME ": shared IRQ"; 168564fa3affSSharon Dvir 168664fa3affSSharon Dvir return devm_kasprintf(dev, GFP_KERNEL, 168764fa3affSSharon Dvir DRV_NAME ": queue %d", i + vec); 168864fa3affSSharon Dvir } 168964fa3affSSharon Dvir if (i == 0) 169064fa3affSSharon Dvir return DRV_NAME ": default queue"; 169164fa3affSSharon Dvir 169264fa3affSSharon Dvir if (i == trans_p->alloc_vecs - 1) 169364fa3affSSharon Dvir return DRV_NAME ": exception"; 169464fa3affSSharon Dvir 169564fa3affSSharon Dvir return devm_kasprintf(dev, GFP_KERNEL, 169664fa3affSSharon Dvir DRV_NAME ": queue %d", i); 169764fa3affSSharon Dvir } 169864fa3affSSharon Dvir 16992e5d4a8fSHaim Dreyfuss static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 17002e5d4a8fSHaim Dreyfuss struct iwl_trans_pcie *trans_pcie) 17012e5d4a8fSHaim Dreyfuss { 1702496d83caSHaim Dreyfuss int i; 17032e5d4a8fSHaim Dreyfuss 1704496d83caSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 17052e5d4a8fSHaim Dreyfuss int ret; 17065a41a86cSSharon Dvir struct msix_entry *msix_entry; 170764fa3affSSharon Dvir const char *qname = queue_name(&pdev->dev, trans_pcie, i); 170864fa3affSSharon Dvir 170964fa3affSSharon Dvir if (!qname) 171064fa3affSSharon Dvir return -ENOMEM; 17112e5d4a8fSHaim Dreyfuss 17125a41a86cSSharon Dvir msix_entry = &trans_pcie->msix_entries[i]; 17135a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, 17145a41a86cSSharon Dvir msix_entry->vector, 17152e5d4a8fSHaim Dreyfuss iwl_pcie_msix_isr, 1716496d83caSHaim Dreyfuss (i == trans_pcie->def_irq) ? 17172e5d4a8fSHaim Dreyfuss iwl_pcie_irq_msix_handler : 17182e5d4a8fSHaim Dreyfuss iwl_pcie_irq_rx_msix_handler, 17192e5d4a8fSHaim Dreyfuss IRQF_SHARED, 172064fa3affSSharon Dvir qname, 17215a41a86cSSharon Dvir msix_entry); 17222e5d4a8fSHaim Dreyfuss if (ret) { 17232e5d4a8fSHaim Dreyfuss IWL_ERR(trans_pcie->trans, 17242e5d4a8fSHaim Dreyfuss "Error allocating IRQ %d\n", i); 17255a41a86cSSharon Dvir 17262e5d4a8fSHaim Dreyfuss return ret; 17272e5d4a8fSHaim Dreyfuss } 17282e5d4a8fSHaim Dreyfuss } 17297c8d91ebSHaim Dreyfuss iwl_pcie_irq_set_affinity(trans_pcie->trans); 17302e5d4a8fSHaim Dreyfuss 17312e5d4a8fSHaim Dreyfuss return 0; 17322e5d4a8fSHaim Dreyfuss } 17332e5d4a8fSHaim Dreyfuss 1734e705c121SKalle Valo static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1735e705c121SKalle Valo { 1736e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1737e705c121SKalle Valo int err; 1738e705c121SKalle Valo 1739e705c121SKalle Valo lockdep_assert_held(&trans_pcie->mutex); 1740e705c121SKalle Valo 1741e705c121SKalle Valo err = iwl_pcie_prepare_card_hw(trans); 1742e705c121SKalle Valo if (err) { 1743e705c121SKalle Valo IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1744e705c121SKalle Valo return err; 1745e705c121SKalle Valo } 1746e705c121SKalle Valo 1747099a628bSEmmanuel Grumbach iwl_pcie_sw_reset(trans); 1748e705c121SKalle Valo 174952b6e168SEmmanuel Grumbach err = iwl_pcie_apm_init(trans); 175052b6e168SEmmanuel Grumbach if (err) 175152b6e168SEmmanuel Grumbach return err; 1752e705c121SKalle Valo 17532e5d4a8fSHaim Dreyfuss iwl_pcie_init_msix(trans_pcie); 175483730058SHaim Dreyfuss 1755e705c121SKalle Valo /* From now on, the op_mode will be kept updated about RF kill state */ 1756e705c121SKalle Valo iwl_enable_rfkill_int(trans); 1757e705c121SKalle Valo 1758326477e4SJohannes Berg trans_pcie->opmode_down = false; 1759326477e4SJohannes Berg 1760e705c121SKalle Valo /* Set is_down to false here so that...*/ 1761e705c121SKalle Valo trans_pcie->is_down = false; 1762e705c121SKalle Valo 1763e705c121SKalle Valo /* ...rfkill can call stop_device and set it false if needed */ 17649ad8fd0bSJohannes Berg iwl_pcie_check_hw_rf_kill(trans); 1765e705c121SKalle Valo 17664cbb8e50SLuciano Coelho /* Make sure we sync here, because we'll need full access later */ 17674cbb8e50SLuciano Coelho if (low_power) 17684cbb8e50SLuciano Coelho pm_runtime_resume(trans->dev); 17694cbb8e50SLuciano Coelho 1770e705c121SKalle Valo return 0; 1771e705c121SKalle Valo } 1772e705c121SKalle Valo 1773e705c121SKalle Valo static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power) 1774e705c121SKalle Valo { 1775e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1776e705c121SKalle Valo int ret; 1777e705c121SKalle Valo 1778e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1779e705c121SKalle Valo ret = _iwl_trans_pcie_start_hw(trans, low_power); 1780e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1781e705c121SKalle Valo 1782e705c121SKalle Valo return ret; 1783e705c121SKalle Valo } 1784e705c121SKalle Valo 1785e705c121SKalle Valo static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1786e705c121SKalle Valo { 1787e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1788e705c121SKalle Valo 1789e705c121SKalle Valo mutex_lock(&trans_pcie->mutex); 1790e705c121SKalle Valo 1791e705c121SKalle Valo /* disable interrupts - don't enable HW RF kill interrupt */ 1792e705c121SKalle Valo iwl_disable_interrupts(trans); 1793e705c121SKalle Valo 1794e705c121SKalle Valo iwl_pcie_apm_stop(trans, true); 1795e705c121SKalle Valo 1796e705c121SKalle Valo iwl_disable_interrupts(trans); 1797e705c121SKalle Valo 1798e705c121SKalle Valo iwl_pcie_disable_ict(trans); 1799e705c121SKalle Valo 1800e705c121SKalle Valo mutex_unlock(&trans_pcie->mutex); 1801e705c121SKalle Valo 18022e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1803e705c121SKalle Valo } 1804e705c121SKalle Valo 1805e705c121SKalle Valo static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1806e705c121SKalle Valo { 1807e705c121SKalle Valo writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1808e705c121SKalle Valo } 1809e705c121SKalle Valo 1810e705c121SKalle Valo static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1811e705c121SKalle Valo { 1812e705c121SKalle Valo writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1813e705c121SKalle Valo } 1814e705c121SKalle Valo 1815e705c121SKalle Valo static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1816e705c121SKalle Valo { 1817e705c121SKalle Valo return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1818e705c121SKalle Valo } 1819e705c121SKalle Valo 1820e705c121SKalle Valo static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1821e705c121SKalle Valo { 1822e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1823e705c121SKalle Valo ((reg & 0x000FFFFF) | (3 << 24))); 1824e705c121SKalle Valo return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1825e705c121SKalle Valo } 1826e705c121SKalle Valo 1827e705c121SKalle Valo static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1828e705c121SKalle Valo u32 val) 1829e705c121SKalle Valo { 1830e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1831e705c121SKalle Valo ((addr & 0x000FFFFF) | (3 << 24))); 1832e705c121SKalle Valo iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1833e705c121SKalle Valo } 1834e705c121SKalle Valo 1835e705c121SKalle Valo static void iwl_trans_pcie_configure(struct iwl_trans *trans, 1836e705c121SKalle Valo const struct iwl_trans_config *trans_cfg) 1837e705c121SKalle Valo { 1838e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1839e705c121SKalle Valo 1840e705c121SKalle Valo trans_pcie->cmd_queue = trans_cfg->cmd_queue; 1841e705c121SKalle Valo trans_pcie->cmd_fifo = trans_cfg->cmd_fifo; 1842e705c121SKalle Valo trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 1843e705c121SKalle Valo if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 1844e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = 0; 1845e705c121SKalle Valo else 1846e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 1847e705c121SKalle Valo if (trans_pcie->n_no_reclaim_cmds) 1848e705c121SKalle Valo memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 1849e705c121SKalle Valo trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 1850e705c121SKalle Valo 18516c4fbcbcSEmmanuel Grumbach trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 18526c4fbcbcSEmmanuel Grumbach trans_pcie->rx_page_order = 18536c4fbcbcSEmmanuel Grumbach iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 1854e705c121SKalle Valo 1855e705c121SKalle Valo trans_pcie->bc_table_dword = trans_cfg->bc_table_dword; 1856e705c121SKalle Valo trans_pcie->scd_set_active = trans_cfg->scd_set_active; 185741837ca9SEmmanuel Grumbach trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx; 1858e705c121SKalle Valo 185921cb3222SJohannes Berg trans_pcie->page_offs = trans_cfg->cb_data_offs; 186021cb3222SJohannes Berg trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 186121cb3222SJohannes Berg 186239bdb17eSSharon Dvir trans->command_groups = trans_cfg->command_groups; 186339bdb17eSSharon Dvir trans->command_groups_size = trans_cfg->command_groups_size; 186439bdb17eSSharon Dvir 1865e705c121SKalle Valo /* Initialize NAPI here - it should be before registering to mac80211 1866e705c121SKalle Valo * in the opmode but after the HW struct is allocated. 1867e705c121SKalle Valo * As this function may be called again in some corner cases don't 1868e705c121SKalle Valo * do anything if NAPI was already initialized. 1869e705c121SKalle Valo */ 1870bce97731SSara Sharon if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 1871e705c121SKalle Valo init_dummy_netdev(&trans_pcie->napi_dev); 1872e705c121SKalle Valo } 1873e705c121SKalle Valo 1874e705c121SKalle Valo void iwl_trans_pcie_free(struct iwl_trans *trans) 1875e705c121SKalle Valo { 1876e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 18776eb5e529SEmmanuel Grumbach int i; 1878e705c121SKalle Valo 18792e5d4a8fSHaim Dreyfuss iwl_pcie_synchronize_irqs(trans); 1880e705c121SKalle Valo 188113a3a390SSara Sharon if (trans->cfg->gen2) 188213a3a390SSara Sharon iwl_pcie_gen2_tx_free(trans); 188313a3a390SSara Sharon else 1884e705c121SKalle Valo iwl_pcie_tx_free(trans); 1885e705c121SKalle Valo iwl_pcie_rx_free(trans); 1886e705c121SKalle Valo 188710a54d81SLuca Coelho if (trans_pcie->rba.alloc_wq) { 188810a54d81SLuca Coelho destroy_workqueue(trans_pcie->rba.alloc_wq); 188910a54d81SLuca Coelho trans_pcie->rba.alloc_wq = NULL; 189010a54d81SLuca Coelho } 189110a54d81SLuca Coelho 18922e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 18937c8d91ebSHaim Dreyfuss for (i = 0; i < trans_pcie->alloc_vecs; i++) { 18947c8d91ebSHaim Dreyfuss irq_set_affinity_hint( 18957c8d91ebSHaim Dreyfuss trans_pcie->msix_entries[i].vector, 18967c8d91ebSHaim Dreyfuss NULL); 18977c8d91ebSHaim Dreyfuss } 18982e5d4a8fSHaim Dreyfuss 18992e5d4a8fSHaim Dreyfuss trans_pcie->msix_enabled = false; 19002e5d4a8fSHaim Dreyfuss } else { 1901e705c121SKalle Valo iwl_pcie_free_ict(trans); 19022e5d4a8fSHaim Dreyfuss } 1903e705c121SKalle Valo 1904e705c121SKalle Valo iwl_pcie_free_fw_monitor(trans); 1905e705c121SKalle Valo 19066eb5e529SEmmanuel Grumbach for_each_possible_cpu(i) { 19076eb5e529SEmmanuel Grumbach struct iwl_tso_hdr_page *p = 19086eb5e529SEmmanuel Grumbach per_cpu_ptr(trans_pcie->tso_hdr_page, i); 19096eb5e529SEmmanuel Grumbach 19106eb5e529SEmmanuel Grumbach if (p->page) 19116eb5e529SEmmanuel Grumbach __free_page(p->page); 19126eb5e529SEmmanuel Grumbach } 19136eb5e529SEmmanuel Grumbach 19146eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 1915a2a57a35SEmmanuel Grumbach mutex_destroy(&trans_pcie->mutex); 1916e705c121SKalle Valo iwl_trans_free(trans); 1917e705c121SKalle Valo } 1918e705c121SKalle Valo 1919e705c121SKalle Valo static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 1920e705c121SKalle Valo { 1921e705c121SKalle Valo if (state) 1922e705c121SKalle Valo set_bit(STATUS_TPOWER_PMI, &trans->status); 1923e705c121SKalle Valo else 1924e705c121SKalle Valo clear_bit(STATUS_TPOWER_PMI, &trans->status); 1925e705c121SKalle Valo } 1926e705c121SKalle Valo 192723ba9340SEmmanuel Grumbach static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, 1928e705c121SKalle Valo unsigned long *flags) 1929e705c121SKalle Valo { 1930e705c121SKalle Valo int ret; 1931e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1932e705c121SKalle Valo 1933e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, *flags); 1934e705c121SKalle Valo 1935e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 1936e705c121SKalle Valo goto out; 1937e705c121SKalle Valo 1938e705c121SKalle Valo /* this bit wakes up the NIC */ 1939e705c121SKalle Valo __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 1940e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 19416e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1942e705c121SKalle Valo udelay(2); 1943e705c121SKalle Valo 1944e705c121SKalle Valo /* 1945e705c121SKalle Valo * These bits say the device is running, and should keep running for 1946e705c121SKalle Valo * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 1947e705c121SKalle Valo * but they do not indicate that embedded SRAM is restored yet; 1948fb70d49fSLuca Coelho * HW with volatile SRAM must save/restore contents to/from 1949fb70d49fSLuca Coelho * host DRAM when sleeping/waking for power-saving. 1950e705c121SKalle Valo * Each direction takes approximately 1/4 millisecond; with this 1951e705c121SKalle Valo * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 1952e705c121SKalle Valo * series of register accesses are expected (e.g. reading Event Log), 1953e705c121SKalle Valo * to keep device from sleeping. 1954e705c121SKalle Valo * 1955e705c121SKalle Valo * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 1956e705c121SKalle Valo * SRAM is okay/restored. We don't check that here because this call 1957fb70d49fSLuca Coelho * is just for hardware register access; but GP1 MAC_SLEEP 1958fb70d49fSLuca Coelho * check is a good idea before accessing the SRAM of HW with 1959fb70d49fSLuca Coelho * volatile SRAM (e.g. reading Event Log). 1960e705c121SKalle Valo * 1961e705c121SKalle Valo * 5000 series and later (including 1000 series) have non-volatile SRAM, 1962e705c121SKalle Valo * and do not save/restore SRAM when power cycling. 1963e705c121SKalle Valo */ 1964e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 1965e705c121SKalle Valo CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN, 1966e705c121SKalle Valo (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 1967e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000); 1968e705c121SKalle Valo if (unlikely(ret < 0)) { 1969fb12777aSKirtika Ruchandani iwl_trans_pcie_dump_regs(trans); 1970e705c121SKalle Valo iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI); 1971e705c121SKalle Valo WARN_ONCE(1, 1972e705c121SKalle Valo "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 197323ba9340SEmmanuel Grumbach iwl_read32(trans, CSR_GP_CNTRL)); 1974e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 1975e705c121SKalle Valo return false; 1976e705c121SKalle Valo } 1977e705c121SKalle Valo 1978e705c121SKalle Valo out: 1979e705c121SKalle Valo /* 1980e705c121SKalle Valo * Fool sparse by faking we release the lock - sparse will 1981e705c121SKalle Valo * track nic_access anyway. 1982e705c121SKalle Valo */ 1983e705c121SKalle Valo __release(&trans_pcie->reg_lock); 1984e705c121SKalle Valo return true; 1985e705c121SKalle Valo } 1986e705c121SKalle Valo 1987e705c121SKalle Valo static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans, 1988e705c121SKalle Valo unsigned long *flags) 1989e705c121SKalle Valo { 1990e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1991e705c121SKalle Valo 1992e705c121SKalle Valo lockdep_assert_held(&trans_pcie->reg_lock); 1993e705c121SKalle Valo 1994e705c121SKalle Valo /* 1995e705c121SKalle Valo * Fool sparse by faking we acquiring the lock - sparse will 1996e705c121SKalle Valo * track nic_access anyway. 1997e705c121SKalle Valo */ 1998e705c121SKalle Valo __acquire(&trans_pcie->reg_lock); 1999e705c121SKalle Valo 2000e705c121SKalle Valo if (trans_pcie->cmd_hold_nic_awake) 2001e705c121SKalle Valo goto out; 2002e705c121SKalle Valo 2003e705c121SKalle Valo __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2004e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2005e705c121SKalle Valo /* 2006e705c121SKalle Valo * Above we read the CSR_GP_CNTRL register, which will flush 2007e705c121SKalle Valo * any previous writes, but we need the write that clears the 2008e705c121SKalle Valo * MAC_ACCESS_REQ bit to be performed before any other writes 2009e705c121SKalle Valo * scheduled on different CPUs (after we drop reg_lock). 2010e705c121SKalle Valo */ 2011e705c121SKalle Valo mmiowb(); 2012e705c121SKalle Valo out: 2013e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags); 2014e705c121SKalle Valo } 2015e705c121SKalle Valo 2016e705c121SKalle Valo static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2017e705c121SKalle Valo void *buf, int dwords) 2018e705c121SKalle Valo { 2019e705c121SKalle Valo unsigned long flags; 2020e705c121SKalle Valo int offs, ret = 0; 2021e705c121SKalle Valo u32 *vals = buf; 2022e705c121SKalle Valo 202323ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2024e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); 2025e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2026e705c121SKalle Valo vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); 2027e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2028e705c121SKalle Valo } else { 2029e705c121SKalle Valo ret = -EBUSY; 2030e705c121SKalle Valo } 2031e705c121SKalle Valo return ret; 2032e705c121SKalle Valo } 2033e705c121SKalle Valo 2034e705c121SKalle Valo static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2035e705c121SKalle Valo const void *buf, int dwords) 2036e705c121SKalle Valo { 2037e705c121SKalle Valo unsigned long flags; 2038e705c121SKalle Valo int offs, ret = 0; 2039e705c121SKalle Valo const u32 *vals = buf; 2040e705c121SKalle Valo 204123ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 2042e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2043e705c121SKalle Valo for (offs = 0; offs < dwords; offs++) 2044e705c121SKalle Valo iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2045e705c121SKalle Valo vals ? vals[offs] : 0); 2046e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2047e705c121SKalle Valo } else { 2048e705c121SKalle Valo ret = -EBUSY; 2049e705c121SKalle Valo } 2050e705c121SKalle Valo return ret; 2051e705c121SKalle Valo } 2052e705c121SKalle Valo 2053e705c121SKalle Valo static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans, 2054e705c121SKalle Valo unsigned long txqs, 2055e705c121SKalle Valo bool freeze) 2056e705c121SKalle Valo { 2057e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2058e705c121SKalle Valo int queue; 2059e705c121SKalle Valo 2060e705c121SKalle Valo for_each_set_bit(queue, &txqs, BITS_PER_LONG) { 2061b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[queue]; 2062e705c121SKalle Valo unsigned long now; 2063e705c121SKalle Valo 2064e705c121SKalle Valo spin_lock_bh(&txq->lock); 2065e705c121SKalle Valo 2066e705c121SKalle Valo now = jiffies; 2067e705c121SKalle Valo 2068e705c121SKalle Valo if (txq->frozen == freeze) 2069e705c121SKalle Valo goto next_queue; 2070e705c121SKalle Valo 2071e705c121SKalle Valo IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n", 2072e705c121SKalle Valo freeze ? "Freezing" : "Waking", queue); 2073e705c121SKalle Valo 2074e705c121SKalle Valo txq->frozen = freeze; 2075e705c121SKalle Valo 2076bb98ecd4SSara Sharon if (txq->read_ptr == txq->write_ptr) 2077e705c121SKalle Valo goto next_queue; 2078e705c121SKalle Valo 2079e705c121SKalle Valo if (freeze) { 2080e705c121SKalle Valo if (unlikely(time_after(now, 2081e705c121SKalle Valo txq->stuck_timer.expires))) { 2082e705c121SKalle Valo /* 2083e705c121SKalle Valo * The timer should have fired, maybe it is 2084e705c121SKalle Valo * spinning right now on the lock. 2085e705c121SKalle Valo */ 2086e705c121SKalle Valo goto next_queue; 2087e705c121SKalle Valo } 2088e705c121SKalle Valo /* remember how long until the timer fires */ 2089e705c121SKalle Valo txq->frozen_expiry_remainder = 2090e705c121SKalle Valo txq->stuck_timer.expires - now; 2091e705c121SKalle Valo del_timer(&txq->stuck_timer); 2092e705c121SKalle Valo goto next_queue; 2093e705c121SKalle Valo } 2094e705c121SKalle Valo 2095e705c121SKalle Valo /* 2096e705c121SKalle Valo * Wake a non-empty queue -> arm timer with the 2097e705c121SKalle Valo * remainder before it froze 2098e705c121SKalle Valo */ 2099e705c121SKalle Valo mod_timer(&txq->stuck_timer, 2100e705c121SKalle Valo now + txq->frozen_expiry_remainder); 2101e705c121SKalle Valo 2102e705c121SKalle Valo next_queue: 2103e705c121SKalle Valo spin_unlock_bh(&txq->lock); 2104e705c121SKalle Valo } 2105e705c121SKalle Valo } 2106e705c121SKalle Valo 21070cd58eaaSEmmanuel Grumbach static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 21080cd58eaaSEmmanuel Grumbach { 21090cd58eaaSEmmanuel Grumbach struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 21100cd58eaaSEmmanuel Grumbach int i; 21110cd58eaaSEmmanuel Grumbach 21120cd58eaaSEmmanuel Grumbach for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { 2113b2a3b1c1SSara Sharon struct iwl_txq *txq = trans_pcie->txq[i]; 21140cd58eaaSEmmanuel Grumbach 21150cd58eaaSEmmanuel Grumbach if (i == trans_pcie->cmd_queue) 21160cd58eaaSEmmanuel Grumbach continue; 21170cd58eaaSEmmanuel Grumbach 21180cd58eaaSEmmanuel Grumbach spin_lock_bh(&txq->lock); 21190cd58eaaSEmmanuel Grumbach 21200cd58eaaSEmmanuel Grumbach if (!block && !(WARN_ON_ONCE(!txq->block))) { 21210cd58eaaSEmmanuel Grumbach txq->block--; 21220cd58eaaSEmmanuel Grumbach if (!txq->block) { 21230cd58eaaSEmmanuel Grumbach iwl_write32(trans, HBUS_TARG_WRPTR, 2124bb98ecd4SSara Sharon txq->write_ptr | (i << 8)); 21250cd58eaaSEmmanuel Grumbach } 21260cd58eaaSEmmanuel Grumbach } else if (block) { 21270cd58eaaSEmmanuel Grumbach txq->block++; 21280cd58eaaSEmmanuel Grumbach } 21290cd58eaaSEmmanuel Grumbach 21300cd58eaaSEmmanuel Grumbach spin_unlock_bh(&txq->lock); 21310cd58eaaSEmmanuel Grumbach } 21320cd58eaaSEmmanuel Grumbach } 21330cd58eaaSEmmanuel Grumbach 2134e705c121SKalle Valo #define IWL_FLUSH_WAIT_MS 2000 2135e705c121SKalle Valo 213638398efbSSara Sharon void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) 213738398efbSSara Sharon { 2138afb84431SEmmanuel Grumbach u32 txq_id = txq->id; 2139afb84431SEmmanuel Grumbach u32 status; 2140afb84431SEmmanuel Grumbach bool active; 2141afb84431SEmmanuel Grumbach u8 fifo; 214238398efbSSara Sharon 2143afb84431SEmmanuel Grumbach if (trans->cfg->use_tfh) { 2144afb84431SEmmanuel Grumbach IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, 2145bb98ecd4SSara Sharon txq->read_ptr, txq->write_ptr); 2146ae79785fSSara Sharon /* TODO: access new SCD registers and dump them */ 2147ae79785fSSara Sharon return; 2148afb84431SEmmanuel Grumbach } 2149ae79785fSSara Sharon 2150afb84431SEmmanuel Grumbach status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); 2151afb84431SEmmanuel Grumbach fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; 2152afb84431SEmmanuel Grumbach active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); 215338398efbSSara Sharon 215438398efbSSara Sharon IWL_ERR(trans, 2155afb84431SEmmanuel Grumbach "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", 2156afb84431SEmmanuel Grumbach txq_id, active ? "" : "in", fifo, 2157afb84431SEmmanuel Grumbach jiffies_to_msecs(txq->wd_timeout), 2158afb84431SEmmanuel Grumbach txq->read_ptr, txq->write_ptr, 2159afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & 216038398efbSSara Sharon (TFD_QUEUE_SIZE_MAX - 1), 2161afb84431SEmmanuel Grumbach iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & 2162afb84431SEmmanuel Grumbach (TFD_QUEUE_SIZE_MAX - 1), 2163afb84431SEmmanuel Grumbach iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); 216438398efbSSara Sharon } 216538398efbSSara Sharon 2166d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2167e705c121SKalle Valo { 2168e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2169e705c121SKalle Valo struct iwl_txq *txq; 2170e705c121SKalle Valo unsigned long now = jiffies; 2171e705c121SKalle Valo u8 wr_ptr; 2172e705c121SKalle Valo 2173d6d517b7SSara Sharon if (!test_bit(txq_idx, trans_pcie->queue_used)) 2174d6d517b7SSara Sharon return -EINVAL; 2175e705c121SKalle Valo 2176d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2177d6d517b7SSara Sharon txq = trans_pcie->txq[txq_idx]; 21786aa7de05SMark Rutland wr_ptr = READ_ONCE(txq->write_ptr); 2179e705c121SKalle Valo 21806aa7de05SMark Rutland while (txq->read_ptr != READ_ONCE(txq->write_ptr) && 2181e705c121SKalle Valo !time_after(jiffies, 2182e705c121SKalle Valo now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 21836aa7de05SMark Rutland u8 write_ptr = READ_ONCE(txq->write_ptr); 2184e705c121SKalle Valo 2185e705c121SKalle Valo if (WARN_ONCE(wr_ptr != write_ptr, 2186e705c121SKalle Valo "WR pointer moved while flushing %d -> %d\n", 2187e705c121SKalle Valo wr_ptr, write_ptr)) 2188e705c121SKalle Valo return -ETIMEDOUT; 2189192185d6SJohannes Berg usleep_range(1000, 2000); 2190e705c121SKalle Valo } 2191e705c121SKalle Valo 2192bb98ecd4SSara Sharon if (txq->read_ptr != txq->write_ptr) { 2193e705c121SKalle Valo IWL_ERR(trans, 2194d6d517b7SSara Sharon "fail to flush all tx fifo queues Q %d\n", txq_idx); 2195d6d517b7SSara Sharon iwl_trans_pcie_log_scd_error(trans, txq); 2196d6d517b7SSara Sharon return -ETIMEDOUT; 2197e705c121SKalle Valo } 2198e705c121SKalle Valo 2199d6d517b7SSara Sharon IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2200d6d517b7SSara Sharon 2201d6d517b7SSara Sharon return 0; 2202d6d517b7SSara Sharon } 2203d6d517b7SSara Sharon 2204d6d517b7SSara Sharon static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2205d6d517b7SSara Sharon { 2206d6d517b7SSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2207d6d517b7SSara Sharon int cnt; 2208d6d517b7SSara Sharon int ret = 0; 2209d6d517b7SSara Sharon 2210d6d517b7SSara Sharon /* waiting for all the tx frames complete might take a while */ 2211d6d517b7SSara Sharon for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2212d6d517b7SSara Sharon 2213d6d517b7SSara Sharon if (cnt == trans_pcie->cmd_queue) 2214d6d517b7SSara Sharon continue; 2215d6d517b7SSara Sharon if (!test_bit(cnt, trans_pcie->queue_used)) 2216d6d517b7SSara Sharon continue; 2217d6d517b7SSara Sharon if (!(BIT(cnt) & txq_bm)) 2218d6d517b7SSara Sharon continue; 2219d6d517b7SSara Sharon 2220d6d517b7SSara Sharon ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 222138398efbSSara Sharon if (ret) 2222d6d517b7SSara Sharon break; 2223d6d517b7SSara Sharon } 2224e705c121SKalle Valo 2225e705c121SKalle Valo return ret; 2226e705c121SKalle Valo } 2227e705c121SKalle Valo 2228e705c121SKalle Valo static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2229e705c121SKalle Valo u32 mask, u32 value) 2230e705c121SKalle Valo { 2231e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2232e705c121SKalle Valo unsigned long flags; 2233e705c121SKalle Valo 2234e705c121SKalle Valo spin_lock_irqsave(&trans_pcie->reg_lock, flags); 2235e705c121SKalle Valo __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2236e705c121SKalle Valo spin_unlock_irqrestore(&trans_pcie->reg_lock, flags); 2237e705c121SKalle Valo } 2238e705c121SKalle Valo 2239c24c7f58SLuca Coelho static void iwl_trans_pcie_ref(struct iwl_trans *trans) 2240e705c121SKalle Valo { 2241e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2242e705c121SKalle Valo 2243e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2244e705c121SKalle Valo return; 2245e705c121SKalle Valo 2246b3ff1270SLuca Coelho pm_runtime_get(&trans_pcie->pci_dev->dev); 22475d93f3a2SLuca Coelho 22485d93f3a2SLuca Coelho #ifdef CONFIG_PM 22495d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 22505d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 22515d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2252e705c121SKalle Valo } 2253e705c121SKalle Valo 2254c24c7f58SLuca Coelho static void iwl_trans_pcie_unref(struct iwl_trans *trans) 2255e705c121SKalle Valo { 2256e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2257e705c121SKalle Valo 2258e705c121SKalle Valo if (iwlwifi_mod_params.d0i3_disable) 2259e705c121SKalle Valo return; 2260e705c121SKalle Valo 2261b3ff1270SLuca Coelho pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev); 2262b3ff1270SLuca Coelho pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev); 2263b3ff1270SLuca Coelho 22645d93f3a2SLuca Coelho #ifdef CONFIG_PM 22655d93f3a2SLuca Coelho IWL_DEBUG_RPM(trans, "runtime usage count: %d\n", 22665d93f3a2SLuca Coelho atomic_read(&trans_pcie->pci_dev->dev.power.usage_count)); 22675d93f3a2SLuca Coelho #endif /* CONFIG_PM */ 2268e705c121SKalle Valo } 2269e705c121SKalle Valo 2270e705c121SKalle Valo static const char *get_csr_string(int cmd) 2271e705c121SKalle Valo { 2272e705c121SKalle Valo #define IWL_CMD(x) case x: return #x 2273e705c121SKalle Valo switch (cmd) { 2274e705c121SKalle Valo IWL_CMD(CSR_HW_IF_CONFIG_REG); 2275e705c121SKalle Valo IWL_CMD(CSR_INT_COALESCING); 2276e705c121SKalle Valo IWL_CMD(CSR_INT); 2277e705c121SKalle Valo IWL_CMD(CSR_INT_MASK); 2278e705c121SKalle Valo IWL_CMD(CSR_FH_INT_STATUS); 2279e705c121SKalle Valo IWL_CMD(CSR_GPIO_IN); 2280e705c121SKalle Valo IWL_CMD(CSR_RESET); 2281e705c121SKalle Valo IWL_CMD(CSR_GP_CNTRL); 2282e705c121SKalle Valo IWL_CMD(CSR_HW_REV); 2283e705c121SKalle Valo IWL_CMD(CSR_EEPROM_REG); 2284e705c121SKalle Valo IWL_CMD(CSR_EEPROM_GP); 2285e705c121SKalle Valo IWL_CMD(CSR_OTP_GP_REG); 2286e705c121SKalle Valo IWL_CMD(CSR_GIO_REG); 2287e705c121SKalle Valo IWL_CMD(CSR_GP_UCODE_REG); 2288e705c121SKalle Valo IWL_CMD(CSR_GP_DRIVER_REG); 2289e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP1); 2290e705c121SKalle Valo IWL_CMD(CSR_UCODE_DRV_GP2); 2291e705c121SKalle Valo IWL_CMD(CSR_LED_REG); 2292e705c121SKalle Valo IWL_CMD(CSR_DRAM_INT_TBL_REG); 2293e705c121SKalle Valo IWL_CMD(CSR_GIO_CHICKEN_BITS); 2294e705c121SKalle Valo IWL_CMD(CSR_ANA_PLL_CFG); 2295e705c121SKalle Valo IWL_CMD(CSR_HW_REV_WA_REG); 2296e705c121SKalle Valo IWL_CMD(CSR_MONITOR_STATUS_REG); 2297e705c121SKalle Valo IWL_CMD(CSR_DBG_HPET_MEM_REG); 2298e705c121SKalle Valo default: 2299e705c121SKalle Valo return "UNKNOWN"; 2300e705c121SKalle Valo } 2301e705c121SKalle Valo #undef IWL_CMD 2302e705c121SKalle Valo } 2303e705c121SKalle Valo 2304e705c121SKalle Valo void iwl_pcie_dump_csr(struct iwl_trans *trans) 2305e705c121SKalle Valo { 2306e705c121SKalle Valo int i; 2307e705c121SKalle Valo static const u32 csr_tbl[] = { 2308e705c121SKalle Valo CSR_HW_IF_CONFIG_REG, 2309e705c121SKalle Valo CSR_INT_COALESCING, 2310e705c121SKalle Valo CSR_INT, 2311e705c121SKalle Valo CSR_INT_MASK, 2312e705c121SKalle Valo CSR_FH_INT_STATUS, 2313e705c121SKalle Valo CSR_GPIO_IN, 2314e705c121SKalle Valo CSR_RESET, 2315e705c121SKalle Valo CSR_GP_CNTRL, 2316e705c121SKalle Valo CSR_HW_REV, 2317e705c121SKalle Valo CSR_EEPROM_REG, 2318e705c121SKalle Valo CSR_EEPROM_GP, 2319e705c121SKalle Valo CSR_OTP_GP_REG, 2320e705c121SKalle Valo CSR_GIO_REG, 2321e705c121SKalle Valo CSR_GP_UCODE_REG, 2322e705c121SKalle Valo CSR_GP_DRIVER_REG, 2323e705c121SKalle Valo CSR_UCODE_DRV_GP1, 2324e705c121SKalle Valo CSR_UCODE_DRV_GP2, 2325e705c121SKalle Valo CSR_LED_REG, 2326e705c121SKalle Valo CSR_DRAM_INT_TBL_REG, 2327e705c121SKalle Valo CSR_GIO_CHICKEN_BITS, 2328e705c121SKalle Valo CSR_ANA_PLL_CFG, 2329e705c121SKalle Valo CSR_MONITOR_STATUS_REG, 2330e705c121SKalle Valo CSR_HW_REV_WA_REG, 2331e705c121SKalle Valo CSR_DBG_HPET_MEM_REG 2332e705c121SKalle Valo }; 2333e705c121SKalle Valo IWL_ERR(trans, "CSR values:\n"); 2334e705c121SKalle Valo IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2335e705c121SKalle Valo "CSR_INT_PERIODIC_REG)\n"); 2336e705c121SKalle Valo for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2337e705c121SKalle Valo IWL_ERR(trans, " %25s: 0X%08x\n", 2338e705c121SKalle Valo get_csr_string(csr_tbl[i]), 2339e705c121SKalle Valo iwl_read32(trans, csr_tbl[i])); 2340e705c121SKalle Valo } 2341e705c121SKalle Valo } 2342e705c121SKalle Valo 2343e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUGFS 2344e705c121SKalle Valo /* create and remove of files */ 2345e705c121SKalle Valo #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2346e705c121SKalle Valo if (!debugfs_create_file(#name, mode, parent, trans, \ 2347e705c121SKalle Valo &iwl_dbgfs_##name##_ops)) \ 2348e705c121SKalle Valo goto err; \ 2349e705c121SKalle Valo } while (0) 2350e705c121SKalle Valo 2351e705c121SKalle Valo /* file operation */ 2352e705c121SKalle Valo #define DEBUGFS_READ_FILE_OPS(name) \ 2353e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2354e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2355e705c121SKalle Valo .open = simple_open, \ 2356e705c121SKalle Valo .llseek = generic_file_llseek, \ 2357e705c121SKalle Valo }; 2358e705c121SKalle Valo 2359e705c121SKalle Valo #define DEBUGFS_WRITE_FILE_OPS(name) \ 2360e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2361e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2362e705c121SKalle Valo .open = simple_open, \ 2363e705c121SKalle Valo .llseek = generic_file_llseek, \ 2364e705c121SKalle Valo }; 2365e705c121SKalle Valo 2366e705c121SKalle Valo #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2367e705c121SKalle Valo static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2368e705c121SKalle Valo .write = iwl_dbgfs_##name##_write, \ 2369e705c121SKalle Valo .read = iwl_dbgfs_##name##_read, \ 2370e705c121SKalle Valo .open = simple_open, \ 2371e705c121SKalle Valo .llseek = generic_file_llseek, \ 2372e705c121SKalle Valo }; 2373e705c121SKalle Valo 2374e705c121SKalle Valo static ssize_t iwl_dbgfs_tx_queue_read(struct file *file, 2375e705c121SKalle Valo char __user *user_buf, 2376e705c121SKalle Valo size_t count, loff_t *ppos) 2377e705c121SKalle Valo { 2378e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2379e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2380e705c121SKalle Valo struct iwl_txq *txq; 2381e705c121SKalle Valo char *buf; 2382e705c121SKalle Valo int pos = 0; 2383e705c121SKalle Valo int cnt; 2384e705c121SKalle Valo int ret; 2385e705c121SKalle Valo size_t bufsz; 2386e705c121SKalle Valo 2387e705c121SKalle Valo bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues; 2388e705c121SKalle Valo 2389b2a3b1c1SSara Sharon if (!trans_pcie->txq_memory) 2390e705c121SKalle Valo return -EAGAIN; 2391e705c121SKalle Valo 2392e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2393e705c121SKalle Valo if (!buf) 2394e705c121SKalle Valo return -ENOMEM; 2395e705c121SKalle Valo 2396e705c121SKalle Valo for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { 2397b2a3b1c1SSara Sharon txq = trans_pcie->txq[cnt]; 2398e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2399e705c121SKalle Valo "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n", 2400bb98ecd4SSara Sharon cnt, txq->read_ptr, txq->write_ptr, 2401e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_used), 2402e705c121SKalle Valo !!test_bit(cnt, trans_pcie->queue_stopped), 2403e705c121SKalle Valo txq->need_update, txq->frozen, 2404e705c121SKalle Valo (cnt == trans_pcie->cmd_queue ? " HCMD" : "")); 2405e705c121SKalle Valo } 2406e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2407e705c121SKalle Valo kfree(buf); 2408e705c121SKalle Valo return ret; 2409e705c121SKalle Valo } 2410e705c121SKalle Valo 2411e705c121SKalle Valo static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2412e705c121SKalle Valo char __user *user_buf, 2413e705c121SKalle Valo size_t count, loff_t *ppos) 2414e705c121SKalle Valo { 2415e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2416e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 241778485054SSara Sharon char *buf; 241878485054SSara Sharon int pos = 0, i, ret; 241978485054SSara Sharon size_t bufsz = sizeof(buf); 2420e705c121SKalle Valo 242178485054SSara Sharon bufsz = sizeof(char) * 121 * trans->num_rx_queues; 242278485054SSara Sharon 242378485054SSara Sharon if (!trans_pcie->rxq) 242478485054SSara Sharon return -EAGAIN; 242578485054SSara Sharon 242678485054SSara Sharon buf = kzalloc(bufsz, GFP_KERNEL); 242778485054SSara Sharon if (!buf) 242878485054SSara Sharon return -ENOMEM; 242978485054SSara Sharon 243078485054SSara Sharon for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 243178485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 243278485054SSara Sharon 243378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 243478485054SSara Sharon i); 243578485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2436e705c121SKalle Valo rxq->read); 243778485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2438e705c121SKalle Valo rxq->write); 243978485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2440e705c121SKalle Valo rxq->write_actual); 244178485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2442e705c121SKalle Valo rxq->need_update); 244378485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2444e705c121SKalle Valo rxq->free_count); 2445e705c121SKalle Valo if (rxq->rb_stts) { 244678485054SSara Sharon pos += scnprintf(buf + pos, bufsz - pos, 244778485054SSara Sharon "\tclosed_rb_num: %u\n", 244878485054SSara Sharon le16_to_cpu(rxq->rb_stts->closed_rb_num) & 244978485054SSara Sharon 0x0FFF); 2450e705c121SKalle Valo } else { 2451e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 245278485054SSara Sharon "\tclosed_rb_num: Not Allocated\n"); 2453e705c121SKalle Valo } 245478485054SSara Sharon } 245578485054SSara Sharon ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 245678485054SSara Sharon kfree(buf); 245778485054SSara Sharon 245878485054SSara Sharon return ret; 2459e705c121SKalle Valo } 2460e705c121SKalle Valo 2461e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2462e705c121SKalle Valo char __user *user_buf, 2463e705c121SKalle Valo size_t count, loff_t *ppos) 2464e705c121SKalle Valo { 2465e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2466e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2467e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2468e705c121SKalle Valo 2469e705c121SKalle Valo int pos = 0; 2470e705c121SKalle Valo char *buf; 2471e705c121SKalle Valo int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2472e705c121SKalle Valo ssize_t ret; 2473e705c121SKalle Valo 2474e705c121SKalle Valo buf = kzalloc(bufsz, GFP_KERNEL); 2475e705c121SKalle Valo if (!buf) 2476e705c121SKalle Valo return -ENOMEM; 2477e705c121SKalle Valo 2478e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2479e705c121SKalle Valo "Interrupt Statistics Report:\n"); 2480e705c121SKalle Valo 2481e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2482e705c121SKalle Valo isr_stats->hw); 2483e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2484e705c121SKalle Valo isr_stats->sw); 2485e705c121SKalle Valo if (isr_stats->sw || isr_stats->hw) { 2486e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2487e705c121SKalle Valo "\tLast Restarting Code: 0x%X\n", 2488e705c121SKalle Valo isr_stats->err_code); 2489e705c121SKalle Valo } 2490e705c121SKalle Valo #ifdef CONFIG_IWLWIFI_DEBUG 2491e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2492e705c121SKalle Valo isr_stats->sch); 2493e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2494e705c121SKalle Valo isr_stats->alive); 2495e705c121SKalle Valo #endif 2496e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2497e705c121SKalle Valo "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2498e705c121SKalle Valo 2499e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2500e705c121SKalle Valo isr_stats->ctkill); 2501e705c121SKalle Valo 2502e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2503e705c121SKalle Valo isr_stats->wakeup); 2504e705c121SKalle Valo 2505e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, 2506e705c121SKalle Valo "Rx command responses:\t\t %u\n", isr_stats->rx); 2507e705c121SKalle Valo 2508e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2509e705c121SKalle Valo isr_stats->tx); 2510e705c121SKalle Valo 2511e705c121SKalle Valo pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2512e705c121SKalle Valo isr_stats->unhandled); 2513e705c121SKalle Valo 2514e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2515e705c121SKalle Valo kfree(buf); 2516e705c121SKalle Valo return ret; 2517e705c121SKalle Valo } 2518e705c121SKalle Valo 2519e705c121SKalle Valo static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2520e705c121SKalle Valo const char __user *user_buf, 2521e705c121SKalle Valo size_t count, loff_t *ppos) 2522e705c121SKalle Valo { 2523e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2524e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2525e705c121SKalle Valo struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2526e705c121SKalle Valo u32 reset_flag; 2527078f1131SJohannes Berg int ret; 2528e705c121SKalle Valo 2529078f1131SJohannes Berg ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2530078f1131SJohannes Berg if (ret) 2531078f1131SJohannes Berg return ret; 2532e705c121SKalle Valo if (reset_flag == 0) 2533e705c121SKalle Valo memset(isr_stats, 0, sizeof(*isr_stats)); 2534e705c121SKalle Valo 2535e705c121SKalle Valo return count; 2536e705c121SKalle Valo } 2537e705c121SKalle Valo 2538e705c121SKalle Valo static ssize_t iwl_dbgfs_csr_write(struct file *file, 2539e705c121SKalle Valo const char __user *user_buf, 2540e705c121SKalle Valo size_t count, loff_t *ppos) 2541e705c121SKalle Valo { 2542e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2543e705c121SKalle Valo 2544e705c121SKalle Valo iwl_pcie_dump_csr(trans); 2545e705c121SKalle Valo 2546e705c121SKalle Valo return count; 2547e705c121SKalle Valo } 2548e705c121SKalle Valo 2549e705c121SKalle Valo static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2550e705c121SKalle Valo char __user *user_buf, 2551e705c121SKalle Valo size_t count, loff_t *ppos) 2552e705c121SKalle Valo { 2553e705c121SKalle Valo struct iwl_trans *trans = file->private_data; 2554e705c121SKalle Valo char *buf = NULL; 2555e705c121SKalle Valo ssize_t ret; 2556e705c121SKalle Valo 2557e705c121SKalle Valo ret = iwl_dump_fh(trans, &buf); 2558e705c121SKalle Valo if (ret < 0) 2559e705c121SKalle Valo return ret; 2560e705c121SKalle Valo if (!buf) 2561e705c121SKalle Valo return -EINVAL; 2562e705c121SKalle Valo ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2563e705c121SKalle Valo kfree(buf); 2564e705c121SKalle Valo return ret; 2565e705c121SKalle Valo } 2566e705c121SKalle Valo 2567fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2568fa4de7f7SJohannes Berg char __user *user_buf, 2569fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2570fa4de7f7SJohannes Berg { 2571fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2572fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2573fa4de7f7SJohannes Berg char buf[100]; 2574fa4de7f7SJohannes Berg int pos; 2575fa4de7f7SJohannes Berg 2576fa4de7f7SJohannes Berg pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2577fa4de7f7SJohannes Berg trans_pcie->debug_rfkill, 2578fa4de7f7SJohannes Berg !(iwl_read32(trans, CSR_GP_CNTRL) & 2579fa4de7f7SJohannes Berg CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2580fa4de7f7SJohannes Berg 2581fa4de7f7SJohannes Berg return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2582fa4de7f7SJohannes Berg } 2583fa4de7f7SJohannes Berg 2584fa4de7f7SJohannes Berg static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2585fa4de7f7SJohannes Berg const char __user *user_buf, 2586fa4de7f7SJohannes Berg size_t count, loff_t *ppos) 2587fa4de7f7SJohannes Berg { 2588fa4de7f7SJohannes Berg struct iwl_trans *trans = file->private_data; 2589fa4de7f7SJohannes Berg struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2590fa4de7f7SJohannes Berg bool old = trans_pcie->debug_rfkill; 2591fa4de7f7SJohannes Berg int ret; 2592fa4de7f7SJohannes Berg 2593fa4de7f7SJohannes Berg ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill); 2594fa4de7f7SJohannes Berg if (ret) 2595fa4de7f7SJohannes Berg return ret; 2596fa4de7f7SJohannes Berg if (old == trans_pcie->debug_rfkill) 2597fa4de7f7SJohannes Berg return count; 2598fa4de7f7SJohannes Berg IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2599fa4de7f7SJohannes Berg old, trans_pcie->debug_rfkill); 2600fa4de7f7SJohannes Berg iwl_pcie_handle_rfkill_irq(trans); 2601fa4de7f7SJohannes Berg 2602fa4de7f7SJohannes Berg return count; 2603fa4de7f7SJohannes Berg } 2604fa4de7f7SJohannes Berg 2605e705c121SKalle Valo DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 2606e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(fh_reg); 2607e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(rx_queue); 2608e705c121SKalle Valo DEBUGFS_READ_FILE_OPS(tx_queue); 2609e705c121SKalle Valo DEBUGFS_WRITE_FILE_OPS(csr); 2610fa4de7f7SJohannes Berg DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 2611e705c121SKalle Valo 2612f8a1edb7SJohannes Berg /* Create the debugfs files and directories */ 2613f8a1edb7SJohannes Berg int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 2614e705c121SKalle Valo { 2615f8a1edb7SJohannes Berg struct dentry *dir = trans->dbgfs_dir; 2616f8a1edb7SJohannes Berg 2617e705c121SKalle Valo DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR); 2618e705c121SKalle Valo DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR); 2619e705c121SKalle Valo DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR); 2620e705c121SKalle Valo DEBUGFS_ADD_FILE(csr, dir, S_IWUSR); 2621e705c121SKalle Valo DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR); 2622fa4de7f7SJohannes Berg DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR); 2623e705c121SKalle Valo return 0; 2624e705c121SKalle Valo 2625e705c121SKalle Valo err: 2626e705c121SKalle Valo IWL_ERR(trans, "failed to create the trans debugfs entry\n"); 2627e705c121SKalle Valo return -ENOMEM; 2628e705c121SKalle Valo } 2629e705c121SKalle Valo #endif /*CONFIG_IWLWIFI_DEBUGFS */ 2630e705c121SKalle Valo 26316983ba69SSara Sharon static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 2632e705c121SKalle Valo { 26333cd1980bSSara Sharon struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2634e705c121SKalle Valo u32 cmdlen = 0; 2635e705c121SKalle Valo int i; 2636e705c121SKalle Valo 26373cd1980bSSara Sharon for (i = 0; i < trans_pcie->max_tbs; i++) 26386983ba69SSara Sharon cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i); 2639e705c121SKalle Valo 2640e705c121SKalle Valo return cmdlen; 2641e705c121SKalle Valo } 2642e705c121SKalle Valo 2643e705c121SKalle Valo static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 2644e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2645e705c121SKalle Valo int allocated_rb_nums) 2646e705c121SKalle Valo { 2647e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2648e705c121SKalle Valo int max_len = PAGE_SIZE << trans_pcie->rx_page_order; 264978485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 265078485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2651e705c121SKalle Valo u32 i, r, j, rb_len = 0; 2652e705c121SKalle Valo 2653e705c121SKalle Valo spin_lock(&rxq->lock); 2654e705c121SKalle Valo 26556aa7de05SMark Rutland r = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF; 2656e705c121SKalle Valo 2657e705c121SKalle Valo for (i = rxq->read, j = 0; 2658e705c121SKalle Valo i != r && j < allocated_rb_nums; 2659e705c121SKalle Valo i = (i + 1) & RX_QUEUE_MASK, j++) { 2660e705c121SKalle Valo struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 2661e705c121SKalle Valo struct iwl_fw_error_dump_rb *rb; 2662e705c121SKalle Valo 2663e705c121SKalle Valo dma_unmap_page(trans->dev, rxb->page_dma, max_len, 2664e705c121SKalle Valo DMA_FROM_DEVICE); 2665e705c121SKalle Valo 2666e705c121SKalle Valo rb_len += sizeof(**data) + sizeof(*rb) + max_len; 2667e705c121SKalle Valo 2668e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 2669e705c121SKalle Valo (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 2670e705c121SKalle Valo rb = (void *)(*data)->data; 2671e705c121SKalle Valo rb->index = cpu_to_le32(i); 2672e705c121SKalle Valo memcpy(rb->data, page_address(rxb->page), max_len); 2673e705c121SKalle Valo /* remap the page for the free benefit */ 2674e705c121SKalle Valo rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0, 2675e705c121SKalle Valo max_len, 2676e705c121SKalle Valo DMA_FROM_DEVICE); 2677e705c121SKalle Valo 2678e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2679e705c121SKalle Valo } 2680e705c121SKalle Valo 2681e705c121SKalle Valo spin_unlock(&rxq->lock); 2682e705c121SKalle Valo 2683e705c121SKalle Valo return rb_len; 2684e705c121SKalle Valo } 2685e705c121SKalle Valo #define IWL_CSR_TO_DUMP (0x250) 2686e705c121SKalle Valo 2687e705c121SKalle Valo static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 2688e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2689e705c121SKalle Valo { 2690e705c121SKalle Valo u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 2691e705c121SKalle Valo __le32 *val; 2692e705c121SKalle Valo int i; 2693e705c121SKalle Valo 2694e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 2695e705c121SKalle Valo (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 2696e705c121SKalle Valo val = (void *)(*data)->data; 2697e705c121SKalle Valo 2698e705c121SKalle Valo for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 2699e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2700e705c121SKalle Valo 2701e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2702e705c121SKalle Valo 2703e705c121SKalle Valo return csr_len; 2704e705c121SKalle Valo } 2705e705c121SKalle Valo 2706e705c121SKalle Valo static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 2707e705c121SKalle Valo struct iwl_fw_error_dump_data **data) 2708e705c121SKalle Valo { 2709e705c121SKalle Valo u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 2710e705c121SKalle Valo unsigned long flags; 2711e705c121SKalle Valo __le32 *val; 2712e705c121SKalle Valo int i; 2713e705c121SKalle Valo 271423ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2715e705c121SKalle Valo return 0; 2716e705c121SKalle Valo 2717e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 2718e705c121SKalle Valo (*data)->len = cpu_to_le32(fh_regs_len); 2719e705c121SKalle Valo val = (void *)(*data)->data; 2720e705c121SKalle Valo 2721723b45e2SLiad Kaufman if (!trans->cfg->gen2) 2722723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 2723723b45e2SLiad Kaufman i += sizeof(u32)) 2724e705c121SKalle Valo *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 2725723b45e2SLiad Kaufman else 2726723b45e2SLiad Kaufman for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2; 2727723b45e2SLiad Kaufman i += sizeof(u32)) 2728723b45e2SLiad Kaufman *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 2729723b45e2SLiad Kaufman i)); 2730e705c121SKalle Valo 2731e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2732e705c121SKalle Valo 2733e705c121SKalle Valo *data = iwl_fw_error_next_data(*data); 2734e705c121SKalle Valo 2735e705c121SKalle Valo return sizeof(**data) + fh_regs_len; 2736e705c121SKalle Valo } 2737e705c121SKalle Valo 2738e705c121SKalle Valo static u32 2739e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 2740e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data, 2741e705c121SKalle Valo u32 monitor_len) 2742e705c121SKalle Valo { 2743e705c121SKalle Valo u32 buf_size_in_dwords = (monitor_len >> 2); 2744e705c121SKalle Valo u32 *buffer = (u32 *)fw_mon_data->data; 2745e705c121SKalle Valo unsigned long flags; 2746e705c121SKalle Valo u32 i; 2747e705c121SKalle Valo 274823ba9340SEmmanuel Grumbach if (!iwl_trans_grab_nic_access(trans, &flags)) 2749e705c121SKalle Valo return 0; 2750e705c121SKalle Valo 275114ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 2752e705c121SKalle Valo for (i = 0; i < buf_size_in_dwords; i++) 275314ef1b43SGolan Ben-Ami buffer[i] = iwl_read_prph_no_grab(trans, 275414ef1b43SGolan Ben-Ami MON_DMARB_RD_DATA_ADDR); 275514ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 2756e705c121SKalle Valo 2757e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 2758e705c121SKalle Valo 2759e705c121SKalle Valo return monitor_len; 2760e705c121SKalle Valo } 2761e705c121SKalle Valo 2762e705c121SKalle Valo static u32 2763e705c121SKalle Valo iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 2764e705c121SKalle Valo struct iwl_fw_error_dump_data **data, 2765e705c121SKalle Valo u32 monitor_len) 2766e705c121SKalle Valo { 2767e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2768e705c121SKalle Valo u32 len = 0; 2769e705c121SKalle Valo 2770e705c121SKalle Valo if ((trans_pcie->fw_mon_page && 2771e705c121SKalle Valo trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) || 2772e705c121SKalle Valo trans->dbg_dest_tlv) { 2773e705c121SKalle Valo struct iwl_fw_error_dump_fw_mon *fw_mon_data; 2774e705c121SKalle Valo u32 base, write_ptr, wrap_cnt; 2775e705c121SKalle Valo 2776e705c121SKalle Valo /* If there was a dest TLV - use the values from there */ 2777e705c121SKalle Valo if (trans->dbg_dest_tlv) { 2778e705c121SKalle Valo write_ptr = 2779e705c121SKalle Valo le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg); 2780e705c121SKalle Valo wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count); 2781e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2782e705c121SKalle Valo } else { 2783e705c121SKalle Valo base = MON_BUFF_BASE_ADDR; 2784e705c121SKalle Valo write_ptr = MON_BUFF_WRPTR; 2785e705c121SKalle Valo wrap_cnt = MON_BUFF_CYCLE_CNT; 2786e705c121SKalle Valo } 2787e705c121SKalle Valo 2788e705c121SKalle Valo (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 2789e705c121SKalle Valo fw_mon_data = (void *)(*data)->data; 2790e705c121SKalle Valo fw_mon_data->fw_mon_wr_ptr = 2791e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, write_ptr)); 2792e705c121SKalle Valo fw_mon_data->fw_mon_cycle_cnt = 2793e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 2794e705c121SKalle Valo fw_mon_data->fw_mon_base_ptr = 2795e705c121SKalle Valo cpu_to_le32(iwl_read_prph(trans, base)); 2796e705c121SKalle Valo 2797e705c121SKalle Valo len += sizeof(**data) + sizeof(*fw_mon_data); 2798e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2799e705c121SKalle Valo /* 2800e705c121SKalle Valo * The firmware is now asserted, it won't write anything 2801e705c121SKalle Valo * to the buffer. CPU can take ownership to fetch the 2802e705c121SKalle Valo * data. The buffer will be handed back to the device 2803e705c121SKalle Valo * before the firmware will be restarted. 2804e705c121SKalle Valo */ 2805e705c121SKalle Valo dma_sync_single_for_cpu(trans->dev, 2806e705c121SKalle Valo trans_pcie->fw_mon_phys, 2807e705c121SKalle Valo trans_pcie->fw_mon_size, 2808e705c121SKalle Valo DMA_FROM_DEVICE); 2809e705c121SKalle Valo memcpy(fw_mon_data->data, 2810e705c121SKalle Valo page_address(trans_pcie->fw_mon_page), 2811e705c121SKalle Valo trans_pcie->fw_mon_size); 2812e705c121SKalle Valo 2813e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2814e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) { 2815e705c121SKalle Valo /* 2816e705c121SKalle Valo * Update pointers to reflect actual values after 2817e705c121SKalle Valo * shifting 2818e705c121SKalle Valo */ 2819e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2820e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2821e705c121SKalle Valo iwl_trans_read_mem(trans, base, fw_mon_data->data, 2822e705c121SKalle Valo monitor_len / sizeof(u32)); 2823e705c121SKalle Valo } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) { 2824e705c121SKalle Valo monitor_len = 2825e705c121SKalle Valo iwl_trans_pci_dump_marbh_monitor(trans, 2826e705c121SKalle Valo fw_mon_data, 2827e705c121SKalle Valo monitor_len); 2828e705c121SKalle Valo } else { 2829e705c121SKalle Valo /* Didn't match anything - output no monitor data */ 2830e705c121SKalle Valo monitor_len = 0; 2831e705c121SKalle Valo } 2832e705c121SKalle Valo 2833e705c121SKalle Valo len += monitor_len; 2834e705c121SKalle Valo (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 2835e705c121SKalle Valo } 2836e705c121SKalle Valo 2837e705c121SKalle Valo return len; 2838e705c121SKalle Valo } 2839e705c121SKalle Valo 2840e705c121SKalle Valo static struct iwl_trans_dump_data 2841e705c121SKalle Valo *iwl_trans_pcie_dump_data(struct iwl_trans *trans, 2842a80c7a69SEmmanuel Grumbach const struct iwl_fw_dbg_trigger_tlv *trigger) 2843e705c121SKalle Valo { 2844e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2845e705c121SKalle Valo struct iwl_fw_error_dump_data *data; 2846b2a3b1c1SSara Sharon struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue]; 2847e705c121SKalle Valo struct iwl_fw_error_dump_txcmd *txcmd; 2848e705c121SKalle Valo struct iwl_trans_dump_data *dump_data; 2849e705c121SKalle Valo u32 len, num_rbs; 2850e705c121SKalle Valo u32 monitor_len; 2851e705c121SKalle Valo int i, ptr; 285296a6497bSSara Sharon bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 285396a6497bSSara Sharon !trans->cfg->mq_rx_supported; 2854e705c121SKalle Valo 2855e705c121SKalle Valo /* transport dump header */ 2856e705c121SKalle Valo len = sizeof(*dump_data); 2857e705c121SKalle Valo 2858e705c121SKalle Valo /* host commands */ 2859e705c121SKalle Valo len += sizeof(*data) + 2860bb98ecd4SSara Sharon cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE); 2861e705c121SKalle Valo 2862e705c121SKalle Valo /* FW monitor */ 2863e705c121SKalle Valo if (trans_pcie->fw_mon_page) { 2864e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2865e705c121SKalle Valo trans_pcie->fw_mon_size; 2866e705c121SKalle Valo monitor_len = trans_pcie->fw_mon_size; 2867e705c121SKalle Valo } else if (trans->dbg_dest_tlv) { 2868e705c121SKalle Valo u32 base, end; 2869e705c121SKalle Valo 2870e705c121SKalle Valo base = le32_to_cpu(trans->dbg_dest_tlv->base_reg); 2871e705c121SKalle Valo end = le32_to_cpu(trans->dbg_dest_tlv->end_reg); 2872e705c121SKalle Valo 2873e705c121SKalle Valo base = iwl_read_prph(trans, base) << 2874e705c121SKalle Valo trans->dbg_dest_tlv->base_shift; 2875e705c121SKalle Valo end = iwl_read_prph(trans, end) << 2876e705c121SKalle Valo trans->dbg_dest_tlv->end_shift; 2877e705c121SKalle Valo 2878e705c121SKalle Valo /* Make "end" point to the actual end */ 28796e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 || 2880e705c121SKalle Valo trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) 2881e705c121SKalle Valo end += (1 << trans->dbg_dest_tlv->end_shift); 2882e705c121SKalle Valo monitor_len = end - base; 2883e705c121SKalle Valo len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) + 2884e705c121SKalle Valo monitor_len; 2885e705c121SKalle Valo } else { 2886e705c121SKalle Valo monitor_len = 0; 2887e705c121SKalle Valo } 2888e705c121SKalle Valo 2889e705c121SKalle Valo if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) { 2890e705c121SKalle Valo dump_data = vzalloc(len); 2891e705c121SKalle Valo if (!dump_data) 2892e705c121SKalle Valo return NULL; 2893e705c121SKalle Valo 2894e705c121SKalle Valo data = (void *)dump_data->data; 2895e705c121SKalle Valo len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2896e705c121SKalle Valo dump_data->len = len; 2897e705c121SKalle Valo 2898e705c121SKalle Valo return dump_data; 2899e705c121SKalle Valo } 2900e705c121SKalle Valo 2901e705c121SKalle Valo /* CSR registers */ 2902e705c121SKalle Valo len += sizeof(*data) + IWL_CSR_TO_DUMP; 2903e705c121SKalle Valo 2904e705c121SKalle Valo /* FH registers */ 2905723b45e2SLiad Kaufman if (trans->cfg->gen2) 2906723b45e2SLiad Kaufman len += sizeof(*data) + 2907723b45e2SLiad Kaufman (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2); 2908723b45e2SLiad Kaufman else 2909723b45e2SLiad Kaufman len += sizeof(*data) + 2910723b45e2SLiad Kaufman (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND); 2911e705c121SKalle Valo 2912e705c121SKalle Valo if (dump_rbs) { 291378485054SSara Sharon /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 291478485054SSara Sharon struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 2915e705c121SKalle Valo /* RBs */ 29166aa7de05SMark Rutland num_rbs = le16_to_cpu(READ_ONCE(rxq->rb_stts->closed_rb_num)) 2917e705c121SKalle Valo & 0x0FFF; 291878485054SSara Sharon num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 2919e705c121SKalle Valo len += num_rbs * (sizeof(*data) + 2920e705c121SKalle Valo sizeof(struct iwl_fw_error_dump_rb) + 2921e705c121SKalle Valo (PAGE_SIZE << trans_pcie->rx_page_order)); 2922e705c121SKalle Valo } 2923e705c121SKalle Valo 29245538409bSLiad Kaufman /* Paged memory for gen2 HW */ 29255538409bSLiad Kaufman if (trans->cfg->gen2) 29265538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) 29275538409bSLiad Kaufman len += sizeof(*data) + 29285538409bSLiad Kaufman sizeof(struct iwl_fw_error_dump_paging) + 29295538409bSLiad Kaufman trans_pcie->init_dram.paging[i].size; 29305538409bSLiad Kaufman 2931e705c121SKalle Valo dump_data = vzalloc(len); 2932e705c121SKalle Valo if (!dump_data) 2933e705c121SKalle Valo return NULL; 2934e705c121SKalle Valo 2935e705c121SKalle Valo len = 0; 2936e705c121SKalle Valo data = (void *)dump_data->data; 2937e705c121SKalle Valo data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 2938e705c121SKalle Valo txcmd = (void *)data->data; 2939e705c121SKalle Valo spin_lock_bh(&cmdq->lock); 2940bb98ecd4SSara Sharon ptr = cmdq->write_ptr; 2941bb98ecd4SSara Sharon for (i = 0; i < cmdq->n_window; i++) { 29424ecab561SEmmanuel Grumbach u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr); 2943e705c121SKalle Valo u32 caplen, cmdlen; 2944e705c121SKalle Valo 29456983ba69SSara Sharon cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds + 29466983ba69SSara Sharon trans_pcie->tfd_size * ptr); 2947e705c121SKalle Valo caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 2948e705c121SKalle Valo 2949e705c121SKalle Valo if (cmdlen) { 2950e705c121SKalle Valo len += sizeof(*txcmd) + caplen; 2951e705c121SKalle Valo txcmd->cmdlen = cpu_to_le32(cmdlen); 2952e705c121SKalle Valo txcmd->caplen = cpu_to_le32(caplen); 2953e705c121SKalle Valo memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen); 2954e705c121SKalle Valo txcmd = (void *)((u8 *)txcmd->data + caplen); 2955e705c121SKalle Valo } 2956e705c121SKalle Valo 2957e705c121SKalle Valo ptr = iwl_queue_dec_wrap(ptr); 2958e705c121SKalle Valo } 2959e705c121SKalle Valo spin_unlock_bh(&cmdq->lock); 2960e705c121SKalle Valo 2961e705c121SKalle Valo data->len = cpu_to_le32(len); 2962e705c121SKalle Valo len += sizeof(*data); 2963e705c121SKalle Valo data = iwl_fw_error_next_data(data); 2964e705c121SKalle Valo 2965e705c121SKalle Valo len += iwl_trans_pcie_dump_csr(trans, &data); 2966e705c121SKalle Valo len += iwl_trans_pcie_fh_regs_dump(trans, &data); 2967e705c121SKalle Valo if (dump_rbs) 2968e705c121SKalle Valo len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 2969e705c121SKalle Valo 29705538409bSLiad Kaufman /* Paged memory for gen2 HW */ 29715538409bSLiad Kaufman if (trans->cfg->gen2) { 29725538409bSLiad Kaufman for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) { 29735538409bSLiad Kaufman struct iwl_fw_error_dump_paging *paging; 29745538409bSLiad Kaufman dma_addr_t addr = 29755538409bSLiad Kaufman trans_pcie->init_dram.paging[i].physical; 29765538409bSLiad Kaufman u32 page_len = trans_pcie->init_dram.paging[i].size; 29775538409bSLiad Kaufman 29785538409bSLiad Kaufman data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 29795538409bSLiad Kaufman data->len = cpu_to_le32(sizeof(*paging) + page_len); 29805538409bSLiad Kaufman paging = (void *)data->data; 29815538409bSLiad Kaufman paging->index = cpu_to_le32(i); 29825538409bSLiad Kaufman dma_sync_single_for_cpu(trans->dev, addr, page_len, 29835538409bSLiad Kaufman DMA_BIDIRECTIONAL); 29845538409bSLiad Kaufman memcpy(paging->data, 29855538409bSLiad Kaufman trans_pcie->init_dram.paging[i].block, page_len); 29865538409bSLiad Kaufman data = iwl_fw_error_next_data(data); 29875538409bSLiad Kaufman 29885538409bSLiad Kaufman len += sizeof(*data) + sizeof(*paging) + page_len; 29895538409bSLiad Kaufman } 29905538409bSLiad Kaufman } 29915538409bSLiad Kaufman 2992e705c121SKalle Valo len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 2993e705c121SKalle Valo 2994e705c121SKalle Valo dump_data->len = len; 2995e705c121SKalle Valo 2996e705c121SKalle Valo return dump_data; 2997e705c121SKalle Valo } 2998e705c121SKalle Valo 29994cbb8e50SLuciano Coelho #ifdef CONFIG_PM_SLEEP 30004cbb8e50SLuciano Coelho static int iwl_trans_pcie_suspend(struct iwl_trans *trans) 30014cbb8e50SLuciano Coelho { 3002e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3003e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 30044cbb8e50SLuciano Coelho return iwl_pci_fw_enter_d0i3(trans); 30054cbb8e50SLuciano Coelho 30064cbb8e50SLuciano Coelho return 0; 30074cbb8e50SLuciano Coelho } 30084cbb8e50SLuciano Coelho 30094cbb8e50SLuciano Coelho static void iwl_trans_pcie_resume(struct iwl_trans *trans) 30104cbb8e50SLuciano Coelho { 3011e4c49c49SLuca Coelho if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 && 3012e4c49c49SLuca Coelho (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3)) 30134cbb8e50SLuciano Coelho iwl_pci_fw_exit_d0i3(trans); 30144cbb8e50SLuciano Coelho } 30154cbb8e50SLuciano Coelho #endif /* CONFIG_PM_SLEEP */ 30164cbb8e50SLuciano Coelho 3017623e7766SSara Sharon #define IWL_TRANS_COMMON_OPS \ 3018623e7766SSara Sharon .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3019623e7766SSara Sharon .write8 = iwl_trans_pcie_write8, \ 3020623e7766SSara Sharon .write32 = iwl_trans_pcie_write32, \ 3021623e7766SSara Sharon .read32 = iwl_trans_pcie_read32, \ 3022623e7766SSara Sharon .read_prph = iwl_trans_pcie_read_prph, \ 3023623e7766SSara Sharon .write_prph = iwl_trans_pcie_write_prph, \ 3024623e7766SSara Sharon .read_mem = iwl_trans_pcie_read_mem, \ 3025623e7766SSara Sharon .write_mem = iwl_trans_pcie_write_mem, \ 3026623e7766SSara Sharon .configure = iwl_trans_pcie_configure, \ 3027623e7766SSara Sharon .set_pmi = iwl_trans_pcie_set_pmi, \ 3028623e7766SSara Sharon .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3029623e7766SSara Sharon .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3030623e7766SSara Sharon .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3031623e7766SSara Sharon .ref = iwl_trans_pcie_ref, \ 3032623e7766SSara Sharon .unref = iwl_trans_pcie_unref, \ 3033623e7766SSara Sharon .dump_data = iwl_trans_pcie_dump_data, \ 3034fb12777aSKirtika Ruchandani .dump_regs = iwl_trans_pcie_dump_regs, \ 3035623e7766SSara Sharon .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3036623e7766SSara Sharon .d3_resume = iwl_trans_pcie_d3_resume 3037623e7766SSara Sharon 3038623e7766SSara Sharon #ifdef CONFIG_PM_SLEEP 3039623e7766SSara Sharon #define IWL_TRANS_PM_OPS \ 3040623e7766SSara Sharon .suspend = iwl_trans_pcie_suspend, \ 3041623e7766SSara Sharon .resume = iwl_trans_pcie_resume, 3042623e7766SSara Sharon #else 3043623e7766SSara Sharon #define IWL_TRANS_PM_OPS 3044623e7766SSara Sharon #endif /* CONFIG_PM_SLEEP */ 3045623e7766SSara Sharon 3046e705c121SKalle Valo static const struct iwl_trans_ops trans_ops_pcie = { 3047623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3048623e7766SSara Sharon IWL_TRANS_PM_OPS 3049e705c121SKalle Valo .start_hw = iwl_trans_pcie_start_hw, 3050e705c121SKalle Valo .fw_alive = iwl_trans_pcie_fw_alive, 3051e705c121SKalle Valo .start_fw = iwl_trans_pcie_start_fw, 3052e705c121SKalle Valo .stop_device = iwl_trans_pcie_stop_device, 3053e705c121SKalle Valo 3054e705c121SKalle Valo .send_cmd = iwl_trans_pcie_send_hcmd, 3055e705c121SKalle Valo 3056e705c121SKalle Valo .tx = iwl_trans_pcie_tx, 3057e705c121SKalle Valo .reclaim = iwl_trans_pcie_reclaim, 3058e705c121SKalle Valo 3059e705c121SKalle Valo .txq_disable = iwl_trans_pcie_txq_disable, 3060e705c121SKalle Valo .txq_enable = iwl_trans_pcie_txq_enable, 3061e705c121SKalle Valo 306242db09c1SLiad Kaufman .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 306342db09c1SLiad Kaufman 3064d6d517b7SSara Sharon .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3065d6d517b7SSara Sharon 3066e705c121SKalle Valo .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer, 30670cd58eaaSEmmanuel Grumbach .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3068623e7766SSara Sharon }; 3069e705c121SKalle Valo 3070623e7766SSara Sharon static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3071623e7766SSara Sharon IWL_TRANS_COMMON_OPS, 3072623e7766SSara Sharon IWL_TRANS_PM_OPS 3073623e7766SSara Sharon .start_hw = iwl_trans_pcie_start_hw, 3074eda50cdeSSara Sharon .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3075eda50cdeSSara Sharon .start_fw = iwl_trans_pcie_gen2_start_fw, 307677c09bc8SSara Sharon .stop_device = iwl_trans_pcie_gen2_stop_device, 3077e705c121SKalle Valo 3078ca60da2eSSara Sharon .send_cmd = iwl_trans_pcie_gen2_send_hcmd, 3079e705c121SKalle Valo 3080ab6c6445SSara Sharon .tx = iwl_trans_pcie_gen2_tx, 3081623e7766SSara Sharon .reclaim = iwl_trans_pcie_reclaim, 3082623e7766SSara Sharon 30836b35ff91SSara Sharon .txq_alloc = iwl_trans_pcie_dyn_txq_alloc, 30846b35ff91SSara Sharon .txq_free = iwl_trans_pcie_dyn_txq_free, 3085d6d517b7SSara Sharon .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3086e705c121SKalle Valo }; 3087e705c121SKalle Valo 3088e705c121SKalle Valo struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3089e705c121SKalle Valo const struct pci_device_id *ent, 3090e705c121SKalle Valo const struct iwl_cfg *cfg) 3091e705c121SKalle Valo { 3092e705c121SKalle Valo struct iwl_trans_pcie *trans_pcie; 3093e705c121SKalle Valo struct iwl_trans *trans; 309496a6497bSSara Sharon int ret, addr_size; 3095e705c121SKalle Valo 30965a41a86cSSharon Dvir ret = pcim_enable_device(pdev); 30975a41a86cSSharon Dvir if (ret) 30985a41a86cSSharon Dvir return ERR_PTR(ret); 30995a41a86cSSharon Dvir 3100623e7766SSara Sharon if (cfg->gen2) 3101623e7766SSara Sharon trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 3102623e7766SSara Sharon &pdev->dev, cfg, &trans_ops_pcie_gen2); 3103623e7766SSara Sharon else 3104e705c121SKalle Valo trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), 31051ea423b0SLuca Coelho &pdev->dev, cfg, &trans_ops_pcie); 3106e705c121SKalle Valo if (!trans) 3107e705c121SKalle Valo return ERR_PTR(-ENOMEM); 3108e705c121SKalle Valo 3109e705c121SKalle Valo trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3110e705c121SKalle Valo 3111e705c121SKalle Valo trans_pcie->trans = trans; 3112326477e4SJohannes Berg trans_pcie->opmode_down = true; 3113e705c121SKalle Valo spin_lock_init(&trans_pcie->irq_lock); 3114e705c121SKalle Valo spin_lock_init(&trans_pcie->reg_lock); 3115e705c121SKalle Valo mutex_init(&trans_pcie->mutex); 3116e705c121SKalle Valo init_waitqueue_head(&trans_pcie->ucode_write_waitq); 31176eb5e529SEmmanuel Grumbach trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 31186eb5e529SEmmanuel Grumbach if (!trans_pcie->tso_hdr_page) { 31196eb5e529SEmmanuel Grumbach ret = -ENOMEM; 31206eb5e529SEmmanuel Grumbach goto out_no_pci; 31216eb5e529SEmmanuel Grumbach } 3122e705c121SKalle Valo 3123e705c121SKalle Valo 3124e705c121SKalle Valo if (!cfg->base_params->pcie_l1_allowed) { 3125e705c121SKalle Valo /* 3126e705c121SKalle Valo * W/A - seems to solve weird behavior. We need to remove this 3127e705c121SKalle Valo * if we don't want to stay in L1 all the time. This wastes a 3128e705c121SKalle Valo * lot of power. 3129e705c121SKalle Valo */ 3130e705c121SKalle Valo pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3131e705c121SKalle Valo PCIE_LINK_STATE_L1 | 3132e705c121SKalle Valo PCIE_LINK_STATE_CLKPM); 3133e705c121SKalle Valo } 3134e705c121SKalle Valo 31356983ba69SSara Sharon if (cfg->use_tfh) { 31362c6262b7SSara Sharon addr_size = 64; 31373cd1980bSSara Sharon trans_pcie->max_tbs = IWL_TFH_NUM_TBS; 31388352e62aSSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd); 31396983ba69SSara Sharon } else { 31402c6262b7SSara Sharon addr_size = 36; 31413cd1980bSSara Sharon trans_pcie->max_tbs = IWL_NUM_OF_TBS; 31426983ba69SSara Sharon trans_pcie->tfd_size = sizeof(struct iwl_tfd); 31436983ba69SSara Sharon } 31443cd1980bSSara Sharon trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie); 31453cd1980bSSara Sharon 3146e705c121SKalle Valo pci_set_master(pdev); 3147e705c121SKalle Valo 314896a6497bSSara Sharon ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size)); 3149e705c121SKalle Valo if (!ret) 315096a6497bSSara Sharon ret = pci_set_consistent_dma_mask(pdev, 315196a6497bSSara Sharon DMA_BIT_MASK(addr_size)); 3152e705c121SKalle Valo if (ret) { 3153e705c121SKalle Valo ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 3154e705c121SKalle Valo if (!ret) 3155e705c121SKalle Valo ret = pci_set_consistent_dma_mask(pdev, 3156e705c121SKalle Valo DMA_BIT_MASK(32)); 3157e705c121SKalle Valo /* both attempts failed: */ 3158e705c121SKalle Valo if (ret) { 3159e705c121SKalle Valo dev_err(&pdev->dev, "No suitable DMA available\n"); 31605a41a86cSSharon Dvir goto out_no_pci; 3161e705c121SKalle Valo } 3162e705c121SKalle Valo } 3163e705c121SKalle Valo 31645a41a86cSSharon Dvir ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3165e705c121SKalle Valo if (ret) { 31665a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 31675a41a86cSSharon Dvir goto out_no_pci; 3168e705c121SKalle Valo } 3169e705c121SKalle Valo 31705a41a86cSSharon Dvir trans_pcie->hw_base = pcim_iomap_table(pdev)[0]; 3171e705c121SKalle Valo if (!trans_pcie->hw_base) { 31725a41a86cSSharon Dvir dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3173e705c121SKalle Valo ret = -ENODEV; 31745a41a86cSSharon Dvir goto out_no_pci; 3175e705c121SKalle Valo } 3176e705c121SKalle Valo 3177e705c121SKalle Valo /* We disable the RETRY_TIMEOUT register (0x41) to keep 3178e705c121SKalle Valo * PCI Tx retries from interfering with C3 CPU state */ 3179e705c121SKalle Valo pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3180e705c121SKalle Valo 3181e705c121SKalle Valo trans_pcie->pci_dev = pdev; 3182e705c121SKalle Valo iwl_disable_interrupts(trans); 3183e705c121SKalle Valo 3184e705c121SKalle Valo trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3185e705c121SKalle Valo /* 3186e705c121SKalle Valo * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3187e705c121SKalle Valo * changed, and now the revision step also includes bit 0-1 (no more 3188e705c121SKalle Valo * "dash" value). To keep hw_rev backwards compatible - we'll store it 3189e705c121SKalle Valo * in the old format. 3190e705c121SKalle Valo */ 31916e584873SSara Sharon if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) { 3192e705c121SKalle Valo unsigned long flags; 3193e705c121SKalle Valo 3194e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xfff0) | 3195e705c121SKalle Valo (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2); 3196e705c121SKalle Valo 3197e705c121SKalle Valo ret = iwl_pcie_prepare_card_hw(trans); 3198e705c121SKalle Valo if (ret) { 3199e705c121SKalle Valo IWL_WARN(trans, "Exit HW not ready\n"); 32005a41a86cSSharon Dvir goto out_no_pci; 3201e705c121SKalle Valo } 3202e705c121SKalle Valo 3203e705c121SKalle Valo /* 3204e705c121SKalle Valo * in-order to recognize C step driver should read chip version 3205e705c121SKalle Valo * id located at the AUX bus MISC address space. 3206e705c121SKalle Valo */ 3207e705c121SKalle Valo iwl_set_bit(trans, CSR_GP_CNTRL, 3208e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 3209e705c121SKalle Valo udelay(2); 3210e705c121SKalle Valo 3211e705c121SKalle Valo ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 3212e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3213e705c121SKalle Valo CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 3214e705c121SKalle Valo 25000); 3215e705c121SKalle Valo if (ret < 0) { 3216e705c121SKalle Valo IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n"); 32175a41a86cSSharon Dvir goto out_no_pci; 3218e705c121SKalle Valo } 3219e705c121SKalle Valo 322023ba9340SEmmanuel Grumbach if (iwl_trans_grab_nic_access(trans, &flags)) { 3221e705c121SKalle Valo u32 hw_step; 3222e705c121SKalle Valo 322314ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG); 3224e705c121SKalle Valo hw_step |= ENABLE_WFPM; 322514ef1b43SGolan Ben-Ami iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step); 322614ef1b43SGolan Ben-Ami hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG); 3227e705c121SKalle Valo hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF; 3228e705c121SKalle Valo if (hw_step == 0x3) 3229e705c121SKalle Valo trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) | 3230e705c121SKalle Valo (SILICON_C_STEP << 2); 3231e705c121SKalle Valo iwl_trans_release_nic_access(trans, &flags); 3232e705c121SKalle Valo } 3233e705c121SKalle Valo } 3234e705c121SKalle Valo 3235c00ee467SJohannes Berg /* 3236c00ee467SJohannes Berg * 9000-series integrated A-step has a problem with suspend/resume 3237c00ee467SJohannes Berg * and sometimes even causes the whole platform to get stuck. This 3238c00ee467SJohannes Berg * workaround makes the hardware not go into the problematic state. 3239c00ee467SJohannes Berg */ 3240c00ee467SJohannes Berg if (trans->cfg->integrated && 3241c00ee467SJohannes Berg trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 && 3242c00ee467SJohannes Berg CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP) 3243c00ee467SJohannes Berg iwl_set_bit(trans, CSR_HOST_CHICKEN, 3244c00ee467SJohannes Berg CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME); 3245c00ee467SJohannes Berg 3246f6586b69STzipi Peres #if IS_ENABLED(CONFIG_IWLMVM) 32471afb0ae4SHaim Dreyfuss trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID); 3248f6586b69STzipi Peres if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) { 3249f6586b69STzipi Peres u32 hw_status; 3250f6586b69STzipi Peres 3251f6586b69STzipi Peres hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS); 3252f6586b69STzipi Peres if (hw_status & UMAG_GEN_HW_IS_FPGA) 32535f19d6ddSTzipi Peres trans->cfg = &iwla000_2ax_cfg_qnj_hr_f0; 3254f6586b69STzipi Peres else 3255f6586b69STzipi Peres trans->cfg = &iwla000_2ac_cfg_hr; 3256f6586b69STzipi Peres } 3257f6586b69STzipi Peres #endif 32581afb0ae4SHaim Dreyfuss 32592e5d4a8fSHaim Dreyfuss iwl_pcie_set_interrupt_capa(pdev, trans); 3260e705c121SKalle Valo trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3261e705c121SKalle Valo snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3262e705c121SKalle Valo "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3263e705c121SKalle Valo 3264e705c121SKalle Valo /* Initialize the wait queue for commands */ 3265e705c121SKalle Valo init_waitqueue_head(&trans_pcie->wait_command_queue); 3266e705c121SKalle Valo 32674cbb8e50SLuciano Coelho init_waitqueue_head(&trans_pcie->d0i3_waitq); 32684cbb8e50SLuciano Coelho 32692e5d4a8fSHaim Dreyfuss if (trans_pcie->msix_enabled) { 32702388bd7bSDan Carpenter ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 32712388bd7bSDan Carpenter if (ret) 32725a41a86cSSharon Dvir goto out_no_pci; 32732e5d4a8fSHaim Dreyfuss } else { 3274e705c121SKalle Valo ret = iwl_pcie_alloc_ict(trans); 3275e705c121SKalle Valo if (ret) 32765a41a86cSSharon Dvir goto out_no_pci; 3277e705c121SKalle Valo 32785a41a86cSSharon Dvir ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 32795a41a86cSSharon Dvir iwl_pcie_isr, 3280e705c121SKalle Valo iwl_pcie_irq_handler, 3281e705c121SKalle Valo IRQF_SHARED, DRV_NAME, trans); 3282e705c121SKalle Valo if (ret) { 3283e705c121SKalle Valo IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3284e705c121SKalle Valo goto out_free_ict; 3285e705c121SKalle Valo } 3286e705c121SKalle Valo trans_pcie->inta_mask = CSR_INI_SET_MASK; 32872e5d4a8fSHaim Dreyfuss } 3288e705c121SKalle Valo 328910a54d81SLuca Coelho trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 329010a54d81SLuca Coelho WQ_HIGHPRI | WQ_UNBOUND, 1); 329110a54d81SLuca Coelho INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 329210a54d81SLuca Coelho 3293b3ff1270SLuca Coelho #ifdef CONFIG_IWLWIFI_PCIE_RTPM 3294b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3; 3295b3ff1270SLuca Coelho #else 3296b3ff1270SLuca Coelho trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED; 3297b3ff1270SLuca Coelho #endif /* CONFIG_IWLWIFI_PCIE_RTPM */ 3298b3ff1270SLuca Coelho 3299e705c121SKalle Valo return trans; 3300e705c121SKalle Valo 3301e705c121SKalle Valo out_free_ict: 3302e705c121SKalle Valo iwl_pcie_free_ict(trans); 3303e705c121SKalle Valo out_no_pci: 33046eb5e529SEmmanuel Grumbach free_percpu(trans_pcie->tso_hdr_page); 3305e705c121SKalle Valo iwl_trans_free(trans); 3306e705c121SKalle Valo return ERR_PTR(ret); 3307e705c121SKalle Valo } 3308