1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include "iwl-trans.h" 7 #include "iwl-prph.h" 8 #include "iwl-context-info.h" 9 #include "iwl-context-info-gen3.h" 10 #include "internal.h" 11 #include "fw/dbg.h" 12 13 #define FW_RESET_TIMEOUT (HZ / 5) 14 15 /* 16 * Start up NIC's basic functionality after it has been reset 17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 18 * NOTE: This does not load uCode nor start the embedded processor 19 */ 20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 21 { 22 int ret = 0; 23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 25 26 /* 27 * Use "set_bit" below rather than "write", to preserve any hardware 28 * bits already set by default after reset. 29 */ 30 31 /* 32 * Disable L0s without affecting L1; 33 * don't wait for ICH L0s (ICH bug W/A) 34 */ 35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 40 41 /* 42 * Enable HAP INTA (interrupt from management bus) to 43 * wake device's PCI Express link L1a -> L0s 44 */ 45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 47 48 iwl_pcie_apm_config(trans); 49 50 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 51 if (ret) 52 return ret; 53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 55 56 return 0; 57 } 58 59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 60 { 61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 62 63 if (op_mode_leave) { 64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 65 iwl_pcie_gen2_apm_init(trans); 66 67 /* inform ME that we are leaving */ 68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 69 CSR_RESET_LINK_PWR_MGMT_DISABLED); 70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 71 CSR_HW_IF_CONFIG_REG_PREPARE | 72 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 73 mdelay(1); 74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 75 CSR_RESET_LINK_PWR_MGMT_DISABLED); 76 mdelay(5); 77 } 78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 80 81 /* Stop device's DMA activity */ 82 iwl_pcie_apm_stop_master(trans); 83 84 iwl_trans_sw_reset(trans); 85 86 /* 87 * Clear "initialization complete" bit to move adapter from 88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 89 */ 90 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 91 } 92 93 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans) 94 { 95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96 int ret; 97 98 trans_pcie->fw_reset_state = FW_RESET_REQUESTED; 99 100 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 101 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 102 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); 103 else 104 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 105 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 106 107 /* wait 200ms */ 108 ret = wait_event_timeout(trans_pcie->fw_reset_waitq, 109 trans_pcie->fw_reset_state != FW_RESET_REQUESTED, 110 FW_RESET_TIMEOUT); 111 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) { 112 IWL_INFO(trans, 113 "firmware didn't ACK the reset - continue anyway\n"); 114 iwl_trans_fw_error(trans, true); 115 } 116 117 trans_pcie->fw_reset_state = FW_RESET_IDLE; 118 } 119 120 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 121 { 122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 123 124 lockdep_assert_held(&trans_pcie->mutex); 125 126 if (trans_pcie->is_down) 127 return; 128 129 if (trans_pcie->fw_reset_handshake && 130 trans->state >= IWL_TRANS_FW_STARTED) 131 iwl_trans_pcie_fw_reset_handshake(trans); 132 133 trans_pcie->is_down = true; 134 135 /* tell the device to stop sending interrupts */ 136 iwl_disable_interrupts(trans); 137 138 /* device going down, Stop using ICT table */ 139 iwl_pcie_disable_ict(trans); 140 141 /* 142 * If a HW restart happens during firmware loading, 143 * then the firmware loading might call this function 144 * and later it might be called again due to the 145 * restart. So don't process again if the device is 146 * already dead. 147 */ 148 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 149 IWL_DEBUG_INFO(trans, 150 "DEVICE_ENABLED bit was set and is now cleared\n"); 151 iwl_txq_gen2_tx_free(trans); 152 iwl_pcie_rx_stop(trans); 153 } 154 155 iwl_pcie_ctxt_info_free_paging(trans); 156 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 157 iwl_pcie_ctxt_info_gen3_free(trans, false); 158 else 159 iwl_pcie_ctxt_info_free(trans); 160 161 /* Make sure (redundant) we've released our request to stay awake */ 162 iwl_clear_bit(trans, CSR_GP_CNTRL, 163 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 164 165 /* Stop the device, and put it in low power state */ 166 iwl_pcie_gen2_apm_stop(trans, false); 167 168 iwl_trans_sw_reset(trans); 169 170 /* 171 * Upon stop, the IVAR table gets erased, so msi-x won't 172 * work. This causes a bug in RF-KILL flows, since the interrupt 173 * that enables radio won't fire on the correct irq, and the 174 * driver won't be able to handle the interrupt. 175 * Configure the IVAR table again after reset. 176 */ 177 iwl_pcie_conf_msix_hw(trans_pcie); 178 179 /* 180 * Upon stop, the APM issues an interrupt if HW RF kill is set. 181 * This is a bug in certain verions of the hardware. 182 * Certain devices also keep sending HW RF kill interrupt all 183 * the time, unless the interrupt is ACKed even if the interrupt 184 * should be masked. Re-ACK all the interrupts here. 185 */ 186 iwl_disable_interrupts(trans); 187 188 /* clear all status bits */ 189 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 190 clear_bit(STATUS_INT_ENABLED, &trans->status); 191 clear_bit(STATUS_TPOWER_PMI, &trans->status); 192 193 /* 194 * Even if we stop the HW, we still want the RF kill 195 * interrupt 196 */ 197 iwl_enable_rfkill_int(trans); 198 199 /* re-take ownership to prevent other users from stealing the device */ 200 iwl_pcie_prepare_card_hw(trans); 201 } 202 203 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 204 { 205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 206 bool was_in_rfkill; 207 208 iwl_op_mode_time_point(trans->op_mode, 209 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 210 NULL); 211 212 mutex_lock(&trans_pcie->mutex); 213 trans_pcie->opmode_down = true; 214 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 215 _iwl_trans_pcie_gen2_stop_device(trans); 216 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 217 mutex_unlock(&trans_pcie->mutex); 218 } 219 220 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 221 { 222 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 223 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 224 trans->cfg->min_txq_size); 225 226 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 227 spin_lock_bh(&trans_pcie->irq_lock); 228 iwl_pcie_gen2_apm_init(trans); 229 spin_unlock_bh(&trans_pcie->irq_lock); 230 231 iwl_op_mode_nic_config(trans->op_mode); 232 233 /* Allocate the RX queue, or reset if it is already allocated */ 234 if (iwl_pcie_gen2_rx_init(trans)) 235 return -ENOMEM; 236 237 /* Allocate or reset and init all Tx and Command queues */ 238 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size)) 239 return -ENOMEM; 240 241 /* enable shadow regs in HW */ 242 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 243 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 244 245 return 0; 246 } 247 248 static void iwl_pcie_get_rf_name(struct iwl_trans *trans) 249 { 250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251 char *buf = trans_pcie->rf_name; 252 size_t buflen = sizeof(trans_pcie->rf_name); 253 size_t pos; 254 u32 version; 255 256 if (buf[0]) 257 return; 258 259 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 260 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF): 261 pos = scnprintf(buf, buflen, "JF"); 262 break; 263 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF): 264 pos = scnprintf(buf, buflen, "GF"); 265 break; 266 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4): 267 pos = scnprintf(buf, buflen, "GF4"); 268 break; 269 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 270 pos = scnprintf(buf, buflen, "HR"); 271 break; 272 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 273 pos = scnprintf(buf, buflen, "HR1"); 274 break; 275 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 276 pos = scnprintf(buf, buflen, "HRCDB"); 277 break; 278 default: 279 return; 280 } 281 282 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 283 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 284 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 286 version = iwl_read_prph(trans, CNVI_MBOX_C); 287 switch (version) { 288 case 0x20000: 289 pos += scnprintf(buf + pos, buflen - pos, " B3"); 290 break; 291 case 0x120000: 292 pos += scnprintf(buf + pos, buflen - pos, " B5"); 293 break; 294 default: 295 pos += scnprintf(buf + pos, buflen - pos, 296 " (0x%x)", version); 297 break; 298 } 299 break; 300 default: 301 break; 302 } 303 304 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x", 305 trans->hw_rf_id); 306 307 IWL_INFO(trans, "Detected RF %s\n", buf); 308 309 /* 310 * also add a \n for debugfs - need to do it after printing 311 * since our IWL_INFO machinery wants to see a static \n at 312 * the end of the string 313 */ 314 pos += scnprintf(buf + pos, buflen - pos, "\n"); 315 } 316 317 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 318 { 319 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 320 321 iwl_pcie_reset_ict(trans); 322 323 /* make sure all queue are not stopped/used */ 324 memset(trans->txqs.queue_stopped, 0, 325 sizeof(trans->txqs.queue_stopped)); 326 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 327 328 /* now that we got alive we can free the fw image & the context info. 329 * paging memory cannot be freed included since FW will still use it 330 */ 331 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 332 iwl_pcie_ctxt_info_gen3_free(trans, true); 333 else 334 iwl_pcie_ctxt_info_free(trans); 335 336 /* 337 * Re-enable all the interrupts, including the RF-Kill one, now that 338 * the firmware is alive. 339 */ 340 iwl_enable_interrupts(trans); 341 mutex_lock(&trans_pcie->mutex); 342 iwl_pcie_check_hw_rf_kill(trans); 343 344 iwl_pcie_get_rf_name(trans); 345 mutex_unlock(&trans_pcie->mutex); 346 } 347 348 static void iwl_pcie_set_ltr(struct iwl_trans *trans) 349 { 350 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 351 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 352 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 353 u32_encode_bits(250, 354 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 355 CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 356 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 357 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 358 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 359 360 /* 361 * To workaround hardware latency issues during the boot process, 362 * initialize the LTR to ~250 usec (see ltr_val above). 363 * The firmware initializes this again later (to a smaller value). 364 */ 365 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 366 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 367 !trans->trans_cfg->integrated) { 368 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 369 } else if (trans->trans_cfg->integrated && 370 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 371 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 372 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 373 } 374 } 375 376 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 377 const struct fw_img *fw, bool run_in_rfkill) 378 { 379 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 380 bool hw_rfkill; 381 int ret; 382 383 /* This may fail if AMT took ownership of the device */ 384 if (iwl_pcie_prepare_card_hw(trans)) { 385 IWL_WARN(trans, "Exit HW not ready\n"); 386 ret = -EIO; 387 goto out; 388 } 389 390 iwl_enable_rfkill_int(trans); 391 392 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 393 394 /* 395 * We enabled the RF-Kill interrupt and the handler may very 396 * well be running. Disable the interrupts to make sure no other 397 * interrupt can be fired. 398 */ 399 iwl_disable_interrupts(trans); 400 401 /* Make sure it finished running */ 402 iwl_pcie_synchronize_irqs(trans); 403 404 mutex_lock(&trans_pcie->mutex); 405 406 /* If platform's RF_KILL switch is NOT set to KILL */ 407 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 408 if (hw_rfkill && !run_in_rfkill) { 409 ret = -ERFKILL; 410 goto out; 411 } 412 413 /* Someone called stop_device, don't try to start_fw */ 414 if (trans_pcie->is_down) { 415 IWL_WARN(trans, 416 "Can't start_fw since the HW hasn't been started\n"); 417 ret = -EIO; 418 goto out; 419 } 420 421 /* make sure rfkill handshake bits are cleared */ 422 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 423 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 424 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 425 426 /* clear (again), then enable host interrupts */ 427 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 428 429 ret = iwl_pcie_gen2_nic_init(trans); 430 if (ret) { 431 IWL_ERR(trans, "Unable to init nic\n"); 432 goto out; 433 } 434 435 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 436 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 437 else 438 ret = iwl_pcie_ctxt_info_init(trans, fw); 439 if (ret) 440 goto out; 441 442 iwl_pcie_set_ltr(trans); 443 444 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 445 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 446 else 447 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); 448 449 /* re-check RF-Kill state since we may have missed the interrupt */ 450 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 451 if (hw_rfkill && !run_in_rfkill) 452 ret = -ERFKILL; 453 454 out: 455 mutex_unlock(&trans_pcie->mutex); 456 return ret; 457 } 458