1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2017 Intel Deutschland GmbH 9 * Copyright(c) 2018 Intel Corporation 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Copyright(c) 2017 Intel Deutschland GmbH 23 * Copyright(c) 2018 Intel Corporation 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 *****************************************************************************/ 53 #include "iwl-trans.h" 54 #include "iwl-prph.h" 55 #include "iwl-context-info.h" 56 #include "internal.h" 57 58 /* 59 * Start up NIC's basic functionality after it has been reset 60 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 61 * NOTE: This does not load uCode nor start the embedded processor 62 */ 63 static int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 64 { 65 int ret = 0; 66 67 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 68 69 /* 70 * Use "set_bit" below rather than "write", to preserve any hardware 71 * bits already set by default after reset. 72 */ 73 74 /* 75 * Disable L0s without affecting L1; 76 * don't wait for ICH L0s (ICH bug W/A) 77 */ 78 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 79 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 80 81 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 82 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 83 84 /* 85 * Enable HAP INTA (interrupt from management bus) to 86 * wake device's PCI Express link L1a -> L0s 87 */ 88 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 89 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 90 91 iwl_pcie_apm_config(trans); 92 93 /* 94 * Set "initialization complete" bit to move adapter from 95 * D0U* --> D0A* (powered-up active) state. 96 */ 97 iwl_set_bit(trans, CSR_GP_CNTRL, 98 BIT(trans->cfg->csr->flag_init_done)); 99 100 /* 101 * Wait for clock stabilization; once stabilized, access to 102 * device-internal resources is supported, e.g. iwl_write_prph() 103 * and accesses to uCode SRAM. 104 */ 105 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 106 BIT(trans->cfg->csr->flag_mac_clock_ready), 107 BIT(trans->cfg->csr->flag_mac_clock_ready), 108 25000); 109 if (ret < 0) { 110 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 111 return ret; 112 } 113 114 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 115 116 return 0; 117 } 118 119 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 120 { 121 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 122 123 if (op_mode_leave) { 124 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 125 iwl_pcie_gen2_apm_init(trans); 126 127 /* inform ME that we are leaving */ 128 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 129 CSR_RESET_LINK_PWR_MGMT_DISABLED); 130 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 131 CSR_HW_IF_CONFIG_REG_PREPARE | 132 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 133 mdelay(1); 134 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 135 CSR_RESET_LINK_PWR_MGMT_DISABLED); 136 mdelay(5); 137 } 138 139 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 140 141 /* Stop device's DMA activity */ 142 iwl_pcie_apm_stop_master(trans); 143 144 iwl_trans_sw_reset(trans); 145 146 /* 147 * Clear "initialization complete" bit to move adapter from 148 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 149 */ 150 iwl_clear_bit(trans, CSR_GP_CNTRL, 151 BIT(trans->cfg->csr->flag_init_done)); 152 } 153 154 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power) 155 { 156 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 157 158 lockdep_assert_held(&trans_pcie->mutex); 159 160 if (trans_pcie->is_down) 161 return; 162 163 trans_pcie->is_down = true; 164 165 /* Stop dbgc before stopping device */ 166 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0); 167 udelay(100); 168 iwl_write_prph(trans, DBGC_OUT_CTRL, 0); 169 170 /* tell the device to stop sending interrupts */ 171 iwl_disable_interrupts(trans); 172 173 /* device going down, Stop using ICT table */ 174 iwl_pcie_disable_ict(trans); 175 176 /* 177 * If a HW restart happens during firmware loading, 178 * then the firmware loading might call this function 179 * and later it might be called again due to the 180 * restart. So don't process again if the device is 181 * already dead. 182 */ 183 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 184 IWL_DEBUG_INFO(trans, 185 "DEVICE_ENABLED bit was set and is now cleared\n"); 186 iwl_pcie_gen2_tx_stop(trans); 187 iwl_pcie_rx_stop(trans); 188 } 189 190 iwl_pcie_ctxt_info_free_paging(trans); 191 iwl_pcie_ctxt_info_free(trans); 192 193 /* Make sure (redundant) we've released our request to stay awake */ 194 iwl_clear_bit(trans, CSR_GP_CNTRL, 195 BIT(trans->cfg->csr->flag_mac_access_req)); 196 197 /* Stop the device, and put it in low power state */ 198 iwl_pcie_gen2_apm_stop(trans, false); 199 200 iwl_trans_sw_reset(trans); 201 202 /* 203 * Upon stop, the IVAR table gets erased, so msi-x won't 204 * work. This causes a bug in RF-KILL flows, since the interrupt 205 * that enables radio won't fire on the correct irq, and the 206 * driver won't be able to handle the interrupt. 207 * Configure the IVAR table again after reset. 208 */ 209 iwl_pcie_conf_msix_hw(trans_pcie); 210 211 /* 212 * Upon stop, the APM issues an interrupt if HW RF kill is set. 213 * This is a bug in certain verions of the hardware. 214 * Certain devices also keep sending HW RF kill interrupt all 215 * the time, unless the interrupt is ACKed even if the interrupt 216 * should be masked. Re-ACK all the interrupts here. 217 */ 218 iwl_disable_interrupts(trans); 219 220 /* clear all status bits */ 221 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 222 clear_bit(STATUS_INT_ENABLED, &trans->status); 223 clear_bit(STATUS_TPOWER_PMI, &trans->status); 224 225 /* 226 * Even if we stop the HW, we still want the RF kill 227 * interrupt 228 */ 229 iwl_enable_rfkill_int(trans); 230 231 /* re-take ownership to prevent other users from stealing the device */ 232 iwl_pcie_prepare_card_hw(trans); 233 } 234 235 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power) 236 { 237 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 238 bool was_in_rfkill; 239 240 mutex_lock(&trans_pcie->mutex); 241 trans_pcie->opmode_down = true; 242 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 243 _iwl_trans_pcie_gen2_stop_device(trans, low_power); 244 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 245 mutex_unlock(&trans_pcie->mutex); 246 } 247 248 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 249 { 250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 251 252 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 253 spin_lock(&trans_pcie->irq_lock); 254 iwl_pcie_gen2_apm_init(trans); 255 spin_unlock(&trans_pcie->irq_lock); 256 257 iwl_op_mode_nic_config(trans->op_mode); 258 259 /* Allocate the RX queue, or reset if it is already allocated */ 260 if (iwl_pcie_gen2_rx_init(trans)) 261 return -ENOMEM; 262 263 /* Allocate or reset and init all Tx and Command queues */ 264 if (iwl_pcie_gen2_tx_init(trans)) 265 return -ENOMEM; 266 267 /* enable shadow regs in HW */ 268 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 269 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 270 271 return 0; 272 } 273 274 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 275 { 276 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 277 278 iwl_pcie_reset_ict(trans); 279 280 /* make sure all queue are not stopped/used */ 281 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 282 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 283 284 /* now that we got alive we can free the fw image & the context info. 285 * paging memory cannot be freed included since FW will still use it 286 */ 287 iwl_pcie_ctxt_info_free(trans); 288 } 289 290 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 291 const struct fw_img *fw, bool run_in_rfkill) 292 { 293 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 294 bool hw_rfkill; 295 int ret; 296 297 /* This may fail if AMT took ownership of the device */ 298 if (iwl_pcie_prepare_card_hw(trans)) { 299 IWL_WARN(trans, "Exit HW not ready\n"); 300 ret = -EIO; 301 goto out; 302 } 303 304 iwl_enable_rfkill_int(trans); 305 306 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 307 308 /* 309 * We enabled the RF-Kill interrupt and the handler may very 310 * well be running. Disable the interrupts to make sure no other 311 * interrupt can be fired. 312 */ 313 iwl_disable_interrupts(trans); 314 315 /* Make sure it finished running */ 316 iwl_pcie_synchronize_irqs(trans); 317 318 mutex_lock(&trans_pcie->mutex); 319 320 /* If platform's RF_KILL switch is NOT set to KILL */ 321 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 322 if (hw_rfkill && !run_in_rfkill) { 323 ret = -ERFKILL; 324 goto out; 325 } 326 327 /* Someone called stop_device, don't try to start_fw */ 328 if (trans_pcie->is_down) { 329 IWL_WARN(trans, 330 "Can't start_fw since the HW hasn't been started\n"); 331 ret = -EIO; 332 goto out; 333 } 334 335 /* make sure rfkill handshake bits are cleared */ 336 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 337 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 338 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 339 340 /* clear (again), then enable host interrupts */ 341 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 342 343 ret = iwl_pcie_gen2_nic_init(trans); 344 if (ret) { 345 IWL_ERR(trans, "Unable to init nic\n"); 346 goto out; 347 } 348 349 ret = iwl_pcie_ctxt_info_init(trans, fw); 350 if (ret) 351 goto out; 352 353 /* re-check RF-Kill state since we may have missed the interrupt */ 354 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 355 if (hw_rfkill && !run_in_rfkill) 356 ret = -ERFKILL; 357 358 out: 359 mutex_unlock(&trans_pcie->mutex); 360 return ret; 361 } 362