1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2017 Intel Deutschland GmbH 9 * Copyright(c) 2018 Intel Corporation 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Copyright(c) 2017 Intel Deutschland GmbH 23 * Copyright(c) 2018 Intel Corporation 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 30 * * Redistributions of source code must retain the above copyright 31 * notice, this list of conditions and the following disclaimer. 32 * * Redistributions in binary form must reproduce the above copyright 33 * notice, this list of conditions and the following disclaimer in 34 * the documentation and/or other materials provided with the 35 * distribution. 36 * * Neither the name Intel Corporation nor the names of its 37 * contributors may be used to endorse or promote products derived 38 * from this software without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 *****************************************************************************/ 53 #include "iwl-trans.h" 54 #include "iwl-prph.h" 55 #include "iwl-context-info.h" 56 #include "iwl-context-info-gen3.h" 57 #include "internal.h" 58 #include "fw/dbg.h" 59 60 /* 61 * Start up NIC's basic functionality after it has been reset 62 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 63 * NOTE: This does not load uCode nor start the embedded processor 64 */ 65 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 66 { 67 int ret = 0; 68 69 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 70 71 /* 72 * Use "set_bit" below rather than "write", to preserve any hardware 73 * bits already set by default after reset. 74 */ 75 76 /* 77 * Disable L0s without affecting L1; 78 * don't wait for ICH L0s (ICH bug W/A) 79 */ 80 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 81 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 82 83 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 84 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 85 86 /* 87 * Enable HAP INTA (interrupt from management bus) to 88 * wake device's PCI Express link L1a -> L0s 89 */ 90 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 92 93 iwl_pcie_apm_config(trans); 94 95 /* 96 * Set "initialization complete" bit to move adapter from 97 * D0U* --> D0A* (powered-up active) state. 98 */ 99 iwl_set_bit(trans, CSR_GP_CNTRL, 100 BIT(trans->cfg->csr->flag_init_done)); 101 102 /* 103 * Wait for clock stabilization; once stabilized, access to 104 * device-internal resources is supported, e.g. iwl_write_prph() 105 * and accesses to uCode SRAM. 106 */ 107 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 108 BIT(trans->cfg->csr->flag_mac_clock_ready), 109 BIT(trans->cfg->csr->flag_mac_clock_ready), 110 25000); 111 if (ret < 0) { 112 IWL_DEBUG_INFO(trans, "Failed to init the card\n"); 113 return ret; 114 } 115 116 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 117 118 return 0; 119 } 120 121 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 122 { 123 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 124 125 if (op_mode_leave) { 126 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 127 iwl_pcie_gen2_apm_init(trans); 128 129 /* inform ME that we are leaving */ 130 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 131 CSR_RESET_LINK_PWR_MGMT_DISABLED); 132 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 133 CSR_HW_IF_CONFIG_REG_PREPARE | 134 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 135 mdelay(1); 136 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 137 CSR_RESET_LINK_PWR_MGMT_DISABLED); 138 mdelay(5); 139 } 140 141 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 142 143 /* Stop device's DMA activity */ 144 iwl_pcie_apm_stop_master(trans); 145 146 iwl_trans_sw_reset(trans); 147 148 /* 149 * Clear "initialization complete" bit to move adapter from 150 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 151 */ 152 iwl_clear_bit(trans, CSR_GP_CNTRL, 153 BIT(trans->cfg->csr->flag_init_done)); 154 } 155 156 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power) 157 { 158 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 159 160 lockdep_assert_held(&trans_pcie->mutex); 161 162 if (trans_pcie->is_down) 163 return; 164 165 trans_pcie->is_down = true; 166 167 /* Stop dbgc before stopping device */ 168 _iwl_fw_dbg_stop_recording(trans, NULL); 169 170 /* tell the device to stop sending interrupts */ 171 iwl_disable_interrupts(trans); 172 173 /* device going down, Stop using ICT table */ 174 iwl_pcie_disable_ict(trans); 175 176 /* 177 * If a HW restart happens during firmware loading, 178 * then the firmware loading might call this function 179 * and later it might be called again due to the 180 * restart. So don't process again if the device is 181 * already dead. 182 */ 183 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 184 IWL_DEBUG_INFO(trans, 185 "DEVICE_ENABLED bit was set and is now cleared\n"); 186 iwl_pcie_gen2_tx_stop(trans); 187 iwl_pcie_rx_stop(trans); 188 } 189 190 iwl_pcie_ctxt_info_free_paging(trans); 191 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560) 192 iwl_pcie_ctxt_info_gen3_free(trans); 193 else 194 iwl_pcie_ctxt_info_free(trans); 195 196 /* Make sure (redundant) we've released our request to stay awake */ 197 iwl_clear_bit(trans, CSR_GP_CNTRL, 198 BIT(trans->cfg->csr->flag_mac_access_req)); 199 200 /* Stop the device, and put it in low power state */ 201 iwl_pcie_gen2_apm_stop(trans, false); 202 203 iwl_trans_sw_reset(trans); 204 205 /* 206 * Upon stop, the IVAR table gets erased, so msi-x won't 207 * work. This causes a bug in RF-KILL flows, since the interrupt 208 * that enables radio won't fire on the correct irq, and the 209 * driver won't be able to handle the interrupt. 210 * Configure the IVAR table again after reset. 211 */ 212 iwl_pcie_conf_msix_hw(trans_pcie); 213 214 /* 215 * Upon stop, the APM issues an interrupt if HW RF kill is set. 216 * This is a bug in certain verions of the hardware. 217 * Certain devices also keep sending HW RF kill interrupt all 218 * the time, unless the interrupt is ACKed even if the interrupt 219 * should be masked. Re-ACK all the interrupts here. 220 */ 221 iwl_disable_interrupts(trans); 222 223 /* clear all status bits */ 224 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 225 clear_bit(STATUS_INT_ENABLED, &trans->status); 226 clear_bit(STATUS_TPOWER_PMI, &trans->status); 227 228 /* 229 * Even if we stop the HW, we still want the RF kill 230 * interrupt 231 */ 232 iwl_enable_rfkill_int(trans); 233 234 /* re-take ownership to prevent other users from stealing the device */ 235 iwl_pcie_prepare_card_hw(trans); 236 } 237 238 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans, bool low_power) 239 { 240 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 241 bool was_in_rfkill; 242 243 mutex_lock(&trans_pcie->mutex); 244 trans_pcie->opmode_down = true; 245 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 246 _iwl_trans_pcie_gen2_stop_device(trans, low_power); 247 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 248 mutex_unlock(&trans_pcie->mutex); 249 } 250 251 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 252 { 253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 254 255 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 256 spin_lock(&trans_pcie->irq_lock); 257 iwl_pcie_gen2_apm_init(trans); 258 spin_unlock(&trans_pcie->irq_lock); 259 260 iwl_op_mode_nic_config(trans->op_mode); 261 262 /* Allocate the RX queue, or reset if it is already allocated */ 263 if (iwl_pcie_gen2_rx_init(trans)) 264 return -ENOMEM; 265 266 /* Allocate or reset and init all Tx and Command queues */ 267 if (iwl_pcie_gen2_tx_init(trans, trans_pcie->cmd_queue, TFD_CMD_SLOTS)) 268 return -ENOMEM; 269 270 /* enable shadow regs in HW */ 271 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 272 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 273 274 return 0; 275 } 276 277 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 278 { 279 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 280 281 iwl_pcie_reset_ict(trans); 282 283 /* make sure all queue are not stopped/used */ 284 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); 285 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); 286 287 /* now that we got alive we can free the fw image & the context info. 288 * paging memory cannot be freed included since FW will still use it 289 */ 290 iwl_pcie_ctxt_info_free(trans); 291 } 292 293 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 294 const struct fw_img *fw, bool run_in_rfkill) 295 { 296 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 297 bool hw_rfkill; 298 int ret; 299 300 /* This may fail if AMT took ownership of the device */ 301 if (iwl_pcie_prepare_card_hw(trans)) { 302 IWL_WARN(trans, "Exit HW not ready\n"); 303 ret = -EIO; 304 goto out; 305 } 306 307 iwl_enable_rfkill_int(trans); 308 309 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 310 311 /* 312 * We enabled the RF-Kill interrupt and the handler may very 313 * well be running. Disable the interrupts to make sure no other 314 * interrupt can be fired. 315 */ 316 iwl_disable_interrupts(trans); 317 318 /* Make sure it finished running */ 319 iwl_pcie_synchronize_irqs(trans); 320 321 mutex_lock(&trans_pcie->mutex); 322 323 /* If platform's RF_KILL switch is NOT set to KILL */ 324 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 325 if (hw_rfkill && !run_in_rfkill) { 326 ret = -ERFKILL; 327 goto out; 328 } 329 330 /* Someone called stop_device, don't try to start_fw */ 331 if (trans_pcie->is_down) { 332 IWL_WARN(trans, 333 "Can't start_fw since the HW hasn't been started\n"); 334 ret = -EIO; 335 goto out; 336 } 337 338 /* make sure rfkill handshake bits are cleared */ 339 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 340 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 341 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 342 343 /* clear (again), then enable host interrupts */ 344 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 345 346 ret = iwl_pcie_gen2_nic_init(trans); 347 if (ret) { 348 IWL_ERR(trans, "Unable to init nic\n"); 349 goto out; 350 } 351 352 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_22560) 353 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 354 else 355 ret = iwl_pcie_ctxt_info_init(trans, fw); 356 if (ret) 357 goto out; 358 359 /* re-check RF-Kill state since we may have missed the interrupt */ 360 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 361 if (hw_rfkill && !run_in_rfkill) 362 ret = -ERFKILL; 363 364 out: 365 mutex_unlock(&trans_pcie->mutex); 366 return ret; 367 } 368