1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2022 Intel Corporation 5 */ 6 #include "iwl-trans.h" 7 #include "iwl-prph.h" 8 #include "iwl-context-info.h" 9 #include "iwl-context-info-gen3.h" 10 #include "internal.h" 11 #include "fw/dbg.h" 12 13 #define FW_RESET_TIMEOUT (HZ / 5) 14 15 /* 16 * Start up NIC's basic functionality after it has been reset 17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 18 * NOTE: This does not load uCode nor start the embedded processor 19 */ 20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 21 { 22 int ret = 0; 23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 25 26 /* 27 * Use "set_bit" below rather than "write", to preserve any hardware 28 * bits already set by default after reset. 29 */ 30 31 /* 32 * Disable L0s without affecting L1; 33 * don't wait for ICH L0s (ICH bug W/A) 34 */ 35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 40 41 /* 42 * Enable HAP INTA (interrupt from management bus) to 43 * wake device's PCI Express link L1a -> L0s 44 */ 45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 47 48 iwl_pcie_apm_config(trans); 49 50 ret = iwl_finish_nic_init(trans); 51 if (ret) 52 return ret; 53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 55 56 return 0; 57 } 58 59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 60 { 61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 62 63 if (op_mode_leave) { 64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 65 iwl_pcie_gen2_apm_init(trans); 66 67 /* inform ME that we are leaving */ 68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 69 CSR_RESET_LINK_PWR_MGMT_DISABLED); 70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 71 CSR_HW_IF_CONFIG_REG_PREPARE | 72 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 73 mdelay(1); 74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 75 CSR_RESET_LINK_PWR_MGMT_DISABLED); 76 mdelay(5); 77 } 78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 80 81 /* Stop device's DMA activity */ 82 iwl_pcie_apm_stop_master(trans); 83 84 iwl_trans_sw_reset(trans, false); 85 86 /* 87 * Clear "initialization complete" bit to move adapter from 88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 89 */ 90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 91 iwl_clear_bit(trans, CSR_GP_CNTRL, 92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 93 else 94 iwl_clear_bit(trans, CSR_GP_CNTRL, 95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 96 } 97 98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans) 99 { 100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 101 int ret; 102 103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED; 104 105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); 108 else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 111 else 112 iwl_write32(trans, CSR_DOORBELL_VECTOR, 113 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 114 115 /* wait 200ms */ 116 ret = wait_event_timeout(trans_pcie->fw_reset_waitq, 117 trans_pcie->fw_reset_state != FW_RESET_REQUESTED, 118 FW_RESET_TIMEOUT); 119 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) { 120 IWL_INFO(trans, 121 "firmware didn't ACK the reset - continue anyway\n"); 122 iwl_trans_fw_error(trans, true); 123 } 124 125 trans_pcie->fw_reset_state = FW_RESET_IDLE; 126 } 127 128 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 129 { 130 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 131 132 lockdep_assert_held(&trans_pcie->mutex); 133 134 if (trans_pcie->is_down) 135 return; 136 137 if (trans->state >= IWL_TRANS_FW_STARTED) 138 if (trans_pcie->fw_reset_handshake) 139 iwl_trans_pcie_fw_reset_handshake(trans); 140 141 trans_pcie->is_down = true; 142 143 /* tell the device to stop sending interrupts */ 144 iwl_disable_interrupts(trans); 145 146 /* device going down, Stop using ICT table */ 147 iwl_pcie_disable_ict(trans); 148 149 /* 150 * If a HW restart happens during firmware loading, 151 * then the firmware loading might call this function 152 * and later it might be called again due to the 153 * restart. So don't process again if the device is 154 * already dead. 155 */ 156 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 157 IWL_DEBUG_INFO(trans, 158 "DEVICE_ENABLED bit was set and is now cleared\n"); 159 iwl_pcie_rx_napi_sync(trans); 160 iwl_txq_gen2_tx_free(trans); 161 iwl_pcie_rx_stop(trans); 162 } 163 164 iwl_pcie_ctxt_info_free_paging(trans); 165 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 166 iwl_pcie_ctxt_info_gen3_free(trans, false); 167 else 168 iwl_pcie_ctxt_info_free(trans); 169 170 /* Stop the device, and put it in low power state */ 171 iwl_pcie_gen2_apm_stop(trans, false); 172 173 /* re-take ownership to prevent other users from stealing the device */ 174 iwl_trans_sw_reset(trans, true); 175 176 /* 177 * Upon stop, the IVAR table gets erased, so msi-x won't 178 * work. This causes a bug in RF-KILL flows, since the interrupt 179 * that enables radio won't fire on the correct irq, and the 180 * driver won't be able to handle the interrupt. 181 * Configure the IVAR table again after reset. 182 */ 183 iwl_pcie_conf_msix_hw(trans_pcie); 184 185 /* 186 * Upon stop, the APM issues an interrupt if HW RF kill is set. 187 * This is a bug in certain verions of the hardware. 188 * Certain devices also keep sending HW RF kill interrupt all 189 * the time, unless the interrupt is ACKed even if the interrupt 190 * should be masked. Re-ACK all the interrupts here. 191 */ 192 iwl_disable_interrupts(trans); 193 194 /* clear all status bits */ 195 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 196 clear_bit(STATUS_INT_ENABLED, &trans->status); 197 clear_bit(STATUS_TPOWER_PMI, &trans->status); 198 199 /* 200 * Even if we stop the HW, we still want the RF kill 201 * interrupt 202 */ 203 iwl_enable_rfkill_int(trans); 204 } 205 206 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 207 { 208 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 209 bool was_in_rfkill; 210 211 iwl_op_mode_time_point(trans->op_mode, 212 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 213 NULL); 214 215 mutex_lock(&trans_pcie->mutex); 216 trans_pcie->opmode_down = true; 217 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 218 _iwl_trans_pcie_gen2_stop_device(trans); 219 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 220 mutex_unlock(&trans_pcie->mutex); 221 } 222 223 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 224 { 225 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 226 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 227 trans->cfg->min_txq_size); 228 229 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 230 spin_lock_bh(&trans_pcie->irq_lock); 231 iwl_pcie_gen2_apm_init(trans); 232 spin_unlock_bh(&trans_pcie->irq_lock); 233 234 iwl_op_mode_nic_config(trans->op_mode); 235 236 /* Allocate the RX queue, or reset if it is already allocated */ 237 if (iwl_pcie_gen2_rx_init(trans)) 238 return -ENOMEM; 239 240 /* Allocate or reset and init all Tx and Command queues */ 241 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size)) 242 return -ENOMEM; 243 244 /* enable shadow regs in HW */ 245 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 246 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 247 248 return 0; 249 } 250 251 static void iwl_pcie_get_rf_name(struct iwl_trans *trans) 252 { 253 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 254 char *buf = trans_pcie->rf_name; 255 size_t buflen = sizeof(trans_pcie->rf_name); 256 size_t pos; 257 u32 version; 258 259 if (buf[0]) 260 return; 261 262 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 263 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF): 264 pos = scnprintf(buf, buflen, "JF"); 265 break; 266 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF): 267 pos = scnprintf(buf, buflen, "GF"); 268 break; 269 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4): 270 pos = scnprintf(buf, buflen, "GF4"); 271 break; 272 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 273 pos = scnprintf(buf, buflen, "HR"); 274 break; 275 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 276 pos = scnprintf(buf, buflen, "HR1"); 277 break; 278 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 279 pos = scnprintf(buf, buflen, "HRCDB"); 280 break; 281 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS): 282 pos = scnprintf(buf, buflen, "MS"); 283 break; 284 default: 285 return; 286 } 287 288 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 289 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 290 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 291 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 292 version = iwl_read_prph(trans, CNVI_MBOX_C); 293 switch (version) { 294 case 0x20000: 295 pos += scnprintf(buf + pos, buflen - pos, " B3"); 296 break; 297 case 0x120000: 298 pos += scnprintf(buf + pos, buflen - pos, " B5"); 299 break; 300 default: 301 pos += scnprintf(buf + pos, buflen - pos, 302 " (0x%x)", version); 303 break; 304 } 305 break; 306 default: 307 break; 308 } 309 310 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x", 311 trans->hw_rf_id); 312 313 IWL_INFO(trans, "Detected RF %s\n", buf); 314 315 /* 316 * also add a \n for debugfs - need to do it after printing 317 * since our IWL_INFO machinery wants to see a static \n at 318 * the end of the string 319 */ 320 pos += scnprintf(buf + pos, buflen - pos, "\n"); 321 } 322 323 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 324 { 325 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 326 327 iwl_pcie_reset_ict(trans); 328 329 /* make sure all queue are not stopped/used */ 330 memset(trans->txqs.queue_stopped, 0, 331 sizeof(trans->txqs.queue_stopped)); 332 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 333 334 /* now that we got alive we can free the fw image & the context info. 335 * paging memory cannot be freed included since FW will still use it 336 */ 337 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 338 iwl_pcie_ctxt_info_gen3_free(trans, true); 339 else 340 iwl_pcie_ctxt_info_free(trans); 341 342 /* 343 * Re-enable all the interrupts, including the RF-Kill one, now that 344 * the firmware is alive. 345 */ 346 iwl_enable_interrupts(trans); 347 mutex_lock(&trans_pcie->mutex); 348 iwl_pcie_check_hw_rf_kill(trans); 349 350 iwl_pcie_get_rf_name(trans); 351 mutex_unlock(&trans_pcie->mutex); 352 } 353 354 static bool iwl_pcie_set_ltr(struct iwl_trans *trans) 355 { 356 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 357 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 358 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 359 u32_encode_bits(250, 360 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 361 CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 362 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 363 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 364 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 365 366 /* 367 * To workaround hardware latency issues during the boot process, 368 * initialize the LTR to ~250 usec (see ltr_val above). 369 * The firmware initializes this again later (to a smaller value). 370 */ 371 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 372 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 373 !trans->trans_cfg->integrated) { 374 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 375 return true; 376 } 377 378 if (trans->trans_cfg->integrated && 379 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 380 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 381 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 382 return true; 383 } 384 385 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) { 386 /* First clear the interrupt, just in case */ 387 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, 388 MSIX_HW_INT_CAUSES_REG_IML); 389 /* In this case, unfortunately the same ROM bug exists in the 390 * device (not setting LTR correctly), but we don't have control 391 * over the settings from the host due to some hardware security 392 * features. The only workaround we've been able to come up with 393 * so far is to try to keep the CPU and device busy by polling 394 * it and the IML (image loader) completed interrupt. 395 */ 396 return false; 397 } 398 399 /* nothing needs to be done on other devices */ 400 return true; 401 } 402 403 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans) 404 { 405 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */ 406 #define IML_WAIT_TIMEOUT (HZ / 10) 407 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 408 unsigned long end_time = jiffies + IML_WAIT_TIMEOUT; 409 u32 value, loops = 0; 410 bool irq = false; 411 412 if (WARN_ON(!trans_pcie->iml)) 413 return; 414 415 value = iwl_read32(trans, CSR_LTR_LAST_MSG); 416 IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n", 417 value); 418 419 while (time_before(jiffies, end_time)) { 420 if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) & 421 MSIX_HW_INT_CAUSES_REG_IML) { 422 irq = true; 423 break; 424 } 425 /* Keep the CPU and device busy. */ 426 value = iwl_read32(trans, CSR_LTR_LAST_MSG); 427 loops++; 428 } 429 430 IWL_DEBUG_INFO(trans, 431 "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n", 432 irq, loops, value); 433 434 /* We don't fail here even if we timed out - maybe we get lucky and the 435 * interrupt comes in later (and we get alive from firmware) and then 436 * we're all happy - but if not we'll fail on alive timeout or get some 437 * other error out. 438 */ 439 } 440 441 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 442 const struct fw_img *fw, bool run_in_rfkill) 443 { 444 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 445 bool hw_rfkill, keep_ram_busy; 446 int ret; 447 448 /* This may fail if AMT took ownership of the device */ 449 if (iwl_pcie_prepare_card_hw(trans)) { 450 IWL_WARN(trans, "Exit HW not ready\n"); 451 return -EIO; 452 } 453 454 iwl_enable_rfkill_int(trans); 455 456 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 457 458 /* 459 * We enabled the RF-Kill interrupt and the handler may very 460 * well be running. Disable the interrupts to make sure no other 461 * interrupt can be fired. 462 */ 463 iwl_disable_interrupts(trans); 464 465 /* Make sure it finished running */ 466 iwl_pcie_synchronize_irqs(trans); 467 468 mutex_lock(&trans_pcie->mutex); 469 470 /* If platform's RF_KILL switch is NOT set to KILL */ 471 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 472 if (hw_rfkill && !run_in_rfkill) { 473 ret = -ERFKILL; 474 goto out; 475 } 476 477 /* Someone called stop_device, don't try to start_fw */ 478 if (trans_pcie->is_down) { 479 IWL_WARN(trans, 480 "Can't start_fw since the HW hasn't been started\n"); 481 ret = -EIO; 482 goto out; 483 } 484 485 /* make sure rfkill handshake bits are cleared */ 486 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 487 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 488 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 489 490 /* clear (again), then enable host interrupts */ 491 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 492 493 ret = iwl_pcie_gen2_nic_init(trans); 494 if (ret) { 495 IWL_ERR(trans, "Unable to init nic\n"); 496 goto out; 497 } 498 499 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 500 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 501 else 502 ret = iwl_pcie_ctxt_info_init(trans, fw); 503 if (ret) 504 goto out; 505 506 keep_ram_busy = !iwl_pcie_set_ltr(trans); 507 508 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 509 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE); 510 iwl_set_bit(trans, CSR_GP_CNTRL, 511 CSR_GP_CNTRL_REG_FLAG_ROM_START); 512 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 513 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 514 } else { 515 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); 516 } 517 518 if (keep_ram_busy) 519 iwl_pcie_spin_for_iml(trans); 520 521 /* re-check RF-Kill state since we may have missed the interrupt */ 522 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 523 if (hw_rfkill && !run_in_rfkill) 524 ret = -ERFKILL; 525 526 out: 527 mutex_unlock(&trans_pcie->mutex); 528 return ret; 529 } 530