1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include "iwl-trans.h" 7 #include "iwl-prph.h" 8 #include "iwl-context-info.h" 9 #include "iwl-context-info-gen3.h" 10 #include "internal.h" 11 #include "fw/dbg.h" 12 13 #define FW_RESET_TIMEOUT (HZ / 5) 14 15 /* 16 * Start up NIC's basic functionality after it has been reset 17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 18 * NOTE: This does not load uCode nor start the embedded processor 19 */ 20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 21 { 22 int ret = 0; 23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 25 26 /* 27 * Use "set_bit" below rather than "write", to preserve any hardware 28 * bits already set by default after reset. 29 */ 30 31 /* 32 * Disable L0s without affecting L1; 33 * don't wait for ICH L0s (ICH bug W/A) 34 */ 35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 40 41 /* 42 * Enable HAP INTA (interrupt from management bus) to 43 * wake device's PCI Express link L1a -> L0s 44 */ 45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 47 48 iwl_pcie_apm_config(trans); 49 50 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 51 if (ret) 52 return ret; 53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 55 56 return 0; 57 } 58 59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 60 { 61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 62 63 if (op_mode_leave) { 64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 65 iwl_pcie_gen2_apm_init(trans); 66 67 /* inform ME that we are leaving */ 68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 69 CSR_RESET_LINK_PWR_MGMT_DISABLED); 70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 71 CSR_HW_IF_CONFIG_REG_PREPARE | 72 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 73 mdelay(1); 74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 75 CSR_RESET_LINK_PWR_MGMT_DISABLED); 76 mdelay(5); 77 } 78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 80 81 /* Stop device's DMA activity */ 82 iwl_pcie_apm_stop_master(trans); 83 84 iwl_trans_sw_reset(trans); 85 86 /* 87 * Clear "initialization complete" bit to move adapter from 88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 89 */ 90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 91 iwl_clear_bit(trans, CSR_GP_CNTRL, 92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 93 else 94 iwl_clear_bit(trans, CSR_GP_CNTRL, 95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 96 } 97 98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans) 99 { 100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 101 int ret; 102 103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED; 104 105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); 108 else 109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 111 112 /* wait 200ms */ 113 ret = wait_event_timeout(trans_pcie->fw_reset_waitq, 114 trans_pcie->fw_reset_state != FW_RESET_REQUESTED, 115 FW_RESET_TIMEOUT); 116 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) { 117 IWL_INFO(trans, 118 "firmware didn't ACK the reset - continue anyway\n"); 119 iwl_trans_fw_error(trans, true); 120 } 121 122 trans_pcie->fw_reset_state = FW_RESET_IDLE; 123 } 124 125 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 126 { 127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 128 129 lockdep_assert_held(&trans_pcie->mutex); 130 131 if (trans_pcie->is_down) 132 return; 133 134 if (trans->state >= IWL_TRANS_FW_STARTED) 135 if (trans_pcie->fw_reset_handshake) 136 iwl_trans_pcie_fw_reset_handshake(trans); 137 138 trans_pcie->is_down = true; 139 140 /* tell the device to stop sending interrupts */ 141 iwl_disable_interrupts(trans); 142 143 /* device going down, Stop using ICT table */ 144 iwl_pcie_disable_ict(trans); 145 146 /* 147 * If a HW restart happens during firmware loading, 148 * then the firmware loading might call this function 149 * and later it might be called again due to the 150 * restart. So don't process again if the device is 151 * already dead. 152 */ 153 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 154 IWL_DEBUG_INFO(trans, 155 "DEVICE_ENABLED bit was set and is now cleared\n"); 156 iwl_txq_gen2_tx_free(trans); 157 iwl_pcie_rx_stop(trans); 158 } 159 160 iwl_pcie_ctxt_info_free_paging(trans); 161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 162 iwl_pcie_ctxt_info_gen3_free(trans, false); 163 else 164 iwl_pcie_ctxt_info_free(trans); 165 166 /* Make sure (redundant) we've released our request to stay awake */ 167 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 168 iwl_clear_bit(trans, CSR_GP_CNTRL, 169 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 170 else 171 iwl_clear_bit(trans, CSR_GP_CNTRL, 172 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 173 174 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 175 iwl_set_bit(trans, CSR_GP_CNTRL, 176 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 177 } 178 /* Stop the device, and put it in low power state */ 179 iwl_pcie_gen2_apm_stop(trans, false); 180 181 iwl_trans_sw_reset(trans); 182 183 /* 184 * Upon stop, the IVAR table gets erased, so msi-x won't 185 * work. This causes a bug in RF-KILL flows, since the interrupt 186 * that enables radio won't fire on the correct irq, and the 187 * driver won't be able to handle the interrupt. 188 * Configure the IVAR table again after reset. 189 */ 190 iwl_pcie_conf_msix_hw(trans_pcie); 191 192 /* 193 * Upon stop, the APM issues an interrupt if HW RF kill is set. 194 * This is a bug in certain verions of the hardware. 195 * Certain devices also keep sending HW RF kill interrupt all 196 * the time, unless the interrupt is ACKed even if the interrupt 197 * should be masked. Re-ACK all the interrupts here. 198 */ 199 iwl_disable_interrupts(trans); 200 201 /* clear all status bits */ 202 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 203 clear_bit(STATUS_INT_ENABLED, &trans->status); 204 clear_bit(STATUS_TPOWER_PMI, &trans->status); 205 206 /* 207 * Even if we stop the HW, we still want the RF kill 208 * interrupt 209 */ 210 iwl_enable_rfkill_int(trans); 211 212 /* re-take ownership to prevent other users from stealing the device */ 213 iwl_pcie_prepare_card_hw(trans); 214 } 215 216 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 217 { 218 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 219 bool was_in_rfkill; 220 221 iwl_op_mode_time_point(trans->op_mode, 222 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 223 NULL); 224 225 mutex_lock(&trans_pcie->mutex); 226 trans_pcie->opmode_down = true; 227 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 228 _iwl_trans_pcie_gen2_stop_device(trans); 229 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 230 mutex_unlock(&trans_pcie->mutex); 231 } 232 233 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 234 { 235 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 236 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 237 trans->cfg->min_txq_size); 238 239 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 240 spin_lock_bh(&trans_pcie->irq_lock); 241 iwl_pcie_gen2_apm_init(trans); 242 spin_unlock_bh(&trans_pcie->irq_lock); 243 244 iwl_op_mode_nic_config(trans->op_mode); 245 246 /* Allocate the RX queue, or reset if it is already allocated */ 247 if (iwl_pcie_gen2_rx_init(trans)) 248 return -ENOMEM; 249 250 /* Allocate or reset and init all Tx and Command queues */ 251 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size)) 252 return -ENOMEM; 253 254 /* enable shadow regs in HW */ 255 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 256 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 257 258 return 0; 259 } 260 261 static void iwl_pcie_get_rf_name(struct iwl_trans *trans) 262 { 263 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 264 char *buf = trans_pcie->rf_name; 265 size_t buflen = sizeof(trans_pcie->rf_name); 266 size_t pos; 267 u32 version; 268 269 if (buf[0]) 270 return; 271 272 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 273 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF): 274 pos = scnprintf(buf, buflen, "JF"); 275 break; 276 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF): 277 pos = scnprintf(buf, buflen, "GF"); 278 break; 279 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4): 280 pos = scnprintf(buf, buflen, "GF4"); 281 break; 282 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 283 pos = scnprintf(buf, buflen, "HR"); 284 break; 285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 286 pos = scnprintf(buf, buflen, "HR1"); 287 break; 288 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 289 pos = scnprintf(buf, buflen, "HRCDB"); 290 break; 291 default: 292 return; 293 } 294 295 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 296 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 297 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 298 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 299 version = iwl_read_prph(trans, CNVI_MBOX_C); 300 switch (version) { 301 case 0x20000: 302 pos += scnprintf(buf + pos, buflen - pos, " B3"); 303 break; 304 case 0x120000: 305 pos += scnprintf(buf + pos, buflen - pos, " B5"); 306 break; 307 default: 308 pos += scnprintf(buf + pos, buflen - pos, 309 " (0x%x)", version); 310 break; 311 } 312 break; 313 default: 314 break; 315 } 316 317 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x", 318 trans->hw_rf_id); 319 320 IWL_INFO(trans, "Detected RF %s\n", buf); 321 322 /* 323 * also add a \n for debugfs - need to do it after printing 324 * since our IWL_INFO machinery wants to see a static \n at 325 * the end of the string 326 */ 327 pos += scnprintf(buf + pos, buflen - pos, "\n"); 328 } 329 330 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 331 { 332 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 333 334 iwl_pcie_reset_ict(trans); 335 336 /* make sure all queue are not stopped/used */ 337 memset(trans->txqs.queue_stopped, 0, 338 sizeof(trans->txqs.queue_stopped)); 339 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 340 341 /* now that we got alive we can free the fw image & the context info. 342 * paging memory cannot be freed included since FW will still use it 343 */ 344 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 345 iwl_pcie_ctxt_info_gen3_free(trans, true); 346 else 347 iwl_pcie_ctxt_info_free(trans); 348 349 /* 350 * Re-enable all the interrupts, including the RF-Kill one, now that 351 * the firmware is alive. 352 */ 353 iwl_enable_interrupts(trans); 354 mutex_lock(&trans_pcie->mutex); 355 iwl_pcie_check_hw_rf_kill(trans); 356 357 iwl_pcie_get_rf_name(trans); 358 mutex_unlock(&trans_pcie->mutex); 359 } 360 361 static void iwl_pcie_set_ltr(struct iwl_trans *trans) 362 { 363 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 364 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 365 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 366 u32_encode_bits(250, 367 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 368 CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 369 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 370 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 371 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 372 373 /* 374 * To workaround hardware latency issues during the boot process, 375 * initialize the LTR to ~250 usec (see ltr_val above). 376 * The firmware initializes this again later (to a smaller value). 377 */ 378 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 379 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 380 !trans->trans_cfg->integrated) { 381 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 382 } else if (trans->trans_cfg->integrated && 383 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 384 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 385 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 386 } 387 } 388 389 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 390 const struct fw_img *fw, bool run_in_rfkill) 391 { 392 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 393 bool hw_rfkill; 394 int ret; 395 396 /* This may fail if AMT took ownership of the device */ 397 if (iwl_pcie_prepare_card_hw(trans)) { 398 IWL_WARN(trans, "Exit HW not ready\n"); 399 ret = -EIO; 400 goto out; 401 } 402 403 iwl_enable_rfkill_int(trans); 404 405 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 406 407 /* 408 * We enabled the RF-Kill interrupt and the handler may very 409 * well be running. Disable the interrupts to make sure no other 410 * interrupt can be fired. 411 */ 412 iwl_disable_interrupts(trans); 413 414 /* Make sure it finished running */ 415 iwl_pcie_synchronize_irqs(trans); 416 417 mutex_lock(&trans_pcie->mutex); 418 419 /* If platform's RF_KILL switch is NOT set to KILL */ 420 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 421 if (hw_rfkill && !run_in_rfkill) { 422 ret = -ERFKILL; 423 goto out; 424 } 425 426 /* Someone called stop_device, don't try to start_fw */ 427 if (trans_pcie->is_down) { 428 IWL_WARN(trans, 429 "Can't start_fw since the HW hasn't been started\n"); 430 ret = -EIO; 431 goto out; 432 } 433 434 /* make sure rfkill handshake bits are cleared */ 435 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 436 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 437 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 438 439 /* clear (again), then enable host interrupts */ 440 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 441 442 ret = iwl_pcie_gen2_nic_init(trans); 443 if (ret) { 444 IWL_ERR(trans, "Unable to init nic\n"); 445 goto out; 446 } 447 448 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 449 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 450 else 451 ret = iwl_pcie_ctxt_info_init(trans, fw); 452 if (ret) 453 goto out; 454 455 iwl_pcie_set_ltr(trans); 456 457 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 458 iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE); 459 iwl_set_bit(trans, CSR_GP_CNTRL, 460 CSR_GP_CNTRL_REG_FLAG_ROM_START); 461 } else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 462 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 463 } else { 464 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); 465 } 466 467 /* re-check RF-Kill state since we may have missed the interrupt */ 468 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 469 if (hw_rfkill && !run_in_rfkill) 470 ret = -ERFKILL; 471 472 out: 473 mutex_unlock(&trans_pcie->mutex); 474 return ret; 475 } 476