1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2021 Intel Corporation 5 */ 6 #include "iwl-trans.h" 7 #include "iwl-prph.h" 8 #include "iwl-context-info.h" 9 #include "iwl-context-info-gen3.h" 10 #include "internal.h" 11 #include "fw/dbg.h" 12 13 #define FW_RESET_TIMEOUT (HZ / 5) 14 15 /* 16 * Start up NIC's basic functionality after it has been reset 17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 18 * NOTE: This does not load uCode nor start the embedded processor 19 */ 20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 21 { 22 int ret = 0; 23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 25 26 /* 27 * Use "set_bit" below rather than "write", to preserve any hardware 28 * bits already set by default after reset. 29 */ 30 31 /* 32 * Disable L0s without affecting L1; 33 * don't wait for ICH L0s (ICH bug W/A) 34 */ 35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 40 41 /* 42 * Enable HAP INTA (interrupt from management bus) to 43 * wake device's PCI Express link L1a -> L0s 44 */ 45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 47 48 iwl_pcie_apm_config(trans); 49 50 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 51 if (ret) 52 return ret; 53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 55 56 return 0; 57 } 58 59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 60 { 61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 62 63 if (op_mode_leave) { 64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 65 iwl_pcie_gen2_apm_init(trans); 66 67 /* inform ME that we are leaving */ 68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 69 CSR_RESET_LINK_PWR_MGMT_DISABLED); 70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 71 CSR_HW_IF_CONFIG_REG_PREPARE | 72 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 73 mdelay(1); 74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 75 CSR_RESET_LINK_PWR_MGMT_DISABLED); 76 mdelay(5); 77 } 78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 80 81 /* Stop device's DMA activity */ 82 iwl_pcie_apm_stop_master(trans); 83 84 iwl_trans_sw_reset(trans); 85 86 /* 87 * Clear "initialization complete" bit to move adapter from 88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 89 */ 90 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 91 iwl_clear_bit(trans, CSR_GP_CNTRL, 92 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 93 else 94 iwl_clear_bit(trans, CSR_GP_CNTRL, 95 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 96 } 97 98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans) 99 { 100 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 101 int ret; 102 103 trans_pcie->fw_reset_state = FW_RESET_REQUESTED; 104 105 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 106 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 107 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); 108 else 109 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 110 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 111 112 /* wait 200ms */ 113 ret = wait_event_timeout(trans_pcie->fw_reset_waitq, 114 trans_pcie->fw_reset_state != FW_RESET_REQUESTED, 115 FW_RESET_TIMEOUT); 116 if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) { 117 IWL_INFO(trans, 118 "firmware didn't ACK the reset - continue anyway\n"); 119 iwl_trans_fw_error(trans, true); 120 } 121 122 trans_pcie->fw_reset_state = FW_RESET_IDLE; 123 } 124 125 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 126 { 127 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 128 129 lockdep_assert_held(&trans_pcie->mutex); 130 131 if (trans_pcie->is_down) 132 return; 133 134 if (trans->state >= IWL_TRANS_FW_STARTED) { 135 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 136 iwl_set_bit(trans, CSR_GP_CNTRL, 137 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 138 iwl_poll_bit(trans, CSR_GP_CNTRL, 139 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 140 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 141 5000); 142 msleep(100); 143 iwl_set_bit(trans, CSR_GP_CNTRL, 144 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 145 } else if (trans_pcie->fw_reset_handshake) { 146 iwl_trans_pcie_fw_reset_handshake(trans); 147 } 148 } 149 150 trans_pcie->is_down = true; 151 152 /* tell the device to stop sending interrupts */ 153 iwl_disable_interrupts(trans); 154 155 /* device going down, Stop using ICT table */ 156 iwl_pcie_disable_ict(trans); 157 158 /* 159 * If a HW restart happens during firmware loading, 160 * then the firmware loading might call this function 161 * and later it might be called again due to the 162 * restart. So don't process again if the device is 163 * already dead. 164 */ 165 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 166 IWL_DEBUG_INFO(trans, 167 "DEVICE_ENABLED bit was set and is now cleared\n"); 168 iwl_txq_gen2_tx_free(trans); 169 iwl_pcie_rx_stop(trans); 170 } 171 172 iwl_pcie_ctxt_info_free_paging(trans); 173 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 174 iwl_pcie_ctxt_info_gen3_free(trans, false); 175 else 176 iwl_pcie_ctxt_info_free(trans); 177 178 /* Make sure (redundant) we've released our request to stay awake */ 179 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 180 iwl_clear_bit(trans, CSR_GP_CNTRL, 181 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 182 else 183 iwl_clear_bit(trans, CSR_GP_CNTRL, 184 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 185 186 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 187 iwl_set_bit(trans, CSR_GP_CNTRL, 188 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 189 } 190 /* Stop the device, and put it in low power state */ 191 iwl_pcie_gen2_apm_stop(trans, false); 192 193 iwl_trans_sw_reset(trans); 194 195 /* 196 * Upon stop, the IVAR table gets erased, so msi-x won't 197 * work. This causes a bug in RF-KILL flows, since the interrupt 198 * that enables radio won't fire on the correct irq, and the 199 * driver won't be able to handle the interrupt. 200 * Configure the IVAR table again after reset. 201 */ 202 iwl_pcie_conf_msix_hw(trans_pcie); 203 204 /* 205 * Upon stop, the APM issues an interrupt if HW RF kill is set. 206 * This is a bug in certain verions of the hardware. 207 * Certain devices also keep sending HW RF kill interrupt all 208 * the time, unless the interrupt is ACKed even if the interrupt 209 * should be masked. Re-ACK all the interrupts here. 210 */ 211 iwl_disable_interrupts(trans); 212 213 /* clear all status bits */ 214 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 215 clear_bit(STATUS_INT_ENABLED, &trans->status); 216 clear_bit(STATUS_TPOWER_PMI, &trans->status); 217 218 /* 219 * Even if we stop the HW, we still want the RF kill 220 * interrupt 221 */ 222 iwl_enable_rfkill_int(trans); 223 224 /* re-take ownership to prevent other users from stealing the device */ 225 iwl_pcie_prepare_card_hw(trans); 226 } 227 228 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 229 { 230 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 231 bool was_in_rfkill; 232 233 iwl_op_mode_time_point(trans->op_mode, 234 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 235 NULL); 236 237 mutex_lock(&trans_pcie->mutex); 238 trans_pcie->opmode_down = true; 239 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 240 _iwl_trans_pcie_gen2_stop_device(trans); 241 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 242 mutex_unlock(&trans_pcie->mutex); 243 } 244 245 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 246 { 247 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 248 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 249 trans->cfg->min_txq_size); 250 251 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 252 spin_lock_bh(&trans_pcie->irq_lock); 253 iwl_pcie_gen2_apm_init(trans); 254 spin_unlock_bh(&trans_pcie->irq_lock); 255 256 iwl_op_mode_nic_config(trans->op_mode); 257 258 /* Allocate the RX queue, or reset if it is already allocated */ 259 if (iwl_pcie_gen2_rx_init(trans)) 260 return -ENOMEM; 261 262 /* Allocate or reset and init all Tx and Command queues */ 263 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size)) 264 return -ENOMEM; 265 266 /* enable shadow regs in HW */ 267 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 268 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 269 270 return 0; 271 } 272 273 static void iwl_pcie_get_rf_name(struct iwl_trans *trans) 274 { 275 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 276 char *buf = trans_pcie->rf_name; 277 size_t buflen = sizeof(trans_pcie->rf_name); 278 size_t pos; 279 u32 version; 280 281 if (buf[0]) 282 return; 283 284 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 285 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF): 286 pos = scnprintf(buf, buflen, "JF"); 287 break; 288 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF): 289 pos = scnprintf(buf, buflen, "GF"); 290 break; 291 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4): 292 pos = scnprintf(buf, buflen, "GF4"); 293 break; 294 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 295 pos = scnprintf(buf, buflen, "HR"); 296 break; 297 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 298 pos = scnprintf(buf, buflen, "HR1"); 299 break; 300 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 301 pos = scnprintf(buf, buflen, "HRCDB"); 302 break; 303 default: 304 return; 305 } 306 307 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) { 308 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR): 309 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1): 310 case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB): 311 version = iwl_read_prph(trans, CNVI_MBOX_C); 312 switch (version) { 313 case 0x20000: 314 pos += scnprintf(buf + pos, buflen - pos, " B3"); 315 break; 316 case 0x120000: 317 pos += scnprintf(buf + pos, buflen - pos, " B5"); 318 break; 319 default: 320 pos += scnprintf(buf + pos, buflen - pos, 321 " (0x%x)", version); 322 break; 323 } 324 break; 325 default: 326 break; 327 } 328 329 pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x", 330 trans->hw_rf_id); 331 332 IWL_INFO(trans, "Detected RF %s\n", buf); 333 334 /* 335 * also add a \n for debugfs - need to do it after printing 336 * since our IWL_INFO machinery wants to see a static \n at 337 * the end of the string 338 */ 339 pos += scnprintf(buf + pos, buflen - pos, "\n"); 340 } 341 342 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 343 { 344 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 345 346 iwl_pcie_reset_ict(trans); 347 348 /* make sure all queue are not stopped/used */ 349 memset(trans->txqs.queue_stopped, 0, 350 sizeof(trans->txqs.queue_stopped)); 351 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 352 353 /* now that we got alive we can free the fw image & the context info. 354 * paging memory cannot be freed included since FW will still use it 355 */ 356 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 357 iwl_pcie_ctxt_info_gen3_free(trans, true); 358 else 359 iwl_pcie_ctxt_info_free(trans); 360 361 /* 362 * Re-enable all the interrupts, including the RF-Kill one, now that 363 * the firmware is alive. 364 */ 365 iwl_enable_interrupts(trans); 366 mutex_lock(&trans_pcie->mutex); 367 iwl_pcie_check_hw_rf_kill(trans); 368 369 iwl_pcie_get_rf_name(trans); 370 mutex_unlock(&trans_pcie->mutex); 371 } 372 373 static void iwl_pcie_set_ltr(struct iwl_trans *trans) 374 { 375 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 376 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 377 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 378 u32_encode_bits(250, 379 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 380 CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 381 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 382 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 383 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 384 385 /* 386 * To workaround hardware latency issues during the boot process, 387 * initialize the LTR to ~250 usec (see ltr_val above). 388 * The firmware initializes this again later (to a smaller value). 389 */ 390 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 391 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 392 !trans->trans_cfg->integrated) { 393 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 394 } else if (trans->trans_cfg->integrated && 395 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 396 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 397 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 398 } 399 } 400 401 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 402 const struct fw_img *fw, bool run_in_rfkill) 403 { 404 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 405 bool hw_rfkill; 406 int ret; 407 408 /* This may fail if AMT took ownership of the device */ 409 if (iwl_pcie_prepare_card_hw(trans)) { 410 IWL_WARN(trans, "Exit HW not ready\n"); 411 ret = -EIO; 412 goto out; 413 } 414 415 iwl_enable_rfkill_int(trans); 416 417 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 418 419 /* 420 * We enabled the RF-Kill interrupt and the handler may very 421 * well be running. Disable the interrupts to make sure no other 422 * interrupt can be fired. 423 */ 424 iwl_disable_interrupts(trans); 425 426 /* Make sure it finished running */ 427 iwl_pcie_synchronize_irqs(trans); 428 429 mutex_lock(&trans_pcie->mutex); 430 431 /* If platform's RF_KILL switch is NOT set to KILL */ 432 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 433 if (hw_rfkill && !run_in_rfkill) { 434 ret = -ERFKILL; 435 goto out; 436 } 437 438 /* Someone called stop_device, don't try to start_fw */ 439 if (trans_pcie->is_down) { 440 IWL_WARN(trans, 441 "Can't start_fw since the HW hasn't been started\n"); 442 ret = -EIO; 443 goto out; 444 } 445 446 /* make sure rfkill handshake bits are cleared */ 447 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 448 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 449 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 450 451 /* clear (again), then enable host interrupts */ 452 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 453 454 ret = iwl_pcie_gen2_nic_init(trans); 455 if (ret) { 456 IWL_ERR(trans, "Unable to init nic\n"); 457 goto out; 458 } 459 460 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 461 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 462 else 463 ret = iwl_pcie_ctxt_info_init(trans, fw); 464 if (ret) 465 goto out; 466 467 iwl_pcie_set_ltr(trans); 468 469 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 470 iwl_set_bit(trans, CSR_GP_CNTRL, 471 CSR_GP_CNTRL_REG_FLAG_ROM_START); 472 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 473 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 474 else 475 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); 476 477 /* re-check RF-Kill state since we may have missed the interrupt */ 478 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 479 if (hw_rfkill && !run_in_rfkill) 480 ret = -ERFKILL; 481 482 out: 483 mutex_unlock(&trans_pcie->mutex); 484 return ret; 485 } 486