1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2017 Intel Deutschland GmbH 4 * Copyright (C) 2018-2020 Intel Corporation 5 */ 6 #include "iwl-trans.h" 7 #include "iwl-prph.h" 8 #include "iwl-context-info.h" 9 #include "iwl-context-info-gen3.h" 10 #include "internal.h" 11 #include "fw/dbg.h" 12 13 #define FW_RESET_TIMEOUT (HZ / 5) 14 15 /* 16 * Start up NIC's basic functionality after it has been reset 17 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 18 * NOTE: This does not load uCode nor start the embedded processor 19 */ 20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans) 21 { 22 int ret = 0; 23 24 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 25 26 /* 27 * Use "set_bit" below rather than "write", to preserve any hardware 28 * bits already set by default after reset. 29 */ 30 31 /* 32 * Disable L0s without affecting L1; 33 * don't wait for ICH L0s (ICH bug W/A) 34 */ 35 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 36 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 37 38 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 39 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 40 41 /* 42 * Enable HAP INTA (interrupt from management bus) to 43 * wake device's PCI Express link L1a -> L0s 44 */ 45 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 46 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 47 48 iwl_pcie_apm_config(trans); 49 50 ret = iwl_finish_nic_init(trans, trans->trans_cfg); 51 if (ret) 52 return ret; 53 54 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 55 56 return 0; 57 } 58 59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 60 { 61 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 62 63 if (op_mode_leave) { 64 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 65 iwl_pcie_gen2_apm_init(trans); 66 67 /* inform ME that we are leaving */ 68 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 69 CSR_RESET_LINK_PWR_MGMT_DISABLED); 70 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 71 CSR_HW_IF_CONFIG_REG_PREPARE | 72 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 73 mdelay(1); 74 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 75 CSR_RESET_LINK_PWR_MGMT_DISABLED); 76 mdelay(5); 77 } 78 79 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 80 81 /* Stop device's DMA activity */ 82 iwl_pcie_apm_stop_master(trans); 83 84 iwl_trans_sw_reset(trans); 85 86 /* 87 * Clear "initialization complete" bit to move adapter from 88 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 89 */ 90 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 91 } 92 93 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans) 94 { 95 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 96 int ret; 97 98 trans_pcie->fw_reset_done = false; 99 100 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 101 iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER, 102 UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE); 103 else 104 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 105 UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE); 106 107 /* wait 200ms */ 108 ret = wait_event_timeout(trans_pcie->fw_reset_waitq, 109 trans_pcie->fw_reset_done, FW_RESET_TIMEOUT); 110 if (!ret) 111 IWL_ERR(trans, 112 "firmware didn't ACK the reset - continue anyway\n"); 113 } 114 115 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 116 { 117 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 118 119 lockdep_assert_held(&trans_pcie->mutex); 120 121 if (trans_pcie->is_down) 122 return; 123 124 if (trans_pcie->fw_reset_handshake && 125 trans->state >= IWL_TRANS_FW_STARTED) 126 iwl_trans_pcie_fw_reset_handshake(trans); 127 128 trans_pcie->is_down = true; 129 130 /* tell the device to stop sending interrupts */ 131 iwl_disable_interrupts(trans); 132 133 /* device going down, Stop using ICT table */ 134 iwl_pcie_disable_ict(trans); 135 136 /* 137 * If a HW restart happens during firmware loading, 138 * then the firmware loading might call this function 139 * and later it might be called again due to the 140 * restart. So don't process again if the device is 141 * already dead. 142 */ 143 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 144 IWL_DEBUG_INFO(trans, 145 "DEVICE_ENABLED bit was set and is now cleared\n"); 146 iwl_txq_gen2_tx_stop(trans); 147 iwl_pcie_rx_stop(trans); 148 } 149 150 iwl_pcie_ctxt_info_free_paging(trans); 151 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 152 iwl_pcie_ctxt_info_gen3_free(trans); 153 else 154 iwl_pcie_ctxt_info_free(trans); 155 156 /* Make sure (redundant) we've released our request to stay awake */ 157 iwl_clear_bit(trans, CSR_GP_CNTRL, 158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 159 160 /* Stop the device, and put it in low power state */ 161 iwl_pcie_gen2_apm_stop(trans, false); 162 163 iwl_trans_sw_reset(trans); 164 165 /* 166 * Upon stop, the IVAR table gets erased, so msi-x won't 167 * work. This causes a bug in RF-KILL flows, since the interrupt 168 * that enables radio won't fire on the correct irq, and the 169 * driver won't be able to handle the interrupt. 170 * Configure the IVAR table again after reset. 171 */ 172 iwl_pcie_conf_msix_hw(trans_pcie); 173 174 /* 175 * Upon stop, the APM issues an interrupt if HW RF kill is set. 176 * This is a bug in certain verions of the hardware. 177 * Certain devices also keep sending HW RF kill interrupt all 178 * the time, unless the interrupt is ACKed even if the interrupt 179 * should be masked. Re-ACK all the interrupts here. 180 */ 181 iwl_disable_interrupts(trans); 182 183 /* clear all status bits */ 184 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 185 clear_bit(STATUS_INT_ENABLED, &trans->status); 186 clear_bit(STATUS_TPOWER_PMI, &trans->status); 187 188 /* 189 * Even if we stop the HW, we still want the RF kill 190 * interrupt 191 */ 192 iwl_enable_rfkill_int(trans); 193 194 /* re-take ownership to prevent other users from stealing the device */ 195 iwl_pcie_prepare_card_hw(trans); 196 } 197 198 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans) 199 { 200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 201 bool was_in_rfkill; 202 203 iwl_op_mode_time_point(trans->op_mode, 204 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 205 NULL); 206 207 mutex_lock(&trans_pcie->mutex); 208 trans_pcie->opmode_down = true; 209 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 210 _iwl_trans_pcie_gen2_stop_device(trans); 211 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 212 mutex_unlock(&trans_pcie->mutex); 213 } 214 215 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans) 216 { 217 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 218 int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE, 219 trans->cfg->min_txq_size); 220 221 /* TODO: most of the logic can be removed in A0 - but not in Z0 */ 222 spin_lock_bh(&trans_pcie->irq_lock); 223 iwl_pcie_gen2_apm_init(trans); 224 spin_unlock_bh(&trans_pcie->irq_lock); 225 226 iwl_op_mode_nic_config(trans->op_mode); 227 228 /* Allocate the RX queue, or reset if it is already allocated */ 229 if (iwl_pcie_gen2_rx_init(trans)) 230 return -ENOMEM; 231 232 /* Allocate or reset and init all Tx and Command queues */ 233 if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size)) 234 return -ENOMEM; 235 236 /* enable shadow regs in HW */ 237 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 238 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 239 240 return 0; 241 } 242 243 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr) 244 { 245 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 246 247 iwl_pcie_reset_ict(trans); 248 249 /* make sure all queue are not stopped/used */ 250 memset(trans->txqs.queue_stopped, 0, 251 sizeof(trans->txqs.queue_stopped)); 252 memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used)); 253 254 /* now that we got alive we can free the fw image & the context info. 255 * paging memory cannot be freed included since FW will still use it 256 */ 257 iwl_pcie_ctxt_info_free(trans); 258 259 /* 260 * Re-enable all the interrupts, including the RF-Kill one, now that 261 * the firmware is alive. 262 */ 263 iwl_enable_interrupts(trans); 264 mutex_lock(&trans_pcie->mutex); 265 iwl_pcie_check_hw_rf_kill(trans); 266 mutex_unlock(&trans_pcie->mutex); 267 } 268 269 static void iwl_pcie_set_ltr(struct iwl_trans *trans) 270 { 271 u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ | 272 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 273 CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) | 274 u32_encode_bits(250, 275 CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) | 276 CSR_LTR_LONG_VAL_AD_SNOOP_REQ | 277 u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC, 278 CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) | 279 u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL); 280 281 /* 282 * To workaround hardware latency issues during the boot process, 283 * initialize the LTR to ~250 usec (see ltr_val above). 284 * The firmware initializes this again later (to a smaller value). 285 */ 286 if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 || 287 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) && 288 !trans->trans_cfg->integrated) { 289 iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val); 290 } else if (trans->trans_cfg->integrated && 291 trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) { 292 iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL); 293 iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val); 294 } 295 } 296 297 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 298 const struct fw_img *fw, bool run_in_rfkill) 299 { 300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 301 bool hw_rfkill; 302 int ret; 303 304 /* This may fail if AMT took ownership of the device */ 305 if (iwl_pcie_prepare_card_hw(trans)) { 306 IWL_WARN(trans, "Exit HW not ready\n"); 307 ret = -EIO; 308 goto out; 309 } 310 311 iwl_enable_rfkill_int(trans); 312 313 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 314 315 /* 316 * We enabled the RF-Kill interrupt and the handler may very 317 * well be running. Disable the interrupts to make sure no other 318 * interrupt can be fired. 319 */ 320 iwl_disable_interrupts(trans); 321 322 /* Make sure it finished running */ 323 iwl_pcie_synchronize_irqs(trans); 324 325 mutex_lock(&trans_pcie->mutex); 326 327 /* If platform's RF_KILL switch is NOT set to KILL */ 328 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 329 if (hw_rfkill && !run_in_rfkill) { 330 ret = -ERFKILL; 331 goto out; 332 } 333 334 /* Someone called stop_device, don't try to start_fw */ 335 if (trans_pcie->is_down) { 336 IWL_WARN(trans, 337 "Can't start_fw since the HW hasn't been started\n"); 338 ret = -EIO; 339 goto out; 340 } 341 342 /* make sure rfkill handshake bits are cleared */ 343 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 344 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 345 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 346 347 /* clear (again), then enable host interrupts */ 348 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 349 350 ret = iwl_pcie_gen2_nic_init(trans); 351 if (ret) { 352 IWL_ERR(trans, "Unable to init nic\n"); 353 goto out; 354 } 355 356 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 357 ret = iwl_pcie_ctxt_info_gen3_init(trans, fw); 358 else 359 ret = iwl_pcie_ctxt_info_init(trans, fw); 360 if (ret) 361 goto out; 362 363 iwl_pcie_set_ltr(trans); 364 365 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 366 iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1); 367 else 368 iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1); 369 370 /* re-check RF-Kill state since we may have missed the interrupt */ 371 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 372 if (hw_rfkill && !run_in_rfkill) 373 ret = -ERFKILL; 374 375 out: 376 mutex_unlock(&trans_pcie->mutex); 377 return ret; 378 } 379