1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3  * Copyright (C) 2017 Intel Deutschland GmbH
4  * Copyright (C) 2018-2023 Intel Corporation
5  */
6 #include "iwl-trans.h"
7 #include "iwl-prph.h"
8 #include "iwl-context-info.h"
9 #include "iwl-context-info-gen3.h"
10 #include "internal.h"
11 #include "fw/dbg.h"
12 
13 #define FW_RESET_TIMEOUT (HZ / 5)
14 
15 /*
16  * Start up NIC's basic functionality after it has been reset
17  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
18  * NOTE:  This does not load uCode nor start the embedded processor
19  */
20 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans)
21 {
22 	int ret = 0;
23 
24 	IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
25 
26 	/*
27 	 * Use "set_bit" below rather than "write", to preserve any hardware
28 	 * bits already set by default after reset.
29 	 */
30 
31 	/*
32 	 * Disable L0s without affecting L1;
33 	 * don't wait for ICH L0s (ICH bug W/A)
34 	 */
35 	iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
36 		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
37 
38 	/* Set FH wait threshold to maximum (HW error during stress W/A) */
39 	iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
40 
41 	/*
42 	 * Enable HAP INTA (interrupt from management bus) to
43 	 * wake device's PCI Express link L1a -> L0s
44 	 */
45 	iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
46 		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
47 
48 	iwl_pcie_apm_config(trans);
49 
50 	ret = iwl_finish_nic_init(trans);
51 	if (ret)
52 		return ret;
53 
54 	set_bit(STATUS_DEVICE_ENABLED, &trans->status);
55 
56 	return 0;
57 }
58 
59 static void iwl_pcie_gen2_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
60 {
61 	IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
62 
63 	if (op_mode_leave) {
64 		if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
65 			iwl_pcie_gen2_apm_init(trans);
66 
67 		/* inform ME that we are leaving */
68 		iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
69 			    CSR_RESET_LINK_PWR_MGMT_DISABLED);
70 		iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
71 			    CSR_HW_IF_CONFIG_REG_PREPARE |
72 			    CSR_HW_IF_CONFIG_REG_ENABLE_PME);
73 		mdelay(1);
74 		iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
75 			      CSR_RESET_LINK_PWR_MGMT_DISABLED);
76 		mdelay(5);
77 	}
78 
79 	clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
80 
81 	/* Stop device's DMA activity */
82 	iwl_pcie_apm_stop_master(trans);
83 
84 	iwl_trans_sw_reset(trans, false);
85 
86 	/*
87 	 * Clear "initialization complete" bit to move adapter from
88 	 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
89 	 */
90 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
91 		iwl_clear_bit(trans, CSR_GP_CNTRL,
92 			      CSR_GP_CNTRL_REG_FLAG_MAC_INIT);
93 	else
94 		iwl_clear_bit(trans, CSR_GP_CNTRL,
95 			      CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
96 }
97 
98 static void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans)
99 {
100 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
101 	int ret;
102 
103 	trans_pcie->fw_reset_state = FW_RESET_REQUESTED;
104 
105 	if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
106 		iwl_write_umac_prph(trans, UREG_NIC_SET_NMI_DRIVER,
107 				    UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE);
108 	else if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210)
109 		iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6,
110 				    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
111 	else
112 		iwl_write32(trans, CSR_DOORBELL_VECTOR,
113 			    UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE);
114 
115 	/* wait 200ms */
116 	ret = wait_event_timeout(trans_pcie->fw_reset_waitq,
117 				 trans_pcie->fw_reset_state != FW_RESET_REQUESTED,
118 				 FW_RESET_TIMEOUT);
119 	if (!ret || trans_pcie->fw_reset_state == FW_RESET_ERROR) {
120 		u32 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
121 
122 		IWL_ERR(trans,
123 			"timeout waiting for FW reset ACK (inta_hw=0x%x)\n",
124 			inta_hw);
125 
126 		if (!(inta_hw & MSIX_HW_INT_CAUSES_REG_RESET_DONE))
127 			iwl_trans_fw_error(trans, true);
128 	}
129 
130 	trans_pcie->fw_reset_state = FW_RESET_IDLE;
131 }
132 
133 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
134 {
135 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
136 
137 	lockdep_assert_held(&trans_pcie->mutex);
138 
139 	if (trans_pcie->is_down)
140 		return;
141 
142 	if (trans->state >= IWL_TRANS_FW_STARTED)
143 		if (trans_pcie->fw_reset_handshake)
144 			iwl_trans_pcie_fw_reset_handshake(trans);
145 
146 	trans_pcie->is_down = true;
147 
148 	/* tell the device to stop sending interrupts */
149 	iwl_disable_interrupts(trans);
150 
151 	/* device going down, Stop using ICT table */
152 	iwl_pcie_disable_ict(trans);
153 
154 	/*
155 	 * If a HW restart happens during firmware loading,
156 	 * then the firmware loading might call this function
157 	 * and later it might be called again due to the
158 	 * restart. So don't process again if the device is
159 	 * already dead.
160 	 */
161 	if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
162 		IWL_DEBUG_INFO(trans,
163 			       "DEVICE_ENABLED bit was set and is now cleared\n");
164 		iwl_pcie_synchronize_irqs(trans);
165 		iwl_pcie_rx_napi_sync(trans);
166 		iwl_txq_gen2_tx_free(trans);
167 		iwl_pcie_rx_stop(trans);
168 	}
169 
170 	iwl_pcie_ctxt_info_free_paging(trans);
171 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
172 		iwl_pcie_ctxt_info_gen3_free(trans, false);
173 	else
174 		iwl_pcie_ctxt_info_free(trans);
175 
176 	/* Stop the device, and put it in low power state */
177 	iwl_pcie_gen2_apm_stop(trans, false);
178 
179 	/* re-take ownership to prevent other users from stealing the device */
180 	iwl_trans_sw_reset(trans, true);
181 
182 	/*
183 	 * Upon stop, the IVAR table gets erased, so msi-x won't
184 	 * work. This causes a bug in RF-KILL flows, since the interrupt
185 	 * that enables radio won't fire on the correct irq, and the
186 	 * driver won't be able to handle the interrupt.
187 	 * Configure the IVAR table again after reset.
188 	 */
189 	iwl_pcie_conf_msix_hw(trans_pcie);
190 
191 	/*
192 	 * Upon stop, the APM issues an interrupt if HW RF kill is set.
193 	 * This is a bug in certain verions of the hardware.
194 	 * Certain devices also keep sending HW RF kill interrupt all
195 	 * the time, unless the interrupt is ACKed even if the interrupt
196 	 * should be masked. Re-ACK all the interrupts here.
197 	 */
198 	iwl_disable_interrupts(trans);
199 
200 	/* clear all status bits */
201 	clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
202 	clear_bit(STATUS_INT_ENABLED, &trans->status);
203 	clear_bit(STATUS_TPOWER_PMI, &trans->status);
204 
205 	/*
206 	 * Even if we stop the HW, we still want the RF kill
207 	 * interrupt
208 	 */
209 	iwl_enable_rfkill_int(trans);
210 }
211 
212 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans)
213 {
214 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
215 	bool was_in_rfkill;
216 
217 	iwl_op_mode_time_point(trans->op_mode,
218 			       IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE,
219 			       NULL);
220 
221 	mutex_lock(&trans_pcie->mutex);
222 	trans_pcie->opmode_down = true;
223 	was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
224 	_iwl_trans_pcie_gen2_stop_device(trans);
225 	iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
226 	mutex_unlock(&trans_pcie->mutex);
227 }
228 
229 static int iwl_pcie_gen2_nic_init(struct iwl_trans *trans)
230 {
231 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
232 	int queue_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
233 			       trans->cfg->min_txq_size);
234 
235 	/* TODO: most of the logic can be removed in A0 - but not in Z0 */
236 	spin_lock_bh(&trans_pcie->irq_lock);
237 	iwl_pcie_gen2_apm_init(trans);
238 	spin_unlock_bh(&trans_pcie->irq_lock);
239 
240 	iwl_op_mode_nic_config(trans->op_mode);
241 
242 	/* Allocate the RX queue, or reset if it is already allocated */
243 	if (iwl_pcie_gen2_rx_init(trans))
244 		return -ENOMEM;
245 
246 	/* Allocate or reset and init all Tx and Command queues */
247 	if (iwl_txq_gen2_init(trans, trans->txqs.cmd.q_id, queue_size))
248 		return -ENOMEM;
249 
250 	/* enable shadow regs in HW */
251 	iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
252 	IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
253 
254 	return 0;
255 }
256 
257 static void iwl_pcie_get_rf_name(struct iwl_trans *trans)
258 {
259 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
260 	char *buf = trans_pcie->rf_name;
261 	size_t buflen = sizeof(trans_pcie->rf_name);
262 	size_t pos;
263 	u32 version;
264 
265 	if (buf[0])
266 		return;
267 
268 	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
269 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_JF):
270 		pos = scnprintf(buf, buflen, "JF");
271 		break;
272 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF):
273 		pos = scnprintf(buf, buflen, "GF");
274 		break;
275 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_GF4):
276 		pos = scnprintf(buf, buflen, "GF4");
277 		break;
278 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
279 		pos = scnprintf(buf, buflen, "HR");
280 		break;
281 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
282 		pos = scnprintf(buf, buflen, "HR1");
283 		break;
284 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
285 		pos = scnprintf(buf, buflen, "HRCDB");
286 		break;
287 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_MS):
288 		pos = scnprintf(buf, buflen, "MS");
289 		break;
290 	default:
291 		return;
292 	}
293 
294 	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
295 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR):
296 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HR1):
297 	case CSR_HW_RFID_TYPE(CSR_HW_RF_ID_TYPE_HRCDB):
298 		version = iwl_read_prph(trans, CNVI_MBOX_C);
299 		switch (version) {
300 		case 0x20000:
301 			pos += scnprintf(buf + pos, buflen - pos, " B3");
302 			break;
303 		case 0x120000:
304 			pos += scnprintf(buf + pos, buflen - pos, " B5");
305 			break;
306 		default:
307 			pos += scnprintf(buf + pos, buflen - pos,
308 					 " (0x%x)", version);
309 			break;
310 		}
311 		break;
312 	default:
313 		break;
314 	}
315 
316 	pos += scnprintf(buf + pos, buflen - pos, ", rfid=0x%x",
317 			 trans->hw_rf_id);
318 
319 	IWL_INFO(trans, "Detected RF %s\n", buf);
320 
321 	/*
322 	 * also add a \n for debugfs - need to do it after printing
323 	 * since our IWL_INFO machinery wants to see a static \n at
324 	 * the end of the string
325 	 */
326 	pos += scnprintf(buf + pos, buflen - pos, "\n");
327 }
328 
329 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr)
330 {
331 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
332 
333 	iwl_pcie_reset_ict(trans);
334 
335 	/* make sure all queue are not stopped/used */
336 	memset(trans->txqs.queue_stopped, 0,
337 	       sizeof(trans->txqs.queue_stopped));
338 	memset(trans->txqs.queue_used, 0, sizeof(trans->txqs.queue_used));
339 
340 	/* now that we got alive we can free the fw image & the context info.
341 	 * paging memory cannot be freed included since FW will still use it
342 	 */
343 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
344 		iwl_pcie_ctxt_info_gen3_free(trans, true);
345 	else
346 		iwl_pcie_ctxt_info_free(trans);
347 
348 	/*
349 	 * Re-enable all the interrupts, including the RF-Kill one, now that
350 	 * the firmware is alive.
351 	 */
352 	iwl_enable_interrupts(trans);
353 	mutex_lock(&trans_pcie->mutex);
354 	iwl_pcie_check_hw_rf_kill(trans);
355 
356 	iwl_pcie_get_rf_name(trans);
357 	mutex_unlock(&trans_pcie->mutex);
358 }
359 
360 static bool iwl_pcie_set_ltr(struct iwl_trans *trans)
361 {
362 	u32 ltr_val = CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ |
363 		      u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
364 				      CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE) |
365 		      u32_encode_bits(250,
366 				      CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL) |
367 		      CSR_LTR_LONG_VAL_AD_SNOOP_REQ |
368 		      u32_encode_bits(CSR_LTR_LONG_VAL_AD_SCALE_USEC,
369 				      CSR_LTR_LONG_VAL_AD_SNOOP_SCALE) |
370 		      u32_encode_bits(250, CSR_LTR_LONG_VAL_AD_SNOOP_VAL);
371 
372 	/*
373 	 * To workaround hardware latency issues during the boot process,
374 	 * initialize the LTR to ~250 usec (see ltr_val above).
375 	 * The firmware initializes this again later (to a smaller value).
376 	 */
377 	if ((trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210 ||
378 	     trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) &&
379 	    !trans->trans_cfg->integrated) {
380 		iwl_write32(trans, CSR_LTR_LONG_VAL_AD, ltr_val);
381 		return true;
382 	}
383 
384 	if (trans->trans_cfg->integrated &&
385 	    trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000) {
386 		iwl_write_prph(trans, HPM_MAC_LTR_CSR, HPM_MAC_LRT_ENABLE_ALL);
387 		iwl_write_prph(trans, HPM_UMAC_LTR, ltr_val);
388 		return true;
389 	}
390 
391 	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) {
392 		/* First clear the interrupt, just in case */
393 		iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD,
394 			    MSIX_HW_INT_CAUSES_REG_IML);
395 		/* In this case, unfortunately the same ROM bug exists in the
396 		 * device (not setting LTR correctly), but we don't have control
397 		 * over the settings from the host due to some hardware security
398 		 * features. The only workaround we've been able to come up with
399 		 * so far is to try to keep the CPU and device busy by polling
400 		 * it and the IML (image loader) completed interrupt.
401 		 */
402 		return false;
403 	}
404 
405 	/* nothing needs to be done on other devices */
406 	return true;
407 }
408 
409 static void iwl_pcie_spin_for_iml(struct iwl_trans *trans)
410 {
411 /* in practice, this seems to complete in around 20-30ms at most, wait 100 */
412 #define IML_WAIT_TIMEOUT	(HZ / 10)
413 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
414 	unsigned long end_time = jiffies + IML_WAIT_TIMEOUT;
415 	u32 value, loops = 0;
416 	bool irq = false;
417 
418 	if (WARN_ON(!trans_pcie->iml))
419 		return;
420 
421 	value = iwl_read32(trans, CSR_LTR_LAST_MSG);
422 	IWL_DEBUG_INFO(trans, "Polling for IML load - CSR_LTR_LAST_MSG=0x%x\n",
423 		       value);
424 
425 	while (time_before(jiffies, end_time)) {
426 		if (iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD) &
427 				MSIX_HW_INT_CAUSES_REG_IML) {
428 			irq = true;
429 			break;
430 		}
431 		/* Keep the CPU and device busy. */
432 		value = iwl_read32(trans, CSR_LTR_LAST_MSG);
433 		loops++;
434 	}
435 
436 	IWL_DEBUG_INFO(trans,
437 		       "Polled for IML load: irq=%d, loops=%d, CSR_LTR_LAST_MSG=0x%x\n",
438 		       irq, loops, value);
439 
440 	/* We don't fail here even if we timed out - maybe we get lucky and the
441 	 * interrupt comes in later (and we get alive from firmware) and then
442 	 * we're all happy - but if not we'll fail on alive timeout or get some
443 	 * other error out.
444 	 */
445 }
446 
447 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
448 				 const struct fw_img *fw, bool run_in_rfkill)
449 {
450 	struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
451 	bool hw_rfkill, keep_ram_busy;
452 	int ret;
453 
454 	/* This may fail if AMT took ownership of the device */
455 	if (iwl_pcie_prepare_card_hw(trans)) {
456 		IWL_WARN(trans, "Exit HW not ready\n");
457 		return -EIO;
458 	}
459 
460 	iwl_enable_rfkill_int(trans);
461 
462 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
463 
464 	/*
465 	 * We enabled the RF-Kill interrupt and the handler may very
466 	 * well be running. Disable the interrupts to make sure no other
467 	 * interrupt can be fired.
468 	 */
469 	iwl_disable_interrupts(trans);
470 
471 	/* Make sure it finished running */
472 	iwl_pcie_synchronize_irqs(trans);
473 
474 	mutex_lock(&trans_pcie->mutex);
475 
476 	/* If platform's RF_KILL switch is NOT set to KILL */
477 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
478 	if (hw_rfkill && !run_in_rfkill) {
479 		ret = -ERFKILL;
480 		goto out;
481 	}
482 
483 	/* Someone called stop_device, don't try to start_fw */
484 	if (trans_pcie->is_down) {
485 		IWL_WARN(trans,
486 			 "Can't start_fw since the HW hasn't been started\n");
487 		ret = -EIO;
488 		goto out;
489 	}
490 
491 	/* make sure rfkill handshake bits are cleared */
492 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
493 	iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
494 		    CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
495 
496 	/* clear (again), then enable host interrupts */
497 	iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
498 
499 	ret = iwl_pcie_gen2_nic_init(trans);
500 	if (ret) {
501 		IWL_ERR(trans, "Unable to init nic\n");
502 		goto out;
503 	}
504 
505 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
506 		ret = iwl_pcie_ctxt_info_gen3_init(trans, fw);
507 	else
508 		ret = iwl_pcie_ctxt_info_init(trans, fw);
509 	if (ret)
510 		goto out;
511 
512 	keep_ram_busy = !iwl_pcie_set_ltr(trans);
513 
514 	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
515 		iwl_write32(trans, CSR_FUNC_SCRATCH, CSR_FUNC_SCRATCH_INIT_VALUE);
516 		iwl_set_bit(trans, CSR_GP_CNTRL,
517 			    CSR_GP_CNTRL_REG_FLAG_ROM_START);
518 	} else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
519 		iwl_write_umac_prph(trans, UREG_CPU_INIT_RUN, 1);
520 	} else {
521 		iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
522 	}
523 
524 	if (keep_ram_busy)
525 		iwl_pcie_spin_for_iml(trans);
526 
527 	/* re-check RF-Kill state since we may have missed the interrupt */
528 	hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
529 	if (hw_rfkill && !run_in_rfkill)
530 		ret = -ERFKILL;
531 
532 out:
533 	mutex_unlock(&trans_pcie->mutex);
534 	return ret;
535 }
536